SP8855E [MITEL]

2.8GHz Parallel Load Professional Synthesiser; 2.8GHz的并行加载专业合成器


型号：	SP8855E
厂家：	MITEL NETWORKS CORPORATION
描述：	2.8GHz Parallel Load Professional Synthesiser 2.8GHz的并行加载专业合成器
文件：	总14页 (文件大小：172K)
中文：	中文翻译
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SP8855E

2.8GHz Parallel Load Professional Synthesiser

Advance Information

Supersedes version in January 1996 Professional Products IC Hanbook, HB2480-3.0

DS4239 - 3.0 March 1999

The SP8855E is one of a family of parallel load

synthesisers containing all the elements apart from the loop

amplifier to fabricate a PLL synthesis loop. Other devices in

the series are the SP8852E which is a fully programmable

device requiring two 16 bit words to set the RF and reference

counters, and the SP8854E which has hard wired reference

counter programming and requires a single bit word to pro-

gram the RF divider. The SP8855E replaces the existing

SP8855D.

PIN 1

The SP8855E is intended for applications where a fixed

synthesiser frequency is required although it can also be used

where frequency selection is set by switches. In general the

device will be programmed by connecting the programming

pins to either V_CCor ground. Additional hard wired inputs can

be used to control the F_pdand F_refoutputs set the control

direction of the loop and select the phase detector gain.

Another input may be used to disable the phase detector

output.

HC44

The device is available in both plastic (HP) and ceramic

(HC) J-leaded 44-lead chip carrier. Ambient temperature

ranges available are shown in the ordering information.

OPTIONAL

PIN 1

REFERENCE

FEATURES

■ 2.8GHz Operating Frequency (IG GRADE)

■ Single 5V Supply Operation

HP44

■ High Comparison Frequency 50MHz

■ High Gain Phase Detector 1mA/rad

■ Programmable Phase Detector Gain

■ Zero "Dead Band" Phase Detector

■ Wide range of RF and Reference Divide Ratios

■ Programming by Hard Wired Inputs

■ Low cost plastic package option

■ GPS HI-REL level a screened option

Description

Pin Description

Control Direction

Input bus bit 10

Input bus bit 9

Input bus bit 8

Input bus bit 7

Input bus bit 6

Input bus bit 5

Input bus bit 4

Input bus bit 3

Input bus bit 2

Input bus bit 1

Input bus bit 0

0V (prescaler)

RF input

V_CC+ 5V (prescaler)

V_EE0V

Lock detect output

C-lock detect

Rset

Charge pump output

Charge pump ref.

F_ref/F_pdenable

F_pd*

F_ref*

+5V

Ref. osc capacitor

Ref in/XTAL

Reference bit 9

Reference bit 8

Reference bit 7

Reference bit 6

Reference bit 5

Reference bit 4

Reference bit 3

Reference bit 2

Reference bit 1

Reference bit 0

Phase Detect Enable

Phase Detect Gain 1

ABSOLUTE MAXIMUM RATINGS

Supply voltage

-0.3V to 6V

-65 °C to +150°C

-55°C to +100°C

2.5V p-p

Storage temperature

Operating temperature

Prescaler & reference Input Voltage

Data Inputs

Phase Detect Gain

Input bus bit 13

Input bus bit 12

Input bus bit 11

V_CC+0.3V

V_EE-0.3V

Junction temperature

+ 175°C (HC package)

+ 150°C (HP package)

*Fpd and Fref outputs are reversed using the Control Direction

input. The table above is correct when pin 23 is high.

Fig.1 Pin connections - top view

SP8855E

D E T E C T O R

P H A S E

F.2SP85Eblockdigram

SP8855E

PIN DESCRIPTION

DESCRIPTION

1,2,3,4,5,6,7,8,9,10,11,42,43,44

13, 14 (RF INPUT)

These pins are the data inputs used to set the RF divider ratio

(M.N+A). Open circuit = 1 (high) on these pins. Inputs are transparent into

the data buffers.

Balanced inputs to the RF pre-amplifier. For single ended operation the

signal is AC coupled into pin 13 with pin 14 AC decoupled to ground (or

vice -versa). Pins 13 and 14 are internally DC biased.

17 (LOCK DETECT INPUT)

18 (C-LOCK DETECT)

A current sink into this pin is enabled when the lock detect circuit indicates

lock. Used to give an external indication of phase lock.

A capacitor connected to this point determines the lock detect integrator time

constant and can be used to vary the sensitivity of the phase lock indicator.

19 (Rset)

An external resistor from Pin 19 to V_CCsets the charge pump output current

20 (CP OUTPUT)

The phase detector output is a single ended charge pump sourcing or

sinking current to the inverting input of an external loop filter.

21 (CP REF)

Connected to the non-inverting input of the loop filter to set the optimum DC

bias.

22 (F_ref/F_pdENABLE

23 (CONTROL DIRECTION)

Part of the data input bus. When this pin is logic HI the F_refand F_pdoutputs

are enabled. Open circuit = HI

This pin controls charge pump output direction. For Pin 23 HI the output

sinks current when F_pd> F_refor when the RF phase leads Ref phase. For Pin

23 LO the relationship is reversed. (see table 2).

Changing the state of pin 23 reverses the pins on which Fref and Fpd output

occur. See pin 24 and Pin 25 below for details. Open circuit = HI.

24 = F_pdif Pin 23 is HI

= F_refif Pin 23 is LO

RF divider output pulses. Fpd = RF input frequency /(M.N+A). Pulse width =

8 RF input cycles (1 cycle of the divide by 8 prescaler output).

25 = F_refif Pin 223 is HI

27 (Reference Oscillator Capacitor)

28 (Ref IN/XTAL)

Reference divider output pulses. Fref = Reference input frequency/R. Pulse

width = high period of Ref input.

Leave open circuit if an external reference is used. See fig. 5 for typical

connection for use as an onboard crystal oscillator.

This pin is the input buffer amplifier for an external reference signal. This

amplifier provides the active element if an onboard crystal oscillator is used.

29,30,31,32,33,34,35,36,37,38

39 (Phase Detector ENABLE)

40, 41 (PD Gain)

These pins set the Reference divider ratio R. Open circuit = HI.

When this pin is HI the phase detector output is enable. Open circuit = HI.

These pins set the charge pump current multiplication factor (see table 1). Open

circuit = HI.

SP8855E

ELECTRICAL CHARACTERISTICS

Guaranteed over the full temperature and supply voltage range (unless otherwise stated)

Temperature T_ambfor KG parts -55°C and +100°C,

Temperature T_ambfor IG parts -40°C and +85°, Temperature T_casefor

MA part -55°C and +125°C Supply Voltage = 4.75V and 5.25V

Characteristics

Value

Typ

Units

Conditions

Min

Max

Supply current15, 26

180

240

RF input sensitivity

13, 14

13,14,24

28, 25

28,24,25

-5.0

+7.0

16383

1023

dBm

100MHz to 2.8/2.7GHz See Fig. 3

RF division ratio

Reference division ratio

Comparison frequency

Reference input frequency

MHz

100

Reference division ratio ≥ 2 at frequencies

>50MHz also see Note 1.

Reference input voltage

F_ref/F_pdoutput voltage high

F_red/F_pdoutput voltage low

Lock detect output voltage

24, 25

630

1200

- 0.8

- 1.4

300

2000

mV p-p

Vwrt V_CC

Sine Wave 10-100MHz

2.2K to 0V

500

I_OUT= 3mA

Charge pump current at

multiplication factor = 1

19,20,21

±1.4

±2.0

±3.4

±5.4

3.5

±1.5

±1.7

V_{pin 20}= V_{pin 21,}

I_{pin 19}= 1.6mA

Charge pump current at

multiplication factor = 1.5

19,20,21

±2.3

±3.8

±6.1

±2.5

±4.6

±6.5

V_{pin 20}= V_{pin 21,}

I_{pin 19}= 1.6mA

Charge pump current at

multiplication factor = 2.5

V_{pin 20}= V_{pin 21,}

I_{pin 19}= 1.6mA

Charge pump current at

multiplication factor = 4.0

V_{pin 20}= V_{pin 21,}

I_{pin 19}= 1.6mA

Input bus high logic level

Input bus low logic level

Input bus current source

Input bys current sink

1-11, 22

23, 29-44

1-11, 22

23,29-44

1-11,22

23,29-44

-200

µA

V_IN= 0V

V_IN= V_CC

1-11, 22

23,29-44

±5

Up down current matching

V_{pin 20}= V_{pin 21,}

I_{pin 19}= 1.6mA

Charge pump reference

voltage

V_CC-0.5

I_{pin 19}=1.6mA current

multiplication factor = 1

Charge pump reference

voltage

V_CC-1.6

I_{pin 19}=1.6mA current

multiplication factor = 4

R_setcurrent

0.5

1.6

See Note 2

R_setVoltage 19

I_{pin 19}= 1.6mA

Notes: 1. Lower reference frequencies may be used if slew rates are maintained.

2. Pin 19 current x multiplication factor must be less than 5mA if charge pump accuracy is to be maintained.

SP8855E

TYPICAL OVERLOAD

+20

+10

OPERATING

AREA FOR

'IG' PARTS

ONLY

GUARANTEED

OPERTAING

WINDOW

-5

-10

-20

-30

TYPICAL SENSITIVITY

2.7GHz

2GHz

2.8GHz

10GHz

1GHz

100MHz

INPUT DRIVE REQUIREMENTS

Fig. 3 SP8855E

+j1

+j0.5

+j2

Zo = 50Ω

+j0.2

0.2

0.5

50MHz

1.1GHz

2.5GHz

-j0.2

-j0.5

-j2

-j1

Fig. 4 R.F. input impedance

SP8855E

+5V

VCC

VALUES DEPEND

ON APPLICATION

REFERENCE COUNTER

PROGRAMMING

RF COUNTER

PROGRAMMING

VCC

VCO

APPLICATION USING

CRYSTAL REFERENCE

LOOP

FILTER

SP8855

2k2

+30V

100n

Fpd Fref

33p

OP27

ETC

10MHz

CRYSTAL

100p

10n

*100n

1µ

10n

Ref in

Fig. 5 Typical application diagram

DESCRIPTION

Prescaler and AM counter

Phase Comparator and Charge pump

The programmable divider chain is of AM counter

construction and therefore contains a dual modulus front end

prescaler, an A counter which controls the dual modulus ratio

and an M counter which performs the bulk multi-modulus

division. A programmable divider of this construction has a

division ratio of MN+A and a minimum integer steppable

division ratio of N(N-1), where N is the prescaler ratio.

The SP8855E has a digital phase/frequency comparator

driving a charge pump with programmable current output.

The charge pump current level at the minimum gain setting

is approximately equal to the current fed into the R_se_tinput

pin 19 and can be increased by programming pins 40 and

41 according to Table 1 by up to 4 times.

Programming

Pin 40

Pin 41

Current Multiplication

Factor

The device is programmed by connecting the

programming pins to either V_CCor ground. The programming

inputswillgohighifleftopencircuitbutforbestnoiseimmunity

a wired connection to V_CCis preferable. The programming

inputscanbedrivenfromTTLorCMOSlogiclevelsifrequired.

1.0

1.5

2.5

4.0

Reference input

The reference source can be either driven from an external

sine or square wave source of up to 100MHz or a crystal can

be connected as shown in Fig. 5.

Table 1

SP8855E

V_CC- 1.6V

R_set

The charge pump connections to the loop amplifier consist

of the charge pump output and the charge pump reference.

The matching of the charge pump up and down currents will

only be maintained if the charge pumps output is held at a

voltage equal to the charge pump reference using an

operational amplifier to produce a virtual earth condition at pin

20.

The lock detect circuit can drive an LED to give visual

indication of phase lock or provide an indication to the control

system if a pull-up resistor is used in place of the LED. A small

capacitor connected from the C-lock detector pin to ground

may be used to delay lock detect indication and remove

glitches produced by momentary phase coincidence during

lock up. The phase detector can be disabled by pulling pin 39

to logic low.

Pin 19 current .

Phase detector gain =

I_{pin 19}(mA) X multiplication factor

mA/radian

2π

To allow for control direction changes introduced by the

design of the PLL, pin 23 can be programmed to reverse the

control direction of the loop by transposing the F_pdand F_ref

connections.Inorderthatanyexternalphasedetectorwillalso

be reversed by this function, the F_pdand F_refoutputs are also

interchanged as shown in Table 2.

Output for RF Phase Lag

Control direction pin 23

pin 20

29 30 31 32 33 34 35 36 37 38 PIN

Current Source

Current Sink

TEN BIT REFERENCE COUNTER

Table 2

REFERENCE DIVIDER PROGRAMMING PIN ALLOCATION

The Fpd and Fref signals to the phase detector are available

on pin 24 and 25 and may be used to monitor the frequency

input to the phase detector or used in conjunction with an

external phase detector. When the Fpd/Fref outputs are to be

used at high frequencies, an external pull down resistor of

minimum value 330Ω may be used connected to ground to

reduce the fall time of the output pulse.

40 41 42 43 44

10 11 PIN

13 12 11 10

M COUNTER

3 BIT A

COUNTER

PHASE

DETECTOR

GAIN

CONTROL

see Table 1

REFERENCE DIVIDER PROGRAMMING PIN ALLOCATION

Fig. 6 Programming data format

SP8855E

Vcc

325

40k

INPUT

500

INPUT

50µA

3mA

Fig. 7a RF and reference divider programming bits, F_pd/F_ref

enable, control direction and phase detector gain control

inputs

Fig. 7b RF inputs

C-LOCK DETECT (HIGH WHEN LOCKED)

Vcc

2k5

Vcc

LOW

WHEN

LOCKED

50k

V_REF

4.7V

LOCK

DETECT

OUTPUT

400µA

100

100µA

20µA

Fig. 7c Lock detect decouple

Fig. 7d Lock detect output

CHARGE PUMP

OUTPUT

REFERENCE

R_set

Vcc

20 21

450

Vcc

CHARGE PUMP

CURRENT SOURCES

Vcc

DOWN

2mA

130

Fig. 7e R_setpin

Fig. 7f Charge pump circuit

Fig. 7 Interface circuit diagrams

SP8855E

Vcc

40k

Vcc

40k

296

24, 25

F_pd,F_ref,

OUTPUTS

60k

3.3mA

50µA

100µA

Fig. 7h Reference oscillator

Fig. 7g F_pd, and F_refoutputs

APPLICATIONS

RF inputs

RF Layout

The prescaler has a differential input amplifier to improve

inputsensitivity.Generallytheinput drivewillbesingle ended

and the RF signal should be AC coupled to either of the inputs

using a chip capacitor. The remaining input should be

decoupled to ground , again using a chip capacitor. The inputs

can be driven differentially but the input circuit should not

provide DC path between inputs or to ground.

The SP8855E can operate with input frequencies up to

2.8GHz but to obtain optimum performance, good RF layout

practices should be used. A suitable layout technique is to use

double sided printed circuit board with through plated holes.

Wherever possible the top surface on which the SP8855E is

mountedshouldbeleftasacontinuoussheetofcoppertoform

a low impedance earth plane. The ground pins 12 and 16

should be connected directly to the earth plane. Pins such as

V_ccand the unused RF input should be decoupled with chip

capacitorsmountedasclosetothedevice pinaspossiblewith

a direct connection to the earth plane, suitable values are

10nF for the power supplies and <1nF for the RF input pin. (a

lower value should be used sufficient to give good decoupling

at the RF frequency of operation). A larger decoupling

capacitor mounted as close as possible to pin 26 should be

used to prevent modulation of V_CCby the charge pump pulses.

The R_setresistor should also be mounted close to the R_setpin

topreventnoisepick-up,andthecapacitorconnectedfromthe

charge pump output should be a chip component with short

connections to the SP8855E.

When the reference is derived from a crystal connected to

pins27and28asshowninFig.5theoscillatorcomponentsare

best mounted close to the SP8855E.

All signals such as the programming inputs, RF in

reference in and the connections to the op-amp are best taken

through the pc board adjacent to the SP8855E with through

plated holes allowing connections to remote points without

fragmenting the earth plane.

Lock detect circuit

The lock detect circuit uses the up and down correction

pulses from the phase detector to determine whether the loop

is in or out of lock. When the loop is locked, both up and down

pulses are very narrow compared to the reference frequency,

but the pulse width in the out of lock condition continuously

varies, depending on the phase difference between the

outputs of the reference and RF counters. The logical AND of

the up and down pulses is used to switch a 20µA current sink

to pin 18 and a 50k resistor provides a load to V_CC. The circuit

is shown in Fig.7c. When lock is established, the narrow

pulses from the phase detector ensure that the current source

isoffforthemajorityofthetimeandsopin18willbepulledhigh

by the 50k resistor. A voltage comparator with a switching

threshold at abount 4.7V monitors the voltage at pin 18 and

switches pin 17 low when pin 18 is more positive than the 4.7V

threshold. When the loop is unlocked, the frequency

difference at the counter outputs will produce a cyclic change

in pulse width from the phase detector outputs with a

frequencyequaltothedifferenceinfrequencyatthereference

andRFcounteroutputs. Asmallcapacitorconnectedtopin18

prevents the indication of a false phase lock conditions at pin

17 for momentaary phase coincidence. Because of the

variable width pulse nature of the signal at pin 18 the

calculation of a suitable capacitor value is complex, but if an

indication with a delay amounting to several times the

expected lock up time is acceptable, the delay will be

approximately equal to the time constant of the capacitor on

pin 18 and the internal 50k resistor.

Programming inputs

The input pins are designed to be compatible with TTL or

CMOS logic with a switching threshold set at about 2.4V by

three forward biased base emitter diodes. The inputs will be

taken high by an internal pull up resistor if left open circuit but

for best noise immunity it is better to connect unused inputs

directly to V_CCor ground.

SP8855E

When selecting a suitable amplifier for the loop filter, a

number of parameters are important; input offset voltage in

most designs is only a few millivolts and an offset of 5mV will

produce a mismatch in the up and down currents of about 4%

with the charge pump multiplication factor set at 1. The

mismatch in up down currents caused by input offset voltage

willbereducedinproportiontothechargepump multiplication

factor in use. If the linearity of the phase detector about the

normal phase locked operating point is critical, the input offset

voltage of most amplifiers can be adjusted to near zero by

means of a potentiometer.

Thechargepumpreferencevoltageonpin21isabout1.3V

belowthepositivesupplyandwillchangewiththetemperature

and with the programmed charge pump multiplication factor.

In many cases it is convenient to operate the amplifier with the

negative power supply pin connected to 0V as this removes

the need for an additional power supply. The amplifier

selected must have a common mode range to within 3.4V

(minimum charge pump reference voltage) of the negative

supplypintooperatecorrectlywithoutanegativesupply. Most

popular amplifiers can be operated from a 30V positive supply

to give a wide VCO voltage drive range and have adequate

common mode range to operate with inputs at +3.4V with

respect to the negative supply. Input bias and offset current

levels to most operational amplifiers are unlikely to be high

enough to significantly affect the accuracy of the charge pump

circuit currents but the bias current can be important in

reducing reference side bands and local oscillator drift during

frequencychanges.Whentheloopislocked,thechargepump

produces only very narrow pulses of sufficient width to make

up for any charge lost from the loop filter components during

the reference cycle. The charge lost will be due to leakage

from the charge pump output pin and to the amplifier input

bias current the latter usually being more significant. The

resultofthelostchargeisasawtoothrippleontheVCOcontrol

line which frequency modulates the phase locked oscillator at

the reference frequency and its harmonics.

If a faster indication is required, comparable with the loop

lock up time, the capacitor will need to be 2-3 times smaller

than the time constant calculation suggests. The time to

respond to an out of lock conditions is 2-3 times less than that

required to indicate lock.

Charge pump circuit

Thechargepumpcircuitconvertsthevariablewidthupand

down pulses from the phase detector into adjustable current

pulses which can be directly connected to the loop amplifier.

Themagnitudeofthecurrentandthereforethephasedetector

gain can be modified when new frequency data is entered to

compensate for change in the VCO gain characteristics over

its frequency band. The charge pump pulse current is

determined by the current fed into pin 19 and is approximately

equal to pin 19 current when the programmed multiplication

ratio is one. The circuit diagram Fig. 7e shows the internal

components on pin 19 which mirror the input current into the

chargepump. Thevoltageatpin19willbeapproximately1.6V

above ground due to two V_bedrops in the current mirror. This

voltagewillexhibitanegativetemperaturecoefficient,causing

the charge pump current to change with chip temperature by

upto10%overthefullmilitarytemperaturerangeifthecurrent

programming resistor is connected to V_CCas shown in the

application diagram Fig. 5. In critical applications where this

change in charge pump current would be too large the resistor

topin19couldbeincreasedinvalueandconnectedtoahigher

supply to reduce the effect of V_bevariation on the current level.

A suitable resistor connected to a 30V supply would reduce

the variation in pin 19 current due to temperature to less than

1.5%. Alternatively a stable current source could be used to

set pin 19 current.

The charge pump output on pin 20 will only produce

symmetricalupanddowncurrentsifthevoltageisequaltothat

on the voltage reference pin 21. In order to ensure that this

voltage relationship is maintained, an operational amplifier

must be used as shown in the typical application Fig. 5. Using

this configuration pin 20 voltage will be forced to be equal to

that pin 21 since the operational amplifier differential input

voltage will be no more than a few millivolts (the input offset

voltageoftheamplifier).Whenthesynthesiserisfirstswitched

onorwhenafrequencyoutsideVCOrangeisprogrammedthe

amplifier output will limit, allowing pin 20 voltage to differ from

that on pin 21. As soon as an achievable frequency value is

programmedandtheamplifieroutputstartstoslewthecorrect

voltage relationship between pin 20 and 21 will be restored.

Because of the importance of voltage equality between the

charge pump reference and output pins, a resistor should

never be connected in series with the operational amplifier

inverting input and pin 20 as is the case with a phase detector

giving voltage outputs. Any current drawn from the charge

pump reference pin should be limited to the few micro amps

input current of a typical operational amplifier. A resistor

between the charge pump reference and the non inverting

input could be added to provide isolation but the value should

not be so high that more than a few millivolts drop are

produced by the amplifier input current.

It is possible to disable the charge pump by taking pin 39

low. In this case any leakage current will cause the oscillator

to drift off frequency. This feature may be useful where having

achieved lock an external phase detector of the user's choice

can be employed to suit a specific application.

F_pdand F_refoutputs

These outputs provide access to the outputs from the RF

and reference dividers and are provided for monitoring

purposes during product development or test, and for

connection of an external phase detector if required. The

output circuit is of ECL type, the circuit diagram being shown

in Fig. 7g. The outputs are enabled when pin 22 is high and

disabled when pin22 is low, but are best left in the disabled

state when not required as the fast edge speeds on the output

can increase the level of reference sidebands on the

synthesised oscillator.

The emitter follower outputs have no internal pull down

resistor to save current and if the outputs are required an

external pull down resistor should be fitted. The value should

be kept as high as possible to reduce supply current, about

2.2k. being suitable for monitoring with a high impedance

oscilloscope probe or for driving an AC coupled 50 Ohm load.

SP8855E

Loop Filter Design

Aminimumvalueforthepulldownresistoris330Ohms.When

the F_pdand F_refoutputs are disabled the output level will be at

the logic low level of about 3.5V so that the additional supply

current due to the load resistors will be present even when the

outputs are disabled.

Generally the third order filter configuration shown in Fig.8

gives better results than the more commonly used second

order because the reference sidebands are reduced. Three

equations are required to determine values for the three

constants where;

τ₁= C₁

Reference input

τ₂= R₂(C₁+ C₂)

τ₃= C₂R₂

Thereferenceinputcircuitfunctionsasaninputamplifieror

crystal oscillator. When an external reference signal is used

this is simply AC coupled to pin 28, the base of the input

emitter follower. When a low phase noise synthesiser is

requiredthereferencesignaliscriticalsinceanynoisepresent

here will be multiplied by the loop. To obtain the lowest

possible phase noise from the SP8855E it is best to use the

highest possible reference input frequency and to divide this

down internally to obtain the required frequency at the phase

detector. The amplitude of the reference input is also

important, and a level close to the maximum will give the

lowest noise. When the use of a low reference input frequency

say 4-10MHz is essential some advantage may be gained by

using a limiting amplifier such as a CMOS gate to square up

the reference input.

The equations are

1/2

K_φK₀

1 + ω_n²τ₂

τ₁=

1 + ω_n²τ₃

Nω_n

τ₂=

τ₃=

ω_n²τ₃

cos

- tan φ_ο+

ω_n

Where;

K_φ

In cases where a suitable reference signal is not available,

it may be more convenient to use the input buffer as a crystal

oscillator in this case the emitter follower input transistor is

connected as a Colpitts oscillator with the crystal connected

from the base to ground and with the feedback necessary for

oscillation provided by a capacitor tap at the emitter. The

is the phase detector gain factor in mA/radian

is theVCO gain factor in radian/second/Volt

is the total division ratio from VCO to reference

frequency

K₀

arrangement

shown

inset

Fig.

ω_n

φ_ο

is the natural loop bandwidth

is the phase margin normally set to 45°

Since the phase detector is linear over a range of 2π radian,

K_φcan be calculated from

K_φ= Phase comparator current setting/2π mA/radian

FROM

CHARGE

PUMP

These values can now be substituted in equation 1 to obtain

a value for C₁and equation 2 and 3 used to determine values

for C₂and R₂

OUTPUT

VCO

FROM

CHARGE

PUMP

EXAMPLE

Calculate values for a loop with the following parameters

REFERENCE

Frequency to be synthesised:

Reference frequency

Division ratio

ω_nnatural loop frequency

K₀VCO gain factor

φ₀phase margin

1000MHz

10MHz

1000MHz/10MHz = 100

100KHz

2π x 10MHz/Volt

45°

Fig. 8 third order loop filter circuit diagram

Phase comparator current

6.3mA

The phase detector gain factor K_φ

= 6.3mA /2π = 1mA/radian

SP8855E

From equation 3:

Where A is:

1 + ω_n²τ₂

1 + (2π x 100kHz) x (3.844 x 10 ^-6

)

- tan 45° +

0.4142

628319

cos 45°

τ₃

1 + ω_n²τ₃

1 + (2π x 100kHz) x (659 x 10 ^-9

)

100kHz x 2π

τ₃= 659 x 10^-9

1/2

62832

6.833

1.1714

τ₁

39.48 x 10¹²

From equation 2:

τ₂

τ₁= 1.59 x 10 ^-9x 2.415

τ₁= 3.84 x 10 ^-9

(100kHz x 2π)²x 659 x 10^-9

τ₂= 3.844 x 10^-6

Now τ₁= C1 C1 = 3.84nF

τ₂= R₂(C₁+ C₂)

Using these values in equation 1:

1 x 10 ^-3x 2π x 10MHz/V

100 x (2π x 100kHz)²

[A]^1/2

τ₁

τ₃= C₂R₂

Substituting for C₂

τ₃

τ₂= R₂C₁+

R₂

τ₂= R₂C₁+ τ₃

3.844 x 10 ^-6- 659 x 10 ^-9

9.61 x 10 ^-9

τ₂- τ₃

R₂=

C₁

R₂= 829.4Ω

τ₃= C₂R₂

659 x 10 ^-9

829.4

τ₃

C₂=

R₂

C₂= 0.794nF

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