SP8855E/IG/HCAR [ROCHESTER]
PLL FREQUENCY SYNTHESIZER, 2800 MHz, CQCC44, LDCC-44;型号: | SP8855E/IG/HCAR |
厂家: | Rochester Electronics |
描述: | PLL FREQUENCY SYNTHESIZER, 2800 MHz, CQCC44, LDCC-44 |
文件: | 总15页 (文件大小:1133K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SP8855E
2.8GHz Parallel Load Professional Synthesiser
Advance Information
DS4239
ISSUE 3.0
PIN 1
March 1999
The SP8855E is one of a family of parallel load
synthesisers containing all the elements apart from the loop
amplifier to fabricate a PLL synthesis loop. Other devices in
the series are the SP8852E which is a fully programmable
device requiring two 16 bit words to set the RF and reference
counters, and the SP8854E which has hard wired reference
counter programming and requires a single bit word to pro-
gram the RF divider. The SP8855E replaces the existing
SP8855D.
The SP8855E is intended for applications where a fixed
synthesiserfrequencyisrequiredalthoughitcanalsobeused
where frequency selection is set by switches. In general the
device will be programmed by connecting the programming
pins to either VCC or ground. Additional hard wired inputs can
HC44
be used to control the Fpd and Fref outputs set the control
direction of the loop and select the phase detector gain.
Another input may be used to disable the phase detector
output.
The device is available in both plastic (HP) and ceramic
(HC) J-leaded 44-lead chip carrier. Ambient temperature
ranges available are shown in the ordering information.
OPTIONAL
PIN 1
REFERENCE
Features
•
•
•
•
•
•
•
•
•
•
2.8GHz Operating Frequency (IG GRADE)
Single 5V Supply Operation
HP44
High Comparison Frequency 50MHz
High Gain Phase Detector 1mA/rad
Programmable Phase Detector Gain
Zero "Dead Band" Phase Detector
Wide range of RF and Reference Divide Ratios
Programming by Hard Wired Inputs
Low cost plastic package option
Pin
1
2
3
4
5
6
7
8
Description
Pin Description
Control Direction
Input bus bit 10
Input bus bit 9
Input bus bit 8
Input bus bit 7
Input bus bit 6
Input bus bit 5
Input bus bit 4
Input bus bit 3
Input bus bit 2
Input bus bit 1
Input bus bit 0
0V (prescaler)
RF input
RF input
VCC + 5V (prescaler)
VEE 0V
Lock detect output
C-lock detect
Rset
Charge pump output
Charge pump ref.
Fref/Fpd enable
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Fpd*
Fref*
+5V
Ref. osc capacitor
Ref in/XTAL
Reference bit 9
Reference bit 8
Reference bit 7
Reference bit 6
Reference bit 5
Reference bit 4
Reference bit 3
Reference bit 2
Reference bit 1
Reference bit 0
Phase Detect Enable
Phase Detect Gain 1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GPS HI-REL level a screened option
Absolute Maximum Ratings
Supply voltage
Storage temperature
Operating temperature
Prescaler & reference Input Voltage
-0.3V to 6V
-65 °C to +150°C
-55°C to +100°C
2.5V p-p
Data Inputs
VCC +0.3V
Phase Detect Gain
Input bus bit 13
Input bus bit 12
Input bus bit 11
0
VEE -0.3V
Junction temperature
+ 175°C (HC package)
+ 150°C (HP package)
*Fpd and Fref outputs are reversed using the Control Direction
input. The table above is correct when pin 23 is high.
Figure 1 - Pin connections - top view
SP8855E Advance Information
D E T E C T O R
P H A S E
2
Advance Information SP8855E
PIN Description
PIN
Description
1,2,3,4,5,6,7,8,9,10,11,42,43,44
13, 14 (RF INPUT)
These pins are the data inputs used to set the RF divider ratio
(M.N+A). Open circuit = 1 (high) on these pins. Inputs are transparent into
the data buffers.
Balanced inputs to the RF pre-amplifier. For single ended operation the
signal is AC coupled into pin 13 with pin 14 AC decoupled to ground (or
vice -versa). Pins 13 and 14 are internally DC biased.
17 (LOCK DETECT INPUT)
18 (C-LOCK DETECT)
A current sink into this pin is enabled when the lock detect circuit indicates
lock. Used to give an external indication of phase lock.
A capacitor connected to this point determines the lock detect integrator time
constant and can be used to vary the sensitivity of the phase lock indicator.
19 (Rset)
An external resistor from Pin 19 to VCC sets the charge pump output current
20 (CP OUTPUT)
The phase detector output is a single ended charge pump sourcing or
sinking current to the inverting input of an external loop filter.
21 (CP REF)
Connected to the non-inverting input of the loop filter to set the optimum DC
bias.
22 (Fref/Fpd ENABLE
23 (CONTROL DIRECTION)
Part of the data input bus. When this pin is logic HI the Fref and Fpd outputs
are enabled. Open circuit = HI
This pin controls charge pump output direction. For Pin 23 HI the output
sinks current when Fpd > Fref or when the RF phase leads Ref phase. For Pin
23 LO the relationship is reversed. (see table 2).
Changing the state of pin 23 reverses the pins on which Fref and Fpd output
occur. See pin 24 and Pin 25 below for details. Open circuit = HI.
24 = Fpd if Pin 23 is HI
= Fref if Pin 23 is LO
RF divider output pulses. Fpd = RF input frequency /(M.N+A). Pulse width =
8 RF input cycles (1 cycle of the divide by 8 prescaler output).
25 = Fref if Pin 223 is HI
27 (Reference Oscillator Capacitor)
28 (Ref IN/XTAL)
Reference divider output pulses. Fref = Reference input frequency/R. Pulse
width = high period of Ref input.
Leave open circuit if an external reference is used. See fig. 5 for typical
connection for use as an onboard crystal oscillator.
This pin is the input buffer amplifier for an external reference signal. This
amplifier provides the active element if an onboard crystal oscillator is used.
29,30,31,32,33,34,35,36,37,38
39 (Phase Detector ENABLE)
40, 41 (PD Gain)
These pins set the Reference divider ratio R. Open circuit = HI.
When this pin is HI the phase detector output is enable. Open circuit = HI.
These pins set the charge pump current multiplication factor (see table 1).
Open circuit = HI.
3
SP8855E Advance Information
Electrical Characteristics
Guaranteed over the full temperature and supply voltage range (unless otherwise stated)
Temperature Tamb for KG parts -55°C and +100°C,
Temperature Tamb for IG parts -40°C and +85°, Temperature Tcase for
MA part -55°C and +125°C Supply Voltage = 4.75V and 5.25V
Characteristics
Pin
Value
Typ
Units
Conditions
Min
Max
Supply current15, 26
180
240
mA
RF input sensitivity
13, 14
13,14,24
28, 25
28,24,25
28
-5.0
56
1
+7.0
16383
1023
50
dBm
100MHz to 2.8/2.7GHz See Fig. 3
RF division ratio
Reference division ratio
Comparison frequency
Reference input frequency
MHz
MHz
10
100
Reference division ratio ≥ 2 at frequencies
>50MHz also see Note 1.
Reference input voltage
Fref/Fpd output voltage high
Fred/Fpd output voltage low
Lock detect output voltage
28
24, 25
24, 25
17
630
1200
- 0.8
- 1.4
300
2000
mV p-p
Vwrt VCC
Vwrt VCC
mV
Sine Wave 10-100MHz
2.2K to 0V
2.2K to 0V
500
1.7
IOUT = 3mA
Charge pump current at
multiplication factor = 1
19,20,21
1.4
2.0
3.4
5.4
3.5
1.5
mA
Vpin 20 = Vpin
21,
Ipin 19 = 1.6mA
Charge pump current at
multiplication factor = 1.5
19,20,21
19,20,21
19,20,21
2.3
3.8
6.1
2.5
4.6
6.5
mA
mA
mA
V
Vpin 20 = Vpin
21,
Ipin 19 = 1.6mA
Charge pump current at
multiplication factor = 2.5
Vpin 20 = Vpin
21,
Ipin 19 = 1.6mA
Charge pump current at
multiplication factor = 4.0
Vpin 20 = Vpin
21,
Ipin 19 = 1.6mA
Input bus high logic level
Input bus low logic level
Input bus current source
Input bys current sink
1-11, 22
23, 29-44
1-11, 22
23,29-44
1
V
1-11,22
23,29-44
-200
µA
µA
%
VIN = 0V
VIN = VCC
1-11, 22
23,29-44
10
5
Up down current matching
20
21
21
Vpin 20 = Vpin
21,
Ipin 19 = 1.6mA
Charge pump reference
voltage
VCC-0.5
V
Ipin 19 =1.6mA current
multiplication factor = 1
Charge pump reference
voltage
VCC-1.6
V
Ipin 19 =1.6mA current
multiplication factor = 4
Rset current
19
0.5
1.6
2
mA
See Note 2
Rset Voltage 19
V
Ipin 19 = 1.6mA
Notes: 1. Lower reference frequencies may be used if slew rates are maintained.
2. Pin 19 current x multiplication factor must be less than 5mA if charge pump accuracy is to be maintained.
4
Advance Information SP8855E
TYPICAL OVERLOAD
+20
+10
+7
OPERATING
AREA FOR
'IG' PARTS
ONLY
GUARANTEED
OPERTAING
WINDOW
-5
-10
-20
-30
TYPICAL SENSITIVITY
2.7GHz
2GHz
2.8GHz
10GHz
1GHz
100MHz
INPUT DRIVE REQUIREMENTS
Figure 3 - SP8855E
+j1
+j0.5
+j2
Zo = 50Ω
+j0.2
0
0.2
0.5
1
50MHz
1.1GHz
-j0.2
2.5GHz
-j0.5
-j2
-j1
Figure 4 - R.F. input impedance
5
SP8855E Advance Information
+5V
VCC
*
VALUES DEPEND
ON APPLICATION
REFERENCE COUNTER
PROGRAMMING
RF COUNTER
PROGRAMMING
1k
VCC
7
39
38
37
8
9
10
36
35
34
33
11
12
1n
13
VCO
14
32
31
15
APPLICATION USING
CRYSTAL REFERENCE
30
16
17
LOOP
29
FILTER
SP8855
*
28
27
*
*
2k2
+30V
100n
Fpd Fref
-
33p
+
OP27
ETC
10MHz
CRYSTAL
100p
1n
10n
*100n
1µ
1n
10n
Ref in
Figure 5 - Typical application diagram
Description
Prescaler and AM counter
Phase Comparator and Charge pump
The programmable divider chain is of AM counter
construction and therefore contains a dual modulus front end
prescaler, an A counter which controls the dual modulus ratio
and an M counter which performs the bulk multi-modulus
division. A programmable divider of this construction has a
division ratio of MN+A and a minimum integer steppable
division ratio of N(N-1), where N is the prescaler ratio.
The SP8855E has a digital phase/frequency comparator
driving a charge pump with programmable current output.
The charge pump current level at the minimum gain setting
is approximately equal to the current fed into the Rset input
pin 19 and can be increased by programming pins 40 and
41 according to Table 1 by up to 4 times.
Programming
The device is programmed by connecting the
programming pins to either VCC or ground. The programming
inputswillgohighifleftopencircuitbutforbestnoiseimmunity
a wired connection to VCC is preferable. The programming
inputscanbedrivenfromTTLorCMOSlogiclevelsifrequired.
Pin 40
Pin 41
Current Multiplication
Factor
0
0
1
1
0
1
0
1
1.0
1.5
2.5
4.0
Reference input
The reference source can be either driven from an external
sine or square wave source of up to 100MHz or a crystal can
be connected as shown in Fig. 5.
Table 1
6
Advance Information SP8855E
VCC - 1.6V
Rset
The charge pump connections to the loop amplifier consist
of the charge pump output and the charge pump reference.
The matching of the charge pump up and down currents will
only be maintained if the charge pumps output is held at a
voltage equal to the charge pump reference using an
operational amplifier to produce a virtual earth condition at pin
20.
The lock detect circuit can drive an LED to give visual
indication of phase lock or provide an indication to the control
system if a pull-up resistor is used in place of the LED. A small
capacitor connected from the C-lock detector pin to ground
may be used to delay lock detect indication and remove
glitches produced by momentary phase coincidence during
lock up. The phase detector can be disabled by pulling pin 39
to logic low.
Pin 19 current .
Phase detector gain =
Ipin 19 (mA) X multiplication factor
mA/radian
2π
To allow for control direction changes introduced by the
design of the PLL, pin 23 can be programmed to reverse the
control direction of the loop by transposing the Fpd and Fref
connections.Inorderthatanyexternalphasedetectorwillalso
be reversed by this function, the Fpd and Fref outputs are also
interchanged as shown in Table 2.
Output for RF Phase Lag
Control direction pin 23
pin 20
1
0
Current Source
Current Sink
29 30 31 32 33 34 35 36 37 38 PIN
9
8
7
6
5
4
3
2
1
0
2
2
2
2
2
2
2
2
2
2
TEN BIT REFERENCE COUNTER
Table 2
REFERENCE DIVIDER PROGRAMMING PIN ALLOCATION
The Fpd and Fref signals to the phase detector are available
on pin 24 and 25 and may be used to monitor the frequency
input to the phase detector or used in conjunction with an
external phase detector. When the Fpd/Fref outputs are to be
used at high frequencies, an external pull down resistor of
minimum value 330Ω may be used connected to ground to
reduce the fall time of the output pulse.
40 41 42 43 44
1
2
9
3
4
7
5
6
5
7
8
9
10 11 PIN
13 12 11 10
8
6
4
3
2
1
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
M COUNTER
3 BIT A
COUNTER
PHASE
DETECTOR
GAIN
CONTROL
see Table 1
REFERENCE DIVIDER PROGRAMMING PIN ALLOCATION
RF
Figure 6 - Programming data format
7
SP8855E Advance Information
Vcc
Vcc
325
325
4k
5k
40k
5k
40k
RF
INPUT
13
500
500
INPUT
RF
INPUT
50µA
14
3mA
0V
3k
0V
Figure 7a - RF and reference divider programming bits,
Figure 7b - RF inputs
F
pd/Fref enable, control direction and phase detector gain
control inputs
C-LOCK DETECT (HIGH WHEN LOCKED)
Vcc
18
2k5
2k5
Vcc
3k
3k
LOW
WHEN
LOCKED
3k
50k
17
3k
VREF
4.7V
LOCK
DETECT
OUTPUT
400µA
1k
11
100
100
100µA
20µA
0V
0V
Figure 7c - Lock detect decouple
Figure 7d - Lock detect output
CHARGE PUMP
OUTPUT
REFERENCE
Rset
19
Vcc
20 21
450
450
Vcc
CHARGE PUMP
CURRENT SOURCES
83
83
UP
Vcc
DOWN
2mA
130
Figure 7e - Rset pin
Figure 7f - Charge pump circuit
Figure 7 - Interface circuit diagrams
8
Advance Information SP8855E
Vcc
Vcc
296
296
3k
40k
3k
40k
296
24, 25
Fpd, Fref,
OUTPUTS
28
27
60k
60k
3.3mA
50µA
50µA
0V
0V
100µA
100µA
100µA
Figure 7g - Fpd, and Fref outputs
Figure 7h - Reference oscillator
Applications
RF inputs
RF Layout
The prescaler has a differential input amplifier to improve
inputsensitivity.Generallytheinput drivewillbesingle ended
and the RF signal should be AC coupled to either of the inputs
using a chip capacitor. The remaining input should be
decoupledtoground, againusingachipcapacitor. Theinputs
can be driven differentially but the input circuit should not
provide DC path between inputs or to ground.
The SP8855E can operate with input frequencies up to
2.8GHz but to obtain optimum performance, good RF layout
practices shouldbeused. Asuitable layout technique istouse
double sided printed circuit board with through plated holes.
Wherever possible the top surface on which the SP8855E is
mountedshouldbeleftasacontinuoussheetofcoppertoform
a low impedance earth plane. The ground pins 12 and 16
should be connected directly to the earth plane. Pins such as
Vcc and the unused RF input should be decoupled with chip
Lock detect circuit
The lock detect circuit uses the up and down correction
pulses from the phase detector to determine whether the loop
is in or out of lock. When the loop is locked, both up and down
pulses are very narrow compared to the reference frequency,
but the pulse width in the out of lock condition continuously
varies, depending on the phase difference between the
outputs of the reference and RF counters. The logical AND of
the up and down pulses is used to switch a 20µA current sink
to pin 18 and a 50k resistor provides a load to VCC. The circuit
is shown in Fig.7c. When lock is established, the narrow
pulses from the phase detector ensure that the current source
isoffforthemajorityofthetimeandsopin18willbepulledhigh
by the 50k resistor. A voltage comparator with a switching
threshold at abount 4.7V monitors the voltage at pin 18 and
switches pin 17 low when pin 18 is more positive than the 4.7V
threshold. When the loop is unlocked, the frequency
difference at the counter outputs will produce a cyclic change
in pulse width from the phase detector outputs with a
frequencyequaltothedifferenceinfrequencyatthereference
andRFcounteroutputs. Asmallcapacitorconnectedtopin18
prevents the indication of a false phase lock conditions at pin
17 for momentaary phase coincidence. Because of the
variable width pulse nature of the signal at pin 18 the
calculation of a suitable capacitor value is complex, but if an
indication with a delay amounting to several times the
expected lock up time is acceptable, the delay will be
approximately equal to the time constant of the capacitor on
pin 18 and the internal 50k resistor.
capacitorsmountedasclosetothedevice pinaspossiblewith
a direct connection to the earth plane, suitable values are
10nF for the power supplies and <1nF for the RF input pin. (a
lower value should be used sufficient to give good decoupling
at the RF frequency of operation). A larger decoupling
capacitor mounted as close as possible to pin 26 should be
used to prevent modulation of VCC by the charge pump pulses.
The Rset resistor should also be mounted close to the Rset pin
topreventnoisepick-up,andthecapacitorconnectedfromthe
charge pump output should be a chip component with short
connections to the SP8855E.
When the reference is derived from a crystal connected to
pins27and28asshowninFig.5theoscillatorcomponentsare
best mounted close to the SP8855E.
All signals such as the programming inputs, RF in
reference in and theconnectionsto theop-amp arebesttaken
through the pc board adjacent to the SP8855E with through
plated holes allowing connections to remote points without
fragmenting the earth plane.
Programming inputs
The input pins are designed to be compatible with TTL or
CMOS logic with a switching threshold set at about 2.4V by
three forward biased base emitter diodes. The inputs will be
taken high by an internal pull up resistor if left open circuit but
for best noise immunity it is better to connect unused inputs
directly to VCC or ground.
9
SP8855E Advance Information
If a faster indication is required, comparable with the loop
When selecting a suitable amplifier for the loop filter, a
lock up time, the capacitor will need to be 2-3 times smaller
than the time constant calculation suggests. The time to
respond to an out of lock conditions is 2-3 times less than that
required to indicate lock.
number of parameters are important; input offset voltage in
most designs is only a few millivolts and an offset of 5mV will
produce a mismatch in the up and down currents of about 4%
with the charge pump multiplication factor set at 1. The
mismatch in up down currents caused by input offset voltage
willbereducedinproportiontothechargepump multiplication
factor in use. If the linearity of the phase detector about the
normal phase locked operating point is critical, the input offset
voltage of most amplifiers can be adjusted to near zero by
means of a potentiometer.
Charge pump circuit
Thechargepumpcircuitconvertsthevariablewidthupand
down pulses from the phase detector into adjustable current
pulses which can be directly connected to the loop amplifier.
Themagnitudeofthecurrentandthereforethephasedetector
gain can be modified when new frequency data is entered to
compensate for change in the VCO gain characteristics over
its frequency band. The charge pump pulse current is
determined by the current fed into pin 19 and is approximately
equal to pin 19 current when the programmed multiplication
ratio is one. The circuit diagram Fig. 7e shows the internal
components on pin 19 which mirror the input current into the
chargepump. Thevoltageatpin19willbeapproximately1.6V
above ground due to two Vbe drops in the current mirror. This
Thechargepumpreferencevoltageonpin21isabout1.3V
belowthepositivesupplyandwillchangewiththetemperature
and with the programmed charge pump multiplication factor.
In many cases it is convenient to operate the amplifier with the
negative power supply pin connected to 0V as this removes
the need for an additional power supply. The amplifier
selected must have a common mode range to within 3.4V
(minimum charge pump reference voltage) of the negative
supplypintooperatecorrectlywithoutanegativesupply. Most
popular amplifiers can be operated from a 30V positive supply
to give a wide VCO voltage drive range and have adequate
common mode range to operate with inputs at +3.4V with
respect to the negative supply. Input bias and offset current
levels to most operational amplifiers are unlikely to be high
enough to significantly affect the accuracy of the charge pump
circuit currents but the bias current can be important in
reducing reference side bands and local oscillator drift during
frequencychanges.Whentheloopislocked,thechargepump
produces only very narrow pulses of sufficient width to make
up for any charge lost from the loop filter components during
the reference cycle. The charge lost will be due to leakage
from the charge pump output pin and to the amplifier input
bias current the latter usually being more significant. The
resultofthelostchargeisasawtoothrippleontheVCOcontrol
line which frequency modulates the phase locked oscillator at
the reference frequency and its harmonics.
voltagewillexhibitanegativetemperaturecoefficient,causing
the charge pump current to change with chip temperature by
upto10%overthefullmilitarytemperaturerangeifthecurrent
programming resistor is connected to VCC as shown in the
application diagram Fig. 5. In critical applications where this
change in charge pump current would be too large the resistor
topin19couldbeincreasedinvalueandconnectedtoahigher
supply to reduce the effect of Vbe variation on the current level.
A suitable resistor connected to a 30V supply would reduce
the variation in pin 19 current due to temperature to less than
1.5%. Alternatively a stable current source could be used to
set pin 19 current.
The charge pump output on pin 20 will only produce
symmetricalupanddowncurrentsifthevoltageisequaltothat
on the voltage reference pin 21. In order to ensure that this
voltage relationship is maintained, an operational amplifier
must be used as shown in the typical application Fig. 5. Using
this configuration pin 20 voltage will be forced to be equal to
that pin 21 since the operational amplifier differential input
voltage will be no more than a few millivolts (the input offset
voltageoftheamplifier).Whenthesynthesiserisfirstswitched
onorwhenafrequencyoutsideVCOrangeisprogrammedthe
amplifier output will limit, allowing pin 20 voltage to differ from
that on pin 21. As soon as an achievable frequency value is
programmedandtheamplifieroutputstartstoslewthecorrect
voltage relationship between pin 20 and 21 will be restored.
Because of the importance of voltage equality between the
charge pump reference and output pins, a resistor should
never be connected in series with the operational amplifier
inverting input and pin 20 as is the case with a phase detector
giving voltage outputs. Any current drawn from the charge
pump reference pin should be limited to the few micro amps
input current of a typical operational amplifier. A resistor
between the charge pump reference and the non inverting
input could be added to provide isolation but the value should
not be so high that more than a few millivolts drop are
produced by the amplifier input current.
It is possible to disable the charge pump by taking pin 39
low. In this case any leakage current will cause the oscillator
to drift off frequency. This feature may be useful where having
achieved lock an external phase detector of the user's choice
can be employed to suit a specific application.
Fpd and Fref outputs
These outputs provide access to the outputs from the RF
and reference dividers and are provided for monitoring
purposes during product development or test, and for
connection of an external phase detector if required. The
output circuit is of ECL type, the circuit diagram being shown
in Fig. 7g. The outputs are enabled when pin 22 is high and
disabled when pin22 is low, but are best left in the disabled
state when not required as the fast edge speeds on the output
can increase the level of reference sidebands on the
synthesised oscillator.
The emitter follower outputs have no internal pull down
resistor to save current and if the outputs are required an
external pull down resistor should be fitted. The value should
be kept as high as possible to reduce supply current, about
2.2k. being suitable for monitoring with a high impedance
oscilloscope probe or for driving an AC coupled 50 Ohm load.
10
Advance Information SP8855E
Aminimumvalueforthepulldownresistoris330Ohms.When
Loop Filter Design
the Fpd and Fref outputs are disabled the output level will be at
the logic low level of about 3.5V so that the additional supply
current due to the load resistors will be present even when the
outputs are disabled.
Generally the third order filter configuration shown in Fig.8
gives better results than the more commonly used second
order because the reference sidebands are reduced. Three
equations are required to determine values for the three
constants where;
Reference input
Thereferenceinputcircuitfunctionsasaninputamplifieror
crystal oscillator. When an external reference signal is used
this is simply AC coupled to pin 28, the base of the input
emitter follower. When a low phase noise synthesiser is
requiredthereferencesignaliscriticalsinceanynoisepresent
here will be multiplied by the loop. To obtain the lowest
possible phase noise from the SP8855E it is best to use the
highest possible reference input frequency and to divide this
down internally to obtain the required frequency at the phase
detector. The amplitude of the reference input is also
important, and a level close to the maximum will give the
lowest noise. When the use of a low reference input frequency
say 4-10MHz is essential some advantage may be gained by
using a limiting amplifier such as a CMOS gate to square up
the reference input.
τ = C1
τ1 = R2 (C1 + C2)
τ23 = C2 R2
The equations are
1/2
2
2
Kφ K0
1 + ωn τ2
1
2
τ1 =
τ2 =
2
2
2
1 + ωn τ3
Nωn
1
2
ωn τ3
1
cos
- tan φο +
φ
ο
3
τ3 =
ωn
In cases where a suitable reference signal is not available,
it may be more convenient to use the input buffer as a crystal
oscillator in this case the emitter follower input transistor is
connected as a Colpitts oscillator with the crystal connected
from the base to ground and with the feedback necessary for
oscillation provided by a capacitor tap at the emitter. The
Where;
Kφ
is the phase detector gain factor in mA/radian
is theVCO gain factor in radian/second/Volt
is the total division ratio from VCO to reference
frequency
K0
N
arrangement
is
shown
inset
in
Fig.
5.
ωn
φο
is the natural loop bandwidth
C
C
R
1
is the phase margin normally set to 45°
2
2
Since the phase detector is linear over a range of 2π radian,
Kφ can be calculated from
FROM
CHARGE
PUMP
Kφ = Phase comparator current setting/2π mA/radian
-
OUTPUT
TO
VCO
These values can now be substituted in equation 1 to obtain
a value for C1 and equation 2 and 3 used to determine values
for C2 and R2
+
FROM
CHARGE
PUMP
REFERENCE
EXAMPLE
Calculate values for a loop with the following parameters
Figure 8 - third order loop filter circuit diagram
Frequency to be synthesised:
Reference frequency
Division ratio
ωn natural loop frequency
K VCO gain factor
φ00 phase margin
1000MHz
10MHz
1000MHz/10MHz = 100
100KHz
2π x 10MHz/Volt
45°
Phase comparator current
6.3mA
The phase detector gain factor Kφ
= 6.3mA /2π = 1mA/radian
11
SP8855E Advance Information
From equation 3:
Where A is:
1
2
2
2
1 + ωn τ22 1 + (2π x 100kHz) x (3.844 x 10 -6
)
- tan 45° +
0.4142
628319
cos 45°
=
=
τ3
=
2
2
1 + ωn τ32 1 + (2π x 100kHz) x (659 x 10 -9
)
2
100kHz x 2π
τ3 = 659 x 10-9
1/2
62832
6.833
1.1714
τ1
=
39.48 x 1012
From equation 2:
τ2
τ1 = 1.59 x 10 -9 x 2.415
τ1 = 3.84 x 10 -9
1
=
(100kHz x 2π)2 x 659 x 10-9
τ2 = 3.844 x 10-6
Now τ1 = C1 ∴ C1 = 3.84nF
τ2 = R2 (C1 + C2)
Using these values in equation 1:
1 x 10 -3 x 2π x 10MHz/V
100 x (2π x 100kHz)2
[A]1/2
τ1
=
τ3 = C2 R2
Substituting for C2
τ3
∴ τ2 = R2 C1 + τ3
τ2 = R2 C1 +
R2
3.844 x 10 -6 - 659 x 10 -9
9.61 x 10 -9
τ2 - τ3
∴ R2 =
=
C1
R2 = 829.4Ω
τ3 = C2 R2
659 x 10 -9
829.4
τ3
R2
∴ C2 =
=
C2 = 0.794nF
12
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号:
©2020 ICPDF网 联系我们和版权申明