MT9125 [MITEL]
CMOS Dual ADPCM Transcoder; CMOS双ADPCM代码转换器
| 型号： | MT9125 |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | CMOS Dual ADPCM Transcoder |
| 文件： | 总16页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS MT9125
Dual ADPCM Transcoder
Preliminary Information
ISSUE 3
August 1993
Features
Ordering Information
•
•
•
Dual channel full duplex transcoder
32 kbit/s and 24 kbit/s ADPCM coding,
MT9125AE
MT9125AP
24 Pin Plastic DIP
28 Pin PLCC
compatible to G.721 & and G.723 (1988) and
ANSI T1.303-1989
-40 to +85°C
•
•
Low power operation, total 25mW typical
Asynchronous 4.096 MHz master clock
operation
Description
•
•
Transparent ADPCM bypass capability
The Dual-channel ADPCM transcoder is a low
power, CMOS device capable of two encoder
functions and two decoder functions. Two 64 kbit/s
PCM channels are compressed into two 32 kbit/s
ADPCM channels, and two 32 kbit/s ADPCM
channels are expanded into two 64 kbit/s PCM
Serial interface for both PCM and ADPCM data
streams
•
•
•
ST-BUS interface supported
Pin selected µ-law or A-law operation
Pin selected CCITT or sign-magnitude PCM
coding
channels.
algorithm utilized conforms to CCITT Recom-
mendation G.721 and ANSI T1.303-1989. The
The 32 kbit/s ADPCM transcoding
•
•
Single 5 volt power supply
Optional reset value (CCITT Table 3/G.721)
capability
device also supports a 24 kbit/s (three bit word)
algorithm (CCITT/G.723).
Applications
Switching, on-the-fly, between 32 kbit/s and 24
kbit/s, is possible by toggling the appropriate Mode
Select (MS1-MS4) control pins.
•
•
•
Pair gain
Voice mail systems
Wireless set base stations
C2o
BCLK
F0i
EN1
EN2
Timing
ST-BUS
Converter
MCLK
ENS
DSTo
ADPCMi
ADPCM
I/O
Transcoder 1
DSTi
PCM
I/O
ENB1
ENB2
ADPCMo
ENA
Control Decode
Transcoder 2
VDD VSS PWRDN
IC
MS1 MS2 A/µ FORMAT MS3 MS4
Figure 1 - Functional Block Diagram
8-17
MT9125
Preliminary Information
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
MCLK
F0i
C2o
ENS
EN2
EN1
ADPCMo
ADPCMi
ENA
VDD
IC
DSTo
DSTi
BCLK
VSS
ENB2
ENB1
MS1
MS2
MS3
24 PIN PDIP
PWRDN
FORMAT
A/µ
9
10
11
12
MS4
•
DSTo
ADPCMo
5
25
24
23
22
21
20
19
DSTi
BCLK
VSS
ADPCMi
ENA
VDD
NC
IC
PWRDN
6
7
28 PIN PLCC
8
NC
ENB2
ENB1
9
10
11
Figure 2 - Pin Connections
Description
Pin Description
Pin #
Name
DIP PLCC
1
2
MCLK Master Clock input. This 4.096 MHz clock is used as an internal master clock and must be
provided during both ST-BUS and SSI modes of operation. This is a TTL level input.
In ST-BUS mode the MCLK input (also known as C4i in ST-BUS terms) is derived from the
synchronous 4.096 MHz clock available from the layer 1 transceiver device. The C4i clock,
input to MCLK, is used in this mode as both the internal master clock and for deriving the
C2o output clock and EN1/EN2 output enable strobes.
In SSI mode a 4.096 MHz master clock must be derived from an external source. This
master clock may be asynchronous relative to the 8 kHz frame reference.
2
3
3
4
F0i
Frame alignment input pulse for ST-BUS interface operation. This input should be tied low
if ST-BUS operation is not required.
This is a TTL level input.
C2o
2.048MHz Clock output for ST-BUS applications. This clock is MCLK divided by 2 and
inverted. The C2o output activity state is governed by the F0i input pin condition.
F0i input
C2o output
V
disabled (SSI mode automatically activated)
SS
V
enabled
DD
Active F0i strobe
enabled and aligned to F0i due to C4i input at MCLK
4
5
5
6
DSTo Serial PCM octet output stream. Refer to the serial timing diagram of Figure 12.
DSTi Serial PCM octet input data stream. Refer to the serial timing diagram of Figure 12.
This is a TTL level input.
8-18
Preliminary Information
MT9125
Pin Description (continued)
Pin #
Name
Description
DIP PLCC
6
7
BCLK Bit Clock input for both PCM and ADPCM ports; used in SSI mode only. The falling edge of
this clock is used to clock data in on DSTi and ADPCMi. The rising edge is used to clock
data out on DSTo and ADPCMo. Can be any rate between 128 kHz and 2.048 MHz. Refer
to the serial timing diagrams of Figures 12 and 13. When not used, this pin should be tied
to V
.
SS
This is a TTL level input.
7
8
8
V
Power supply ground (0 volts).
SS
10
ENB2 Enable Strobe input for B2 channel PCM timing in SSI mode only. A valid 8-bit strobe must
be present at this input if there are no ST-BUS signals at F0i and MCLK. When the device
detects a valid frame pulse at F0i, PCM timing for the B2 ST-BUS channel is decoded
internally and the ENB2 input is ignored. When not used this pin should be tied to V
This is a TTL level input.
.
SS
9
11
ENB1 Enable Strobe input for B1 channel PCM timing in SSI mode only. A valid 8-bit strobe must
be present at this input if there are no ST-BUS signals at F0i and MCLK. When the device
detects a valid frame pulse at F0i, PCM timing for the B1 ST-BUS channel is decoded
internally and the ENB1 input is ignored. When not used this pin should be tied to V
This is a TTL level input.
.
SS
10, 12,
11 13
MS1, Mode select control input pins 1 and 2 for the B1 channel according to the following:
MS2
MS2
MS1
B1 Channel
0
0
1
1
0
1
0
1
algorithm reset
ADPCM bypass mode (24 or 32 kbit/s)
24 kbit/s ADPCM mode
32 kbit/s ADPCM mode
These are TTL level inputs.
12, 14,
MS3, Mode select control input pins 3 and 4 for the B2 channel according to the following:
13
16
MS4
A/µ
MS4
MS3
B2 Channel
algorithm reset
ADPCM bypass mode (24 or 32 kbit/s)
24 kbit/s ADPCM mode
32 kbit/s ADPCM mode
0
0
1
1
0
1
0
1
These are TTL level inputs.
14
15
16
17
Law select input. Selects µ-Law when low, A-Law when high.
This is a TTL level input.
18 FORMAT Format select input. Selects CCITT PCM coding if high, or SIGN MAGNITUDE PCM if low.
This is a TTL level input.
19 PWRDN Power Down input. Logic low on this pin forces the device to assume an internal power
down mode where all operation is halted. This mode minimizes power consumption.
Outputs are tri-stated. This is a schmidt trigger input.
17
18
19
20
22
23
IC
Internal Connection. Tie to V for normal operation.
SS
V
Positive power supply input, 5 volts ± 10%.
DD
ENA
Enable Strobe input for both input and output ADPCM channels; used for SSI operation
only. Refer to Figure 3. When not used, tie to VSS.
This is a TTL level input.
20
21
24 ADPCMi Serial ADPCM word input data stream. Refer to the serial timing diagram of Fig. 13. This is
a TTL level input.
25 ADPCMo Serial ADPCM word output stream. Refer to the serial timing diagram of Fig.13.
8-19
MT9125
Preliminary Information
Pin Description (continued)
Pin #
Name
Description
DIP PLCC
22
23
24
26
27
28
EN1
EN2
ENS
Channel 1 Output Enable strobe. This output is decoded from the ST-BUS C4i and F0i
signals and its position, within the ST-BUS stream, may be controlled via the ENS pin.
Refer to the ST-BUS relative timing diagram shown in Figure 4.
Channel 2 Output Enable strobe. This output is decoded from the ST-BUS C4i and F0i
signals and its position, within the ST-BUS stream, may be controlled via the ENS pin.
Refer to the ST-BUS timing diagram shown in Figure 4.
Enable Select input for ST-BUS operation only. This control pin changes the ST-BUS
channel position of EN1 and EN2 as well as the ADPCM channel position. Refer to the ST-
BUS timing diagram shown in Figure 4. When not used this pin should be tied to V . This
DD
is a TTL level input.
1, 9,
15,
21
NC
No Connection. Leave open circuit.
clock output, useful for driving the timing input pins
of standard CODEC devices.
Functional Description
The Dual-channel ADPCM Transcoder is a low
power, CMOS device capable of two encoder
functions and two decoder functions. Two 64 kbit/s
PCM channels (PCM octets) are compressed into
two 32 kbit/s ADPCM channels (ADPCM words), and
two 32 kbit/s ADPCM channels (ADPCM words) are
expanded into two 64 kbit/s PCM channels (PCM
octets). The ADPCM transcoding algorithm utilized
conforms to CCITT recommendation G.721 and
ANSI T1.303-1989. The device also supports a 24
kbit/s (three bit word) algorithm (CCITT/G.723).
Switching, on-the-fly, between 32 kbit/s and 24 kbit/s
is possible by toggling the appropriate Mode Select
(MS1-MS4) control pins.
Serial I/O Ports (ADPCMi, ADPCMo, ENA, ENB1,
ENB2, DSTi, DSTo, C2o, EN1, EN2, ENS, F0i)
Serial I/O data transfer to the Dual ADPCM
Transcoder is provided through the PCM and the
ADPCM ports. Serial I/O port operation is similar for
both ST-BUS and SSI modes. The Dual ADPCM
Transcoder determines the mode of operation by
monitoring the signal applied to the F0i pin. When a
valid ST-BUS Frame Pulse (244ns low going pulse)
is connected to the F0i pin the transcoder will
assume ST-BUS operation. If F0i is tied continuously
to V the transcoder will assume SSI operation. Pin
SS
functionality in each of these modes is described in
the following sub-sections.
The internal circuitry requires very little power to
operate; 25mW typically for dual channel operation.
A master clock frequency of 4.096 MHz is required
for the circuit to complete two encode channels and
two decode channels. Operation with an
asynchronous master clock, relative to the 8 kHz
reference, is allowed.
ADPCM Port Operation (ADPCMi, ADPCMo, ENA)
The ADPCM port consists of ADPCMi, ADPCMo and
ENA. ADPCM port functionality is similar for both ST-
BUS and SSI operation, the difference being in
where the BCLK signal is derived and in where the
ADPCM words are placed within the 8 kHz frame.
All optional functions of the device are pin selected,
no microprocessor is required. This allows a simple
interface with industry standard Codecs, Dual
For SSI operation (i.e., when F0i is tied continuously
Codecs, Digital Phone devices, and Layer
transceivers.
1
to V ) both channels of ADPCM code words are
SS
transferred over ADPCMi/ADPCMo at the bit clock
rate (BCLK) during the channel time defined by the
input strobe at ENA. Refer to Figure 3 and to Figure
13. Data is latched into the ADPCMi pin with the
falling edge of BCLK while output data is made
available at ADPCMo on the rising edge of BCLK.
The PCM and ADPCM serial busses are
a
Synchronous Serial Interface (SSI), allowing serial
clock rates from 128 kHz to 2.048 MHz. Additional
pins on the device allow an easy interface to an ST-
BUS component. On chip channel counters provide
channel enable outputs, as well as a 2.048 MHz
8-20
Preliminary Information
MT9125
For ST-BUS operation (i.e., when a valid ST-BUS
frame pulse is applied to the F0i input) the bit rate, at
2.048 MHz, is generated internally from the master
clock input at the MCLK pin. The BCLK and ENA
inputs are ignored. Data is latched into the ADPCMi
pin at the three-quarter bit position which occurs at
the second rising edge of MCLK (C4i) within the bit
cell boundary. Output data, on ADPCMo, is made
available at the first falling edge of MCLK (C4i) within
the bit cell boundary. Refer to Figure 13.
time defined by the input strobes at ENB1 and ENB2
or by internally generated timeslots.
For ST-BUS operation, (i.e., when a valid ST-BUS
frame pulse is applied to the F0i input) the bit rate, at
2.048 MHz, is generated internally from the master
clock input at the MCLK pin. The BCLK and ENA
inputs are ignored. ST-BUS timeslot assignment is
also generated internally and can be programmed
into channels 0 and 1 or into channels 2 and 3 with
the ENS input pin. Refer to Figure 4. In this mode the
ENB1 and ENB2 inputs are ignored by the device.
The decoded channel timeslots (0 and 1 or 2 and 3)
are made available, along with the 2.048 MHz bit
clock, at EN1, EN2 and C2o for controlling CODEC
devices as shown in the Applications section (refer
to Figures 7 and 11). Data is latched into the DSTi
pin at the three-quarter bit position which occurs at
the second rising edge of MCLK (C4i) within the bit
cell boundary. Output data, on DSTo, is made
available at the first falling edge of MCLK (C4i) within
the bit cell boundary. Refer to Figure 12.
ADPCM word placement, within the ST-BUS frame,
is governed by the logic state applied at the ENS
input pin. Referring to Figure 4, when ENS = 0, the
ADPCM words are placed in channel 2 while when
ENS = 1 the ADPCM words are placed in channel 3.
Unlike the PCM octets the ADPCM words never
reside within the ST-BUS channel 0 or 1 timeslots.
PCM Port Operation (DSTi, DSTo, ENB1, ENB2)
The PCM port consists of DSTi, DSTo, ENB1 and
ENB2. PCM port functionality is almost identical for
both ST-BUS and SSI operation, the difference being
from where the BCLK signal is derived and whether
the enable strobes are generated internally or
sourced externally.
For SSI operation, (i.e., when F0i is tied continuously
to V ) the bit rate is set by the input clock presented
SS
at the BCLK pin. Data is transferred at the bit clock
rate (BCLK) during the B1 and B2 channels as
defined by input strobes ENB1 and ENB2,
respectively. Note that ENB1 and ENB2 are also
used as the framing inputs for internal operation of
Both channels of PCM octets are transferred over
DSTi/DSTo at the bit clock rate during the channel
8 bits
ENB1
8 bits
ENB2
DSTi/o
B1 Channel
B2 Channel
4 bits
4 bits
ENA
4 bits
B1
4 bits
B2
ADPCMi/o
B1
B2
Normally ENA is derived from the same strobes which drive the ENB1 or ENB2 inputs. However, as long as ENA
is eight cycles of BCLK length, it may be positioned anywhere within the 8 kHz frame.
Figure 3 - SSI Mode Relative Timing
8-21
MT9125
Preliminary Information
F0i
Channel 0
B1
Channel 1
B2
Channel 2
B1
Channel 3
B2
DSTi/o
EN1
ENS=0
EN2
ADPCMi/o
B1
B2
EN1
ENS=1
EN2
ADPCMi/o
B1
B2
In ST-BUS mode the ENA, ENB1 and ENB2 input strobes are ignored. All timing is
dervied internally from the F0i, MCLK and ENS inputs.
Figure 4 - ST-BUS Mode Relative Timing
the device and must, therefore, be present whenever
a transcoding operation is required. These inputs
may be tied together and connected to the same
strobe for single channel operation. Only the B1
nibble is valid in this mode. Data is latched into the
DSTi pin with the falling edge of the bit clock while
output data is made available at DSTo on the rising
edge of the bit clock.
Forcing the C2o output to logic low enhances power
conservation as well as removing a non-required
clock signal from the circuit. This 2.048 MHz bit clock
may be used to control external CODEC functions.
The 4.096 MHz and frame pulse signals are also
decoded into two output strobes corresponding to
the B1 and B2 channel timeslots of the ST-BUS.
These strobes (EN1 and EN2) are then used to
control the timing inputs of an external CODEC. A
typical example of this connection scheme is shown
in the application diagram of Figure 7.
ST-BUS Conversion (F0i, C2o, EN1, EN2, ENS)
A simple converter circuit is incorporated which
allows ST-BUS signals to be converted to SSI
signals. In this manner it is very simple for an ST-
BUS application to be mixed with CODECs utilizing a
strobed data I/O.
The Enable Strobe pin (ENS) is used to position the
output strobes EN1 and EN2 within the ST-BUS
frame. Referring to Figure 4, when ENS=0 the output
strobes are positioned in channels 0 and 1 of the ST-
BUS frame. When ENS=1 the output strobes are
positioned in channels 2 and 3 of the ST-BUS frame.
This flexibility allows the transcoder to be used in
ST-BUS basic rate applications where channels 0
and 1 are defined as the D and C channels,
respectively, and also in line-card applications where
the full 2.048 MHz bandwidth is used for conveying
data and/or digitally encoded voice information.
This converter circuit consists of the F0i input and
C2o, EN1 and EN2 output pins (as well as the MCLK
input master clock). The output C4b clock and frame
pulse strobe (F0b), from the ST-BUS layer 1
transceiver, are connected directly to the master
clock (MCLK) and frame pulse (F0i) inputs of the
transcoder. A 2.048 MHz (C2o) bit clock output is
made available when a valid Frame Pulse is
connected to the F0i pin or the F0i pin is tied high. If
the F0i pin is tied low the C2o output is forced
continuously to a logic low level (not tri-stated).
8-22
Preliminary Information
MT9125
Mode Selection (MS1, MS2, MS3, MS4)
DSTo
ADPCMi
ADPCMo
Separate mode select pins are available for per-
channel B1 and B2 operation. MS1 and MS2 are
used to configure the B1 channel while MS3 and
MS4 configure the B2 channel. Normally the mode
select pins are operated as static control lines. The
exception to this is for on-the-fly programming to/
from 32 kbit/s from/to 24 kbit/s modes.
DSTi
Dual ADPCM Transcoder
B1
B2
ADPCM i/o
X X X X
3 2 1 0
3 2 1 0
B1 Channel
B2 Channel
MS4 MS3
3 2 1 0
3 2 1 0
X X X X
DSTi/o
MS2 MS1 Operational Mode
B1
B2
0
0
0
1
algorithm reset
ADPCM bypass mode
(24 or 32 kbit/s)
24 kbit/s ADPCM mode
32 kbit/s ADPCM mode
0
0
0
1
In ADPCM by-pass mode, the B1 and B2 channel ADPCM
words are transparently passed (with a two frame delay) to
the most significant nibbles of the PCM octets. This feature
allows two voice terminals, which utilize ADPCM transcod-
ing, to communicate through a system (i.e., PBX, key-system)
without incurring unnecessary transcode conversions. This
arrangement also allows byte-wide or nibble-wide transport
through a switching matrix.
1
1
0
1
1
1
0
1
Algorithm Reset Mode
Figure 5 - ADPCM By-pass Mode
An algorithm reset is accomplished by forcing all
mode select pins simultaneously to logic zero. While
asserted, this will cause the device to incrementally
converge the internal variables of both channels to
the 'Optional reset values' per G.721. Invoking the
reset conditon on only one channel will cause that
channel to be reset properly and the other channel’s
operation to be undefined. This optional reset
requires that the master clock (MCLK) and frame
pulse (ENB1/2 or F0i) remain active and that the
reset condition be valid for at least four frames. Note
that this is not a power down mode.
requirements necessary for on-the-fly control of the
Mode Select pins. The 3-bit ADPCM words occupy
the most significant bit positions of the standard 4-bit
ADPCM word.
32 kbit/s ADPCM Mode
In 32 kbit/s mode PCM octets are transcoded into
four bit words as described in CCITT G.721. This is
the standard mode of operation and, if the other
modes are not required, can be implemented by
simply tying the per-channel mode select pins to
V
.
ADPCM By-Pass Mode
DD
Master Clock (MCLK)
In ADPCM bypass mode the B1 and B2 channel
words are transparently relayed (with a two-frame
delay) to/from the ADPCM port and placed into the
most significant nibbles of the B1 and B2 channel
PCM octets. Refer to Figure 5. The ability to transfer
ADPCM words transparently through the transcoder
enables set-to-set connections for wireless
telephony applications.
A 4.096 MHz master clock is required for execution
of the dual transcoding algorithm. The algorithm
requires 512 cycles of MCLK during one frame for
proper operation. This input, at the MCLK pin, may
be asynchronous with the 8 kHz frame provided that
the lowest frequency, and/or deviation due to clock
jitter, still meets the minimum strobe period
requirement of 512 t
-50nSec. (See AC Electrical
24 kbit/s Mode
C4P
Characteristics - Serial PCM/ADPCM Interfaces.)
In 24 kbit/s mode (CCITT G.723) PCM octets are
transcoded into three bit words rather than the four
bit words of the standard 32 kbit/s ADPCM. This is
useful in situations where lower bandwidth
transmission is required. Dynamic operation of the
mode select control pins will allow switching from 32
kbit/s mode to 24 kbit/s mode on a frame by frame
basis. Figure 6 shows the internal pipelining of the
conversion sequence and how the mode select pins
are to be used. Fig. 15 details the timing
For example, a system producing large jitter values
can be accommodated by running an over-speed
MCLK to ensure that a minimum 512 MCLK cycles
per frame is obtained. The minimum MCLK period is
190 nSeconds, which translates to a maximum
frequency of 5.26 MHz. Extra MCLK cycles (>512/
frame) are acceptable because the transcoder is re-
aligned by the appropriate strobe signals each
frame.
8-23
MT9125
Preliminary Information
frame n-1
frame n
frame n+1
DSTi
PCM Byte "X" processed according
to MSn input states latched during
frame n
ADPCM Word "X" output from
device during frame n+1
PCM Byte "X" latched into device
during frame n-1
ADPCMo
ENA
ENB1 or
EN1
MS1/3
MS2/4
1,1=32 kb/s
1,1=32 kb/s
1,0=24 kb/s
This diagram shows the conversion sequence from PCM to ADPCM. The same pipelining occurs in the
reverse ADPCM to PCM direction.
Total delay from data input to data output = 2 frames. See Figure 15 for detailed ENB1/EN1 timing.
Figure 6 - Pipelining for Dynamic 32/24 kb/s Operation
Bit Clock (BCLK)
FORMAT
For SSI operation the bit rate, for both ADPCM and
PCM ports, is determined by the clock input at BCLK.
BCLK must be eight periods in duration and
synchronous with the 8 kHz frame input at ENB1.
Data is sampled at DSTi and at ADPCMi concurrent
with the falling edge of BCLK. Data is available at
DSTo and ADPCMo concurrent with the rising edge
of BCLK. BCLK may be any rate between 128 kHz
and 2.048 MHz. Refer to Figures 12 and 13.
0
1
CCITT (G.711)
Sign-
Magnitude
A/µ = 0 or 1
PCM Code
(A/µ = 0)
(A/µ = 1)
+ Full Scale
+ Zero
1111 1111
1000 0000
0000 0000
0111 1111
1000 0000
1111 1111
0111 1111
0000 0000
1010 1010
1101 0101
0101 0101
0010 1010
- Zero
For ST-BUS operation BCLK is ignored and the bit
rate is internally set to 2.048 MHz.
- Full Scale
Table 1
Processing Delay through the Device
PCM Law Control (A/µ, FORMAT)
The PCM companding/coding law invoked by the
transcoder is controlled via the A/µ and FORMAT
One 8 kHz frame is required for serial loading of the
input buffers, and one frame is required for
processing, for a total of two frame delays through
the device. All internal input/output PCM and
ADPCM shift registers are parallel loaded through
secondary buffers on an internal frame pulse. The
device derives its internal frame reference from the
F0i, ENB1 and ENB2 pins in the following manner. If
a valid ST-BUS frame pulse is present at the F0i pin
the transcoder will assume ST-BUS operation and
will use this input as the frame reference. In this
pins. CCITT G.711 companding curves, µ-Law and
A-Law, are determined by the A/µ pin (0=µ-
Law; 1=A-Law). Per sample, digital code assignment
can conform to CCITT G.711 (when FORMAT=1) or
to Sign-Magnitude coding (when FORMAT=0). Table
1 illustrates these choices.
8-24
Preliminary Information
MT9125
DX
MT9125
DR
VFxL+
VFxL-
MT8910
C2o
ENS
S
L
FSX
BCLK
F0i
T
FSR
I
Lin+
Lin-
T
F0b
C4b
EN1
EN2
C
BCLKX
MCLKX
MCLK
Lout+
R
VFRO
Lout
-
R
ADPCMi
ADPCMo
ENA
DSTo
DSTi
DSTi
DSTo
ENB1
ENB2
DX
DR
VFxL+
VFxL-
S
FSX
L
T
FSR
I
C
BCLKX
MCLKX
R
VFRO
FPi
C4i
VDD
DX
MT9125
DR
VFxL+
VFxL-
C2o
ENS
S
DSTi
DSTo
FSX
L
T
I
BCLK
F0i
FSR
EN1
EN2
C
BCLKX
MCLKX
Gate Array
MCLK
R
VFRO
ADPCMi
ADPCMo
ENA
DSTi
DSTo
ENB1
ENB2
Ring
DX
Generator
DR
VFxL+
VFxL-
S
L
FSX
T
FSR
I
Hookswitch
from SLICs
C
BCLKX
MCLKX
to SLICs
R
VFRO
Figure 7 - Pair Gain Application (ST-BUS/SSI)
Dout
MT9125
Din
R
T
2 x
Ain+
Ain-
MT8910
C2o
ENS
STB1
CLK
BCLK
F0i
S
L
I
Lin+
T
EN1
EN2
F0b
C4b
Lin-
Lout
Lout
R
T
Aout
MCLK
C
+
-
R
Dual Codec
ADPCMi
ADPCMo
ENA
DSTo
DSTi
DSTi
DSTo
ENB1
ENB2
FPi
C4i
VDD
Dout
MT9125
Din
2 x
R
T
Ain+
Ain-
C2o
ENS
DSTi
DSTo
STB1
CLK
BCLK
F0i
S
L
I
EN1
EN2
R
T
Aout
Gate Array
MCLK
C
Dual Codec
ADPCMi
ADPCMo
ENA
DSTi
DSTo
ENB1
ENB2
Ring
Generator
Hookswitch
from SLICs
to SLICs
Figure 8 - Pair Gain Application (ST-BUS/ST-BUS)
8-25
MT9125
Preliminary Information
configuration the ENB1 and ENB2 inputs are
Removal of the BCLK and MCLK inputs is not
necessary during power-down mode. If the device is
released from power-down without a valid MCLK the
ADPCMo and PCMo outputs will become active,
driving either continuous logic high or logic low, until
a MCLK signal is applied to resume internal
operation.
ignored. If F0i is tied continuously to V , then SSI
SS
operation will be assumed and the transcoder will
use the strobes connected to ENB1 and ENB2 as its
internal reference.
Power-Down Operation (PWRDN)
PWRDN is a schmidt trigger input.
To minimize power consumption a pin selected,
power-down option is provided. Device power down
is accomplished by forcing the PWRDN pin to V
.
SS
This asynchronous control forces all internal clocking
to halt and the C2o, EN1, EN2, DSTo and ADPCMo
outputs to become tri-stated. Upon returning
Applications
Various configurations of Pair Gain drops are
depicted in Figures 7, 8 and 9. These show
applications using mixed ST-BUS/SSI, all ST-BUS
and all SSI implementations. Figure10 shows an ST-
BUS line card application for Pair Gain while Figure
11 shows a 2-channel, wireless-set, base station
application based upon ST-BUS.
PWRDN to V
coincident with the next alignment
DD
signal, all outputs will return to their active state and
the internal clocks are re-started. In this mode the
ADPCM algorithm is not reset to the 'optional reset
values', however, the self-convergent nature of the
algorithm will ensure that convergence of the
(AD)PCM streams will occur within 3496 frames as
specified by CCITT G.721.
VDD
DX
MT9125
DR
VFxL+
BCLK
ENS
FSX
S
L
I
VFxL-
F0i
T
FSR
Lin+
Lin-
T
BCLK
MCLK
BCLKX
MCLKX
C
MCLK
R
Lout+
VFRO
Lout
-
R
ADPCMi
ADPCMo
ENA
DSTi
DSTo
ENB1
ENB2
TX
RX
DX
EN1
EN2
DR
VFxL+
VFxL-
FSX
S
L
I
T
FSR
C
BCLKX
MCLKX
R
VFRO
VDD
DX
MT9125
DR
Gate
Array
VFxL+
VFxL-
BCLK
ENS
FSX
S
L
I
T
F0i
FSR
BCLKX
MCLKX
C
MCLK
R
VFRO
Ring
Generator
ADPCMi
ADPCMo
ENA
DSTi
DSTo
ENB1
ENB2
DX
DR
VFxL+
VFxL-
S
L
I
FSX
Hookswitch
from SLICs
T
FSR
to SLICs
C
BCLKX
MCLKX
R
VFRO
Figure 9 - Pair Gain Application (SSI/SSI)
8-26
Preliminary Information
MT9125
VDD
MT8980
B Channel Switch
MT9125
C2o
MT8910
Lin+
ENS
C4ib
DSTi
DSTo
BCLK
F0i
FPib
DSTi
F0b
C4b
EN1
EN2
Lin-
Lout
Lout
C4ib
DSTo
MCLK
+
-
FPib
DSTo
DSTi
C4ib
ADPCMi
ADPCMo
ENA
DSTo
DSTi
DSTi
DSTo
ENB1
ENB2
FPob
1
FPob
FPb
MT9125
System Frame pulse or
delayed frame pulse
from previous selection
DSTo
DSTi
C4ib
FPib
C2o
ENS
BCLK
F0i
EN1
EN2
FPob
MCLK
7
ADPCMi
ADPCMo
ENA
DSTi
DSTo
ENB1
ENB2
FPib
DSTo
DSTi
C4ib
MT8980
C & D Channel
Switch
FPob
1/2 bandwidth
unusable
8
Figure 10 - Application (ST-BUS Line Card)
VDD
BIT CLOCK
MT9125
MT89xx
C2o
ENS
ADPCM ENABLE
BCLK
F0i
Lout
T
EN1
EN2
RFB1
F0b
MCLK
C4b
Lin
Lin
R
T
DSTi
ADPCMi
ADPCMo
DSTo
DSTi
DSTo
ENB1
ENB2
ENA
RFB2
Lout
R
The layer 1 device shown may be the 2-wire
MT8910 or MT8972 or the 4-wire MT8930.
2 Channel RF Section
B1
B2
ADPCM nibbles concatenated into one 8
bit timeslot
B3 B2 B1 B0 B3 B2 B1 B0
B1
B2
Normal ST-BUS channel assignment
B7 B6 B5 B4
B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
In ADPCM by-pass mode (MS pin control)
the ADPCM nibbles are automatically
inserted into the most significant nibbles
of the 8-bit DSTi/o B1 and B2 bytes.
B1
B2
X
X
X
X
B3 B2 B1 B0
B3 B2 B1 B0
X
X
X
X
ENB1 (and ENA)
ENB2
Figure 11 - Application (2-Channel, Wireless-set, Base Station)
8-27
MT9125
Preliminary Information
Absolute Maximum Ratings*
Parameter
Symbol
-V
Min
Max
Units
1
2
3
4
5
6
Supply Voltage
V
-0.3
-0.3
7.0
V
V
DD SS
Voltage on any I/O pin
Continuous Current on any I/O pin
Storage Temperature
Power Dissipation
V | V
V
+ 0.3
DD
i
o
I | I
±20
150
500
mA
°C
i
o
T
-65
ST
P
mW
mA
D
Latch-up Immunity
I
±100
LU
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Supply Voltage
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
V
4.5
2.4
0
5.0
5.5
V
V
DD
Input High Voltage
Input Low Voltage
V
V
400mV noise margin
400mV noise margin
IH
DD
V
0.4
85
V
IL
Operating Temperature
T
-40
°C
A
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
2.0
2.4
Typ
Max
Units
Test Conditions
1
Supply Current
I
100
5
µA
mA
PWRDN = 0
PWRDN = 1, clocks active
static
operating
CC
I
DD1
2
3
4
High level input voltage
Low level input voltage
Input leakage current
V
V
V
All inputs except PWRDN
All inputs except PWRDN
IH
V
0.8
10
IL
I /I
0.1
µA
V
=5.5V,
DD
IH IL
V =V to V
IN
SS
DD
5
6
7
8
9
High level output voltage
Low level output voltage
Output low (sink) current
Output high (source) current
High impedance leakage
V
V
V
OH
V
0.4
10
OL
OL
I
4.0
4.0
15
10
1
mA
mA
µA
V
V
V
=0.4V, V =4.5V
DD
OL
OH
DD
I
=2.4V, V =4.5V
OH
DD
I
=5.5V,
OZ
V =V to V
IN
SS
DD
10 Output capacitance
11 Input capacitance
C
10
15
pF
pF
V
o
C
i
12 Positive Going Threshold
Voltage (PWRDN only)
Hysteresis
V+
3.7
V -V
1.0
V
V
+
-
Negative Going Threshold
Voltage (PWRDN only)
V
1.3
-
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
8-28
Preliminary Information
MT9125
AC Electrical Characteristics† - Serial PCM/ADPCM Interfaces (see Figures 12 & 13)
Voltages are with respect to ground (VSS) unless otherwise stated.
†
Characteristics
Data Clock High
Sym
Min
Typ
Max
Units
Test Conditions
C =150pF
1
2
3
4
t
160
160
400
ns
ns
ns
ns
CLH
L
Data Clock Low
BCLK Period
t
C =150pF
L
CLL
BCL
t
7900
C =150pF
L
Data Output Delay (excluding
first bit)
60
60
C =150pF
L
t
DD
5
6
Output Active to High Z
Strobe Signal Setup
t
ns
ns
C =150pF
L
AHZ
SSS
t
80
80
t
t
-
-
C =150pF
L
BCL
80
7
8
9
Strobe Signal Hold
t
ns
ns
C =150pF
L
SSH
BCL
80
Strobe period relative to MCLK
(ENB1, ENB2, ENA)
512t
-
C =150pF
L
C4P
50
50
50
Data Input Setup
t
ns
ns
ns
ns
ns
%
C =150pF
L
DIS
10 Data Input Hold
11 Strobe to Data Delay (first bit)
12 F0i Setup
t
C =150pF
L
DIH
t
60
122
122
50
C =150pF
L
SD
t
t
50
50
40
150
150
60
C =150pF
L
F0iS
F0iH
13 F0i Hold
C =150pF
L
14 MCLK (C4i) duty cycle
t /t
C =150pF
L
H L
x100
15 MCLK (C4i) period
16 Data Output delay
17 Data in Hold time
18 Data in Setup time
t
190
244.2
125
ns
ns
ns
ns
C =150pF
L
C4P
t
C =150pF
L
DSToD
t
50
50
C =150pF
L
DSTiH
t
C =150pF
L
DSTiS
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
8-29
MT9125
Preliminary Information
tCLH
tBCL
tCLL
VIH
BCLK
VIL
tSSH
tSSS
S
S
I
ENB1
or
ENB2
VIH
VIL
tDIS
tDIH
VIL
b7
b7
b6
tDSTiS
b5
b5
b1
b1
b0
DSTi
VIL
tAHZ
tDD
tDSTiH
tSD
VOH
VOL
b6
b0
DSTo
tDSToD
tH
VIH
VIL
S
T
-
B
U
S
MCLK
F0i
tF0iH
tC4P
tL
VIH
VIL
tF0iS
Figure 12- Serial PCM Port Timing
tCLH
tBCL
tCLL
VIH
VIL
BCLK
ENA
tSSH
tSSS
S
S
I
VIH
VIL
tDIS
tDIH
VIL
VIL
b1-1
b1-1
b1-2
tDSTiS
b1-3
b2-3
tDD
b2-4
tAHZ
ADPCMi
tSD
tDSTiH
VOH
VOL
b1-2
b1-3
b2-3
b2-4
ADPCMo
tDSToD
tH
VIH
VIL
S
T
-
B
U
S
MCLK
F0i
tF0iH
tC4P
tL
VIH
VIL
tF0iS
Figure 13 - Serial ADPCM Port Timing
8-30
Preliminary Information
MT9125
AC Electrical Characteristics† - ST-BUS Conversion (see Figure 14)
Voltages are with respect to ground (VSS) unless otherwise stated.
†
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
150pF Load
150pF Load
1
2
Delay MCLK falling to C2o rising
Delay MCLK falling to Enable
t
100
100
ns
ns
D1
t
D2
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
VIH
F0i
VIL
VIL
VIL
MCLK
(C4i)
tD1
VOH
VOL
C2o
VOH
VOL
EN1
EN2
tD2
tD2
Figure 14 - ST-BUS Timing for External Signal Generation
AC Electrical Characteristics† - Mode Select Timing (see Figure 15)
Voltages are with respect to ground (VSS) unless otherwise stated.
†
Characteristics
Mode Select Setup
Mode Select Hold
Sym
Min
Typ
Max
Units
Test Conditions
1
2
t
500
ns
ns
SU
t
500
HOLD
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tSU
tHOLD
MS1-MS4
ENB1 (SSI Mode)
EN1 (ST-BUS Mode)
Figure 15 - Mode Select Set-up and Hold Timing for Dynamic Operation
8-31
MT9125
Preliminary Information
NOTES:
8-32
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