MT9126 [MITEL]
CMOS Quad ADPCM Transcoder; CMOS四路ADPCM代码转换器
| 型号： | MT9126 |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | CMOS Quad ADPCM Transcoder |
| 文件： | 总22页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS MT9126
Quad ADPCM Transcoder
Preliminary Information
ISSUE 2
May 1995
Features
•
Full duplex transcoder with four encode
channels and four decode channels
Ordering Information
MT9126AE
MT9126AS
28 Pin Plastic DIP
28 Pin SOIC
•
32 kb/s, 24 kb/s and 16 kb/s ADPCM coding
complying with ITU-T (previously CCITT) G.726
(without 40 kb/s), and ANSI T1.303-1989
-40 °C to +85 °C
•
•
Low power operation, 25 mW typical
Description
Asynchronous 4.096 MHz master clock
operation
The Quad ADPCM Transcoder is a low power,
CMOS device capable of four encode and four
decode functions per frame. Four 64 kbit/s PCM
octets are compressed into four 32, 24 or 16 kbit/s
ADPCM words, and four 32, 24 or 16 kbit/s ADPCM
words are expanded into four 64 kbit/s PCM octets.
The 32, 24 and 16 kbit/s ADPCM transcoding
•
•
•
•
•
•
•
•
SSI and ST-BUS interface options
Transparent PCM bypass
Transparent ADPCM bypass
Linear PCM code
No microprocessor control required
Simple interface to Codec devices
Pin selectable µ−Law or A-Law operation
algorithms
utilized
conform
to
ITU-T
Recommendation G.726 (excluding 40 kbit/s), and
ANSI T1.303 - 1989.
Pin selectable ITU-T or signed magnitude PCM
coding
Switching, on-the-fly, between 32 kbit/s and 24 kbit/s
ADPCM, is possible by controlling the appropriate
mode select (MS1 - MS6) control pins. All optional
functions of the device are pin selectable allowing a
simple interface to industry standard codecs, digital
phone devices and Layer 1 transceivers. Linear
coded PCM is provided to facilitate external DSP
functions .
•
Single 5 volt power supply
Applications
•
•
•
Pair gain
Voice mail systems
Wireless telephony systems
PCMo1
PCMi1
Full Duplex
ADPCMi
ADPCMo
ADPCM
I/O
PCM
I/O
Quad
Transcoder
PCMo2
PCMi2
ENB1
ENB2/F0od
BCLK
F0i
MCLK
Timing
C2o
EN1
EN2
Control Decode
VDD VSS PWRDN IC
MS1 MS2 MS3
FORMAT MS4 MS5 MS6 LINEAR SEL
A/µ
Figure 1 - Functional Block Diagram
8-33
MT9126
Preliminary Information
1
2
3
4
5
6
7
8
EN1
MCLK
F0i
EN2
MS6
MS5
MS4
ADPCMo
ADPCMi
VDD
MS3
MS2
MS1
IC
PWRDN
FORMAT
A/µ
28
27
26
25
24
23
22
21
20
19
18
17
C2o
BCLK
PCMo1
PCMi1
VSS
LINEAR
9
10
11
12
13
14
ENB2/F0od
ENB1
PCMo2
PCMi2
SEL
16
15
Figure 2 - Pin Connections
Pin Description
Pin #
1
Name
EN1
Description
Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1
PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1.
In SSI mode this output is high impedance.
2
MCLK
Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the
transcoder function; it must be supplied in both ST-BUS and SSI modes of operation.
In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is
also used to control the data I/O flow on the PCM and ADPCM input/output pins
according to ST-BUS requirements.
In SSI mode this master clock input is derived from an external source and may be
asynchronous with respect to the 8 kHz frame. MCLK rates greater than 4.096 MHz are
acceptable in this mode since the data I/O rate is governed by BCLK.
3
4
F0i
Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI
operation is enabled by connecting this pin to VSS
.
C2o
2.048 MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input
divided by two, inverted, and synchronized to F0i. This output is high-impedance during
SSI operation.
5
BCLK
Bit Clock (Input). 128 kHz to 4096 kHz bit clock input for both PCM and ADPCM ports;
used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1
and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This input
must be tied to VSS for ST-BUS operation.
6
7
PCMo1
PCMi1
Serial PCM Stream 1 (Output). 128 kbit/s to 4096 kbit/s serial companded/linear PCM
output stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out by
MCLK divided by two in ST-BUS mode. See Figure 14.
Serial PCM Stream 1 (Input). 128 kbit/s to 4096 kbit/s serial companded/linear PCM
input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the
3/4 bit position of MCLK in ST-BUS mode. See Figure 14.
8
9
VSS
Digital Ground. Nominally 0 volts.
LINEAR
Linear PCM Select (Input). When tied to V the PCM I/O ports (PCM1,PCM2) are 16-
DD
bit linear PCM. Linear PCM operates only at a bit rate of 2048 kbit/s. Companded PCM is
selected when this pin is tied to VSS. See Figures 5 & 8.
8-34
Preliminary Information
MT9126
Pin Description
Pin #
10
Name
Description
ENB2/F0od PCM B-Channel Enable Strobe 2 (Input) / Delayed Frame Pulse (Output).
SSI operation: ENB2 (Input). An 8-bit wide enable strobe input defining B2 channel
(AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. See
Figures 4 & 6.
ST-BUS operation: F0od (Output). This pin is a delayed frame strobe output. When LIN-
EAR=0, this becomes a delayed frame pulse output occurring 64 C4 clock cycles after
F0i and when LINEAR = 1 at 128 C4 clock cycles after F0i . See Figures 7, 8, 9 & 14.
11
ENB1
PCM B-Channel Enable Strobe 1 (Input).
SSI operation: An 8-bit wide enable strobe input defining B1 channel (AD)PCM data. A
valid 8-bit strobe must be present at this input for SSI operation.
ST-BUS operation: When tied to VSS transparent bypass of the ST-BUS D- and C- chan-
nels is enabled. When tied to VDD the ST-BUS D-channel and C-channel output timeslots
are forced to a high-impedance state.
12
13
14
PCMo2
PCMi2
SEL
Serial PCM Stream 2 (Output). 128 kbit/s to 4096 kbit/s serial companded/linear PCM
output stream. Clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK
divided by two in ST-BUS mode. See Figure 14.
Serial PCM Stream 2 (Input). 128 kbit/s to 4096 kbit/s serial companded/linear PCM input
stream. Data bits are clocked in on falling edge of BCLK in SSI mode. Clocked in at the
3/4 bit position of MCLK in ST-BUS mode. See Figure 14.
SELECT (Input).
PCM bypass mode: When SEL=0 the PCM1 port is selected for PCM bypass operation
and when SEL=1 the PCM2 port is selected for PCM bypass operation.
See Figures 6 & 9.
16 kbit/s transcoding mode:
SSI Operation - in 16 kbit/s transcoding mode, the ADPCM words are assigned to the I/O
timeslot defined by ENB2 when SEL=1 and by ENB1 when SEL=0. See Figure 4.
ST-BUS operation- in 16 kbit/s transcoding mode, the ADPCM words are assigned to the
B2 timeslot when SEL=1 and to the B1 timeslot when SEL=0. See Figure 9.
15
16
A/µ
A-Law/µ−Law Select (Input). This input pin selects µ−Law companding when set to
logic 0, and A-Law companding when set to logic 1. This control is for all channels .This
input is ignored in Linear mode during which it may be tied to VSS or VDD
.
FORMAT
FORMAT Select (Input). Selects ITU-T PCM coding when high and Sign-Magnitude
PCM coding when low. This control is for all channels.This input is ignored in Linear
mode during which it may be tied to VSS or VDD
.
17
18
PWRDN
IC
Power-down (Input). An active low reset forcing the device into a low power mode
where all outputs are high-impedance and device operation is halted.
Internal Connection (Input). Tie to VSS for normal operation.
8-35
MT9126
Preliminary Information
Pin Description
Pin #
Name
Description
Mode Selects 1, 2 and 3 (Inputs). Mode selects for all four encoders.
19
20
21
MS1
MS2
MS3
MS3 MS2 MS1
MODE
0
0
0
0
0
1
0
1
0
32 kbit/s ADPCM
24 kbit/s ADPCM
16 kbit/s ADPCM in EN1/ENB1 when SEL=0
in EN2/ENB2 when SEL=1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
ADPCM Bypass for 32 kbit/s and 24 kbit/s
ADPCM Bypass for 16 kbit/s
PCM Bypass (64 kbit/s) to PCM1 if SEL=0, PCM2 if SEL=1
Algorithm reset (ITU-T optional reset)
ADPCMo disable
22
23
VDD
Positive Power Supply. Nominally 5 volts +/-10%
ADPCMi
Serial ADPCM Stream ( Input). 128 kbit/s to 4096 kbit/s serial ADPCM word input
stream. Data bits are clocked in on falling edge of BCLK in SSI mode and clocked in on
the 3/4 bit edge of MCLK in ST-BUS mode.
24
ADPCMo
Serial ADPCM Stream (Output). 128 kbit/s to 4096 kbit/s serial ADPCM word output
stream. Data bits are clocked out by rising edge of BCLK in SSI mode and clocked out by
MCLK divided by two in ST-BUS mode.
25
26
27
MS4
MS5
MS6
Mode Selects 4, 5 and 6 (Inputs). Mode selects for all four decoders.
MS6 MS5 MS4
MODE
0
0
0
0
0
1
0
1
0
32 kbit/s ADPCM
24 kbit/s ADPCM
16 kbit/s ADPCM in EN1/ENB1 when SEL=0
in EN2/ENB2 when SEL=1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
ADPCM Bypass for 32 kbit/s and 24 kbit/s
ADPCM Bypass for 16 kbit/s
PCM Bypass (64 kbit/s) to PCM1 if SEL=0, PCM2 if SEL=1
Algorithm reset (ITU-T optional reset)
PCMo1/2 disable
28
EN2
Enable Strobe 2 (Output). This 8 bit wide, active high strobe is active during the B2
PCM channel in ST-BUS mode. Forced to high impedance when LINEAR=1.
Notes:
All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.
All inputs have TTL compatible logic levels except for MCLK which has CMOS compatible logic levels and PWRDN which has Schmitt
trigger compatible logic levels.
All outputs are CMOS with CMOS logic levels (See DC Electrical Characteristics).
8-36
Preliminary Information
MT9126
Functional Description
Serial (AD)PCM Data I/O
The Quad-channel ADPCM Transcoder is a low
power, CMOS device capable of four encode and
four decode operations per frame. Four 64 kbit/s
channels (PCM octets) are compressed into four 32,
24 or 16 kbit/s ADPCM channels (ADPCM words),
and four 32, 24 or 16 kbit/s ADPCM channels
(ADPCM words) are expanded into four 64 kbit/s
PCM channels (PCM octets). The ADPCM
transcoding algorithm utilized conforms to ITU-T
recommendation G.726 (excluding 40 kb/s), and
ANSI T1.303 - 1989. Switching on-the-fly between
32 and 24 kbit/s transcoding is possible by toggling
the appropriate mode select pins (supports T1
robbed-bit signalling).
Serial data transfer to/from the Quad ADPCM
transcoder is provided through one ADPCM and two
PCM ports (ADPCMi, ADPCMo, PCMi1, PCMo1,
PCMi2, PCMo2). Data is transferred through these
ports according to either ST-BUS or SSI
requirements. The device determines the mode of
operation by monitoring the signal applied to the F0i
pin. When a valid ST-BUS frame pulse (244nSec low
going pulse) is applied to the F0i pin the transcoder
will assume ST-BUS operation. If F0i is tied
continuously to VSS the transcoder will assume SSI
operation. Pin functionality in each of these modes is
described in the following sub-sections.
ST-BUS Mode
All functions supported by the device are pin
selectable. The four encode functions comprise a
common group controlled via Mode Select pins MS1,
MS2 and MS3. Similarily, the four decode functions
form a second group commonly controlled via Mode
Select pins MS4, MS5 and MS6. All other pin
controls are common to the entire transcoder.
During ST-BUS operation the C2o, EN1, EN2 and
F0od outputs become active and all serial timing is
derived from the MCLK (C4) and F0i inputs while the
BCLK input is tied to VSS. (See Figures 7, 8 & 9.)
Basic Rate “D” and “C” Channels
The device requires 25 mWatts (MCLK= 4.096 MHz)
typically for four channel transcode operation. A
minimum master clock frequency of 4.096 MHz is
required for the circuit to complete four encode
channels and four decode channels per frame. For
SSI operation a master clock frequency greater than
4.096 MHz and asynchronous, relative to the 8 kHz
frame, is allowed.
In ST-BUS mode, when ENB1 is brought low,
transparent transport of the ST-BUS "Basic Rate D-
and C-channels" is supported through the PCMi1
and PCMo1 pins. This allows a microprocessor
controlled device, connected to the PCMi/o1 pins, to
access the "D" and "C" channels of a transmission
device connected to the ADPCMi/o pins. When
ENB1 is brought high, the “D” and “C” channel
outputs are tristated. Basic Rate “D” and “C”
channels are not supported in LINEAR mode.(See
Figure 7.)
The PCM and ADPCM serial busses support both
ST-BUS and Synchronous Serial Interface (SSI)
operation. This allows serial data clock rates from
128 kHz to 4096 kHz, as well as compatibility with
Mitel’s standard Serial Telecom BUS (ST-BUS). For
ST-BUS operation, on chip channel counters provide
channel enable outputs as well as a 2048 kHz bit
clock output which may be used by down-stream
devices utilizing the SSI bus interface.
SSI Mode
During SSI operation the BCLK, ENB1 and ENB2/
F0od inputs become active. The C2o, EN1, and EN2
outputs are forced to a high-impedance state except
during LINEAR operation during which the EN1
output remains active. (See Figures 4, 5 & 6.)
Linear coded PCM is also supported. In this mode
the encoders compress, four 14-bit, two’s
complement
(S,S,S,12,...,1,0),
uniform
PCM
The SSI port is a serial data interface, including data
input and data output pins, a variable rate bit clock
input and two input strobes providing enables for
data transfers. There are three SSI I/O ports on the
Quad ADPCM; the PCMi/o1 PCM port, the PCMi/o2
PCM port, and the ADPCMi/o port. The two PCM
ports may transport 8-bit companded PCM or 16-bit
linear PCM. The alignment of the channels is
determined by the two input strobe signals ENB1
and ENB2/F0od. The bit clock (BCLK) and input
strobes (ENB1 and ENB2/F0od) are common for all
channels into four 4, 3 or 2 bit ADPCM channels.
Similarly, the decoder expands four 4, 3 or 2 bit
ADPCM channels into four 16-bit, two’s complement
(S,14,...,1,0), uniform PCM channels. The data rate
for both ST-BUS and SSI operation in this mode is
2048 kbit/s.
8-37
MT9126
Preliminary Information
three of the serial I/O ports. BCLK can be any
frequency between 128 kHz and 4096 kHz
synchronized to the input strobes. BCLK may be
discontinuous outside of the strobe boundaries
except when LINEAR=1. In LINEAR mode, BCLK
must be 2048 kHz and continuous for 64 cycles after
the ENB1 rising edge and for the duration of ENB2/
F0od.
16 kbit/s ADPCM Mode
When SEL is set to 0, the 8-bit PCM octets of the B1,
B2, B3 and B4 channels (PCMi1 and PCMi2) are
compressed into four 2-bit ADPCM words on
ADPCMo during the ENB1 timeslot in SSI mode and
during the B1 timeslot in ST-BUS mode. Similarily,
the four 2-bit ADPCM words on ADPCMi are
expanded into four 8-bit PCM octets (on PCMo1 and
PCMo2) during the ENB1/B1 timeslot. (See Figures 4
& 7.)
Mode Select Operation (MS1, MS2, MS3,
MS4, MS5, MS6)
When SEL is set to 1, The same conversion takes
place as described when SEL = 0 except that the
ENB2/B2 timeslots are utilized.
Mode Select pins MS1, MS2 and MS3 program
different bit rate ADPCM coding, bypass, algorithmic
reset and disable modes for all four encoder
functions simultaneously. When 24 kbit/s ADPCM
mode is selected bit 4 is unused while in 16 kb/s
ADPCM mode all ADPCM channels are packed
contiguously into one 8-bit octet. Mode Select pins
MS4, MS5 and MS6 operate in the same manner for
the four decode functions. The mode selects must be
set up according to the timing constraints illustrated
in Figures 16 and 17.
A-Law or µ-Law 8-bit PCM are received and
transmitted most significant bit first starting with b7
and ending with b0. ADPCM data are most
significant bit first starting with I1 and ending with I2.
ADPCM BYPASS (32 and 24 kbit/s)
In ADPCM bypass mode the B1 and B2 channel
ADPCM words are bypassed (with a two-frame
delay) to/from the ADPCM port and placed into the
most significant nibbles of the PCM1/2 port octets.
Note that the SEL pin performs no function for these
two modes (See Figures 6 & 9). LINEAR, FORMAT
and A/µ pins are ignored in bypass mode.
32 kbit/s ADPCM Mode
In 32 kbit/s ADPCM mode, the 8-bit PCM octets of
the B1, B2, B3 and B4 channels (PCMi1 and PCMi2)
are compressed into four 4-bit ADPCM words on
ADPCMo. Conversely, the 4-bit ADPCM words of the
B1, B2, B3 and B4 channels from ADPCMi are
expanded into four 8-bit PCM octets on PCMo1 and
PCMo2. The 8-bit PCM octets (A-Law or µ-Law) are
transferred most significant bit first starting with b7
and ending with b0. ADPCM words are transferred
most significant bit first starting with I1 and ending
with I4 (See Figures 4 & 7). Reference ITU-T G.726
for I-bit definitions.
In 32 kb/s ADPCM bypass mode, Bits 1 to 4 of the
B1, B2, B3 and B4 channels from PCMi1 and PCMi2
are transparently passed, with a two frame delay, to
the same channels on ADPCMo. In the same
manner, the B1, B2, B3 and B4 channels from
ADPCMi are transparently passed, with a two frame
delay, to the same channels on PCMo1 and PCMo2
pins. Bits 5 to 8 are don’t care. This feature allows
two voice terminals, which utilize ADPCM
transcoding, to communicate through a system
24 kbit/s ADPCM Mode
without
incurring
unnecessary
transcode
In 24 kbit/s mode PCM octets are transcoded into 3-
bit words rather than the 4-bit words utilized in 32
kbit/s ADPCM. This is useful in situations where
lower bandwidth transmission is required. Dynamic
operation of the mode select control pins will allow
switching from 32 kbit/s mode to 24 kbit/s mode on a
frame by frame basis. The 8 bit PCM octets (A-Law
or µ-Law) are transferred most significant bit first
starting with b7 and ending with b0. ADPCM words
are transferred most significant bit first starting with
I1 and ending with I3 (I4 becomes don’t care). (See
Figures 4 & 7.)
conversions. This arrangement allows byte-wide or
nibble-wide transport through a switching matrix.
24 kb/s ADPCM bypass mode is the same as 32 kb/s
mode bypass excepting that only bits 1 to 3 are
bypassed and bits 4 to 8 are don’t care.
ADPCM BYPASS (16 kbit/s)
When SEL is set to 0, only bits 1 and 2 of the B1, B2,
B3 and B4 PCM octets (on PCMi1 and PCMi2) are
bypassed, with a two frame delay, to the same
channels on ADPCMo during the ENB1 timeslot in
SSI mode and during the B1 timeslot in ST-BUS
8-38
Preliminary Information
MT9126
mode. Similarily, the four 2-bit ADPCM words on
ADPCMi are transparently bypassed, with a two
frame delay, to PCMo1 and PCMo2 during the ENB1
or B1 timeslot. Bits 3-8 are don’t care. (See Figures 6
& 9.)
When the decoders are programmed for PCMo1/2
disable (MS4 to MS6 set to 1) the PCMo1/2 outputs
are high impedance during the B Channel timeslots
and also, during ST-BUS operation, the D and C
channel timeslots according to the state of ENB1.
Therefore convergence is maintained. The encode
processing function and data I/O remain active.
When SEL is set to 1, the same bypass occurs as
described when SEL = 0 except that the ENB2 or B2
timeslots are utilized.
Whenever any combination of the encoders or
decoders are set to the disable mode the following
outputs remain active. A) ST-BUS mode: ENB2/
F0od, EN1, EN2 and C2o. Also the “D” and “C”
channels from PCMo1 and ADPCMo remain active if
ENB1 is set to 0. If ENB1 is brought high then
PCMo1 and ADPCMo are fully tri-stated. B) SSI
mode: When used in the 16-bit linear mode, only the
EN1 output remains active. For complete chip power
down see PWRDN.
LINEAR, FORMAT and A/µ pins are ignored in
bypass mode.
PCM BYPASS
When SEL is set to 0, the B1 and B2 PCM channels
on PCMi1 are transparently passed, with a two-
frame delay, to the same channels on the ADPCMo.
Simiarily, the two 8-bit words which are on ADPCMi
are transparently passed, with a two-frame delay, to
channels B1 and B2 of PCMo1 while PCMo2 is set
to a high-impedance state.(See Figures 6 & 9.)
Other Pin Controls
16 Bit Linear PCM
Setting the LINEAR pin to logic one causes the
device to change to 16-bit linear (uniform) PCM
transmission on the PCMi/o1 and PCMi/o2 ports.
The data rate for both ST-BUS and SSI operation in
this mode is 2048 kbit/s and all decode and encode
functions are affected by this pin. In SSI mode, the
input channel strobes ENB1 and ENB2/F0od remain
active for 8 cycles of BCLK for an ADPCM transfer.
The EN1 output is high for one BCLK period at the
When SEL is set to 1, the B3 and B4 channels on
PCMi2 are transparently passed, with a two frame
delay, to the same channels on ADPCMo. Similarily,
the two 8-bit words which are on ADPCMi are
transparently passed, with a two-frame delay, to
channels B3 and B4 of PCMo2. In this case PCMo1
is always high-impedance if ENB1 = 0. If ENB1 = 1
during ST-BUS operation then the D and C channels
are active on PCMo1.
th
end of the frame (i.e., during the 256 BCLK period).
In ST-BUS mode, the output strobes EN1 and ENB2/
F0od are adjusted to accommodate the required
PCM I/O streams. The EN1 output becomes a single
bit high true pulse during the last clock period of the
LINEAR, FORMAT and A/µ pins are ignored in
bypass mode.
th
Algorithm Reset Mode
frame (i.e., the 256 bit period) while ENB2/F0od
becomes a delayed, low true frame-pulse (F0od)
th
output occuring during the 64 bit period after the
EN1 rising edge.
While an algorithmic reset is asserted the device will
incrementally converge its internal variables to the
'Optional reset values' stated in G.726. Algorithmic
reset requires that the master clock (MCLK) and
frame pulse (ENB1/2 or F0i) remain active and that
the reset condition be valid for at least four frames.
Note that this is not a power down mode; see
PWRDN for this function.
Linear PCM on PCMi1 and PCMi2, are received as
14-bit, two’s complement data with three bits of sign
extension in the most significant positions (i.e.,
S,S,S,12,...1,0) for a total of 16 bits. The linear PCM
data transmitted from PCMo1 and PCmo2 are 16-bit,
two’s complement data with one sign bit in the most
significant position (i.e., S,14,13,...1,0)
ADPCMo & PCMo1/2 Disable
32 and 24 kbit/s ADPCM mode
When the encoders are programmed for ADPCMo
disable (MS1 to MS3 set to 1) the ADPCMo output is
set to a high impedance state and the internal
In 32 kbit/s and 24 kbit/s linear mode, the 16-bit
uniform PCM dual-octets of the B1, B2, B3 and B4
channels (from PCMi1 and PCMi2) are compressed
into four 4-bit words on ADPCMo. The four 4-bit
ADPCM words of the B1, B2, B3 and B4 channels
encode
function
remains
active.
Therefore
convergence is maintained. The decode processing
function and data I/O remain active.
8-39
MT9126
Preliminary Information
from ADPCMi are expanded into four 16-bit uniform
PCM dual-octets on PCMo1 and PCMo2. 16-bit
uniform PCM are received and transmitted most
significant bit first starting with b15 and ending with
b0. ADPCM data are transferred most significant bit
first starting with I1 and ending with I4 for 32 kbit/s
and ending with I3 for 24 kbit/s operation (i.e., I4 is
don’t care).(See Figures 5 & 8.)
and assuming that clocks are applied to the MCLK
and BCLK pins, the internal clocks will still not begin
to operate until the first frame alignment is detected
on the ENB1 pin for SSI mode or on the F0i pin for
ST-BUS mode. The C2o clock and EN1, EN2 pins
will not start operation until a valid frame pulse is
applied to the F0i pin. If the F0i pin remains low for
longer than 2 cycles of MCLK then the C2o pin will
top toggling and will stay low. If the F0i pin is held
high then the C2o pin will continue to operate. In ST-
BUS mode the EN1 and EN2 pins will stop toggling if
the frame pulse (F0i) is not applied every frame.
16 kbit/sADPCM mode
When SEL is set to 0, the four, 2-bit ADPCM words
are transmitted/received on ADPCMo/i during the
ENB1 time-slot in SSI mode and during the B1
timeslot in ST-BUS mode. When SEL is set to 1, the
four, 2-bit ADPCM words are transmitted/received
on ADPCMo/i during the ENB2 timeslot in SSI mode
and during the B2 timeslot in ST-BUS mode. (See
Figures 5 & 8.)
Master Clock (MCLK)
A minimum 4096 kHz master clock is required for
execution of the transcoding algorithm. The
algorithm requires 512 cycles of MCLK during one
frame for proper operation. For SSI operation this
input, at the MCLK pin, may be asynchronous with
the 8 kHz frame provided that the lowest frequency
and deviation due to clock jitter still meets the strobe
PCM Law Control (A/µ, FORMAT)
period requirement of a minimum of 512 t
-
C4P
The PCM companding/coding law invoked by the
transcoder is controlled via the A/µ and FORMAT
pins. ITU-T G.711 companding curves, µ-Law and
A-Law, are selected by the A/µ pin (0=µ-Law;
1=A-Law). Per sample, digital code assignment can
conform to ITU-T G.711 (when FORMAT=1) or to
Sign-Magnitude coding (when FORMAT=0). Table 1
illustrates these choices.
25%t
(see Figure 3). For example, a system
C4P
producing large jitter values can be accommodated
by running an over-speed MCLK that will ensure a
minimum 512 MCLK cycles per frame is obtained.
The minimum MCLK period is 61 nSec, which
translates to a maximum frequency of 16.384 MHz.
Extra MCLK cycles (>512/frame) are acceptable
since the transcoder is aligned by the appropriate
strobe signals each frame.
FORMAT
ENB1
MCLK
0
1
ITU-T (G.711)
Sign-
Magnitude
A/µ = 0 or 1
PCM Code
(A/µ = 0)
(A/µ = 1)
512 t
- 25%t
Minimum
C4P
C4P
+ Full Scale 1111 1111 1000 0000 1010 1010
Figure 3 - MCLK Minimum Requirement
+ Zero
- Zero
1000 0000 1111 1111 1101 0101
0000 0000 0111 1111 0101 0101
0111 1111 0000 0000 0010 1010
Bit Clock (BCLK)
- Full Scale
Table 1 - Companded PCM
For SSI operation the bit rate, for both ADPCM and
PCM ports, is determined by the clock input at BCLK.
BCLK must be eight periods in duration and
synchronous with the 8 kHz frame inputs at ENB1
and ENB2. Data is sampled at PCMi1/2 and at
ADPCMi concurrent with the falling edge of BCLK.
Data is available at PCMo1/2 and ADPCMo
concurrent with the rising edge of BCLK. BCLK may
be any rate between 128 kHz and 4096 kHz. For ST-
BUS operation BCLK is ignored (tie to VSS) and the
bit rate is internally set to 2048 kbit/s.
Power Down
Setting the PWRDN pin low will asynchronously
cause all internal operation to halt and the device to
go to a power down condition where no internal
clocks are running. Output pins C2o, EN1, EN2,
PCMo1, PCMo2 and ADPCMo and I/O pin F0od/
ENB2 are forced to
a
high-impedance state.
Following the reset (i.e., PWRDN pin brought high)
8-40
Preliminary Information
MT9126
BCLK
ENB1
ENB2/F0od
PCMi/o1
B1
B2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
B3
B4
PCMi/o2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
32 kb/s
1 2 3 4 1 2 3 4
1 2 3 4 1 2 3 4
B1
B2
B3
B4
ADPCM i/o
ADPCM i/o
1 2 3 x 1 2 3 x 1 2 3 x 1 2 3 x
24 kb/s
B1 B2 B3 B4
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
B1 B2 B3 B4
16 kb/s
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
SEL for 16 kb/s only
SEL = 0
SEL = 1
Figure 4 - SSI 8-Bit Companded PCM Relative Timing
Notes:
S = 3 bits sign extension
µ−Law is 13 bit 2’s complement data (bits 0 -12)
BCLK
... (2.048 MHz only)
A-Law is 12 bit 2’s complement data (shifted left once and utilizing
bits 1 - 12, bit 0 not defined)
EN1
ENB1
ENB2/F0od
PCMi/o1
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B1
B2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B4
B3
PCMi/o2
32 kb/s
1234 1234 1234 1234
1234 1234
B3 B4
B3
B1 B2
B4
ADPCM i/o
24 kb/s
123x 123x
123x 123x 123x 123x
12 12 12 12 12 12 12 12
B B B B B B B B
1 2 3 4 1 2 3 4
12 12 12 12
B B B B
ADPCMi/o
16 kb/s
1 2 3 4
SEL = 1
SEL = 0
SEL = 1
SEL for 16 kb/s only
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
Figure 5 - SSI 16-Bit Linear PCM Relative Timing
8-41
MT9126
Preliminary Information
BCLK
ENB1
ENB2/F0od
7
6
5
4
3
2
1 0
7
6
5
4
3
2
1
0
B1
B2
PCMi/o1
SEL = 0
SSI PCM
Bypass
7
2 1 0
6
5
4
3 2 1 0
7
6
5
4
3
ADPCMo/i
PCMi/o2
SEL = 1
B3
3
B4
4
7
6
5
4
2 1 0
7
6
5
3 2 1 0
1
2
3
4
x
x
x
x
1
2
3
4
x x x x
B1
B2
PCMi/o1
ADPCMo/i
PCMi/o2
32 kb/s using bits 1 2 3 4
24 kb/s where bit 4 = x
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
B3
B4
1
1
2
3
4
x
x
x
x
x
x
x
x
x
1
1
2
3
4
x
x
x
x
x
x
x
x
x
SSI ADPCM
Bypass
2
x
2
x
B2
B1
PCMi/o1
SEL = 0
SEL = 1
16 kb/s
ADPCM o/i
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
B1 B2 B3 B4 B1 B2 B3 B4
B3
B4
PCMi/o2
1
2
x
x
x
x
x
x
1 2 x x x x x x
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
Figure 6 - SSI PCM and ADPCM Bypass Relative Timing
8-42
Preliminary Information
MT9126
MCLK (C4)
F0i
ENB2/F0od
C2o (output)
EN1 (output)
EN2 (output)
PCMi1
0 1
0 1
7 6 5 4 3
C
2 1 0
7 6 5 4 3
B1
2 1 0
7 6 5 4
3 2 1 0
D
B2
7 6 5 4 3 2 1 0
7 6 5 4
3 2 1 0 7 6 5 4 3 2 1 0
PCMo1
7 6 5 4 3 2 1
0
0
7 6 5 4 3 2 1
0
0
PCMi2
transparent relay of D- and C- channels
when ENB1=0
B3
B4
7 6 5 4 3 2 1
7 6 5 4 3 2 1
PCMo2
ADPCMi
ADPCMo
0 1
7 6 5 4
3 2 1 0
3 2 1 0
1 2 3 4 1 2 3 4
1 2 3 4 1 2 3 4
B3
B1
B2
B4
D
C
1 2 3 4 1 2 3 4
1 2 3 4 1 2 3 4
0 1
7 6 5 4
SEL=0
SEL=1
32 kb/s is shown
In 24 kb/s, bit 4 becomes “X”
B1 B2 B3 B4
B1 B2 B3 B4
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
B1 B2 B3 B4
B1 B2 B3 B4
1 2 1 2 1
16 kb/s
SEL operates for
16 kb/s only
1 2 1 2 1
2 1 2
2 1 2
outputs=High impedance
inputs = don’t care
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Figure 7 - ST-BUS 8-bit Companded PCM Relative Timing
8-43
MT9126
Preliminary Information
MCLK (C4i)
F0i
C2o
(output)
EN1
F0od/ENB2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
PCMi/o1
PCMi/o2
B1
B2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B3
B4
1234 1234 1234 1234
ADPCMi/o
(32/24 kb/s)
B3
B1 B2
B4
bit 4 = x at 24 kbit/s
12 12 12 12 12 12 12 12
B B B B B B B B
ADPCMi/o
(16 kb/s)
1
2 3 4 1 2 3 4
SEL = 0
SEL operated for
16kb/s only
SEL = 1
outputs = High impedance
inputs = don’t care
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Note: D &C channels not supported in this mode.
Figure 8 - ST-BUS 16-bit Linear PCM Relative Timing
8-44
Preliminary Information
MT9126
MCLK
F0i
ENB2/F0od
C2o
EN1 (output)
EN2 (output)
0 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
PCMi1
D
C
B1
B2
P
C
M
0 1
7 6 5 4 3 2 1 0
SEL=0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
PCMo1
PCMi2
PCMo2
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
B
y
p
a
s
s
SEL=1
B3
B4
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
0 1
0 1
7 6 5 4 3 2 1 0
C
7 6 5 4 3 2 1 0
B1/B3
7 6 5 4 3 2 1 0
B2/B4
ADPCMi
ADPCMo
D
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
B1
B2
x x x 1 2 3 4
7 6 5 4 3 2 1 0
C
x
1 2 3 4
0
x x x x
x x x x
1
PCMi/o1
PCMi/o2
D
B3
B4
x x x x
A
D
P
C
M
1 2 3 4
1 2 3 4
7 6 5 4 3 2 1 0
C
1 2 3 4 1 2 3 4
B1 B2
1 2 3 4 1 2 3 4
B3 B4
0 1
ADPCMi/o
32 kb/s
24 kb/s bit 4 = X
D
B
y
p
a
s
s
SEL=0
SEL=1
D
C
B1 B2 B3 B4
1 2 1 2 1 2 1 2
B1 B2 B3 B4
1 2 1 2 1 2 1 2
ADPCMi/o
(16 kb/s)
7 6 5 4 3 2 1 0
0 1
0 1
B1
B2
PCMi/o1
PCMi/o2
1 2 x x x x x x
1 2 x x x x x x
7 6 5 4 3 2 1 0
C
D
B3
B4
1 2 x x x x x x
1 2 x x x x x x
outputs = High impedance
inputs = don’t care
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Figure 9 - ST-BUS PCM and ADPCM Bypass Relative Timing
8-45
MT9126
Preliminary Information
Processing Delay Through the Device
Applications
In order to accommodate variable rate PCM and
ADPCM interfaces, the serial input and output
streams require a complete frame to load internal
shift registers. Internal frame alignment of the
encoding/decoding functions are taken from either of
the F0i or ENB1 & ENB2 input strobes depending
upon the device operating mode (i.e., ST-BUS or
SSI). The encoding/decoding of all channels then
takes one frame to complete before the output
buffers are loaded. This results in a two frame
transcoding delay. The two frame delay also applies
to the D and C channels and to the PCM and
ADPCM bypass functions.(See Figure 10.)
Figure 11 depicts an ISDN line card utilizing the
MT8910 ’U’ interface transciever and MT9126
ADPCM transcoder. This central office application
implements the network end of a Pair-Gain system.
Figure 12 shows Mitel devices used to construct the
remote Pair-Gain loop terminator.
Figure 13 depicts an ADPCM to linear PCM
converter for applications where further, value
added, functions are being performed via digital
signal processor. Access to linear coded PCM
reduces the overhead of the DSP by removing the
need for a companded to linear conversion. The
linear PCM capability of the ADPCM transcoder in
conjunction with the frame alignment signal EN1
allows direct connection to the serial port of both
Motorola and Texas Instruments Digital Signal
Processors. Daisy-chaining via the delayed frame
strobe output ensures that the ADPCM array is
distributed over the complete 2048 kbit bandwidth. If
the DSP has a second serial port then access to the
processed PCM can be had directly. For processors
with only one serial port the MT8920 connected to
the DSP parallel port will provide serial access by
parallel to serial conversion. The same daisy-
chained arrangement of Quad ADPCM transcoders
will provide a general system resource for PCM-
ADPCM conversion by setting the device to non-
linear operation.
Note: When changing the relative positions of the
ENB1 and ENB2 strobes, precaution must be taken
to ensure that two conditions are met. They are:
1) There must be at least 512 master clock cycles
between consecutive rising edges of ENB1. This
condition also holds true for ENB2.
2) The ENB1 strobe must alternate with the ENB2
strobe.
Violation of these requirements may cause noise on
the output channels.
frame n-1
frame n
frame n+1
PCMi1/2
ADPCMo
Byte "x"
PCM Byte "X" processed according
to MSn input states latched during
frame n
ADPCM Word "X" output from
PCM Byte "X" latched into device
device during frame n+1
during frame n-1
Word "x"
ENB1 or ENB2
F0i
MS1 or 4
32 kb/s
24 kb/s
32 kb/s
Where MS2, 3, 5, 6 = 0
This diagram shows the conversion sequence from PCM to ADPCM. The same pipelining occurs in the
reverse ADPCM to PCM direction.
Total delay from data input to data output = 2 frames.
Figure 10 - Data Throughput
8-46
Preliminary Information
MT9126
F0i
8910
MT
MT9126
PCMi1
PCMo1
LIN+
LIN-
T
2
F0i
F0b
LOUT-
R
MCLK
C4b
LOUT+
PCMi2
PCMo2
ADPCMi
ADPCMo
DSTo
DSTi
F0od
C4i
F0od
1
8
T R
R
T
F0i
F0i
F0i
F0od
F0od
F0od
C4i
F0i
8
2
1
MT8980
DX
F0i
ST1i
ST1o
C4i
ST2o
ST2i
Figure 11 - ISDN Line Card with 32 kbit/s ADPCM
8-47
MT9126
Preliminary Information
8-48
Preliminary Information
MT9126
System Frame pulse
System 4.096MHz
MT9126
C2o
F0i
MCLK (C4i)
PCMo1
PCMo2
ADPCMo
ADPCMi
PCMi1
PCMi2
+5v
+5v
+5v
LINEAR
EN1 ENB2/F0od
MT8920
MT9126
CLKR
CLKX
C2o
F0i
MCLK (C4i)
PCMo1
PCMo2
ADPCMo
ADPCMi
S
T
PCMi1
PCmi2
DR
DX
TI DSP
P
A
LINEAR
EN1 ENB2/F0od
MT9126
C2o
F0i
MCLK (C4i)
PCMo1
PCmo2
ADPCMo
ADPCMi
PCMi1
PCMi2
LINEAR
2nd serial port
if available
STPA
ST-BUS
port
EN1 ENB2/F0od
MT9126
C2o
F0i
MCLK (C4i)
PCMo1
PCMo2
ADPCMo
ADPCMi
PCMi1
PCMi2
+5v
LINEAR
EN1 ENB2/F0od
ADPCM BUS
Figure 13 - ST-BUS to DSP Platform
8-49
MT9126
Preliminary Information
Absolute Maximum Ratings*
Parameter
Symbol
-V
Min
Max
Units
1
2
3
4
5
Supply Voltage
V
-0.3
7.0
V
V
DD SS
Voltage on any I/O pin
Continuous Current on any I/O pin
Storage Temperature
V | V
V
-0.3
V
+ 0.3
DD
i
o
SS
I | I
±20
150
500
mA
°C
i
o
T
-65
ST
Package Power Dissipation
P
mW
D
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Supply Voltage
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
V
4.5
2.4
5.0
5.5
V
V
DD
TTL Input High Voltage
TTL Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Operating Temperature
V
400mV noise margin
400mV noise margin
DD
V
0.4
V
SS
4.5
V
V
DD
V
0.5
V
SS
T
-40
+85
°C
A
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Supply Current
Sym
Min
Typ
Max
Units
Test Conditions
1
I
I
100
µA
mA
PWRDN = 0
PWRDN = 1, clocks active
CC
DD
5
2
3
4
5
Input HIGH voltage (TTL)
Input LOW voltage (TTL)
Input HIGH voltage (CMOS)
Input LOW voltage (CMOS)
V
2.0
3.5
V
V
V
V
IH
V
0.8
IL
M
C
L
V
IHC
V
1.5
10
ILC
K
6
7
Input leakage current
High level output voltage
Low level output voltage
High impedance leakage
Output capacitance
I /I
0.1
µA
V
V =V to V
IN SS
IH IL
DD
DD
V
2.4
I
I
=5.0mA
=5.0mA
OH
OL
OL
8
V
0.4
10
V
OL
OZ
9
I
1
10
8
µA
pF
pF
V =V to V
IN SS
10
11
12
C
o
Input capacitance
C
i
P
Positive Threshold Voltage
Hysteresis
Negative Threshold Voltage
V+
V
V-
3.7
V
V
V
W
R
D
N
1.0
H
1.3
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* DC Electrical Characteristics are over recommended temperature and supply voltage.
8-50
Preliminary Information
MT9126
AC Electrical Characteristics† - Serial PCM/ADPCM Interfaces (see Figure 14)
Voltages are with respect to ground (VSS) unless otherwise stated.
†
Characteristics
BCLK Clock High
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
t
80
80
ns
ns
ns
ns
BCH
BCLK Clock Low
BCLK Period
t
BCL
t
200
7900
BCP
Data Output Delay (excluding first
bit)
60
60
C =150pF//R =1K
L L
t
DD
5
6
Output Active to High Z
Strobe Signal Setup
t
ns
ns
C =150pF//R =1K
L L
AHZ
t
80
80
t
t
-
-
SSS
BCL
80
7
Strobe Signal Hold
t
ns
SSH
BCL
80
8
9
Data Input Setup
Data Input Hold
t
50
50
ns
ns
ns
ns
ns
%
DIS
t
DIH
10 Strobe to Data Delay (first bit)
11 F0i Setup
t
60
122
122
50
C =150pF//R =1K
L L
SD
t
50
50
40
150
150
60
F0iS
F0iH
12 F0i Hold
t
13 MCLK (C4i) duty cycle
t /t
H L
x100
14 F0od Delay
t
60
ns
ns
ns
ns
ns
ns
C =150pF//R =1K
L L
DFD
15 F0od Pulse Width
16 MCLK (C4i) period
17 Data Output delay
18 Data in Hold time
19 Data in Setup time
t
244
C =150pF//R =1K
L L
DFW
t
61
244.2
95
C4P
DSD
DSH
t
C =150pF//R =1K
L L
t
50
50
t
DSS
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
8-51
MT9126
Preliminary Information
tBCH
tBCP
tBCL
VIH
BCLK
VIL
tSSH
S
S
I
tSSS
ENB1
or
ENB2
VIH
VIL
tDIS
tDIH
VIH
VIL
PCMi/ADPCMi
PCMo/ADPCMo
tDSS
tAHZ
tDD
tSD
tDSH
VOH
VOL
tDSD
tH
VIHC
VILC
S
MCLK
T
-
tC4P
B
U
tL
tF0iH
VIH
VIL
S
F0i
tDFD
tF0iS
tDFD
F0od
VOH
VOL
tDFW
Figure 14 - Serial Port Timing
AC Electrical Characteristics† - ST-BUS C2o Conversion
Voltages are with respect to ground (VSS) unless otherwise stated.
†
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
Delay MCLK falling to C2o rising
Delay MCLK falling to Enable
t
100
100
ns
ns
150pF//1K Load
150pF//1K Load
D1
t
D2
VIH
VIL
F0i
VIHC
VILC
MCLK
(C4i)
tD1
VOH
VOL
C2o
VOH
VOL
EN1
EN2
tD2
tD2
Figure 15 - ST-BUS Timing for External Signal Generation
8-52
Preliminary Information
MT9126
AC Electrical Characteristics† - Mode Select Timing (see Figures 16 & 17)
Voltages are with respect to ground (VSS) unless otherwise stated.
†
Characteristics
Mode Select Setup
Mode Select Hold
Sym
Min
Typ
Max
Units
Test Conditions
MCLK=4096 kHz
1
2
t
500
500
ns
ns
SU
t
HOLD
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
t
SU
HOLD
MS1
to
MS6
VIH
VIL
VIH
ENB1 (input)
Figure 16 - SSI Mode Select Set-up and Hold Timing
t
t
HOLD
SU
VIH
VIL
MS1
to
MS6
MCLK
F0i
Refer to Figure 14 for ST-BUS F0i timing.
Figure 17 - ST-BUS Mode Select Set-up and Hold Timing
8-53
MT9126
Preliminary Information
Notes:
8-54
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