MH1Q [MITEL]
Quadrature Downconverter; 正交下变频器
| 型号： | MH1Q |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | Quadrature Downconverter |
| 文件： | 总20页 (文件大小：569K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SL1711
Quadrature Downconverter
Preliminary Information
Supersedes November 1996 version, DS4032 - 1.6
DS4032 - 4.0 October 1997
The SL1711 is a quadrature downconverter, intended
primarily for application in professional and consumer digital
satellite tuners.
The device contains all elements necessary, with the
exception of external local oscillator tank to form a complete
system operating at standard satellite receiver intermediate
frequencies. It is intended for use with external carrier
recovery.
1
16
VCCB
AGC
IOUT
VEEA
IFINB
IFIN
VCODIS
VCO B
VCO A
VEEB
The device includes a low noise RF input amplifier, a
reference VCO with prescaler output buffer and In-phase and
Quadraturemixerswithbasebandbufferamplifierscontaining
AGC gain control.
IVCCA
QOUT
VEEC
PSCAL
PSCALB
VCCC
The SL1711 is optimised to drive a dual ADC converter
such as the VP216.
MH16
The SL1711 utilises a power MP package, whereas the
SL1711B variant uses a standard MP16 plastic package and
features a revised operating temperature.
FEATURES
1
16
VCCB
AGC
IOUT
VEEA
IFINB
IFIN
■ Single chip system for wideband quadrature
VCODIS
VCO B
VCO A
VEEB
downconversion
■ Compatible with all standard high IF frequencies
IVCCA
QOUT
VEEC
PSCAL
PSCALB
VCCC
■ Excellent gain and phase match up to 30MHz
baseband
■ High output referred linearity for low distortion and
multi channel application
MP16
■ Simple low component application
Fig. 1 Pin allocation
■ Fully balanced low radiation design with fully
integrated quadrature generation
ORDERING INFORMATION
SL1711/KG/MH1P (Sticks)
■ High operating input sensitivity
■ On-board AGC facility
SL1711/KG/MH1Q (Tape and Reel)
SL1711B/KG/MP1S (Sticks)
■ On chip oscillator for varactor tuning or SAW
resonator operation
SL1711B/KG/MP1T (Tape and Reel)
■ ESD protection (Normal ESD handling procedures
should be observed)
APPLICATIONS
■ Satellite receiver systems
■ Data communications systems
■ Cable systems
SL1711
QUICK REFERENCE DATA
Characteristic
Value
17
Units
dB
Input noise figure, DSB
Maximum conversion gain
Minimum conversion gain
IP32T output referred
44
dB
28
dB
+8
dBV
Vp-p
dB
Output clip voltage
1.5
Gain match up to 22MHz
Gain match up to 30MHz
Phase match up to 30MHz
Gain flatness up to 30MHz
VCO phase noise, SSB @ 10kHz offset
Prescaler division ratio
Prescaler output swing
± 0.3
± 0.5
± 1.5
± 0.5
- 96
32
dB
deg
dB
dBc/Hz
1.6
Vp-p
AGC
IFIN
I OUT
AGC
IFINB
Q OUT
AGC
VCODIS
0 deg
90 deg
PSCAL
VCOA
VCOB
Quadrature
generator
÷32
LO
PSCALB
Fig. 2 SL1711 block diagram
2
SL1711
FUNCTIONAL DESCRIPTION
The SL1711 is a wideband quadrature downconverter,
optimised for application in both professional and consumer
digital satellite receiver systems and requiring a minimum
external component count. It contains all the elements
required for construction of a quadrature demodulator, with
the exception of tank circuit for the local oscillator.
A block diagram is shown in Fig. 2.
The SL1711 oscillator can be used with either a varator
tuned tank circuit or with a SAW resonator. Both
configurations are described in the Application Notes section
of this Data Sheet.
The mixer outputs are fed to balanced baseband AGC
amplifierstages,whichprovideforaminimumof16dBofAGC
control. The typical AGC characteristic is shown in Fig. 4.
These amplifiers then feed a low output impedance true
differential to single-ended converter output stage. In normal
application the output can be either directly AC coupled to the
ADC converter such as the VP216, which will generally have
a high input impedance, or to drive an anti alias filter. In this
later case the maximum load presented to the SL1711 must
not exceed a parallel combination of 1KΩ and 20pF. The
typical baseband output impedance is contained in Fig. 5.
It is recommended that the device is operated with an
output amplitude of 760mV under lock conditions.
A typical digital satellite tuner application from tuner input
to data transport stream is shown in Fig. 13
In normal application the second satellite IF frequency of
typically 402.75 or 479.5 MHz is fed from the tuner SAW filter
to the RF preamplifier, which is optimised for impedance
match and signal handling. The amplifier output signal is then
split into two balanced channels to drive the In-phase and
Quadrature mixers. The typical RF input impedance is shown
in Fig. 3
In-phase and Quadrature LO signals for the mixers are
derived from the on board local oscillator, which uses an
external varactor tuned resonant network and is optimised for
low phase noise. The VCO also drives an on board divide by
32prescalerwhoseoutputscanbeusedfordrivinganexternal
PLL control loop for the VCO, where the PLL loop is contained
within the QPSK demodulator, for example the VP305. For
optimum performance in the varactor tuned application the
VCOshouldbefullysymmetric. TheVCOhasadisablefacility
by grounding pin 15, VCODIS; in normal applications this pin
is pulled to Vcc via a 4K7 resistor.
Under transient conditions the output should not exceed
the clipping voltage.
Input and output interface circuitry is contained in Fig. 6.
Thetypicalkeyperformancefiguresat480MHzIF,5VVcc,
1kΩ loadand25degCambientarecontainedintableheaded
'QUICK REFERENCE DATA'. With SAWR oscillator
application the gain and phase match performance will
typically exceed these numbers.
3
SL1711
Marker 1 480MHz
Zreal = 96Ω
Zimag = 54Ω
+j1
+j0.5
+j2
+j0.2
0.2
0.5
1
0
X
-j0.2
-j0.5
-j2
START 350 MHz
STOP 650 MHz
-j1
Fig.3 Typical RF input impedance
4
SL1711
55
50
45
40
35
30
25
20
15
AGC CONTROL VOLTS
Fig.4 Typical AGC characteristic
j1
+j0.5
+j2
+j0.2
X
3
2
X
0.5
1
0
0.2
X
1
-j0.2
1
2
3
1MHz
15MHz
30MHz
-j0.5
-j2
-j1
Fig. 5 Typical baseband output impedance
5
SL1711
VCO
VCO
IFIN
IFINB
2x20k
Vref
IF Input
VCO
Vcc
O/P
55k
VCODIS
Vref
I & Q baseband output
VCO disable input
Vcc
O/P
50k
AGC
Vref
Prescaler outputs
AGC input
Fig. 6 I/O port peripheral circuitry
6
SL1711
Fg.SL71sevlutinboard
7
SL1711
Fig.8
Fig.9
8
SL1711
Fg0.L71I&QdcvwihSAWesnator
9
SL1711
Fig. 11
Fig. 12
10
SL1711
APPLICATION NOTES
These application notes should be read in conjunction with
circuit diagrams contained in Fig. 7 and 10, and a
recommended front end tuner solution contained in Fig. 13.
These boards have been designed to demonstrate
performance and to allow for initial evaluation of the SL1711.
These enable the VCO frequency to be synthesised by a PLL
frequency synthesiser; on the demo board an SP5611 is used
for this function however in a real application this function will
be provided by the QPSK demodulator function contained in
for example the VP305
It is recommended that the prescaler outputs are loaded
symmetrically to balance radiation effects.
Varator Tuned Oscillator
Refer to Fig. 7 circuit diagram and Figs. 11 and 12 PCB
layout.
Saw Resonator Oscillator
This application uses a synthesised VCO with a tuning
range of 460 MHz to 500 MHz. The surface mount inductor L1
is 12 nH. The VCO frequency is controlled by the SP5611
synthesiserwhichisprogrammedviaanI2Cbus. TheRFinput
to the synthesiser is from the SL1711 prescaler outputs
coupled via RF inductors L3 and L4.
For functional checking the VCO can be tuned by
physically shorting the base of transistor T3 to ground and
then adjusting the +30 volt supply to tune the VCO. Under
these conditions, due to the unlocked state of the LO, the
board WILL NOT BE representative of locked gain and phase
match or phase noise performance.
In real applications such the VCO control voltage will be
provided by the QPSK demodulator circuit, such as the
VP305. This circuit provides a line voltage to align the
reference LO in the 1711 in both frequency and phase to the
centre of the modulation bandwidth, normally 402.75 or 479.5
MHz.
Refer to Fig. 10 circuit diagram and Figs 11 and 12 PCB
layout.
In the standard application the oscillator uses a varactor
diode tuned tank circuit which allows fine tuning of the
oscillator frequency via a voltage control line. This control
voltage is usually derived from the QPSK/FEC decoder
VP305/VP306
Certain applications do not require this fine tune facility so
afixedfrequencyapplicationusingaSAWresonatorhasbeen
developed. In this application the frequency of the oscillator is
determined by the SAW resonator. The SAW is AC coupled
into the VCO pins of the device pins 13 and 14 via 100pF
coupling capacitors.
The SAW resonator used in this application is a ;
Murata Part No SAR479.45MB10X200
Prescaler Outputs (SAWR tuned VCO)
As in all feedback loops the bandwidth of the varactor line
must be optimised for the symbol rate of the received
modulation.
It is recommended for optimum performance that the VCO
application is implemented symmetrically, in presented drive
and impedance to the VCO ports, as demonstrated in the
evaluation schematic and PCB.
In the recommended application the varactor diodes are
referenced to the VCO port DC bias voltages. This limits the
minimum tuning voltage on the varactor line to 3V. If lower
tuning voltage is required the tank can be AC coupled to the
VCO ports by 390pF capacitor and a DC reference voltage for
the varactor diodes applied by centre tapping the tank
inductors. NB the varactor diodes require a minimum of 1V
reverse bias for correct operation.
The VCO frequency divided by 32 is available at the
differential prescaler outputs, pins 10 and 11. Normally these
outputswillnotberequiredsincethederotationandfinetuning
required will be processed by the QPSK demodulator.
However these frequencies could be used if required for other
system reference frequencies or clocks.
If used it is recommended that the prescaler outputs are
loaded symmetrically to balance radiation effects.
VCO Disable
The on-chip oscillator can be disabled by connecting
VCODIS, pin 15, to ground and enabled by connecting to Vcc
via a 4k7 Ω pull up resistor.
In real applications the maximum tuning range required for
the VCO will be determined by the required lock range of the
tuner and the manufacturing tolerance of the tank, assuming
the quadrature downconverter section will be alignment free.
This tuning range will be typically be much smaller than the
demonstration board, which will consequently improve the
VCO phase noise performance.
This application can be ported direct to real system
implementations. NormalgoodRFpracticemustbeappliedto
the layout implementation.
AGC
TheAGCfacilitycanbeusedtocontroltheconversiongain
of the SL1711.
On the demonstration boards the conversion gain is
adjusted by means of a potentiometer, which is set to 2.5V so
giving a conversion gain of 38 dB. The voltage adjustment
range for the AGC is approximately 1.5 to 3.5 V.
It is important that the AGC voltage minimum does not give
a conversion gain of greater than 44dBs otherwise the
channel amplitude match may be degraded. In real
applications the AGC can be either set at a fixed control
voltage or controlled by means of the AGC control signal from
the QPSK demodulator dependant on the overall dynamic
range requirement of the tuner and it’s gain distribution.
Prescaler Outputs (varactor tuned VCO)
The VCO frequency divided by 32 is available at the
differential prescaler outputs, pins 10 and 11.
11
SL1711
I & Q baseband outputs
I2C Bus connections
The board is provided with an RJ11 I2C bus connector
which feeds directly to the SP5611 synthesiser.
The SL1711 offers a greatly improved drive capability over
the SL1710 and as such is much less sensitive to the load
conditions.
It is still important however to carefully balance the loads
presented to the SL1711 to ensure no differential gain or
phasedegradationisintroducedbytheloadcircuits, whichwill
also include effects due to track striplines etc.
This connects to a standard 6-way connector cable which
is supplied with the I2C/3-wire bus interface box.
Input and Output connections
For demonstration purposes the output is unsuitable for
connection via co-axial cables to standard test equipment,
where such equipment is normally 50 Ω or highly capacitive.
To overcome this problem the outputs of the SL1711 are
therefore buffered through emitter followers which are
optimisedtodrive50Ω loadswithoutappreciabledegradation
in the SL1711 performance. These buffer stages are
selectable so enabling the outputs to be loaded directly for
interfacing direct with an ADC via a low capacitive link.
In most applications the SL1711 will normally interface
direct into the ADC converter such as the VP216, which will
present a >1 kΩ low capacitive load, though it can interface
with lower impedances if desired.
The board is provided with the following connectors:
A) IF I/P SMA connector SK1 which is AC coupled to the
RF input of the SL1711.
B) I CH OUT SK2 and Q CH OUT (SK3) which provide
either a buffered or direct baseband output signal from
the SL1711 (depending on which way the links LK1
and LK2 are set). The output buffers should be used
when driving 50Ω test equipment or co-axial lines.
The output is optimised for typical drive levels of 760
mVp-p and the onset of clipping is typically > 1.5V.
Links and Switches
The board is provided with the following:
VCO DISABLE switch
Care must be taken with system design to ensure that the
I and Q baseband output signals never exceed 1.2V pk-pk.
Any gross distortion in the output waveform caused by
overdriving the output stages will compromise the system
performance.
This disables the VCO of the SL1711. It does NOT power
down the chip.
Device performance characteristics can only be
guaranteed if the device is operated below the onset of
clipping.
AGC ADJUST potentiometer
The potentiometer sets the AGC input voltage of the
SL1711 which controls the gain of the chip. TP1 is provided as
a means of monitoring the AGC voltage.
SL1711 Evaluation Board
This board has been created to show the operation of the
SL1711 I/Q downconverter.
LK1 and LK2
It does not attempt to simulate a real system, since in
practice the 479.5MHz IF oscillator on the SL1711and the
60MHz clock on the subsequent ADC would be controlled via
the baseband IQ demodulator chip such as the VP305 which
follows the dual channel ADC. For simplicity, the VCO is
locked using Mitel Semiconductor SP5611 synthesiser, con-
trolled via an I2C bus.
These are links which may be placed either vertically or
horizontally to connect the outputs of the SL1711 either
directly or via buffers to the SMA output connectors of the
board.
If the links are placed vertically 1-2 and 3- the outputs are
connected directly.
If the links are placed horizontally 1-3 and 2- the ouputs are
connected via buffers.
For full evaluation, 30V and 5V supplies are necessary.
Supplies
The board must be provided with the following supplies:
A) 5V for the SL1711 and SP5611 and 30V for the
varactor line.
The supply connector is a 3 pin 0.1" pitch pin header. The
centre pin of the connector is GND.
Outputs driven into hard clipping can exhibit amplitude
decline.AGCloopsshouldbedesignedtotakeaccountofthis.
12
SL1711
SL1711 Operation
Programming of Synthesisers
The SL1711 will mix an IF input with its own local oscillator.
This is controlled as above via a SP5611 synthesiser.
Normally the VCO will be set to the same frequency as the
IF input, and the signal mixed directly down to baseband.
Alternatively, a CW RF source may be fed into the input of
the SL1711 which is deliberately offset from the VCO. By
varying the offset from 0-20MHz and monitoring the I and Q
channel baseband outputs, the flatness response of the chip/
output filter can be measured.
A SP5611 synthesiser is used to set the frequency of the
SL1711 VCO 480MHz. Since the SL1711 incorporates a
divide by 32 the synthesised frequency that the SP5611 must
be programmed to is 480/32=15MHz.
Example
a) To program the SL1711 to 480MHz.
I2C Byte
Hex Code
The SL1711 oscillator may also be disabled by setting the
ON-VCO-OFF switch to the OFF position.
An AGC voltage adjust pot marked AGC ADJUST is
provided, together with a test point.
Byte 1 (address)
C2
00
F0
CE
00
Byte 2 (programmable divider 8 MSBs)
Byte 3 (programmable divider 8 LSBs)
Byte 4 (control data)
Byte 5 (port data)
Measurement of Gain and Phase Match.
a) Synthesise the required frequency 480MHz is used in the
example above.
C2 is the address byte byte 1.
0F00 is the programmable divider information bytes 2 and 3.
CE is the control data information byte 4.
b) Connect an RF signal generator to the input.
c)Input a signal which should give an output of approx 0dBm
(0.707V p-p), in combination with the appropriate AGC set-
ting.
**Note - the programmable divider information should be
set to program 480MHz /32 = 15MHz since the SL1711
provides a divide by 32 prescaler output rather than the VCO
carrier frequency.
It is not possible to program the VCO to 479.5MHz when
using a 7.8125kHz phase comparator frequency. The mini-
mum step size is 7.8125kHz x 8 (RF prescaler inside SP5611)
x 32 (SL1711 output prescaler) = 2MHz.
If the reference divider is set to 1024 mode3.90625kHz
phase comparator frequency, the minimum step size will be
1MHz.
This may be achieved by programming the control byte to
CC and modifying the programmable divider information for
the new step size.
d) Connect a vector voltmeter to the BUFFERED outputs
when using 50Ω inputs. When using high impedance probes,
the direct outputs may be used. Selection of outputs is via the
on board U links.
e) CALIBRATE the vector voltmeter and the leads to be used.
The calibration should be performed at the chosen baseband
frequency and level for maximum accuracy.
f) Vary the RF input frequency either side of the LO and note
the relative I and Q gain and phase reading.
If you experience any difficulties with this board, or require
further help, please contact Robert Marsh on 01793 518234
or Fred Herman on 01793 518423
13
SL1711
0.22MHz
0.7V pk-pk
RF I/P
from
LNB
480MHz IF
Data
Stream
ADC
I
I/P
Filter
QPSK
Demod & FEC
(VP305)
IF
Filter
TUNER
(SL2015)
2x6 bit, 90MS/s
(VP216)
(SL1711)
AGC
Q
950MHz
2.15GHz
VCO I/p
AGC
Tank
circuit
TANK
VCO
Loop/line
Filters
AGC
PLL SYNTH. options
(SP5658) (3w bus)
2
(SP5055) (I C bus)
2
(SP5655) (I C bus)
RF TUNER
MODULE
2
(SP5659) (I C bus)
Fig.13 Example digital front end architecture
Note: All ICs shown in Fig. 13 are available from Mitel Semiconductor.
14
SL1711
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated)
o
o
T
= 0 C to 85 C,* V = 0V, Vcc = 4.75 to 5.25 V, Fif = 479.5 MHz, IF bandwidth ± 22 MHz, output amplitude -11dBV
ee
amb
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage unless otherwise stated.
Characteristic
Supply voltage
Supply current
IF input operating
frequency (1)
Pin
6,9,16
6,9,16
4, 5
Min
Typ
Max
5.25
125
550
Units
V
Conditions
4.75
109
mA
350
12
MHz
IF input impedance
4, 5
4, 5
4, 5
75
17
Ω
Over specified frequency
operating range, see Fig. 6.
Over specified frequency
operating range, see Fig. 6.
Maximum gain setting
Input return loss
dB
Input noise figure, DSB
Variation in NF with gain
setting
19
1
dB
dB/dB
VCO operation range
350
550
-85
MHz
Centre frequency and tuning
range determined by
application.
VCO phase noise, SSB
@ 10kHz offset
VCO Vcc sensitivity
VCO temperature
stability
96
dBc/Hz
Varactor tuned, determined
by application.
2E3
100
ppm/V
Free running
ppm/°C
Uncompensated
Prescaler output swing
Prescaler output duty
cycle
10, 11
10, 11
1.2
40
1.6
50
Vp-p
%
60
Conversion gain for
AGC setting of;
1.5V
See Fig. 4
44
dB
Terminated voltage
conversion gain from 50Ω
source to 1kΩ load
2.5V
3.5V
38
dB
dB
µA
dB
dB
deg
dB
dB
dB
28
100
±1
AGC input current
I Q gain match
1
All AGC settings
See Note 3.
±0.3
±0.5
±1.5
±0.3
±0.5
-29
I Q gain match
±1
See Note 4.
I Q phase match
I & Q channel in band ripple
I & Q channel in band ripple
I Q crosstalk
±3
See Note 4.
±1
see Note 3.
±1
See Note 4.
-20
See Note 4 and Note 2 for
derivation of cross modulation
15
SL1711
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise stated)
o
o
T
= 0 C to 85 C,* V = 0V, Vcc = 4.75 to 5.25 V, Fif = 479.5 MHz, IF bandwidth +- 22 MHz
amb ee
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage unless otherwise stated.
Characteristic
Pin
Min
Typ
Max
Units
Conditions
I & Q baseband output
impedance
2,7
8
20
Ω
See note (5), and Fig. 5.
I & Q baseband output
clipping level
2, 7
1.2
+3
1.5
+9
Vp-p
dBV
See note(6), into 1KΩ load up to
22MHz baseband
IP32T, output referred
2 input carriers at -39 dBV
within IF bandwidth of ±22MHz
AGC set to give composite
output of -11 dBV, IM3 tone
within baseband bandwidth
2 input carriers within IF
IM32T output referred
-40
-30
dBc
bandwidth of ±22MHz, AGC
set to give composite output
of -11 dBV, IM3 tone within
baseband bandwidth
All prescaler and other
spurs in I & Q baseband
output.
dBc
dBc
0.1 - 100MHz, referred to output
amplitude of - 11 dBV.
Power supply rejection
20
Attenuation Vcc to I & Q outputs,
over 0-500kHz
Notes: 1.
2.
Performance not guaranteed over full specified IF input operating range
I Q crosstalk is determined from the gain and phase match by the following formula
Crosstalk = 20* Log (tan(phase error + Atan (1+amplitude imbalance) -45°))
Over specified gain dynamic, 1kΩ load up to 22MHz baseband
Over specified gain dynamic range, 1kΩ load up to 30MHz baseband
Baseband bandwidth 0.1 to 22MHz
3.
4.
5.
6.
The device should not be operated beyond the point of output clipping. The quality and amplitude of the
baseband output signals cannot be guaranteed once this level has been exceeded.
7.
8.
* Operating temperature range for the SL1711B is 0°C to 70°C. This applies to applications featuring a double
sided copper board. For other applications not using such a board, the maximum operating
temperature may be reduced.
The above device characteristics are guaranteed provided the output is maintained below the onset of clipping.
16
SL1711
ABSOLUTE MAXIMUM RATINGS
All voltages are reffered to Vee at 0V
Characteristics
Min
-0.3
Max
7
Units
V
Conditions
Supply voltage, Vcc
IFFIN &IFINB input voltage
IFIN & IFINB input DC offset
IOUT & QOUT DC offset
AGC DC offset
2.5
Vp-p
V
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-55
Vcc+0.3
Vcc+0.3
Vcc+0.3
Vcc+0.3
Vcc+0.3
Vcc+0.3
125
V
V
VCO1 & 2 DC offset
V
VCODDIS DC offset
V
PSCAL & PSCALB DC offset
Storage temperature
°C
°C
Junction temperature
PSOP16 package thermal
resistance, chip to ambient
PSOP16 package thermal
resitance, chip to case
MP16 package thermal resistance
chip to Ambient
150
TBA
°C/W
TBA
81
°C/W
°C/W
°C/W
MP16 package thermal resistance
chip to case
28
Power consumption at 5.25V
ESD protection
657
mW
kV
2
Mil std 883B method 3015 cat 1
ADDITIONAL INFORMATION REGARDING THE PSOP PACKAGE.
The following information should be noted when using the PSOP package fitted to the SL1711.
(a)
(b)
This package uses the standard SOIC 16 footprint.
There is no need to make a thermal connection between the package and the board. If such a connection is made using
a thermal adhesive this will enhance the long term reliability of the product by reducing the junction temperature.
(c) The heatsink that is evident on the base of the package is solderable.
(d) There is no direct electrical connection between any of the device pins and the metal heatsinkslug. However if the
heatsink is to be electrically connected to the PCB these connections should be confined to the ground plane.
17
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