MH1RT [ATMEL]
Rad Hard 1.6M Used Gates 0.35 μm CMOS Sea of Gates/ Embedded Array; 抗辐射1.6M用盖茨的盖茨0.35微米CMOS海/嵌入式阵列
| 型号： | MH1RT |
| 厂家： | 
ATMEL |
| 描述： | Rad Hard 1.6M Used Gates 0.35 μm CMOS Sea of Gates/ Embedded Array |
| 文件： | 总20页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
•
•
•
•
Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries
High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 (nominal)
System Level Integration Technology Cores on Request
Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC
I/O Interfaces:
– 5V Tolerant/Compliant (S) or 3V (R) Matrix Options
– CMOS, LVTTL, LVDS, PCI, USB, etc.
– Output Currents Programmable from 2 to 24 mA, by Step of 2 mA
– Cold Sparing Buffers (2 µA Max. Leakage Current at 3.6V Worst Case Mil Temp.)
250 MHz PLL (on request), 220 MHz LVDS and 800 MHz Max. Toggle Frequency at 3.3V
Deep Submicron CAD Flow
•
•
•
•
•
•
•
Rad Hard
1.6M Used
Gates 0.35 µm
CMOS Sea of
Gates/
ESD better than 2000V
No Single Event Latch-Up below an LET Threshold of 80 MeV/mg/cm2
SEU Hardened Flip-flops
Tested Up to a Total Dose of 300 Krad (Si) according to Mil STD 883 Method 1019
Quality Grades
- QML Q and V with SMD 5962-01B01
- ESCC QML with ESCC 9202 / 076
Embedded
Array
Description
The MH1RT Gate Array and Embedded Array families from Atmel are fabricated on a
radiation hardened 0.35 micron CMOS process, with up to 4 levels of metal for inter-
connect. This family features arrays with up to 1.6 million routable gates and 596
pads. The high density and high pin count capabilities of the MH1RT family, coupled
with the ability to embed cores or memories on the same silicon, make the MH1RT
series of arrays one of the best choices for System Level Integration.
MH1RT
The MH1RT series is supported by an advanced software environment based on
industry standards linking proprietary and commercial tools. Verilog®, DFT®, Synop-
sys® and Vital are the reference front end tools. The Cadence® ‘Logic Design Planner’
floor planning associated with timing driven layout provides an efficient back end
cycle.
The MH1RT series comes as a dual use of the MH1 series, adding:
- through process changes, the latch-up susceptibility better than 80 MeV/mg/cm2 and
the 300 Krad (Si) radiation level as required by most space programs.
- through cells relayout, an SEU built-in protection allowing to SEU harden only where
it is necessary with respect to function requirements
With a background of 15 years experience, the MH1RT series comes as the Atmel
7th generation of ASIC series designed for radiation hardened applications.
4110K–AERO–11/07
Table 1. List of Available MH1RT Matrices
Device
Number
Typical Routable
Gates
Max Pad
Count
Max
I/O Count
Gate
Speed(1)
Max. Sites Count
920,385
MH1099E
MH1156E
MH1242E
MH1332E
519,000
764,000
332
412
512
596
324
404
504
588
180 ps
180 ps
180 ps
180 ps
1,447,975
1,198,000
1,634,000
2,275,377
3,098,804
Notes: 1. Nominal 2 Input NAND Gate FO = 2 at 3.3V.
Design
Design Systems
Supported
Atmel supports several major software systems for design with complete macro cell libraries, as
well as utilities for checking the netlist and estimated pre-route delay simulations.
The following design systems are supported:
Table 2. Supported design systems
System
Available Tools
Verilog-XL® - Verilog Simulator
Logic Design Planner™ - Floorplanner
BuildGates® - Synthesis (Ambit)
Cadence
Modelsim Verilog and VHDL (VITAL) Simulator
DFT- Scan insertion and ATPG, BIST
Mentor/Model Tech
Design Compiler™ - Synthesis
Primetime® - Static Path
Synopsys®
Formality®
- Equivalence Checking
2
MH1RT
4110K–AERO–11/07
MH1RT
Design Flow
and Tools
Atmel’s design flow for Gate Array/Embedded Array is structured to allow the designer to consol-
idate the greatest number of system components possible onto the same silicon chip, using
available third party design tools. Atmel’s cell library reflects silicon performance over extremes
of temperature, voltage, and process, and includes the effects of metal loading, inter-level
capacitance, and edge rise and fall times. The Design Flow includes clock tree synthesis to min-
imize skew and latency. RC extraction is performed on final design database and incorporated
into the timing analysis.
The Typical Gate Array/Embedded Array Design Flow, shown on page 4, provides a pictorial
description of the typical interaction between Atmel’s Gate Array/Embedded Array design staff
and the customer. Atmel will deliver design kits to support the customer’s synthesis, verification,
floorplanning, and SCAN insertion activities. Tools such as Synopsys Synthesis, Cadence and
Mentor Logic Simulators are used, and many others are available. Should a design include
embedded memory or an embedded core, Atmel needs to understand the partition of the Array,
and define the location of the memory blocks and/or cores (preliminary place and route) so that
an underlayer layout model can be created (Base Wafer).
Following a Preliminary Design Review, so called Logic Review, the design is routed, and post-
route RC data is extracted. Following post-route verification and a Final Design Review, so
called Design Review, the design is taped out for fabrication.
The purpose of these reviews is to check the conformity of the design to Atmel rules, and
acknowledge it in formal documents.
3
4110K–AERO–11/07
Figure 1. Typical Gate Array/Embedded Array Design Flow
Atmel
Design Kit
Delivery
Base Wafer
Definition
Kickoff
Design
Synthesis
SCAN
Insertion
Functional
and Static
Path Sims
Atmel
Preliminary
Place & Route
Base Wafer
Creation
Floorplan
Atmel
Database
Acceptance
Database
Handoff
Base Wafer
Pre-route
Verification
Logic
Review
Atmel
Atmel
Place & Route
and
Clock Tree
Base Wafer
Fabrication
Post-route
Verification
Design
Review
Atmel
Tape Out
Metallization
Layers
Atmel
Masks
Generation
Atmel
Fab.,
Assembly
and Test
Joint
Rev.1.6 - 07/2003
Atmel
Customer
4
MH1RT
4110K–AERO–11/07
MH1RT
Pin Definition
Requirements
The corner pads are reserved for Power and Ground only. All other pads are fully programmable
as Input, Output, Bidirectional, Power or Ground. When implementing a design with 5V compli-
ant buffers, one buffer site must be reserved for the VDD5 pin, which is used to distribute power to
the buffers.
Figure 2. Gate Array
Figure 3. Embedded Array
Standard
Gate Array
Architecture
SRAM
Core
I/O Site: Pad and
Sub-Sections
The I/O sites can be configured as input, output, 3-state output and bidirectional buffers, each
with pullup or pulldown capability, if required, by utilizing their corresponding sub-section. Bidi-
rectionnal buffers are the result of an input and output buffers placed in adjacent sub-sections in
the same I/O site. Special buffers may require multiple I/O sites. Oscillators require 2 I/O sites,
each power and ground pin utilizes one I/O site.
PCI Buffers
PCI compatible input and output buffers are available for each bias voltage, 3V and 5V.
LVDS Buffers
Each LVDS buffer uses 2 I/O sites.
LVDS drivers are specific for each bias voltage and require one external current bias resistor per
Ω
chip; LVDS receiver is the same for all bias voltages and requires 1 external line matching 100
resistor per receiver.
Cold Sparing
It is the use of twice the same chip, A1 and A2, A1 ON and A2 OFF, with all signal pins/pads
connected by pairs, A1I1 with A2I1, A101 with A201,...
5
4110K–AERO–11/07
During this mode operation:
–
the chip OFF must survive and operate when turned ON without functional, AC, DC
or reliability impact,
–
the current pulled by the OFF chip must be limited to a low value: Atmel specification
for their dedicated cold sparing buffers is 2 µA worst case by signal pins/pads.
For any other operation mode, refer to maximum ratings.
Memory Blocks
Memory blocks can be either synthesized on gates (when smaller than 8 bits) or compiled and
embedded in the array itself. Various combinations of Through Flow or Bus Watch EDACs, 4, 8,
16 and 32 bit wide, can be used to alleviate the effect of SEU induced errors.
6
MH1RT
4110K–AERO–11/07
MH1RT
ASIC Design
Translation
Atmel has successfully translated existing designs from most major ASIC vendors (LSI Logic®,
Motorola®, SMOS®, Oki®, NEC®, Fujitsu®, AMI® and others) into the gate arrays. These designs
have been optimized for speed and gate count and modified to add logic or memory, or repli-
cated for a pin-to-pin compatible, drop-in replacement.
Design Entry
Design entry is performed by the customer using an Atmel ASIC library. A complete netlist and
vector set must then be provided to Atmel. Upon acceptance of this data set, Atmel continues
with the standard design flow.
FPGA and PLD Atmel has successfully translated existing FPGA/PLD designs from most major vendors (Xil-
inx®, Actel®, Altera®, AMD® and Atmel) into the gate arrays. There are four primary reasons to
Conversions
convert from an FPGA/PLD to a gate array. Conversion of high volume devices for a single or
combined design is cost effective. Performance can often be optimized for speed or low power
consumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost while
reducing on-board space requirements. Finally, in situations where an FPGA/PLD was used for
fast cycle time prototyping, a gate array may provide a lower cost answer for long-term volume
production.
Cell Library
Atmel's MH1RT Series gate arrays make use of an extensive library of macro cell structures,
including logic cells, buffers and inverters, multiplexers, decoders, and I/O options. Soft macros
are also available.
The MH1RT Series PLL operates at frequencies of up to 250 MHz with minimal phase error and
jitter, making it ideal for frequency synthesis of high speed on-chip clocks and chip to chip
synchronization.
These cells are well characterized by use of SPICE modeling at the transistor level, with perfor-
mance verified on manufactured test arrays. Characterization is performed over the rated
temperature and voltage ranges to ensure that the simulation accurately predicts the perfor-
mance of the finished product.
Cells
Number of Cells
Logic Cells
95
I/O Buffers
3V or 2.5V or 3.3V
5V Tolerant
110
36
70
5V Compliant
Specific Cells
LVDS, PCI
11
9
SEU Hardened Cells
Cold Sparing
63
7
4110K–AERO–11/07
Electrical Characteristics
Absolute Maximum Ratings
*NOTE:
Stresses beyond those listed under "Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Operating Ambient Temperature .........-55°C to +125°C
Storage Temperature........................... -65°C to +150°C
Maximum Input Voltage VDD ...+0.5V and VCC + 0.5V
Maximum 3.3V Operating Voltage................. 4V (VDD)
Maximum 5V Operating Voltage.................... 6V (VCC)
ESD level ........................................................... > 2000V
DC Characteristics
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Table 3. 2.5V DC Characteristics
Symbol Parameter
Buffer
All
Test Condition
Min.
-55
Typ
25
Max.
125
2.7
Units
TA
Operating Temperature
C
V
VDD
Supply Voltage
All
2.3
2.5
Low-level Input Current
Pull-up resistors PRU1 (1)
Pull down resistor PRD1
-1
70
-5
1
230
5
µA
µA
µA
IIL
CMOS
VIN = VSS
High level Input Current
Pull-up resistors PRU1
Pull down resistor PRD1 (2) CMOS
-1
-5
1
5
IIH
VIN = VDD ( Max.)
70
540
Vin = Vdd or Vss, Vdd = Vdd
(Max.)
-1
–
1
High impedance state
output current
IOZ
All
No pull resistor
CMOS
PCI
0.3Vdd
0.325Vdd
1.25
V
V
VIL
Low level Input voltage
High level Input voltage
Schmitt level
CMOS
PCI
0.78
0.7 Vdd
0.475Vdd
1.06
VIH
Schmitt level
1.61
Delta V CMOS Hysterisis
0.25
0.34
V
Cold sparing leakage input
current
-2
-2
2
2
µA
µA
IICS
PICZ
Vin = 0 to VDDmax
Cold sparing leakage
output current
IOCS
POxxZ
POxxZ
Vout = 0 to VDDmax
Iocs = 100 µA
Supply threshold of cold
sparing buffers
0.5
V
(3)
VCSTH
8
MH1RT
4110K–AERO–11/07
MH1RT
Table 3. 2.5V DC Characteristics (Continued)
Symbol Parameter Buffer
Test Condition
Min.
Typ
Max.
Units
VOL
VOH
Low-level Output Voltage (4) PO11
High level output voltage (5) PO11
Output short circuit current
IOL = 0.8 mA, Vdd = Vdd (Min.)
Ioh = -0.6 mA, Vdd = Vdd (Min.)
0.4
V
V
2
Vdd = Vdd (Max.),
Vout = Vdd
Iosn
Iosp
PO11
PO11
15
8
mA
IOS
Vouy = Vss
ICCSB
ICCOP
1.
Leakage current per cell
Dynamic current per gate
Vdd = Vdd (Max.)
Vdd = Vdd (Max.)
0.27
4
0.32
nA
µW/MHz
For standard pull-ups: PRU (#), # = {1-31} index for Ron: Ron = # x RO where RO = 19 k
Ω
typ, 30 k
Ω
Max., 12 k
Ω typ, 30 kΩ Max., 5 kΩ Min.
Ω
Min.
2.
3.
4.
For standard pull-downs: PRD (#), # = {1-31} index for Ron: Ron = # x RO where RO = 11 k
Guaranteed not tested
For output buffers PO (1-C) (1-C):
1-C: hex value: convert hex to decimal x IO = p and n-channel output drive
IO = 1.6 mA for standard buffers (including cold sparing) measured at Vol = 0.4V
For output buffers PO (1-C) (1-C):
5.
1-C: hex value: convert hex to decimal x IO = p and n-channel output drive
IO = -1.6 mA for standard buffers (including cold sparing) measured at Voh = 2.0V
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Table 4. 3V DC Characteristics
Symbol Parameter
Buffer
All
Test Condition
Min.
-55
Typ
25
Max.
125
3.3
Units
TA
Operating Temperature
C
V
VDD
Supply Voltage
All
2.7
3.0
-1
108
-5
1
330
5
Low-level Input Current
Pull-up resistors PRU1
(1)
µA
µA
µA
IIL
Pull down resistor PRD1
CMOS
CMOS
VIN = VSS
High level Input Current
Pull-up resistors PRU1
Pull down resistor PRD1
-1
-5
1
5
(2)
IIH
VIN = VDD( Max.)
108
825
VIN = VDD OR VSS, VDD =
VDD (Max.)
-1
1
High impedance state
output current
IOZ
All
No pull resistor
CMOS
PCI
0.8
0.325VDD
1.42
V
V
VIL
Low level Input voltage
High level Input voltage
Schmitt level
CMOS
PCI
0.90
2
0.475VDD
1.25
VIH
Schmitt level
1.93
-2
Delta V CMOS Hysterisis
Cold sparing leakage input
0.31
0.42
–
V
-2
µA
IICS
current
PICZ
VIN = 0 to VDDmax
9
4110K–AERO–11/07
Table 4. 3V DC Characteristics (Continued)
Symbol Parameter
Buffer
Test Condition
Min.
Typ
Max.
Units
µA
Cold sparing leakage
output current
-2
–
-2
IOCS
POxxZ
POxxZ
Vout = 0 to VDDmax
Iocs = 100 µA
Supply threshold of cold
sparing buffers
–
0.5
–
V
(3)
VCSTH
Low-level Output Voltage
(4)
–
–
–
0.4
–
V
V
VOL
VOH
PO11
PO11
IOL = 1 mA, Vdd = Vdd(Min.)
(5)
High level output voltage
Ioh = -0.8 mA, Vdd = Vdd(Min.)
2.4
Output short circuit current
Vdd = Vdd(Max.),
Vout = Vdd
Iosn
Iosp
PO11
PO11
–
–
21
12
mA
IOS
Vouy = Vss
ICCSB
ICCOP
Leakage current per cell
Dynamic current per gate
–
–
Vdd = Vdd(Max.)
Vdd = Vdd(Max.)
–
–
0.6
–
5
nA
0.54
µW/MHz
1.
For standard pull-ups: PRU (#), # = {1-31} index for Ron: Ron = # x RO where RO = 15 k
Ω
typ, 25 k
For standard pull-downs: PRD (#), # = {1-31} index for Ron: Ron = # x RO where RO = 9 kΩ
Ω
Max., 10 k
typ, 25 kΩ
Ω
Min.
Min.
2.
3.
4.
Max., 4 kΩ
Guaranteed not tested.
For output buffers PO (1-C) (1-C):
1-C: hex value: convert hex to decimal x IO = p and n-channel output drive
IO = -1.8 mA for standard buffers (including cold sparing) measured at Vol = 0.4V
For output buffers PO (1-C) (1-C):1-C:
5.
hex value: convert hex to decimal x IO = p and n-channel output drive
IO = -1.8 mA for standard buffers (including cold sparing) measured at Voh = 2.4V
Table 5. 3.3V DC Characteristics
Symbol Parameter
Buffer
All
Test Condition
Min.
Typ
25
Max.
125
3.6
Units
TA
Operating Temperature
Supply Voltage
-55
3
C
V
VDD
All
3.3
Low-level Input Current
Pull-up resistors PRU1
-1
120
-5
1
400
5
(1)
µA
µA
µA
IIL
Pull down resistor PRD1
CMOS
CMOS
VIN = VSS
High level Input Current
Pull-up resistors PRU1
Pull down resistor PRD1
-1
-5
1
5
(2)
IIH
VIN = VDD( Max.)
150
900
Vin = Vdd or Vss, Vdd =
Vdd(Max.)
-1
1
High impedance state
output current
Ioz
All
No pull resistor
CMOS
PCI
0.8
0.325Vdd
1.51
V
VIL
Low level Input voltage
High level Input voltage
Schmitt level
CMOS
PCI
0.99
2
0.475Vdd
1.40
V
V
VIH
Schmitt level
2.08
Delta V CMOS Hysterisis
0.37
0.48
10
MH1RT
4110K–AERO–11/07
MH1RT
Table 5. 3.3V DC Characteristics (Continued)
Symbol Parameter
Buffer
Test Condition
Min.
Typ
Max.
Units
µA
Vdd = Vss = 0V
Cold sparing leakage input
current
-2
-2
-2
IICS
PICZ
Vin = 0 to VDD Max
Vdd = Vss = 0V
µA
Cold sparing leakage
output current
-2
IOCS
POxxZ
POxxZ
Vin = 0 to VDD Max
Supply threshold of cold
sparing buffers
0.5
V
(3)
VCSTH
Iocs = 100 µA
Low-level Output Voltage
(4)
0.4
V
V
VOL
VOH
PO11
PO11
IOL = 2 mA, Vdd = Vdd(Min.)
(5)
High level output voltage
Ioh = -1.8 mA, Vdd = Vdd(Min.)
2.4
Output short circuit current
Vdd = Vdd(Max.),
Vout = Vdd
Iosn
Iosp
PO11
PO11
23
13
mA
IOS
Vouy = Vss
ICCSB
ICCOP
Leakage current per cell
Dynamic current per gate
Vdd = Vdd(Max.)
Vdd = Vdd(Max.)
0.7
5
nA
0.69
µW/MHz
1.
For standard pull-ups: PRU(#), # = {1-31} index for Ron: Ron = # x RO where RO = 14 k
Ω
typ, 25 kΩ Max., 9 k
For standard pull-downs:PRD(#), # = {1-31} index for Ron: Ron = # x RO where RO = 8kΩ typ, 20 kΩ Max., 4 kΩ
Ω
Min.
Min.
2.
3.
4.
Guaranteed not tested.
For output buffers PO (1-C) (1-C):
1-C: hex value: convert hex to kΩ x IO = p and n-channel output drive
IO = -2.0 mA for standard buffers (including cold sparing) measured at Vol = 0.4V
For output buffers PO (1-C) (1-C):
5.
1-C: hex value: convert hex to kΩ x IO = p and n-channel output drive
IO = -2.0 mA for standard buffers (including cold sparing) measured at Voh = 2.4V
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Table 6. 5V DC Characteristics
Symbol Parameter
Buffer
Test Condition
Min.
-55
3.0
Typ
25
3.3
5
Max.
Units
TA
Operating Temperature
All
125
3.6
5.5
C
V
V
Vdd
Vcc
Supply Voltage
Supply Voltage
5V Tolerant
5V Compliant
4.5
Low-level Input Current
Pull-up resistors PRU1 (1)
Pull down resistor PRD1
-1
180
-5
1
690
5
µA
IIL
CMOS
VIN = VSS
High level Input Current
Pull-up resistors PRU1
Pull down resistor PRD1 (2) CMOS
-1
-5
1
5
µA
µA
IIH
VIN = VDD( Max.)
30
400
Vin = Vdd orVss,Vdd=Vdd(max
No pull resistor
High impedance state
output current
-1
1
Ioz
All
11
4110K–AERO–11/07
Table 6. 5V DC Characteristics (Continued)
Symbol Parameter
Buffer
Test Condition
Min.
Typ
Max.
0.8
Units
PICV, PICV5
PCI
0.325Vdd
1.51
V
Vil
Low level Input voltage
Schmitt level
PICV, PICV5
PCI
0.99
2
0.475Vdd
1.40
V
VIH
High level Input voltage
Schmitt level
2.08
Delta V CMOS Hysterisis
0.37
0.48
V
Cold sparing leakage input
current
-2
-2
-2
-2
µA
µA
IICS
PICZ
Vin = 0 to VDDmax
Cold sparing leakage
output current
IOCS
POxxZ
POxxZ
Vout = 0 to VDDmax
Iocs = 100 µA
Supply threshold of cold
sparing buffers
0.6
V
V
(3)
VCSTH
Low Voltage/2.5V range
Low Voltage/3.0V range
Low Voltage/3.3V range
Low Voltage/2.5V range
Low Voltage/3.0V range
Low Voltage/3.3V range
PO11V
PO11V
PO11V
PO11V5
PO11V5
PO11V5
Iol = 0.5 mA
Iol = 0.6 mA
Iol = 1.2 mA
Iol = 1.1 mA
Iol = 1.3 mA
Iol = 1.5 mA
0.4
(4)
VOL
Low Voltage/2.5V range
Low Voltage/3.0V range
Low Voltage/3.3V range
Low Voltage/2.5V range
Low Voltage/3.0V range
Low Voltage/3.3V range
PO11V
PO11V
PO11V
PO11V5
PO11V5
PO11V5
Ioh = 0.5 mA
Ioh = 0.6 mA
Ioh = 1.2 mA
Ioh = 1.1 mA
Ioh = 1.3 mA
Ioh = 1.5 mA
2
2.4
2.4
2.4
2.4
2.4
V
(5)
VOH
Output short circuit current
Vdd = Vdd(Max.),
Vout = Vdd
Iosn
Iosp
PO11V
PO11V
28
17
mA
IOS
Vouy = Vss
1.
For 5V tolerant/compliant pull-ups: PRU(#), # = {1-31} index for Ron: Ron = # x RO where RO = 14 k
Min.
Ω
typ, 25 kΩ Max., 8 kΩ
2.
For 5V tolerant/compliant pull-downs: PRD(#), # = {1-31} index for Ron: Ron = # x RO where:
RO = 19 kΩ typ, 45 kΩ Max., 9 kΩ Min. in 3.3V range,
RO = 23 kΩ typ, 55 kΩ Max., 11 kΩ Min. in 3V range,
RO = 36 kΩ typ, 80 kΩ Max., 17 kΩ Min. in 2.5V range,
Guaranteed not tested.
3.
4.
Tolerant Buffers (including cold spearing):
IO = -1.0, 1.3, 1.4 mA measured at VOL = 0.4, 0.4, 0.4V in 2.5, 3.0, 3.3V range respectively.
Compliant Buffers (VCC = 4.5V)
IO = -1.1, 1.4, 1.6 mA measured at VOL = 0.4, 0.4, 0.4 V in 2.5, 3.0, 3.3V range respectively.
12
MH1RT
4110K–AERO–11/07
MH1RT
5.
Tolerant Buffers (including cold spearing):
IO = -1.0, -1.3, -1.4 mA measured at VOH = 2.0, 2.4, 2.4V in 2.5, 3.0, 3.3V range respectively.
Compliant Buffers (VCC = 4.5V)
IO = -1.1, -1.4, -1.6 mA measured at VOH = 2.0, 2.4, 2.4 V in 2.5, 3.0, 3.3V range respectively.
13
4110K–AERO–11/07
LVDS Driver DC
and AC
Characteristics
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Table 7. 2.5V LVDS Driver DC/AC Characteristics
Symbol
Parameter
Test Condition
Min.
Max.
Units
°C
Comments
–
TA
Operating Temperature
Supply Voltage
–
-55
125
VDD
–
2.3
2.7
V
–
|VOD|
Vol
Output differential voltage
Output voltage low
Output voltage high
Output offset voltage
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
230.7
1224
993
446.5
1817
1406
1610
mV
mV
mV
mV
see Figure 4
see Figure 4
see Figure 4
see Figure 4
Voh
VOS
1108
Change in |VOD| between "0"
and "1"
0
0
50
mV
mV
–
–
|Delta VOD|
Rload = 100Ω
Change in |VOS| between "0"
and "1"
100
|Delta VOS|
ISA, ISB
ISAB
Rload = 100Ω
Output current
Output current
Bias resistor
Drivers shorted to ground or VDD
1.0
2.4
9.8
5.8
6.3
4.8
mA
mA
KΩ
mA
–
–
Drivers shorted together
Rbias
–
–
10.2
11.7
1 per chip
Ibias
Bias static current
Maximum operating
frequency
Consumption
14.8 mA
–
180
MHz
F Max.
Clock
Tfall
VDD = 2.5V 0.2V
Max. frequency
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Clock signal duty cycle
Fall time 80-20%
Rise time 20-80%
Propagation delay
Duty cycle skew
45
669
670
1270
0
55
%
ps
ps
ps
ps
–
1178
1167
2660
110
see Figure 4
see Figure 4
see Figure 4
–
Trise
Tp
Tsk1
Channel to channel skew
(same edge)
0
50
ps
–
Tsk2
Rload = 100Ω
14
MH1RT
4110K–AERO–11/07
MH1RT
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Table 8. 3V LVDS Driver DC/ AC Characteristics
Symbol
TA
Parameter
Test Condition
–
Min.
-55
Max.
125
Units
°C
Comments
–
Operating Temperature
Supply Voltage
VDD
–
2.7
3.3
V
–
|VOD|
Vol
Output differential voltage
Output voltage low
Output voltage high
Output offset voltage
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
244
1088
828
958
462
mV
mV
mV
mV
see Figure 4
see Figure 4
see Figure 4
see Figure 4
1775
1358
568
Voh
VOS
Change in |VOD| between "0"
and "1"
0
0
50
mV
mV
–
–
|Delta VOD|
Rload = 100Ω
Change in |VOS| between "0"
and "1"
150
|Delta VOS|
ISA, ISB
ISAB
Rload = 100Ω
Output current
Output current
Bias resistor
Drivers shorted to ground or VDD
1.0
2.6
6.3
5
mA
mA
KΩ
mA
–
Drivers shorted together
–
1 per chip
–
Rbias
–
–
12.8
6.5
13.2
13.8
Ibias
Bias static current
Maximum operating
frequency
Consumption
18.6 mA
–
200
MHz
F Max.
Clock
Tfall
VDD = 3V 0.3V
Max. frequency
Rload = 10Ω
Clock signal duty cycle
Fall time 80-20%
Rise time 20-80%
Propagation delay
Duty cycle skew
45
512
512
1150
0
55
968
970
2300
70
%
ps
ps
ps
ps
–
see Figure 4
see Figure 4
see Figure 4
–
Trise
Tp
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Tsk1
Channel to channel skew
(same edge)
0
50
ps
–
Tsk2
Rload = 100Ω
15
4110K–AERO–11/07
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Table 9. 3.3V LVDS Driver DC/ AC Characteristics
Symbol
TA
Parameter
Test Condition
–
Min.
-55
Max.
125
Units
°C
Comments
–
Operating Temperature
Supply Voltage
VDD
–
3
3.6
V
–
|VOD|
Vol
Output differential voltage
Output voltage low
Output voltage high
Output offset voltage
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
251.4
1071
804
937
452.2
1731
1323
1527
mV
mV
mV
mV
see Figure 4
see Figure 4
see Figure 4
see Figure 4
Voh
VOS
Change in |VOD| between "0"
and "1"
0
0
50
mV
mV
–
–
|Delta VOD|
Rload = 100Ω
Change in |VOS| between "0"
and "1"
200
|Delta VOS|
ISA, ISB
ISAB
Rload = 100Ω
Output current
Output current
Bias resistor
Drivers shorted to ground or VDD
1.0
2.6
16.3
7
6.2
4.8
mA
mA
kΩ
–
Drivers shorted together
–
1 per chip
–
Rbias
–
–
16.7
14.6
Ibias
Bias static current
mA
Maximum operating
frequency
Consumption
20.9 mA
–
220
MHz
F Max.
Clock
Tfall
VDD = 3.3V 0.3V
Max. frequency
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Clock signal duty cycle
Fall time 80-20%
Rise time 20-80%
Propagation delay
Duty cycle skew
45
445
445
1120
0
55
838
841
2120
80
%
ps
ps
ps
ps
–
see Figure 4
see Figure 4
see Figure 4
–
Trise
Tp
Tsk1
Channel to channel skew
(same edge)
0
50
ps
–
Tsk2
Rload = 100Ω
Figure 4. Test Termination Measurements
A
100 Ω
VOD
B
(VA + VB)
VOS = --------------------------
2
16
MH1RT
4110K–AERO–11/07
MH1RT
Figure 5. Rise and Fall Measurements
A
100 Ω
5 pF
B
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Table 10. LVDS Receiver DC/ AC Characteristics
Symbol
TA
Parameter
Test Condition
Min.
-55
2.3
0
Max.
125
Units
°C
Comments
Operating Temperature
Supply Voltage
–
–
–
–
–
–
–
–
VDD
3.6
V
Vi
Input voltage range
Input differential voltage
2400
+100
mV
mV
Vidth
-100
Cout = 50 pF, VDD = 2.5V 0.2V
Cout = 50 pF, VDD = 3.0V 0.3V
Cout = 50 pF, VDD = 3.3V 0.3V
0.9
0.7
0.7
3.5
2.7
2.4
ns
ps
–
–
Tp
Propagation delay
Tskew
Duty cycle distortion
Cout = 50 pF
-
500
Table 11. I/O Buffers DC Characteristics
Symbol
CIN
Parameter
Test Condition
Typical
Units
pF
Capacitance, Input Buffer (die)
Capacitance, Output Buffer (die)
Capacitance, Bi-Directional
3V
3V
3V
2.4
5.6
6.6
COUT
CI/O
pF
pF
17
4110K–AERO–11/07
Testability
Techniques
For complex designs, involving blocks of memory and/or cores, careful attention must be given
to design-for-test techniques. The sheer size of complex designs and the number of functional
vectors that would need to be created to exercise them fully, strongly suggests the use of more
efficient techniques. Combinations of SCAN paths, multiplexed access to memory and/or core
blocks, and built-in-self-test logic must be employed, in addition to functional test patterns, to
provide both the user and Atmel the ability to test the finished product.
An example of a highly complex design could include a PLL for clock management or synthesis,
a microcontroller or DSP engine or both, SRAM to support the microcontroller or DSP engine,
and glue logic to support the interconnectivity of each of these blocks. The design of each of
these blocks must take into consideration the fact that the manufactured device will be tested on
a high performance digital tester. Combinations of parametric, functional, and structural tests,
defined for digital testers, should be employed to create a suite of manufacturing tests.
The type of block dictates the type of testability technique to be employed. The PLL will, by con-
struction, provide access to key nodes so that functional and/or parametric testing can be
performed. Since a digital tester must control all the clocks during the testing of a Gate
Array/Embedded Array, provision must be made for the VCO to be bypassed. Atmel’s PLLs
include a multiplexing capability for just this purpose. The addition of a few pins will allow other
portions of the PLL to be isolated for test, without impinging upon the normal functionality.
In a similar vein, access to microcontroller, DSP, and SRAM blocks must be provided so that
controllability and observability of the inputs and outputs to the blocks are achieved with the min-
imum amount of preconditioning. SRAM blocks need to provide access to both address and data
ports so that comprehensive memory tests can be performed. Multiplexing I/O pins provides a
method for providing this accessibility.
The glue logic can be designed using full SCAN techniques to enhance its testability.
It should be noted that, in almost all of these cases, the purpose of the testability technique is to
provide Atmel a means to assess the structural integrity of a Gate Array/Embedded Array, i.e.,
sort devices with manufacturing-induced defects. All of the techniques described above should
be considered supplemental to a set of patterns which exercise the functionality of the design in
its anticipated operating modes.
18
MH1RT
4110K–AERO–11/07
MH1RT
Advanced
Packaging
The MH1RT Series are offered in ceramic packages: multi layers quad flat packs (MQFP) and a
BGA based on ceramic land grid arrays, so called multi layer column grid array (MCGA). Pack-
ages lid may be connected to ground or not.
Table 12. Packaging Options
Package Type (1)
Pin Count
MQFP(2)
196, 256 and 352
349, 472 (1.27 mm pitch)
MCGA(2)
Notes: 1. Contact Atmel local design centers to check the availability of the matrix/package combination.
2. Four decks packages.
Document
Revision
History
4110K - 11/07
1. Added missing ESD information. See pages 1 & 8.
19
4110K–AERO–11/07
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