LS840 [MICROSS]
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET; 线性系统的超低漏电低漂移单片双路JFET
| 型号： | LS840 |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET |
| 文件： | 总1页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LS840
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
FEATURES
LOW DRIFT
LOW LEAKAGE
LOW NOISE
LOW OFFSET VOLTAGE
The LS840 is a high-performance monolithic dual
| V GS1‐2 / T| ≤5µV/°C
IG = 10pA TYP.
en = 8nV/√Hz TYP.
| V GS1‐2|= 2mV TYP.
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LS840 features a 5-
mV offset and 5-µV/°C drift.
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
Maximum Voltage and Current for Each Transistor – Note 1
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
‐65°C to +150°C
+150°C
‐VGSS
‐VDSO
‐IG(f)
Gate Voltage to Drain or Source
Drain to Source Voltage
Gate Forward Current
60V
60V
50mA
(See Packaging Information).
LS840 Applications:
Maximum Power Dissipation
Device Dissipation @ Free Air – Total
400mW @ +125°C
Wideband Differential Amps
High-Speed,Temp-Compensated Single-
Ended Input Amps
High-Speed Comparators
Impedance Converters and vibrations
detectors.
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V GS1‐2 / T| max.
DRIFT VS.
5
µV/°C
VDG=20V, ID=200µA
TA=‐55°C to +125°C
VDG=20V, ID=200µA
TEMPERATURE
| V GS1‐2 | max.
OFFSET VOLTAGE
5
mV
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
BVGSS
BVGGO
CHARACTERISTICS
Breakdown Voltage
Gate‐To‐Gate Breakdown
TRANSCONDUCTANCE
Full Conduction
MIN.
60
60
TYP.
60
‐‐
MAX.
‐‐
‐‐
UNITS
V
V
CONDITIONS
VDS = 0
ID=1nA
I G= 1nA
ID= 0
IS= 0
YfSS
YfS
|YFS1‐2 / Y FS|
1000
500
‐‐
‐‐
‐‐
0.6
4000
1000
3
µmho
µmho
%
VDG= 20V
VDG= 20V
VGS= 0V f = 1kHz
ID= 200µA
Typical Operation
Mismatch
DRAIN CURRENT
Full Conduction
IDSS
0.5
2
5
mA
VDG= 20V
VGS= 0V
Click To Buy
|IDSS1‐2 / IDSS
|
Mismatch at Full Conduction
‐‐
1
5
%
GATE VOLTAGE
VGS(off) or Vp
VGS(on)
Pinchoff voltage
Operating Range
GATE CURRENT
Operating
High Temperature
Reduced VDG
1
0.5
2
‐‐
4.5
4
V
V
VDS= 20V
VDS=20V
ID= 1nA
ID=200µA
‐IGmax.
‐IGmax.
‐IGmax.
‐IGSSmax.
‐‐
‐‐
‐‐
‐‐
10
‐‐
5
50
50
‐‐
pA
nA
pA
pA
VDG= 20V ID= 200µA
TA= +125°C
VDG = 10V ID= 200µA
VDG= 20V , VDS =0
At Full Conduction
OUTPUT CONDUCTANCE
Full Conduction
‐‐
100
YOSS
YOS
‐‐
‐‐
‐‐
‐‐
0.1
0.01
10
1
0.1
µmho
µmho
µmho
VDG= 20V
VDG= 20V
VGS= 0V
ID= 200µA
Operating
Differential
|YOS1‐2
|
COMMON MODE REJECTION
CMR
‐20 log | V GS1‐2/ V DS
‐20 log | V GS1‐2/ V DS
NOISE
|
|
‐‐
‐‐
100
75
‐‐
‐‐
dB
∆VDS = 10 to 20V
∆VDS = 5 to 10V
VDS= 20V VGS= 0V
f= 100Hz
ID=200µA
ID=200µA
RG= 10MΩ
NBW= 6Hz
NF
en
Figure
Voltage
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
0.5
10
15
10
dB
nV/√Hz
VDS=20V ID=200µA f=1KHz NBW=1Hz
VDS=20V ID=200µA f=10Hz NBW=1Hz
CAPACITANCE
Input
Reverse Transfer
Drain‐to‐Drain
CISS
CRSS
CDD
‐‐
‐‐
‐‐
4
1.2
0.1
VDS= 20V, ID=200µA
pF
5
‐‐
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
PDIP & SOIC (Top View)
Available Packages:
LS840 / LS840 in PDIP & SOIC
LS840 / LS840 available as bare die
Please contact Micross for full package and die dimensions
Tel: +44 1603 788967
Email: chipcomponents@micross.com
Web: http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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