LS840-SOIC-8L [Linear]
Transistor,;
Linear 
LS840 LS841 LS842
LOW NOISE LOW DRIFT
LOW CAPACITANCE
MONOLITHIC DUAL N-CHANNEL JFET
FEATURES
LOW NOISE
en=8nV/Hz TYP.
LOW LEAKAGE
LOW DRIFT
IG=10pA TYP.
I VGS1-2/TI=5µV/ºC max.
IVGS1-2I=2mV TYP.
LOW OFFSET VOLTAGE
ABSOLUTE MAXIMUM RATINGS1
@ 25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
-55°C to +150°C
-55°C to +150°C
Operating Junction Temperature
Maximum Voltage and Current for Each Transistor1
-VGSS Gate Voltage to Drain or Source 60V
SOIC
Top View
TO-71/78
Top View
IG(f)
Gate Forward Current
10mA
Maximum Power Dissipation
Device Dissipation2 @ Free Air - Total
400mW TA=+25°C
ELECTRICAL CHARACTERISTICS @ 25ºC (unless otherwise noted)
SYMBOL
CHARACTERISTIC
LS840 LS841 LS842 UNITS CONDITIONS
I VGS1-2 / TI max.
Drift vs. Temperature
5
10
40
µV/ºC
VDG = 20V
ID = 200µA
ID = 200µA
TA = -55ºC to +125ºC
VDG = 20V
IVGS1-2I max.
Offset Voltage
5
10
25
mA
SYMBOL
BVGSS
CHARACTERISTIC3
Breakdown Voltage
Gate-to-Gate Breakdown
TRANSCONDUCTANCE
Full Conduction
MIN.
-60
TYP. MAX. UNITS CONDITIONS
--
--
--
--
V
V
VDS= 0
ID= -1nA
BVGGO
±60
IGGO= ±1µA ID= 0
IS = 0
Gfss
1000
500
4000
1000
µS
µS
VDG= 20V VGS= 0
f = 1kHz
Gfs
Typical Conduction
VDG= 20V ID= 200µA
4
Gfs1
Gfs2
│
│
Mismatch Transconductance
Ratio
0.97
1.0
DRAIN CURRENT
IDSS
Full Conduction
0.5
2
5
mA
VDG= 20V VGS= 0
4
IDSS1
IDSS2
│
│
Drain Current Ratio
0.95
1.0
GATE-SOURCE
Pinchoff Voltage
Operating Range
GATE CURRENT
Operating
VGS(off)
VGS
-1
-2
--
-4.5
-4
V
V
VDS= 20V ID= 1nA
-0.5
VDS= 20V ID= 200µA
-IG
--
--
--
--
10
--
50
50
--
pA
nA
pA
pA
VDG= 20V ID =200µA
-IG
High Temperature
Reduced VDG
VDG= 20V ID =200µA TA=+125ºC
VDG= 10V ID =200µA
-IG
5
-IGSS
At Full Conduction
--
100
VDG= 20V VDS =0
Linear Integrated Systems
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201143 8/16/2012 Rev#A7 ECN# LS840 LS841 LS842
SYMBOL
CHARACTERISTIC
OUTPUT CONDUCTANCE
Full Conduction
MIN.
TYP. MAX. UNITS CONDITIONS
GOSS
--
--
--
--
10
1
µS
µS
µS
VDG= 20V
VDG= 20V
VGS= 0
GOS
Operating
0.1
ID= 200µA
│GOS 1-2
│
Differential
0.01
0.1
COMMON MODE REJECTION
CMRR
CMRR
--
--
100
75
--
--
dB
dB
V DS= 10 to 20V
V DS= 5 to 10V
ID=200µA
ID=200µA
-20 log │V GS1-2/ V DS
│
NOISE
NF
en
Figure
--
--
--
--
--
--
0.5
10
15
dB
VDS= 20V
f= 100Hz
VGS= 0
RG=10M
NBW= 6Hz
Voltage
Voltage
nV/Hz VDS= 20V
NBW= 1Hz
ID= 200µA f= 1KHz
en
nV/Hz VDS= 20V
NBW= 1Hz
ID= 200µA f= 10Hz
CAPACITANCE
Input
CISS
CRSS
CDD
--
--
--
4
10
5
pF
pF
pF
VDS= 20V
VDG= 20V
ID=200µA
ID= 200µA
Reverse Transfer
Drain-to-Drain
1.2
0.1
--
TO-78
TO-71
Six Lead
0.335
0.370
0.305
0.230
0.209
DIA.
0.195
0.175
DIA.
0.335
MAX.
0.040
0.030
MAX.
0.165
0.185
0.210
0.170
0.016
0.019
DIM. A
MIN. 0.500
6 LEADS
0.016
0.021
DIM. B
0.500 MIN.
0.050
SEATING
PLANE
0.019
0.016
DIA.
0.200
0.100
0.100
0.029
0.045
3
7
2
1
3
7
2
5
6
1
5
6
0.100
45°
45°
0.028
0.046
0.036
0.048
0.028
0.034 Note: All Dimensions in inches
NOTES:
1. These ratings are limiting values above which the serviceability of any semiconductor may be impaired
2. Derate 4mW/ºC above 25ºC
3. All MIN/TYP/MAX limits are absolute numbers. Negative signs indicate electrical polarity only.
4. Assumes smaller number in the numerator.
Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing
high-quality discrete components. Expertise brought to LIS is based on processes and products developed
at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall,
a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide,
co-founder and vice president of R&D at Intersil, and founder/president of Micro Power Systems.
Linear Integrated Systems
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201143 8/16/2012 Rev#A7 ECN# LS840 LS841 LS842
相关型号：
LS841-TO-71
Small Signal Field-Effect Transistor, 2-Element, N-Channel, Silicon, Junction FET, HERMETIC SEALED, TO-71, 6 PIN
MICROSS
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