ZL30251LDG1 [MICROSEMI]
Microprocessor Circuit, CMOS, QFN-32;
| 型号： | ZL30251LDG1 |
| 厂家： | 
Microsemi |
| 描述： | Microprocessor Circuit, CMOS, QFN-32 外围集成电路 |
| 文件： | 总79页 (文件大小：1394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Register Map: Section 6.2
ZL30250, ZL30251
4-Input, 3-Output Any-to-Any Clock
Multiplier and Frequency Synthesizer ICs
Data Sheet
January 2018
Ordering Information
Features
ZL30250LDG1
ZL30250LDF1
ZL30251LDG1
ZL30251LDF1
32 Pin QFN
32 Pin QFN
32 Pin QFN
32 Pin QFN
Trays
Tape and Reel
Trays
• Four Input Clocks
• One crystal/CMOS input
• Two differential/CMOS inputs
• One single-ended/CMOS input
Tape and Reel
Matte Tin
Package size: 5 x 5 mm
• Any input frequency from 9.72MHz to 1250MHz
(9.72MHz to 300MHz for CMOS)
• Clock selection by pin or register control
• Low-Jitter Fractional-N APLL and 3 Outputs
• Any output frequency from <1Hz to 1035MHz
• Precise output alignment circuitry and per-
output phase adjustment
• Per-output enable/disable and glitchless
• High-resolution fractional frequency conversion
start/stop (stop high or low)
with 0ppm error
• General Features
• Easy-to-configure, encapsulated design
requires no external VCXO or loop filter
components
• Automatic self-configuration at power-up from
external (ZL30250) or internal (ZL30251)
EEPROM; up to four configs, pin-selectable
• SPI or I2C processor Interface
• Numerically controlled oscillator mode
• Spread-spectrum modulation mode
• Tiny 5x5mm QFN package
• Each output has independent dividers
• Output jitter as low as 0.16ps RMS (12kHz-
20MHz integration band)
• Outputs are CML or 2xCMOS, can interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
• Easy-to-use evaluation software
• In 2xCMOS mode, the P and N pins can be
different frequencies (e.g. 125MHz and 25MHz)
Applications
• Per-output supply pin with CMOS output
•
Frequency conversion and frequency synthesis in
a wide variety of equipment types
voltages from 1.5V to 3.3V
IC1P, IC1N
IC2P, IC2N
IC3P/GPIO3
HSDIV1
HSDIV2
HSDIV3
OC1P, OC1N
VDDO1
OC2P, OC2N
VDDO2
OC3P, OC3N
VDDO3
HSDIV1
DIV1
DIV2
DIV3
APLL
~3.7 to 4.2GHz,
Fractional-N
NCO
SS
Figure 6
HSDIV2
XA
XB
xtal
driver
×2
Microprocessor Port
(SPI or I2C Serial)
and HW Control and Status Pins
Figure 1 - Functional Block Diagram
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Copyright 2018. Microsemi Corporation. All Rights Reserved.
ZL30250, ZL30251
Data Sheet
Table of Contents
1.
2.
APPLICATION EXAMPLES.......................................................................................................... 5
DETAILED FEATURES................................................................................................................. 5
2.1 INPUT CLOCK FEATURES .............................................................................................................. 5
2.2 APLL FEATURES.......................................................................................................................... 5
2.3 OUTPUT CLOCK FEATURES........................................................................................................... 5
2.4 GENERAL FEATURES .................................................................................................................... 5
2.5 EVALUATION SOFTWARE............................................................................................................... 6
3.
4.
5.
PIN DIAGRAM............................................................................................................................... 6
PIN DESCRIPTIONS..................................................................................................................... 7
FUNCTIONAL DESCRIPTION ...................................................................................................... 9
5.1 DEVICE IDENTIFICATION ................................................................................................................ 9
5.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET ............................................................. 9
5.2.1
5.2.2
ZL30250—External EEPROM or No EEPROM................................................................................... 10
ZL30251—Internal EEPROM............................................................................................................... 10
5.3 LOCAL OSCILLATOR OR CRYSTAL ................................................................................................ 10
5.3.1
5.3.2
5.3.3
5.3.4
External Oscillator................................................................................................................................ 11
External Crystal and On-Chip Driver Circuit ........................................................................................ 11
Clock Doubler....................................................................................................................................... 12
Ring Oscillator (for System Start-Up)................................................................................................... 12
5.4 INPUT SIGNAL FORMAT CONFIGURATION...................................................................................... 12
5.5 NUMERICALLY CONTROLLED OSCILLATOR / SPREAD SPECTRUM BLOCK (NCO/SS)........................ 13
5.5.1
5.5.2
Numerically Controlled Oscillator (NCO) Mode ................................................................................... 13
Spread-Spectrum Modulation Mode .................................................................................................... 13
5.6 APLL CONFIGURATION ............................................................................................................... 14
5.6.1
5.6.2
5.6.3
APLL Input Selection and Frequency .................................................................................................. 14
APLL Output Frequency....................................................................................................................... 14
APLL Phase Adjustment ...................................................................................................................... 15
5.7 OUTPUT CLOCK CONFIGURATION ................................................................................................ 15
5.7.1
5.7.2
5.7.3
5.7.4
5.7.4.1
5.7.4.2
5.7.4.3
Output Enable, Signal Format, Voltage and Interfacing ...................................................................... 16
Output Frequency Configuration.......................................................................................................... 16
Output Duty Cycle Adjustment............................................................................................................. 17
Output Phase Adjustment and Phase Alignment................................................................................. 17
Phase Adjustment......................................................................................................................... 17
Phase Alignment, Output-to-Output.............................................................................................. 18
Phase Alignment, Input-to-Output ................................................................................................ 19
Output Clock Start and Stop ................................................................................................................ 19
A-to-B Phase Offset Measurement ...................................................................................................... 20
5.7.5
5.7.6
5.8 MICROPROCESSOR INTERFACE ................................................................................................... 23
5.8.1
5.8.2
5.8.3
SPI Slave ............................................................................................................................................. 23
SPI Master (ZL30250 Only) ................................................................................................................. 25
I2C Slave .............................................................................................................................................. 26
5.9 INTERRUPT LOGIC ...................................................................................................................... 28
5.10
5.11
5.12
RESET LOGIC.......................................................................................................................... 29
POWER-SUPPLY CONSIDERATIONS .......................................................................................... 29
AUTO-CONFIGURATION FROM EEPROM .................................................................................. 29
5.12.1 Generating Device Configurations ....................................................................................................... 29
5.12.2 Direct EEPROM Write Mode (ZL30251 Only) ..................................................................................... 30
5.12.3 Holding Other Devices in Reset During Auto-Configuration................................................................ 30
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ZL30250, ZL30251
Data Sheet
5.13
POWER SUPPLY DECOUPLING AND LAYOUT RECOMMENDATIONS............................................... 30
6.
REGISTER DESCRIPTIONS....................................................................................................... 30
6.1 REGISTER TYPES ....................................................................................................................... 30
6.1.1
6.1.2
6.1.3
6.1.4
Status Bits............................................................................................................................................ 30
Configuration Fields ............................................................................................................................. 30
Multiregister Fields............................................................................................................................... 30
Bank-Switched Registers (ZL30251 Only)........................................................................................... 31
6.2 REGISTER MAP .......................................................................................................................... 31
6.3 REGISTER DEFINITIONS .............................................................................................................. 33
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Global Configuration Registers ............................................................................................................ 33
Status Registers................................................................................................................................... 41
APLL Configuration Registers.............................................................................................................. 49
Output Clock Configuration Registers.................................................................................................. 55
Input Clock Configuration Registers .................................................................................................... 61
NCO/Spread-Spectrum Configuration Registers ................................................................................. 61
7.
8.
ELECTRICAL CHARACTERISTICS ........................................................................................... 63
PACKAGE AND THERMAL INFORMATION.............................................................................. 74
8.1 PACKAGE TOP MARK FORMAT..................................................................................................... 74
8.2 THERMAL SPECIFICATIONS.......................................................................................................... 75
9.
MECHANICAL DRAWING .......................................................................................................... 76
10. ACRONYMS AND ABBREVIATIONS......................................................................................... 77
11. DATA SHEET REVISION HISTORY ........................................................................................... 77
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ZL30250, ZL30251
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram ........................................................................................................................... 1
Figure 2 - Ethernet Frequency Synthesis Application ................................................................................................. 5
Figure 3 - PCI Express Frequency Multiplication Application...................................................................................... 5
Figure 4 - Pin Diagram................................................................................................................................................. 6
Figure 5 - Crystal Equivalent Circuit / Recommended Crystal Circuit....................................................................... 11
Figure 6 - APLL Block Diagram ................................................................................................................................. 14
Figure 7 - SPI Read Transaction Functional Timing.................................................................................................. 24
Figure 8 - SPI Write Enable Transaction Functional Timing (ZL30251 Only) ........................................................... 24
Figure 9 - SPI Write Transaction Functional Timing.................................................................................................. 25
Figure 10 – I2C Read Transaction Functional Timing................................................................................................ 27
Figure 11 – I2C Register Write Transaction Functional Timing ................................................................................. 27
Figure 12 – I2C EEPROM Write Transaction Functional Timing (ZL30251 Only) ..................................................... 27
Figure 13 – I2C EEPROM Read Status Transaction Functional Timing (ZL30251 Only) ......................................... 27
Figure 14 – Interrupt Structure................................................................................................................................... 28
Figure 15 - Electrical Characteristics: Clock Inputs................................................................................................... 65
Figure 16 - Example External Components for Differential Input Signals ................................................................. 66
Figure 17 - Electrical Characteristics: CML Clock Outputs........................................................................................ 67
Figure 18 – Example External Components for CML Output Signals ....................................................................... 67
Figure 19 – Example External Components for HCSL Output Signals ..................................................................... 68
Figure 20 - SPI Slave Interface Timing...................................................................................................................... 70
Figure 21 - SPI Master Interface Timing.................................................................................................................... 72
Figure 22 - I2C Slave Interface Timing....................................................................................................................... 73
Figure 23 - Non-customized Device Top Mark.......................................................................................................... 74
Figure 24 - Custom Factory Programmed Device Top Mark..................................................................................... 74
List of Tables
Table 1 - Pin Descriptions............................................................................................................................................ 7
Table 2 - Crystal Selection Parameters..................................................................................................................... 12
Table 3 – SPI Commands.......................................................................................................................................... 23
Table 4 - Register Map .............................................................................................................................................. 31
Table 5 - Recommended DC Operating Conditions.................................................................................................. 63
Table 6 - Electrical Characteristics: Supply Currents ................................................................................................ 63
Table 7 - Electrical Characteristics: Non-clock CMOS Pins ...................................................................................... 64
Table 8 - Electrical Characteristics: XA Clock Input .................................................................................................. 64
Table 9 - Electrical Characteristics: Clock Inputs, ICxP/N......................................................................................... 65
Table 10 - Electrical Characteristics: CML Clock Outputs......................................................................................... 66
Table 11 - Electrical Characteristics: CMOS and HSTL (Class I) Clock Outputs...................................................... 68
Table 12 - Electrical Characteristics: APLL Frequencies .......................................................................................... 68
Table 13 - Electrical Characteristics: Jitter Specifications......................................................................................... 69
Table 14 - Electrical Characteristics: Typical Output Jitter Performance .................................................................. 69
Table 15 - Electrical Characteristics: Typical Input-to-Output Clock Delay............................................................... 69
Table 16 - Electrical Characteristics: Typical Output-to-Output Clock Delay............................................................ 69
Table 17 - Electrical Characteristics: SPI Slave Interface Timing, Device Registers................................................ 70
Table 18 - Electrical Characteristics: SPI Slave Interface Timing, Internal EEPROM (ZL30251 Only) .................... 71
Table 19 - Electrical Characteristics: SPI Master Interface Timing (ZL30250 Only) ................................................. 72
Table 20 - Electrical Characteristics: I2C Slave Interface Timing .............................................................................. 73
Table 21 – Package Top Mark Legend ..................................................................................................................... 74
Table 22 - 5x5mm QFN Package Thermal Properties .............................................................................................. 75
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ZL30250, ZL30251
Data Sheet
1. Application Examples
2x 156.25MHz differential
50MHz
ZL3025x
125MHz CMOS
25MHz CMOS
Frequency synthesis from crystal resonator
Figure 2 - Ethernet Frequency Synthesis Application
25MHz
3x 100MHz differential
ZL3025x
Frequency multiplication from input clock signal
Figure 3 - PCI Express Frequency Multiplication Application
2. Detailed Features
2.1 Input Clock Features
•
•
Four input clocks: one crystal/CMOS, two differential/CMOS, one single-ended/CMOS
Input clocks can be any frequency from 9.72MHz up to 1250MHz (differential) or 300MHz (CMOS)
2.2 APLL Features
•
•
•
•
Very high-resolution fractional (i.e. non-integer) multiplication
Any-to-any frequency conversion with 0ppm error
Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5)
Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter
components
•
Bypass mode supports system testing
2.3 Output Clock Features
•
•
•
•
•
Three low-jitter output clocks
Each output can be one differential output or two CMOS outputs
Output clocks can be any frequency from 1Hz to 1035MHz (250MHz max for CMOS and HSTL outputs)
Output jitter as low as 0.16ps RMS (12kHz to 20MHz integration band)
In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin
(example: OC3P 125MHz, OC3N 25MHz)
•
•
•
•
•
•
•
•
Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components
Can produce PCIe clocks (PCIe gen. 1, 2 and 3)
Sophisticated output-to-output phase alignment
Per-output phase adjustment with high resolution and unlimited range
Per-output enable/disable
Per-output glitchless start/stop (stop high or low)
2.4 General Features
•
•
SPI or I2C serial microprocessor interface
Automatic self-configuration at power-up from external (ZL30250) or internal (ZL30251) EEPROM
memory; pin control to specify one of four stored configurations
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ZL30250, ZL30251
Data Sheet
•
Numerically controlled oscillator (NCO) mode allows system software to steer frequency with resolution
better than 0.01ppb
•
•
•
Spread-spectrum modulation mode (meets PCI Express requirements)
Four general-purpose I/O pins each with many possible status and control options
Reference can be fundamental-mode crystal, low-cost XO or clock signal from elsewhere in the system
2.5 Evaluation Software
•
•
•
•
•
•
Simple, intuitive Windows-based graphical user interface
Supports all device features and register fields
Makes lab evaluation of the ZL30250 or ZL30251 quick and easy
Generates configuration scripts to be stored in external (ZL30250) or internal (ZL30251) EEPROM
Generates full or partial configuration scripts to be run on a system processor
Works with or without a ZL30250 or ZL30251 evaluation board
3. Pin Diagram
The device is packaged in a 5x5mm 32-pin QFN.
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
IF1/MISO
SDA/MOSI
DVDD33
IC3/GPIO3
IC2N
OC1P
OC1N
AVDD33
OC2N
OC2P
IC2P
VDDO2
AVDD18
AVDD18
GND (E-pad)
IC1N
IC1P
9
10
11
12
13
14
15
16
Figure 4 - Pin Diagram
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ZL30250, ZL30251
Data Sheet
4. Pin Descriptions
All device inputs and outputs are LVCMOS unless described otherwise. The Type column uses the following
symbols: I – input, IPU – input with 50k internal pullup resistor, O – output, A – analog, P – power supply pin. All
GPIO and SPI/I2C interface pins have Schmitt-trigger inputs and have output drivers that can be disabled (high
impedance).
Table 1 - Pin Descriptions
Pin #
Name
Type
Description
Input Clock Pins
Differential or Single-ended signal format. Programmable frequency.
Differential: See Table 9 for electrical specifications, and see Figure 16 for
recommended external circuitry for interfacing these differential inputs to
LVDS, LVPECL, CML or HSCL output pins on neighboring devices.
Single-ended: For input signal amplitude >2.5V, connect the signal directly to
ICxP pin. For input signal amplitude ≤2.5V, AC-coupling the signal to ICxP
is recommended. Connect the N pin to a capacitor (0.1F or 0.01F) to
VSS. As shown in Figure 16, the ICxP and ICxN pins are internally biased to
approximately 1.3V. Treat the ICxN pin as a sensitive node; minimize stubs;
do not connect to anything else including other ICxN pins.
8
7
6
5
4
IC1P
IC1N
IC2P
I
I
I
IC2N
I
IC3P/GPIO3
I/O
Unused: Set ICEN.ICxEN=0. The ICxP and ICxN pins can be left floating.
Note that the IC3N pin is not bonded out. A differential signal can be
connected to IC3P by AC-coupling the POS trace to IC3P and terminating the
signal on the driver side of the coupling cap. If not needed as an input clock
pin, IC3P can behave as general-purpose I/O pin GPIO3, which is configured
by GPIOCR2. Its state is indicated in GPIOSR.
Crystal or Input Clock Pins
Crystal: MCR1.XAB=01. An on-chip crystal driver circuit is designed to work
with an external crystal connected to the XA and XB pins. See section 5.3.2
for crystal characteristics and recommended external components.
10
11
XA
XB
A / I
Input Clock: MCR1.XAB=10. An external local oscillator or clock signal can be
connected to the XA pin. The XB pin must be left unconnected.
Output Clock Pins
24
23
20
21
15
14
OC1P
OC1N
OC2P
OC2N
OC3P
OC3N
CML, HSTL or 1 or 2 CMOS. Programmable frequency and drive strength.
See Table 10 and Figure 18 for electrical specifications and recommended
external circuitry for interfacing to LVDS, LVPECL or CML input pins on
neighboring devices.
See Table 11 for electrical specifications for interfacing to CMOS and HSTL
inputs on neighboring devices.
O
See Figure 19 for recommended external circuitry for interfacing to HCSL inputs
on neighboring devices.
Reset (Active Low)
When this global asynchronous reset is pulled low, all internal circuitry is reset
to default values. The device is held in reset as long as RSTN is low. See
section 5.10.
IPU
30
RSTN
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ZL30250, ZL30251
Data Sheet
Table 1 - Pin Descriptions (continued)
Pin #
Name
Type
Description
Auto-Configure [1:0] / General Purpose I/O 0 and 1
Auto Configure: On the rising edge of RSTN these pins behave as AC[1:0] and
specify one of the configurations stored in EEPROM. See section 5.2.
28
27
AC0/GPIO0
AC1/GPIO1
I/O
General-Purpose I/O: After reset these pins are GPIO0 and GPIO1. GPIOCR1
configures the pins. Their states are indicated in GPIOSR.
Factory Test / General Purpose I/O 2
Factory Test: On the rising edge of RSTN the pin behaves as TEST. Factory
test mode is enabled when TEST is high. For normal operation TEST must be
low on the rising edge of RSTN.
26
TEST/GPIO2
I/O
General-Purpose I/O: After reset this pin is GPIO2. GPIOCR2 configures the
pin. It state is indicated in GPIOSR.
Interface Mode 0 / SPI Chip Select (Active Low)
Interface Mode: On the rising edge of RSTN the pin behaves as IF0 and,
together with IF1, specifies the interface mode for the device. See section 5.2.
32
IF0/CSN
I/O
SPI Chip Select: After reset this pin is CSN. When the device is configured as
a SPI slave, an external SPI master must assert (low) CSN to access device
registers. When the device is configured as a SPI master (ZL30250 only), the
device asserts CSN to access an external SPI EEPROM during auto-
configuration.
I2C Clock / SPI Clock
I2C Clock: When the device is configured as an I2C slave, an external I2C
master must provide the I2C clock signal on the SCL pin. Note that I2C requires
an external pullup resistor on this signal. See the I2C specification for details.
31
SCL/SCLK
I/O
SPI Clock: When the device is configured as a SPI slave, an external SPI
master must provide the SPI clock signal on SCLK. When the device is
configured as a SPI master(ZL30250 only), the device drives SCLK as an
output to clock accesses to an external SPI EEPROM during auto-
configuration.
Interface Mode 1 / SPI Master-In-Slave-Out
Interface Mode: On the rising edge of RSTN the pin behaves as IF1 and,
together with IF0, specifies the interface mode for the device. See section 5.2.
SPI MISO: After reset this pin is MISO. When the device is configured as a SPI
slave, the device outputs data to an external SPI master on MISO during SPI
read transactions. When the device is configured as a SPI master (ZL30250
only), the device receives data on MISO from an external SPI EEPROM during
auto-configuration.
1
2
IF1/MISO
I/O
I/O
Note: On rev A parts, in I2C interface mode this pin toggles between driving low and high-
impedance during register accesses. Therefore in I2C mode this pin must not be wired directly to
VDD. To implement a static high value on IF1/MISO, wire it to VDD through a resistor
(approximately 10k recommended).
I2C Data / SPI Master-Out-Slave-In
I2C Data: When the device is configured as an I2C slave, SDA is the
bidirectional data line between the device and an external I2C master. Note
that I2C requires an external pullup resistor on this signal. See the I2C
SDA/MOSI
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ZL30250, ZL30251
Data Sheet
Pin #
Name
Type
Description
specification for details.
SPI MOSI: When the device is configured as a SPI slave, an external SPI
master sends commands, addresses and data to the device on MOSI. When
the device is configured as a SPI master (ZL30250 only), the device sends
commands, addresses and data on MOSI to an external SPI EEPROM during
auto-configuration.
Table 1 - Pin Descriptions (continued)
Pin #
Name
Type
Description
12
13
17
18
22
29
3
25
19
16
9
AVDD18
P
Analog Power Supply. 1.8V 5%.
AVDD33
DVDD18
DVDD33
VDDO1
VDDO2
VDDO3
VDDXO33
VSS
P
P
P
P
P
P
P
P
Analog Power Supply. 3.3V 5%.
Digital Power Supply. 1.8V 5%.
Digital Power Supply. 3.3V 5%.
Output OC1 Power Supply. 1.5V to 3.3V ±5%.
Output OC2 Power Supply. 1.5V to 3.3V ±5%.
Output OC3 Power Supply. 1.5V to 3.3V ±5%.
Analog Power Supply for Crystal Driver Circuitry. 3.3V 5%.
Ground. 0 Volts.
E-pad
5. Functional Description
5.1 Device Identification
The 12-bit read-only ID field and the 4-bit revision field are found in the ID1 and ID2 registers. Contact the factory
to interpret the revision value and determine the latest revision.
5.2 Pin-Controlled Automatic Configuration at Reset
The device configuration is determined at reset (i.e. on the rising edge of RSTN) by the signal levels on five device
pins: TEST/GPIO2, AC1/GPIO1, AC0/GPIO0, IF1/MISO and IF0/CSN. For each of these pins, the first name
(TEST, AC1, AC0, IF1, IF0) indicates their function when they are sampled by the rising edge of the RSTN pin. The
second name refers to their function after reset. The values of these pins are latched into the CFGSR register when
RSTN goes high. To ensure the device properly samples the reset values of these pins, the following guidelines
should be followed:
1. Any pullup or pulldown resistors used to set the value of these pins at reset should be 1k.
2. RSTN must be asserted at least as long as specified in section 5.10.
The hardware configuration pins are grouped into three sets:
1. TEST - Manufacturing test mode
2. IF[1:0] – Microprocessor interface mode and I2C address
3. AC[1:0] – Auto-configuration from EEPROM
The TEST pin selects manufacturing test modes when TEST=1 (the AC[1:0] pins specify the test mode). For
ZL30251, TEST=1 and AC[1:0]=00 configures the part so that production SPI EEPROM programmers can program
the internal EEPROM (see section 5.12.2). For more information about auto-configuration from EEPROM see
section 5.12.1.
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5.2.1 ZL30250—External EEPROM or No EEPROM
Data Sheet
For the ZL30250 the IF[1:0] pins specify the processor interface mode and the I2C slave address. When IF[1:0]=11
(SPI) two options are available:
If AC[1:0]=00 the device sets up its processor interface as SPI slave through which it can be
configured by software running on the SPI master. In this option the device cannot auto-configure
from an external EEPROM.
If AC[1:0]=01, 10, or 11 the device first sets up its processor interface as a SPI master. It then
auto-configures itself by reading the configuration number specified by AC[1:0] from an external
SPI EEPROM connected to its SPI pins. After auto-configuration is complete, the device
reconfigures its processor interface to be SPI slave.
These options are summarized in the following table:
IF1
0
0
1
1
1
1
1
IF0 AC1 AC0
Processor Interface
I2C, slave address 11011 00
I2C, slave address 11011 01
I2C, slave address 11011 10
SPI Slave
External EEPROM
Auto Configuration
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
No
No
No
n/a
n/a
n/a
No
n/a
Yes
Yes
Yes
Configuration 1
Configuration 2
Configuration 3
SPI Master to external EEPROM for
auto-configuration then SPI Slave
Notes about the device auto-configuring from external EEPROM:
1. The device’s CSN pin must have a pull-up resistor to VDD to ensure its processor interface is inactive after
auto-configuration is complete. The SCLK, MISO and MOSI pins should also have pull-up resistors to VDD
to keep them from floating.
2. If a processor or similar device will access device registers after the device has auto-configured from
external EEPROM, the SPI SCLK, MOSI and MISO wires can be connected directly to the processor, the
device and the external EEPROM. The processor and device CSN pins can be wired together also. The
EEPROM CSN signal must be controlled by the device’s CSN pin during device auto-configuration and
then held inactive when the processor accesses device registers.
5.2.2 ZL30251—Internal EEPROM
For the ZL30251 the IF[1:0] pins specify the processor interface mode and the I2C slave address. The AC[1:0] pins
specify which of four device configurations in the EEPROM to execute after reset.
IF1
0
0
1
1
IF0
0
1
0
1
Processor Interface
I2C, slave address 11011 00
I2C, slave address 11011 01
I2C, slave address 11011 10
SPI Slave
AC1
AC0
Auto Configuration
Configuration 0
Configuration 1
Configuration 2
Configuration 3
0
0
1
1
0
1
0
1
5.3 Local Oscillator or Crystal
Section 5.3.1 describes how to connect an external oscillator and the required characteristics of the oscillator.
Section 5.3.2 describes how to connect an external crystal to the on-chip crystal driver circuit and the required
characteristics of the crystal.
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Data Sheet
5.3.1 External Oscillator
A signal from an external oscillator can be connected to the XA pin (XB must be left unconnected). Table 8
specifies the range of possible frequencies for the XA input. To minimize jitter, the signal must be properly
terminated and must have very short trace length. A poorly terminated single-ended signal can greatly increase
output jitter, and long single-ended trace lengths are more susceptible to noise. When MCR1.XAB=10, XA is
enabled as a single-ended input.
While the stability of the external oscillator can be important, its absolute frequency accuracy is less important
because any known frequency inaccuracy of the oscillator can be compensated. When the device is configured for
NCO or spread-spectrum operation, the DFREQZ parameter can be used to compensate for oscillator frequency
error. When the device is configured for APLL-only mode, the APLL's fractional feedback divider value (AFBDIV)
can be adjusted by ppb or ppm to compensate for oscillator frequency error.
The jitter on output clock signals depends on the phase noise and frequency of the external oscillator. For the
device to operate with the lowest possible output jitter, the external oscillator should have the following
characteristics:
•
•
Phase Jitter: less than 0.1ps RMS over the 12kHz to 5MHz integration band
Frequency: The higher the better, all else being equal
5.3.2 External Crystal and On-Chip Driver Circuit
The on-chip crystal driver circuit is designed to work with a fundamental mode, AT-cut crystal resonator. See Table
2 for recommended crystal specifications. To enable the crystal driver, set MCR1.XAB=01.
See Figure 5 for the crystal equivalent circuit and the recommended external capacitor connections. To achieve a
crystal load (CL) of 10pF, an external 16pF is placed in parallel with the 4pF internal capacitance of the XA pin, and
an external 16pF is placed in parallel with the 4pF internal capacitance of the XB pin. The crystal then sees a load
of 20pF in series with 20pF, which is 10pF total load. Note that the 16pF capacitance values in Figure 5 include all
capacitance on those nodes. If, for example, PCB trace capacitance between crystal pin and IC pin is 2pF then
14pF capacitors should be used to make 16pF total.
The crystal, traces, and two external capacitors should be placed on the board as close as possible to the XA and
XB pins to reduce crosstalk of active signals into the oscillator. Also no active signals should be routed under the
crystal circuitry.
Note: Crystals have temperature sensitivies that can cause frequency changes in response to ambient temperature
changes. In applications where significant temperature changes are expected near the crystal, it is recommended
that the crystal be covered with a thermal cap, or an external XO or TCXO should be used instead.
XTAL
4pF
C1
XA
R1
1M
CO
LS
Crystal
(CL = 10pF)
XB
R2
4pF
CS
C2
RS
The optimal values of C1, C2 and R2 depend on PCB capacitance and crystal
frequency and power rating. See application note ZLAN-494 for calculations.
Figure 5 - Crystal Equivalent Circuit / Recommended Crystal Circuit
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Table 2 - Crystal Selection Parameters
Parameter
Crystal oscillation frequency1
Shunt capacitance
Symbol
fOSC
Min.
25
Typ.
Max.
60
5
Units
MHz
pF
CO
2
Load capacitance
CL
10
pF
Equivalent series resistance
fOSC < 40MHz
fOSC > 40MHz
RS
RS
60
50
(ESR)2
Maximum crystal drive level
Note 1: Higher frequencies give lower output jitter, all else being equal.
100
W
Note 2: These ESR limits are chosen to constrain crystal drive level to less than 100W. If the crystal can tolerate a drive level greater than
100W then proportionally higher ESR is acceptable.
Parameter
Symbol
Min.
Typ.
Max.
Units
ppm per 10%
in VDD
Crystal Frequency Stability vs. Power Supply
fFVD
0.2
0.5
Any known frequency inaccuracy of the crystal can be compensated in the APLL by adjusting the APLL's fractional
feedback divider value (AFBDIV) by ppb or ppm to compensate for crystal frequency error.
5.3.3 Clock Doubler
Figure 1 shows an optional clock doubler (“x2” block) following the crystal driver block. The doubler, which is
enabled by setting MCR1.DBL=1, can be used to double the frequency of the internal crystal driver circuit or an
clock signal on the XA pin. The following table shows scenarios when the clock doubler can be used.
Device Mode
With Crystal
Maybe1
Yes
With XO or Clock Signal
APLL, Integer Multiply
APLL, Fractional Multiply
NCO
Maybe1
Yes
Yes
Yes
Spread-Spectrum
Yes
Yes
Note 1: For APLL integer multiplication, use of the doubler is application-dependent. On the positive side, use of the
doubler reduces random jitter. On the negative side, the doubler causes a large spur at the XA frequency (but this spur
may be outside the band of interest for the application).
5.3.4 Ring Oscillator (for System Start-Up)
To ensure that registers can be written immediately after system start-up, in its power-on reset state the device
operates its registers and processor interface from an internal ring oscillator.
When operating the device in NCO mode or spread spectrum mode, as soon as the external oscillator connected
to the XA pin has stabilized and is ready to use, the MCR1.MCSEL bit must be set to source the NCO/SS master
clock from XA. If the ring oscillator causes undesirable spurs it can be disabled (powered down) by setting
MCR1.ROSCD=1.
When operating the part in APLL-only mode, a master clock signal on the XA pin is not required, and the ring
oscillator is left enabled to provide a clock for the processor interface logic and registers.
5.4 Input Signal Format Configuration
Input clocks IC1, IC2 and IC3 are enabled by setting the enable bits in the ICEN register. The power consumed by
a differential receiver is shown in Table 6. The electrical specifications for these inputs are listed in Table 9. Each
input clock can be configured to accept nearly any differential signal format by using the proper set of external
components (see Figure 16). To configure these differential inputs to accept single-ended CMOS signals, connect
the single-ended signal to the ICxP pin, and connect the ICxN pin to a capacitor (0.1F or 0.01F) to VSS. Each
ICxP and ICxN pin is internally biased to approximately 1.3V. If an input is not used, both ICxP and ICxN pins can
be left floating. Note that the IC3N pin is not present. A differential signal can be connected to IC3P by AC-coupling
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the POS trace to IC3P and terminating the signal on the driver side of the coupling cap. If not needed as an input
clock pin, IC3P can behave as general-purpose I/O pin GPIO3.
5.5 Numerically Controlled Oscillator / Spread Spectrum Block (NCO/SS)
The NCO/SS block allows the device to behave as a numerically controlled oscillator and optionally perform
spread-spectrum frequency modulation. This block is enabled by setting PLLEN.NCSSEN=1 and is the input
reference for the APLL when APLLCR3.APLLMUX=11x. The NCO/SS block requires a clock signal from an
external oscillator connected to the XA pin (see section 5.3.1). Table 8 shows the allowable frequency range for the
XA signal. Note that device output jitter increases as XA frequency decreases.
5.5.1 Numerically Controlled Oscillator (NCO) Mode
The NCO/SS block operates in NCO mode when NCSSCR1.MODE=0001. In this mode system software controls
the NCO/SS block by controlling the value of the 40-bit FREQZ field in the DFREQZ registers. The resolution of
frequency control is better than 0.01ppb.
The nominal FREQZ value, hereafter referred to as FREQZ0, is computed by the evaluation software for the
desired device configuration When the FREQZ field is set to the FREQZ0 value, the device’s output clock
frequencies have a fractional frequency offset of zero with respect to the NCO master clock signal applied to the
XA pin.
(Fractional frequency offset (FFO) is defined as (actual_frequency – nominal_frequency) / nominal_frequency. FFO
is a unitless number but is typically expressed in parts per billion (ppb), parts per million (ppm) or percent.)
To control the NCO, system software first reads the FREQZ0 value from the device. FREQZ0 is a 40-bit unsigned
integer.
To change the NCO frequency to a specific FFO (in ppm), system software calculates newFREQZ (a 40-bit
unsigned integer) as follows:
newFREQZ = round(FREQZ0 * (1 + FFO/1e6))
System software then writes the newFREQZ value directly to the FREQZ field in the DFREQZ registers.
Note that any subsequent frequency changes are calculated using the same equation from the original FREQZ0
value and are not a function of the previous newFREQZ value. The value of newFREQZ should be kept within
±1000ppm of FREQZ0 and within ±500ppm of the previous newFREQZ value to avoid causing the APLL to lose
lock. If spread spectrum modulation is also in use, the total frequency change caused by spread spectrum
modulation and NCO control should be kept within ±5000ppm of FREQZ0 to avoid causing the APLL to lose lock.
5.5.2 Spread-Spectrum Modulation Mode
For EMI-sensitive applications such as PCI Express, the device can perform spread spectrum modulation (SSM).
In SSM the frequency of the output clock is continually varied over a narrow frequency range to spread the energy
of the signal and thereby reduce EMI. This mode is a special case of NCO mode.
The NCO/SS block operates in spread spectrum mode when NCSSCR1.MODE=0010. In this mode the NCO/SS
block performs frequency modulation starting from a base frequency offset specified in the 40-bit FREQZ field in
the DFREQZ registers. The frequency modulation is triangle-wave center-spread of up to ±0.5% deviation from the
center frequency with modulation rate configurable from 25kHz to 55kHz. The nominal value of FREQZ and the
spread configuration register values are determined by the evaluation software.
Down-spread applications can be supported by converting them into center-spread. This is done by setting the
NCO/SS block’s center frequency to be the center of the modulation range rather than the high end of range. For
example, 100MHz with -1% downspread can be converted into ±0.5% center spread with center frequency of
100MHz/1.005=99.502488MHz.
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In PCI Express applications the device can be used as a “point of load” spread-spectrum generator. In such an
application, the 100MHz PCI Express clock signal without SSM can be generated centrally and distributed to
various points in the system. A device positioned at one of those points can accept the 100MHz signal on its XA pin
and generate multiple 100MHz signals on its outputs. System software can then choose to enable or disable SSM
in the device as needed to suit the needs of the application.
5.6 APLL Configuration
5.6.1 APLL Input Selection and Frequency
The APLL can lock to any of inputs IC1 through IC3, a clock signal on XA (optionally clock-doubled), or the crystal
driver circuit (optionally clock-doubled) when a crystal is connected to XA and XB. The APLL can also lock to the
output of the NCO/SS block (see section 5.5).
The input to the APLL can be controlled by a GPIO pin or by the APLLCR3.APLLMUX register field. When
APLLCR3.EXTSW=0, the APLLCR3.APLLMUX register field controls the APLL input mux.
When APLLCR3.EXTSW=1, a GPIO pin controls the APLL input mux. When the GPIO pin is low, the mux selects
the input specified by APLLCR3.APLLMUX. When the GPIO pin is high, the mux selects the input specified by
APLLCR3.ALTMUX. MCR2.EXTSS specifies which GPIO pin controls this behavior.
In APLL-only mode, the frequencies of all enabled input clocks (ICx and XA) must divide to a common APLL
phase-frequency detector (PFD) frequency from 9.72MHz to 156.25MHz. In this mode the input high-speed
dividers (ICxCR1.HSDIV) can be used to divide the ICx frequencies by 1, 2, 4 or 8. The XA pin does not have an
internal divider, and, therefore, if XA is an enabled input clock then the XA frequency sets the APLL common PFD
frequency. The polarity of an ICx input signal can be inverted by setting ICxCR1.POL.
5.6.2 APLL Output Frequency
APLL
APLLCR2.HSDIV1[3:0]
Phase/
Freq
Detector
Clock to
Output
Dividers
VCO
3.715- 4.18
GHz
Loop
Filter
High-Speed
Divider 1
Clock from APLL
Input Muxes
(whole ÷ 4-15,
half ÷ 4.5-7.5)
Feedback
Divider
(fractional)
Clock to
Output
Dividers
High-Speed
Divider 2
Input Frequency Range:
9.72MHz to 156.25MHz
AFBDIV[74:0], AFBREM,
AFBDEN, AFBBP
APLLCR2.HSDIV2[3:0]
Figure 6 - APLL Block Diagram
The APLL is enabled when PLLEN.APLLEN=1. The APLL has a fractional-N architecture and therefore can
produce output frequencies that are either integer or non-integer multiples of the input clock frequency. Figure 6
shows a block diagram of the APLL, which is built around an ultra-low-jitter multi-GHz VCO. Register fields
AFBDIV, AFBREM, AFBDEN and AFBBP configure the frequency multiplication ratio of the APLL. The
APLLCR2.HSDIV1 and HSDIV2 fields specify how the VCO frequency is divided down by the high-speed dividers.
Dividing by six is the typical setting to produce 622.08MHz for SDH/SONET or 625MHz for Ethernet applications.
Internally, the exact APLL feedback divider value is expressed in the form AFBDIV + AFBREM / AFBDEN *
2-(33-AFBBP). This feedback divider value must be chosen such that APLL_input_frequency * feedback_divider_value
is in the operating range of the VCO (as specified in Table 12). The AFBDIV term is a fixed-point number with 9
integer bits and a configurable number of fractional bits (up to 33, as specified by AFBBP). Typically AFBBP is set
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to 9 to specify that AFBDIV has 33 – 9 = 24 fractional bits. Using more than 24 fractional bits does not yield a
detectable benefit. Using less than 12 fractional bits is not recommended.
The following equations show how to calculate the feedback divider values for the situation where the APLL should
multiply the APLL input frequency by integer M and also fractionally scale by the ratio of integers N / D. In other
words, VCO_frequency = input_frequency * M * N / D. An example of this is multiplying 77.76MHz by M=48 and
scaling by N / D = 255 / 237 for forward error correction applications.
AFBDIV = trunc(M * N / D * 224)
lsb_fraction = M * N / D * 224 – AFBDIV
AFBDEN = D
(1)
(2)
(3)
(4)
(5)
AFBREM = round(lsb_fraction * AFBDEN)
AFBBP = 33 – 24 = 9
The trunc() function returns only the integer portion of the number. The round() function rounds the number to the
nearest integer. In Equation (1), AFBDIV is set to the full-precision feedback divider value, M * N / D, truncated
after the 24th fractional bit. In Equation (2) the temporary variable 'lsb_fraction' is the fraction that was truncated in
Equation (1) and therefore is not represented in the AFBDIV value. In Equation (3), AFBDEN is set to the
denominator of the original M * N / D ratio. In Equation (4), AFBREM is calculated as the integer numerator of a
fraction (with denominator AFBDEN) that equals the 'lsb_fraction' temporary variable. Finally, in Equation (5)
AFBBP is set to 33 – 24 = 9 to correspond with AFBDIV having 24 fractional bits.
When a fractional scaling scenario involves multiplying an integer M times multiple scaling ratios N1 / D1 through
Nn / Dn, the equations above can still be used if the numerators are multiplied together to get N = N1 x N2 x … x Nn
and the denominators are multiplied together to get D = D1 x D2 x … x Dn.
The easiest way to calculate the exact values to write to the APLL registers is to use the ZL3025x evaluation
software, available on the Microsemi website. This software can be used even when no evaluation board is
attached to the computer.
Note: After the APLL's feedback divider settings are configured in register fields AFBDIV, AFBREM, AFBDEN and
AFBBP, the APLL enable bit PLLEN.APLLEN should be changed from 0 to 1 to cause the APLL to reacquire lock
with the new settings. The real-time lock/unlock status of the APLL is indicated by APLLSR.ALK and ALK2.
5.6.3 APLL Phase Adjustment
The phase of the APLL’s output clock can be incremented or decremented by 1/8th of a VCO cycle. This phase
step size is 30ps at maximum VCO frequency of 4180MHz and 33.7ps at minimum VCO frequency of 3715MHz.
The APLLCR4.PDSS field specifies the phase decrement control signal, which can be the APLLCR4.DECPH bit or
any of the four GPIOs. The APLLCR4.PISS field specifies the phase increment control signal, which can be the
APLLCR4.INCPH bit or any of the four GPIOs. Phase is adjusted on every rising edge and every falling edge of the
control signal. This phase adjustment affects the output of both high-speed dividers.
5.7 Output Clock Configuration
The device has three output clock signal pairs. Each output has individual divider, enable and signal format
controls. In CMOS mode each signal pair can become two CMOS outputs, allowing the device to have up to six
output clock signals. Also in CMOS mode, the OCxN pin can have an additional divider allowing the OCxN
frequency to be an integer divisor of the OCxP frequency (example: OC3P 125MHz and OC3N 25MHz). The
outputs can be aligned relative to each other and relative to an input signal, and the phases of output signals can
be adjusted dynamically with high resolution and infinite range.
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5.7.1 Output Enable, Signal Format, Voltage and Interfacing
To use an output, the output driver must be enabled by setting OCxCR2.OCSF0, and the per-output dividers must
be enabled by setting the appropriate bit in the OCEN register. The per-output dividers include the medium-speed
divider, the low-speed divider and the associated phase adjustment/alignment circuitry and start/stop logic.
Using the OCxCR2.OCSF register field, each output pair can be disabled or configured as a CML output, an HSTL
output, or one or two CMOS outputs. When an output is disabled it is high impedance, and the output driver is in a
low-power state. In CMOS mode, the OCxN pin can be disabled, in phase or inverted vs. the OCxP pin. In CML
mode the normal 800mV VOD differential voltage is available as well as a half-swing 400mV VOD. All of these
options are specified by OCxCR2.OCSF. The clock to the output driver can inverted by setting OCxCR2.POL=1.
The CMOS/HSTL output driver can be set to any of four drive strengths using OCxCR2.DRIVE.
Each output has its own power supply pin to allow CMOS or HSTL signal swing from 1.5V to 3.3V for glueless
interfacing to neighboring components. If OCSF is set to HSTL mode then a 1.5V power supply voltage should be
used to get a standards-compliant HSTL output. Note that differential (CML) outputs must have a power supply of
3.3V.
The differential outputs can be easily interfaced to LVDS, LVPECL, CML, HCSL, HSTL and other differential inputs
on neighboring ICs using a few external passive components. See Figure 18 for examples.
5.7.2 Output Frequency Configuration
The frequency of each output is determined by the configuration of the APLL, the high-speed dividers and the per-
output dividers. Each output can be connected to either high-speed divider 1 (HSDIV1) or 2 (HSDIV2) using the
OCxCR3.DIVSEL field.
Each output has two output dividers, a 7-bit medium-speed divider (OCxCR1.MSDIV) and a 25-bit low-speed
output divider (LSDIV field in the OCxDIV registers). These dividers are in series, medium-speed divider first then
output divider. These dividers produce signals with 50% duty cycle for all divider values including odd numbers.
The low-speed divider can only be used if the medium-speed divider is used (i.e. OCxCR1.MSDIV>0). The
maximum input frequency to the medium-speed divider is 850MHz. The maximum input frequency to the low-speed
divider is 425MHz.
Since each output has its own independent dividers, the device can output families of related frequencies that have
an APLL HSDIV output frequency as a common multiple. For example, for Ethernet clocks, a 625MHz HSDIV
output clock can be divided by four for one output to get 156.25MHz, divided by five for another output to get
125MHz, and divided by 25 for another output to get 25MHz. Similarly, for SDH/SONET clocks, a 622.08MHz
HSDIV output clock can be divided by 4 to get 155.52MHz, by 8 to get 77.76MHz, by 16 to get 38.88MHz or by 32
to get 19.44MHz.
Two Different Frequencies in 2xCMOS Mode
When an output is in 2xCMOS mode it can be configured to have the frequency of the OCxN clock be an integer
divisor of the frequency of the OCxP clock. Examples of where this can be useful:
•
•
•
125MHz on OCxP and 25MHz on OCxN for Ethernet applications
77.76MHz on OCxP and 19.44MHz on OCxN for SONET/SDH applications
25MHz on OCxP and 1Hz (i.e. 1PPS) on OCxN for telecom applications with Synchronous Ethernet and
IEEE1588 timing
An output can be configured to operate like this by setting the LSDIV value in the OCxDIV registers to OCxP_freq /
OCxN_freq - 1 and setting OCxCR3.LSSEL=0 and OCxCR3.NEGLSD=1. Here are some notest about this dual-
frequency configuration option:
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•
•
In this mode only the medium speed divider is used to create the OCxP frequency. The low-
speed divider is then used to divide the OCxP frequency down to the OCxN frequency. This
means that the lowest OCxP frequency is the high-speed divider output frequency divided by 128.
An additional constraint is that the medium-speed divider must be configured to divide by 6 or
more (i.e. must have OCxCR1.MSDIV5).
5.7.3 Output Duty Cycle Adjustment
For output frequencies less than or equal to 141.666MHz, the duty cycle of the output clock can be modified using
the OCxDC.OCDC register field. This behavior is only available when MSDIV>0 and LSDIV > 1. When OCDC = 0
the output clock is 50%. Otherwise the clock signal is a pulse with a width of OCDC number of MSDIV output clock
periods. The range of OCDC can create pulse widths of 1 to 255 MSDIV output clock periods. When
OCxCR2.POL=0, the pulse is high and the signal is low the remainder of the cycle. When POL=1, the pulse is low
and the signal is high the remainder of the cycle.
Note that duty cycle adjustment is done in the low-speed divider. Therefore when OCxCR3.LSSEL=0 the duty
cycle of the output is not affected. Also, when a CMOS output is configured with OCxCR3.LSSEL=0 and
OCxCR3.NEGLSD=1, the OCxN pin has duty cycle adjustment but the OCxP pin does not. This allows a higher-
speed 50% duty cycle clock signal to be output on the OCxP pin and a lower-speed frame/phase/time pulse (e.g.
2kHz, 8kHz or 1PPS) to be output on the OCxN pin at the same time.
An output configured for CMOS or HSTL signal format should not be configured to have a duty cycle with high time
shorter than 2ns or low time shorter than 2ns.
5.7.4 Output Phase Adjustment and Phase Alignment
The device has flexible, high-resolution tools for managing the phases of the output clocks relative to one another.
The key register fields for this are found in the PACR1 and PACR2 global configuration registers and the per-output
OCxPH register.
Phase alignment and phase adjustment are done in the medium-speed dividers. Resoution is 0.5 periods (also
known as unit intervals or UI) of the high-speed divider (HSDIV) output clock. For example, for an HSDIV output
frequency of 800MHz, resolution is 625ps.
5.7.4.1 Phase Adjustment
A phase adjustment is a phase change for an output relative to that output’s most recent phase. To cause the
device to perform phase adjustment of an output clock, set PACR1.MODE=1, set OCxCR1.PHEN=1 to enable the
output for phase adjustment, and write the phase adjustment amount to the output’s OCxPH register. Then an
arm/trigger methodology is used to cause the phase adjustment to happen.
The arm step tells the device that it is enabled to perform the phase adjustment when it sees the trigger stimulus.
The source of the arm signal is specified by PACR2.ARMSRC. Options include the 0-to-1 transition of the
PACR1.ARM bit, APLL transition from unlocked to locked, or a transition on one of the GPIO pins.
The source of the trigger signal is specified by PACR2.TRGSRC. Options include 0-to-1 transition of the
PACR1.TRIG bit, APLL transition from unlocked to locked, or a transition on one of the GPIO pins. The trigger
signal can be inverted by setting PACR1.TINV. With TINV=1, the same GPIO signal can arm on one edge and
trigger on the opposite edge.
Any combination of outputs can be phase adjusted by the same trigger, and each output can be adjusted by a
different amount. Only outputs with OCxCR1.PHEN=1 and OCxPH.PHADJ0 have their phases adjusted.
There are a few constraints on the range of possible phase adjustments. These have to do with the output’s
medium-speed divider value.
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1) Phase adjustment is not available unless OCxCR1.MSDIV>0.
2) The largest negative phase adjustment magnitude in HSDIV periods is:
If OCxCR1.MSDIV is odd: (OCxCR1.MSDIV – 1) / 2
If OCxCR1.MSDIV is even: (OCxCR1.MSDIV – 2) / 2
3) The largest positive phase adjustment in HSDIV periods is:
If OCxCR1.MSDIV is odd: (127 – OCxCR1.MSDIV) / 2
If OCxCR1.MSDIV is even: (128 – OCxCR1.MSDIV) / 2
The implications of constraints 2) and 3) are shown in this table:
Largest Negative
Largest Positive
Phase Adjust,
Phase Adjust,
OCxCR1.MSDIV
1 or 2
HSDIV periods
HSDIV periods
Notes
no negative adjustment
0
1
2
…
61
62
63
63
62
61
…
2
3 or 4
5 or 6
…
123 or 124
125 or 126
127
1
0
no positive adjustment
During a phase adjustment the MSDIV output period is changed for one period. The MSDIV output signal during
that period will have longer high time (unless inverted) during a positive phase adjustment and shorter high time
(unless inverted) during a negative phase adjustment. With negative phase adjustments care must be taken to not
shorten the high time of the output clock signal to be too short for the components that receive the clock. There are
several possible ways to avoid this issue including: (1) using small negative adjustments such as -0.5UI repeatedly
instead of one larger negative adjustment, (2) using positive adjustments to “wrap around” to the desired negative
adjustment, or (3) holding the components that receive the clock in reset during the phase adjustment.
An armed phase adjustment can be canceled before the trigger occurs by setting the PACR1.RST bit.
The PASR register has real-time status bits indicating whether a phase adjustment is armed and waiting for a
trigger (ARMED bit) or in progress (BUSY bit). It also has a latched status bit (ADJL bit) to indicate the adjustment
has completed.
Example: +1.0 HSDIV period phase adjustment for output OC1 using ARM and TRIG register bits:
OC1CR1.PHEN=1
(Enable phase adjust on OC1)
OC1PH.PHADJ=00000010 (Specify +1.0 HSDIV period phase adjustment)
PACR1.MODE=1
PACR2.ARMSRC=0001
PACR2.TRGSRC=0000
PACR1.RST=1
(Phase adjustment mode)
(arm signal is PACR1.ARM bit)
(trigger signal is PACR1.TRIG bit)
(reset phase adjust/align state machine after changing ARMSRC)
(arm for phase adjust)
PACR1.ARM=1
PACR1.TRIG=1
(do the phase adjust: add +1.0 UI to output phase)
repeat the next two writes as needed:
PACR1.ARM=1 .TRIG=0
PACR1.TRIG=1
(arm again; clearing the TRIG bit is required when MSDIV period < master
clock period because TRIG is not self-clearing in this situation)
(add +1.0 UI to output phase again)
5.7.4.2 Phase Alignment, Output-to-Output
A phase alignment is a special case of phase adjustment where the MSDIV and LSDIV dividers for all participating
outputs are reset just before the phase adjustment occurs. For output-to-output alignment the trigger can be the
PACR1.TRIG bit or the APLL lock signal.
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To avoid glitches (i.e. “runt pulses”) on the output clock it is possible to manually stop the output(s), before
triggering the phase alignment, and then restart the output(s) after the alignment (See section 5.7.5).
When aligning outputs, it is important to note that, by default, the phase of outputs configured as HSTL format or
“two CMOS, OCxP inverted vs. OCxN” format is opposite that of CML outputs. For example, consider the case
where OC1 is 100MHz CML format and OC2 is 100MHz HSTL format. When OC1 and OC2 are aligned then
OC2N is high when OC1P is high. The polarity bit OCxCR2.POL can be used to change this as needed.
There are several rules when alignment is enabled for multiple outputs:
•
•
All participating outputs must come from the same high-speed divider
All outputs that use both medium-speed and low-speed divider must have the same MSDIV value, the
same LSDIV value and PHADJ=0. Subsequent phase adjustment(s) can be used to move the output(s) to
other phase(s).
•
•
All outputs that only use medium-speed divider can have PHADJ values smaller than the period of the
highest output frequency among them.
When some outputs use only medium-speed divider and other outputs use both medium-speed and low-
speed divider, all MSDIV values must be the same, and those output using low-speed divider must have
PHADJ=0.
Contact Microsemi Timing Applications Support for help with alignment scenarios that don’t meet the rules listed
above.
Example: OC1-to-OC2 alignment (+3.5 HSDIV UI offset) after the APLL locks:
OC1CR1.PHEN=1
OC2CR1.PHEN=1
(Enable phase adjust on OC1)
(Enable phase adjust on OC2)
OC1PH.PHADJ=00000000 (0.0UI)
OC2PH.PHADJ=00000111 (+3.5UI)
PACR1.MODE=0
(Phase alignment mode)
PACR2.ARMSRC=0001
PACR2.TRGSRC=0001
PACR1.RST=1
(arm signal is PACR1.ARM bit)
(trigger signal is APLL transition from unlocked to locked)
(reset phase adjust/align state machine after changing ARMSRC, TRGSRC)
(arm for phase alignment)
PACR1.ARM=1
(Aligns/realigns outputs when the APLL locks or relocks)
5.7.4.3 Phase Alignment, Input-to-Output
The phase alignment tool described in section 5.7.4.2 can use a GPIO pin as the alignment trigger. However there
is some uncertainty associated with sampling the GPIO signal. Therefore the phase alignment tool by itself is is not
sufficient to achieve input-to-output phase alignment. The procedure is to first do a phase alignment as described
in section 5.7.4.2 but with a GPIO input as the trigger. Then the phase measurement tool described in section 5.7.6
can be used to determine the phase difference between an output signal and the input signal. Then phase
adjustment as described in section 5.7.4.1 can be used to change the phase of one or more output signals to align
with input signal phase.
It is important to note that, by default, outputs that only use the medium-speed divider have their rising edge
aligned with the rising edge of the trigger signal. Meanwhile,outputs that use both the medium-speed and low-
speed dividers have their rising edge aligned with the falling edge of the trigger signal. Per-output polarity bits
(OCxCR2.POL) can be used to invert the polarity of output signals as needed so that all are rising-edge aligned or
falling-edge aligned or any combination as needed.
5.7.5 Output Clock Start and Stop
Output clocks can be stopped high or low. One use for this behavior is to ensure “glitchless” output clock operation
while the output is reconfigured or phase aligned with some other signal.
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Each output has an OCxSTOP register with fields to control this behavior. The OCxSTOP.MODE field specifies
whether the output clock signal stops high, stops low, or or does not stop. The OCxSTOP.SRC field specifies the
source of the stop signal. Options include the OCxSTOP.STOP bit, assertion of one of the GPIO pins, and the
arming of a phase adjustment (which is indicate by PASR.ARMED).
When the stop mode is Stop High (OCxSTOP.MODE=01) and the stop signal is asserted, the output clock is
stopped after the next rising edge of the output clock. When the stop mode is Stop Low (OCxSTOP.MODE=10)
and the stop signal is asserted, the output clock is stopped after the next falling edge of the output clock. Internally
the clock signal continues to toggle while the output is stopped. When the stop signal is deasserted, the output
clock resumes on the opposite edge that it stopped on. Low-speed output clocks can take long intervals before
being stopped after the stop signal goes active. For example, a 1 Hz output could take up to 1 second to stop.
OCxCR1.MSDIV must be > 0 for this function to operate since MSDIV=0 bypasses the start-stop circuits. Note that
when OCxCR3.NEGLSD=1 the start-stop logic is bypassed for the OCxN pin, and OCxN may not start/stop without
glitches.
When OCxCR2.POL=1 the output stops on the opposite polarity that is specified by the OCxSTOP.MODE field.
When OCxCR2.STOPDIS=1 the output driver is disabled (high impedance) while the output clock is stopped.
Each output has a status register (OCxSR) with several stop/start status bits. The STOPD bit is a real-time status
bit indicating stopped or not stopped. The STOPL bit is a latched status bit that is set when the output clock has
stopped. The STARTL bit is a latched status bit that is set when the output clock has started.
5.7.6 A-to-B Phase Offset Measurement
The phase or time offset between two signals (A and B) can be measured in units of a timebase clock. This
capability can be used to for several purposes, including:
•
•
Keeping output clocks and low-speed output phase/time signals—such as frame sync, multiframe sync, or
1 pulse per second (1PPS) signals—aligned with input phase/time signals. The A-to-B measurement
circuitry can detect phase changes in the input signal. Then the output phase adjustment circuitry
described in section 5.7.4 can be used to move phase(s) of output(s) to follow the input phase change.
Keeping output clock signals and/or low-speed output phase/time signals aligned with one another. The A-
to-B measurement circuitry can detect relative phase changes, and the phase adjustment circuitry
described in section 5.7.4 can be used to move phase(s) of output(s) as needed.
The A and B signals can be any ICx input, any OCx output, or any GPIO, as specified by MABCR2.ASRC and
MABCR3.BSRC. The timebase signal can be the external oscillator signal (or the output of the crystal driver circuit,
optionally doubled by the clock doubler) or the output clock of any of the three medium-speed dividers (MSDIV1,
MSDIV2, MSDIV3). The timebase signal is specified by MABCR1.TBSRC.
A new measurement is started by writing MABCR1.START=1. Any previously started measurement must be
completed before a new measurement is started. If a measurement has not finished it can be aborted by writing
MABCR1.RST=1 before starting a new measurement. The measurement is complete when MABSR1.RDYL is set.
Example: consider an SDH/SONET application where OC1 is a 19.44MHz output clock and OC2 is an 8kHz frame
sync signal. The goal is to measure the phase offset of OC1 vs. OC2. If they are found to have a phase offset then
the phase adjustment circuitry in section 5.7.4 can be used to slowly change the phase of OC1 to match the phase
of OC2 (or vice versa).
MABCR1.TBSRC=001
MABCR2.ASRC=10001
MABCR3.BSRC=10000
MABCR1.START=1
(MSDIV1 output clock is 311.04MHz = 3.2 ns period)
(OC2 8kHz sync signal)
(OC1 19.44MHz clock)
(Start measurement)
Wait for MABSR1.RDYL=1
(Measurement ready)
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Read MABSR1.OVFL
(to see if the measurement is valid)
MABSR1.RDYL=1, MABSR1.OVFL=1 (clear latched status bits)
Read MEAS bits from MABSR1
and MABSR2
If, for example, MEAS = 111 1111 1001 (-8) then the rising edge of OC1 (the ‘B’ signal) precedes the rising edge of
OC2 (the ‘A’ signal) by 8 MSDIV1 ouptut clock periods (25.7ns).
An A-to-B measurement is performed by sampling the A and B signals with the selected timebase clock and
detecting the rising or falling edges to measure. The number of timebase clocks between the A and B edges is
counted. If the counter doesn’t overflow then the phase difference is reported in the MEAS field in MABSR1 and
MABSR2. If the counter does overflow then MABSR1.OVFL is set and the value of MEAS is invalid.
While the measurement is in progress the MABSR1.BUSY bit is set to 1. When the measurement is complete
MABSR1.BUSY is set to 0 and MABSR1.RDYL is set to 1. Since the A and B signals are sampled by the timebase
signal, this measurement tool is only useful when the timebase signal is much higher frequency than the A and B
signals (at least 8-10x). Also, when possible, the timebase signal frequency should be less than or equal to 1000
times faster than the the frequencies of the A and B frequencies to avoid measurement counter overflow.
Constraints on A-to-B measurement:
•
fB = fA x N
where fA is the frequency of signal A, fB is the frequency of signal B and
N is a positive integer
When measuring from an ICx input or a GPIO (signal A) to an ICx or a GPIO (signal B) and when measuring from
an OCx output to an OCx output, the measured value is MEAS * timebase_period. This measurement has a
variability of 0 to +1 timebase clock period.
When measuring from an ICx input or a GPIO (signal A) to an OCx output (signal B), the measurement in time
units is MEAS * timebase_period + 6 * HSCLK_period, where HSCLK_period is the period of the output of the high-
speed divider from which OCx signal is derived. This measurement has a variability of 0 to +1 timebase clock
period plus 0 to +1 HSCLK periods.
When measuring from an OCx output (signal A) to an ICx input or a GPIO (signal B), the the measurement in time
units is MEAS * timebase_period – 6 * HSCLK_period, where HSCLK_period is the period of the output of the high-
speed divider from which OCx signal is derived. This measurement has a variability of 0 to +1 timebase clock
period plus 0 to +1 HSCLK periods.
Guidance for Use
When the A and B signals are aligned to within one timebase clock cycle, the measurement hardware does not
report 0. Instead it reports a measurement value that is equivalent to +1 cycle of signal B.
If the timebase clock is 1023 times faster than signal B (so that the MEAS field cannot overflow, unless signal B
is grossly too slow or not toggling at all) then system software should check the measured phase value. If the
measured value is equal to the period of signal B then the A and B signals are aligned.
If the timebase clock is 1024 to 2047 times faster than signal B (and therefore the measurement counter can
overflow) then the measurement hardware reports overflow when the A and B signals are aligned to within one
timebase clock cycle. This report of overflow can be distinguished from other overflow cases by setting
MABCR3.BINV=1 and then remeasuring from signal A to the opposite edge of signal B. If the new measured value
is equal to half the period of signal B then the A and B signals are aligned.
If the timebase clock is > 2047 times faster than signal B then the measurement hardware reports overflow when
the A and B signals are aligned to within one timebase clock cycle. This report of overflow is not distinguishable
from other overflow cases. One way system software could work around this to determine that A and B are aligned
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is to use phase adjustment to move one of the signals by 2 or more timebase clocks then remeasure. If the new
measured value matches the phase adjustment then the signals were aligned before the phase adjustment.
Software can then adjust the phase of the signal back to its original position. Not all applications can tolerate such
phase adjustments; for those applications it is recommended that the timebase clock be 2047 times faster than
signal B.
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5.8 Microprocessor Interface
The device can communicate over a SPI interface or an I2C interface.
In SPI mode the ZL30250 can be configured at reset to be a SPI slave to a processor master or a SPI master to an
external EEPROM slave. The ZL30251 can only be configured as a SPI slave to a processor master. Both devices
are always slaves on the I2C bus.
Section 5.2 describes reset pin settings required to configure the device for these interfaces.
5.8.1 SPI Slave
The device can present a SPI slave port on the CSN, SCLK, MOSI, and MISO pins. SPI is a widely used
master/slave bus protocol that allows a master and one or more slaves to communicate over a serial bus. SPI
masters are typically microprocessors, ASICs or FPGAs. Data transfers are always initiated by the master, which
also generates the SCLK signal. The device receives serial data on the MOSI (Master Out Slave In) pin and
transmits serial data on the MISO (Master In Slave Out) pin. MISO is high impedance except when the device is
transmitting data to the bus master.
Bit Order. The register address and all data bytes are transmitted most significant bit first on both MOSI and
MISO.
Clock Polarity and Phase. The device latches data on MOSI on the rising edge of SCLK and updates data on
MISO on the falling edge of SCLK. SCLK does not have to toggle between accesses, i.e., when CSN is high.
Device Selection. Each SPI device has its own chip-select line. To select the device, the bus master drives its
CSN pin low.
Command and Address. After driving CSN low, the bus master transmits an 8-bit command followed by a 16-bit
register address. The available commands are shown below.
Table 3 – SPI Commands
Command
Write Enable
Write
Read
Read Status
Hex
Bit Order, Left to Right
0000 0110
0000 0010
0000 0011
0000 0101
0x06
0x02
0x03
0x05
Read Transactions. The device registers are accessible when EESEL=0. On a ZL30251 the internal EEPROM
memory is accessible when EESEL=1. On a ZL30250 EESEL must be set to 0. After driving CSN low, the bus
master transmits the read command followed by the 16-bit address. The device then responds with the requested
data byte on MISO, increments its address counter, and prefetches the next data byte. If the bus master continues
to demand data, the device continues to provide the data on MISO, increment its address counter, and prefetch the
following byte. The read transaction is completed when the bus master drives CSN high. See Figure 7.
Register Write Transactions. The device registers are accessible when EESEL=0. After driving CSN low, the bus
master transmits the write command followed by the 16-bit register address followed by the first data byte to be
written. The device receives the first data byte on MOSI, writes it to the specified register, increments its internal
address register, and prepares to receive the next data byte. If the master continues to transmit, the device
continues to write the data received and increment its address counter. The write transaction is completed when
the bus master drives CSN high. See Figure 9.
EEPROM Writes (ZL30251 Only). The internal EEPROM memory is accessible when EESEL=1. After driving
CSN low, the bus master transmits the write enable command and then drives CSN high to set the internal write
enable latch. The bus master then drives CSN low again and transmits the write command followed by the 16-bit
address followed by the first data byte to be written. The device first copies the page to be written from EEPROM to
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its page buffer. The device then receives the first data byte on MOSI, writes it to its page buffer, increments its
internal address register, and prepares to receive the next data byte. If the master continues to transmit, the device
continues to write the data received to its page buffer and continues to increment its address counter. The address
counter rolls over at the 32-byte page boundary (i.e. when the five least-significant address bits are 11111). When
the bus master drives CSN high, the device transfers the data in the page buffer to the appropriate page in the
EEPROM memory. See Figure 8 and Figure 9.
EEPROM Read Status (ZL30251 Only). After the bus master drives CSN high to end an EEPROM write
command, the EEPROM memory is not accessible for up to 5ms while the data is transferred from the page buffer.
To determine when this transfer is complete, the bus master can use the Read Status command. After driving CSN
low, the bus master transmits the Read Status command. The device then responds with the status byte on MISO.
In this byte, the least significant bit is set to 1 if the transfer is still in progress and 0 if the transfer has completed.
Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by
pulling CSN high. In response to early terminations, the device resets its SPI interface logic and waits for the start
of the next transaction. If a register write transaction is terminated prior to the SCLK edge that latches the least
significant bit of a data byte, the data byte is not written. On ZL30251, if an EEPROM write transaction is
terminated prior to the SCLK edge that latches the least significant bit of a data byte, none of the bytes in that write
transaction are written.
Design Option: Wiring MOSI and MISO Together. Because communication between the bus master and the
device is half-duplex, the MOSI and MISO pins can be wired together externally to reduce wire count. To support
this option, the bus master must not drive the MOSI/MISO line when the device is transmitting.
AC Timing. See Table 17 and Figure 20 for AC timing specifications for the SPI interface.
CS
0
1
2
3
4
5
6
7
8
9
10
22 23 24 25 26 27 28 29 30 31
SCLK
Command
16-bit Address
15 14 13
0
0
0
0
0
0
1
1
1
0
MOSI
MISO
Data Byte1
Data Byte n
High Impedance
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 7 - SPI Read Transaction Functional Timing
CS
0
1
2
3
4
5
6
7
SCLK
MOSI
Command
0
0
0
0
0
1
1
0
Figure 8 - SPI Write Enable Transaction Functional Timing (ZL30251 Only)
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CS
0
1
2
3
4
5
6
7
8
9
10
22 23 24 25 26 27 28 29 30 31
SCLK
Command
16-bit Address
15 14 13
Data Byte1
Data Byte n
0
0
0
0
0
0
1
0
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MOSI
Figure 9 - SPI Write Transaction Functional Timing
5.8.2 SPI Master (ZL30250 Only)
After reset the ZL30250 can present a SPI master port on the CSN, SCLK, MOSI, and MISO pins for auto-
configuration using data read from an external SPI EEPROM. During auto-configuration the device is always the
SPI master and generates the CSN and SCLK signals. The device transmits serial data on the the MOSI (Master
Out Slave In) pin and receives serial data on the MISO (Master In Slave Out) pin.
Bit Order. The register address and all data bytes are transmitted most significant bit first on both MOSI and
MISO.
Clock Polarity and Phase. The device latches data on MISO on the rising edge of SCLK and updates data on
MOSI on the falling edge of SCLK.
Device Selection. Each SPI device has its own chip-select line. To select the external EEPROM, the device drives
the CSN signal low.
Command and Address. After driving CSN low, the device transmits an 8-bit read command followed by a 16-bit
register address. The read command is shown below.
Command
Hex
Bit Order, Left to Right
Read
0x03
0000 0011
Read Transactions. After driving CSN low, the device transmits the read command followed by the 16-bit register
address. The external EEPROM then responds with the requested data byte on MISO, increments its address
counter, and prefetches the next data byte. If the device continues to demand data, the EEPROM continues to
provide the data on MISO, increment its address counter, and prefetch the following byte. The read transaction is
completed when the device drives CSN high. See Figure 7.
Writing the External EEPROM. Due to the small package size and low pin count of the device, there is no way to
use the ZL30250 to write the external EEPROM. The auto-configuration data used by the ZL30250 must be pre-
programmed into the EEPROM by some other method, such as:
1. The EEPROM manufacturer can write the data to the EEPROM during production testing.
This is a service they routinely provide.
2. A contract manufacturer or distributor can write the data to the EEPROM using a production
EEPROM programmer before the EEPROM is mounted to the board.
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5.8.3 I2C Slave
The device can present a fast-mode (400kbit/s) I2C slave port on the SCL and SDA pins. I2C is a widely used
master/slave bus protocol that allows one or more masters and one or more slaves to communicate over a two-
wire serial bus. I2C masters are typically microprocessors, ASICs or FPGAs. Data transfers are always initiated by
the master, which also generates the SCL signal. The device is compliant with version 2.1 of the I2C specification.
The I2C interface on the device is a protocol translator from external I2C transactions to internal SPI transactions.
This explains the slightly increased protocol complexity described in the paragraphs that follow.
Read Transactions. The device registers are accessible when EESEL=0. On a ZL30251 the internal EEPROM
memory is accessible when EESEL=1. On ZL30250 EESEL must be set to 0. The bus master first does an I2C
write to the device. In this transaction three bytes are written: the SPI Read command (see Table 3), the upper byte
of the register address, and the lower byte of the register address. The bus master then does an I2C read. During
each acknowledge (A) bit the device fetches data from the read address and then increments the read address.
The device then transmits the data to the bus master during the next 8 SCL cycles. The bus master terminates the
read with a not-acknowledge (NA) followed by a STOP condition (P). See Figure 10. Note: If the I2C write is
separated in time from the I2C read by other I2C transactions then the device only outputs the data value from the
first address and repeats that same data value after each acknowledge (A) generated by the bus master.
Register Write Transactions. The device registers are accessible when EESEL=0. The bus master does an I2C
write to the device. The first three bytes of this transaction are the SPI Write command (see Table 3), the upper
byte of the register address, and the lower byte of the register address. Subsequent bytes are data bytes to be
written. After each data byte is received, the device writes the byte to the write address and then increments the
write address. The bus master terminates the write with a STOP condition (P). See Figure 11.
EEPROM Writes (ZL30251 Only). The EEPROM memory is accessible when EESEL=1. The bus master first
does an I2C write to transmit the SPI Write Enable command (see Table 3) to the device. The bus master then
does an I2C write to transmit data to the device as described in the Register Write Transactions paragraph above.
See Figure 12.
EEPROM Read Status (ZL30251 Only). The bus master first does an I2C write to transmit the SPI Read Status
command (see Table 3) to the device. The bus master then does an I2C read to get the status byte. In this byte, the
least significant bit is set to 1 if the transfer is still in progress and 0 if the transfer has completed. See Figure 13.
I2C Features Not Supported by the Device. The I2C specification has several optional features that are not
supported by the device. These are: 3.4Mbit/s high-speed mode (Hs-mode), 10-bit device addressing, general call
address, software reset, and device ID. The device does not hold SCL low to force the master to wait.
I2C Slave Address. The device’s 7-bit slave address can be pin-configured for any of three values. These values
are show in the table in section 5.2.
Bit Order. The I2C specification requires device address, register address and all data bytes to be transmitted most
significant bit first on the SDA signal.
Note: as required by the I2C specification, when power is removed from the device, the SDA and SCL pins are left
floating so they don’t obstruct the bus lines.
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S = START condition
P = STOP condition
A = acknowledge (SDA low)
slave device
address
read
reg. address
reg. address
lower byte
S
S
R/W A
A
A
A
A P
command
upper byte
7 bits
NA = not acknowledge (SDA high)
0 (write)
slave device
address
R/W A data byte1
data byteN NA P
7 bits
1 (read)
Figure 10 – I2C Read Transaction Functional Timing
slave device
address
write
command
reg. address
upper byte
reg. address
lower byte
S
R/W A
A
A
A
data byte1
A
data byteN A P
7 bits
S = START condition
P = STOP condition
0 (write)
A = acknowledge (SDA low)
NA = not acknowledge (SDA high)
Figure 11 – I2C Register Write Transaction Functional Timing
S = START condition
P = STOP condition
A = acknowledge (SDA low)
NA = not acknowledge (SDA high)
slave device
address
write enable
command
S
S
R/W A
A P
7 bits
0 (write)
slave device
address
write
command
reg. address
reg. address
lower byte
R/W A
A
A
A
data byte1
A
data byteN A P
upper byte
7 bits
0 (write)
Figure 12 – I2C EEPROM Write Transaction Functional Timing (ZL30251 Only)
S = START condition
P = STOP condition
A = acknowledge (SDA low)
NA = not acknowledge (SDA high)
slave device
address
read status
command
S
S
R/W A
A P
7 bits
0 (write)
slave device
address
R/W A status byte NA
P
7 bits
1 (read)
Figure 13 – I2C EEPROM Read Status Transaction Functional Timing (ZL30251 Only)
Note: In Figure 10 through Figure 13, a STOP condition (P) immediately followed by a START condition (S) can be
replaced by a repeated START condition (Sr) as described in the I2C specification.
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5.9 Interrupt Logic
Any of the GPIO pins can be configured as an interrupt-request output by setting the appropriate GPIOxC field in
the GPIOCR registers to one of the status output options (01xx) and configuring the appropriate GPIOxSS register
to follow the INTSR.INT bit. If system software is written to poll rather than receive interrupt requests, then software
can read the INTSR.INT bit first to determine if any interrupt requests are active in the device.
Many of the latched status bits in the device can be the source of an interrupt request if their corresponding
interrupt enable bits are set. The device’s interrupt logic is shown in Figure 14. See the register map (Table 4) and
the status register descriptions in section 6.3.2 for descriptions of the register bits shown in the figure.
MABSR1.RDYL
GLOBISR.MAB
MABSR1.RDYIE
INTSR.GLOB
PASR.ADJL
GLOBISR.PA
PASR.ADJIE
OC1SR.STOPL
OC1SR.STOPIE
OC1SR.STARTL
OCISR.OC1
OC1SR.STARTIE
OC1SR.LSCLKL
OC1SR.LSCLKIE
OC2SR.STOPL
OC2SR.STOPIE
OC2SR.STARTL
INTSR.OC
OCISR.OC2
OC2SR.STARTIE
OC2SR.LSCLKL
OC2SR.LSCLKIE
OC3SR.STOPL
OC3SR.STOPIE
OC3SR.STARTL
OC3SR.STARTIE
OC3SR.LSCLKL
OC3SR.LSCLKIE
GPIOn
INTSR.INT
OCISR.OC3
INTSR.INTIE
GPIOnSS
GPIOCRx.GPIOnC
APLLSR.ALKL
APLLSR.ALKIE
APLLISR.APLL
INTSR.APLL
Figure 14 – Interrupt Structure
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5.10 Reset Logic
The device has two reset controls: the RSTN pin and the RST bit in MCR1. The RSTN pin asynchronously resets
the entire device. When the RSTN pin is low all internal registers are reset to their default values. The RSTN pin
must have one rising edge after power-up. At initial power-up reset should be asserted for at least 1µs. During
operation, the RSTN assertion time can be as short as 1µs with one important exception:
Consider each of these four pins: AC0/GPIO0, AC1/GPIO1, TEST/GPIO2 and IF1/MISO. If (1) the
pin could be an output driving high when RSTN is asserted, and (2) an external pulldown resistor is
used to set the at-reset value of the pin, then RSTN should be asserted for 100 milliseconds.
The MCR1.RST bit resets the entire device (except for the microprocessor interface and the RST bit itself), but
when the RST bit is active, the register fields with pin-programmed defaults do not latch their values from, or based
on, the corresponding input pins. Instead these fields are reset to the default values that were latched when the
RSTN pin was last active.
Microsemi recommends holding RSTN low while the internal ring oscillator starts up and stabilizes. An incorrect
reset condition could result if RSTN is released before the oscillator has started up completely. After the external
oscillator or internal crystal driver circuit has been enabled and stabilized, the master clock can be switched from
the ring oscillator to the external oscillator using the MCR1.MCSEL bit.
Important: System software must wait at least 100µs after RSTN is deasserted and wait for
GLOBISR.BCDONE=1 before configuring the device.
5.11 Power-Supply Considerations
Due to the multi-power-supply nature of the device, some I/Os have parasitic diodes between a <3.3V supply and a
3.3V supply. When ramping power supplies up or down, care must be taken to avoid forward-biasing these diodes
because it could cause latchup. Two methods are available to prevent this. The first method is to place a Schottky
diode external to the device between the <3.3V supply and the 3.3V supply to force the 3.3V supply to be within
one parasitic diode drop of the <3.3V supply. The second method is to ramp up the 3.3V supply first and then ramp
up the <3.3V supply. In some applications VDDOx power supply pins can be at other voltages, such as 2.5V or
1.5V. In these applications the general solution is to ramp up the supplies in order from highest nominal to lowest
nominal voltage.
5.12 Auto-Configuration from EEPROM
For the ZL30250, for applications where the device can operate stand-alone without supervision from a processor,
the device can configure itself at reset from an external EEPROM connected to its SPI interface. The EEPROM can
store up to three configurations, known as configurations 1, 2 and 3. As described in section 5.2.1, IF[1:0] must be
11 at reset, and the device configuration to be used is specified by the values of the AC[1:0] pins at reset (1, 2 or
3).
For the ZL30251, the internal EEPROM memory can store up to four device configurations, known as
configurations 0, 1, 2 and 3. As described in section 5.2.2, the device configuration to be used is specified by the
values of the AC[1:0] pins at reset.
5.12.1 Generating Device Configurations
Device configurations must be generated using the evaluation software. This is true for auto-configurations stored
in internal or external EEPROM and for configurations that are written to the device by a system processor. The
reason for this requirement is that writes to undocumented registers must be done to tune analog circuitry for
optimal performance. The writes to be done depend on integer vs. fractional multiplication, device mode and other
factors. The registers involved control very low-level device parameters that are difficult to describe and difficult to
understand how to use. Instead the evaluation software has all of the expert knowledge built-in to keep
configuration easy for the user.
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5.12.2 Direct EEPROM Write Mode (ZL30251 Only)
Data Sheet
To simplify writing the ZL30251’s internal EEPROM during manufacturing, the device has a test mode known as
direct EEPROM write mode. The device enters this mode when TEST=1 and AC[1:0]=00 on the rising edge of
RSTN. In this mode the EEPROM memory is mapped into the address map and can be written as needed to store
configuration scripts in the device. Device registers are not accessible in this mode. The device exits this mode
when TEST=0 on the rising edge of RSTN. Note: the device drives the MISO pin continually during this mode.
Therefore this mode cannot be used when MOSI and MISO are tied together (as described in the Design Option:
Wiring MOSI and MISO Together paragraph in section 5.8.1).
5.12.3 Holding Other Devices in Reset During Auto-Configuration
Using the appropriate GPIOCR and GPIO0SS registers, a GPIO pin can be configured to follow the
GLOBISR.BCDONE status bit. This GPIO can then be used as a reset signal to hold other devices (that use clocks
from this device) in reset while the device configures itself. As an example, to configure GPIO0 to follow BCDONE
with 0=reset add the following writes at the beginning of the configuration file: write 0x1F to GPIO0SS and write
0x04 to GPIOCR1.
5.13 Power Supply Decoupling and Layout Recommendations
Application Note ZLAN-490 describes recommended power supply decoupling and layout practices.
6. Register Descriptions
The device has an overall address range from 000h to 6FFh. Table 4 shows the register map. In each register, bit 7
is the MSb and bit 0 is the LSb. Register addresses not listed and bits marked “—“ are reserved and must be
written with 0. Writing other values to these registers may put the device in a factory test mode resulting in
undefined operation. Bits labeled “0” or “1” must be written with that value for proper operation. Register fields with
underlined names are read-only fields; writes to these fields have no effect. All other fields are read-write. Register
fields are described in detail in the register descriptions that follow Table 4.
6.1 Register Types
6.1.1 Status Bits
The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the
time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending
on the bit) and cleared when written with a logic 1 value. Writing a 0 has no effect. When set, some latched status
bits can cause an interrupt request if enabled to do so by corresponding interrupt enable bits. Status bits marked
“—“ are reserved and must be ignored.
6.1.2 Configuration Fields
Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the
register definition. Configuration register bits marked “—“ are reserved and must be written with 0.
6.1.3 Multiregister Fields
Multiregister fields—such as FREQZ[39:0] in registers DFREQZ1 through DFREQZ5—must be handled carefully to
ensure that the bytes of the field remain consistent. A write access to a multiregister field is accomplished by
writing all the registers of the field in order from smallest address to largest. Writes to registers other than the last
register in the field (i.e. the register with the largest address) are stored in a transfer register. When the last register
of the field is written, the entire multiregister field is updated simultaneously from the transfer register. If the last
register of the field is not written, the field is not updated. Any reads from the multiregister field that occur during the
middle of the multiregister write will read the existing value of the field not the new value in the transfer register.
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Data Sheet
A read access from a multiregister field is accomplished by reading the registers of the field in order from smallest
address to largest. When the first register in the field (i.e. the register with the lowest address) is read, the entire
multiregister field is copied to the transfer register. During subsequent reads from the other registers in the
multiregister field, the data comes from the transfer register. Any writes to the multiregister field that occur during
the middle of the multiregister read will overwrite values in the transfer register.
The device has one write transfer register and one read transfer register that it reuses for all multiregister fields. For
proper operation system software should be organized such that only one software process accesses the device’s
registers. If two or more processes are allowed to make uncoordinated accesses to the device’s registers, their
accesses to multiregister fields could interrupt one another leading to incorrect writes and reads of the multiregister
fields.
The multiregister fields are:
Field
Registers
Type
FREQZ[39:0]
DFREQZ1 to DFREQZ5
Read/Write
6.1.4 Bank-Switched Registers (ZL30251 Only)
The EESEL register is a bank-select control field that maps the device registers into the memory map at address
0x1 and above when EESEL=0 and maps the EEPROM memory into the memory map at address 0x1 and above
when EESEL=1. The EESEL register itself is always in the memory map at address 0x0 for both EESEL=0 and
EESEL=1.
6.2 Register Map
Table 4 - Register Map
ADDR
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Global Configuration Registers
00h
09
0A
0B
0C
0D
0E
0F
12
13
14
15
1B
1C
1D
1E
1F
EESEL
MCR1
MCR2
PLLEN
ICEN
—
RST
—
—
—
—
—
—
—
—
ROSCD
—
—
DBL
—
—
IC3EN
OC3EN
—
EESEL
XAB[1:0]
MCSEL1 MCSEL
—
—
IC2EN
OC2EN
—
EXTSS[1:0]
—
NCSSEN
—
—
—
—
—
—
—
—
—
—
APLLEN
IC1EN
OC1EN
—
—
OCEN
GPIO1C[3:0]
GPIO3C[3:0]
GPIO0C[3:0]
GPIO2C[3:0]
BIT[2:0]
GPIOCR1
GPIOCR2
GPIO0SS
GPIO1SS
GPIO2SS
GPIO3SS
PACR1
REG[4:0]
REG[4:0]
REG[4:0]
REG[4:0]
ARM
BIT[2:0]
BIT[2:0]
BIT[2:0]
TINV
RST
TRIG
ARMSRC[3:0]
START
—
—
—
—
—
—
MODE
PACR2
TRGSRC[3:0]
TBSRC[2:0]
MABCR1
MABCR2
MABCR3
RST
AINV
BINV
—
—
—
ASRC[4:0]
BSRC[4:0]
—
Status Registers
30
31
40
41
ID1
ID2
CFGSR
GPIOSR
IDU[7:0]
IDL[3:0]
XOFAIL
REV[3:0]
TEST
—
—
—
—
—
IF[1:0]
AC[1:0]
GPIO1 GPIO0
—
GPIO3
GPIO2
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Data Sheet
ADDR
42
43
45
46
REGISTER
INTSR
GLOBISR BCDONE
BIT 7
—
BIT 6
GLOB
—
—
—
BIT 5
OC
—
—
—
BIT 4
—
—
—
—
BIT 3
—
—
—
—
BIT 2
APLL
—
OC3
—
BIT 1
INTIE
PA
OC2
—
BIT 0
INT
MAB
OC1
APLL
ALK
OCISR
APLLISR
APLLSR
MABSR1
MABSR2
PASR
OC1SR
OC2SR
OC3SR
—
—
—
—
48
ALK2IE
OVFL
ALK2L
RDYIE
ALK2
RDYL
—
BUSY
ALKIE
ALKL
4B
4C
4D
53
54
55
MEAS[10:8]
MEAS[7:0]
—
—
—
—
ADJIE
ADJL
BUSY
STOPL
STOPL
STOPL
ARMED
STOPD
STOPD
STOPD
LSCLKIE LSCLKL
LSCLKIE LSCLKL
LSCLKIE LSCLKL
LSCLK STARTIE STARTL
LSCLK STARTIE STARTL
LSCLK STARTIE STARTL
STOPIE
STOPIE
STOPIE
APLL Configuration Registers
100
101
102
103
106
107
108
109
10A
10B
10C
10D
10E
10F
110
111
112
113
114
APLLCR1
APLLCR2
APLLCR3
APLLCR4 DECPH
AFBDIV1
AFBDIV2
AFBDIV3
AFBDIV4
AFBDIV5
AFBDIV6
AFBDEN1
AFBDEN2
AFBDEN3
AFBDEN4
AFBREM1
AFBREM2
AFBREM3
AFBREM4
AFBBP
—
—
—
—
—
ENHS2
BYPHS2
—
HSDIV2[3:0]
EXTSW
HSDIV1[3:0]
—
ALTMUX[2:0]
APLLMUX[2:0]
PISS[2:0]
PDSS[2:0]
INCPH
AFBDIV[7:0]
AFBDIV[15:8]
AFBDIV[23:16]
AFBDIV[31:24]
AFBDIV[39:32]
—
—
—
—
—
—
AFBDIV[41:40]
AFBDEN[7:0]
AFBDEN[15:8]
AFBDEN[23:16]
AFBDEN[31:24]
AFBREM[7:0]
AFBREM[15:8]
AFBREM[23:16]
AFBREM[31:24]
AFBBP[7:0]
Output Clock Configuration Registers
OC1 Registers
200
201
202
203
204
205
206
207
208
OC1CR1
OC1CR2
PHEN
—
MSDIV[6:0]
STOPDIS
POL
DRIVE[1:0]
OCSF[2:0]
OC1CR3 SRLSEN DIVSEL NEGLSD
LSSEL
—
—
—
LSDIV[24]
OC1DIV1
OC1DIV2
OC1DIV3
OC1DC
LSDIV[7:0]
LSDIV[15:8]
LSDIV[23:16]
OCDC[7:0]
PHADJ[7:0]
SRC[3:0]
OC1PH
OC1STOP
OC2 Registers
OC2CR1
STOP
—
MODE[1:0]
210
…
…
same as OC1 registers
218
OC2STOP
OC3 Registers
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Data Sheet
ADDR
220
…
REGISTER
OC3CR1
…
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
same as OC1 registers
228
OC3STOP
Input Clock Configuration
300
320
340
IC1CR1
IC2CR1
IC3CR1
—
—
—
POL
POL
POL
—
—
—
—
—
—
—
—
—
—
—
—
HSDIV[1:0]
HSDIV[1:0]
HSDIV[1:0]
NCO/SS Configuration Registers
40B NCSSCR1
—
—
—
—
MODE[3:0]
420
421
422
423
424
DFREQZ1
DFREQZ2
DFREQZ3
DFREQZ4
DFREQZ5
FREQZ[7:0]
FREQZ[15:8]
FREQZ[23:16]
FREQZ[31:24]
FREQZ[39:32]
6.3
Register Definitions
6.3.1 Global Configuration Registers
Register Name:
EESEL
Register Description:
Register Address:
EEPROM Memory Selection Register
00h
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
—
0
Bit 1
—
0
Bit 0
EESEL
0
Name
Default
Bit 0: EEPROM Memory Select (EESEL). This bit is a bank-select that specfies whether device register space or
EEPROM memory is mapped into addresses 0x1 and above. This applies only to the ZL30251. The ZL30250 does
not have internal EEPROM memory. See sections 5.8 and 6.1.4. Note that this bit is write-only; the value read is
not reliable.
0 = Device registers
1= EEPROM memory
Register Name:
MCR1
Register Description:
Register Address:
Master Configuration Register 1
09h
Bit 7
RST
0
Bit 6
—
0
Bit 5
MCSEL1
0
Bit 4
MCSEL
0
Bit 3
ROSCD
0
Bit 2
DBL
0
Bit 1
Bit 0
Name
Default
XAB[1:0]
0
0
Bit 7: Device Reset (RST). When this bit is high the entire device is held in reset, and all register fields, except the
RST bit itself, are reset to their default states. When RST is high, the register fields with pin-programmed defaults
do not latch their values from the corresponding input pins. Instead these fields are reset to the default values that
were latched from the pins when the RSTN pin was last active. See section 5.10.
0 = Normal operation
1 = Reset
Note: For proper sequencing of internal logic, write MCR1 to clear the MCSEL1, MCSEL and ROSCD bits first
(without changing the value of the RST bit) then perform a second write to set the RST bit.
(Note: on rev A devices (ID2.REV=0) do not set this bit to 1.)
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Data Sheet
Bit 5: NCO/SS Master Clock Select IC1 (MCSEL1). This bit overrides the MCSEL bit to specify IC1 as the source
of the NCO/SS block’s master clock.
0 = Master clock selected by MCSEL bit
1 = Master clock sourced from IC1, which has a divider and a polarity control bit
Bit 4: NCO/SS Master Clock Select (MCSEL). This bit selects the source of the NCO/SS block’s master clock. At
reset the internal ring oscillator is enabled and selected. When operating the device in NCO mode or spread
spectrum mode, this bit must be set to 1 after the external oscillator connected to the XA pin has stabilized and is
ready to use. See section 5.3.4.
0 = Master clock sourced from internal ring oscillator
1 = Master clock sourced from the XA pin (optionally through the clock doubler)
Bit 3: Ring Oscillator Disable (ROSCD). This bit disables the ring oscillator. It can be set to 1 when either MCSEL
or MCSEL1 is set 1 so that the ring oscillator does not cause unwanted phase noise spurs in output clock signals.
See section 5.3.4.
0 = Enable
1 = Disable (power-down)
Bit 2: Clock Doubler Enable (DBL). This bit enables the clock doubler for either the output of the crystal driver
circuitry or the signal on the XA pin. During power-up, system software must wait at least 5ms for the crystal driver
circuit to stabilize before enabling the clock doubler. See section 5.3.3.
0 = Disable (power down)
1 = Enable
Bits 1 to 0: XA/XB Pin Mode (XAB[1:0]). This field specifies the behavior of the XA and XB pins. See section 5.3.
00 = Crystal driver and input disabled / powered down
01 = Crystal driver and input enabled on XA/XB
10 = XA enabled as single-ended input for external oscillator signal; XB must be left floating
11 = {unused value}
Register Name:
MCR2
Register Description:
Register Address:
Master Configuration Register 2
0Ah
Bit 7
—
Bit 6
Bit 5
Bit 4
—
Bit 3
—
Bit 2
—
Bit 1
—
Bit 0
—
Name
EXTSS[1:0]
Default
0
0
0
0
0
0
0
0
Bits 6 to 5: External Switch Source Select (EXTSS[1:0]). This field selects the GPIO source for the external
switch control signal. It is only valid when APLLCR3.EXTSW=1. See section 5.6.1.
00 = GPIO0
01 = GPIO1
10 = GPIO2
11 = GPIO3
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Register Name:
PLLEN
Register Description:
Register Address:
APLL Enable Register
0Bh
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
NCSSEN
0
Bit 3
—
0
Bit 2
—
0
Bit 1
—
0
Bit 0
APLLEN
0
Name
Default
Bit 4: NCO/SS Block Enable (NCSSEN). This field enables or disables the NCO/SS block. See section 5.5. Note
that the XA clock source must be properly configured and selected to operate the NCO/SS block.
0 = Disable (powered down)
1 = Enable
Bit 0: APLL Enable (APLLEN). This bit enables or disables the APLL. For normal operation the APLL must be
enabled. See section 5.6.2.
0 = Disabled
1 = Enabled
Register Name:
ICEN
Register Description:
Register Address:
Input Clock Enable Register
0Ch
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
IC3EN
0
Bit 1
IC2EN
0
Bit 0
IC1EN
0
Name
Default
Bit 2: Input Clock 3 Enable (IC3EN). This bit enables and disables the input clock 3 differential receiver and input
dividers. See section 5.4.
0 = Disabled
1 = Enabled
Bit 1: Input Clock 2 Enable (IC2EN). This bit enables and disables the input clock 2 differential receiver and input
dividers. See section 5.4.
0 = Disabled
1 = Enabled
Bit 0: Input Clock 1 Enable (IC1EN). This bit enables and disables the input clock 1 differential receiver and input
dividers. See section 5.4.
0 = Disabled
1 = Enabled
Register Name:
OCEN
Register Description:
Register Address:
Output Clock Enable Register
0Dh
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
OC3EN
0
Bit 1
OC2EN
0
Bit 0
OC1EN
0
Name
Default
Bit 2: Output Clock 3 Enable (OC3EN). This bit enables and disables the output clock 3 drivers, output dividers,
phase adjustment/alignment circuitry and start/stop circuitry. See section 5.7.1.
0 = Disabled
1 = Enabled
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Bit 1: Output Clock 2 Enable (OC2EN). This bit enables and disables the output clock 2 drivers, output dividers,
phase adjustment/alignment circuitry and start/stop circuitry. See section 5.7.1.
0 = Disabled
1 = Enabled
Bit 0: Output Clock 1 Enable (OC1EN). This bit enables and disables the output clock 1 drivers, output dividers,
phase adjustment/alignment circuitry and start/stop circuitry. See section 5.7.1.
0 = Disabled
1 = Enabled
Register Name:
GPIOCR1
Register Description:
Register Address:
GPIO Configuration Register 1
0Eh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
GPIO1C[3:0]
GPIO0C[3:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 4: GPIO1 Configuration (GPIO1C[3:0]). This field configures the GPIO1 pin as a general-purpose input,
a general-purpose output driving low or high, or a status output. The current state of the pin can be read from
GPIOSR.GPIO1. When GPIO1 is a status output, the GPIO1SS register specifies which status bit is output.
0000 = General-purpose input
0001 = General-purpose input - inverted polarity
0010 = General-purpose output driving low
0011 = General-purpose output driving high
0100 = Status output – non-inverted polarity
0101 = Status output - inverted polarity of the status bit it follows
0110 = Status output – 0 drives low, 1 high impedance
0111 = Status output – 0 high impedance, 1 drives low
1000 to 1111 = {unused values}
Bits 3 to 0: GPIO0 Configuration (GPIO0C[3:0]). This field configures the GPIO0 pin as a general-purpose input,
a general-purpose output driving low or high, or a status output. The current state of the pin can be read from
GPIOSR.GPIO0. When GPIO0 is a status output, the GPIO0SS register specifies which status bit is output.
0000 = General-purpose input
0001 = General-purpose input - inverted polarity
0010 = General-purpose output driving low
0011 = General-purpose output driving high
0100 = Status output – non-inverted polarity
0101 = Status output - inverted polarity of the status bit it follows
0110 = Status output – 0 drives low, 1 high impedance
0111 = Status output – 0 high impedance, 1 drives low
1000 to 1111 = {unused values}
Register Name:
GPIOCR2
Register Description:
Register Address:
GPIO Configuration Register 2
0Fh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
GPIO3C[3:0]
GPIO2C[3:0]
Default
0
0
0
0
0
0
0
0
These fields are identical to those in GPIOCR1 except they control GPIO2 and GPIO3.
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Register Name:
GPIO0SS
Register Description:
Register Address:
GPIO0 Status Select Register
12h
Bit 7
Bit 6
Bit 5
REG[4:0]
0
Bit 4
Bit 3
Bit 2
Bit 1
BIT[2:0]
0
Bit 0
Name
Default
0
0
0
0
0
0
Bits 7 to 3: Status Register (REG[4:0]). When GPIOCR1.GPIO0C=01xx, this field specifies the register of the
status bit that GPIO0 will follow while the BIT field below specifies the status bit within the register. Setting the
combination of this field and the BIT field below to point to a bit that isn’t implemented as a real-time or latched
status register bit results in GPIO0 being driven low. The address of the status bit that GPIO0 follows is 0x40 +
REG[4:0]
Bits 2 to 0: Status Bit (BIT[2:0]). When GPIOCR1.GPIO0C=01xx, the REG field above specifies the register of
the status bit that GPIO0 will follow while this field specifies the status bit within the register. Setting the
combination of the REG field and this field to point to a bit that isn’t implemented as a real-time or latched status
register bit results in GPIO1 being driven low. 000=bit 0 of the register. 111=bit 7 of the register.
Note: The device does not allow the GPIO status register bits in GPIOSR to be followed by a GPIO.
Register Name:
GPIO1SS
Register Description:
Register Address:
GPIO1 Status Select Register
13h
Bit 7
Bit 6
Bit 5
REG[4:0]
0
Bit 4
Bit 3
Bit 2
Bit 1
BIT[2:0]
0
Bit 0
Name
Default
0
0
0
0
0
0
These fields are identical to those in GPIO0SS except they control GPIO1.
Register Name:
GPIO2SS
Register Description:
Register Address:
GPIO2 Status Select Register
14h
Bit 7
Bit 6
Bit 5
REG[4:0]
0
Bit 4
Bit 3
Bit 2
Bit 1
BIT[2:0]
0
Bit 0
Name
Default
0
0
0
0
0
0
These fields are identical to those in GPIO0SS except they control GPIO2.
Register Name:
GPIO3SS
Register Description:
Register Address:
GPIO3 Status Select Register
15h
Bit 7
Bit 6
Bit 5
REG[4:0]
0
Bit 4
Bit 3
Bit 2
Bit 1
BIT[2:0]
0
Bit 0
Name
Default
0
0
0
0
0
0
These fields are identical to those in GPIO0SS except they control GPIO3.
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Register Name:
PACR1
Register Description:
Register Address:
Phase Adjust Configuration Register 1
1Bh
Bit 7
RST
0
Bit 6
TRIG
0
Bit 5
ARM
0
Bit 4
—
0
Bit 3
—
0
Bit 2
—
0
Bit 1
TINV
0
Bit 0
MODE
0
Name
Default
Bit 7: Phase Adjustment Reset Bit (RST). This bit is used to reset the phase adjustment state machine. This is
used to abort the phase adjustment after arming but before the trigger occurs. Resetting puts the state machine
back to waiting for an arm signal. This bit is self-clearing. See section 5.7.4.
1 = Reset a phase adjustment event in progress, self clearing
Bit 6: Phase Adjustment Trigger Bit (TRIG). This bit is used to trigger the phase adjustment event when
PACR2.TRGSRC=0000 and the phase adjustment has been armed. This bit is self-clearing and must be written
again to cause another trigger. When the ARM bit and TRIG bit are selected as the sources for arming and
triggering, respectively, the ARM bit must be set first then the TRIG bit can be set in a subsequent register write to
initiate a trigger event. See section 5.7.4.
1 = Trigger a phase adjustment, self clearing
Note: For (1) phase adjustment when any OCx output’s MSDIV period is less than master clock period, or
(2) phase alignment when device is in APLL-only mode and any OCx output has MSDIV period + 7 x
HSDIV period < 15.38ns, this bit may or may not self-clear depending on exact device configuration and
therefore must be cleared by system software for proper operation.
Bit 5: Phase Adjustment Arm Bit (ARM). When PACR2.ARMSRC=0001, setting this bit to 1 while
PASR.ARMED=0 arms the phase adjustment. Writing a 0 to this bit has no effect. Changing the value of this bit
from 0 to 1 while PASR.ARMED=1 has no effect. TSee section 5.7.4.
1 = Arm the phase adjustment, self clearing
Bit 1: Phase Adjustment Trigger Invert (TINV). This bit specifies the polarity of the trigger signal. See section
5.7.4.
0 = Trigger signal normal polarity
1 = Trigger signal inverted
Bit 0: Phase Adjust/Alignment Mode (MODE). This field sets the mode of the phase change. In output phase
alignment mode, the device resets the MSDIV and LSDIV dividers for all participating outputs so that they are all
aligned and then adjusts the phase of each participating output as specified in the OCxPH register. In output phase
adjustment mode the device does not reset the MSDIV and LSDIV dividers and therefore causes each participating
output to have the phase adjustment specified in the OCxPH register relative to that output’s previous phase. See
section 5.7.4.
0 = Phase alignment mode
1 = Phase adjustment mode
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Data Sheet
Register Name:
PACR2
Register Description:
Register Address:
Phase Adjust Configuration Register 2
1Ch
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
ARMSRC[3:0]
TRGSRC[3:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 4: Output Phase Adjustment Arm Source (ARMSRC[3:0]). This field selects the source of the phase
adjustment arming signal. See section 5.7.4.
0000 = Always armed (see Note)
0001 = PACR1.ARM bit (one-shot)
0010 = APLL transition from unlocked to locked
0011 to 0111 = {unused values}
1000 = GPIO0 transition (see note below)
1001 = GPIO1 transition
1010 = GPIO2 transition
1011 = GPIO3 transition
1100 to 1111 = {unused values}
Note: When using always armed, any change to the PACR1 or PACR2 registers or any change to the
OCxCR1.PHEN bits must be followed by a reset of the phase adjustment state machine (set
PACR1.RST=1).
Bits 3 to 0: Output Phase Adjustment Trigger Source (TRGSRC[3:0]). This field selects the source of the
phase adjustment trigger signal. The phase adjustment must be armed or the trigger signal is ignored. The trigger
source transition initiates the phase adjustment event. See section 5.7.4.
0000 = PACR1.TRIG bit
0001 = APLL transition from unlocked to locked
0010 to 0111 = {unused values}
1000 = GPIO0 transition (see note below)
1001 = GPIO1 transition
1010 = GPIO2 transition
1011 = GPIO3 transition
1100 to 1111 = {unused values}
Note: In both fields above the GPIO transitions are 0-to-1 when GPIOCR1.GPIOxC=0000 and 1-to-0 when
GPIOCR1.GPIOxC=0001.
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Data Sheet
Register Name:
MABCR1
Register Description:
Register Address:
Measure A-to-B Configuration Register 1
1Dh
Bit 7
RST
0
Bit 6
START
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
Bit 1
TBSRC[2:0]
0
Bit 0
Name
Default
0
0
Bit 7: Measurement Reset (RST). This field stops the current A-to-B phase measurement. This bit is self clearing.
See section 5.7.6.
1 = Stop measurement (self-clearing)
Bit 6: Measurement Start (START). This field starts a new A-to-B phase measurement. This bit is self clearing.
See section 5.7.6.
1= Start new measurement (self-clearing)
Bits 2 to 0: Measurement Time Base Source (TBSRC[2:0]). This field selects the source of the measurement
time base. See section 5.7.6.
000 = {reserved value, do not use}
001 = Medium-speed divider 1 (MSDIV1) output clock
010 = Medium-speed divider 2 (MSDIV2) output clock
011 = Medium-speed divider 3 (MSDIV3) output clock
Register Name:
MABCR2
Register Description:
Register Address:
Measure A-to-B Configuration Register 2
1Eh
Bit 7
AINV
0
Bit 6
—
0
Bit 5
—
0
Bit 4
Bit 3
Bit 2
ASRC[4:0]
0
Bit 1
Bit 0
Name
Default
0
0
0
0
Bit 7: Measurement Input A Invert (AINV). This field inverts the signal of measurement input A. See section
5.7.6.
0 = Measure to and from rising edge of input A
1 = Measure to and from falling edge of input A
Bits 4 to 0: Measurement Input A Source (ASRC[4:0]). This field selects the source of measurement input A.
See section 5.7.6.
00000=IC1
00001=IC2
00010=IC3
01000 = GPIO0
01001 = GPIO1
01010 = GPIO2
01011 = GPIO3
10000=OC1
10001=OC2
10010=OC3
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Data Sheet
Register Name:
MABCR3
Register Description:
Register Address:
Measure A to B Configuration Register 3
1Fh
Bit 7
BINV
0
Bit 6
—
0
Bit 5
—
0
Bit 4
Bit 3
Bit 2
BSRC[4:0]
0
Bit 1
Bit 0
Name
Default
0
0
0
0
Bit 7: Measurement Input B Invert (BINV). This field inverts the signal of measurement input B. See section
5.7.6.
0 = Measure to and from rising edge of input B
1 = Measure to and from falling edge of input B
Bits 4 to 0: Measurement Input B Source (BSRC[4:0]). This field selects the source of measurement input B.
See section 5.7.6.
00000=IC1
00001=IC2
00010=IC3
01000 = GPIO0
01001 = GPIO1
01010 = GPIO2
01011 = GPIO3
10000=OC1
10001=OC2
10010=OC3
6.3.2 Status Registers
Register Name:
ID1
Register Description:
Register Address:
Device Identification Register, MSB
30h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
IDU[7:0]
Bit 2
Bit 1
Bit 0
Name
Default
0
0
0
1
1
0
0
1
Bits 7 to 0: Device ID Upper (IDU[7:0]). This field is the upper eight bits of the device ID.
Register Name:
ID2
Register Description:
Register Address:
Device Identification Register, LSB and Revision
31h
Bit 7
Name
Default
Bit 6
IDL[3:0]
See below
Bit 5
Bit 4
Bit 3
Bit 2
REV[3:0]
0
Bit 1
Bit 0
0
0
1
Bits 7 to 4: Device ID Lower (IDL[3:0]). This field is the lower four bits of the device ID.
ZL30250 = 0000
ZL30251 = 0001
Bits 3 to 0: Device Revision (REV[3:0]). These bits are the device hardware revision starting at 0.
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Register Name:
CFGSR
Register Description:
Register Address:
Configuration Status Register
40h
Bit 7
TEST
see below
Bit 6
XOFAIL
0
Bit 5
—
0
Bit 4
—
0
Bit 3
Bit 2
Bit 1
AC[1:0]
see below see below see below see below
Bit 0
Name
Default
IF[1:0]
Bit 7: Test Mode (TEST). This read-only bit is the latched state of the TEST/GPIO2 pin when the RSTN pin
transitions high. For proper operation it should be 0. See section 5.2.
Bit 6: XO Fail (XOFAIL). This read-only bit is set when the external oscillator signal on the XA pin fails or when the
crystal connected to the XA/XB pins fails to oscillate.
Bits 3 to 2: Interface Mode (IF[1:0]). These read-only bits are the latched state of the IF1/MISO and IF0/CSN pins
when the RSTN pin transitions high. See section 5.2.
Bits 1 to 0: Auto-Configuration (AC[1:0]). These read-only bits are the latched state of the AC1/GPIO1 and
AC0/GPIO0 pins when the RSTN pin transitions high. See section 5.2.
Register Name:
GPIOSR
Register Description:
Register Address:
GPIO Status Register
41h
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
GPIO3
0
Bit 2
GPIO2
0
Bit 1
GPIO1
0
Bit 0
GPIO0
0
Name
Default
Bit 3: GPIO3 State (GPIO3). This real-time status bit indicates the current state of the GPIO3 pin, not influenced
by any inversion that may be specified by GPIOCR2.GPIO3C.
0 = low
1 = high
Bit 2: GPIO2 State (GPIO2). This real-time status bit indicates the current state of the GPIO2 pin, not influenced
by inversion that may be specified by GPIOCR2.GPIO2C.
0 = low
1 = high
Bit 1: GPIO1 State (GPIO1). This real-time status bit indicates the current state of the GPIO1 pin, not influenced
by inversion that may be specified by GPIOCR1.GPIO1C.
0 = low
1 = high
Bit 0: GPIO0 State (GPIO0). This real-time status bit indicates the current state of the GPIO0 pin, not influenced
by inversion that may be specified by GPIOCR1.GPIO0C.
0 = low
1 = high
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Data Sheet
Register Name:
INTSR
Register Description:
Register Address:
Interrupt Status Register
42h
Bit 7
—
0
Bit 6
GLOB
0
Bit 5
OC
0
Bit 4
—
0
Bit 3
—
0
Bit 2
APLL
0
Bit 1
INTIE
0
Bit 0
INT
0
Name
Default
Bit 6: Global Interrupt Status (GLOB). This read-only bit is set if any of the global interrupt status bits are set in
the GLOBISR register. See section 5.9.
Bit 5: Output Clock Interrupt Status (OC). This read-only bit is set if any of the output clock interrupt status bits
are set in the OCISR register. See section 5.9.
Bit 2: APLL Interrupt Status (APLL). This read-only bit is set if any of the APLL interrupt status bits are set in the
APLLISR register. See section 5.9.
Bit 1: Interrupt Enable Bit (INTIE). This is the global interrupt enable bit. When this bit is 0 all interrupt sources
are prevented from setting the INT global interrupt status bit (below). See section 5.9.
0 = Interrupts are disabled at the global level
1 = Interrupts are enabled at the global level
Bit 0: Interrupt Status (INT). This read-only bit is set when any of the GLOB, OC or APLL bits in this INTSR
register are set and the INTIE bit is set. This bit can cause an interrupt request when set by configuring one of the
GPIO pins to follow it. See section 5.9.
0 = No interrupt
1 = An unmasked interrupt source is active
Register Name:
GLOBISR
Register Description:
Register Address:
Global Functions Interrupt Status Register
43h
Bit 7
BCDONE
see below
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
—
0
Bit 1
PA
0
Bit 0
MAB
0
Name
Default
Bit 7: Boot Controller Done (BCDONE). This bit indicates the status of the on-chip boot controller, which
performs auto-configuration from EEPROM. It is cleared when the device is reset and set after the boot controller
finishes auto-configuration of the device. See section 5.12.
Bit 1: Phase Adjust Interrupt Status (PA). This bit indicates the current status of the interrupt sources from the
phase adjust function (see section 5.7.4). It is set when any latched status bit in the PASR register is set and the
associated interrupt enable bit is also set. See section 5.9.
Bit 0: Measure AB Interrupt Status (MAB). This bit indicates the current status of the interrupt sources from the
A-to-B phase offset measurement function (see section 5.7.6). It is set when any latched status bit in the MABSR1
register is set and the associated interrupt enable bit is also set. See section 5.9.
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Data Sheet
Register Name:
OCISR
Register Description:
Register Address:
Output Clock Interrupt Status Register
45h
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
OC3
0
Bit 1
OC2
0
Bit 0
OC1
0
Name
Default
Bit 2: Output Clock 3 Interrupt Status (OC3). This bit indicates the current status of the interrupt sources for
OC3. It is set when any latched status bit in the OC3SR register is set and the associated interrupt enable bit is
also set. See section 5.9.
Bit 1: Output Clock 2 Interrupt Status (OC2). This bit indicates the current status of the interrupt sources for
OC2. It is set when any latched status bit in the OC2SR register is set and the associated interrupt enable bit is
also set. See section 5.9.
Bit 0: Output Clock 1 Interrupt Status (OC1). This bit indicates the current status of the interrupt sources for
OC1. It is set when any latched status bit in the OC1SR register is set and the associated interrupt enable bit is
also set. See section 5.9.
Register Name:
APLLISR
Register Description:
Register Address:
APLL Interrupt Status Register
46h
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
—
0
Bit 1
—
0
Bit 0
APLL
0
Name
Default
Bit 0: APLL Interrupt Status (APLL). This bit indicates the current status of the interrupt sources for the APLL. It
is set when any latched status bit in the APLLSR register is set and the associated interrupt enable bit is also set.
See section 5.9.
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Data Sheet
Register Name:
APLLSR
Register Description:
Register Address:
APLL Status Register
48h
Bit 7
—
0
Bit 6
ALK2IE
0
Bit 5
ALK2L
0
Bit 4
ALK2
0
Bit 3
—
0
Bit 2
ALKIE
0
Bit 1
ALKL
0
Bit 0
ALK
0
Name
Default
Bit 6: APLL Lock 2 Interrupt Enable (ALK2IE). This bit enables the ALK2L latched status bit to send an interrupt
request into device’s interrupt logic.
0 = Interrupt is disabled
1 = Interrupt is enabled
Bit 5: APLL Lock 2 Latched Status (ALK2L). This latched status bit is set to 1 when the ALK2 status bit changes
state (set or cleared). ALK2L is cleared when written with a 1. When ALK2L is set it can cause an interrupt request
if the ALK2IE interrupt enable bit is set.
Bit 4: APLL Lock Status 2 (ALK2). This real-time status bit provides one type of APLL lock status. System
software should consider the APLL locked when ALK (bit 0) is set to 1 AND ALK2=1. See section 5.6.
Bit 2: APLL Lock Interrupt Enable (ALKIE). This bit enables the ALKL latched status bit to send an interrupt
request into device’s interrupt logic.
0 = Interrupt is disabled
1 = Interrupt is enabled
Bit 1: APLL Lock Latched Status (ALKL). This latched status bit is set to 1 when the ALK status bit changes
state (set or cleared). ALKL is cleared when written with a 1. When ALKL is set it can cause an interrupt request if
the ALKIE interrupt enable bit is set.
Bit 0: APLL Lock Status (ALK). This real-time status bit indicates one type of APLL lock status. System software
should consider the APLL locked when ALK=1 AND ALK2 (bit 4) is set to 1. See section 5.6.
0 = Not locked
1 = Locked
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Data Sheet
Register Name:
MABSR1
Register Description:
Register Address:
Measure A to B Status Register 1
4Bh
Bit 7
—
0
Bit 6
OVFL
0
Bit 5
RDYIE
0
Bit 4
RDYL
0
Bit 3
BUSY
0
Bit 2
Bit 1
MEAS[10:8]
0
Bit 0
Name
Default
0
0
Bit 6: Measurement Overflow (OVFL). This latched status bit is set when the phase measurement is ready and
an overflow has occurred. See section 5.7.6.
0 = No measurement overflow, MEAS is a valid value
1 = A measurement overflow occured, MEAS is not a valid value
Bit 5: Measurement Ready Interrupt Enable (RDYIE). This bit enables the RDYL latched status bit to send an
interrupt request into device’s interrupt logic.
0 = Interrupt is disabled
1 = Interrupt is enabled
Bit 4: Measurement Ready (RDYL). This latched status bit is set when a new phase measurement is ready. See
section 5.7.6.
0 = New measurement not ready
1 = A new measurement in MEAS is ready
Bit 3: Measurement Busy (BUSY). This real-time status bit is set when a new phase measurement is being
performed. See section 5.7.6.
0 = A measurement is not being performed
1 = A measurement is being performed
Bits 2 to 0: Measurement Value (MEAS[10:8]). See the MABSR2 register description.
Register Name:
MABSR2
Register Description:
Register Address:
Measure A to B Status Register 2
4Ch
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
MEAS[7:0]
Bit 2
Bit 1
Bit 0
Name
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Measurement Value (MEAS[7:0]). The full 11-bit MEAS[10:0] field spans this register and the lower
bits of MABSR1. The format is two’s-complement. This field indicates the result of the A-to-B measurement when
BUSY=0, RDYL=1 and OVFL=0. Its value is in units of the selected timebase period and has a range of +1023 to
-1024 periods. See section 5.7.6.
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Register Name:
PASR
Register Description:
Register Address:
Phase Adjust Status Register
4Dh
Bit 7
—
1
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
ADJIE
0
Bit 2
ADJL
1
Bit 1
BUSY
0
Bit 0
ARMED
0
Name
Default
Bit 3: Phase Adjustment Finished Interrupt Enable (ADJIE). This bit enables the ADJL latched status bit to
send an interrupt request into the device’s interrupt logic.
0 = Interrupt is disabled
1 = Interrupt is enabled
Bit 2: Phase Adjustment Finished (ADJL). This latched status bit is set when the output phase adjustment is
completed for all participating outputs. Writing a 1 to this bit clears it. See section 5.7.4.
0 = Output phase adjustment has not completed
1 = Output phase adjustment has completed
Note: For (1) phase adjustment when any OCx output’s MSDIV period is less than master clock period, or
(2) phase alignment when device is in APLL-only mode and any OCx output has MSDIV period + 7 x
HSDIV period < 15.38ns, this bit may or may not be set depending on exact device configuration and
therefore should not be checked by system software. Instead the state of the BUSY real-time bit (bit 1)
should be checked.
Bit 1: Phase Adjustment Busy (BUSY). This bit is a real time status that indicates that the output phase
adjustment has been triggered and is in progress on the participating outputs. See section 5.7.4.
0 = Output phase adjustment is not in progress
1 = Output phase adjustment is in progress
Bit 0: Phase Adjustment Armed (ARMED). This bit is a real time status that indicates that the output phase
adjustment is armed and waiting for a trigger. It is cleared when the trigger event occurs. See section 5.7.4.
0 = Output phase adjustment is not armed
1 = Output phase adjustment is armed
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Data Sheet
Register Name:
OCxSR
Register Description:
Register Address:
Output Clock x Status Register
OC1: 53h, OC2: 54h, OC3: 55h
Bit 7
LSCLKIE
0
Bit 6
LSCLKL
0
Bit 5
LSCLK
0
Bit 4
STARTIE
0
Bit 3
STARTL
0
Bit 2
STOPIE
0
Bit 1
STOPL
see note
Bit 0
STOPD
see note
Name
Default
Bit 7: (LSCLKIE). This bit enables the LSCLKL latched status bit to send an interrupt request into device’s
interrupt logic.
0 = Interrupt is disabled
1 = Interrupt is enabled
Bit 6: (LSCLKL). This latched status bit is set when the low-speed divider output clock transitions low-to-high.
Writing a 1 to this bit clears it.
0 = Low speed output clock has not transitioned low to high
1 = Low speed output clock has transitioned low to high
Bit 5: (LSCLK). This real-time status bit follows the level of the low-speed divider output clock when the
OCxCR3.SRLSEN bit is set.
0 = LSCLK is high
1 = LSCLK is low
Bit 4: (STARTIE). This bit enables the STARTL latched status bit to send an interrupt request into device’s
interrupt logic.
0 = Interrupt is disabled
1 = Interrupt is enabled
Bit 3: (STARTL). This latched status bit is set when the output clock signal has been started after being stopped.
Writing a 1 to this bit clears it. See section 5.7.5.
0 = Output clock signal has not resumed from being stopped
1 = Output clock signal has resumed from being stopped
Bit 2: (STOPIE). This bit enables the STOPL latched status bit to send an interrupt request into device’s interrupt
logic.
0 = Interrupt is disabled
1 = Interrupt is enabled
Bit 1: (STOPL). This latched status bit is set when the output clock signal has been stopped. Writing a 1 to this bit
clears it. See section 5.7.5.
0 = Output clock signal has not stopped
1 = Output clock signal has stopped
Bit 0: (STOPD). This real-time status bit is high when the output clock signal is stopped and low when the output
clock is not stopped. See section 5.7.5.
0 = Output clock signal is not stopped
1 = Output clock signal is stopped
Note: STOPL and STOPD are controlled by logic that does not have a clock at reset. Therefore their reset values
are indeterminate. They will become 0 when the output clock path is configured and one of the high-speed clocks
from the APLL is connected to the logic.
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Data Sheet
6.3.3 APLL Configuration Registers
Register Name:
APLLCR1
Register Description:
Register Address:
APLL Configuration Register 1
100h
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
ENHS2
0
Bit 1
BYPHS2
0
Bit 0
—
0
Name
Default
Bit 2: Enable High-Speed Divider 2 (ENHS2). This bit is an enable/disable control for HSDIV2. When HSDIV2 is
disabled, device power consumption is reduced as shown in Table 6. HSDIV2 is enabled when PLLEN.APLLEN=1,
ENHS2=1 and APLLCR1.BYPHS2=0.
0 = Disable
1 = Enable
Bit 1: Bypass APLL and High-Speed Divider 2 (BYPHS2). This bit controls the mux immediately to the right of
HSDIV2 in Figure 1. The mux that provides the bypass signal to this mux is controlled by APLLMUX and related
fields in APLLCR3.
0 = No bypass
1 = Bypass
Register Name:
APLLCR2
Register Description:
Register Address:
APLL Configuration Register 2
101h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
HSDIV2[3:0]
HSDIV1[3:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 4: APLL High-Speed Divider 2 (HSDIV2[3:0]). This field controls the APLL’s high-speed divider 2 block
(see Figure 6). See section 5.6.2.
0000 = Divide by 4
0001 = Divide by 4.5
0010 = Divide by 5
0011 = Divide by 5.5
0100 = Divide by 6
0101 = Divide by 6.5
0110 = Divide by 7
0111 = Divide by 7.5
1000 = Divide by 8
1001 = Divide by 9
1010 = Divide by 10
1011 = Divide by 11
1100 = Divide by 12
1101 = Divide by 13
1110 = Divide by 14
1111 = Divide by 15
Bits 3 to 0: APLL High-Speed Divider 1 (HSDIV1[3:0]). This field controls the APLL’s high-speed divider 1 block
(see Figure 6). See section 5.6.2.
0000 = Divide by 4
0001 = Divide by 4.5
0010 = Divide by 5
0011 = Divide by 5.5
0100 = Divide by 6
0101 = Divide by 6.5
0110 = Divide by 7
0111 = Divide by 7.5
1000 = Divide by 8
1001 = Divide by 9
1010 = Divide by 10
1011 = Divide by 11
1100 = Divide by 12
1101 = Divide by 13
1110 = Divide by 14
1111 = Divide by 15
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Register Name:
APLLCR3
Register Description:
Register Address:
APLL Configuration Register 3
102h
Bit 7
—
0
Bit 6
EXTSW
0
Bit 5
Bit 4
ALTMUX[2:0]
0
Bit 3
Bit 2
Bit 1
APLLMUX[2:0]
0
Bit 0
Name
Default
0
0
0
0
Bit 6: APLL External Switching Mode (EXTSW). This bit enables APLL external reference switching mode. In
this mode, if the selected GPIO signal is low the APLL input mux is controlled by APLLCR3.APLLMUX. If the
selected GPIO signal is high the APLL input mux is controlled by APLLCR3.ALTMUX. MCR2.EXTSS specifies
which GPIO pin controls this behavior. See section 5.6.1
Bits 5 to 3: APLL Alternate Mux Control (ALTMUX[2:0]). When APLLCR3.EXTSW=0 this field is ignored. When
APLLCR3.EXTSW=1 and the selected GPIO signal is high, this field controls the APLL input muxes. See section
5.6.1.
000 = Crystal driver circuit if crystal is connected, otherwise XA input
(clock frequency can be 2x if clock doubler enabled by MCR1.DBL=1)
001 = IC1 input
010 = IC2 input
011 = IC3 input
100-111 = {unused values}
Bits 2 to 0: APLL Mux Control (APLLMUX[2:0]). By default this field controls the APLL input muxes. When
APLLCR3.EXTSW=1 and the selected GPIO signal is high, this field is ignored, and the APLL's clock source is
specified by APLLCR3.ALTMUX. See section 5.6.1.
000 = Crystal driver circuit if crystal is connected, otherwise XA input
(clock frequency can be 2x if clock doubler enabled by MCR1.DBL=1)
001 = IC1 input
010 = IC2 input
011 = IC3 input
110 = NCO/SS output to the APLL, XA (optionally doubled) sent to the bypass mux
111 = NCO/SS output to the APLL, no signal sent to the bypass mux (set APLLCR1.BYPHS2=0)
The following decodes are for applications where the NCO/SS master clock comes from IC1 rather than
XA (MCR1.MCSEL1=1).
100 = NCO/SS output to the APLL, IC1 sent to the bypass mux
101 = NCO/SS output to the APLL, no signal sent to the bypass mux (set APLLCR1.BYPHS2=0)
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Data Sheet
Register Name:
APLLCR4
Register Description:
Register Address:
APLL Configuration Register 4
103h
Bit 7
DECPH
0
Bit 6
Bit 5
PDSS[2:0]
0
Bit 4
Bit 3
INCPH
0
Bit 2
Bit 1
PISS[2:0]
0
Bit 0
Name
Default
0
0
0
0
Bit 7: Decrement Phase (DECPH). When PDSS=000, this bit is the APLL phase decrement control signal. See
section 5.6.3. Decrement moves the signal earlier in time (to the left on a scope).
Bits 6 to 4: Phase Decrement Source Select (PDSS[2:0]). This field specifies the APLL phase decrement control
signal. Every low-to-high transition and every high-to-low transition of the signal decrements the APLL’s output
phase. See section 5.6.3.
000 = DECPH bit
001 = GPIO0
010 = GPIO1
011 = GPIO2
100 = GPIO3
101 to 111 = {unused values}
Bit 3: Increment Phase (INCPH). When PISS=000, this bit is the APLL phase increment control signal. See
section 5.6.3. Increment moved the signal later in time (to the right on a scope).
Bits 2 to 0: Phase Increment Source Select (PISS[2:0]). This field specifies the APLL phase increment control
signal. Every low-to-high transition and every high-to-low transition of the signal increments the APLL’s output
phase. See section 5.6.3.
000 = INCPH bit
001 = GPIO0
010 = GPIO1
011 = GPIO2
100 = GPIO3
101 to 111 = {unused values}
Register Name:
AFBDIV1
Register Description:
Register Address:
APLL Feedback Divider Register 1
106h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBDIV[7:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Register (AFBDIV[7:0]). The full 42-bit AFBDIV[41:0] field spans the
AFBDIV1 through AFBDIV6 registers. AFBDIV is an unsigned number with 9 integer bits (AFBDIV[41:33]) and up
to 33 fractional bits. AFBDIV specifies the fixed-point term of the APLL's fractional feedback divide value. The value
AFBDIV=0 is undefined. Unused least significant bits must be written with 0. See section 5.6.2.
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Data Sheet
Register Name:
AFBDIV2
Register Description:
Register Address:
APLL Feedback Divider Register 2
107h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBDIV[15:8]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Register (AFBDIV[15:8]). See the AFBDIV1 register description.
Register Name:
AFBDIV3
Register Description:
Register Address:
APLL Feedback Divider Register 3
108h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBDIV[23:16]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Register (AFBDIV[23:16]). See the AFBDIV1 register description.
Register Name:
AFBDIV4
Register Description:
Register Address:
APLL Feedback Divider Register 4
109h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBDIV[31:24]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Register (AFBDIV[31:24]). See the AFBDIV1 register description.
Register Name:
AFBDIV5
Register Description:
APLL Feedback Divider Register 5
Register Address:
10Ah
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBDIV[39:32]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Register (AFBDIV[39:32]). See the AFBDIV1 register description.
Register Name:
AFBDIV6
Register Description:
Register Address:
APLL Feedback Divider Register 6
10Bh
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
—
Bit 2
—
Bit 1
AFBDIV[41:40]
Bit 0
Name
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Register (AFBDIV[41:40]). See the AFBDIV1 register description.
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Data Sheet
Register Name:
AFBDEN1
Register Description:
Register Address:
APLL Feedback Divider Denominator Register 1
10Ch
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBDEN[7:0]
Default
0
0
0
0
0
0
0
1
Bits 7 to 0: APLL Feedback Divider Denominator Register (AFBDEN[7:0]). The full 32-bit AFBDEN[31:0] field
spans AFBDEN1 through AFBDEN4 registers. AFBDEN is an unsigned integer that specifies the denominator of
the APLL's fractional feedback divide value. The value AFBDEN=0 is undefined. When AFBBP=0, AFBDEN must
be set to 1. See section 5.6.2.
Register Name:
AFBDEN2
Register Description:
Register Address:
APLL Feedback Divider Denominator Register 2
10Dh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBDEN[15:8]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Denominator Register (AFBDEN[15:8]). See the AFBDEN1 register
description.
Register Name:
AFBDEN3
Register Description:
Register Address:
APLL Feedback Divider Denominator Register 3
10Eh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBDEN[23:16]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Denominator Register (AFBDEN[23:16]). See the AFBDEN1 register
description.
Register Name:
AFBDEN4
Register Description:
Register Address:
APLL Feedback Divider Denominator Register 4
10Fh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBDEN[31:24]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Denominator Register (AFBDEN[31:24]). See the AFBDEN1 register
description.
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Data Sheet
Register Name:
AFBREM1
Register Description:
Register Address:
APLL Feedback Divider Remainder Register 1
110h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBREM[7:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Remainder Register (AFBREM[7:0]). The full 32-bit AFBDEN[31:0] field
spans AFBREM1 through AFBREM4 registers. AFBREM is an unsigned integer that specifies the remainder of the
APLL's fractional feedback divider value. When AFBBP=0, AFBREM must be set to 0. See section 5.6.2.
Register Name:
AFBREM2
Register Description:
Register Address:
APLL Feedback Divider Remainder Register 2
111h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBREM[15:8]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Remainder Register (AFBREM[15:8]). See the AFBREM1 register
description.
Register Name:
AFBREM3
Register Description:
Register Address:
APLL Feedback Divider Remainder Register 3
112h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBREM[23:16]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Remainder Register (AFBREM[23:16]). See the AFBREM1 register
description.
Register Name:
AFBREM4
Register Description:
Register Address:
APLL Feedback Divider Remainder Register 4
113h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBREM[31:24]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Remainder Register (AFBREM[31:24]). See the AFBREM1 register
description.
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Data Sheet
Register Name:
AFBBP
Register Description:
Register Address:
APLL Feedback Divider Truncate Bit Position
114h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBBP[7:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Truncate Bit Position (AFBBP[7:0]). This unsigned integer specifies the
number of fractional bits that are valid in the AFBDIV value. There are 33 fractional bits in AFBDIV. The value in
this AFBBP field specifies 33 – number_of_valid_AFBDIV_fractional_bits. When AFBBP=0 all 33 AFBDIV fractional
bits are valid. When AFBBP=9, the most significant 24 AFBDIV fractional bits are valid and the least significant 9
bits must be set to 0. This register field is only used when the feedback divider value is expressed in the form
AFBDIV + AFBREM / AFBDEN. AFBBP values greater than 33 are invalid. When AFBBP=0, AFBREM must be set
to 0 and AFBDEN must be set to 1. See section 5.6.2.
6.3.4 Output Clock Configuration Registers
Register Name:
OCxCR1
Register Description:
Register Address:
Output Clock x Configuration Register 1
OC1: 200h, OC2: 210h, OC3: 220h
Bit 7
PHEN
0
Bit 6
Bit 5
Bit 4
Bit 3
MSDIV[6:0]
0
Bit 2
Bit 1
Bit 0
Name
Default
0
0
0
0
0
0
Bit 7: Phase Adjust Enable (PHEN). This bit enables this output to participate in phase adjustment/alignment.
See section 5.7.4.
0 = Phase adjustment/alignment disabled for this output
1 = Phase adjustment/alignment enabled for this output
Bits 6 to 0: Medium-Speed Divider Value (MSDIV[6:0]). This field specifies the setting for the output clock's
medium-speed divider. The divisor is MSDIV+1. Note that if MSDIV is not set to 0 (bypass) then MSDIV must be
set to a value that causes the output clock of the medium-speed divider to be 425MHz or less. When MSDIV=0, the
medium-speed divider, phase adjust, low-speed divider, start/stop and output duty cycle adjustment circuits are
bypassed and the high-frequency clock signal is directly sent to the output driver. See section 5.7.2.
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Data Sheet
Register Name:
OCxCR2
Register Description:
Register Address:
Output Clock x Configuration Register 2
OC1: 201h, OC2: 211h, OC3: 221h
Bit 7
—
0
Bit 6
POL
0
Bit 5
Bit 4
Bit 3
STOPDIS
0
Bit 2
Bit 1
OCSF[2:0]
0
Bit 0
Name
Default
DRIVE[1:0]
0
0
0
0
Bit 6: Clock Path Polarity (POL). The clock path to the CML, HSTL and CMOS outputs is inverted when this bit
set. This does not invert the LSDIV path to the CMOS OCxN pin if that path is enabled. See section 5.7.1.
Bits 5 to 4: CMOS/HSTL Output Drive Strength (DRIVE[1:0]). The CMOS/HSTL output drivers have four equal
sections that can be enabled or disabled to achieve four different drive strengths from 1x to 4x. When the output
power supply VDDOx is 3.3V or 2.5V, the user should start with 1x and only increase drive strength if the output is
highly loaded and signal transition time is unacceptable. When VDDOx is 1.8V or 1.5V the user should start with 4x
and only decrease drive strength if the output signal has unacceptable overshoot. See section 5.7.1.
00 = 1x
01 = 2x
10 = 3x
11 = 4x
Bit 3: Stop Disable (STOPDIS). This bit causes the output to become disabled (high impedance) while the output
clock is stopped. See section 5.7.5.
0 = Do not disable the output while stopped
1 = Disable the output while stopped
Bits 2 to 0: Output Clock Signal Format (OCSF[2:0]). Note that OCEN.OCxEN=0 forces the output driver to be
high-impedance regardless of the value of the OCSF register field. See section 5.7.1.
000 = Disabled (high-impedance, low power mode)
001 = CML, standard swing (VOD =800mVP-P typical)
010 = CML, narrow swing (VOD =400mVP-P typical)
011 = HSTL (Set OCxCR2.DRIVE=11 (4x) to meet JESD8-6)
100 = Two CMOS: OCxP in phase with OCxN
101 = One CMOS: OCxP high impedance, OCxN enabled
110 = One CMOS: OCxP enabled, OCxN high impedance
111 = Two CMOS: OCxP inverted vs. OCxN
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Data Sheet
Register Name:
OCxCR3
Register Description:
Register Address:
Output Clock x Configuration Register 3
OC1: 202h, OC2: 212h, OC3: 222h
Bit 7
SRLSEN
0
Bit 6
DIVSEL
0
Bit 5
NEGLSD
0
Bit 4
LSSEL
0
Bit 3
—
0
Bit 2
—
0
Bit 1
—
0
Bit 0
LSDIV[24]
0
Name
Default
Bit 7 Enable LSDIV Statuses (SRLSEN). This bit enables the OCxSR.LSCLK real-time status bit and its
associated latched status bit OCxSR.LSCLKL.
0 = LSCLK status bit is not enabled (low)
1 = LSCLK status bit is enabled
Bit 6: High Speed Divider Select (DIVSEL). This bit selects which high-speed divider is the source of the clock for
the output. See section 5.7.2.
0 = HSDIV1
1 = HSDIV2
Bit 5: OCxN Low Speed Divider (NEGLSD). This bit selects the source of the clock on the OCxN pin in CMOS
mode. See section 5.7.2.
0 = Same as OCxP
1 = Output of the LSDIV divider
Note: NEGLSD should only be set to one in two-CMOS mode (OCxCR2.OCSF=100 or 111) and when
OCxCR2.POL=0.
Bit 4: LSDIV Select (LSSEL). This bit selects the source of the output clock. When the MSDIV divider is selected
(LSSEL=0) the LSDIV divider output can be independently selected as the source for the OCxN pin (in CMOS
output mode) or monitored by the OCxSR.LSCLK status bit. This bit is only valid when OCxCR1.MSDIV > 0. See
section 5.7.2.
0 = The output clock is sourced from the MSDIV divider.
1 = The output clock is sourced from the LSDIV divider.
Bit 0: Low-Speed Divider Value (LSDIV[24]). See the OCxDIV1 register description.
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Data Sheet
Register Name:
OCxDIV1
Register Description:
Register Address:
Output Clock x Divider Register 1
OC1: 203h, OC2: 213h, OC3: 223h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
LSDIV[7:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Low-Speed Divider Value (LSDIV[7:0]). The full 25-bit LSDIV[24:0] field spans this register,
OCxDIV2, OCxDIV3. and bit 0 of OCxCR3. LSDIV is an unsigned integer. The frequency of the clock from the
medium-speed divider is divided by LSDIV+1. The OCxCR3.LSSEL and NEGLSD bits control when the output of
the low-speed divider is present on the OCxP and OCxN output pins. OCxCR1.MSDIV must be > 0 for the low-
speed divider to operate. See section 5.7.2.
Register Name:
OCxDIV2
Register Description:
Register Address:
Output Clock x Divider Register 2
OC1: 204h, OC2: 214h, OC3: 224h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
LSDIV[15:8]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Low-Speed Divider Value (LSDIV[15:8]). See the OCxDIV1 register description.
Register Name:
OCxDIV3
Register Description:
Register Address:
Output Clock x Divider Register 3
OC1: 205h, OC2: 215h, OC3: 225h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
LSDIV[23:16]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Low-Speed Divider Value (LSDIV[23:16]). See the OCxDIV1 register description.
Register Name:
OCxDC
Register Description:
Register Address:
Output Clock x Duty Cycle Register
OC1: 206h, OC2: 216h, OC3: 226h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
OCDC[7:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Output Clock Duty Cycle (OCDC[7:0]). This field controls the output clock signal duty cycle when
MSDIV>0 and LSDIV>1. When OCDC = 0 the output clock is 50%. Otherwise the clock signal is a pulse with a
width of OCDC number of MSDIV output clock periods. The range of OCDC can create pulse widths from 1 to 255
MSDIV output clock periods. When OCxCR2.POL=0, the pulse is high and the signal is low the remainder of the
cycle. When POL=1, the pulse is low and the signal is high the remainder of the cycle. See section 5.7.3.
Note: Rev A devices require MSDIV>5.
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Data Sheet
Register Name:
OCxPH
Register Description:
Register Address:
Output Clock x Phase Adjust Register
OC1: 207h, OC2: 217h, OC3: 227h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PHADJ[7:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Phase Adjust Value (PHADJ[7:0]). When OCxCR1.PHEN=1, this field specifies the phase
adjustment of the output clock during a phase adjustment event. When OCxCR1.PHEN=0, this field is ignored. The
specified phase adjustment occurs once during a phase adjustment event. The format of the field is 2’s-
complement with the LSB being one half of an HSDIV output clock period. Positive values move the signal later in
time (to the right on a scope). See section 5.7.4.
00000000 = 0.0 UI
00000001 = +0.5 UI
00000010 = +1.0 UI
00000011 = +1.5 UI
…
01111110 = +63.0 UI
01111111 = +63.5 UI
10000000 = -64.0 UI
10000001 = -63.5 UI
…
11111101 = -1.5 UI
11111110 = -1.0 UI
11111111 = -0.5 UI
Register Name:
OCxSTOP
Register Description:
Register Address:
Output Clock x Start Stop Register
OC1: 208h, OC2: 218h, OC3: 228h
Bit 7
STOP
0
Bit 6
—
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Default
SRC[3:0]
MODE[1:0]
0
0
0
0
0
0
Bit 7: Output Clock Stop (STOP). When SRC=0000, this bit is used to stop the output clock high or low. The
output stays stopped while this bit is high. See section 5.7.5.
0 = Do not stop the output clock
1 = Stop the output clock
Bits 5 to 2: Output Clock Stop Source (SRC[3:0]). This field specifies the source of the stop signal. See section
5.7.5.
0000 = STOP bit
0001 = The arming of a phase adjustment (signal stopped when PASR.ARMED is asserted; signal started
when PASR.ADJL is asserted)
0010 to 0111 = {unused values}
1000 = GPIO0
1001 = GPIO1
1010 = GPIO2
1011 = GPIO3
1100 to 1111 = {unused values}
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Data Sheet
Bits 1 to 0: Output Clock Stop Mode (MODE[1:0]). This field selects the mode of the start-stop function. See
section 5.7.5.
00 = Never stop
01 = Stop High: stop after rising edge of output clock, start after falling edge of output clock
10 = Stop Low: stop after falling edge of output clock, start after rising edge of output clock
11 = {unused value}
The following table shows which pin(s) stop high or low as specified above for each output signal format:
Signal Format
OCxCR2.OCSF Pin that Stops As Specified
CML
HSTL
001 or 010
011
OCxP
OCxN
Two CMOS, OCxP in phase with OCxN
One CMOS, OCxN enabled
One CMOS, OCxP enabled
Two CMOS, OCxP inverted vs. OCxN
100
101
110
111
OCxP and OCxN
OCxN
OCxP
OCxN
Notes:
1. The highest priority condition for an output is when it is stopped and OCxCR2.STOPDIS=1. When this
condition occurs both OCxP and OCxN become high-impedance regardless of the state of the control
bits mentioned below.
2. When the output is not stopped or when OCxCR2.STOPDIS=0, OCxCR3.NEGLSD=1 causes the OCxN
pin to follow the output clock of the low-speed divider uninverted regardless of the signal format,
regardless of the state of OCxCR2.POL, and regardless of whether the output is stopped.
3. When the above situations do not apply, OCxCR2.POL=1 changes Stop High to Stop Low and vice
versa.
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6.3.5 Input Clock Configuration Registers
Data Sheet
Register Name:
ICxCR1
Register Description:
Register Address:
Input Clock x Configuration Register 1
IC1: 300h, IC2: 320h, IC3: 340h
Bit 7
—
0
Bit 6
POL
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
—
0
Bit 1
Bit 0
Name
Default
HSDIV[1:0]
0
0
Bit 6: Locking Polarity (POL). This field specifies which input clock signal edge the APLL will lock to. See section
5.6.1.
0 = Rising edge
1 = Falling edge
Bits 1 to 0: Input Clock High-Speed Divider (HSDIV[1:0]). This field specifies the divide value for the input clock
high-speed divider. See section 5.6.1.
00 = Divide by 1
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8
6.3.6 NCO/Spread-Spectrum Configuration Registers
Register Name:
NCSSCR1
Register Description:
Register Address:
NCO/SS Configuration Register 1
40Bh
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
Bit 2
Bit 1
Bit 0
Name
MODE[3:0]
Default
0
0
0
0
0
0
0
0
Bits 3 to 0: NCO/SS Mode (MODE[3:0]). This field selects the operational mode of the NCO/SS block. See
section 5.5.
0000: Reset
0001: NCO
0010: Spread-spectrum
all other values are invalid
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Data Sheet
Register Name:
DFREQZ1
Register Description:
Register Address:
Digital Frequency Tuning Word Register 1
420h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
FREQZ[7:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Digital Frequency Tuning Word (FREQZ[7:0]). The full 40-bit DFREQZ[39:0] field spans this register
and the DFREQZ2 to DFREQZ5 registers and is a multi-register field (see section 6.1.3). This unsigned coefficient
is the frequency tuning word value that sets the frequency the NCO/SS block generates in NCO mode. It is also the
base frequency to which the NCO/SS adds a dynamic offset during spread spectrum mode. The nominal value of
this field is set by the evaluation software. In NCO mode, system software can change this value by any fraction
(less than 1 ppb to multiple ppm) to cause a fractional change in the device’s output frequency. See section 5.5.1.
Register Name:
DFREQZ2
Register Description:
Register Address:
Digital Frequency Tuning Word Register 2
421h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
FREQZ[15:8]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Digital Frequency Tuning Word (FREQZ[15:8]). See the DFREQZ1 register description.
Register Name:
DFREQZ3
Register Description:
Register Address:
Digital Frequency Tuning Word Register 3
422h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
FREQZ[23:16]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Digital Frequency Tuning Word (FREQZ[23:16]). See the DFREQZ1 register description.
Register Name:
DFREQZ4
Register Description:
Register Address:
Digital Frequency Tuning Word Register 4
423h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
FREQZ[31:24]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Digital Frequency Tuning Word (FREQZ[31:24]). See the DFREQZ1 register description.
Register Name:
DFREQZ5
Register Description:
Register Address:
Digital Frequency Tuning Word Register 5
424h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
FREQZ[39:32]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Digital Frequency Tuning Word (FREQZ[39:32]). See the DFREQZ1 register description.
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ZL30250, ZL30251
Data Sheet
7. Electrical Characteristics
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Supply voltage, nominal 1.8V
VDD18
-0.3
1.98
V
Supply voltage, nominal 3.3V
VDD33
VDDOx
VANAPIN
VDIGPIN
TST
-0.3
-0.3
-0.3
-0.3
-55
3.63
3.63
3.63
5.5
V
V
Supply voltage, VDDOx (x=1,2,3)
Voltage on XA, any ICxP/N, any OCxP/N pin
Voltage on any digital I/O pin
V
V
Storage Temperature Range
+125
°C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (VSS) unless otherwise stated.
Note 1: The typical values listed in the tables of Section 7 are not production tested.
Note 2: Specifications to -40C and 85C are guaranteed by design or characterization and not production tested.
Table 5 - Recommended DC Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Units
Supply voltage, nominal 1.8V
VDD18
1.71
1.8
1.89
V
Supply voltage, nominal 3.3V
Supply voltage, VDDOx (x=1,2,3)
Operating temperature
VDD33
VDDOx
TA
3.135
3.3
3.465
V
V
1.425
1.71
2.375
3.135
1.5
1.8
2.5
3.3
1.575
1.89
2.625
3.465
-40
+85
°C
Table 6 - Electrical Characteristics: Supply Currents
Characteristics
Symbol
Min.
Typ.1
Max
Units
Notes
Total power, one input and one nomal-swing
CML output enabled, XA/XB disabled
Total current, all 1.8V supply pins, NCO and
SSM modes
Total current, all 3.3V supply pins, NCO and
SSM modes
Total current, all 1.8V supply pins, APLL-only
mode
Total current, all 3.3V supply pins, APLL-only
mode
PDISS
0.57
W
IDD18
242
184
208
168
16
20
28
10
17
10
9
297
225
251
206
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note 2
Note 2
Note 2
Note 2
IDD33
IDD18
IDD33
3.3V supply current change from enabling or
disabling the crystal driver circuit
3.3V supply current change from enabling or
disabling high-speed divider 2
IDD33XTAL
IDD33HSD
IDD18ODIV
IDD18CML
IDD33CML
IDD18CMLN
IDD33CMLN
IDD18CMOS
IDD33CMOS
1.8V supply current from enabling/disabling per-
output mux and dividers using OCEN.OCxEN bit
1.8V supply current change from enabling or
disabling a CML output, standard swing
3.3V supply current change from enabling or
disabling a CML output, standard swing
1.8V supply current change from enabling or
disabling a CML output, narrow swing
3.3V supply current change from enabling or
disabling a CML output, narrow swing
1.8V supply current change from enabling or
disabling a pair of single-ended outputs
VDDOx supply current change from enabling or
disabling a pair of single-ended outputs
2
16
Note 3
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ZL30250, ZL30251
Data Sheet
Characteristics
1.8V supply current change from enabling or
disabling an input clock
Symbol
Min.
Typ.1
Max
Units
Notes
13
mA
IDD18IN
Note 1:
Note 2:
Typical values measured at 1.80V and 3.30V supply voltages and 25C ambient temperature.
Max IDD measurements made with all blocks enabled, 650MHz signals on IC1 and IC2 inputs, 187.5MHz signal on IC3, VCO
frequency of 3750MHz, both HSDIV enabled and dividing by 6, all MSDIV dividing by 2, all LSDIV dividing by 2, and all outputs
enabled as full-swing CML outputs driving 156.25MHz signals. NCO or SSM modes: 114.285M XO master clock on XA. APLL-
only mode: Crystal driver and doubler off, guaranteed by design.
Note 3:
VDDOx=3.3V, 1x drive strength, fO=250MHz, 2pF load
Table 7 - Electrical Characteristics: Non-clock CMOS Pins
Characteristics
Symbol
Min.
0.7 x
VDD33
Typ.
Max.
Units
Notes
VIH
Input high voltage, SCL and SDA
V
0.3 x
VDD33
VIL
Input low voltage, SCL and SDA
V
VIH
VIL
Input high voltage, all other digital inputs
Input low voltage, all other digital inputs
2.0
V
V
0.8
10
IILPU
IILGP3
IIL
Input leakage current, RSTN pin
Input leakage current, GPIO3/IC3P pin
Input leakage current, all other digital inputs
Input capacitance
-85
-20
-10
Note 1
A
A
A
pF
pF
20
10
10
11
Note 1
Note 1
CIN
3
3
CIN
Input capacitance, SCL/SCLK, SDA/MOSI
0.05*
VDD33
Input hysteresis, SCL and SDA in I2C Bus Mode
Output leakage (when high impedance)
Output high voltage
mV
ILO
VOH
VOL
-10
2.4
10
Note 1
A
V
IO = -3.0mA
IO = 3.0mA
Output low voltage
0.4
V
Note 1:
Note 2:
0V < VIN < VDD33 for all other digital inputs.
VOH does not apply for SCL and SDA in I2C interface mode since they are open drain.
Table 8 - Electrical Characteristics: XA Clock Input
This table covers the case when there is no external crystal connected and an external oscillator or clock signal is connected to the XA pin.
Characteristics
Input high voltage, XA
Symbol
Min.
1.2
Typ.
Max.
Units
V
Notes
VIH
VIL
Input low voltage, XA
0.8
V
Input frequency on XA pin, master clock for NCO
mode, clock doubler disabled
fIN
80
40
80
130
MHz
MHz
MHz
MHz
Input frequency on XA pin, internally doubled to
make master clock for NCO mode
fIN
fIN
fIN
65
130
65
Input frequency on XA pin, master clock for
Spread Spectrum mode, clock doubler disabled
Input frequency on XA pin, internally doubled to
make master clock for Spread Spectrum mode
55
fIN
fIN
IIL
Input frequency, XA pin to APLL mux
Input frequency, XA pin to HSDIV2 bypass mux
Input leakage current
9.72
156.25
156.25
10
MHz
MHz
A
-10
40
Input duty cycle
60
%
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ZL30250, ZL30251
Data Sheet
Table 9 - Electrical Characteristics: Clock Inputs, ICxP/N
Characteristics
Input voltage tolerance (each pin, single-ended)
Input differential voltage
Symbol
VTOL
Min.
0
Typ.
Max.
VDD33
1.4
Units
Notes
Note 1
V
V
V
|VID|
VCMI
0.1
Note 2
Input DC bias voltage (internally biased)
1.3
9.72
9.72
1250
300
MHz
MHz
Differential
fIN
Input frequency, ICx pins
Single-ended
smaller of
3ns or 0.3 x 1
/ fIN
Minimum input clock high, low time,
tH, tL
tH, tL
ns
ns
Note 5
Note 6
fIN 250MHz
Minimum input clock high, low time,
fIN > 250MHz
0.4
RINVDD18
RINVSS
Input resistance, single-ended to VDD18, ICxP or ICxN
Input resistance, single-ended to VSS, ICxP or ICxN
50
80
k
k
Note 1:
The device can tolerate voltages as specified in VTOL w.r.t. VSS on its ICxP and ICxN pins without being damaged.
For differential input signals, proper operation of the input circuitry is only guaranteed when the other specifications in this table,
including |VID|, are met.
Note 2:
Note 3:
For inputs IC1P/N and IC2P/N VID=VICxP – VICxN. For input IC3P, VID=VIC3P – VCMI. The max VID spec only applies when a
differential signal is applied on ICxP/N; it does not apply when a single-ended signal is applied on ICxP.
Differential signals. The differential inputs can easily be interfaced to neighboring ICs driving LVDS, LVPECL, CML, HCSL,
HSTL or other differential signal formats using a few external passive components. In general, Microsemi recommends terminating
the signal with the termination/load recommended in the neighboring component’s data sheet and then AC-coupling the signal into
the ICxP/ICxN pins. See Figure 16 for details. To connect a differential signal to IC3, AC-couple one side of the signal to IC3P and
AC-couple the other side to VSS. For DC-coupling, treat the input as 1.8V CML.
Note 4:
Single-ended signals can be connected to ICxP pins. Signals with amplitude greater than 2.5V must be DC-coupled. For signals
with amplitudes less than 2.5V Microsemi recommends AC-coupling but DC-coupling can also be used. When a single-ended
signal is connected to ICxP, ICxN should be connected to a capacitor (0.1F or 0.01F) to VSS.
If MCR1.MCSEL1=1 then IC1 is the NCO/SS block’s master clock source and therefore the duty cycle spec in Table 8 applies to
IC1 rather than the tH, tL spec in this table.
Note 5:
Note 6:
The input high-speed divider must be used to divide the frequency by 2 or more.
VDD33
1/fIN
tH, tL
VICxP
VICxN
VSS
|VID|
VTOL
VCMI
Figure 15 - Electrical Characteristics: Clock Inputs
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Data Sheet
Example termination networks:
VDD_driver
LVDS
LVPECL
CML
HCSL
Microsemi
VDD_driver
VDD_driver
50
Driver-
specified
termination
network
+
R1
R1 50
50
Signal
Driver
DC
Receiver
bias
100
50
-
R2
R2
50
50
VDD_driver=3.3V: R1=127, R2=82
VDD_driver=2.5V: R1=250, R2=62.5
VDD_driver
Place the 100 termination resistor as close as possible
to the device pins.
Microsemi
50
50
Consult the signal driver’s data sheet for any required
DC network for this arrangement where the termination
resistor is on the receiver side of the AC coupling caps.
Driver-
specified
DC
+
Signal
Driver
DC
bias
100
Receiver
network
-
LVPECL drivers often need resistors (typically <200) to
ground in the DC network.
Figure 16 - Example External Components for Differential Input Signals
Table 10 - Electrical Characteristics: CML Clock Outputs
VODDx = 3.3V±5% for CML operation.
Characteristics
Output frequency
Symbol
fOCML
Min.
Typ.
Max.
1035
Units
MHz
Notes
Output frequency from medium-speed
divider
Output high voltage, single-ended, OCxP or
OCxN
fOCML,MSDIV
VOH,S
425
MHz
V
VDDOx
– 0.2
Output low voltage, single-ended, OCxP or
OCxN
VDDOx
– 0.6
Standard Swing
(OCxCR2.OCSF=1),
AC coupled to
VOL,S
V
VDDOx
– 0.4
VCM,S
Output common mode voltage
V
50 termination
|VOD,S
|
|VOD,S,PP
|
Output differential voltage
320
640
400
800
500
mV
Output differential voltage, peak-to-peak
1000
mVP-P
Output high voltage, single-ended, OCxP or
OCxN
Output low voltage, single-ended, OCxP or
OCxN
VDDOx
– 0.1
VOH,N
VOL,N
VCM,N
V
V
V
Narrow Swing
VDDOx
– 0.3
(half the power)
(OCxCR2.OCSF=2),
AC coupled to
VDDOx
– 0.2
Output common mode voltage
50 termination
|VOD,N
|
|VOD,N,PP
|
Output differential voltage
160
320
200
400
250
500
mV
Output differential voltage, peak-to-peak
mVP-P
Difference in Magnitude of Differential
Voltage for Complementary States
Output Rise/Fall Time
VDOS
tR, tF
50
mV
150
50
ps
%
%
20%-80%
Notes 2
Notes 3
Output Duty Cycle
Output Duty Cycle
45
40
55
60
Single Ended, to
VDDOx
ROUT
Output Impedance
Mismatch in a pair
50
ROUT
10
%
Note 1:
Note 2:
The differential CML outputs can easily be interfaced to LVDS, LVPECL, CML and other differential inputs on neighboring ICs
using a few external passive components. See Figure 18 for details.
For all HSDIV, MSDIV and LSDIV combinations other than those specified in Note 3.
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ZL30250, ZL30251
Data Sheet
Note 3:
For the case when APLLCR1.HSDIV specifies a half divide and OCxCR1.MSDIV=0 and OCxDIV=0.
1/fOCML
VOCxP
VOH
VCM
VOL
|VOD
|
VOCxN
VOCxP - VOCxN
0
|VOD,PP
|
Figure 17 - Electrical Characteristics: CML Clock Outputs
Microsemi
LVDS
VDDOx (3.3V)
Receiver
50
3.3V
+
internal bias
assumed
CML Tx
Microsemi
100
50
82
82
-
VDDOx (3.3V)
LVPECL
Receiver
integrated in some receivers
50
50
+
CML Tx
-
MIcrosemi
CML
VDDOx (3.3V)
Receiver
50
50
+
130
130
internal bias and
termination
assumed
CML Tx
-
can be AC or
DC coupled
Figure 18 – Example External Components for CML Output Signals
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Data Sheet
Table 11 - Electrical Characteristics: CMOS and HSTL (Class I) Clock Outputs
Characteristics
Output frequency
Symbol
fOCMOS
Min.
<<1Hz
Typ.
Max.
250
Units
MHz
Notes
Note 1
VDDOx
–0.4
VOH
VOL
VDDOx
0.4
Output high voltage
V
V
Notes 3, 4
Notes 3, 4
2pF load
Output low voltage
Output rise/fall time, VCCOx=1.8V,
OCxCR2.DRIVE=4x
Output rise/fall time, VCCOx=1.8V,
OCxCR2.DRIVE=4x
Output rise/fall time, VCCOx=3.3V,
OCxCR2.DRIVE=1x
0
0.4
1.2
0.7
2.2
ns
ns
ns
ns
15pF load
2pF load
15pF load
tR, tF
Output rise/fall time, VCCOx=3.3V,
OCxCR2.DRIVE=1x
Output duty cycle
45
42
50
50
50
46
10
55
58
%
%
Note 5
Output duty cycle
Notes 6, 7
Note 6
Output duty cycle, OCxNEG single-ended
Output duty cycle, OCxPOS single-ended
Output current when output disabled
%
%
Note 6
OCxCR2.OCSF=0
A
Note 1:
Note 2:
Minimum output frequency is a function of VCO frequency and output divider values and is guaranteed by design.
Measured with a series resistor of 33 and a 5pF load capacitance unless otherwise specified.
Note 3:
For HSTL Class I, VOH and VOL apply for both unterminated loads and for symmetrically terminated loads, i.e. 50 to
VDDOx/2.
Note 4:
Note 5:
Note 6:
Note 7:
For VDDOx=3.3V and OCxCR2.DRIVE=1x, IO=4mA. For VDDOx=1.5V and OCxCR2.DRIVE=4x, IO=8mA.
Output clock frequency ≤ 160MHz or VDDOx ≥ 1.8V.
Output clock frequency > 160MHz and VDDOx < 1.8V.
Measured differentially.
Interfacing to HCSL Components
Outputs in HSTL mode with VDDOx=1.5V or VDDOx=1.8V can provide an HCSL signal (VOH typ. 0.75V) to a
neighboring component when configured as shown in Figure 19 below. For VDDOx=1.5V the value of RS should be
set to 30 and OCxCR2.DRIVE should be set to 4x. For VDDOx=1.8V the value of RS should be set to 20 and
OCxCR2.DRIVE should be set to 2x.
Microsemi
Device with
HCSL Input
1.5V
VDDOx
POS
HSTL Mode
NEG
RS
RS
50
50
POS
NEG
Figure 19 – Example External Components for HCSL Output Signals
Table 12 - Electrical Characteristics: APLL Frequencies
Characteristics
APLL VCO frequency range
APLL PFD input frequency
Symbol
Min.
3715
9.72
Typ.
Max.
4180
Units
MHz
Notes
fVCO
tPFD
156.25
MHz
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ZL30250, ZL30251
Data Sheet
Table 13 - Electrical Characteristics: Jitter Specifications
Characteristics Min.
Output Phase Jitter, 622.08MHz
Typ.
0.16
0.06
8
Max.
0.225
Units
ps RMS
ps RMS
ps pk-pk
ps pk-pk
ps pk
Notes
Notes 1, 2
Output Phase Jitter, 625MHz, (1.875MHz-20MHz)
Output Period Jitter
Note 4
N=10000, Note 5
N=10000, Note 5
N=10000, Note 5
Note 3
Output Half-Period Jitter
14
Output Cycle-to-Cycle Jitter
7.5
Jitter Transfer Bandwidth
600
0.18
kHz
Bypass Path Additive Jitter, 100MHz in/out
ps RMS
12kHz-20MHz
Note 1:
Note 2:
Jitter calculated from integrated phase noise from 12kHz to 20MHz.
Tested with 155.52MHz XO (Vectron VCC1) connected to IC1, APLL VCO frequency 3732.48MHz, HSDIV1=6, OC1 frequency
622.08MHz.
Note 3:
Note 4:
Note 5:
APLL bandwidth and damping factor can be field configured over a limited range. Contact the factory for details.
With 50MHz crystal doubled as APLL input. Jitter calculated from integrated phase noise from 1.875MHz to 20MHz.
Outputs from a half-divide (e.g. 4.5) in the high-speed divider followed by only an odd divide in the medium-speed divider can have
higher jitter values. Example: 100MHz from VCO=3750MHz, HSDIV1=7.5, MSDIV=5 has typical period jitter of 16ps, typical cycle-
to-cycle jitter of 15ps and typical half-period jitter of 58ps.
Table 14 - Electrical Characteristics: Typical Output Jitter Performance
Output Jitter, ps RMS
Output Jitter, ps RMS
Output Frequency
625MHz
125MHz XO Reference1
50MHz Crystal Reference2
0.155
0.18
0.19
0.26
0.25
0.27
0.26
0.275
0.25
0.28
0.185
0.21
0.21
0.28
0.27
0.315
0.29
0.30
0.28
0.32
156.25MHz
125MHz
25MHz CMOS
622.08MHz
155.52MHz
622.08MHz * 255/237
155.52MHz * 255/237
614.4MHz
153.6MHz
Note 1:
Note 2:
Note 3:
APLL locked to external 125MHz XO (Vectron VCC1-1535-125M000).
APLL locked to external 50MHz crystal (TXC 7M50070021), internal doubler enabled when multiplication is fractional.
All signals are differential unless otherwise stated. Jitter is integrated 12kHz to 5MHz for 25MHz output
frequency and 12kHz to 20MHz for all other output frequencies.
Table 15 - Electrical Characteristics: Typical Input-to-Output Clock Delay
Mode
Delay, Input Clock Edge to Output Clock Edge
Non-deterministic but constant as long as the APLL remains locked and output
clock phases are not adjusted as described in section 5.7.4.1.
All Modes
Table 16 - Electrical Characteristics: Typical Output-to-Output Clock Delay
Mode
Delay, Output Clock Edge to Output Clock Edge
<100ps
All Modes
Requires phase adjustment and phase alignment capability described in section
5.7.4.
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Data Sheet
Table 17 - Electrical Characteristics: SPI Slave Interface Timing, Device Registers
Characteristics (Notes 1 to 3)
SCLK frequency
Symbol
Min.
Typ.
Max.
Units
MHz
ns
Notes
fBUS
10
tCYC
tSUC
tHDC
tCSH
tCLKH
tCLKL
tSUI
SCLK cycle time
100
50
50
50
40
40
10
10
0
CSN setup to first SCLK edge
CSN hold time after last SCLK edge
CSN high time
ns
ns
ns
SCLK high time
ns
SCLK low time
ns
MOSI data setup time
ns
tHDI
MOSI data hold time
ns
tEN
MISO enable time from SCLK edge
MISO disable time from CSN high
MISO data valid time
ns
tDIS
80
40
ns
tDV
ns
tHDO
MISO data hold time from SCLK edge
CSN, MOSI input rise time, fall time
0
ns
tR
,
t
F
10
ns
Note 1:
Note 2:
Note 3:
All timing is specified with 100pF load on all SPI pins.
All parameters in this table are guaranteed by design or characterization.
See timing diagram in Figure 20.
CSN
tSUC
tCYC
tHDC
tCSH
tCLKL
SCLK
tCLKH
tSUI tHDI
MOSI
MISO
tDV
tDIS
tEN
tHDO
Figure 20 - SPI Slave Interface Timing
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Table 18 - Electrical Characteristics: SPI Slave Interface Timing, Internal EEPROM (ZL30251 Only)
Characteristics (Notes 1 to 4)
SCLK frequency
Symbol
Min.
Typ.
Max.
Units
MHz
ns
Notes
fBUS
10
tCYC
tSUC
tHDC
tCSH
tCLKH
tCLKL
tSUI
SCLK cycle time
100
50
51
51
41
41
11
11
0
CSN setup to first SCLK edge
CSN hold time after last SCLK edge
CSN high time
ns
ns
ns
SCLK high time
ns
SCLK low time
ns
MOSI data setup time
ns
tHDI
MOSI data hold time
ns
tEN
MISO enable time from SCLK edge
MISO disable time from CSN high
MISO data valid time
ns
tDIS
90
60
ns
tDV
ns
tHDO
MISO data hold time from SCLK edge
CSN, MOSI input rise time, fall time
0
ns
tR
,
t
F
10
ns
Note 1:
Note 2:
Note 3:
Note 4:
This timing applies (a) when EESEL=1 and (b) in direct EEPROM write mode (see section 5.12.2).
All timing is specified with 100pF load on all SPI pins.
All parameters in this table are guaranteed by design or characterization.
See timing diagram in Figure 20.
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Table 19 - Electrical Characteristics: SPI Master Interface Timing (ZL30250 Only)
Characteristics (Notes 1 to 3)
SCLK output frequency
Symbol
Min.
Typ.
Max.
Units
MHz
ns
Notes
fBUS
5
tCYC
tCLKH/ tCYC
tSUC
SCLK output cycle time
200
45
SCLK output duty cycle
50
55
%
CSN output setup to first SCLK rising edge
CSN output hold after last SCLK falling edge
CSN output high time
200
200
200
15
ns
tHDC
ns
tCSH
ns
MISO input setup time to SCLK rising edge
MISO input hold time from SCLK rising edge
MOSI output valid from SCLK falling edge
SCLK, CSN, MOSI output rise time, fall time
MISO input rise time, fall time
tSU
ns
tHD
5
ns
tDV
10
15
10
ns
tR
t
t
ns
,
,
F
F
tR
ns
Note 1:
Note 2:
Note 3:
All timing is specified with 100pF load on all SPI pins.
All parameters in this table are guaranteed by design or characterization.
See timing diagram in Figure 21.
CSN
tSUC
tCYC
tHDC
tCSH
tCLKL
SCLK
tCLKH
tDV
MOSI
MISO
tSU tHD
Figure 21 - SPI Master Interface Timing
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Data Sheet
Table 20 - Electrical Characteristics: I2C Slave Interface Timing
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
fSCL
SCL clock frequency
400
kHz
tHD:STA
tLOW
Hold time, START condition
Low time, SCL
0.6
1.3
0.6
0.6
0
µs
µs
µs
µs
µs
ns
ns
tHIGH
High time, SCL
tSU:STA
tHD:DAT
tSU:DAT
tR
Setup time, START condition
Data hold time
Notes 2 and 3
Note 4
0.9
Data setup time
100
Rise time
20 +
0.1Cb
Cb is cap. of
one bus line
tF
Fall time
300
ns
tSU:STO
tBUF
Setup time, STOP condition
0.6
1.3
µs
µs
Bus free time between STOP/START
Pulse width of spikes which must be
suppressed by the input filter
tSP
0
50
ns
Note 1:
The timing parameters in this table are specifically for 400kbps Fast Mode. Fast Mode devices are downward-compatible with
100kbps Standard Mode I2C bus timing. All parameters in this table are guaranteed by design or characterization. All values
referred to VIHmin and VILmax levels (see Table 7).
Note 2:
The device internally provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL. Other devices must provide this hold time as well per the I2C
specification.
Note 3:
Note 4:
The I2C specification indicates that the maximum tHD:DAT spec only has to be met if the device does not stretch the low period
(tLOW) of the SCL signal. The device does not stretch the low period of the SCL signal.
Determined by choice of pull-up resistor.
tSU:DAT
tHD:STA
tBUF
SDA
SCL
tF
tR
tLOW
tF
tSP
tHD:STA
tHIGH
tSU:STA
tSU:STO
tHD:DAT
S
Sr
P
S
Figure 22 - I2C Slave Interface Timing
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Data Sheet
8. Package and Thermal Information
8.1 Package Top Mark Format
Z L 3 0 2 5 0
Z L 3 0 2 5 1
e3
e3
F
R
F
R
Y Y W W A Z Z
Y Y W W A Z Z
Pin 1 corner
Pin 1 corner
Figure 23 - Non-customized Device Top Mark
Z L 3 0 2 5 1
e3
F
R
Y Y W W A Z Z
C C I D W P
Pin 1 corner
Figure 24 - Custom Factory Programmed Device Top Mark
Table 21 – Package Top Mark Legend
Line
Characters
Description
1
ZL30250 or
Part Number
ZL30251
2
2
2
3
3
3
3
4
4
F
R
e3
YY
WW
A
ZZ
CCID
WP
Fab Code
Product Revision Code
Denotes Pb-Free Package
Last Two Digits of the Year of Encapsulation
Work Week of Assembly
Assembly Location Code
Assembly Lot Sequence
Custom Programming Identification Code
Work Week of Programming
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ZL30250, ZL30251
Data Sheet
8.2 Thermal Specifications
Table 22 - 5x5mm QFN Package Thermal Properties
PARAMETER
Maximum Ambient Temperature
Maximum Junction Temperature
SYMBOL
TA
TJMAX
CONDITIONS
VALUE
85
125
UNITS
C
C
still air
1m/s airflow
2.5m/s airflow
29.6
23.3
20.6
9.8
Junction to Ambient Thermal Resistance
(Note 1)
JA
C/W
Junction to Board Thermal Resistance
Junction to Case Thermal Resistance
Junction to Pad Thermal Resistance
(Note 2)
Junction to Top-Center Thermal
Characterization Parameter
JB
JC
C/W
C/W
17.5
Still air
Still air
3.4
0.2
JP
C/W
JT
C/W
Note 1:
Theta-JA (JA) is the thermal resistance from junction to ambient when the package is mounted on an 4-layer JEDEC standard
test board and dissipating maximum power.
Note 2:
Note 3:
Theta-JP (JP) is the thermal resistance from junction to the center exposed pad on the bottom of the package.
For all numbers in the table, the exposed pad is connected to the ground plane with a 5x5 array of thermal vias; via diameter
0.33mm; via pitch 0.76mm.
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Data Sheet
9. Mechanical Drawing
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ZL30250, ZL30251
Data Sheet
10. Acronyms and Abbreviations
APLL
CML
GbE
analog phase locked loop
current mode logic
gigabit Ethernet
HCSL
HSTL
I/O
high-speed current steering logic
high-speed transceiver logic
input/output
LVDS
LVPECL
PFD
low-voltage differential signal
low-voltage positive emitter-coupled logic
phase/frequency detector
phase locked loop
PLL
ppb
parts per billion
ppm
parts per million
pk-pk
RMS
RO
peak-to-peak
root-mean-square
read-only
R/W
read/write
SS or SSM
TCXO
UI
spread spectrum modulation
temperature-compensated crystal oscillator
unit interval
UIPP or UIP-P
XO
unit interval, peak to peak
crystal oscillator
11. Data Sheet Revision History
Revision
Description
23-Jun-2014 First general release
In Table 6 added IDD18ODIV spec., added typical power spec for DPLL+APLL with one input and
one output enabled and corrected the IDD numbers to match device characterization.
07-Jul-2014 In Table 8 changed XA VIH min from 1.65V to 1.2V.
In Table 13 added phase jitter for 625MHz measured 1.875-20MHz, period jitter and cycle-to-
cycle jitter plus Note 4.
Changed title to Any-to-Any.
In Table 1, in ICx row changed the note about IC3 to delete the recommendation to AC-couple
the NEG trace to VSS.
07-Aug-2014
Above Figure 19 specified RS should be set to 30 and OCxCR2.DRIVE should be set to 4x.
Corrected references to section 0.
Edited section 5.4 to match the Table 1 edit done 07-Aug-2014.
In Table 13, reduced typical period jitter to 8ps and typical cycle-to-cycle jitter to 7.5ps. In both
29-Sep-2014
specs removed “100MHz” from the name and changed N=50000 to N=10000. Added half-period
jitter spec and footnote 5.
Added section 8.1 to document package top mark.
In section 5.2.1 changed the first three rows of the table to to have AC1=0, AC0=0 rather than
AC1=X, AC0=X to match the implementation.
In section 5.2 added two guidelines to ensure the device properly samples the reset values of
TEST, IF[1:0] and AC[1:0] pins.
31-Mar-2015
In section 5.10 change min reset assert time from 100ns to 100ms to ensure AC0/GPIO0,
AC1/GPIO1, TEST/GPIO2, IF0/CSN and IF1/MISO pads have enough time to set up their
“latched at reset” values. Also added that system software must wait for for
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Data Sheet
Revision
Description
GLOBISR.BCDONE=1 before configuring the device.
In Table 20 Note 1 clarified device compatibility with I2C 400kbps Fast Mode and 100kbps
Standard Mode.
In section 5.12.2 specified that MISO is driven continually during Direct EEPROM Write Mode.
Documented the 100 and 101 decodes of APLLCR3.APLLMUX.
Changed the VDDO1, VDDO2, VDDO3 descriptions in Table 1 to clearly indicate that VDDO1 is
for output OC1, VDDO2 is for output OC2, etc.
Deleted section 5.14.1, renamed and rewrote section 5.12.2 (which became new section 5.12.1)
and renamed section 5.12.
Modified Figure 18. In the LVDS diagram removed the 5k resistors to ground, which are only
appropriate for one type of LVDS receiver design. Added 100 differential termination and note
about how it may be integrated in some receivers. Added note that internal bias and termination
is assumed for the CML receiver diagram.
Edited the Interfacing to HCSL Components discussion on page 68 to include a
recommendation for HCSL when VDDOx=1.8V.
In Table 13 added bypass path additive jitter spec.
In section 5.5 deleted the last sentence: “An external crystal and the internal crystal driver circuit
cannot be used with the NCO/SS block.”
Changed product title on page 1 from 3-input to 4-input.
Added section 5.12.3, Holding Other Devices in Reset During Auto-Configuration.
In the ID2 descrption corrected the bit 0 default value to 1.
Corrected Figure 4 to have square corners rather than chamfered corners to match the
mechanical drawing in section 9.
Added Note 3 to Table 22.
In Table 9 changed tH, t
Note 6.
fIN > 250MHz from 0.4/ fIN typical to 0.4ns min and added
L specs for
28-Mar-2016
Edited section 5.10 to reduce RSTN assertion time for all but one specific situation.
Added a note to the MCR1.RST description to indicate the need to clear the MCSEL, MCSEL1
and ROSCD bits before setting the RST bit.
In section 5.8.3 in the Read Transactions paragraph added a note describing the case where
the I2C write is separated in time from the I2C read.
In section 5.7.2 second paragraph added maximum input frequency sentences for the medium-
speed and low-speed dividers.
In section 6 changed the end of the address range from 0x1FF to 0x6FF to include test
registers.
In the EESEL register description, added a note that the EESEL bit is write-only.
23-Jan-2018
In Table 1, in the SCL/SCLK and SDA/MOSI pin descriptions added notes indicating the need
for an external pullup resistor for I2C operation and referring the reader to the I2C specification
for details.
In OCxPH register description, indicated that positive values represent later in time.
In the APLLCR4 register description indicated that “increment” moves the signal later in time
and “decrement” moves the signal earlier in time.
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