SG1825CJ-883B [MICROSEMI]

Switching Controller, Current-mode, 0.2A, 1500kHz Switching Freq-Max, BIPolar, CDIP16, HERMETIC SEALED, CERAMIC, DIP-16;
SG1825CJ-883B
型号: SG1825CJ-883B
厂家: Microsemi    Microsemi
描述:

Switching Controller, Current-mode, 0.2A, 1500kHz Switching Freq-Max, BIPolar, CDIP16, HERMETIC SEALED, CERAMIC, DIP-16

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SG1825C  
High Speed Current Mode PWM  
Features  
Description  
Improved Reference Initial Tolerance (±1% max.)  
Improved Oscillator Initial Accuracy (±3% typ.)  
Improved Startup Current (500μA typ.)  
Propagation Delay to Outputs (50ns typ.)  
10V to 30V Operation  
The SG1825C is a high-performance pulse width  
modulator optimized for high frequency current-mode  
power supplies. Included in the controller are a  
precision voltage reference, micro power start-up  
circuitry, soft-start, high frequency oscillator, wideband  
error amplifier, fast current limit comparator, full double-  
pulse suppression logic, and dual totem pole output  
drivers. Innovative circuit design and an advanced  
linear Schottky process result in very short propagation  
delays through the current limit comparator, logic, and  
output drivers. This device can be used to implement  
either current mode or voltage mode switching power  
5.1V Reference Trimmed to ±1%  
2MHz Oscillator Capability  
1.5A Peak Totem-Pole Drivers  
U.V. Lockout with Hysteresis  
No Output Driver “FLOAT”  
Programmable Softstart  
supplies.  
It also is useful as a series-resonant  
Double-Pulse Suppression Logic  
Wideband Low-Impedance Error Amplifier  
Current-Mode or Voltage-Mode Control  
controller to frequencies beyond 1MHz. The SG1825C  
is specified for operation over the full military ambient  
temperature range of -55°C to 125°C.  
High Reliability Features  
.
.
Available To MIL-STD-883 883, ¶ 1.2.1  
Available to DSCC  
Standard Microcircuit Drawing (SMD)  
. SGR1825C Rad-Tolerant Version Available  
Product Highlight  
15  
Sample Size = 279  
Mean 401.661  
Std. Dev. = 3.8  
10  
5
0
415  
390  
395  
400  
405  
410  
Initial Oscillator Accuracy - kHz  
Figure 1 · Product Highlight  
November 2014 Rev. 1.4  
www.microsemi.com  
1
© 2014 Microsemi Corporation- Analog Mixed Signal Group  
High Speed Current Mode PWM  
Connection Diagrams and Ordering Information  
Ambient  
Temperature  
Type  
Packaging  
Type  
Package  
Part Number  
Connection Diagram  
INV. INPUT  
VREF  
SG1825CJ  
N.I.INPUT  
E/A OUTPUT  
CLOCK  
RT  
+VIN  
OUTPUT B  
VC  
16-PIN  
CERAMIC  
DUAL INLINE  
PACKAGE  
PWR GND  
OUTPUT A  
GROUND  
ILIM/S.D.  
-55°C to  
125°C  
SG1825CJ-883B  
SG1825CJ-DESC  
CT  
J
CERDIP  
RAMP  
SOFTSTART  
J Package  
(Top View)  
3
19  
1 20  
2
1. N.C.  
11.N.C.  
2. INV.INPUT  
18 3. N.I. INPUT  
12. ILIM / S.D.  
13. GND  
SG1825CL  
.
4
5
6
7
8
4. E/A OUTPUT 14.OUTPUT A  
17  
20-Pin  
CERAMIC  
Leadless Chip  
Carrier  
CLOCK  
5.  
15.PWR GND  
16 6. N.C.  
16.  
17. Vc  
N.C.  
7. RT  
15  
8.  
18. OUTPUT B  
CT  
-55°C to  
125°C  
14  
SG1825CL-883B  
9. RAMP  
19.  
+VIN  
VREF  
L
CLCC  
10. SOFTSTART 20.  
9
13  
10 11 12  
L PACKAGE  
(Top View)  
SG1825CL-DESC  
Notes:  
1. Contact factory for DESC part availability.  
2. All parts are viewed from the top.  
3. Hermetic Packages J, & L use Pb37/Sn63 hot solder lead finish, contact factory for availability of RoHS versions.  
2
Absolute Maximum Ratings1  
Absolute Maximum Ratings1  
Value  
Units  
Parameter  
Input Voltage (VIN and VC)  
Analog Inputs:  
30  
V
Error Amplifier and Ramp  
Softstart and ILIM/S.D.  
-0.3 to 7.0  
0.3 to 6.0  
V
V
V
V
Digital Input (Clock)  
1.5 to 6.0  
Driver Outputs  
-0.3 to VC+1.5  
Source / Sink Output Current (each output):  
Continuous  
0.5  
2.0  
20  
5
A
Pulse, 500ns  
A
Softstart Sink Current  
mA  
mA  
mA  
mA  
Clock Output Current  
Error Amplifier Output Current  
Oscillator Charging Current  
Operating Junction Temperature:  
Hermetic (J, L Package)  
Storage Temperature Range  
Lead Temperature (soldering, 10 seconds)  
Peak Package Solder Reflow Temp. (40 seconds max. exposure)  
5
5
150  
-65 to 150  
300  
°C  
°C  
°C  
°C  
260 (+0, -5)  
Notes: 1. Exceeding these ratings could cause damage to the device.  
Thermal Data  
Parameter  
Value  
Units  
J Package  
°C/W  
°C/W  
Thermal Resistance-Junction to Case, θJC  
Thermal Resistance-Junction to Ambient, θJA  
L Package  
30  
80  
°C/W  
°C/W  
Thermal Resistance-Junction to Case, θJC  
Thermal Resistance-Junction to Ambient, θJA  
35  
120  
Notes:  
Junction Temperature Calculation: TJ = TA + (PD x θJA).  
The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient  
airflow.  
3
High Speed Current Mode PWM  
Recommended Operating Conditions2  
Recommended Operating Conditions  
Symbol  
Parameter  
Units  
Min.  
10  
1.5  
0
Typ.  
Max.  
30  
VIN  
Supply Voltage Range  
V
V
V
V
Voltage Amp Common Mode Range  
Ramp Input Voltage Range  
Current Limit I Shutdown Voltage Range  
Source / Sink Output Current:  
Continuous  
5.5  
5.0  
4.0  
0
200  
1.0  
mA  
A
Pulse, 500ns  
Voltage Reference Output Current  
Oscillator Frequency Range  
Oscillator Charging Current  
Oscillator Timing Resistor  
Oscillator Timing Capacitor  
1
4
10  
1500  
3
mA  
kHz  
mA  
kΩ  
nF  
0.030  
1
100  
10  
RT  
CT  
0.470  
Operating Ambient Temperature Range:  
SG1825C  
-55  
125  
°C  
TA  
Notes: 2. Range over which the device is functional.  
4
Electrical Characteristics  
Electrical Characteristics  
Unless otherwise specified, these specifications apply over the full operating ambient temperatures of -55°C  
TA 125°C and VIN = VC = 15V. Low duty cycle pulse testing techniques are used which maintains  
junction and case temperatures equal to the ambient.  
Symbol  
Min.  
Typ.  
Max  
Parameter  
Test Conditions  
Units  
Reference Section  
Output Voltage  
TJ = 25°C, IL = 1mA  
5.05  
5.10  
2
5.15  
15  
V
mV  
Line Regulation  
VIN = 10V to 30V  
5
15  
Load Regulation  
IL = 1mA to 10mA  
mV  
Temperature Stability3  
Total Output Range3  
Output Noise Voltage3  
Over Operating Temperature  
Over Line, Load, and Temperature  
0.2  
0.4  
5.20  
mV/°C  
V
5.00  
f = 10Hz to 10kHz,  
IL = 0mA  
50  
200  
µVRMS  
Long Term Stability3 and 4  
Short Circuit Current  
TJ = 125 °C, t = 1000 hrs  
VREF = 0V  
5
25  
mV  
mA  
-15  
-50  
-100  
Oscillator Section5  
Initial Accuracy  
TJ = 25°C, CCLK 10pF  
370  
400  
0.2  
430  
2
kHz  
%
Voltage Stability  
VIN = 10V to 30V  
Temperature Stability3  
Over Rated Operating  
Temperature  
5
8
%
Total Frequency Limits3  
Minimum Frequency  
Maximum Frequency  
Clock High Level  
Over Line and Temperature  
RT = 100k, CT = 0.01µF  
RT = 1k, CT = 470pF  
ICLK = -1mA  
350  
450  
4
kHz  
kHz  
MHz  
V
1.5  
3.9  
4.5  
2.3  
2.8  
1.0  
1.8  
Clock Low Level  
ICLK = -1mA  
2.9  
3.0  
V
Ramp Peak Voltage  
Ramp Valley Voltage  
Valley-to-Peak Amplitude  
2.6  
0.7  
1.6  
V
1.25  
2.0  
V
V
Error Amp Section6  
15  
3
Input Offset Voltage  
Input Bias Current  
RS 2k, VERROR = 2.5V  
VERROR = 2.5V  
mV  
µA  
µA  
dB  
0.6  
0.1  
95  
Input Offset Current  
DC Open Loop Gain  
Common Mode Rejection  
VERROR = 2.5V  
1
VERROR = 1V to 4V  
60  
75  
AVOL  
Over Rated Voltage Range,  
VERROR = 2.5V  
95  
dB  
dB  
Power Supply Rejection  
VIN = 10V to 30V,  
VERROR = 2.5V  
85  
110  
1
-0.5  
4.0  
0
2.5  
-1.3  
4.7  
0.5  
5.5  
Output Sink Current  
Output Source Current  
Output High Voltage  
Output Low Voltage  
Unity Gain Bandwidth3  
Slew Rate3  
VERROR = 1V  
VERROR = 4V  
IERROR = -0.5mA  
IERROR = 1mA  
AVOL = 0dB  
mA  
mA  
V
5.0  
1.0  
V
3
MHz  
6
V/µsec  
5
High Speed Current Mode PWM  
Symbol  
Parameter  
Test Conditions  
Units  
Min.  
Typ.  
Max  
PWM Comparator Section 5 and 7  
Ramp Input Bias Current  
-5  
-1  
µA  
%
%
V
Minimum Duty Cycle  
VERROR = 1V  
0
Maximum Duty Cycle8  
Zero Duty Cycle Threshold  
Delay to Driver Output3  
VERROR = 4V  
85  
1.1  
1.25  
50  
VRAMP = 0V to 2V,  
VERROR = 2V  
80  
20  
ns  
Softstart Section  
CSS Charge Current  
VSOFTSTART = 0.5V  
VSOFTSTART = 1.0V  
3
1
9
µA  
CSS Discharge Current  
mA  
Current Limit / Shutdown Section9  
ILIM Input Bias Current  
-15  
0.9  
15  
1.1  
1.55  
80  
µA  
V
Current Limit Threshold  
Shutdown Threshold  
Delay to Driver Output3  
1.0  
1.40  
50  
1.25  
V
VSHUTDOWN = 0V to 1.2V  
ns  
Output Drivers Section (each output)  
Output Low Level  
ISINK = 20mA  
ISINK = 200mA  
ISOURCE = 20mA  
ISOURCE = 200mA  
VC = 30V  
0.25  
1.2  
0.40  
2.0  
V
V
Output High Level  
13.0  
12.0  
13.5  
13.0  
150  
30  
V
V
VC Standby Current  
500  
60  
µA  
ns  
Output Rise / Fall Time3  
CL = 1000pF  
Undervoltage Lockout Section  
Start Threshold Voltage  
UV Lockout Hysteresis  
Supply Current Section5  
Start Up Current  
8.8  
0.4  
9.2  
0.8  
9.7  
1.2  
V
V
VIN = 8V  
0.5  
22  
1.2  
33  
mA  
mA  
VINV, VRAMP, V(ILIM/S.D.) = 0V,  
VN.I. = 1V  
Operating Current  
Notes:  
3. This parameter is guaranteed by design and process control, but is not 100% tested in production.  
4.  
This parameter is non-accumulative, and represents the random fluctuation of the reference voltage within some error  
band when observed over any 1000 hour period of time.  
5. FOSC = 400kHz (RT = 3.65k, CT = 1.0nF).  
6. VCM = 1.5V to 5.5V.  
7. VRAMP = 0V, unless otherwise specified.  
8. 100% duty cycle is defined as a pulse width equal to one oscillator period.  
9. V(ILIM/S.D.) = 0V to 4.0V, unless otherwise specified.  
6
 
 
 
 
 
Block Diagram  
Block Diagram  
VREF  
16  
13 VC  
+9V  
11  
OUTPUT A  
REFERENCE  
REGULATOR  
15  
+VIN  
10  
Q
Q
GND  
+ 4.0V  
T
4
CLOCK  
14  
12  
OUTPUT B  
5
RT  
OSCILLATOR  
S
6
CT  
D
POWER GND  
R
Q
1.25 V  
7
3
2
1
RAMP  
E/A OUTPUT  
N.I. INPUT  
ERROR  
+ 1.0 V  
INV. INPUT  
9 µA  
8
SOFTSTART  
9
ILIM/S.D.  
+ 1.4 V  
7
High Speed Current Mode PWM  
Application Information  
High Speed Layout and Bypassing  
The SG1825C, like all high-speed circuits, requires extra attention to external conductor and component  
layout to minimize undesired inductive and capacitive effects. All lead lengths must be as short as possible.  
The best printed circuit board choice would be a four-layer design, with the two internal planes supplying  
power and ground. Signal interconnects should be placed on the outside, giving a conductor-over-ground-  
plane (microstrip) configuration. A two-sided printed circuit board with one side dedicated as a ground plane  
is next best, and requires careful component placement by a skilled pc designer. Two supply bypass  
capacitors should be employed: a low-inductance 0.1µF ceramic within 0.25 inches of the +VIN pin for high  
frequencies, and a 1 µF to 5µF solid tantalum within 0.5 inches of the VC pin to provide an energy reservoir  
for the high-peak output currents. A low-inductance .01µF bypass for the reference output is also  
recommended.  
16  
VREF  
VREF  
SG1825C  
13  
12  
VC  
PWR GND  
GND  
0.01µF  
10  
15  
+VIN  
0.1µF  
1µF  
+VIN  
Figure 4 · High Speed Layout and Bypassing  
8
Application Information  
Micropower Startup  
Since the SG1825C typically draws 700µA of supply current before turning on, a low power bleeder resistor  
from the rectified AC line supply is all that is required for startup. A start capacitor, CS, is charged with the  
excess current from the bleeder resistor. When the turn-on threshold voltage is reached, the PWM circuit  
becomes active, energizing the power transistors. The additional operating current required by the PWM is  
then provided by a bootstrap winding on the main high-frequency power transformer.  
TO POWER TRANSFORMER  
SG1825C  
13  
VC  
L1  
POWER  
12  
GND  
GND  
RB  
10  
GND  
L2  
15  
+VIN  
1µF  
0.1µF  
CS  
+ VIN  
Figure 5 · Micropower Startup  
Softstart Circuit / Output Duty Cycle Limit  
The softstart pin of the SG1825C is held low when either the chip is in micropower mode, or when a voltage  
greater than +1.4 volts is present at the ILIM/S.D. pin. The maximum positive swing of the voltage error  
amplifier is clamped to the Softstart pin voltage, providing a ramp-up of peak charging currents in the power  
semiconductors at turn-on. In some cases, the duration of the Shutdown signal can be too short to fully  
discharge the softstart capacitor. The illustrated resistor/discrete PNP transistor configuration can be used  
to shorten the discharge time by a factor of 50 or more. When the internal discharge transistor in the  
SG1825C turns on, current will flow through surge limit resistor R1. As the resistor drop approaches 0.6  
volts, the external PNP turns on, providing a low resistance discharge path for the energy in the softstart  
capacitor. The capacitor will be rapidly discharged to +0.7 volts, which corresponds to zero duty cycle in the  
pulse width modulator.  
SG1825C  
R1  
100  
8
CSS  
13  
VC  
12  
PWR GND  
+
CSOFTSTART  
10  
GND  
15  
+VIN  
0.1µF  
1µF  
+
+VIN  
Figure 6 · Softstart Fast Reset  
9
High Speed Current Mode PWM  
Frequency Synchronization  
Two or three SG1825C oscillators may be locked together with the interconnection scheme shown, if the  
devices are within an inch or so of each other. A master unit is programmed for desired frequency with RT  
and CT as usual. The oscillators in the slave units are disabled by grounding CT and by connecting RT to  
VREF. The logic in the slave units is locked to the clock of the master with the wire-OR connection shown.  
Many SG1825Cs can be locked to a master system clock by wiring the oscillators as slave units, and  
distributing the master clock to each using a tree-fan-out geometry.  
MASTER  
SLAVE  
4
4
16  
CLK  
CLK  
VREF  
SG1825C  
SG1825C  
5
5
6
RT  
CT  
RT  
6
CT  
12  
12  
10  
PWR GND  
GND  
PWR GND  
GND  
RT  
10  
15  
15  
CT  
+VIN  
+VIN  
0.1µF  
0.1µF  
+VIN  
Figure 7 · Oscillator Synchronization  
Oscillator  
The oscillator frequency is programmed by external timing components RT and CT. A nominal +3.0 volts appears at  
the RT pin. The current flowing through RT is mirrored internally with a 1:1 ratio. This causes an identical current to  
flow out the CT pin, charging the timing capacitor and generating a linear ramp. When the upper threshold of +2.8  
volts is reached, a discharge network reduces the ramp voltage to +1.0, where a new charge cycle begins.  
The Clock output pin is LOW (+2.3 volts) during the charge cycle, and HIGH (+4.5 volts) during the discharge cycle.  
The Clock pin is driven by an NPN emitter follower, and so can be wire-ORed. Each Clock pin can drive a 1 mA load.  
Since the internal current-source pull-down is approximately 400µA, the DC fan-out to other SG1825C Clock pins is  
at least two.  
The type of capacitor selected for CT is very important. At high frequencies, non-ideal characteristics such as  
effective series resistance (ESR), effective series inductance (ESL), dielectric loss and dielectric absorption all affect  
frequency accuracy and stability. RF capacitors such as silver mica, glass, polystyrene, or COG ceramics are  
recommended. Avoid high-K ceramics, which work best in DC bypass applications.  
10  
Application Information  
SG1825C  
3 V  
IR  
RT  
5
6
+ 5.1 V  
IC = IR  
CT  
+ 4.5 V  
+ 2.3 V  
CLOCK  
4
400µA  
2.8 V  
1.0V  
Figure 8 · Oscillator Functional Diagram  
11  
High Speed Current Mode PWM  
Error Amplifier  
The voltage error amplifier is a true operational amplifier with low impedance output, and can be gain-  
stabilized using conventional feedback techniques. The typical DC open-loop gain is 95dB, with a single low  
frequency pole at 100Hz. The input connections to the error amplifier are determined by the polarity of the  
power supply output voltage. For positive supplies, the common-mode voltage is +5.1 volts and the  
feedback connections in Figure A are used. With negative outputs, the common-mode voltage is half the  
reference, and the feedback divider is connected between the negative output and the +5.1 volt reference as  
shown in Figure B.  
R1  
VREF  
2
R4  
NEGATIVE  
VERROR  
3
OUTPUT  
R2  
VOLTAGE  
1
R1  
2
1
VREF  
R3  
3
VERROR  
R2  
CP  
RZ  
R4  
R3  
POSITIVE  
OUTPUT  
VOLTAGE  
VREF  
2
RZ  
CP  
FIGURE A  
FIGURE B  
Figure 9 · Voltage Amplifier Connections  
Output Driver  
The output drivers are designed to provide up to 1.5 Amps peak output current. To minimize ringing on the  
output waveform, which can be destructive to both the power MOSFET and the PWM chip, the series  
inductance seen by the drivers should be as low as possible. One solution is to keep the distance between  
the PWM and MOSFET gate as short as possible, and to use carbon composition series damping resistors.  
A Faraday shield to intercept radiated EMI from the power transistors is usually required with its choice.  
A second approach is to place the MOSFETs some distance from the PWM chip, and use a series-  
terminated transmission line to preserve drive pulse fidelity. This will minimize noise radiated back to the  
sensitive analog circuitry of the SG1825C. A Faraday shield may also be required. If the drivers are  
connected to an isolation transformer, or if kickback through CGD of the MOSFET is severe, clamp diodes  
may be required. 1 Amp peak Schottky diodes will limit undershoot to less than -0.3 volts.  
FARADAY SHIELD  
13  
VC  
SG1825C  
50  
24Ω  
11  
*
50  
PWR GND  
12  
GND  
10  
* SCHOTTKY CLAMP MAY BE REQUIRED  
Figure 10 · Driving Shielded Cable  
12  
Package Outline Dimensions  
Package Outline Dimensions  
Controlling dimensions are in millimeters, inches are shown for general information.  
E3  
D
MILLIMETERS  
INCHES  
Dim  
MIN  
MAX  
9.14  
MIN  
MAX  
0.360  
0.320  
D/E  
E3  
e
8.64  
-
0.340  
-
8.128  
E
1.270 BSC  
0.635 TYP  
0.050 BSC  
0.025 TYP  
B1  
L
1.02  
1.52  
0.040  
0.060  
0.090  
A
1.626  
2.286  
0.064  
h
1.016 TYP  
0.040 TYP  
A
L2  
L
8
A1  
A1  
A2  
L2  
B3  
1.372  
-
1.68  
1.168  
2.41  
0.054  
-
0.066  
0.046  
0.95  
3
1
1.91  
0.075  
0.203R  
0.008R  
Note:  
1. All exposed metalized area shall be gold plated 60  
micro-inch minimum thickness over nickel plated unless  
otherwise specified in purchase order.  
13  
h
18  
A2  
B3  
e
B1  
Figure 11 · L 20-Pin Ceramic Leadless Chip Carrier (LCC) Package Outline Dimensions  
MILLIMETERS  
INCHES  
Dim  
MIN  
MAX  
5.08  
0.51  
1.65  
0.38  
19.94  
7.11  
MIN  
MAX  
0.200  
0.020  
0.065  
0.015  
0.785  
0.280  
A
b
0.38  
1.04  
0.20  
19.30  
5.59  
0.015  
0.045  
0.008  
0.760  
0.220  
D
b2  
c
9
8
16  
D
E
E
1
e
2.54 BSC  
0.100 BSC  
eA  
b2  
eA  
H
L
7.37  
0.63  
3.18  
-
7.87  
1.78  
5.08  
15°  
0.290  
0.025  
0.125  
-
0.310  
0.070  
0.200  
15°  
Q
A
Seating Plane  
L
α
θ
Q
0.51  
1.02  
0.020  
0.040  
H
b
e
Note:  
Dimensions do not include protrusions; these shall not  
exceed 0.155mm (.006”) on any side. Lead dimension  
shall not include solder coverage.  
Figure 12 · J 16-Pin Ceramic Dual Inline Package Dimensions  
13  
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor  
and system solutions for communications, defense & security, aerospace and industrial  
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SG1825C-1.4/11.14  

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