SG1825CJ/883B [MICROSEMI]

HIGH - SPEED CURRENT - MODE PWM; - 高速电流 - 模式PWM


型号：	SG1825CJ/883B
厂家：	Microsemi
描述：	HIGH - SPEED CURRENT - MODE PWM - 高速电流 - 模式PWM
文件：	总7页 (文件大小：186K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LIN DOC #: 1825

SG1825C/SG2825C/SG3825C

H I G H - S P E E D C U R R E N T - M O D E P W M

T H E I N F I N I T E P O W E R O F I N N O V A T I O N

N O T R E C O M M E N D E D F O R N E W D E S I G N S

DESCRIPTION

KEY FEATURES

■ IMPROVED REFERENCE INITIAL

TOLERANCE (±1% max.)

The SG1825C is a high-performance

pulse width modulator optimized for

high frequency current-mode power

supplies. Included in the controller

are a precision voltage reference,

micropower start-up circuitry, soft-

start, high-frequency oscillator,

wideband error amplifier, fast current-

limit comparator, full double-pulse

suppression logic, and dual totem-

pole output drivers. Innovative

circuit design and an advanced linear

Schottky process result in very short

propagation delays through the

current limit comparator, logic, and

output drivers. This device can be

used to implement either current-

mode or voltage-mode switching

power supplies. It also is useful as

a series-resonant controller to

frequencies beyond 1MHz. The

SG1825C is specified for operation

over the full military ambient tem-

perature range of -55°C to 125°C.

The SG2825C is characterized for the

industrial range of -25°C to 85°C,

and the SG3825C is selected for the

commercial range of 0°C to 70°C.

■ IMPROVED OSCILLATOR INITIAL

ACCURACY (±3% typ.)

■ IMPROVED STARTUP CURRENT

(500µA typ.)

■ PROP DELAY TO OUTPUTS (50ns typ.)

p 10V TO 30V OPERATION

p 5.1V REFERENCE TRIMMED TO ±1%

p 2MHZ OSCILLATOR CAPABILITY

p 1.5A PEAK TOTEM-POLE DRIVERS

p U.V. LOCKOUT WITH HYSTERESIS

p NO OUTPUT DRIVER "FLOAT"

p PROGRAMMABLE SOFTSTART

p DOUBLE-PULSE SUPPRESSION LOGIC

PRODUCT HIGHLIGHT

p WIDEBAND LOW-IMPEDANCE ERROR

AMPLIFIER

I N I T I A L O S C I L L A T O R A C C U R A C Y

p CURRENT-MODE OR VOLTAGE-MODE

CONTROL

p WIDE CHOICE OF HIGH-FREQUENCY

PACKAGES

Sample Size = 42579

Mean 4011.686817

Std. Dev. = 34.83

HIGH RELIABILITY FEATURES

■ AVAILABLE TO MIL-STD-883B

■ LINFINITY LEVEL "S" PROCESSING AVAIL.

390

395

400

405

410

415

Initial Oscillator Accuracy - KHz

PACKAGE ORDER INFORMATION

Plastic DIP

16-pin

Plastic Wide SOIC

16-pin

Plastic LCC

20-pin

Ceramic DIP

16-pin

Ceramic LCC

20-pin

T_J(°C)

0 to 70

-25 to 85

-55 to 125

MIL-STD-883

DESC

SG3825CN

SG2825CN

SG3825CDW

SG2825CDW

SG3825CQ

SG2825CQ

SG3825CJ

SG2825CJ

SG1825CJ

SG1825CL

SG1825CJ/883B

SG1825CJ/DESC

SG1825CL/883B

SG1825CL/DESC

Note: All surface-mount packages are available in Tape & Reel. Append the letter "T" to part number. (i.e. SG3825CDWT)

F O R F U R T H E R I N F O R M A T I O N C A L L ( 7 1 4 ) 8 9 8 - 8 1 2 1

Rev. 1.3 6/96

11861 WESTERN AVENUE, GARDEN GROVE, CA. 92841

P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7

SG1825C/SG2825C/SG3825C

H I G H - S P E E D C U R R E N T - M O D E P W M

N O T R E C O M M E N D E D F O R N E W D E S I G N S

ABSOLUTE MAXIMUM RATINGS (Note 1)

PACKAGE PIN OUTS

Input Voltage (V_INand V_C).......................................................................................... 30V

Analog Inputs:

INV. INPUT

N.I. INPUT

E/A OUTPUT

CLOCK

V_REF

+V_IN

OUTPUT B

V_C

PWR GND

OUTPUT A

GROUND

I_LIM/ S.D.

Error Amplifier and Ramp ........................................................................-0.3V to 7.0V

Softstart and I_LIM/S.D. ................................................................................-0.3V to 6.0V

Digital Input (Clock) ....................................................................................1.5V to 6.0V

Driver Outputs ........................................................................................-0.3V to V_C+1.5V

Source / Sink Output Current (each output):

R_T

C_T

RAMP

SOFTSTART

Continuous .............................................................................................................. 0.5A

Pulse, 500ns ............................................................................................................ 2.0A

Softstart Sink Current................................................................................................ 20mA

Clock Output Current................................................................................................. 5mA

Error Amplifier Output Current ................................................................................. 5mA

Oscillator Charging Current ....................................................................................... 5mA

Operating Junction Temperature:

Hermetic (J, L Package) ....................................................................................... 150°C

Plastic (DW, N, Q Packages) ............................................................................... 150°C

Storage Temperature Range......................................................................-65°C to 150°C

Lead Temperature (soldering, 10 seconds) ............................................................ 300°C

J & N PACKAGE

(Top View)

INV. INPUT

N.I. INPUT

E/A OUTPUT

CLOCK

+V_REF

+V_IN

OUTPUT B

V_C

PWR GND

OUTPUT A

GROUND

I_LIM/ S.D.

R_T

C_T

RAMP

SOFTSTART

DW PACKAGE

(Top View)

Note 1. Exceeding these ratings could cause damage to the device.

THERMAL DATA

20 19

N PACKAGE:

THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ_JA

DW PACKAGE:

65°C/W

95°C/W

80°C/W

THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ_JA

Q PACKAGE:

10 11 12 13

THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ_JA

J PACKAGE:

Q PACKAGE

(Top View)

THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ_JA

L PACKAGE:

1 20 19

THERMAL RESISTANCE-JUNCTION TO CASE, θ_JC

THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ_JA

35°C/W

120°C/W

Junction Temperature Calculation: T_J= T_A+ (P x θ_JA).

The θ_JAnumbers are guidelines for the thermal ^Dperformance of the device/pc-board

system. All of the above assume no ambient airflow.

10 11 12 13

L PACKAGE

(Top View)

1. N.C.

11. N.C.

2. INV. INPUT

3. N.I. INPUT

4. E/A OUTPUT

5. CLOCK

6. N.C.

12. I_LIM/ S.D.

13. GROUND

14. OUTPUT A

15. PWR GND

16. N.C.

7. R_T

17. V_C

8. C_T

9. RAMP

18. OUTPUT B

19. +V_IN

10. SOFTSTART

20. V_REF

Rev. 1.3 6/96

P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7

SG1825C/SG2825C/SG3825C

H I G H - S P E E D C U R R E N T - M O D E P W M

N O T R E C O M M E N D E D F O R N E W D E S I G N S

RECOMMENDED OPERATING CONDITIONS

(Note 2)

Recommended Operating Conditions

Parameter

Symbol

Units

Min.

Typ.

Max.

Supply Voltage Range

1.5

5.5

5.0

4.0

Voltage Amp Common Mode Range

Ramp Input Voltage Range

Current Limit / Shutdown Voltage Range

Source / Sink Output Current

Continuous

200

1.0

Pulse, 500ns

Voltage Reference Output Current

Oscillator Frequency Range

Oscillator Charging Current

Oscillator Timing Resistor

Oscillator Timing Capacitor

Operating Ambient Temperature Range:

SG1825C

1500

kHz

kΩ

0.030

0.470

R_T

C_T

100

T_A

-25

-55

°C

SG2825C

SG3825C

125

Note 2. Range over which the device is functional.

ELECTRICAL CHARACTERISTICS

(Note 3)

(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG3825C with 0°C ≤ T_A≤ 70°C, SG2825C with

-25°C ≤ T ≤ 85°C, SG1825C with -55°C ≤ T_A≤ 125°C, and V_IN=V_C=15V. Low duty cycle pulse testing techniques are used which maintains junction

and case ^Atemperatures equal to the ambient temperature.)

SG1825C/2825C

Min. Typ. Max. Min. Typ. Max.

SG3825C

Parameter

Symbol

Test Conditions

Units

Reference Section

Output Voltage

T_J= 25°C, I_L= 1mA

5.05 5.10 5.15 5.05 5.10 5.15

Line Regulation

V_IN= 10 to 30V

Load Regulation

I_L= 1 to 10mA

Temperature Stability (Note 3)

Total Output Range (Note 3)

Output Noise Voltage (Note 3)

Long Term Stability (Notes 3 &4)

Short Circuit Current

Over Operating Temperature

Over Line, Load, and Temperature

f = 10Hz to 10kHz, I_L= 0mA

T_J= 125°C, t = 1000hrs

V_REF= 0V

0.2 0.4

5.20 5.00

50 200

0.2 0.4

5.20

mV/°C

µV_RMS

5.00

-15 -50 -100 -15 -50 -100

Oscillator Section (Note 5)

370 400 430 370 400 430

kHz

Initial Accuracy

Voltage Stability

T_J= 25°C, C_CLK≤ 10pF

V_IN= 10 to 30V

0.2

Temperature Stability (Note 3)

Total Frequency Limits (Note 3)

Minimum Frequency

Maximum Frequency

Clock High Level

Over Rated Operating Temperature

Over Line and Temperature

R_T= 100KΩ, C_T= 0.01µF

R_T= 1KΩ, C_T= 470pF

I_CLK= -1mA

350

1.5

450 350

450

kHz

MHz

1.5

3.9 4.5

2.3 2.9

3.9 4.5

2.3 2.9

Clock Low Level

I_CLK= -1mA

2.6 2.8 3.0 2.6 2.8 3.0

0.7 1.0 1.25 0.7 1.0 1.25

1.6 1.8 2.0 1.6 1.8 2.0

Ramp Peak Voltage

Ramp Valley Voltage

Valley-to-Peak Amplitude

Note 3. This parameter is guaranteed by design and process control, but is not 100% tested in production.

Note 4. This parameter is non-accumulative, and represents the random fluctuation of the reference voltage within some error band when observed

over any 1000 hour period of time.

Rev. 1.3 6/96

P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7

SG1825C/SG2825C/SG3825C

H I G H - S P E E D C U R R E N T - M O D E P W M

N O T R E C O M M E N D E D F O R N E W D E S I G N S

ELECTRICAL CHARACTERISTICS (Cont'd.)

SG1825C/2825C

Min. Typ. Max. Min. Typ. Max.

SG3825C

Parameter

Symbol

Test Conditions

Units

Error Amplifier Section (Note 6)

Input Offset Voltage

Input Bias Current

R_S≤ 2KΩ, V_ERROR= 2.5V

V_ERROR= 2.5V

µA

0.6

0.1

0.6

0.1

Input Offset Current

DC Open Loop Gain

V_ERROR= 2.5V

V_ERROR= 1 to 4V

µA

A_VOL

Common Mode Rejection

Power Supply Rejection

Output Sink Current

Over Rated Voltage Range, V_ERROR= 2.5V

V_IN= 10V to 30V, V_ERROR= 2.5V

V_ERROR= 1V

85 110

2.5

-0.5 -1.3

4.0 4.7 5.0 4.0 4.7 5.0

85 110

2.5

-0.5 -1.3

Output Source Current

Output High Voltage

V_ERROR= 4V

I_ERROR= -0.5mA

0.5 1.0

5.5

0.5 1.0

5.5

Output Low Voltage

Unity Gain Bandwidth (Note 3)

Slew Rate (Note 3)

I_ERROR= 1mA

A_VOL= 0dB

MHz

V/µsec

PWM Comparator Section (Note 5 & 7)

Ramp Input Bias Current

Minimum Duty Cycle

-1

-5

-1

-5

µA

V_ERROR= 1V

V_ERROR= 4V

Maximum Duty Cycle (Note 8)

Zero Duty Cycle Threshold

1.1 1.25

Delay to Driver Output (Note 3)

V_RAMP= 0V to 2V, V_ERROR= 2V

Softstart Section

C_SSCharge Current

C_SSDischarge Current

µA

V_SOFTSTART= 0.5V

V_SOFTSTART= 1.0V

Current Limit / Shutdown Section (Note 9)

I_LIMInput Bias Current

Current Limit Threshold

±15

±10

µA

0.9 1.0 1.1 0.9 1.0 1.1

1.25 1.40 1.55 1.20 1.40 1.55

Shutdown Threshold

Delay to Driver Output (Note 3)

V_SHUTDOWN= 0V to 1.2V

Output Drivers Section (each output)

0.25 0.40

1.2 2.0

13.0 13.5

12.0 13.0

150 500

30 60

0.25 0.40

1.2 2.0

13.0 13.5

12.0 13.0

150 500

30 60

Output Low Level

I_SINK= 20mA

I_SINK= 200mA

I_SOURCE= 20mA

I_SOURCE= 200mA

V_C= 30V

Output High Level

µA

V_CStandby Current

Output Rise / Fall Time (Note 3)

Undervoltage Lockout Section

C_L= 1000pF

Start Threshold Voltage

UV Lockout Hysteresis

8.8 9.2 9.7 8.8 9.2 9.7

0.4 0.8 1.2 0.4 0.8 1.2

Supply Current Section (Note 5)

Start Up Current

Operating Current

V_IN= 8V

0.5 1.2

22 33

0.5 1.2

22 33

V_INV, V_RAMP, V(I_LIM/S.D.) = 0V, V_N.I.= 1V

Note 5. F_OSC= 400kHz (R_T= 3.65kΩ, C_T= 1.0nF).

Note 6. V_CM= 1.5V to 5.5V.

Note 7. V_RAMP= 0V, unless otherwise specified.

Note 8. 100% duty cycle is defined as a pulsewidth equal to one oscillator period.

Note 9. V(I_LIM/S.D.) = 0V to 4.0V, unless otherwise specified.

Rev. 1.3 6/96

P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7

SG1825C/SG2825C/SG3825C

H I G H - S P E E D C U R R E N T - M O D E P W M

N O T R E C O M M E N D E D F O R N E W D E S I G N S

BLOCK DIAGRAM

V_REF

V_C

+9V

OUTPUT A

REFERENCE

REGULATOR

+V_IN

GND

+ 4.0V

CLOCK

OUTPUT B

R_T

OSCILLATOR

C_T

POWER GND

1.25V

RAMP

E/A OUTPUT

N.I. INPUT

ERROR

INV. INPUT

+ 1.0V

+ 1.4V

9µA

SOFTSTART

I_LIM/S.D.

FIGURE INDEX

Application Circuits

FIGURE #

1. HIGH-SPEED LAYOUT AND BYPASSING

2. MICROPOWER STARTUP

3. SOFTSTART FAST RESET

4. OSCILLATOR SYCHRONIZATION

5. OSCILLATOR FUNCTIONAL DIAGRAM

6. VOLTAGE AMPLIFIER CONNECTIONS

7. DRIVING SHIELDED CABLE

Rev. 1.3 6/96

P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7

SG1825C/SG2825C/SG3825C

H I G H - S P E E D C U R R E N T - M O D E P W M

N O T R E C O M M E N D E D F O R N E W D E S I G N S

APPLICATION INFORMATION

HIGH-SPEED LAYOUT AND BYPASSING

APPLICATION FIGURES

FIGURE 1. HIGH-SPEED LAYOUT and BYPASSING

The SG1825C, like all high-speed circuits, requires extra attention to external

conductor and component layout to minimize undesired inductive and

capacitive effects. All lead lengths must be as short as possible. The best

printed circuit board choice would be a four-layer design, with the two

internal planes supplying power and ground. Signal interconnects should

be placed on the outside, giving a conductor-over-ground-plane

(microstrip) configuration. A two-sided printed circuit board with one side

dedicated as a ground plane is next best, and requires careful component

placement by a skilled pc designer.

V_REF

SG1825C

V_C

PWR GND

0.01µF

GND

+V_IN

0.1µF

1µF

+V_IN

Two supply bypass capacitors should be employed: a low-inductance

0.1µF ceramic within 0.25 inches of the +V_INpin for high frequencies, and

a 1 to 5µF solid tantalum within 0.5 inches of the V_Cpin to provide an energy

reservoir for the high-peak output currents. A low-inductance .01µF bypass

for the reference output is also recommended.

FIGURE 2. MICROPOWER STARTUP

TO POWER TRANSFORMER

MICROPOWER STARTUP

SG1825C

Since the SG1825C typically draws 700µA of supply current before turning

on, a low power bleeder resistor from the rectified AC line supply is all that

is required for startup. A start capacitor, C_S, is charged with the excess

current from the bleeder resistor. When the turn-on threshold voltage is

reached, the PWM circuit becomes active, energizing the power transistors.

The additional operating current required by the PWM is then provided by

a bootstrap winding on the main high-frequency power transformer.

V_C

GND

POWER

GND

R_B

GND

+V_IN

0.1µF

1µF

C_S

+ V_IN

SOFTSTART CIRCUIT / OUTPUT DUTY CYCLE LIMIT

FIGURE 3. SOFTSTART FAST RESET

The softstart pin of the SG1825C is held low when either the chip is in the

micropower mode, or when a voltage greater than +1.4 volts is present at

the I_LIM/S.D.pin. The maximum positive swing of the voltage error amplifier

is clamped to the Softstart pin voltage, providing a ramp-up of peak charging

currents in the power semiconductors at turn-on.

In some cases, the duration of the Shutdown signal can be too short to

fully discharge the softstart capacitor. The illustrated resistor/discrete PNP

transistor configuration can be used to shorten the discharge time by a factor

of 50 or more. When the internal discharge transistor in the SG1825C turns

on, current will flow through surge limit resistor R1. As the resistor drop

approaches 0.6 volts, the external PNP turns on, providing a low resistance

discharge path for the energy in the softstart capacitor. The capacitor will

be rapidly discharged to +0.7 volts, which corresponds to zero duty cycle

in the pulse width modulator.

SG1825C

R₁

100W

C_SS

V_C

PWR GND

C_SOFTSTART

+V_IN

GND

0.1µF

1µF

+ V_IN

FIGURE 4. OSCILLATOR SYCHRONIZATION

FREQUENCY SYNCHRONIZATION

MASTER

CLK

SLAVE

CLK

Two or three SG1825C oscillators may be locked together with the

interconnection scheme shown, if the devices are within an inch or so of

each other. A master unit is programmed for desired frequency with R_Tand

C_Tas usual. The oscillators in the slave units are disabled by grounding C_T

and by connecting R_Tto V_REF. The logic in the slave units is locked to the

clock of the master with the wire-OR connection shown.

Many SG1825Cs can be locked to a master system clock by wiring the

oscillators as slave units, and distributing the master clock to each using a

tree-fanout geometry.

V_REF

SG1825C

R_T

C_T

PWR GND

R_T

+V_IN

C_T

+V_IN

GND

0.1µF

+ V_IN

Rev. 1.3 6/96

P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7

SG1825C/SG2825C/SG3825C

H I G H - S P E E D C U R R E N T - M O D E P W M

N O T R E C O M M E N D E D F O R N E W D E S I G N S

APPLICATION INFORMATION

OSCILLATOR

APPLICATION FIGURES

FIGURE 5. OSCILLATOR FUNCTIONAL DIAGRAM

The oscillator frequency is programmed by external timing components R_T

and C_T. A nominal +3.0 volts appears at the R_Tpin. The current flowing

through R_Tis mirrored internally with a 1:1 ratio. This causes an identical

current to flow out the C_Tpin, charging the timing capacitor and generating

a linear ramp. When the upper threshold of +2.8 volts is reached, a

discharge network reduces the ramp voltage to +1.0, where a new charge

cycle begins.

I_R

R_T

SG1825C

+ 5.1V

I_C= I_R

C_T

+ 4.5V

+ 2.3V

The Clock output pin is LOW (+2.3 volts) during the charge cycle, and

HIGH (+4.5 volts) during the discharge cycle. The Clock pin is driven by

an NPN emitter follower, and so can be wire-ORed. Each Clock pin can drive

a 1mA load. Since the internal current-source pulldown is approximately

400µA, the DC fan-out to other SG1825C Clock pins is at least two.

The type of capacitor selected for C_Tis very important. At high

frequencies, non-ideal characteristics such as effective series resistance

(ESR), effective series inductance (ESL), dielectric loss and dielectric

absorption all affect frequency accuracy and stability. RF capacitors such as

silver mica, glass, polystrene, or COG ceramics are recommended. Avoid

high-K ceramics, which work best in DC bypass applications.

CLOCK

400µA

2.8V

1.0V

FIGURE 6. VOLTAGE AMPLIFIER CONNECTIONS

R₁

ERROR AMPLIFIER

V_REF

V_ERROR

The voltage error amplifier is a true operational amplifier with low-

impedance output, and can be gain-stabilized using conventional feedback

techniques. The typical DC open-loop gain is 95dB, with a single low-

frequency pole at 100Hz.

The input connections to the error amplifier are determined by the

polarity of the power supply output voltage. For positive supplies, the

common-mode voltage is +5.1 volts and the feedback connections in Figure

A are used. With negative outputs, the common-mode voltage is half the

reference, and the feedback divider is connected between the negative

output and the +5.1 volt reference as shown in Figure B.

R₂

R₃

R_Z

C_P

POSITIVE

OUTPUT

VOLTAGE

R₄

FIGURE A

FIGURE B

NEGATIVE

OUTPUT

R₄

VOLTAGE

R₁

V_REF

V_ERROR

R₂

R₃

V_REF

OUTPUT DRIVER

R_Z

C_P

The output drivers are designed to provide up to 1.5 Amps peak output

current. To minimize ringing on the output waveform, which can be

destructive to both the power MOSFET and the PWM chip, the series

inductance seen by the drivers should be as low as possible.

FIGURE 7. DRIVING SHIELDED CABLE

One solution is to keep the distance between the PWM and MOSFET gate

as short as possible, and to use carbon composition series damping resistors.

A Faraday shield to intercept radiated EMI from the power transistors is

usually required with its choice.

A second approach is to place the MOSFETs some distance from the PWM

chip, and use a series-terminated transmission line to preserve drive pulse

fidelity. This will minimize noise radiated back to the sensitive analog

circuitry of the SG1825C. A Faraday shield may also be required.

If the drivers are connected to an isolation transformer, or if kickback

through C_GDof the MOSFET is severe, clamp diodes may be required. 1 Amp

peak Schottky diodes will limit undershoot to less than -0.3 volts.

FARADAY SHIELD

V_C

SG1825C

50W

24W

PWR GND

GND

* SCHOTTKY CLAMP MAY BE REQUIRED

Rev. 1.3 6/96

SG1825CJ/883B [MICROSEMI]

相关型号：

SG1825CJ/883B-TR

SG1825CJ/DESC

SG1825CL

SG1825CL-883B

SG1825CL-DESC

SG1825CL-TR

SG1825CL-TR/883

SG1825CL-TR/883B

SG1825CL-TR/DESC

SG1825CL/883

SG1825CL/883-TR

SG1825CL/883B