MT90820APR [MICROSEMI]
Telecom IC, CMOS, PQCC84;
| 型号： | MT90820APR |
| 厂家： | 
Microsemi |
| 描述： | Telecom IC, CMOS, PQCC84 |
| 文件： | 总37页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS ST-BUSTM Family
MT90820
Large Digital Switch
Data Sheet
August 2005
Features
•
2,048 × 2,048 channel non-blocking switching at
Ordering Information
8.192 Mb/s
MT90820AP
84 Pin PLCC
Tubes
•
Per-channel variable or constant throughput
delay
Automatic identification of ST-BUS/GCI interfaces
MT90820AL
MT90820APR
MT90820AL1
MT90820AP1
100 Pin MQFP
84 Pin PLCC
Trays
Tape & Reel
100 Pin MQFP* Trays
•
•
84 Pin PLCC*
MT90820APR1 84 Pin PLCC*
*Pb Free Matte Tin
Tubes
Tape & Reel
Accept ST-BUS streams of 2.048 Mb/s,
4.096 Mb/s or 8.192 Mb/s
-40°C to +85°C
•
•
•
•
•
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel message mode
Applications
•
•
•
•
•
•
Medium and large switching platforms
CTI application
Control interface compatible to Motorola non-
mulitplexed CPUs
Voice/data multiplexer
Digital cross connects
•
•
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
ST-BUS/GCI interface functions
Support IEEE 802.9a standard
V
V
SS
ODE
TMS
TDI TDO TCK TRST
IC
RESET
DD
Test Port
Loopback
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
Serial
to
Parallel
to
Output
Parallel
Multiple Buffer
Data Memory
MUX
Serial
Converter
Converter
Connection
Memory
Internal
Registers
Timing
Unit
Microprocessor Interface
CLK F0i FE/ WFPS
HCLK
AS/ IM DS/
CS R/W
/WR
D15-D8/ CSTo
A7-A0 DTA
ALE
RD
AD7-AD0
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT90820
Data Sheet
Description
The MT90820 Large Digital Switch has a non-blocking switch capacity of 2,048 x 2,048 channels at a serial bit rate
of 8.192 Mb/s, 1,024 x 1,024 channels at 4.096 Mb/s and 512 x 512 channels at 2.048 Mb/s. The device has many
features that are programmable on per stream or per channel basis, including message mode, input offset delay
and high impedance output control.
Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice
channel and concatenated data channels.
In addition, input stream can be individually calibrated for input frame offset using a dedicated pin.
2
Zarlink Semiconductor Inc.
MT90820
Data Sheet
10
8
6
4
2
84
82
80
78
76
STi0
STi1
CSTo
DTA
D15
D14
D13
D12
D11
D10
D9
13
73
STi2
STi3
15
17
19
21
23
25
27
29
31
71
69
67
65
63
61
59
57
55
STi4
STi5
STi6
STi7
STi8
STi9
D8
84 PIN PLCC
STi10
STi11
STi12
STi13
STi14
STi15
F0i
VSS
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
FE/HCLK
VSS
CLK
VDD
34
36
38
40
42
44
46
48
50
52
80
82
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
DTA
D15
D14
D13
D12
D11
D10
D9
STi0
STi1
STi2
84
86
88
90
92
94
96
STi3
STi4
STi5
STi6
STi7
D8
STi8
VSS
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
STi9
STi10
STi11
STi12
STi13
STi14
STi15
F0i
100 PIN MQFP
98
99
FE/HCLK
VSS
CLK
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Figure 2 - Pin Connections
3
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Pin Description
Pin #
Name
Description
84
100
PLCC MQFP
1, 11, 31, 41,
VSS
Ground.
30, 54 56, 66,
64, 75
76, 99
2, 32,
63
5, 40,
67
VDD
+5 Volt Power Supply.
3 - 10
68-75
STo8 - 15 ST-BUS Output 8 to 15 (Three-state Outputs): Serial data Output stream. These
streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value
programmed at bits DR0 - 1 in the IMS register.
12 - 27 81-96
STi0 - 15 ST-BUS Input 0 to 15 (Inputs): Serial data input stream. These streams may have data
rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 -
1 in the IMS register.
28
97
F0i
Frame Pulse (Input): When the WFPS pin is low, this input accepts and automatically
identifies frame synchronization signals formatted according to ST-BUS and GCI
specifications. When the WFPS pin is high, this pin accepts a negative frame pulse which
conforms to WFPS formats.
29
31
98
FE/HCLK Frame Evaluation / HCLK Clock (Input): When the WFPS pin is low, this pin is the
frame measurement input. When the WFPS pin is high, the HCLK (4.096 MHz clock) is
required for frame alignment in the wide frame pulse (WFP) mode.
100
CLK
Clock (Input): Serial clock for shifting data in/out on the serial streams (STi/o 0 - 15).
Depending upon the value programmed at bits DR0 - 1 in the IMS register, this input
accepts a 4.096, 8.192 or 16.384 MHz clock.
33
34
35
36
37
6
7
TMS
TDI
Test Mode Select (Input): JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up when not driven.
Test Serial Data In (Input): JTAG serial test instructions and data are shifted in on this
pin. This pin is pulled high by an internal pull-up when not driven.
8
TDO
TCK
TRST
Test Serial Data Out (Output): JTAG serial data is output on this pin on the falling edge
of TCK. This pin is held in high impedance state when JTAG scan is not enable.
9
Test Clock (Input): Provides the clock to the JTAG test logic. This pin is pulled high by
an internal pull-up when not driven.
10
Test Reset (Input): Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This
pin should be pulsed low on power-up, or held low, to ensure that the MT90820 is in the
normal functional mode.
38
11
IC
Internal Connection (Input): Connect to VSS for normal operation. This pin must be
low for the MT90820 to function normally and to comply with IEEE 1149 (JTAG)
boundary scan requirements. This pin is pulled low internally when not driven.
4
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Pin Description
Pin #
Name
Description
84
100
PLCC MQFP
39
40
12
13
RESET
Device Reset (Schmitt Trigger Input): This input (active LOW) puts the MT90820 in
its reset state that clears the device internal counters, registers and brings STo0 - 15 and
microport data outputs to a high impedance state. The time constant for a power up reset
circuit must be a minimum of five times the rise time of the power supply. In normal
operation, the RESET pin must be held low for a minimum of 100 nsec to reset the
device.
WFPS
A0 - A7
DS/RD
Wide Frame Pulse Select (Input): When 1, enables the wide frame pulse (WFP) Frame
Alignment interface. When 0, the device operates in ST-BUS/GCI mode.
41 - 48 14-21
Address 0 - 7 (Input): When non-multiplexed CPU bus operation is selected, these lines
provide the A0 - A7 address lines to the internal memories.
49
50
22
23
Data Strobe / Read (Input): For multiplexed bus operation, this input is DS. This active
high DS input works in conjunction with CS to enable the read and write operations.
For Motorola non-multiplexed CPU bus operation, this input is DS. This active low input
works in conjunction with CS to enable the read and write operations.
For multiplexed bus operation, this input is RD. This active low input sets the data bus
lines (AD0-AD7, D8-D15) as outputs.
R/W / WR Read/Write / Write (Input): In the cases of Motorola non-multiplexed and multiplexed
bus operations, this input is R/W. This input controls the direction of the data bus lines
(AD0 - AD7, D8-D15) during a microprocessor access.
For multiplexed bus operation, this input is WR. This active low input is used with RD to
control the data bus (AD0 - 7) lines as inputs.
51
52
24
25
CS
Chip Select (Input): Active low input used by a microprocessor to activate the
microprocessor port of MT90820.
AS/ALE Address Strobe or Latch Enable (Input): This input is used if multiplexed bus
operation is selected via the IM input pin. For Motorola non-multiplexed bus operation,
connect this pin to ground. This pin is pulled low by an internal pull-down when not
driven.
53
26
IM
CPU Interface Mode (input): When IM is high, the microprocessor port is in the
multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed mode.
This pin is pulled low by an internal pull-down when not driven.
55 - 62 32-39
65 - 72 42-49
AD0 - 7
Address/Data Bus 0 to 7 (Bidirectional): These pins are the eight least significant data
bits of the microprocessor port. In multiplexed mode, these pins are also the input address
bits of the microprocessor port.
D8 - 15
DTA
Data Bus 8-15 (Bidirectional): These pins are the eight most significant data bits of the
microprocessor port.
73
50
Data Transfer Acknowledgement (Active Low Output): Indicates that a data bus
transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states,
allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required
to hold a HIGH level when the pin is tri-stated.
74
55
CSTo
Control Output (Output). This is a 4.096, 8.192 or 16.384 Mb/s output containing 512,
1024 or 2048 bits per frame respectively. The level of each bit is determined by the CSTo
bit in the connection memory. See External Drive Control Section.
5
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Pin Description
Pin #
Name
Description
84
100
PLCC MQFP
76 57
ODE
Output Drive Enable (Input): This is the output enable control for the STo0 to STo15
serial outputs. When ODE input is low and the OSB bit of the IMS register is low, STo0-
15 are in a high impedance state. If this input is high, the STo0-15 output drivers are
enabled. However, each channel may still be put into a high impedance state by using the
per channel control bit in the connection memory.
77 - 84 58-65
STo0 - 7
NC
Data Stream Output 0 to 7 (Three-state Outputs): Serial data Output stream. These
streams have selectable data rates of 2.048, 4.096 or 8.192 Mb/s.
-
1 - 4,
27 - 30,
51 - 54
77 - 80
No connection.
Device Overview
The MT90820 Large Digital Switch is capable of switching up to 2,048 × 2,048 channels. The MT90820 is designed
to switch 64 kbit/s PCM or N x 64 kbit/s data. The device maintains frame integrity in data applications and
minimum throughput delay for voice applications on a per channel basis.
The serial input streams of the MT90820 can have a bit rate of 2.048, 4.096 or 8.192 Mbit/s and are arranged in
125 µs wide frames, which contain 32, 64 or 128 channels, respectively. The data rates on input and output
streams are identical.
By using Zarlink’s message mode capability, the microprocessor can access input and output time-slots on a per
channel basis. This feature is useful for transferring control and status information for external circuits or other ST-
BUS devices. The MT90820 automatically identifies the polarity of the frame synchronization input signal and
configures its serial streams to be compatible to either ST-BUS or GCI formats.
Two different microprocessor bus interfaces can be selected through the Input Mode pin (IM): Non-multiplexed or
Multiplexed. These interfaces provide compatibility with multiplexed and Motorola non-multiplexed buses.
The frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin
(FE). The input offset delay can be programmed for individual streams using internal frame input offset registers,
see Table 11.
The internal loopback allows the ST-BUS output data to be looped around to the ST-BUS inputs for diagnostic
purposes.
Functional Description
A functional Block Diagram of the MT90820 is shown in Figure 1.
Data and Connection Memory
For all data rates, the received serial data is converted to parallel format by internal serial-to-parallel converters and
stored sequentially in the data memory. Depending upon the selected operation programmed in the interface mode
select (IMS) register, the useable data memory may be as large as 2,048 bytes. The sequential addressing of the
data memory is performed by an internal counter, which is reset by the input 8 kHz frame pulse (F0i) to mark the
frame boundaries of the incoming serial data streams.
6
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Data to be output on the serial streams may come from either the data memory or connection memory. Locations in
the connection memory are associated with particular ST-BUS output channels. When a channel is due to be
transmitted on an ST-BUS output, the data for this channel can be switched either from an ST-BUS input in
connection mode, or from the lower half of the connection memory in message mode. Data destined for a particular
channel on a serial output stream is read from the data memory or connection memory during the previous channel
time-slot. This allows enough time for memory access and parallel-to-serial conversion.
Connection and Message Modes
In the connection mode, the addresses of the input source data for all output channels are stored in the connection
memory. The connection memory is mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 13 and Table
14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the
selected address are transferred to the parallel-to-serial converters and then onto an ST-BUS output stream.
By having several output channels connected to the same input source channel, data can be broadcasted from one
input channel to several output channels.
In message mode, the microprocessor writes data to the connection memory locations corresponding to the output
stream and channel number. The lower half (8 least significant bits) of the connection memory content is
transferred directly to the parallel-to-serial converter. This data will be output on the ST-BUS streams in every frame
until the data is changed by the microprocessor.
The five most significant bits of the connection memory controls the following for an output channel: message or
connection mode, constant or variable delay, enables/tristate the ST-BUS output drivers and enables/disable the
loopback function. In addition, one of these bits allows the user to control the CSTo output.
If an output channel is set to a high-impedance state through the connection memory, the ST-BUS output
will be in a high impedance state for the duration of that channel. In addition to the per-channel control, all channels
on the ST-BUS outputs can be placed in a high impedance state by either pulling the ODE input pin low or
programming the output stand by (OSB) bit in the interface mode selection register to low. This action overrides the
individual per-channel programming by the connection memory bits.
The connection memory data can be accessed via the microprocessor interface through the D0 to D15 pins. The
addressing of the device internal registers, data and connection memories is performed through the address input
pins and the Memory Select (MS) bit of the control register. For details on device addressing, see Software Control
and Control Register bits description (Table 4, Tables 6 and 7).
Serial Data Interface Timing
The master clock frequency must always be twice the data rate. The master clock (CLK) must be either at 4.096,
8.192 or 16.384 MHz for serial data rate of 2.048, 4.096 or 8.192 Mb/s respectively. The input and output stream
data rates will always be identical.
The MT90820 provides two different interface timing modes controlled by the WFPS pin. If the WFPS pin is low, the
MT90820 is in ST-BUS/GCI mode. If the WFPS pin is high, the MT90820 is in the wide frame pulse (WFP) frame
alignment mode.
In ST-BUS/GCI mode, the input 8 kHz frame pulse can be in either ST-BUS or GCI format. The MT90820
automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS
format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising
edge of CLK, three quarters of the way into the bit cell. In GCI format, every second rising edge of the master clock
marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell,
see Figure 12.
7
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Wide Frame Pulse (WFP) Frame Alignment Timing
When the device is in WFP frame alignment mode, the CLK input must be at 16.384 MHz, the FE/HCLK input is
4.096 MHz and the 8 kHz frame pulse is in ST-BUS format. The timing relationship between CLK, HCLK and the
frame pulse is defined in Figure 12.
When WFPS pin is high, the frame alignment evaluation feature is disabled, but the frame input offset registers may
still be programmed to compensate for the varying frame delays on the serial input streams.
Switching Configurations
The MT90820 maximum non-blocking switching configurations is determined by the data rates selected for the
serial inputs and outputs. The switching configuration is selected by two DR bits in the IMS register. See Table 8
and Table 9.
2.048 Mb/s Serial Links (DR0=0, DR1=0)
When the 2.048 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each
having 32 64 Kbit/s channels each. This mode requires a CLK of 4.094 MHz and allows a maximum non-blocking
capacity of 512 x 512 channels.
4.096 Mb/s Serial Links (DR0=1, DR1=0)
When the 4.096 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each
having 64 64 Kbit/s channels each. This mode requires a CLK of 8.192 MHz and allows a maximum non-blocking
capacity of 1,024 x 1,024 channels.
8.192 Mb/s Serial Links (DR0=0, DR1=1)
When the 8.192 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each
having 128 64 Kbit/s channels each. This mode requires a CLK of 16.384 MHz and allows a maximum non-
blocking capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching configurations and the relationship
between different serial data rates and the master clock frequencies.
Master Clock
Serial Interface
Data Rate
MatrixChannel
Capacity
Required
(MHz)
2 Mb/s
4 Mb/s
8 Mb/s
4.096
8.192
512 x 512
1,024 x 1,024
2,048 x 2,048
16.384
Table 1 - Switching Configuration
8
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Input Frame Offset Selection
Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the
output stream channel alignment (i.e., F0i). This feature is useful in compensating for variable path delays caused
by serial backplanes of variable lengths, which may be implemented in large centralized and distributed switching
systems.
Each input stream can have its own delay offset value by programming the frame input offset (FOR) registers.
Possible adjustment can range up to +4 master clock (CLK) periods forward with resolution of 1/2 clock period. The
output frame offset cannot be offset or adjusted. See Figure 4, Table 11 and Table 12 for delay offset programming.
Serial Input Frame Alignment Evaluation
The MT90820 provides the frame evaluation (FE) input to determine different data input delays with respect to the
frame pulse F0i.
A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the
evaluation starts when the SFE bit in the IMS register is changed from low to high. Two frames later, the complete
frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high to signal that a valid
offset measurement is ready to be read from bits 0 to 11 of the FAR register. The SFE bit must be set to zero before
a new measurement cycle started.
In ST-BUS mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the
ST-BUS frame pulse. In GCI mode, the rising edge of FE is evaluated against the rising edge of the GCI frame
pulse. See Table 10 & Figure 3 for the description of the frame alignment register.
This feature is not available when the WFP Frame Alignment mode is enabled (i.e., when the WFPS pin is
connected to VDD).
Memory Block Programming
The MT90820 provides users with the capability of initializing the entire connection memory block in two frames.
Bits 11 to 15 of every connection memory location will be programmed with the pattern stored in bits 5 to 9 of the
IMS register.
The block programming mode is enabled by setting the memory block program (MBP) bit of the control register
high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The other connection memory bits (bit 0 to
bit 10) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to
zero.
Loopback Control
The loopback control (LPBK) bit of each connection memory location allows the ST-BUS output data to be looped
backed internally to the ST-BUS input for diagnostic purposes.
If the LPBK bit is high, the associated ST-BUS output channel data is internally looped back to the ST-BUS input
channel (i.e., data from STo n channel m will appear in STi n channel m). Note: when LPBK is activated in channel
m STo n+1 (for n even) or STo n-1 (for n odd), the data from channel m of STi n will be switched to channel m STo
n. The associated frame delay offset register must be set to zero for proper operation of the per-channel loopback
function. If the LPBK bit is low, the per-channel loopback feature is disabled and the device will function normally.
Delay Through the MT90820
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform time-slot interchange functions with different throughput delay
capabilities on the per-channel basis. For voice application, select variable throughput delay to ensure minimum
9
Zarlink Semiconductor Inc.
MT90820
Data Sheet
delay between input and output data. In wideband data applications, select constant throughput delay to maintain
the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected in the V/C bit of the
connection memory.
Variable Delay Mode (V/C bit = 0)
The delay in this mode is dependent only on the combination of source and destination channels and is
independent of input and output streams. The minimum delay achievable in the MT90820 is three time-slots. When
the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following
frame (channel n, frame p+1). The same frame delay occurs if the input channel n is switched to output channel
n+1 or n+2. When input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 2 shows the possible delays for the MT90820 in the variable delay mode.
Constant Delay Mode (V/C bit = 1)
In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory
buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2.
In the MT90820, the minimum throughput delay achievable in the constant delay mode will be one frame. For
example, in 2 Mb/s mode, when input time-slot 31 is switched to output time-slot 0. The maximum delay of 94 time-
slots of delay occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 3.
Delay for Variable Throughput Delay Mode
(m - output channel number)
(n - input channel number))
Input Rate
m < n
m = n, n+1, n+2
m > n+2
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
32 - (n-m) time-slots
64 - (n-m) time-slots
128 - (n-m) time-slots
m-n + 32 time-slots
m-n + 64 time-slots
m-n + 128 time-slots
m-n time-slots
m-n time-slots
m-n time-slots
Table 2 - Variable Throughput Delay Value
Delay for Constant Throughput Delay Mode
(m - output channel number)
Input Rate
(n - input channel number))
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
32 + (32 - n) + (m - 1) time-slots
64 + (64 - n) + (m- 1) time-slots
128 + (128 - n) + (m- 1) time-slots
Table 3 - Constant Throughput Delay Value
Microprocessor Interface
The MT90820 provides a parallel microprocessor interface for non-multiplexed or multiplexed bus structures. This
interface is compatible with Motorola non-multiplexed and multiplexed buses.
If the IM pin is low, the MT90820 microprocessor interface assumes Motorola non-multiplexed bus mode. If the IM
pin is high, the device micro-processor interface accepts two different timing modes (mode1 and mode2) which
allows direct connection to multiplexed microprocessors.
10
Zarlink Semiconductor Inc.
MT90820
Data Sheet
The microprocessor interface automatically identifies the type of micro-processor bus connected to the MT90820.
This circuit uses the level of the DS/RD input pin at the rising edge of AS/ALE to identify the appropriate bus timing
connected to the MT90820. If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed timing is
selected. If DS/RD is high at the rising edge of AS/ALE, then the mode 2 multiplexed bus timing is selected.
For multiplexed operation, the required signals are the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15),
Address strobe/Address latch enable (AS/ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR), Chip
select (CS) and Data transfer acknowledge (DTA). See Figure 13 and Figure 14 for multiplexed parallel microport
timing.
For the Motorola non-multiplexed bus, the required signals are the 16-bit data bus (AD0-AD7, D8-D15), 8-bit
address bus (A0-A7) and 4 control lines (CS, DS, R/W and DTA). See Figure 15 for Motorola non-multiplexed
microport timing.
The MT90820 microport provides access to the internal registers, connection and data memories. All locations
provide read/write access except for the data memory and the frame alignment register which are read only.
Memory Mapping
The address bus on the microprocessor interface selects the internal registers and memories of the MT90820. If
the A7 address input is low, then the control (CR), interface mode selection (IMS), frame alignment (FAR) and
frame input offset (FOR) registers are addressed by A6 to A0 according to Table 4.
If the A7 is high, then the remaining address input lines are used to select memory subsections of up to 128
locations corresponding to the maximum number of channels per input or output stream. The address input lines
and the stream address bits (STA) of the control register allow access to the entire data and connection memories.
The control and IMS registers together control all the major functions of the device. The IMS register should be
programmed immediately after system power-up to establish the desired switching configuration as explained in the
Serial Data Interface Timing and Switching Configurations sections.
The control register is used to control switching operations in the MT90820. It selects the internal memory locations
that specify the input and output channels selected for switching.
The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS)
and the stream address bits (STA). The memory block programming bit allows users to program the entire
connection memory block, (see Memory Block Programming section). The memory select bit controls the selection
of the connection memory or the data Memory. The stream address bits define an internal memory subsections
corresponding to input or output ST-BUS streams.
The data in the IMS register consists of block programming bits (BPD0-BPD4), block programming enable bit
(BPE), output stand by bit (OSB), start frame evaluation bit (SFE) and data rate selection bits (DR0, DR1). The
block programming and the block programming enable bits allows users to program the entire connection memory,
(see Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all
ST-BUS output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all ST-BUS output drivers
are enabled.
Connection Memory Control
The contents of the CSTo bit of each connection memory location are output on the CSTo pin once every frame.
The CSTo pin is a 4.096, 8.192 or 16.384 Mb/s output, which carries 512, 1,024 or 2,048 bits, respectively. If the
CSTo bit is set high, the corresponding bit on the CSTo output is transmitted high. If the CSTo bit is low, the
corresponding bit on the CSTo output is transmitted low. The contents of the CSTo bits of the connection memory
are transmitted sequentially on to the CSTo pin and are synchronous with the data rates on the other ST-BUS
streams.
The CSTo bit is output one channel before the corresponding channel on the ST-BUS. For example, in 2 Mb/s
mode, the contents of the CSTo bit in position 0 (STo0, CH0) of the connection memory is output on the first clock
11
Zarlink Semiconductor Inc.
MT90820
Data Sheet
cycle of channel 31 through CSTo pin. The contents of the CSTo bit in position 32 (STo1, CH0) of the connection
memory is output on the second clock cycle of channel 31 via CSTo pin.
If the ODE pin or the OSB bit is high, the OE bit of each connection memory location enables (if high) or disables (if
low) the output drivers for an individual ST-BUS output stream and channel. See Table 5 for detail.
The message channel (MC) bit of the connection memory enables (if high) an associated ST-BUS output channel in
message mode. If the MC bit is low, the contents of the stream address bit (SAB) and the channel address bit
(CAB) of the connection memory defines the source information (stream and channel) of the time-slot that will be
switched to the output. When message mode is enabled, only the lower half (8 least significant bits) of the
connection memory is transferred to the ST-BUS outputs.
Bit V/C (Variable/Constant Delay) of each connection memory location allows the per-channel selection between
variable and constant throughput delay modes.
If the LPBK bit is high, the associated ST-BUS output channel data is internally looped back to the ST-BUS input
channel (i.e., data from STo n channel m will appear in STi n channel m). Note: when LPBK is activated in channel
m STo n+1 (for n even) or STo n-1 (for n odd), the data from channel m of STi n will be switched to channel m STo
n. The associated frame delay offset register must be set to zero for proper operation of the per-channel loopback
function. If the LPBK bit is low, the per-channel loopback feature is disabled and the device will function normally.
Initialization of the MT90820
After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after
power up to keep all ST-BUS outputs in a high impedance state until the microprocessor has initialized the
switching matrix.
During the microprocessor initialization routine, the microprocessor should program the desired active paths
through the switch, and put all other channels into a high impedance state. This procedure prevents two ST-BUS
outputs from driving the same stream simultaneously. When this process is complete, the microprocessor
controlling the matrices can bring the ODE pin or OSB bit high to relinquish the high impedance state control to the
OE bit in the connection memory.
A7
A6
A5
A4
A3
A2
A1
A0
Location
Control Register, CR
(Note 1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Interface Mode Selection Register, IMS
Frame Alignment Register, FAR
Frame Input Offset Register 0, FOR0
Frame Input Offset Register 1, FOR1
Frame Input Offset Register 2, FOR2
Frame Input Offset Register 3, FOR3
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
Ch 0
Ch 1
.
1
1
1
1
1
1
1
1
0
1
Ch 30
Ch 31
(Note 2)
12
Zarlink Semiconductor Inc.
MT90820
Data Sheet
A7
A6
A5
A4
A3
A2
A1
A0
Location
(Note 1)
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
Ch 32
Ch 33
.
1
1
1
1
1
1
1
1
0
1
Ch 62
Ch 63
(Note 3)
1
1
1
1
1
1
1
1
1
1
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
Ch 64
Ch 65
.
1
1
1
1
1
1
1
1
1
1
0
1
Ch 126
Ch 127
(Note 4)
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial interface is at 2 Mb/s mode.
3. Channels 0 to 63 are used when serial interface is at 4 Mb/s mode.
4. Channels 0 to 127 are used when serial interface is at 8 Mb/s mode.
Table 4 - Internal Register and Address Memory Mapping
OE bit in Connection
ODE pin
OSB bit in IMS register
ST-BUS Output Driver Status
Memory
0
Don’t Care
Don’t Care
Per Channel
High Impedance
1
1
1
1
0
0
1
1
0
1
0
1
High Impedance
Enable
Enable
Enable
Table 5 - Output High Impedance Control
Read/Write Address:
Reset Value:
00H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
MBP
MS STA3 STA2 STA1 STA0
Bit
Name
Description
15 - 6
5
Unused
MBP
Must be zero for normal operation.
Memory Block Program. When 1, the connection memory block programming feature is
ready for the programming of Connection Memory high bits, bit 11 to bit 15. When 0, this
feature is disabled.
4
MS
Memory Select. When 0, connection memory is selected for read or write operations. When 1,
the data memory is selected for read operations and connection memory is selected for write
operations. (No microprocessor write operation is allowed for the data memory.)
13
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Read/Write Address:
Reset Value:
00H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
MBP
MS STA3 STA2 STA1 STA0
Bit
Name
STA3-0
Description
3 - 0
Stream Address Bits. The binary value expressed by these bits refers to the input or output
data stream, which corresponds to the subsection of memory made accessible for subsequent
operations. (STA3 = MSB, STA0 = LSB)
Table 6 - Control (CR) Register Bits
Input/Output
Valid Address Lines
Data Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
A4, A3, A2, A1, A0
A5, A4, A3, A2, A1, A0
A6, A5, A4 A3, A2, A1, A0
Table 7 - Valid Address Lines for Different Bit Rates
Read/Write Address:
Reset Value:
01H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BPD
4
BPD
3
BPD
2
BPD
1
BPD
0
0
0
0
0
0
0
BPE
OSB
SFE
DR1
DR0
Bit
Name
Description
15-10
9-5
Unused
BPD4-0
Must be zero for normal operation.
Block Programming Data. These bits carry the value to be loaded into the connection
memory block whenever the memory block programming feature is activated. After the MBP
bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD4- 0
are loaded into bit 15 to bit 11 of the connection memory. Bit 10 to bit 0 of the connection
memory are set to 0.
4
BPE
Begin Block programming Enable. A zero to one transition of this bit enables the memory
block programming function. The BPE and BPD4-0 bits in the IMS register have to be defined
in the same write operation. Once the BPE bit is set high, the device requires two frames to
complete the block programming. After the programming function has finished, the BPE bit
returns to zero to indicate the operation is completed. When the BPE = 1, the BPE or MBP can
be set to 0 to abort the programming operation.
When BPE = 1, the other bits in the IMS register must not be changed for two frames to ensure
proper operation.
14
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Read/Write Address:
Reset Value:
01H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BPD
4
BPD
3
BPD
2
BPD
1
BPD
0
0
0
0
0
0
0
BPE
OSB
SFE
DR1
DR0
Bit
Name
Description
3
OSB
Output Stand By. When ODE = 0 and OSB = 0, the output drivers of STo0 to STo15 are in
high impedance mode. When ODE = 0 and OSB = 1, the output driver of STo0 to STo15
function normally. When ODE = 1, STo0 to STo15 output drivers function normally.
2
SFE
Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the FAR register changes from zero to one, the evaluation
procedure stops. To start another frame evaluation cycle, set this bit to zero for at least one
frame.
1 - 0
DR1-0
Data Rate Select. Input/Output data rate selection. See Table 9 for detailed programming.
Table 8 - Interface Mode Selection (IMS) Register Bits
DR1
DR0
Data Rate Selected
Master Clock Required
0
0
1
1
0
1
0
1
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Reserved
4.096 MHz
8.192 MHz
16.384 MHz
Reserved
Table 9 - Serial Data Rate Selection (16 input x 16 output)
Read Address:
Reset Value:
02H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
CFE
FD11 FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
0
Bit
Name
Description
15 - 13
12
Unused
CFE
Must be zero for normal operation.
Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed and
bits FD10 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.
11
FD11
Frame Delay Bit 11. The falling edge of FE (or rising edge for GCI mode) is sampled
during the CLK-high phase (FD11 = 1) or during the CLK-low phase (FD11 = 0). This
bit allows the measurement resolution to 1/2 CLK cycle.
15
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Read Address:
Reset Value:
02H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
CFE
FD11 FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
0
Bit
10 - 0
Name
Description
FD10-0
Frame Delay Bits. The binary value expressed in these bits refers to the measured
input offset value. These bits are reset to zero when the SFE bit of the IMS register
changes from 1 to 0. (FD10 = MSB, FD0 = LSB)
Table 10 - Frame Alignment (FAR) Register Bits
ST-BUS Frame
CLK
Offset Value
FE Input
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
(FD[10:0] = 06H)
(FD11 = 0, sample at CLK low phase)
GCI Frame
CLK
Offset Value
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FE Input
(FD[10:0] = 09 )
H
(FD11 = 1, sample at CLK high phase)
Figure 3 - Example for Frame Alignment Measurement
16
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Read/Write Address:
Reset value:
03H for FOR0 register,
04H for FOR1 register,
05H for FOR2 register,
06H for FOR3 register,
0000H for all FOR registers.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF32
OF31
OF30
DLE3 OF22
OF21
OF20
DLE2 OF12
OF11
OF10
DLE1 OF02
OF01
OF00
DLE0
FOR0 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF72
OF71
OF70
DLE7 OF62
OF61
OF60
DLE6 OF52
OF51
OF50
DLE5
OF42
OF41
OF40
DLE4
FOR1 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92
OF91
OF90
DLE9
OF82
OF81
OF80
DLE8
FOR2 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
FOR3 register
Name
Description
(Note 1)
OFn2, OFn1, OFn0
Offset Bits 2,1 & 0. These three bits define how long the serial interface receiver takes to
recognize and store bit 0 from the STi input pin: i.e., to start a new frame. The input frame offset
can be selected to +4 clock periods from the point where the external frame pulse input signal is
applied to the F0i input of the device. See Figure 4.
DLEn
Data Latch Edge.
ST-BUS mode:
DLEn =0, if clock rising edge is at the 3/4 point of the bit cell.
DLEn =1, if when clock falling edge is at the 3/4 of the bit cell.
DLEn =0, if clock falling edge is at the 3/4 point of the bit cell.
DLEn =1, if when clock rising edge is at the 3/4 of the bit cell.
GCI mode:
Note 1: n denotes an input stream number from 0 to 15.
Table 11 - Frame Input Offset (FOR) Register Bits
Measurement Result from
Frame Delay Bits
Corresponding
Offset Bits
Input Stream
Offset
FD11
1
FD2
0
FD1
0
FD0
0
OFn2
0
OFn1
0
OFn0
0
DLEn
0
No clock period shift (Default)
17
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Measurement Result from
Frame Delay Bits
Corresponding
Offset Bits
Input Stream
Offset
FD11
FD2
FD1
FD0
OFn2
OFn1
OFn0
DLEn
+ 0.5 clock period shift
+1.0 clock period shift
+1.5 clock period shift
+2.0 clock period shift
+2.5 clock period shift
+3.0 clock period shift
+3.5 clock period shift
+4.0 clock period shift
+4.5 clock period shift
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
Table 12 - Offset Bits (OFn2, OFn1, OFn0, DLEn) & Frame Delay Bits (FD11, FD2-0)
ST-BUS F0i
CLK
offset=0, DLE=0
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
STi Stream
Bit 7
Bit 7
STi Stream
STi Stream
STi Stream
Bit 7
Bit 7
denotes the 3/4 point of the bit cell
GCI F0i
CLK
offset=0, DLE=0
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
Bit 0
Input Stream
Bit 0
Input Stream
Input Stream
Input Stream
Bit 0
Bit 0
denotes the 3/4 point of the bit cell
Figure 4 - Examples for Input Offset Delay Timing
18
Zarlink Semiconductor Inc.
MT90820
Data Sheet
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V/C
MC CSTo
OE
SAB3 SAB2 SAB1 SAB0 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
LPBK
Bit
Name
Description
15
LPBK
Per Channel Loopback. When 1, the STi n channel m data comes from the STo n
channel m. For proper per channel loopback operations, set the delay offset register
bits OFn[2:0] to zero for the streams which are in the loopback mode. Refer to the
section Loopback Control or Connection Memory Control for more details.
14
13
V/C
MC
Variable /Constant Throughput Delay. This bit is used to select between the
variable (low) and the constant delay (high) modes on a per-channel basis.
Message Channel. When 1, the contents of the connection memory are output on the
corresponding output channel and stream. Only the lower byte (bit 7 - bit 0) will be
output to the ST-BUS output pins. When 0, the contents of the connection memory
are the data memory address of the switched input channel and stream.
12
11
CSTo
OE
Control ST-BUS output. This bit is output on the CSTo pin one channel early. The
CSTo bit for stream 0 is output first.
Output Enable. This bit enables the ST-BUS output drivers on a per-channel basis.
When 1, the output driver functions normally. When 0, the output driver is in a high-
impedance state.
10 - 8,
7
SAB3-0
CAB6-0
Source Stream Address Bits. The binary value is the number of the data stream for
the source of the connection.
(Note 1)
6 - 0
Source Channel Address Bits. The binary value is the number of the channel for the
(Note 1)
source of the connection.
Note 1: If bit 13 (MC) of the corresponding connection memory location is 1 (device in message mode), then these entire 8 bits (SAB0, CAB6
- CAB0) are output on the output channel and stream associated with this location.
Table 13 - Connection Memory Bits
Data Rate
CAB Bits Used to Determine the Source Channel of the Connection
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
CAB4 to CAB0 (32 channel/input stream)
CAB5 to CAB0 (64 channel/input stream)
CAB6 to CAB0 (128 channel/input stream)
Table 14 - CAB Bits Programming for Different Data Rates
JTAG Support
The MT90820 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the boundary-scan circuitry is
controlled by an external test access port (TAP) Controller.
19
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Test Access Port (TAP)
The Test Access Port (TAP) provides access to the many test functions of the MT90820. It consists of three input
pins and one output pin. The following pins are from the TAP.
•
•
•
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain
independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrently with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
Vdd when it is not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vdd when it is not driven from an external source.
•
•
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to VDD.
Instruction Register
In accordance with the IEEE 1149.1 standard, the MT90820 uses public instructions. The MT90820 JTAG Interface
contains a two-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when
the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic
functions: to select the test data register that may operate while the instruction is current, and to define the serial
test data register path, which is used to shift data between TDI and DO during data register scanning.
Test Data Register
As specified in IEEE 1149.1, the MT90820 JTAG Interface contains two test data registers:
•
•
The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the MT90820 core logic.
The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO.
The MT90820 boundary scan register contains 118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit
clocked out. All tristate enable bits are active high.
20
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Boundary Scan Bit 0 to Bit 117
Device Pin
Tristate
Control
Output
Input
Scan Cell
Scan Cell
STo7
STo6
STo5
STo4
STo3
STo2
STo1
STo0
0
2
1
3
4
5
6
7
8
9
10
12
14
11
13
15
ODE
CSTo
DTA
16
17
18
19
D15
D14
D13
D12
D11
D10
D9
20
23
26
29
32
35
38
41
21
24
27
30
33
36
39
42
22
25
28
31
34
37
40
43
D8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
44
47
50
53
56
59
62
65
45
48
51
54
57
60
63
66
46
49
52
55
58
61
64
67
IM
AS/ALE
CS
68
69
70
71
72
R/W / WR
DS/RD
A7
A6
A5
A4
A3
A2
A1
A0
73
74
75
76
77
78
79
80
WFPS
81
82
RESET
Table 15 - Boundary Scan Register Bits
21
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Boundary Scan Bit 0 to Bit 117
Device Pin
Tristate
Control
Output
Input
Scan Cell
Scan Cell
CLK
FE/HCLK
F0i
83
84
85
STi15
STi14
STi13
STi12
STi11
STi10
STi9
STi8
STi7
STi6
STi5
STi4
STi3
STi2
STi1
STi0
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
STo15
STo14
STo13
STo12
STo11
STo10
STo9
102
104
106
108
110
112
114
116
103
105
107
109
111
113
115
117
STo8
Table 15 - Boundary Scan Register Bits
Applications
Switch Matrix Architectures
The MT90820 is an ideal device for medium to large size switch matrices. Applications where voice and grouped
data channels are transported within the same frame, the voice samples have to be time interchanged with a
minimum delay while maintaining the integrity of grouped data. To ensure the integrity of grouped data during
switching and to provide a minimum delay for voice connections, the MT90820 provides the per-channel selection
between variable and constant throughput delay. This can be selected by the V/C bit of the Connection Memory.
Figure 5 illustrates how four MT90820 devices can be used to form non-blocking switches up to 4096 channels with
data rate of 8.192 Mb/s.
22
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Serial Input Frame Alignment Evaluation
The MT90820 is capable of performing frame alignment evaluation. The frame pulse under evaluation is connected
to the FE (frame measurement) pin. An external multiplexer is required to selected one of the frame pulses related
to the different input streams. Figure 6 gives an example of performing measurement for 16 frame pulses can be
performed.
16 Streams
16 Streams
16 Streams
MT90820
#1
IN
16 Streams
OUT
MT90820
#2
MT90820
#3
Bit Rate
Size of
(IN/OUT)
Switch Matrix
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
1,024 - Channel Switch
2,048 - Channel Switch
4,096 - Channel Switch
MT90820
#4
Figure 5 - Switch Matrix with Serial Stream at Various Bit Rates
STi0
STi1
STi2
MT90820
Frame Alignment
Evaluation circuit
STo[0:15]
STi15
External
Mux
FE
CLK
FP
input
FP STi0
FP STi1
FP STi2
Central
Timing Source
FP STi15
Note:
1. Use the external mux to select one of the serial frame pulses.
2. To start a measurement cycle, set the Start Frame Evaluation (SFE) bit in the IMS register low for at least 1 frame.
3. Frame evaluation starts when the SFE bit is changed from low to high.
4. Two frames later, the Complete Frame Evaluation (CFE) bit of the Frame Alignment Register (FAR) changes from low to high to
signal the CPU that a valid offset measurement is ready to be read from bit [11:0] of the FAR register.
5. The SFE bit must be set to zero before a new measurement cycle started.
Figure 6 - Serial Input Frame Alignment Evaluation for Various Frame Pulses
Wide Frame Pulse (WFP) Frame Alignment Mode
When the device is the wide frame pulse mode, the device can operate in the HMVIP and MVIP-90 environment if
the input data streams are sampled at 3/4 bit time. When input data stream are sampled at half-bit time as specified
in the HMVIP and MVIP-90 standard, the device can only operate with data rate of 2 Mb/s. Refer to the ST-BUS
output delay parameter, tSOD, as specified in the AC Electrical Characteristic table.
23
Zarlink Semiconductor Inc.
MT90820
Data Sheet
The MT90820 is designed to accept a common frame pulse F0i, the 4.096 MHz and 16.384 MHz clocks required by
the HMVIP standards. To enable the Width Frame Pulse Frame Alignment Mode, the WFPS pin has to be set to
HIGH and the DR1and DR0 bits set for 8.192 MB/s data rate operation.
Digital Access Cross-Connect System
Figure 7 illustrates how the MT90820 can be used to construct, for example, a 256 E1/T1 digital access cross-
connect system (DACS). The system consists of 32 trunk cards each having eight E1 or T1 trunk interfaces for a
total of 256 trunks. The central switching block is constructed from 16 MT90820 devices.
Figure 8 shows how an 8,192 x 8,192 channel switch can be constructed from 4,096 x 4,096 channel switch
modules. Figure 5 shows the implementation of the 4,096 x 4,096 channel switch modules from four MT90820
devices. Therefore, 16 MT90820 devices are required to realize an 8,192 x 8,192 non-blocking switch module with
64 input and 64 output streams. Each stream has 128 channels per frame for a data rate of 8.192 Mb/s.
Figure 9 shows an eight-stream trunk card block diagram. The MT8986 Multi-rate Digital Switch are used to
concentrate the 32-channel 2.048 Mb/s ST-BUS (DSTi and DSTo) streams at each E1/T1 trunk onto four 128-
channel 8.192 Mb/s streams.
It will take 256 MT8986 devices to implement the switching matrix of using 32-channel 2.048 Mb/s ST-BUS streams
in a square (16 x 16) configuration. A large saving in component cost and board area can be achieved by using
128-channel 8.192 Mb/s streams. That is, the same capacity can be achieved using 64 MT8986 devices + 16
MT90820 devices for a total of 80 devices.
Trunk Card (TC) 0
E10
E17
128 channels at 8.192 Mb/s
8 x E1/T1
Trunk Card
TC1
8,192 x 8,192 channel
Switch Matrix
E18
8 x E1/T1
Trunk Card
E115
Sixteen MT90820
operate
in 8 Mb/s mode
64 input streams
x
(Figure 9)
64 output streams
TC31
E1247
E1255
8 x E1/T1
Trunk Card
Figure 7 - 256 E1/T1 Digital Access Cross-Connect System (DACS)
24
Zarlink Semiconductor Inc.
MT90820
Data Sheet
32 Streams
IN
4,096 x 4,096
Switch Matrix
(Figure 5)
4,096 x 4,096
32 Streams
Switch Matrix
(Figure 5)
OUT
32 Streams
4,096 x 4,096
Switch Matrix
(Figure 5)
4,096 x 4,096
Switch Matrix
(Figure 5)
32 Streams
Figure 8 - 8,192 x 8,192 Channel Switch Matrix
DSTo
STi0
STi1
E10
E11
E1/T1 Trunk 0
MT8986
2Mb/s
to
DSTi
STo0
STo1
256-channel out
DSTo
DSTi
8Mb/s
STi7
(8.192Mb/s pre channel)
E1/T1 Trunk 1
STo0
STo1
MT8986
8Mb/s
to
STi0
STi1
256-channel in
DSTo
DSTi
E17
E1/T1 Trunk 7
2Mb/s
STo7
(8.192Mb/s pre channel)
Figure 9 - Trunk Card Block Diagram
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
1
2
3
4
5
Supply Voltage
VDD
VI
Io
PD
TS
6.0
VDD +0.3
20
V
V
mA
W
Voltage on any pin I/O (other than supply pins)
Continuous Current at digital outputs
Package power dissipation (PLCC & PQFP)
Storage temperature
VSS - 0.3
2
- 65
+125
°C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
25
Zarlink Semiconductor Inc.
MT90820
Data Sheet
Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
4
Operating Temperature
Positive Supply
Input High Voltage
Input Low Voltage
TOP
VDD
VIH
VIL
-40
4.75
2.4
+85
5.25
VDD
0.4
°C
V
V
400 mV noise margin
400 mV noise margin
VSS
V
DC Electrical Characteristics - Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
@ 2 Mb/s
Sym.
Min.
Typ.
Max. Units
Test Conditions
Output unloaded
1
50
90
170
mA
mA
mA
V
Supply Current
IDD
@ 4 Mb/s
@ 8 Mb/s
Input High Voltage
Input Low Voltage
Input Leakage (input pins)
Input Leakage (bi-directional pins)
I
N
P
2
3
4
VIH
VIL
IIL
IBL
2.0
U
T
S
0.8
V
15
50
µA
µA
0≤<V≤VDD See Note 1
5
6
7
8
9
Input Pin Capacitance
Output High Voltage
Output Low Voltage
High Impedance Leakage
Output Pin Capacitance
CI
VOH
VOL
IOZ
10
pF
V
V
µA
pF
O
U
T
P
2.4
IOH = 10mA
IOL = 10mA
0 < V < VDD See Note 1
0.4
5
10
U
T
S
CO
Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V)
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics
Sym.
Level
Units
Conditions
1
2
3
TTL Threshold
TTL Rise/Fall Threshold Voltage High
TTL Rise/Fall Threshold Voltage Low
VTT
VHM
VLM
1.5
2.0
0.8
V
V
V
26
Zarlink Semiconductor Inc.
MT90820
Data Sheet
AC Electrical Characteristics - Frame Pulse and CLK
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
WFPS Pin = 0
tFPW
1
Frame pulse width (ST-BUS, GCI)
Bit rate = 2.048 Mb/s
26
26
26
295
145
80
ns
ns
ns
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
tFPS
tFPH
tCP
2
3
4
Frame Pulse Setup time before CLK
falling (ST-BUS or GCI)
Frame Pulse Hold Time from CLK
falling (ST-BUS or GCI)
10
ns
WFPS Pin = 0
WFPS Pin = 0
16
ns
CLK Period
Bit rate = 2.048 Mb/s
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
190
110
55
300
150
70
ns
ns
ns
WFPS Pin = 0
WFPS Pin = 0
WFPS Pin = 0
tCH
5
6
CLK Pulse Width High
Bit rate = 2.048 Mb/s
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
CLK Pulse Width Low
Bit rate = 2.048 Mb/s
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
85
50
20
150
75
ns
ns
ns
40
tCL
85
50
20
150
75
ns
ns
ns
40
tr, tf
7
8
Clock Rise/Fall Time
Wide frame pulse width
Bit rate = 8.192 Mb/s
Frame Pulse Setup Time before
HCLK falling
10
295
ns
ns
tHFPW
195
10
WFPS Pin = 1
WFPS Pin = 1
WFPS Pin = 1
WFPS Pin = 1
WFPS Pin = 1
WFPS Pin = 1
tHFPS
tHFPH
tHCP
9
150
150
300
150
150
ns
ns
ns
ns
ns
10 Frame Pulse Hold Time from HCLK
falling
11 HCLK (4.096MHz) Period
Bit rate = 8.192 Mb/s
12 HCLK (4.096MHz) Pulse Width High
Bit rate = 8.192 Mb/s
13 HCLK (4.096MHz) Pulse Width Low
Bit rate = 8.192 Mb/s
20
190
85
tHCH
tHCL
85
tHr, tHf
tDIF
14 HCLK Rise/Fall Time
15 Delay between falling edge of HCLK
and falling edge of CLK
10
10
ns
ns
-10
WFPS Pin = 0 or 1
27
Zarlink Semiconductor Inc.
MT90820
Data Sheet
AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
tSIS
tSIH
tSOD
1
2
3
Sti Set-up Time
Sti Hold Time
Sto Delay - Active to Active
@ 2.048 Mb/s mode
@ 4.096 Mb/s mode
@ 8.192 Mb/s mode
@ 8.192 Mb/s mode
0
20
ns
ns
58
58
58
39
ns
ns
ns
ns
CL=200pF
CL=200pF
CL=200pF
CL=30pF
4
5
6
STo delay - Active to High-Z
2.048 Mb/s mode
tDZ
37
37
37
ns
ns
ns
RL=1K, CL=200pF, See Note 1
RL=1K, CL=200pF, See Note 1
RL=1K, CL=200pF, See Note 1
4.096 Mb/s mode
8.192 Mb/s mode
Sto delay - High-Z to Active
2.048 Mb/s mode
tZD
37
37
37
ns
ns
ns
RL=1K, CL=200pF, See Note 1
RL=1K, CL=200pF, See Note 1
RL=1K, CL=200pF, See Note 1
4.096 Mb/s mode
8.192 Mb/s mode
Output Driver Enable (ODE) Delay tODE
2.048 Mb/s mode
4.096 Mb/s mode
8.192 Mb/s mode
37
37
37
ns
ns
ns
RL=1K, CL=200pF, See Note 1
RL=1K, CL=200pF, See Note 1
RL=1K, CL=200pF, See Note 1
7
CSTo Output Delay
2.048 Mb/s mode
4.096 Mb/s mode
8.192 Mb/s mode
tXCD
58
58
58
ns
ns
ns
CL=200pF
CL=200pF
CL=200pF
Note 1: High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge
L
C .
L
28
Zarlink Semiconductor Inc.
MT90820
Data Sheet
tFPW
F0i
VTT
tCP
tCH
tFPS
tr
tFPH
tCL
VHM
VTT
CLK
VLM
tSOD
tf
Bit 0, Last Ch (Note1)
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
STo
VTT
tSIS
tSIH
STi
Bit 0, Last Ch (Note1)
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
VTT
Note 1:
2.048 Mb/s mode, last channel = ch 31,
4.196 Mb/s mode, last channel = ch 63,
8.192 Mb/s mode, last channel = ch 127.
Figure 10 - ST-BUS Timing for 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or
8.192 Mb/s, when WFPS pin = 0.
tFPW
F0i
VTT
tCP
tCH
tFPS
tFPH
tCL
tr
VHM
VTT
CLK
VLM
tSOD
tf
Bit 7, Last Ch (Note1)
Bit 0, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
Bit 2, Channel 0
STo
VTT
tSIS
tSIH
STi
Bit 7, Last Ch (Note1)
Bit 0, Channel 0
Bit 1, Channel 0
VTT
Note 1:
2Mb/s mode, last channel = ch 31,
4Mb/s mode, last channel = ch 63,
8Mb/s mode, last channel = ch 127
Figure 11 - GCI Timing at 2.048 Mb/s and High Speed Serial Interface at
4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0
29
Zarlink Semiconductor Inc.
MT90820
Data Sheet
tHFPW
tHFPS
tHFPH
VTT
F0i
tHCP
tHCH
tHCL
HCLK
4.096MHz
VHM
VTT
VLM
tDIF
tHf
tHr
tCP
tCH
tCL
tr
CLK
VTT
VTT
VTT
16.384MHz
tSOD
tf
Bit 1, Ch 127
Bit 0, Ch 127
Bit 0, Ch 127
Bit 7, Ch 0
Bit 6, Ch 0
Bit 5, Ch 0
Bit 4, Ch 0
STo
STi
tSIS
tSIH
Bit 1, Ch 127
Bit 7, Ch 0
Bit 6, Ch 0
Bit 5, Ch 0
Bit 4, Ch 0
Figure 12 - WFP Bus Timing for High Speed Serial Interface (8.192Mb/s), when WFPS pin = 1
Note 1: High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge
L
C .
L
CLK
VTT
(ST-BUS or)
(WFPS mode)
CLK
(GCI mode)
VTT
tDZ
VTT
VTT
VTT
HiZ
Valid Data
STo
STo
tZD
Valid Data
HiZ
tXCD
CSTo
Figure 13 - Serial Output and External Control
30
Zarlink Semiconductor Inc.
MT90820
Data Sheet
VTT
ODE
STo
tODE
tODE
VTT
Valid Data
HiZ
HiZ
Figure 14 - Output Driver Enable (ODE)
AC Electrical Characteristics - Multiplexed Bus Timing (Mode 1)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
4
5
6
7
8
9
ALE pulse width
tALW
tADS
tADH
tALRD
tDDR
tCSRW
tRW
20
10
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup from ALE falling
Address hold from ALE falling
RD active after ALE falling
Data setup from DTA Low on Read
CS hold after RD/WR
RD pulse width (fast read)
CS setup from RD
Data hold after RD
CL=150pF
80
90
tCSR
tDHR
0
10
75
CL=150pF, RL=1K,
Note 1.
10 WR pulse width (fast write)
11 WR delay after ALE falling
12 CS setup from WR
13 Data setup from WR (fast write)
14 Valid Data Delay on write (slow write)
15 Data hold after WR inactive
16 Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory, @ 2Mb/s
@ 4Mb/s
tWW
tALWR
tCSW
tDSW
tSWD
tDHW
tAKD
ns
ns
ns
ns
ns
ns
10
0
90
122
10
55/60
ns
ns
ns
ns
CL=150pF
CL=150pF
CL=150pF
CL=150pF
760/780
400/420
220/240
@ 8Mb/s
17 Acknowledgment Hold Time
tAKH
45
80
ns
CL=150pF, RL=1K,
Note 1.
Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge
CL.
31
Zarlink Semiconductor Inc.
MT90820
Data Sheet
tALW
VTT
ALE
tADS
tADH
AD0-AD7
D8-D15
VTT
HiZ
HiZ
HiZ
ADDRESS
tALRD
DATA
tCSRW
CS
RD
WR
VTT
tCSR
tRW
VTT
tDHR
tWW
VTT
tCSW
tDHW
tSWD
tDSW
tALWR
tDDR
tAKH
DTA
VTT
tAKD
Figure 15 - Multiplexed Bus Timing (Mode 1)
AC Electrical Characteristics - Multiplexed Bus Timing (Mode 2)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
4
5
6
7
8
9
AS pulse width
tASW
tADS
tADH
tDDR
tCSH
tCSS
tDHW
tDWS
tSWD
tRWS
tRWH
tDHR
80
10
10
10
0
0
10
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup from AS falling
Address hold from AS falling
Data setup from DTA Low on Read
CS hold after DS falling
CS setup from DS rising
Data hold after write
CL=150pF
Data setup from DS -Write (fast write)
Valid Data Delay on write (slow write)
122
75
10 R/W setup from DS rising
11 R/W hold after DS falling
12 Data hold after read
60
10
10
50
45
CL=150pF, RL=1K,
Note 1
13 DS delay after AS falling
tDSH
tAKD
10
ns
14 Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory, @ 2Mb/s
@ 4Mb/s
55/60
ns
ns
ns
ns
CL=150pF
CL=150pF
CL=150pF
CL=150pF
760/780
400/420
220/240
@ 8Mb/s
15 Acknowledgment Hold Time
tAKH
80
ns
C =150pF, RL=1K,
NLote 1
Note 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
32
Zarlink Semiconductor Inc.
MT90820
Data Sheet
DS
VTT
tRWS
tRWH
R/W
VTT
tDSH
tASW
VTT
AS
tADS
tADH
tDHW
tDWS
tSW
HiZ
AD0-AD7
D8-D15
WR
DATA
VTT
HiZ
HiZ
ADDRESS
tDHR
AD0-AD7
D8-D15
RD
DATA
VTT
HiZ
ADDRESS
tCSH
tCSS
VTT
CS
tAKH
tDDR
tAKD
DTA
VTT
Figure 16 - Multiplexed Bus Timing (Mode2)
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
4
5
6
7
8
CS setup from DS falling
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
tCSS
tRWS
tADS
tCSH
tRWH
tADH
tDDR
tDHR
0
10
2
0
5
5
0
10
ns
ns
ns
ns
ns
ns
ns
ns
CL=150pF
CL=150pF, RL=1K
Note 1
50
75
9
Data setup on write (fast write)
tDSW
tSWD
tDHW
tAKD
20
8
ns
ns
ns
10 Valid Data Delay on write (slow write)
11 Data hold on write
12 Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory, @ 2Mb/s
@ 4Mb/s
122
55/60
ns
ns
ns
ns
CL=150pF
CL=150pF
CL=150pF
CL=150pF
760/780
400/420
220/240
@ 8Mb/s
13 Acknowledgment Hold Time
tAKH
45
80
ns
C =150pF, RL=1K,
NLote 1
Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge
CL.
33
Zarlink Semiconductor Inc.
MT90820
Data Sheet
VTT
DS
CS
tCSH
tCSS
VTT
tRWH
tRWS
VTT
R/W
tADS
tADH
VTT
VALID ADDRESS
A0-A7
tDHR
VALID READ DATA
tDHW
VALID WRITE DATA
AD0-AD7
D8-D15
READ
VTT
tDSW
tSWD
AD0-AD7
D8-D15
VTT
WRITE
tDDR
VTT
DTA
tAKD
tAKH
Figure 17 - Motorola Non-Multiplexed Bus Timing
34
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
©2020 ICPDF网 联系我们和版权申明