MT9043ANR1_技术文档

MT9043

T1/E1 System Synchronizer

Data Sheet

September 2009

Features

•

Supports AT&T TR62411 and Bellcore GR-1244-

Ordering Information

CORE, Stratum 4 Enhanced and Stratum 4 timing

for DS1 interfaces

MT9043AN

48 pin SSOP

Tubes

Tape & Reel

Tubes

MT9043ANR 48 Pin SSOP

MT9043AN1 48 Pin SSOP*

MT9043ANR1 48 Pin SSOP*

•

Supports ETSI ETS 300 011, TBR 4, TBR 12 and

TBR 13 timing for E1 interfaces

Tape & Reel

*Pb Free Matte Tin

Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or

8 kHz input reference signals

-40°C to +85°C

Provides C1.5, C2, C4, C6, C8, C16, and C19

(STS-3/OC3 clock divided by 8) output clock

signals

Description

The MT9043 T1/E1 System Synchronizer contains a

digital phase-locked loop (DPLL), which provides timing

and synchronization signals for multitrunk T1 and E1

primary rate transmission links.

•

Provides 5 different styles of 8 KHz framing

pulses

•

Attenuates wander from 1.9 Hz

Fast lock mode

The MT9043 generates ST-BUS clock and framing

signals that are phase locked to either a 19.44 MHz,

2.048 MHz, 1.544 MHz, or 8 kHz input reference.

Provides Time Interval Error (TIE) correction

Accepts reference inputs from two independent

sources

The MT9043 is compliant with AT&T TR62411 and

Bellcore GR-1244-CORE, Stratum 4 Enhanced, and

Stratum 4; and ETSI ETS 300 011. It will meet the

jitter/wander tolerance, jitter transfer, intrinsic jitter,

frequency accuracy, capture range, phase change

slope, and MTIE requirements for these specifications.

•

JTAG Boundary Scan

Applications

•

Synchronization and timing control for multitrunk

T1,E1 and STS-3/OC3 systems

•

ST-BUS clock and frame pulse sources

TCLR

OSCi

OSCo

LOCK

VDD

VSS

Virtual

Reference

Master Clock

C19o

C1.5o

C2o

C4o

C6o

C8o

C16o

F0o

F8o

F16o

RSP

TIE

Corrector

Circuit

TCK

DPLL

TDI

TMS

TRST

TDO

IEEE

1149.1a

Output

Interface

Circuit

Selected

State

Select

Reference

Select

PRI

SEC

Input

Impairment

Monitor

MUX

TIE

Corrector

Enable

State

Select

TSP

Reference

Select

Frequency

Select

MUX

RSEL

Control State Machine

Feedback

IM

MS

FLOCK

FS1

FS2

RST

Figure 1 - Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

1

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT9043

Data Sheet

Change Summary

Below are the changes from the February 2005 issue.

Page

Item

Description

2

Pin Description

Corrected pin name from RST to RSP.

V_SS

1

2

3

4

5

6

7

8

9

48

47

46

45

TMS

TCK

TRST

TDI

TDO

IC

FS1

FS2

IC

RSEL

IC

RST

TCLR

IC

SEC

PRI

Vdd

OSCo

OSCi

Vss

F16o

F0o

RSP

TSP

F8o

C1.5o

Vdd

LOCK

C2o

C4o

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

10 MT9043AN

11

12

13

14

15

16

17

18

19

20

21

22

23

24

MS

Vdd

IC

NC

Vss

IC

IM

Vdd

C6o

C16o

C8o

C19o

FLOCK

Vss

IC

Figure 2 - Pin Connections

Description

Pin Description

Pin #

Name

1,10,

V_SS

Ground. 0 Volts. (Vss pads).

23,31

2

RST

Reset (Input). A logic low at this input resets the MT9043. To ensure proper operation, the

device must be reset after reference signal frequency changes and power-up. The RST

pin should be held low for a minimum of 300 ns. While the RST pin is low, all frame pulses

except RSP and TSP and all clock outputs except C6o, C16o and C19o are at logic high.

The RSP, TSP, C6o and C16o are at logic low during reset. The C19o is free-running

during reset. Following a reset, the input reference source and output clocks and frame

pulses are phase aligned as shown in Figure 12.

3

4

TCLR TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)

correction circuit resulting in a realignment of input phase with output phase as shown in

Figure 13. The TCLR pin should be held low for a minimum of 300 ns. This pin is internally

pulled down to VSS.

IC

Internal Connection. Leave open circuit.

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Zarlink Semiconductor Inc.

MT9043

Data Sheet

Pin Description

Pin #

Name

Description

5

SEC

Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources

(falling edge) used for synchronization. One of four possible frequencies (8 kHz, 1.544 MHz,

2.048 MHz or 19.44 MHz) may be used. The selection of the input reference is based upon

the MS, and RSEL, control inputs.This pin is internally pulled up to V_DD

.

6

PRI

V_DD

Primary Reference (Input). See pin description for SEC. This pin is internally pulled up to

V_DD

.

7,17

Positive Supply Voltage. +3.3V_DCnominal.

28,35

8

OSCo Oscillator Master Clock (CMOS Output). For crystal operation, a 20 MHz crystal is

connected from this pin to OSCi, see Figure 9. Not suitable for driving other devices. For

clock oscillator operation, this pin is left unconnected, see Figure 8.

9

OSCi

F16o

F0o

Oscillator Master Clock (CMOS Input). For crystal operation, a 20 MHz crystal is

connected from this pin to OSCo, see Figure 9. For clock oscillator operation, this pin is

connected to a clock source, see Figure 8.

11

12

13

14

15

Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8 kHz 61 ns active low

framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-

BUS operation at 8.192 Mb/s. See Figure 14.

Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output). This is an 8 kHz 244 ns active low

framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-

BUS operation at 2.048 Mb/s and 4.096 Mb/s. See Figure 14.

RSP

TSP

F8o

Receive Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high framing pulse,

which marks the beginning of an ST-BUS frame. This is typically used for connection to the

Siemens MUNICH-32 device. See Figure 15.

Transmit Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high framing pulse,

which marks the beginning of an ST-BUS frame. This is typically used for connection to the

Siemens MUNICH-32 device. See Figure 15.

Frame Pulse (CMOS Output). This is an 8 kHz 122 ns active high framing pulse, which

marks the beginning of a frame. See Figure 14.

16

18

C1.5o Clock 1.544 MHz (CMOS Output). This output is used in T1 applications.

LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to

the input reference.

19

20

C2o

C4o

Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s.

Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s

and 4.096 Mb/s.

21

22

C19o

Clock 19.44 MHz (CMOS Output). This output is used in OC3/STS3 applications.

FLOCK Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference (less

than 500 ms locking time).

24

25

26

IC

Internal Connection. Tie low for normal operation.

C8o

C16o

Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at 8.192 Mb/s.

Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation with a

16.384 MHz clock.

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Zarlink Semiconductor Inc.

MT9043

Data Sheet

Pin Description

Pin #

Name

Description

Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.

27

29

C6o

IM

Impairment Monitor (CMOS Output). A logic high on this pin indicates that the Input

Impairment Monitor has automatically put the device into Freerun Mode.

30

32

IC

NC

IC

Internal Connection. Tie high for normal operation.

No Connection. Leave open circuit.

33,34

36

Internal Connection. Tie low for normal operation.

MS

Mode/Control Select (Input). This input determines the state (Normal or Freerun) of

operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3.

37

38

IC

Internal Connection. Tie low for normal operation.

RSEL Reference Source Select (Input). A logic low selects the PRI (primary) reference source as

the input reference signal and a logic high selects the SEC (secondary) input. The logic level

at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled

down to VSS.

39

40

IC

Internal Connection. Tie low for normal operation.

FS2

Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four

possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI

and SEC inputs. See Table 1.

41

42

43

44

FS1

IC

Frequency Select 1 (Input). See pin description for FS2.

Internal Connection. Tie Low for Normal Operation.

Internal Connection. Leave Open Circuit.

IC

TDO

Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling

edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.

45

46

47

48

TDI

TRST

TCK

Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin.

This pin is internally pulled up to V_DD

.

Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the

Test-Logic-Reset state. If not used, this pin should be held low.

Test Clock (Input). Provides the clock to the JTAG test logic. This pin is internally pulled up

to V_DD

.

TMS

Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP

controller. This pin is internally pulled up to V_DD

.

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Zarlink Semiconductor Inc.

MT9043

Data Sheet

Functional Description

The MT9043 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to

interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which

is described in the following sections.

Reference Select MUX Circuit

The MT9043 accepts two simultaneous reference input signals and operates on their falling edges. Either the

primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE

Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1

and Table 4.

Frequency Select MUX Circuit

The MT9043 operates with one of four possible input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz or

19.44 MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used at

the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST)

must be performed after every frequency select input change. See Table 1.

FS2

FS1

Input Frequency

0

1

0

1

0

1

19.44 MHz

8 kHz

1.544 MHz

2.048 MHz

Table 1 - Input Frequency Selection

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Zarlink Semiconductor Inc.

MT9043

Data Sheet

Time Interval Error (TIE) Corrector Circuit

The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or

SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.

During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary

reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL

would lead to unacceptable phase changes in the output signal.

As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the

signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is

input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.

TCLR

Resets Delay

Control

Circuit

Control Signal

Delay Value

Programmable

Delay Circuit

Virtual

Reference

to DPLL

PRI or SEC

from

Reference

Select Mux

Compare

Circuit

TIE Corrector

Enable

Feedback

Signal from

Frequency

Select MUX

from

State Machine

Figure 3 - TIE Corrector Circuit

During a switch from one reference to the other, the State Machine first changes the mode of the device

from Normal to Freerun. The Compare Circuit then measures the phase delay between the current phase

(feedback signal) and the phase of the new reference signal. This delay value is passed to the Programmable

Delay Circuit (See Figure 3). The state machine then returns the device to Normal Mode and the DPLL begins

using the new virtual reference signal. The difference between the phase position of the new virtual reference and

the previous reference is less than 1 μs.

Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual

reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.

This phase error is a function of the difference in phase between the two input reference signals during reference

rearrangements. Each time a reference switch is made, the delay between input signal and output signal will

change. The value of this delay is the accumulation of the error measured during each reference switch.

The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TCLR) pin. A

minimum reset pulse width is 300 ns. This results in a phase alignment between the input reference signal and the

output signal as shown in Figure 13. The speed of the phase alignment correction is limited to 5 ns per 125 us, and

convergence is in the direction of least phase travel.

The state diagram of Figure 7 indicates the state changes during which the TIE corrector circuit is activated.

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Zarlink Semiconductor Inc.

MT9043

Data Sheet

Digital Phase Lock Loop (DPLL)

As shown in Figure 4, the DPLL of the MT9043 consists of a Phase Detector, Limiter, Loop Filter, Digitally

Controlled Oscillator, and a Control Circuit.

Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the

feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase

difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the

proper feedback signal to be externally selected (e.g., 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz).

Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all

input transient conditions with a maximum output phase slope of 5 ns per 125 us. This is well within the maximum

phase slope of 7.6 ns per 125 us or 81 ns per 1.326 ms specified by AT&T TR62411 and Bellcore GR-1244-CORE,

respectively.

Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four

reference frequency selections (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). This filter ensures that the jitter

transfer requirements in ETS 300 011 and AT&T TR62411 are met.

Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input

Impairment Circuit to set the mode of the DPLL. The two possible modes are Normal and Freerun.

Virtual Reference

from

TIE Corrector

DPLL Reference

to

Output Interface Circuit

Phase

Detector

Digitally

Controlled

Oscillator

Limiter

Loop Filter

State Select

from

Input Impairment Monitor

Control

Circuit

Feedback Signal

from

Frequency Select MUX

State Select

from

State Machine

Figure 4 - DPLL Block Diagram

Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and

based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is

dependent on the state of the MT9043.

In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input

reference signal.

In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.

Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to

the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then

the lock signal will be set high. For specific Lock Indicator design recommendations see the Applications - Lock

Indicator section.

Output Interface Circuit

The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure

5. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,

and a DS2 Divider Circuit to generate the required output signals.

Four tapped delay lines are used to generate 16.384 MHz, 12.352 MHz, 12.624 MHz and 19.44 MHz signals.

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Zarlink Semiconductor Inc.

MT9043

Data Sheet

The E1 Divider Circuit uses the 16.384 MHz signal to generate four clock outputs and five frame pulse outputs. The

C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.

These outputs have a nominal 50% duty cycle.

The T1 Divider Circuit uses the 12.384 MHz signal to generate the C1.5o clock by dividing the internal C12 clock

by eight. This output has a nominal 50% duty cycle.

The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal

50% duty cycle.

T1 Divider

C1.5o

12 MHz

Tapped

Delay

Line

C2o

E1 Divider

C4o

C8o

C16o

F0o

Tapped

Delay

Line

16 MHz

From

DPLL

F8o

F16o

RSP

TSP

Tapped

Delay

Line

C6o

12 MHz

19 MHz

DS2 Divider

Tapped

Delay

Line

C19o

Figure 5 - Output Interface Circuit Block Diagram

The frame pulse outputs (F0o, F8o, F16o, TSP, and RSP) are generated directly from the C16 clock.

The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulse and clock outputs

are locked to one another for all operating states, and are also locked to the selected input reference in Normal

Mode. See Figures 14 & 15.

All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high

capacitance (e.g., 30 pF) loads.

Input Impairment Monitor

This circuit monitors the input signal to the DPLL for a complete loss of incoming signal, or a large frequency shift in

the incoming signal. If the input signal is outside the Impairment Monitor Capture Range the PLL automatically

changes from Normal Mode to Free Run Mode. See AC Electrical Characteristics - Performance for the Impairment

Monitor Capture Range. When the incoming signal returns to normal, the DPLL is returned to Normal Mode.

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Zarlink Semiconductor Inc.

MT9043

Data Sheet

State Machine Control

As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit and the

DPLL. Control is based on the logic levels at the control inputs RSEL and MS (See Figure 6).

All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation

section for full details.

To

To TIE

Corrector

Enable

To DPLL

State

Select

Reference

Select MUX

Control

State Machine

RSEL

MS

Figure 6 - Control State Machine Block Diagram

Master Clock

The MT9043 can use either a clock or crystal as the master timing source. For recommended master timing

circuits, see the Applications - Master Clock section.

Control and Mode of Operation

The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2.

RSEL

Input Reference

0

1

PRI

SEC

Table 2 - Input Reference Selection

MS

Mode

0

1

NORMAL

FREERUN

Table 3 - Operating Modes and States

The MT9043 has two possible modes of operation, Normal and Freerun.

As shown in Table 3, the Mode/Control Select pin MS selects the mode. Refer to Table 4 and Figure 7 for details of

the state change sequences.

Normal Mode

Normal Mode is typically used when a slave clock source, synchronized to the network is required.

In Normal Mode, the MT9043 provides timing (C1.5o, C2o, C4o, C8o, C16o and C19o) and frame synchronization

(F0o, F8o, F16o, TSP and RSP) signals, which are synchronized to one of two reference inputs (PRI or SEC). The

input reference signal may have a nominal frequency of 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz.

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Zarlink Semiconductor Inc.

MT9043

Data Sheet

From a reset condition, the MT9043 will take up to 30 seconds (see AC Electrical Characteristics) of input reference

signal to output signals which are synchronized (phase locked) to the reference input.

The selection of input references is control dependent as shown in state table 4. The reference frequencies are

selected by the frequency control pins FS2 and FS1 as shown in Table 1.

Fast Lock Mode

Fast Lock Mode is a submode of Normal Mode, it is used to allow the MT9043 to lock to a reference more quickly

than Normal mode will allow. Typically, the PLL will lock to the incoming reference within 500 ms if the FLOCK pin is

set high.

Freerun Mode

Freerun Mode is typically used when a master clock source is required, or immediately following system power-up

before network synchronization is achieved.

In Freerun Mode, the MT9043 provides timing and synchronization signals which are based on the master clock

frequency (OSCi) only, and are not synchronized to the reference signals (PRI and SEC).

The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32 ppm output clock

is required, the master clock must also be ±32 ppm. See Applications - Crystal and Clock Oscillator sections.

MT9043 Measures of Performance

The following are some synchronizer performance indicators and their corresponding definitions.

Intrinsic Jitter

Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by

applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may

also be measured when the device is free running by measuring the output jitter of the device. Intrinsic jitter is

usually measured with various band limiting filters depending on the applicable standards. In the MT9043, the

intrinsic Jitter is limited to less than 0.02 UI on the 2.048 MHz and 1.544 MHz clocks.

Jitter Tolerance

Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the

presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied

jitter magnitude and jitter frequency depends on the applicable standards.

Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter

at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured

with various filters depending on the applicable standards.

For the MT9043, two internal elements determine the jitter attenuation. This includes the internal 1.9 Hz low pass

loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5 ns/125 us.

Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the

maximum output phase slope will be limited (i.e., attenuated) to 5 ns/125 us.

The MT9043 has twelve outputs with three possible input frequencies (except for 19.44 MHz, which is internally

divided to 8 KHz) for a total of 36 possible jitter transfer functions. Since all outputs are derived from the same

signal, the jitter transfer values for the four cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz and 2.048 MHz to

2.048 MHz can be applied to all outputs.

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Zarlink Semiconductor Inc.

MT9043

Data Sheet

It should be noted that 1 UI at 1.544 MHz is 644 ns, which is not equal to 1 UI at 2.048 MHz, which is 488 ns.

Consequently, a transfer value using different input and output frequencies must be calculated in common units

(e.g., seconds) as shown in the following example.

What is the T1 and E1 output jitter when the T1 input jitter is 20 UI (T1 UI Units) and the T1 to T1 jitter attenuation is

18 dB?

–A

20

⎛

⎝

⎞

⎠

------

OutputT1 = InputT1×10

–18

20

⎛

⎝

⎞

⎠

--------

OutputT1 = 20×10

= 2.5UI(T1)

(1UIT1)

(1UIE1)

---------------------

OutputE1 = OutputT1 ×

(644ns)

(488ns)

-------------------

OutputE1 = OutputT1 ×

= 3.3UI(T1)

Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on

the three jitter transfer functions provided.

Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, 2.048MHz) and

outputs (8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz) for a given input signal

(jitter frequency and jitter amplitude) are the same.

Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for

large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter

signals (e.g., 75% of the specified maximum jitter tolerance).

Frequency Accuracy

Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an

external reference, but is operating in a free running mode. For the MT9043, the Freerun accuracy is equal to the

Master Clock (OSCi) accuracy.

Capture Range

Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull

into synchronization. The MT9043 capture range is equal to ±230 ppm minus the accuracy of the master clock

(OSCi). For example, a 32 ppm master clock results in a capture range of 198 ppm.

Lock Range

This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock

range is equal to the capture range for the MT9043.

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Zarlink Semiconductor Inc.

MT9043

Data Sheet

Phase Slope

Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect

to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is

nominally equal to the value of the final output signal or final input signal.

Time Interval Error (TIE)

TIE is the time delay between a given timing signal and an ideal timing signal.

Maximum Time Interval Error (MTIE)

MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a

particular observation period.

MTIE(S)= TIEmax(t) – TIEmin(t)

Phase Continuity

Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a

particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.

Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a

mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has

settled to a steady state.

In the case of the MT9043, the output signal phase continuity is maintained to within ±5 ns at the instance (over

one frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or type

of mode change, may accumulate up to 200 ns over many frames. The rate of change of the 200 ns phase shift is

limited to a maximum phase slope of approximately 5 ns/125 us. This meets the AT&T TR62411 maximum phase

slope requirement of 7.6 ns/125 us and Bellcore GR-1244-CORE (81 ns/1.326 ms).

Phase Lock Time

This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal

and output signal are not changing in phase with respect to each other (not including jitter).

Lock time is very difficult to determine because it is affected by many factors which include:

•

initial input to output phase difference

initial input to output frequency difference

synchronizer loop filter

synchronizer limiter

Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.

For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock

time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9043 loop filter and

limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently,

phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical

Characteristics - Performance for Maximum Phase Lock Time.

MT9043 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming reference

within approximately 500 ms.

12

Zarlink Semiconductor Inc.

MT9043

Data Sheet

Description

State

Normal (PRI)

S1

Input Controls

Freerun

Normal (SEC)

MS

RSEL

S0

S2

0

1

0

1

X

S1

S2

-

S1 MTIE

S2 MTIE

S0

-

S0

Legend:

-

No Change

State change occurs with TIE Corrector Circuit

MTIE

Refer to Control State Diagram for state changes to and from Auto-Freerun State

Table 4 - Control State Table

S0

Freerun

(1X)

S1

S1A

S2A

Auto-Freerun

Secondary

(01)

S2

Normal

Secondary

(01)

{A}

Normal

Primary

(00)

Auto-Freerun

Primary

(00)

NOTES:

(XX)

MS RSEL

Invalid Reference Signal

Phase Re-Alignment

{A}

Phase Continuity Maintained (without TIE Corrector Circuit)

Phase Continuity Maintained (with TIE Corrector Circuit)

Movement to Normal State from any

state requires a valid input signal

Figure 7 - Control State Diagram

MT9043 and Network Specifications

The MT9043 fully meets all applicable PLL requirements (intrinsic jitter, jitter/wander tolerance, jitter/wander

transfer, frequency accuracy, capture range, phase change slope and MTIE during reference rearrangement) for

the following specifications.

1. Bellcore GR-1244-CORE June 1995 for, Stratum 4 Enhanced and Stratum 4

2. AT&T TR62411 (DS1) December 1990 for, Stratum 4 Enhanced and Stratum 4

3. ANSI T1.101 (DS1) February 1994 for Stratum 4 Enhanced and Stratum 4

4. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access

13

Zarlink Semiconductor Inc.

MT9043

Data Sheet

5. TBR 4 November 1995

6. TBR 12 December 1993

7. TBR 13 January 1996

8. ITU-T I.431 March 1993

Applications

This section contains MT9043 application specific details for clock and crystal operation, reset operation, power

supply de coupling, and control operation.

Master Clock

The MT9043 can use either a clock or crystal as the master timing source.

In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source

at the OSCi pin. For applications not requiring an accurate Freerun Mode, tolerance of the master timing source

may be ±100 ppm. For applications requiring an accurate Freerun Mode, such as AT&T TR62411, the tolerance of

the master timing source must be no greater than ±32 ppm.

Another consideration in determining the accuracy of the master timing source is the desired capture range. The

sum of the accuracy of the master timing source and the capture range of the MT9043 will always equal 230 ppm.

For example, if the master timing source is 100 ppm, then the capture range will be 130 ppm.

Clock Oscillator - when selecting a Clock Oscillator, numerous parameters must be considered. This includes

absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.

MT9043

+3.3 V

OSCi

+3.3 V

20 MHz OUT

GND

0.1 uF

OSCo

No Connection

Figure 8 - Clock Oscillator Circuit

For applications requiring ±32 ppm clock accuracy, the following clock oscillator module may be used.

FOX F7C-2E3-20.0 MHz

Frequency:

20 MHz

Tolerance:

25 ppm 0C to 70C

10 ns (0.33 V 2.97 V 15 pF)

40% to 60%

Rise & Fall Time:

Duty Cycle:

CTS CB3LV-5I-20.0 MHz

Frequency:

20 MHz

25 ppm

10 ns

Tolerance:

Rise & Fall Time:

Duty Cycle:

45% to 55%

14

Zarlink Semiconductor Inc.

MT9043

Data Sheet

The output clock should be connected directly (not AC coupled) to the OSCi input of the MT9043, and the OSCo

output should be left open as shown in Figure 8.

Crystal Oscillator - Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a

crystal, resistor and capacitors is shown in Figure 9.

MT9043

OSCi

20 MHz

1MΩ

56 pF

39 pF

3-50 pF

OSCo

100 Ω

1 uH

1uH inductor: may improve stability and is optional

Figure 9 - Crystal Oscillator Circuit

The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance.

Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance

contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances, and stray

capacitances have a major effect on the accuracy of the oscillator frequency.

The trimmer capacitor shown in Figure 9 may be used to compensate for capacitive effects. If accuracy is not a

concern, then the trimmer may be removed, the 39 pF capacitor may be increased to 56 pF, and a wider tolerance

crystal may be substituted.

The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler

oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal

specification is as follows.

Frequency:

20 MHz

As required

Fundamental

Parallel

32 pF

Tolerance:

Oscillation Mode:

Resonance Mode:

Load Capacitance:

Maximum Series Resistance:

Approximate Drive Level:

e.g., R1B23B32-20.0 MHz

35 Ω

1 mW

^{(20ppm absolute,}±6 ppm 0C to 50C, 32 pF, 25 Ω)

Reset Circuit

A simple power up reset circuit with about a 50 us reset low time is shown in Figure 10. Resistor R_Pis for protection

only and limits current into the RST pin during power down conditions. The reset low time is not critical but should

be greater than 300 ns.

15

Zarlink Semiconductor Inc.

MT9043

Data Sheet

MT9043

+3.3 V

R

10 kΩ

RST

R_P

1 kΩ

C

10 nF

Figure 10 - Power-Up Reset Circuit

Lock Indicator

The LOCK pin toggles at a random rate when the PLL is frequency locked to the input reference. In Figure 11 the

RC-time-constant circuit can be used to hold the high state of the LOCK pin.

Once the PLL is frequency locked to the input reference, the minimum duration of LOCK pin’s high state would be

32ms and the maximum duration of LOCK pin’s low state would not exceed 1 second. The following equations can

be used to calculate the charge and discharge times of the capacitor.

t_C= - R_DC ln(1 – V_T+/V_DD) = 240 μs

t_C= Capacitor’s charge time

R_D= Dynamic resistance of the diode (100 Ω)

C = Capacitor value (1 μF)

V

_T+= Positive going threshold voltage of the

Schmitt Trigger (3.0 V)

V_DD= 3.3 V

t_D= - R C ln(V_T-/V_DD) = 1.65 seconds

t_D= Capacitor’s discharge time

R = Resistor value (3.3 MΩ)

C = Capacitor value (1 μF)

V

_T-= Negative going threshold voltage of the

Schmitt Trigger (2.0 V)

V_DD= 3.3 V

16

Zarlink Semiconductor Inc.

MT9043

Data Sheet

MT9043

R=3.3M

74HC14

LOCK

Lock

IN4148

+

C=1 μf

Figure 11 - Time-constant Circuit

A digital alternative to the RC-time-constant circuit is presented in Figure 12. The circuit in Figure 12 can be used to

generate a steady lock signal. The circuit monitors the MT9043’s LOCK pin, as long as it detects a positive pulse

every 1.024 seconds or less, the Advanced Lock output will remain high. If no positive pulse is detected on the

LOCK output within 1.024 seconds, the Advanced LOCK output will go low.

MT9043

Figure 12 - Digital Lock Pin Circuit

17

Zarlink Semiconductor Inc.

MT9043

Data Sheet

Absolute Maximum Ratings* - Voltages are with respect to ground (V_SS) unless otherwise stated.

Parameter

Symbol

Min.

Max.

Units

1

2

3

4

5

Supply voltage

V_DD

V_PIN

I_PIN

T_ST

-0.3

7.0

V

Voltage on any pin

Current on any pin

Storage temperature

V_DD+ 0.3

30

V

mA

°C

-55

125

48 SSOP package power dissipation

P_PD

200

mW

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to ground (V_SS) unless otherwise stated.

Characteristics

Supply voltage

Operating temperature

Sym.

Min.

Max.

Units

1

2

V_DD

T_A

3.0

-40

3.6

85

V

°C

DC Electrical Characteristics* - Voltages are with respect to ground (V_SS) unless otherwise stated.

Characteristics

Supply current with: OSCi = 0 V

OSCi = Clock

Sym.

Min.

Max.

Units

Conditions/Notes

1

2

3

4

5

6

7

I_DDS

I_DD

1.8

50

mA

V

Outputs unloaded

CMOS high-level input voltage

CMOS low-level input voltage

Input leakage current

V_CIH

V_CIL

I_IL

0.7V_DD

0.3V_DD

15

V

μA

V

V_I=V_DDor 0 V

I_OH= 10 mA

I_OL= 10 mA

High-level output voltage

V_OH

2.4

Low-level output voltage

V_OL

0.4

V

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

18

Zarlink Semiconductor Inc.

MT9043

Data Sheet

AC Electrical Characteristics - Performance

Conditions/

Notes†

Characteristics

Sym.

Min. Max. Units

1

2

Freerun Mode accuracy with OSCi at: ±0 ppm

-0

+0

ppm 4-8

±32 ppm

±100 ppm

±0 ppm

-32

+32

ppm 4-8

3

-100 +100

-230 +230

-198 +198

-130 +130

30

ppm 4-8

4

Capture range with OSCi at:

ppm 1-3,5-8

5

±32 ppm

6

±100 ppm

7

Phase lock time

s

ns

1-3,5-14

1-2,4-14

1-3,5-14

1-14,27

8

Output phase continuity with:

reference switch

200

9

mode switch to Normal

mode switch to Freerun

200

ns

10

200

ns

11 MTIE (maximum time interval error)

12 Output phase slope

600

ns

45

us/s

13 Impairment Monitor Capture Range at: 8 kHz, 19.44 MHz

-30k +30k

ppm 1-3,5,8,9-11

ppm 1-3,6,9-11

ppm 1-3,7,9-11

14

1.544 MHz

2.048 MHz

15

† See “Notes” following AC Electrical Characteristics tables.

AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - Voltages are

with respect to ground (V_SS) unless otherwise stated

Characteristics

Sym.

CMOS

Units

1

2

3

Threshold Voltage

V_T

0.5V_DD

0.7V_DD

0.3V_DD

V

Rise and Fall Threshold Voltage High

Rise and Fall Threshold Voltage Low

V_HM

V_LM

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

* Timing for input and output signals is based on the worst case result of the CMOS thresholds.

* See Figure 10.

Timing Reference Points

V_HM

V_T

V_LM

ALL SIGNALS

t

_IRF,t_ORF

t_IRF,t_ORF

Figure 13 - Timing Parameter Measurement Voltage Levels

19

Zarlink Semiconductor Inc.

MT9043

Data Sheet

AC Electrical Characteristics - Input/Output Timing

Characteristics

Sym.

Min.

Max.

Units

1

Reference input pulse width high or low

Reference input rise or fall time

8 kHz reference input to F8o delay

1.544 MHz reference input to F8o delay

2.048 MHz reference input to F8o delay

19.44 MHz reference input to F8o delay

F8o to F0o delay

t_RW

t_IRF

100

ns

2

10

6

3

t_R8D

-21

337

222

46

4

t_R15D

t_R2D

t_R19D

t_F0D

363

238

57

130

40

10

-25

10

5

6

7

111

25

8

F16o setup to C16o falling

F16o hold to C16o rising

F8o to C1.5o delay

t_F16S

t_F16H

t_C15D

t_C6D

9

-10

-45

-10

-11

-6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

F8o to C6o delay

F8o to C2o delay

t_C2D

F8o to C4o delay

t_C4D

5

F8o to C8o delay

t_C8D

5

F8o to C16o delay

t_C16D

t_TSPD

t_RSPD

t_C19D

t_C15W

t_C6W

t_C2W

t_C4W

t_C8W

t_C16WL

t_TSPW

t_RSPW

t_C19WH

t_C19WL

t_F0WL

t_F8WH

t_F16WL

t_ORF

5

F8o to TSP delay

10

8

F8o to RSP delay

-8

F8o to C19o delay

-15

309

70

5

C1.5o pulse width high or low

C6o pulse width high or low

C2o pulse width high or low

C4o pulse width high or low

C8o pulse width high or low

C16o pulse width high or low

TSP pulse width high

339

86

258

133

70

35

494

491

35

25

254

135

75

9

230

111

52

24

478

474

25

RSP pulse width high

C19o pulse width high

C19o pulse width low

17

F0o pulse width low

234

109

47

F8o pulse width high

F16o pulse width low

Output clock and frame pulse rise or fall time

Input Controls Setup Time

Input Controls Hold Time

t_S

100

t_H

20

Zarlink Semiconductor Inc.

MT9043

Data Sheet

t

R8D

PRI/SEC

8 kHz

t

RW

V

T

t

R15D

t

PRI/SEC

RW

1.544 MHz

V

T

t

R2D

t

PRI/SEC

RW

2.04 8MHz

V

t_R19D

t_RW

PRI/SEC

19.44 MHz

T

F8o

V

T

NOTES:

1. Input to output delay values

are valid after a TCLR or RST

with no further state changes

Figure 14 - Input to Output Timing (Normal Mode)

21

Zarlink Semiconductor Inc.

MT9043

Data Sheet

t

F8WH

V

T

F8o

F0o

t

F0D

t

F0WL

V

T

t

F16WL

t

V

T

F16o

t

F16H

F16S

t

C16WL

t_C16D

V

T

C16o

C8o

t

C8W

t

C8D

V

T

t

C4W

t

C4D

V

T

C4o

C2o

t

C2D

C2W

V

T

t

C6W

t

C6D

C6W

V

T

C6o

C1.5o

C19o

t

C15D

C15W

V

T

t

C19WH

t

C19D

t

C19WL

V

T

Figure 14 - Output Timing 1

22

Zarlink Semiconductor Inc.

MT9043

Data Sheet

F8o

C2o

V

T

V

T

t_RSPD

V

T

RSP

TSP

t

RSPW

TSPW

V

T

t

TSPD

Figure 15 - Output Timing 2

V

T

F8o

t

H

S

MS1,2,

RSEL,

PCCi

V

T

Figure 16 - Input Controls Setup and Hold Timing

AC Electrical Characteristics - Intrinsic Jitter Unfiltered

Characteristics

Sym.

Max.

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Intrinsic jitter at F8o (8 kHz)

0.0002

0.030

0.040

0.120

0.080

0.104

0.0002

0.27

UIpp

1-14,21-24,28

1-14,21-24,29

1-14,21-24,30

1-14,21-24,31

1-14,21-24,32

1-14,21-24,33

1-14,21-24,34

1-14,21-24,35

Intrinsic jitter at F0o (8 kHz)

Intrinsic jitter at F16o (8 kHz)

Intrinsic jitter at C1.5o (1.544 MHz)

Intrinsic jitter at C2o (2.048 MHz)

Intrinsic jitter at C6o (6.312 MHz)

Intrinsic jitter at C4o (4.096 MHz)

Intrinsic jitter at C8o (8.192 MHz)

Intrinsic jitter at C16o (16.384 MHz)

10 Intrinsic jitter at TSP (8 kHz)

11 Intrinsic jitter at RSP (8 kHz)

12 Intrinsic jitter at C19o (19.44 MHz)

† See “Notes” following AC Electrical Characteristics tables.

23

Zarlink Semiconductor Inc.

MT9043

Data Sheet

AC Electrical Characteristics - C1.5o (1.544 MHz) Intrinsic Jitter Filtered

Characteristics

Sym.

Min.

Max.

Units

Conditions/Notes†

1

2

3

4

Intrinsic jitter (4 Hz to 100 kHz filter)

Intrinsic jitter (10 Hz to 40 kHz filter)

Intrinsic jitter (8 kHz to 40 kHz filter)

Intrinsic jitter (10 Hz to 8 kHz filter)

0.015

0.010

0.005

UIpp

1-14,21-24,29

† See “Notes” following AC Electrical Characteristics tables.

AC Electrical Characteristics - C2o (2.048 MHz) Intrinsic Jitter Filtered

Characteristics

Sym.

Min.

Max.

Units

Conditions/Notes†

1

2

3

4

Intrinsic jitter (4 Hz to 100 kHz filter)

Intrinsic jitter (10 Hz to 40 kHz filter)

Intrinsic jitter (8 kHz to 40 kHz filter)

Intrinsic jitter (10 Hz to 8 kHz filter)

0.015

0.010

0.005

UIpp

1-14,21-24,30

† See “Notes” following AC Electrical Characteristics tables.

AC Electrical Characteristics - 8 kHz Input to 8 kHz Output Jitter Transfer

Characteristics

Sym. Min. Max. Units

Conditions/Notes†

1

2

3

4

5

6

Jitter attenuation for 1 Hz@0.01 UIpp input

0

6

dB

1-3, 5, 9-14,

21-22, 24, 28, 36

Jitter attenuation for 1 Hz@0.54 UIpp input

Jitter attenuation for 10 Hz@0.10 UIpp input

Jitter attenuation for 60 Hz@0.10 UIpp input

Jitter attenuation for 300 Hz@0.10 UIpp input

6

16

22

38

1-3, 5, 9-14,

21-22, 24, 28, 36

12

28

42

45

1-3, 5, 9-14,

21-22, 24, 28, 36

1-3, 5, 9-14,

21-22, 24, 28, 36

1-3, 5, 9-14,

21-22, 24, 28, 36

Jitter attenuation for 3600 Hz@0.005 UIpp

input

1-3, 5, 9-14,

21-22, 24, 28, 36

† See “Notes” following AC Electrical Characteristics tables.

24

Zarlink Semiconductor Inc.

MT9043

Data Sheet

AC Electrical Characteristics - 1.544 MHz Input to 1.544 MHz Output Jitter Transfer

Characteristics

Sym Min Max Units

Conditions/Notes†

1-3,6,9-14,

1

2

3

4

5

6

7

Jitter attenuation for 1 Hz@20 UIpp input

0

6

dB

21-22,24,29,36

Jitter attenuation for 1 Hz@104 UIpp input

Jitter attenuation for 10 Hz@20 UIpp input

Jitter attenuation for 60 Hz@20 UIpp input

Jitter attenuation for 300 Hz@20 UIpp input

Jitter attenuation for 10 kHz@0.3 UIpp input

Jitter attenuation for 100 kHz@0.3 UIpp input

6

16

22

38

1-3,6,9-14,

21-22,24,29,36

12

28

42

45

1-3,6,9-14,

21-22,24,29,36

1-3,6,9-14,

21-22,24,29,36

1-3,6,9-14,

21-22,24,29,36

1-3,6,9-14,

21-22,24,29,36

1-3,6,9-14,

21-22,24,29,36

† See “Notes” following AC Electrical Characteristics tables.

25

Zarlink Semiconductor Inc.

MT9043

Data Sheet

AC Electrical Characteristics - 2.048 MHz Input to 2.048 MHz Output Jitter Transfer

Characteristics

Sym. Min. Max. Units

Conditions/Notes†

1

2

Jitter at output for 1 Hz@3.00 UIpp input

2.9

UIpp 1-3,7,9-14,

21-22,24,30,36

with 40 Hz to 100 kHz filter

0.09

1.3

UIpp 1-3,7,9-14,

21-22,24,30,37

3

Jitter at output for 3 Hz@2.33 UIpp input

with 40 Hz to 100 kHz filter

UIpp 1-3,7,9-14,

21-22,24,30,36

4

0.10

0.80

0.10

0.40

0.10

0.06

0.05

0.04

0.03

0.04

0.02

UIpp 1-3,7,9-14,

21-22,24,30,37

5

Jitter at output for 5 Hz@2.07 UIpp input

with 40 Hz to 100 kHz filter

UIpp 1-3,7,9-14,

21-22,24,30,36

6

UIpp 1-3,7,9-14,

21-22,24,30,37

7

Jitter at output for 10 Hz@1.76 UIpp input

with 40 Hz to 100 kHz filter

UIpp 1-3,7,9-14,

21-22,24,30,36

8

UIpp 1-3,7,9-14,

21-22,24,30,37

9

Jitter at output for 100 Hz@1.50 UIpp input

with 40 Hz to 100 kHz filter

UIpp 1-3,7,9-14,

21-22,24,30,36

10

UIpp 1-3,7,9-14,

21-22,24,30,37

11 Jitter at output for 2400 Hz@1.50 UIpp input

UIpp 1-3,7,9-14,

21-22,24,30,36

with 40 Hz to 100 kHz filter

12

UIpp 1-3,7,9-14,

21-22,24,30,37

13 Jitter at output for 100 kHz@0.20 UIpp input

UIpp 1-3,7,9-14,

21-22,24,30,36

with 40 Hz to 100 kHz filter

14

UIpp 1-3,7,9-14,

21-22,24,30,35

† See “Notes” following AC Electrical Characteristics tables.

26

Zarlink Semiconductor Inc.

MT9043

Data Sheet

AC Electrical Characteristics - 8 kHz Input Jitter Tolerance

Characteristics

Sym.

Min. Max.

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

Jitter tolerance for 1 Hz input

Jitter tolerance for 5 Hz input

Jitter tolerance for 20 Hz input

Jitter tolerance for 300 Hz input

Jitter tolerance for 400 Hz input

Jitter tolerance for 700 Hz input

Jitter tolerance for 2400 Hz input

Jitter tolerance for 3600 Hz input

0.80

0.70

0.60

0.20

0.15

0.08

0.02

0.01

UIpp

1-3,5,9 -14,21-22,24-26,28

† See “Notes” following AC Electrical Characteristics tables.

AC Electrical Characteristics - 1.544 MHz Input Jitter Tolerance

Characteristics

Sym.

Min.

Max.

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Jitter tolerance for 1 Hz input

Jitter tolerance for 5 Hz input

Jitter tolerance for 20 Hz input

Jitter tolerance for 300 Hz input

Jitter tolerance for 400 Hz input

Jitter tolerance for 700 Hz input

Jitter tolerance for 2400 Hz input

Jitter tolerance for 10 kHz input

Jitter tolerance for 100 kHz input

150

140

130

35

25

15

4

UIpp

1-3,6,9 -14,21-22,24-26,29

1

0.5

† See “Notes” following AC Electrical Characteristics tables.

AC Electrical Characteristics - 2.048 MHz Input Jitter Tolerance

Characteristics

Sym.

Min.

Ma.x

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Jitter tolerance for 1 Hz input

Jitter tolerance for 5 Hz input

Jitter tolerance for 20 Hz input

Jitter tolerance for 300 Hz input

Jitter tolerance for 400 Hz input

Jitter tolerance for 700 Hz input

Jitter tolerance for 2400 Hz input

Jitter tolerance for 10 kHz input

Jitter tolerance for 100 kHz input

150

140

130

50

40

20

5

UIpp

1-3,7,9 -14,21-22,24-26,30

1

† See “Notes” following AC Electrical Characteristics tables.

27

Zarlink Semiconductor Inc.

MT9043

Data Sheet

AC Electrical Characteristics - OSCi 20 MHz Master Clock Input

Characteristics

Sym.

Min.

Max.

Units

Conditions/Notes†

1

2

3

4

5

6

Tolerance

-0

-32

-100

40

+0

+32

+100

60

ppm

%

15,18

16,19

17,20

Duty cycle

Rise time

Fall time

10

ns

10

ns

† See “Notes” following AC Electrical Characteristics tables.

† Notes:

Voltages are with respect to ground (V_SS) unless otherwise stated.

Supply voltage and operating temperature are as per Recommended Operating Conditions.

Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels

1. PRI reference input selected.

2. SEC reference input selected.

3. Normal Mode selected.

4. Freerun Mode selected.

5. 8 kHz Frequency Mode selected.

6. 1.544 MHz Frequency Mode selected.

7. 2.048 MHz Frequency Mode selected.

8. 19.44 MHz Frequency Mode selected.

^{9. Master clock input OSCi at 20 MHz}±0 ppm.

^{10. Master clock input OSCi at 20 MHz}±32 ppm.

11. Master clock input OSCi at 20 MHz ±100 ppm.

^{12. Selected reference input at}±0 ppm.

^{13. Selected reference input at}±32 ppm.

^{14. Selected reference input at}±100 ppm.

^{15. For Freerun Mode of}±0 ppm.

^{16. For Freerun Mode of}±32 ppm.

17. For Freerun Mode of ±100 ppm.

^{18. For capture range of}±230 ppm.

^{19. For capture range of}±198 ppm.

20. For capture range of ±130 ppm.

21. 25 pF capacitive load.

22. OSCi Master Clock jitter is less than 2 nspp, or 0.04 UIpp where1 UIpp=1/20 MHz.

23. Jitter on reference input is less than 7 nspp.

24. Applied jitter is sinusoidal.

25. Minimum applied input jitter magnitude to regain synchronization.

26. Loss of synchronization is obtained at slightly higher input jitter amplitudes.

27. Within 10 ms of the state, reference or input change.

28. 1 UIpp = 125 us for 8 kHz signals.

29. 1 UIpp = 648 ns for 1.544 MHz signals.

30. 1 UIpp = 488 ns for 2.048 MHz signals.

31. 1 UIpp = 323 ns for 3.088 MHz signals.

32. 1 UIpp = 244 ns for 4.096 MHz signals.

33. 1 UIpp = 122 ns for 8.192 MHz signals.

34. 1 UIpp = 61 ns for 16.384 MHz signals.

35. 1 UIpp = 51.44 ns for 19.44 MHz signals.

36. No filter.

37. 40 Hz to 100 kHz bandpass filter.

38. With respect to reference input signal frequency.

39. After a RST or TCLR.

40. Master clock duty cycle 40% to 60%.

28

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visit our Web Site at

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TECHNICAL DOCUMENTATION - NOT FOR RESALE


型号：	MT9043ANR1
厂家：	Microsemi
描述：	Telecom Circuit, 1-Func, PDSO48, 0.300 INCH, LEAD FREE, MO-118AA, SSOP-48 电信光电二极管电信集成电路
文件：	总30页 (文件大小：242K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT9043ANR1 [MICROSEMI]

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