MT9044AL_技术文档

MT9044

T1/E1/OC3 System Synchronizer

Advance Information

DS5058

ISSUE 3

September 1999

Features

•

Supports AT&T TR62411 and Bellcore

Ordering Information

GR-1244-CORE Stratum 3, Stratum 4

Enhanced and Stratum 4 timing for DS1

interfaces

MT9044AP

MT9044AL

44 Pin PLCC

44 Pin MQFP

•

Supports ITU-T G.812 Type IV clocks for 1,544

kbit/s interfaces and 2,048 kbit/s interfaces

-40 to +85 °C

Description

Supports ETSI ETS 300 011, TBR 4, TBR 12

and TBR 13 timing for E1 interfaces

The MT9044 T1/E1/OC3 System Synchronizer

contains a digital phase-locked loop (DPLL), which

provides timing and synchronization signals for

multitrunk T1 and E1 primary rate transmission links

and STS-3/0C3 links.

Selectable 1.544MHz, 2.048MHz or 8kHz input

reference signals

Provides C1.5, C2, C3, C4, C6, C8, C16, and

C19 (STS-3/OC3 clock divided by 8) output

clock signals

The MT9044 generates ST-BUS clock and framing

signals that are phase locked to either a 2.048MHz,

1.544MHz, or 8kHz input reference.

•

Provides 5 different styles of 8 KHz framing

pulses

•

Holdover frequency accuracy of 0.05 PPM

Holdover indication

The MT9044 is compliant with AT&T TR62411 and

Bellcore GR-1244-CORE Stratum 3, Stratum 4

Enhanced, and Stratum 4; and ETSI ETS 300 011. It

will meet the jitter/wander tolerance, jitter/wander

transfer, intrinsic jitter/wander, frequency accuracy,

capture range, phase change slope, holdover

frequency and MTIE requirements for these

speciﬁcations.

Attenuates wander from 1.9Hz

Provides Time Interval Error (TIE) correction

Accepts reference inputs from two independent

sources

•

JTAG Boundary Scan

Applications

•

Synchronization and timing control for

multitrunk T1,E1 and STS-3/OC3 systems

•

ST-BUS clock and frame pulse sources

OSCi

OSCo

TCLR

VDD

VSS

C19o

Master Clock

Virtual

C1.5o

TIE

Reference

TCK

C3o

C2o

C4o

C6o

C8o

C16o

F0o

F8o

F16o

RSP

Corrector

Circuit

DPLL

TDI

TMS

TRST

TDO

IEEE

1149.1a

Output

Interface

Circuit

Selected

State

Select

Reference

Select

MUX

PRI

SEC

Input

Impairment

Monitor

TIE

Corrector

Enable

State

Select

Reference

Select

TSP

Feedback

Frequency

Select

MUX

RSEL

LOS1

LOS2

Automatic/Manual

Control State Machine

Guard Time

Circuit

ACKi

APLL

ACKo

MS1

MS2

RST HOLDOVER

GTo

GTi

FS1

FS2

Figure 1 - Functional Block Diagram

1

MT9044

Advance Information

44 43 42 41 40 3938 37 36 35 34

6

5 4 3 2 1 44 43 42 41 40

TEST

RSEL

MS1

MS2

TDO

LOS1

LOS2

GTo

VSS

GTi

33

32

31

30

29

28

27

26

25

24

23

1

2

3

4

5

6

7

8

9

VDD

OSCo

OSCi

VSS

F16o

RSP

F0o

VDD

OSCo

OSCi

VSS

F16o

RSP

39

38

37

36

35

34

33

32

31

30

29

TEST

RSEL

MS1

MS2

7

8

9

10

11

12

13

14

15

16

17

TDO

MT9044AL

MT9044

LOS1

LOS2

GTo

VSS

GTi

F0o

TSP

F8o

TSP

F8o

C1.5o

10

11

C1.5o

HOLDOVER

AVDD

HOLDOVER

AVDD

12 13 14 15 16 17 18 19 20 21 22

18 19 20 21 22 23 24 25 26 27 28

Figure 2 - Pin Connections

Pin Description

Pin # Pin #

PLCC MQFP

Name

Description

1,10, 39,4,17

V_SS

Ground. 0 Volts.

23,31

,25

2

40

TCK

Test Clock (TTL Input): Provides the clock to the JTAG test logic. This pin is

internally pulled up to V

.

DD

3

41

TCLR

TIE Circuit Reset (TTL Input): A logic low at this input resets the Time Interval

Error (TIE) correction circuit resulting in a re-alignment of input phase with output

phase as shown in Figure 19. The TCLR pin should be held low for a minimum of

300ns. This pin is internally pulled down to VSS.

4

5

42

43

TRST

SEC

Test Reset (TTL Input): Asynchronously initializes the JTAG TAP controller by

putting it in the Test-Logic-Reset state. This pin is internally pulled down to VSS.

Secondary Reference (TTL Input). This is one of two (PRI & SEC) input

reference sources (falling edge) used for synchronization. One of three possible

frequencies (8kHz, 1.544MHzMHz, or 2.048MHz) may be used. The selection of

the input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi

control inputs (Automatic or Manual). This pin is internally pulled up to V

.

DD

6

44

PRI

Primary Reference (TTL Input). See pin description for SEC. This pin is

internally pulled up to V

.

DD

7,28

8

1,22

2

V_DD

Positive Supply Voltage. +5V nominal.

DC

OSCo

Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal

is connected from this pin to OSCi, see Figure 10. For clock oscillator operation,

this pin is left unconnected, see Figure 9.

9

3

5

OSCi

F16o

Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is

connected from this pin to OSCo, see Figure 10. For clock oscillator operation, this

pin is connected to a clock source, see Figure 9.

11

Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active

low framing pulse, which marks the beginning of an ST-BUS frame. This is typically

used for ST-BUS operation at 8.192 Mb/s. See Figure 20.

2

Advance Information

MT9044

Pin Description (continued)

Pin # Pin #

Name

Description

PLCC MQFP

12

13

14

15

6

7

8

9

RSP

F0o

TSP

F8o

Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing

pulse, which marks the end of an ST-BUS frame. This is typically used for

connection to the Siemens MUNICH-32 device. See Figure 21.

Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active

low framing pulse, which marks the beginning of an ST-BUS frame. This is typically

used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 20.

Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing

pulse, which marks the beginning of an ST-BUS frame. This is typically used for

connection to the Siemens MUNICH-32 device. See Figure 21.

Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse,

which marks the beginning of a frame. See Figure 20.

16

17

18

19

10

11

12

13

C1.5o

AVdd

C3o

Clock 1.544MHz (CMOS Output). This output is used in T1 applications.

Analog Vdd. +5V nominal.

DC

Clock 3.088MHz (CMOS Output). This output is used in T1 applications.

C2o

Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at

2.048Mb/s.

20

14

C4o

Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at

2.048Mb/s and 4.096Mb/s.

21

22

15

16

C19o

ACKi

Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.

Analog PLL Clock Input (CMOS Input). This input clock is a reference for an

internal analog PLL. This pin is internally pulled down to VSS.

24

25

26

18

19

20

ACKo

C8o

Analog PLL Clock Output (CMOS Output). This output clock is generated by

the internal analog PLL.

Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at

8.192Mb/s.

C16o

Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with

a 16.384MHz clock.

27

29

21

23

C6o

Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.

HOLDOVER Holdover (CMOS Output). This output goes to a logic high whenever the digital

PLL goes into holdover mode.

30

24

GTi

Guard Time (Schmitt Input). This input is used by the MT9044 state machine in

both Manual and Automatic modes. The signal at this pin affects the state changes

between Primary Holdover Mode and Primary Normal Mode, and Primary

Holdover Mode and Secondary Normal Mode. The logic level at this input is gated

in by the rising edge of F8o. See Tables 4 and 5.

32

33

26

27

GTo

Guard Time (CMOS Output). The LOS1 input is gated by the rising edge of F8o,

buffered and output on GTo. This pin is typically used to drive the GTi input through

an RC circuit.

LOS2

Secondary Reference Loss (TTL Input). This input is normally connected to the

loss of signal (LOS) output signal of a Line Interface Unit (LIU). When high, the

SEC reference signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs

control the MT9044 state machine when operating in Automatic Control. The logic

level at this input is gated in by the rising edge of F8o. This pin is internally pulled

down to VSS.

3

MT9044

Advance Information

Pin Description (continued)

Pin # Pin #

Name

Description

PLCC MQFP

34

28

LOS1

Primary Reference Loss (TTL Input). Typically, external equipment applies a

logic high to this input when the PRI reference signal is lost or invalid. The logic

level at this input is gated in by the rising edge of F8o. See LOS2 description. This

pin is internally pulled down to VSS.

35

36

29

30

TDO

MS2

Test Serial Data Out (TTL Output). JTAG serial data is output on this pin on the

falling edge of TCK. This pin is held in high impedance state when JTAG scan is

not enable.

Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1,

determines the device’s mode (Automatic or Manual) and state (Normal, Holdover

or Freerun) of operation. The logic level at this input is gated in by the rising edge

of F8o. See Table 3.

37

38

31

32

MS1

Mode/Control Select 1 (TTL Input). The logic level at this input is gated in by the

rising edge of F8o. See pin description for MS2. This pin is internally pulled down

to VSS.

RSEL

Reference Source Select (TTL Input). In Manual Control, a logic low selects the

PRI (primary) reference source as the input reference signal and a logic high

selects the SEC (secondary) input. In Automatic Control, this pin must be at logic

low. The logic level at this input is gated in by the rising edge of F8o. See Table 2.

This pin is internally pulled down to VSS.

39

40

33

34

TEST

FS2

Test (TTL Input). This input is normally tied low. When pulled high, it enables

internal test modes. This pin is internally pulled down to VSS.

Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects

which of three possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input

to the PRI and SEC inputs. See Table 1.

41

42

35

36

FS1

TDI

Frequency Select 1 (TTL Input). See pin description for FS2.

Test Serial Data In (TTL Input). JTAG serial test instructions and data are shifted

in on this pin. This pin is internally pulled up to V

.

DD

43

37

RST

Reset (Schmitt Input). A logic low at this input resets the MT9044. To ensure

proper operation, the device must be reset after changes to the method of control,

reference signal frequency changes and power-up. The RST pin should be held

low for a minimum of 300ns. While the RST pin is low, all frame and clock outputs

are at logic high. Following a reset, the input reference source and output clocks

and frame pulses are phase aligned as shown in Figure 19.

44

38

TMS

Test Mode Select (TTL Input). JTAG signal that controls the state transitions of

the TAP controller. This pin is internally pulled up to V

.

DD

4

Advance Information

MT9044

Functional Description

FS2

FS1

Input Frequency

The MT9044 is a Multitrunk System Synchronizer,

providing timing (clock) and synchronization (frame)

signals to interface circuits for T1 and E1 Primary

Rate Digital Transmission links.

0

1

0

1

0

1

Reserved

8kHz

1.544MHz

2.048MHz

Figure 1 shows the functional block diagram which is

described in the following sections.

Table 1 - Input Frequency Selection

Time Interval Error (TIE) Corrector Circuit

Reference Select MUX Circuit

The TIE corrector circuit, when enabled, prevents a

step change in phase on the input reference signals

(PRI or SEC) from causing a step change in phase at

the input of the DPLL block of Figure 1.

The MT9044 accepts two simultaneous reference

input signals and operates on their falling edges.

Either the primary reference (PRI) signal or the

secondary reference (SEC) signal can be selected

as input to the TIE Corrector Circuit. The selection is

based on the Control, Mode and Reference

Selection of the device. See Tables 1, 4 and 5.

During reference input rearrangement, such as

during a switch from the primary reference (PRI) to

the secondary reference (SEC), a step change in

phase on the output signals will occur. A phase step

at the input of the DPLL will lead to unacceptable

phase changes in the output signal.

Frequency Select MUX Circuit

The MT9044 operates with one of three possible

input reference frequencies (8kHz, 1.544MHz or

2.048MHz). The frequency select inputs (FS1 and

FS2) determine which of the three frequencies may

be used at the reference inputs (PRI and SEC). Both

inputs must have the same frequency applied to

them. A reset (RST) must be performed after every

frequency select input change. Operation with FS1

and FS2 both at logic low is reserved and must not

be used. See Table 1.

As shown in Figure 3, the TIE Corrector Circuit

receives one of the two reference (PRI or SEC)

signals, passes the signal through a programmable

delay line, and uses this delayed signal as an

internal virtual reference, which is input to the DPLL.

Therefore, the virtual reference is a delayed version

of the selected reference.

During a switch, from one reference to the other, the

State Machine ﬁrst changes the mode of the device

TCLR

Resets Delay

Control

Circuit

Control Signal

Delay Value

Programmable

Delay Circuit

Virtual

Reference

to DPLL

PRI or SEC

from

Reference

Select Mux

Compare

Circuit

TIE Corrector

Enable

Feedback

Signal from

Frequency

Select MUX

from

State Machine

Figure 3 - TIE Corrector Circuit

5

MT9044

Advance Information

from Normal to Holdover. In Holdover Mode, the

DPLL no longer uses the virtual reference signal, but

generates an accurate clock signal using storage

techniques. The Compare Circuit then measures the

phase delay between the current phase (feedback

signal) and the phase of the new reference signal.

This delay value is passed to the Programmable

Delay Circuit (See Figure 3). The new virtual

reference signal is now at the same phase position

as the previous reference signal would have been if

the reference switch had not taken place. The State

Machine then returns the device to Normal Mode.

Digital Phase Lock Loop (DPLL)

As shown in Figure 4, the DPLL of the MT9044

consists of a Phase Detector, Limiter, Loop Filter,

Digitally Controlled Oscillator, and a Control Circuit.

Phase Detector - the Phase Detector compares the

virtual reference signal from the TIE Corrector circuit

with the feedback signal from the Frequency Select

MUX circuit, and provides an error signal

corresponding to the phase difference between the

two. This error signal is passed to the Limiter circuit.

The Frequency Select MUX allows the proper

feedback signal to be externally selected (e.g., 8kHz,

1.544MHz or 2.048MHz).

The DPLL now uses the new virtual reference signal,

and since no phase step took place at the input of

the DPLL, no phase step occurs at the output of the

DPLL. In other words, reference switching will not

create a phase change at the input of the DPLL, or at

the output of the DPLL.

Limiter - the Limiter receives the error signal from

the Phase Detector and ensures that the DPLL

responds to all input transient conditions with a

maximum output phase slope of 5ns per 125us. This

is well within the maximum phase slope of 7.6ns per

125us or 81ns per 1.326ms speciﬁed by AT&T

TR62411, and Bellcore GR-1244-CORE.

Since internal delay circuitry maintains the alignment

between the old virtual reference and the new virtual

reference, a phase error may exist between the

selected input reference signal and the output signal

of the DPLL. This phase error is a function of the

difference in phase between the two input reference

signals during reference rearrangements. Each time

a reference switch is made, the delay between input

signal and output signal will change. The value of

this delay is the accumulation of the error measured

during each reference switch.

Loop Filter - the Loop Filter is similar to a ﬁrst order

low pass ﬁlter with a 1.9 Hz cutoff frequency for all

three reference frequency selections (8kHz,

1.544MHz or 2.048MHz). This ﬁlter ensures that the

jitter transfer requirements in ETS 300 011 and AT&T

TR62411 are met.

Control Circuit - the Control Circuit uses status and

control information from the State Machine and the

Input Impairment Circuit to set the mode of the

DPLL. The three possible modes are Normal,

Holdover and Freerun.

The programmable delay circuit can be zeroed by

applying a logic low pulse to the TIE Circuit Reset

(TCLR) pin. A minimum reset pulse width is 300ns.

This results in a phase alignment between the input

reference signal and the output signal as shown in

Figure 20. The speed of the phase alignment

correction is limited to 5ns per 125us, and

convergence is in the direction of least phase travel.

Digitally Controlled Oscillator (DCO) - the DCO

receives the limited and ﬁltered signal from the Loop

FIlter, and based on its value, generates

a

corresponding digital output signal. The

synchronization method of the DCO is dependent on

the state of the MT9044.

The state diagrams of Figure 7 and 8 indicate the

state changes that activate the TIE Corrector Circuit.

Phase

Detector

Digitally

Controlled

Oscillator

Virtual Reference from

DPLL Reference to

Output Interface Circuit

Limiter

Loop Filter

TIE Corrector

Feedback Signal from

Frequency Select MUX

State Select from

Input Impairment

Monitor

Control

Circuit

State Select from

State Machine

Figure 4 - DPLL Block Diagram

6

Advance Information

MT9044

In Normal Mode, the DCO provides an output signal

which is frequency and phase locked to the selected

input reference signal.

C1.5o

C3o

T1 Divider

12MHz

In Holdover Mode, the DCO is free running at a

frequency equal to the last (less 30ms to 60ms)

frequency the DCO was generating while in Normal

Mode.

Tapped

Delay

Line

C2o

C4o

C8o

C16o

F0o

F8o

E1 Divider

In Freerun Mode, the DCO is free running with an

accuracy equal to the accuracy of the OSCi 20MHz

source.

Tapped

Delay

Line

16MHz

From

DPLL

F16o

Output Interface Circuit

Tapped

Delay

Line

C6o

The output of the DCO (DPLL) is used by the Output

Interface Circuit to provide the output signals shown

in Figure 5. The Output Interface Circuit uses four

Tapped Delay Lines followed by a T1 Divider Circuit ,

an E1 Divider Circuit, a DS2 Divider Circuit and an

analog PLL to generate the required output signals.

12MHz

19MHz

DS2 Divider

Tapped

Delay

Line

C19o

ACKo

Four tapped delay lines are used to generate a

16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz

signals.

Analog PLL

ACKi

Figure 5 - Output Interface Circuit Block

Diagram

The E1 Divider Circuit uses the 16.384MHz signal to

generate four clock outputs and three frame pulse

The frame pulse outputs (F0o, F8o, F16o, TSP, RSP)

are generated directly from the C16 clock.

outputs.

The C8o, C4o and C2o clocks are

generated by simply dividing the C16o clock by two,

four and eight respectively. These outputs have a

nominal 50% duty cycle.

The T1 and E1 signals are generated from a

common DPLL signal. Consequently, the clock

outputs C1.5o, C3o, C2o, C4o, C8o, C16o, F0o, F16o

and C6o are locked to one another for all operating

states, and are also locked to the selected input

reference in Normal Mode. See Figures 20 and 21.

The T1 Divider Circuit uses the 12.384MHz signal to

generate two clock outputs. C1.5o and C3o are

generated by dividing the internal C12 clock by four

and eight respectively.

nominal 50% duty cycle.

These outputs have a

All frame pulse and clock outputs have limited driving

capability, and should be buffered when driving high

capacitance (e.g. 30pF) loads.

The DS2 Divider Circuit uses the 12.624 MHz signal

to generate the clock output C6o. This output has a

nominal 50% duty cycle.

Analog Phase Lock Loop (APLL)

The analog PLL is intended to be used to achieve a

50% duty cycle output clock. Connecting C19o to

ACKi will generate a phase locked 19.44 MHz ACKo

output with a nominal 50% duty cycle. The analog

PLL has an intrinsic jitter of less than 0.01 U.I. In

order to achieve this low jitter level a separate pin is

provided to power (AVdd) the analog PLL.

7

MT9044

Advance Information

Input Impairment Monitor

Guard Time Circuit

This circuit monitors the input signal to the DPLL and

The GTi pin is used by the Automatic/Manual Control

State Machine in the MT9044 under either Manual or

Automatic control. The logic level at the GTi pin

performs two functions, it enables and disables the

TIE Corrector Circuit (Manual and Automatic), and it

selects which mode change takes place (Automatic

only). See the Applications - Guard Time section.

automatically

enables

the

Holdover

Mode

(Auto-Holdover) when the frequency of the incoming

signal is outside the auto-holdover capture range

(See AC Electrical Characteristics - Performance).

This includes a complete loss of incoming signal, or

a large frequency shift in the incoming signal. When

the incoming signal returns to normal, the DPLL is

returned to Normal Mode with the output signal

locked to the input signal. The holdover output

signal is based on the incoming signal 30ms

minimum to 60ms prior to entering the Holdover

Mode. The amount of phase drift while in holdover is

negligible because the Holdover Mode is very

accurate (e.g. ±0.05ppm). The the Auto-Holdover

circuit does not use TIE correction. Consequently,

the phase delay between the input and output after

switching back to Normal Mode is preserved (is the

same as just prior to the switch to Auto-Holdover).

For both Manual and Automatic control, when

switching from Primary Holdover to Primary Normal,

the TIE Corrector Circuit is enabled when GTi=1, and

disabled when GTi=0.

Under Automatic control and in Primary Normal

Mode, two state changes are possible (not counting

Auto-Holdover). These are state changes to Primary

Holdover or to Secondary Normal. The logic level at

the GTi pin determines which state change occurs.

When GTi=0, the state change is to Primary

Holdover. When GTi=1, the state change is to

Secondary Normal.

Automatic/Manual Control State Machine

The Automatic/Manual Control State Machine allows

the MT9044 to be controlled automatically (i.e.

LOS1, LOS2 and GTi signals) or controlled manually

(i.e. MS1, MS2, GTi and RSEL signals). With

manual control a single mode of operation (i.e.

Normal, Holdover and Freerun) is selected. Under

automatic control the state of the LOS1, LOS2 and

GTi signals determines the sequence of modes that

the MT9044 will follow.

Master Clock

The MT9044 can use either a clock or crystal as the

master timing source. For recommended master

timing circuits, see the Applications - Master Clock

section.

Control and Modes of Operation

As shown in Figure 1, this state machine controls the

Reference Select MUX, the TIE Corrector Circuit, the

DPLL and the Guard Time Circuit. Control is based

on the logic levels at the control inputs LOS1, LOS2,

RSEL, MS1, MS2 and GTi of the Guard Time Circuit

(See Figure 6).

The MT9044 can operate either in Manual or

Automatic Control. Each control method has three

possible modes of operation, Normal, Holdover and

Freerun.

As shown in Table 3, Mode/Control Select pins MS2

and MS1 select the mode and method of control.

All state machine changes occur synchronously on

the rising edge of F8o. See the Controls and Modes

of Operation section for full details on Automatic

Control and Manual Control.

Control

RSEL

Input Reference

MANUAL

0

1

0

1

PRI

SEC

To

To TIE

Corrector

Enable

To DPLL

State

Select

Reference

Select MUX

AUTO

State Machine Control

Reserved

RSEL

LOS1

LOS2

To and From

Guard Time

Circuit

Automatic/Manual Control

State Machine

Table 2 - Input Reference Selection

MS1

MS2

Figure 6 - Automatic/Manual Control State

Machine Block Diagram

8

Advance Information

MT9044

Normal Mode

MS2 MS1

Control

Mode

Normal Mode is typically used when a slave clock

source, synchronized to the network is required.

0

1

0

1

0

1

MANUAL

AUTO

NORMAL

HOLDOVER

In Normal Mode, the MT9044 provides timing (C1.5o,

C2o, C3o, C4o, C8o, C16o, and C19) and frame

synchronization (F0o, F8o, F16o, RSP, TSP) signals,

which are synchronized to one of two reference

inputs (PRI or SEC). The input reference signal may

have a nominal frequency of 8kHz, 1.544MHz or

2.048MHz.

FREERUN

State Machine Control

Table 3 - Operating Modes and States

Manual Control

Manual Control should be used when either very

simple MT9044 control is required, or when complex

control is required which is not accommodated by

Automatic Control. For example, very simple control

could include operation in a system which only

requires Normal Mode with reference switching

using only a single input stimulus (RSEL). Very

simple control would require no external circuitry.

Complex control could include a system which

requires state changes between Normal, Holdover

and Freerun Modes based on numerous input

stimuli. Complex control would require external

circuitry, typically a microcontroller.

From a reset condition, the MT9044 will take up to 25

seconds for the output signal to be phase locked to

the selected reference.

The selection of input references is control

dependent as shown in State Tables 4 and 5. The

reference frequencies are selected by the frequency

control pins FS2 and FS1 as shown in Table 1.

Holdover Mode

Holdover Mode is typically used for short durations

(e.g. 2 seconds) while network synchronization is

temporarily disrupted.

Under Manual Control, one of the three modes is

selected by mode/control select pins MS2 and MS1.

The active reference input (PRI or SEC) is selected

by the RSEL pin as shown in Table 2. Refer to Table

In Holdover Mode, the MT9044 provides timing and

synchronization signals, which are not locked to an

external reference signal, but are based on storage

techniques. The storage value is determined while

the device is in Normal Mode and locked to an

external reference signal.

4

and Figure 7 for details of the state change

sequences.

Automatic Control

When in Normal Mode, and locked to the input

reference signal, a numerical value corresponding to

the MT9044 output frequency is stored alternately in

two memory locations every 30ms. When the device

is switched into Holdover Mode, the value in memory

from between 30ms and 60ms is used to set the

output frequency of the device.

Automatic Control should be used when simple

MT9044 control is required, which is more complex

than the very simple control provide by Manual

Control with no external circuitry, but not as complex

as Manual Control with a microcontroller.

For

example, simple control could include operation in a

system which can be accommodated by the

Automatic Control State Diagram shown in Figure 8.

The frequency accuracy of Holdover Mode is

±0.05ppm, which translates to a worst case 35 frame

(125us) slips in 24 hours. This meets the Bellcore

GR-1244-CORE Stratum 3 requirement of ±0.37ppm

(255 frame slips per 24 hours).

Automatic Control is also selected by mode/control

pins MS2 and MS1. However, the mode and active

reference source is selected automatically by the

internal Automatic State Machine (See Figure 6).

The mode and reference changes are based on the

logic levels on the LOS1, LOS2 and GTi control pins.

Refer to Table 5 and Figure 8 for details of the state

change sequences.

Two factors affect the accuracy of Holdover Mode.

One is drift on the Master Clock while in Holdover

Mode, drift on the Master Clock directly affects the

Holdover Mode accuracy. Note that the absolute

Master Clock (OSCi) accuracy does not affect

Holdover accuracy, only the change in OSCi

accuracy while in Holdover. For example, a ±32ppm

9

MT9044

Advance Information

master clock may have a temperature coefﬁcient of

±0.1ppm per degree C. So a 10 degree change in

temperature, while the MT9044 is in Holdover Mode

may result in an additional offset (over the

±0.05ppm) in frequency accuracy of ±1ppm, which

is much greater than the ±0.05ppm of the MT9044.

The other factor affecting accuracy is large jitter on

the reference input prior (30ms to 60ms) to the

mode switch. For instance, jitter of 7.5UI at 700Hz

may reduce the Holdover Mode accuracy from

0.05ppm to 0.10ppm.

Freerun Mode

Freerun Mode is typically used when a master clock

source is required, or immediately following system

power-up before network synchronization is

achieved.

In Freerun Mode, the MT9044 provides timing and

synchronization signals which are based on the

master clock frequency (OSCi) only, and are not

synchronized to the reference signals (PRI and

SEC).

The accuracy of the output clock is equal to the

accuracy of the master clock (OSCi). So if a ±32ppm

output clock is required, the master clock must also

be ±32ppm. See Applications - Crystal and Clock

Oscillator sections.

10

Advance Information

MT9044

Description

State

Normal

(PRI)

Normal

(SEC)

Holdover

(PRI)

Holdover

(SEC)

Input Controls

Freerun

S0

MS2

MS1

RSEL

GTi

S1

S2

S1H

S2H

0

1

0

1

0

1

0

1

X

0

1

S1

S2

/

-

S1 MTIE

S1

S1 MTIE

X

S2 MTIE

S1H

S2H

S0

-

/

S2 MTIE

-

/

-

/

S2H

S0

-

S0

Legend:

-

No Change

Not Valid

/

MTIE

State change occurs with TIE Corrector Circuit

Refer to Manual Control State Diagram for state changes to and from Auto-Holdover State

Table 4 - Manual Control State Table

S0

Freerun

(10X)

S1

S1A

Auto-Holdover

Primary

S2A

Auto-Holdover

Secondary

(001)

S2

Normal

Secondary

(001)

{A}

Normal

Primary

(000)

(GTi=0)

(GTi=1)

S1H

Holdover

Primary

(010)

S2H

Holdover

Secondary

(011)

NOTES:

(XXX)

{A}

MS2 MS1 RSEL

Invalid Reference Signal

Phase Re-Alignment

Phase Continuity Maintained (without TIE Corrector Circuit)

Phase Continuity Maintained (with TIE Corrector Circuit)

Movement to Normal State from any

state requires a valid input signal

Figure 7 - Manual Control State Diagram

11

MT9044

Advance Information

Description

Input Controls

State

Normal

(PRI)

Normal

(SEC)

Holdover

(PRI)

Holdover

(SEC)

Freerun

S0

LOS2

LOS1

GTi

RST

S1

S2

S1H

S2H

1

X

0

1

0

1

X

0

1

0

1

X

0 to 1

-

S0

1

S1

S2

-

S1 MTIE

S1

S1 MTIE

S2 MTIE

-

S1 MTIE

S1H

S2 MTIE

S1H

-

S2 MTIE

-

S2H

Legend:

-

No Change

MTIE

State change occurs with TIE Corrector Circuit

Refer to Automatic Control State Diagram for state changes to and from Auto-Holdover State

Table 5 - Automatic Control (MS1=MS2=1, RSEL=0) State Table

(11X)

(11X) RST=1

Reset

S0

Freerun

(X0X)

(01X)

(X0X)

(01X)

(X0X)

(01X)

(X0X)

(01X)

{A}

S1

Normal

Primary

S1A

Auto-Holdover

Primary

S2A

Auto-Holdover

Secondary

S2

{A}

Normal

Secondary

(X0X)

(011)

(11X)

(010 or 11X)

(X0X)

(011)

(01X)

(X00)

S1H

Holdover

Primary

S2H

Holdover

Secondary

(X01)

(010 or 11X)

(11X)

NOTES:

(XXX)

{A}

LOS2 LOS1 GTi

Invalid Reference Signal

Phase Re-Alignment

Phase Continuity Maintained (without TIE Corrector Circuit)

Phase Continuity Maintained (with TIE Corrector Circuit)

Movement to Normal State from any

state requires a valid input signal

Figure 8 - Automatic Control State Diagram

12

Advance Information

MT9044

same signal, these transfer values apply to all

outputs.

MT9044 Measures of Performance

It should be noted that 1UI at 1.544MHz is 644ns,

which is not equal to 1UI at 2.048MHz, which is

The following are some synchronizer performance

indicators and their corresponding deﬁnitions.

488ns.

Consequently, a transfer value using

different input and output frequencies must be

calculated in common units (e.g. seconds) as shown

in the following example.

Intrinsic Jitter

Intrinsic jitter is the jitter produced by the

synchronizing circuit and is measured at its output.

It is measured by applying a reference signal with no

jitter to the input of the device, and measuring its

output jitter. Intrinsic jitter may also be measured

when the device is in a non-synchronizing mode,

such as free running or holdover, by measuring the

output jitter of the device. Intrinsic jitter is usually

measured with various bandlimiting ﬁlters depending

on the applicable standards.

What is the T1 and E1 output jitter when the T1 input

jitter is 20UI (T1 UI Units) and the T1 to T1 jitter

attenuation is 18dB?

–A

------

20

OutputT1 = InputT1×10

–18

--------

20

OutputT1 = 20×10

= 2.5UI(T1)

Jitter Tolerance

(1UIT1)

---------------------

(1UIE1)

OutputE1 = OutputT1 ×

Jitter tolerance is a measure of the ability of a PLL to

operate properly (i.e., remain in lock and or regain

lock in the presence of large jitter magnitudes at

various jitter frequencies) when jitter is applied to its

reference. The applied jitter magnitude and jitter

frequency depends on the applicable standards.

(644ns)

(488ns)

-------------------

OutputE1 = OutputT1 ×

= 3.3UI(T1)

Using the above method, the jitter attenuation can be

calculated for all combinations of inputs and outputs

based on the three jitter transfer functions provided.

Jitter Transfer

Note that the resulting jitter transfer functions for all

combinations of inputs (8kHz, 1.544MHz, 2.048MHz)

Jitter transfer or jitter attenuation refers to the

magnitude of jitter at the output of a device for a

given amount of jitter at the input of the device. Input

jitter is applied at various amplitudes and

frequencies, and output jitter is measured with

various ﬁlters depending on the applicable

standards.

and

outputs

(8kHz,

1.544MHz,

2.048MHz,

4.096MHz, 8.192MHz, 16.384MHz) for a given input

signal (jitter frequency and jitter amplitude) are the

same.

Since intrinsic jitter is always present,

jitter

attenuation will appear to be lower for small input

jitter signals than for large ones. Consequently,

accurate jitter transfer function measurements are

usually made with large input jitter signals (e.g. 75%

of the speciﬁed maximum jitter tolerance).

For the MT9044, two internal elements determine

the jitter attenuation. This includes the internal

1.9Hz low pass loop ﬁlter and the phase slope

limiter. The phase slope limiter limits the output

phase slope to 5ns/125us. Therefore, if the input

signal exceeds this rate, such as for very large

amplitude low frequency input jitter, the maximum

output phase slope will be limited (i.e. attenuated) to

5ns/125us.

Frequency Accuracy

Frequency accuracy is deﬁned as the absolute

tolerance of an output clock signal when it is not

locked to an external reference, but is operating in a

free running mode. For the MT9044, the Freerun

accuracy is equal to the Master Clock (OSCi)

accuracy.

The MT9044 has thirteen outputs with three possible

input frequencies for a total of 39 possible jitter

transfer functions. However, the data sheet section

on AC Electrical Characteristics - Jitter Transfer

speciﬁes transfer values for only three cases, 8kHz

to 8kHz, 1.544MHz to 1.544MHz and 2.048MHz to

2.048MHz. Since all outputs are derived from the

Holdover Accuracy

Holdover accuracy is deﬁned as the absolute

tolerance of an output clock signal, when it is not

13

MT9044

Advance Information

locked to an external reference signal, but is

end of a particular observation period. Usually, the

given timing signal and the ideal timing signal are of

the same frequency. Phase continuity applies to the

output of the synchronizer after a signal disturbance

due to a reference switch or a mode change. The

observation period is usually the time from the

disturbance, to just after the synchronizer has settled

to a steady state.

operating using storage techniques.

For the

MT9044, the storage value is determined while the

device is in Normal Mode and locked to an external

reference signal.

The absolute Master Clock (OSCi) accuracy of the

MT9044 does not affect Holdover accuracy, but the

change in OSCi accuracy while in Holdover Mode

does.

In the case of the MT9044, the output signal phase

continuity is maintained to within ±5ns at the

instance (over one frame) of all reference switches

and all mode changes. The total phase shift,

depending on the switch or type of mode change,

may accumulate up to ±200ns over many frames.

The rate of change of the ±200ns phase shift is

limited to a maximum phase slope of approximately

5ns/125us. This meets the maximum phase slope

requirement of Bellcore GR-1244-CORE (81ns/

1.326ms).

Capture Range

Also referred to as pull-in range. This is the input

frequency range over which the synchronizer must

be able to pull into synchronization. The MT9044

capture range is equal to ±230ppm minus the

accuracy of the master clock (OSCi). For example, a

±32ppm master clock results in a capture range of

±198ppm.

Phase Lock Time

Lock Range

This is the time it takes the synchronizer to phase

lock to the input signal. Phase lock occurs when the

input signal and output signal are not changing in

phase with respect to each other (not including jitter).

This is the input frequency range over which the

synchronizer

must

be

able

to

maintain

synchronization. The lock range is equal to the

capture range for the MT9044.

Lock time is very difﬁcult to determine because it is

affected by many factors which include:

Phase Slope

i) initial input to output phase difference

ii) initial input to output frequency difference

iii) synchronizer loop ﬁlter

Phase slope is measured in seconds per second and

is the rate at which a given signal changes phase

with respect to an ideal signal. The given signal is

typically the output signal. The ideal signal is of

constant frequency and is nominally equal to the

value of the ﬁnal output signal or ﬁnal input signal.

iv) synchronizer limiter

Although a short lock time is desirable, it is not

always possible to achieve due to other synchronizer

requirements. For instance, better jitter transfer

performance is achieved with a lower frequency loop

ﬁlter which increases lock time. And better (smaller)

phase slope performance (limiter) results in longer

lock times. The MT9044 loop ﬁlter and limiter were

optimized to meet the AT&T TR62411 jitter transfer

Time Interval Error (TIE)

TIE is the time delay between a given timing signal

and an ideal timing signal.

and phase slope requirements.

phase lock time, which is not

Consequently,

standards

Maximum Time Interval Error (MTIE)

a

requirement, may be longer than in other

applications. See AC Electrical Characteristics -

Performance for maximum phase lock time.

MTIE is the maximum peak to peak delay between a

given timing signal and an ideal timing signal within a

particular observation period.

MTIE(S)= TIEmax(t) – TIEmin(t)

Phase Continuity

Phase continuity is the phase difference between a

given timing signal and an ideal timing signal at the

14

Advance Information

MT9044

MT9044 and Network Speciﬁcations

Applications

The MT9044 fully meets all applicable PLL

requirements (intrinsic jitter/wander, jitter/wander

tolerance, jitter/wander transfer, frequency accuracy,

frequency holdover accuracy, capture range, phase

change slope and MTIE during reference

rearrangement) for the following speciﬁcations.

This section contains MT9044 application speciﬁc

details for clock and crystal operation, guard time

usage, reset operation, power supply decoupling,

Manual Control operation and Automatic Control

operation.

Master Clock

1. Bellcore GR-1244-CORE June 1995 for

Stratum 3, Stratum 4 Enhanced and Stratum 4

2. AT&T TR62411 (DS1) December 1990 for

Stratum 3, Stratum 4 Enhanced and Stratum 4

3. ANSI T1.101 (DS1) February 1994 for

Stratum 3, Stratum 4 Enhanced and Stratum 4

4. ETSI 300 011 (E1) April 1992 for

Single Access and Multi Access

The MT9044 can use either a clock or crystal as the

master timing source.

In Freerun Mode, the frequency tolerance at the

clock outputs is identical to the frequency tolerance

of the source at the OSCi pin. For applications not

requiring an accurate Freerun Mode, tolerance of the

master timing source may be ±100ppm.

For

5. TBR 4 November 1995

applications requiring an accurate Freerun Mode,

such as Bellcore GR-1244-CORE, the tolerance of

the master timing source must Be no greater than

±32ppm.

6. TBR 12 December 1993

7. TBR 13 January 1996

8. ITU-T I.431 March 1993

9. ITU-T G.812 June 1998 for type IV clocks for

1,544 kbit/s interfaces and 2,048 kbit/s interfaces

Another consideration in determining the accuracy of

the master timing source is the desired capture

range. The sum of the accuracy of the master timing

source and the capture range of the MT9044 will

always equal ±230ppm. For example, if the master

timing source is ±100ppm, then the capture range

will be ±130ppm.

Clock Oscillator - when selecting a Clock Oscillator,

numerous parameters must be considered. This

includes absolute frequency, frequency change over

temperature, output rise and fall times, output levels

and duty cycle. See AC Electrical Characteristics.

MT9044

+5V

OSCi

+5V

20MHz OUT

GND

0.1uF

OSCo

No Connection

Figure 9 - Clock Oscillator Circuit

For applications requiring ±32ppm clock accuracy,

the following clock oscillator module may be used.

CTS CXO-65-HG-5-C-20.0MHz

Frequency:

Tolerance:

20MHz

25ppm 0C to 70C

15

MT9044

Advance Information

Rise & Fall Time:

Duty Cycle:

8ns (0.5V 4.5V 50pF)

45% to 55%

e.g., CTS R1027-2BB-20.0MHZ

(±20ppm absolute, ±6ppm 0C to 50C, 32pF, 25Ω)

The output clock should be connected directly (not

AC coupled) to the OSCi input of the MT9044, and

the OSCo output should be left open as shown in

Figure 9.

Guard Time Adjustment

Excessive switching of the timing reference (from

PRI to SEC) in the MT9044 can be minimized by ﬁrst

entering Holdover Mode for

a

predetermined

Crystal Oscillator

-

Alternatively,

a

Crystal

maximum time (i.e., guard time). If the degraded

signal returns to normal before the expiry of the

guard time (e.g. 2.5 seconds), then the MT9044 is

returned to its Normal Mode (with no reference

switch taking place). Otherwise, the reference input

may be changed from Primary to Secondary.

Oscillator may be used. A complete oscillator circuit

made up of a crystal, resistor and capacitors is

shown in Figure 10.

MT9044

OSCi

MT9044

GTo

20MHz

1MΩ

R

+

150kΩ

56pF

39pF

3-50pF

C

10uF

OSCo

100Ω

1uH

GTi

1uH inductor: may improve stability and is optional

R

P

1kΩ

Figure 10 - Crystal Oscillator Circuit

Figure 11 - Symmetrical Guard Time Circuit

The accuracy of a crystal oscillator depends on the

crystal tolerance as well as the load capacitance

tolerance. Typically, for a 20MHz crystal speciﬁed

with a 32pF load capacitance, each 1pF change in

load capacitance contributes approximately 9ppm to

the frequency deviation. Consequently, capacitor

tolerances, and stray capacitances have a major

effect on the accuracy of the oscillator frequency.

A simple way to control the guard time (using

Automatic Control) is with an RC circuit as shown in

Figure 11. Resistor R is for protection only and

P

limits the current ﬂowing into the GTi pin during

power down conditions. The guard time can be

calculated as follows.

V

DD

– V

---------------------------------

guard

= RC × ln

≈ RC × 0.6

The trimmer capacitor shown in Figure 10 may be

time

V

DD

SIH

used to compensate for capacitive effects.

If

accuracy is not a concern, then the trimmer may be

removed, the 39pF capacitor may be increased to

56pF, and a wider tolerance crystal may be

substituted.

time

example

guard

≈ 150k × 10u × 0.6= 0.9s

time

The crystal should be a fundamental mode type - not

an overtone. The fundamental mode crystal permits

a simpler oscillator circuit with no additional ﬁlter

components and is less likely to generate spurious

responses. The crystal speciﬁcation is as follows.

•

V_SIHis the logic high going threshold level for the

GTi Schmitt Trigger input, see DC Electrical

Characteristics

In cases where fast toggling might be expected of

the LOS1 input, then an unsymmetrical Guard Time

Circuit is recommended. This ensures that reference

switching doesn’t occur until the full guard time value

has expired. An unsymmetrical Guard Time Circuit

is shown in Figure 12.

Frequency:

20MHz

As required

Fundamental

Parallel

32pF

Tolerance:

Oscillation Mode:

Resonance Mode:

Load Capacitance:

Maximum Series Resistance:

Approximate Drive Level:

35Ω

1mW

16

Advance Information

MT9044

For instance, 10 Normal to Holdover to Normal mode

change sequences occur, and in each case Holdover

was entered for 2s. Each mode change sequence

could account for a phase change as large as 350ns.

Thus, the accumulated phase change could be as

large as 3.5us, and, the overall MTIE could be as

large as 3.5us.

MT9044

GTo

+

R

C

150kΩ

R

D

1kΩ

C

10uF

Phase

= 0.05ppm × 2s = 100ns

= 50ns + 200ns= 250ns

hold

state

GTi

R

P

= 10 × (250ns + 100ns) = 3.5us

1kΩ

10

Figure 12 - Unsymmetrical Guard Time

Circuit

•

0.05ppm is the accuracy of Holdover Mode

50ns is the maximum phase continuity of the

MT9044 from Normal Mode to Holdover Mode

Figure 13 shows a typical timing example of an

unsymmetrical Guard Time Circuit with the MT9044

in Automatic Control.

•

200ns is the maximum phase continuity of the

MT9044 from Holdover Mode to Normal Mode (with

or without TIE Corrector Circuit)

TIE Correction (using GTi)

When 10 Normal to Holdover to Normal mode

change sequences occur without MTIE enabled, and

in each case holdover was entered for 2s, each

mode change sequence could still account for a

phase change as large as 350ns. However, there

would be no accumulated phase change, since the

input to output phase is re-aligned after every

Holdover to Normal state change. The overall MTIE

would only be 350ns.

When Primary Holdover Mode is entered for short

time periods, TIE correction should not be enabled.

This will prevent unwanted accumulated phase

change between the input and output. This is mainly

applicable to Manual Control, since Automatic

Control together with the Guard Time Circuit

inherently operate in this manner.

SEC

SIGNAL

STATUS

GOOD

LOS2

PRI

SIGNAL

STATUS

GOOD

BAD

GOOD

BAD

T

D

LOS1

GTo

GTi

V

SIH

MT9044

STATE

PRI

NORMAL

PRI

HOLDOVER

PRI

NORMAL

PRI

HOLDOVER

SEC

NORMAL

PRI

NORMAL

NOTES:

1. T represents the time delay from when the reference goes

D

bad to when the MT9044 is provided with a LOS indication.

Figure 13 - Automatic Control, Unsymmetrical Guard Time Circuit Timing Example

17

MT9044

Advance Information

Reset Circuit

Dual T1 Reference Sources with MT9044 in

Automatic Control

A simple power up reset circuit with about a 50us

reset low time is shown in Figure 14. Resistor R is

For systems requiring simple state machine control,

the application circuit shown in Figure 15 using

Automatic Control may be used.

P

for protection only and limits current into the RST pin

during power down conditions. The reset low time is

not critical but should be greater than 300ns.

In this circuit, the MT9044 is operating Automatically,

using a Guard Time Circuit, and the LOS1 and LOS2

inputs to determine all mode changes. Since the

Guard Time Circuit is set to about 1s, all line

interruptions (LOS1=1) less than 1s will cause the

MT9044 to go from Primary Normal Mode to

Holdover Mode and not switch references. For line

interruptions greater than 1s, the MT9044 will switch

MT9044

+5V

R

10kΩ

Modes from Holdover to Secondary

Normal,

RST

provided that the secondary signal is valid (LOS2=0).

After receiving a good primary signal (LOS1=0), the

MT9044 will switch back to Primary Normal Mode

For complete Automatic Control state machine

details, refer to Table 5 for the State Table, and

Figure 8 for the State Diagram.

R

P

1kΩ

C

10nF

Figure 14 - Power-Up Reset Circuit

MT9074

To Line 1

DSTo

TTIP

DSTi

To

TX Line

XFMR

TRING

F0i

C4i

RTIP

To

RX Line

XFMR

RRING

MT9044

F0o

PRI

E1.5o

LOS

C4o

SEC

LOS1

LOS2

+ 5V

FS1

MS1

FS2

150kΩ

1kΩ

MS2

RSEL

MT9074

To Line 2

GTo

GTi

DSTo

DSTi

TTIP

TRST

RST

TRING

To

TX Line

XFMR

1kΩ

OSCi

+

F0i

C4i

RTIP

+ 5V

10kΩ

10uF

RRING

To

RX Line

XFMR

10nF

E1.5o

LOS

CLOCK

Out

20MHz ±32ppm

MT8985

STo0

STi0

STo1

STi1

F0i

C4i

Figure 15 - Dual T1 Reference Sources with MT9044 in 1.544MHz Automatic Control

18

Advance Information

MT9044

To Line 1

MT9075

DSTo

DSTi

TTIP

To

TX Line

XFMR

TRING

F0i

C4i

RTIP

To

RX Line

XFMR

RRING

MT9044

RxFP

LOS

F0o

PRI

C4o

SEC

C1.5o

LOS1

LOS2

+ 5V

FS1

FS2

MS1

MS2

RSEL

MT9075

To Line 2

DSTo

DSTi

TTIP

GTi

TRST

RST

To

TX Line

XFMR

CLOCK

Out

20MHz ±32ppm

TRING

OSCi

F0i

C4i

RTIP

RRING

To

RX Line

XFMR

RxFP

LOS

External Stimulus

CONTROLLER

MT8985

STo0

STi0

STo1

STi1

F0i

C4i

Figure 16 - Dual E1 Reference Sources with MT9044 in 8kHz Manual Control

Dual E1 Reference Sources with MT9044 in

Manual Control

circuit reset pin (TCLR), and a complete device reset

is done with the RST pin.

The controller uses two stimulus inputs (LOS)

directly from the MT9075 E1 interfaces, as well as an

external stimulus input. The external input may

come from a device that monitors the status registers

of the E1 interfaces, and outputs a logic one in the

event of an unacceptable status condition.

For systems requiring complex state machine

control, the application circuit shown in Figure 16

using Manual Control may be used.

In this circuit, the MT9044 is operating Manually

and is using a controller for all mode changes. The

controller sets the MT9044 modes (Normal, Holdover

or Freerun) by controlling the MT9044 mode/control

select pins (MS2 and MS1). The input (Primary or

Secondary) is selected with the reference select pin

(RSEL). TIE correction from Primary Holdover Mode

to Primary Normal Mode is enabled and disabled

with the guard time input pin (GTi). The input to

output phase alignment is re-aligned with the TIE

For complete Manual Control state machine details,

refer to Table 4 for the State Table, and Figure 7 for

the State Diagram.

19

MT9044

Advance Information

To E1 Line

MT9075

DSTo

TTIP

DSTi

To

TX Line

XFMR

TRING

F0i

C4i

RTIP

To

RX Line

XFMR

RRING

MT9044

RxFP

LOS

F0o

C4o

PRI

C1.5o

LOS1

LOS2

+ 5V

FS1

FS2

MS1

MS2

RSEL

CLOCK

Out

20MHz ±32ppm

MT90840

To OC3 Line

STo0-7

STi0-7

PDo0-7

PPFTo

OSCi

To

TX Line

XFMR

TCLR

RST

C19o

ACKi

ACKo

1kΩ

F0i

C4b

PDi0-7

GTi

To

RX Line

XFMR

PCKR

PPFRi

+ 5V

PCKT

10kΩ

10nF

MT90820

STo0

STi0

STo1-8

STi1-8

F0i

C4i

Figure 17 - Single Source - E1 to STS-3 with 8kHz Reference

Single Reference Source E1 to STS-3 with 8 kHz

Reference

The device may operate in freerun mode or with a

single reference source. The 8 kHz output from the

MT9075 is sourced from the clock extracted from the

E1 trunk. It becomes the reference for the PLL which

then generates ST-BUS signals F0o, C4o and C2o to

form the system backplane clock. The MT90840

connects to the system backplane, as well as to an

OC3 link via an STS-3 Framer and optical link. The

19.44 Mhz clock required by the MT90840 is

generated by the MT9044. In the event that the E1

link is broken, the LOS output of the MT9075 goes

high placing the MT9044 in freerun mode.

20

Advance Information

MT9044

Absolute Maximum Ratings* - Voltages are with respect to ground (V ) unless otherwise stated.

SS

Parameter

Symbol

Min

Max

Units

1

2

3

4

5

6

Supply voltage

V_DD

-0.3

7.0

V_DD+0.3

20

V

Voltage on any pin

Current on any pin

Storage temperature

V

I

mA

°C

T_ST

-55

125

PLCC package power dissipation

P

900

mW

PD

MQFP package power dissipation

P

900

PD

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions* - * Voltages are with respect to ground (V_SS) unless otherwise stated.

Characteristics

Sym

Min

Max

Units

1

2

Supply voltage

Operating temperature

V_DD

T_A

4.5

-40

5.5

85

V

C

DC Electrical Characteristics* - * Voltages are with respect to ground (V ) unless otherwise stated.

SS

Characteristics

Supply current with: OSCi = 0V

OSCi = Clock

Sym

Min

Max

Units

Conditions/Notes

1

2

3

4

5

6

7

8

9

I_DDS

I_DD

10

90

mA

V

Outputs unloaded

TTL high-level input voltage

TTL low-level input voltage

CMOS high-level input voltage

CMOS low-level input voltage

Schmitt high-level input voltage

Schmitt low-level input voltage

Schmitt hysteresis voltage

V_IH

2.0

V_IL

0.8

V

V_CIH

V_CIL

V_SIH

V_SIL

V_HYS

I_IL

0.7V

V

OSCi

DD

0.3V

V

OSCi

DD

2.3

V

GTi, RST

0.8

V

0.4

-10

V

10 Input leakage current

11 High-level output voltage

12 Low-level output voltage

+10

uA

V

V =V or 0V

I DD

V_OH

0.8V

I_OH=4mA

I_OL=4mA

DD

V_OL

0.2V

V

DD

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

21

MT9044

Advance Information

AC Electrical Characteristics - Performance

Characteristics

Sym

Min

Max

Units Conditions/Notes†

1

2

3

4

5

6

7

8

9

Freerun Mode accuracy with OSCi at:

Holdover Mode accuracy with OSCi at:

Capture range with OSCi at:

±±0ppm

±32ppm

±100ppm

±0ppm

-0

+0

ppm

s

5-8

-32

+32

5-8

-100

+100

5-8

-0.05 +0.05

1,2,4,6-8,40

1-3,6-8

±32ppm

±100ppm

±0ppm

-230

-198

-130

+230

+198

+130

30

±32ppm

±100ppm

1-3,6-8

10 Phase lock time

1-3,6-14

1-2,4-14

1-,4,6-14

1-3,6-14

1-14,27

1-3,6,9-11

1-3,7,9-11

1-3,8-11

11 Output phase continuity with:

reference switch

200

50

ns

12

13

14

mode switch to Normal

mode switch to Freerun

mode switch to Holdover

ns

15 MTIE (maximum time interval error)

600

45

ns

16 Output phase slope

us/s

ppm

17 Reference input for Auto-Holdover with:

8kHz

1.544MHz

2.048MHz

-18k

-36k

+18k

+36k

18

19

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - Voltages are

with respect to ground (V ) unless otherwise stated.

SS

Characteristics

Sym

Schmitt

TTL

CMOS

Units

1

2

3

Threshold Voltage

V

1.5

2.3

0.8

1.5

2.0

0.8

0.5V

0.7V

0.3V

V

T

DD

Rise and Fall Threshold Voltage High

Rise and Fall Threshold Voltage Low

V

HM

V

LM

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

* Timing for input and output signals is based on the worst case result of the combination of TTL and CMOS thresholds.

* See Figure 18.

Timing Reference Points

V

HM

T

LM

V

ALL SIGNALS

V

t

_IRF,t_ORF

t_IRF,t_ORF

Figure 18 - Timing Parameter Measurement Voltage Levels

22

Advance Information

MT9044

AC Electrical Characteristics - Input/Output Timing

Characteristics

Sym

Min

Max

Units

1

Reference input pulse width high or low

Reference input rise or fall time

8kHz reference input to F8o delay

1.544MHz reference input to F8o delay

2.048MHz reference input to F8o delay

F8o to F0o delay

t

100

ns

RW

2

10

6

IRF

3

t

-21

337

222

110

11

R8D

4

t

363

238

134

35

R15D

5

t

R2D

6

t

F0D

7

F16o setup to C16o falling

F16o hold from C16o rising

F8o to C1.5o delay

t

F16S

F16H

C15D

8

t

0

20

9

t

-51

-3

-37

11

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

F8o to C6o delay

t

C6D

C3D

C2D

C4D

C8D

F8o to C3o delay

-51

-13

-10

0

-37

2

F8o to C2o delay

F8o to C4o delay

2

F8o to C8o delay

2

F8o to C16o delay

t

2

C16D

TSPD

RSPD

F8o to TSP delay

t

10

F8o to RSP delay

t

10

F8o to C19o delay

t

52

C19D

C1.5o pulse width high or low

C3o pulse width high or low

C6o pulse width high or low

C2o pulse width high or low

C4o pulse width high or low

C8o pulse width high or low

C16o pulse width high or low

TSP pulse width high

t

309

149

72

339

175

86

C15W

t

C3W

C6W

C2W

C4W

C8W

230

111

52

258

133

70

t

24

35

C16WL

t

478

474

16

494

491

36

TSPW

RSP pulse width high

t

RSPW

C19o pulse width high or low

F0o pulse width low

t

C19W

t

230

111

52

258

133

70

F0WL

F8WH

F8o pulse width high

t

F16o pulse width low

t

F16WL

Output clock and frame pulse rise or fall time

Input Controls Setup Time

Input Controls Hold Time

t

9

ORF

t

100

S

t

H

† See "Notes" following AC Electrical Characteristics tables.

23

MT9044

Advance Information

t

R8D

PRI/SEC

8kHz

t

RW

V

T

t

R15D

PRI/SEC

RW

1.544MHz

V

T

R2D

t

PRI/SEC

RW

2.048MHz

V

T

V

T

F8o

NOTES:

1. Input to output delay values

are valid after a TRST or RST

with no further state changes

Figure 19 - Input to Output Timing (Normal Mode)

t

F8WH

F0D

V

T

F8o

F0o

t

F0WL

t

F16WL

F16o

t

F16S

F16H

t

C16WL

t_C16D

C16o

C8o

t

C8W

t

C8D

C4D

C2D

t

C4W

t

C4o

C2o

t

C2W

V

T

t

C6W

t

C6D

C6o

t

C3W

C3D

V

T

C3o

t

C15D

C15W

V

T

C1.5o

t

C19W

t

C19D

t

C19W

V

T

C19o

Figure 20 - Output Timing 1

24

Advance Information

MT9044

F8o

C2o

V

T

V

T

t_RSPD

V

T

RSP

TSP

t

RSPW

TSPW

V

T

t

TSPD

Figure - 21 Output Timing 2

V

T

F8o

t

S

H

MS1,2

V

T

LOS1,2

RSEL, GTi

Figure 22 - Input Controls Setup and Hold Timing

AC Electrical Characteristics - Intrinsic Jitter Unﬁltered

Characteristics

Sym

Min

Max

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Intrinsic jitter at F8o (8kHz)

0.0002

0.030

0.040

0.060

0.120

0.080

0.160

0.320

0.0002

0.10

UIpp

1-14,21-24,28

1-14,21-24,29

1-14,21-24,30

1-14,21-24,31

1-14,21-24,32

1-14,21-24,33

1-14,21-24,34

1-14,21-24,28

1-14,21-24,41

Intrinsic jitter at F0o (8kHz)

Intrinsic jitter at F16o (8kHz)

Intrinsic jitter at C1.5o (1.544MHz)

Intrinsic jitter at C2o (2.048MHz)

Intrinsic jitter at C3o (3.088MHz)

Intrinsic jitter at C6o (6.312MHz)

Intrinsic jitter at C4o (4.096MHz)

Intrinsic jitter at C8o (8.192MHz)

10 Intrinsic jitter at C16o (16.384MHz)

11 Intrinsic jitter at TSP (8kHz)

12 Intrinsic jitter at RSP (8kHz)

13 Intrinsic jitter at C19o (19.44MHz)

† See "Notes" following AC Electrical Characteristics tables.

25

MT9044

Advance Information

AC Electrical Characteristics - C1.5o (1.544MHz) Intrinsic Jitter Filtered

Characteristics

Sym

Min

Max

Units

Conditions/Notes†

1

2

3

4

Intrinsic jitter (4Hz to 100kHz ﬁlter)

Intrinsic jitter (10Hz to 40kHz ﬁlter)

Intrinsic jitter (8kHz to 40kHz ﬁlter)

Intrinsic jitter (10Hz to 8kHz ﬁlter)

0.015

0.010

0.005

UIpp

1-14,21-24,29

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - C2o (2.048MHz) Intrinsic Jitter Filtered

Characteristics

Sym

Min

Max

Units

Conditions/Notes†

1

2

3

4

Intrinsic jitter (4Hz to 100kHz ﬁlter)

Intrinsic jitter (10Hz to 40kHz ﬁlter)

Intrinsic jitter (8kHz to 40kHz ﬁlter)

Intrinsic jitter (10Hz to 8kHz ﬁlter)

0.015

0.010

0.005

UIpp

1-14,21-24,30

† See "Notes" following AC Electrical Characteristics tables

AC Electrical Characteristics - 8kHz Input to 8kHz Output Jitter Transfer

Characteristics

Sym Min Max Units

Conditions/Notes†

1

2

3

4

5

6

Jitter attenuation for 1Hz@0.01UIpp input

Jitter attenuation for 1Hz@0.54UIpp input

Jitter attenuation for 10Hz@0.10UIpp input

Jitter attenuation for 60Hz@0.10UIpp input

Jitter attenuation for 300Hz@0.10UIpp input

Jitter attenuation for 3600Hz@0.005UIpp input

0

6

dB

1-3,6,9-14,21-22,24,28,35

6

16

22

38

12

28

42

45

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - 1.544MHz Input to 1.544MHz Output Jitter Transfer

Characteristics

Sym Min Max Units

Conditions/Notes†

1

2

3

4

5

6

7

Jitter attenuation for 1Hz@20UIpp input

Jitter attenuation for 1Hz@104UIpp input

Jitter attenuation for 10Hz@20UIpp input

Jitter attenuation for 60Hz@20UIpp input

Jitter attenuation for 300Hz@20UIpp input

Jitter attenuation for 10kHz@0.3UIpp input

Jitter attenuation for 100kHz@0.3UIpp input

0

6

dB

1-3,7,9-14,21-22,24,29,35

6

16

22

38

12

28

42

45

† See "Notes" following AC Electrical Characteristics tables.

26

Advance Information

MT9044

AC Electrical Characteristics - 2.048MHz Input to 2.048 MHz Output Jitter Transfer

Characteristics

Sym Min

Max

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Jitter at output for 1Hz@3.00UIpp input

with 40Hz to 100kHz ﬁlter

2.9

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

0.09

1.3

Jitter at output for 3Hz@2.33UIpp input

with 40Hz to 100kHz ﬁlter

0.10

0.80

0.10

0.40

0.10

0.06

0.05

0.04

0.03

0.04

0.02

Jitter at output for 5Hz@2.07UIpp input

with 40Hz to 100kHz ﬁlter

Jitter at output for 10Hz@1.76UIpp input

with 40Hz to 100kHz ﬁlter

Jitter at output for 100Hz@1.50UIpp input

10 with 40Hz to 100kHz ﬁlter

11 Jitter at output for 2400Hz@1.50UIpp input

12 with 40Hz to 100kHz ﬁlter

13 Jitter at output for 100kHz@0.20UIpp input

14 with 40Hz to 100kHz ﬁlter

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - 8kHz Input Jitter Tolerance

Characteristics

Sym

Min

Max

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

Jitter tolerance for 1Hz input

Jitter tolerance for 5Hz input

Jitter tolerance for 20Hz input

Jitter tolerance for 300Hz input

Jitter tolerance for 400Hz input

Jitter tolerance for 700Hz input

Jitter tolerance for 2400Hz input

Jitter tolerance for 3600Hz input

0.80

0.70

0.60

0.20

0.15

0.08

0.02

0.01

UIpp

1-3,6,9-14,21-22,24-26,28

† See "Notes" following AC Electrical Characteristics tables.

27

MT9044

Advance Information

AC Electrical Characteristics - 1.544MHz Input Jitter Tolerance

Characteristics

Sym

Min

Max

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Jitter tolerance for 1Hz input

Jitter tolerance for 5Hz input

Jitter tolerance for 20Hz input

Jitter tolerance for 300Hz input

Jitter tolerance for 400Hz input

Jitter tolerance for 700Hz input

Jitter tolerance for 2400Hz input

Jitter tolerance for 10kHz input

Jitter tolerance for 100kHz input

150

140

130

35

25

15

4

UIpp

1-3,7,9-14,21-22,24-26,29

1

0.5

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - 2.048MHz Input Jitter Tolerance

Characteristics

Sym

Min

Max

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Jitter tolerance for 1Hz input

Jitter tolerance for 5Hz input

Jitter tolerance for 20Hz input

Jitter tolerance for 300Hz input

Jitter tolerance for 400Hz input

Jitter tolerance for 700Hz input

Jitter tolerance for 2400Hz input

Jitter tolerance for 10kHz input

Jitter tolerance for 100kHz input

150

140

130

50

40

20

5

UIpp

1-3,8,9-14,21-22,24-26,30

1

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - OSCi 20MHz Master Clock Input

Characteristics

Sym

Min

Max

Units

Conditions/Notes†

1

2

3

4

5

6

Frequency accuracy

-0

-32

-100

40

+0

+32

+100

60

ppm

%

15,18

16,19

17,20

(20 MHz nominal)

Duty cycle

Rise time

Fall time

10

ns

10

ns

† See "Notes" following AC Electrical Characteristics tables.

28

Advance Information

MT9044

† Notes:

Voltages are with respect to ground (V ) unless otherwise stated.

SS

Supply voltage and operating temperature are as per Recommended Operating Conditions.

Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels

1. PRI reference input selected.

2. SEC reference input selected.

3. Normal Mode selected.

4. Holdover Mode selected.

5. Freerun Mode selected.

6. 8kHz Frequency Mode selected.

7. 1.544MHz Frequency Mode selected.

8. 2.048MHz Frequency Mode selected.

9. Master clock input OSCi at 20MHz ±0ppm.

10. Master clock input OSCi at 20MHz ±32ppm.

11. Master clock input OSCi at 20MHz ±100ppm.

12. Selected reference input at ±0ppm.

13. Selected reference input at ±32ppm.

14. Selected reference input at ±100ppm.

15. For Freerun Mode of ±0ppm.

16. For Freerun Mode of ±32ppm.

17. For Freerun Mode of ±100ppm.

18. For capture range of ±230ppm.

19. For capture range of ±198ppm.

20. For capture range of ±130ppm.

21. 25pF capacitive load.

22. OSCi Master Clock jitter is less than 2nspp, or 0.04UIpp where1UIpp=1/20MHz.

23. Jitter on reference input is less than 7nspp.

24. Applied jitter is sinusoidal.

25. Minimum applied input jitter magnitude to regain synchronization.

26. Loss of synchronization is obtained at slightly higher input jitter amplitudes.

27. Within 10ms of the state, reference or input change.

28. 1UIpp = 125us for 8kHz signals.

29. 1UIpp = 648ns for 1.544MHz signals.

30. 1UIpp = 488ns for 2.048MHz signals.

31. 1UIpp = 323ns for 3.088MHz signals.

32. 1UIpp = 244ns for 4.096MHz signals.

33. 1UIpp = 122ns for 8.192MHz signals.

34. 1UIpp = 61ns for 16.384MHz signals.

35. No ﬁlter.

36. 40Hz to 100kHz bandpass ﬁlter.

37. With respect to reference input signal frequency.

38. After a RST or TRST.

39. Master clock duty cycle 40% to 60%.

40. Prior to Holdover Mode, device was in Normal Mode and phase locked.

41. 1Ulpp = 51ns for 19.44MHz signals.

29

http://www.mitelsemi.com

World Headquarters - Canada

Tel: +1 (613) 592 2122

Fax: +1 (613) 592 6909

North America

Tel: +1 (770) 486 0194

Fax: +1 (770) 631 8213

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Tel: +65 333 6193

Fax: +65 333 6192

Europe, Middle East,

and Africa (EMEA)

Tel: +44 (0) 1793 518528

Fax: +44 (0) 1793 518581

Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no

liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of

patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or

service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever.

Purchasers of products are also hereby notiﬁed that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or

other intellectual property rights owned by Mitel.

This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or

contract nor to be regarded as a representation relating to the products or services concerned. The products, their speciﬁcations, services and other information appearing in this

publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or

service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speciﬁc

piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or

data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in

any medical products whose failure to perform may result in signiﬁcant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s

conditions of sale which are available on request.

M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation

Mitel Semiconductor is an ISO 9001 Registered Company

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