LE792388VQC [MICROSEMI]
PCM Codec,;
| 型号： | LE792388VQC |
| 厂家： | 
Microsemi |
| 描述： | PCM Codec, PC 电信 电信集成电路 |
| 文件： | 总63页 (文件大小：1492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
Le79238
Octal Subscriber Line Audio-Processing Circuit
Next Generation Carrier Chipset (NGCC)
Data Sheet
Document ID#: 081193
Version 17
June 2012
Applications
•
Cost-effective voice solution for long or short
loops providing POTS, IVD and integrated test
capabilities:
Ordering Information
Le792388TVC 176-Pin LQFP (Green)1 Tr3
Le792388VQC 164-Pin LGA (Green)1 Tray
ZL792388GDG 196-Pin BGA (RoHS-5)2 Tra
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•
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•
IVD, DLC, CO
ZL792388GDF 196-Pin BGA (RoHS-5)2 Tape el
ZL792388GDG2 196-Pin BGA (Gen)1 Tray
Voice-enabled DSLAM
PBX/KTS
ZL792388GDF2 196-Pin BG(Gree1 Tape anReel
1. The green package meets oHS Directiv2002/95C of the
European Council to mize the environmal impact of
electrical equipment
MDU, MSAP, MSAN
2. The RoHS-5 package is compliwith the requirements of the
European UnionRestriction on Uof Hazardous Substances
(“RoHS”) Directive, 002/95/EC, with e following Exemption:
Lead (Pb) in the soldeerminations used in the product.
Features
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•
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Optimized for Next Generation Broadband xDSL
and triple play applications
3. For a apackinystem, add a "T" suffix.
Eliminates CO transients that could cause CRC
errors
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•
Standard CM and MPI digital interfaces
General purpse I/O pins, can be used as relay
drivrs
Best-in-class testing, GR-844 equivalent with
Next Generation VoiceEdgeTM Control Processor
(NGVCP)
Fatures with Le79124 NGVCP
•
•
Wideband 16 kHz sampling mode capability (
product code F and later revisions)
72 hannel call aggregation
GR-844 equivalent line testing
Ideal for high density, medium and larg
count applications
•
•
API-compatible with VE790 Series dsigns
High performance digital sigal process
provides programmable ctrol of all major ine
card functions
2
4
8
VDD33
VDD18
AVDDxx
A1/B1
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
LD1
4
P0-P2, SEL
8
6
8
•
•
A-law/µ-law and near co/filter
DGND
AGND
A2/B2
A3/B3
A4/B4
LD2
LD3
Transmit and receivgain, To-wire AC
8
8
8
IO_0, IO_1
impedance, Transhybribalanc, Equalization
TSCA, TSCB
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•
DC loop feing
Lopervisi
DRA, DRB
DXA, DXB
FS
LD4
LD5
8
8
ng geration and ring-trip
Octal SLAC
PCLK
A5/B5
CS
RST
•
ration and shaping (12 kHz and
1
A6/B6
A7/B7
A8/B8
LD6
LD7
INT
DCLK
8
8
•
Enhanced line control and line-test support
DIN
DOUT
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•
TMF and Modem Tone Detection
IREF
LD8
GR-909 plus extensive line and self test
capabilities
SLB
SHB
SPB
BATL
BATH
BATP
•
Tone generation (DTMF, FSK, and arbitrary
tone)
Figure 1 - Block Diagram
1
Microsemi Corporation
Le79238
Data Sheet
Related Literature
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126583 NGCC Hardware Design Guide
128623 NGCC Designer’s Guide
081555 Le79271 NGSLIC Device Data Sheet
138884 Le79272 Dual NGSLIC Device Data Sheet
136868 ZL79258 External Ringing NGSLAC Device Data Sheet
081567 Le79124 NGVCP Device Data Sheet
133514 Le79234 NGVCP Device Data Sheet
127671 Le79124-SW NGVCP Software Package
133545 Le79234-SW NGVCP Software Package
135486 LE71SK7920-SW Ve792 Software Package
127063 VoicePath™ Profile Wizard User’s Guide
VoicePath™ API-II Reference Guide
Description
The Le79238 Next Generation Octal Subscriber Line Aud-processing rcuit (SLAC), in combination with the
Le79271 SLIC, implements a DSL friendly, high density 8channel uiversal tephone line interface with wideband
capability. This enables the design of a low cost, high perrmane, fully software programmable line interface with
worldwide applicability. All AC, DC, and signaling parametare progrmmable via a microprocessor interface.
The Le79238 has an integrated test tool box whibe usestandlone or with an NGVCP to resolve faults to
the line or line circuit.
Change Summary
Below are the changes from the Mrch 20versione 2012 version.
Page
8, 9
Section
1.0
Description
Ennced product description.
26
7.1, No. 11 & Reducpower dissipation values. Test and use condition values provided.
N
27
7.2, o. 4
Expanded idle channel noise test description.
2
Microsemi Corporation
Le79238
Data Sheet
Table of Contents
1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Wideband Codec Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Le79238 Device Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Features of the NGCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.0 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3.0 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 Green Package Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.0 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Electrical Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.0 Programming of the SLAC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Ringing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4 Tone and Metering Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 AC/DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Transmission Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.3 Transmit and Receive Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.4 Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.5 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.6 Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.7 Gain Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.8 Total Distortion Including Quantizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.9 Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.10 Discrimination Against Out-of-and In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.11 Spurious Out-of-Band Signals ahe Anaut. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.0 Reset at Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.0 Host Bus Control Interfae (HBI) Overvie. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1 Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1.1 Interface Addressg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1.2 Command ructure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1.3 Paged Offset ccess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.1.4 Diect Page OffsAccess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.1.5 StaMailbox c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.1.6 Contine Mailbox Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
nfigurInterfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
t Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CL Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ciated Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.2 Cding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.2.1 Code Load Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.2.2 Host Boot Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2.3 Partial Code Load Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.Application Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.4 Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.4.1 Microprocessor Interface (MPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.0 PCM Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1 PCM Transmit Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3
Microsemi Corporation - CMPG
Le79238
Data Sheet
Table of Contents
10.2 PCM Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.3 PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.0 P-Bus and GPIO Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.1 SLIC Device Bus Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12.0 Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
13.0 Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13.1 176-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13.2 164-Pin LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.3 196-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4
Microsemi Corporation - CMPG
Le79238
Data Sheet
List of Figures
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - NGCC System with Le79124 VCP Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3 - Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4 - 196-Pin BGA Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5 - 164-Pin Land Grid Array (LGA) Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 6 - 176-Pin LQFP Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 - Narrowband Transmit Path Attenuation vs. Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 8 - Narrowband Receive Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9 - Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10 - A-law Gain Linearity with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11 - µ-law Gain Linearity with Tone Input (Both Paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12 - Total Distortion with Tone Input, Both Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13 - A/A Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 14 - Discrimination Against Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15 - Spurious Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16 - Reset Sequence when VDD33 and VDD18 are Powered Up Separately . . . . . . . . . . . . . . . . . . . . . 35
Figure 18 - Host Bus Interface Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19 - Host Bus Interface Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20 - NGCC SLAC Programmer’s Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 21 - 4-wire Master-Slave Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22 - 3-wire Master-Slave Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23 - CS Framing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 24 - One Data Word Write in Byte Frami. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 25 - One Data Word Read in Word Fr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 26 - Microprocessor Interface (Input M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 27 - Microprocessor Interface (Otput Mo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 28 - PCM Highway 8-bit Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 29 - PCM Highway 16-bit ransfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 30 - PCM Highway Timng for XE = 0 (Trsmit on Negative PCLK Edge) . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 31 - PCM Highway Ting for E = 1 (Transmit on Positive PCLK Edge) . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 32 - Channel Timng for Ps SLIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 33 - Global Timing r SLIC evice Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 34 - SLIC Device Bus iming Wveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 35 - OpeRelay Dvers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5
Microsemi Corporation
Le79238
Data Sheet
List of Tables
Table 1 - 196-Pin BGA Pin Numbers and Pin Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2 - 164-Pin LGA Pin Numbers and Pin Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3 - AC/DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4 - Transmission Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 5 - Wideband Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 6 - Minimum Specifications for Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7 - Limits for Spurious Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8 - Recommended Reset Sequence Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9 - Host Bus Interface Transport Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10 - CL Page Base Address High Register (User) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11 - CL Page Base Address Low Register (User) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 12 - CL Page CRC High Register (User) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 13 - CL Page CRC Low Register (User). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 14 - Mailbox Flag Register (User and DSP, located in DSPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 15 - SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 16 - MPI Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 17 - PCM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 18 - PCM Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 19 - P-Bus and SLAC IO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 20 - SLIC Device Bus Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6
Microsemi Corporation
Le79238
Data Sheet
1.0 Product Description
The Next Generation Carrier Chipset integrates all the functions of eight voice subscriber lines. Eight Le79271 SLIC
devices and one Le79238 Octal SLAC device make up the chipset.
•
•
The Le79271 SLIC device is a high voltage, bipolar IC that drives the subscriber line and senses line
conditions.
The Le79238 SLAC device is a low voltage CMOS IC that provides conversion and DSP funcions for eight
channels and senses line conditions.
The SLIC device is built with a high voltage bipolar technology to provide the power necessary twi
variety of subscriber lines. It can be programmed by the SLAC device to operate in eigt differendes that
control power consumption and signaling. The SLIC design is based on a voltage feed, urrensense ahitecture.
The SLAC device processes information regarding line voltage and loop current fm the SLIC dvice. he SLIC
device senses the A and B lead currents, computes the metallic loop current nd fds it in analoform to the
SLAC device. The SLAC device also senses A and B lead voltages and monitors battery oltage levels.
•
•
•
The output signals supplied by the SLAC device to the SLIC device are:
A lead (DCA) and B lead (DCB) DC voltages for DC feed or internal ringing.
AC transmission and 12 or 16 kHz metering signals (on the RC, RCVP
The SLAC device controls the SLIC device mode via the SLIC control buP0-P2, SEL and the load signal LD.
•
The SLAC device contains high-performance circuitthat prove A/D aD/A conversion for voice
(codec/filter), DC-feed control, ringing, and supervisin signls. The SLAC device contains a DSP core that
handles signaling, DC-feed, supervision and line diagnscs for all eght channels. The DSP core also
interfaces to a standard PCM/MPI backplane. se funcons invove converting an analog voice signal into
digital PCM samples and converting digitaples bck to an analog signal. During conversion,
digital filters are used to band-limit the ve PCM codes can be:
•
•
•
•
8-bit companded A-law with 8 kHz sampli
8-bit companded µ-law with 8 kHz smpling
16-bit linear two’s-complemet with 8 kHsampli
16-bit linear two’s-complment with 16 kHz mpling (wideband mode)
The SLAC device provides a omlete software configurable solution to the BORSCHT functions as well as
complete programmable control ver subscriber line DC-feed characteristics, such as current limit and feed
resistance. In addition, the LAC dece provides extensive loop supervision capability including off-hook, ring-trip
and ground-key detection. Detction thesholds for these functions are programmable. A programmable debounce
timer is available at elnates lse detection due to contact bounce.
User-programmable lters include receive and transmit gain and bandwidth, transhybrid balance, two-wire
termindanceand frequency attenuation (equalization) of the receive and transmit signals. All
progl filter coefficients can be calculated using WinSLAC™ software. This PC software allows the
desiescription of system requirements, WinSLAC™ then computes the necessary coefficients and
plots stem results.
7
Microsemi Corporation
Le79238
Data Sheet
The main functions that can be observed and/or controlled through the SLAC device backplane interface are:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Narrowband 3.4 kHz or wideband 7.0 kHz codec modes
DC-feed characteristics
Ground-key detection
Off-hook detection
DTMF tone detection
Modem tone detection
Metering signal
DC voltages on A and B leads
Subscriber line voltage and currents
Ring-trip detection
Abrupt and smooth reversal
Subscriber line impedance matching
Ringing signal generation
Sophisticated line and circuit tests
These functions are all handled in a manner to limit voice sevice transientsMinimizing disturbances caused by the
CO line circuit helps to eliminate cyclic redundancy chec(CRC) erors in IVD ystems.
For subscriber line diagnostics, AC and DC line conditions cabe monitred using built in test tools. DTMF and
modem tone detection functions are also built-in. Mured pameters an be compared to programmed threshold
levels to set a pass/fail bit. Both longitudinal c resisne and capacitance can be measured, which
allows leakage resistance, line capacitance, to be identified.
The Le79124 Next Generation Voice Control Pr) provides integrated test software routines to perform
comprehensive line diagnostics. Self-tesand linabilities can resolve faults to the line or line circuit. In
addition, the VCP device provides ggregatd codecr and call control.
The SLAC device requires twpower supplies. Lw power consumption is achieved by use of a separate +1.8 VDC
supply for the DSP core and te DSP ore Power Reduction firmware algorithm. The analog and digital I/O circuitry
is powered from a +3.3 VDC sul
Figure 2 presents an overew of te NGCC system. Refer to the Next Generation Carrier Chipset Hardware
Design Guide (Document ID 16583) for detailed Application Circuits and Parts Lists for various applications.
8
Microsemi Corporation
Le79238
Data Sheet
+3.3 V
VCC
+3.3 V
+1.8 V
+3.3 V
+1.8 V
VDD18
DVDD
PLL_VDD
VDD18
VDD33
AVDDxx
RCVP
RCVPi
A1 (Tip)
AD
BD
RCVN
DCA
RCVNi
DCAi
GPIOx
GPIOx
CS
Protection
INT
B1 (Ring)
Le79124
VCP
Device
VREF
VREFi
Le79238
SLAC
Device
DCB
IMT
DCBi
CANCELi
IMTi
MPI
SPI
GPI
CONTROL
ONTROL
Le79271
SLIC
VIMTi
Device
VACi
IAi
IA
IB
IBi
LD
SEL
P0
LDi
SEL
P0
PLL_VSS
DVSS
PCM
P1
P1
P2
P2
BGND
AGND
PCM
P2
P0
DATA
SEL
P1
VB
ND
DG
Fure 2 - GCC Sm with Le79124 VCP Device
1.1 Wideband Codec ode
The Le79238 device cn be oted in a wideband mode to provide better voice quality. Wideband mode is
intended to be used with a acket bsed processor with an adaptive echo canceller algorithm.
When wideband mode is selecd, the nominal voice bandwidth is doubled to 7000 Hz. The wideband mode can be
selected on a pehannesin this mode, internal clocks are doubled, increasing the sampling rates of the
internal digital filterNarrowband and wideband modes require their own unique set of coefficients. Therefore if
switchinen PCoperating modes on a given channel, the coefficients must be reprogrammed.
In whe PCM interface transmits and receives two evenly spaced sets of 16-bit timeslots in each
framcts one timeslot during the first 62.5 µS of the frame. The first set of 16-bits will transmit or
receiis timeslot. The timeslot for the second set of 16-bits is generated automatically and placed
25/2 µirst timeslot.
Note: Wideband mode is supported by Product Code F and later revisions.
9
Microsemi Corporation
Le79238
Data Sheet
1.2 Le79238 Device Internal Block Diagram
DCLK
DOUT
DIN
RCVP1
RCVN1
DCA1
DCB1
VREF1
IA1
IB1
IMT1
VIMT1
VAC1
SVA1
SVB1
SLIC2
SLIC3
Microprocessor
Interface
CS
INT
Ch 1
A/D D/A Converters
Block
RST
SLIC1
LD1
LD2
LD3
L4
LD5
LD6
LD7
S
Control
Logic
LD8
SEL
P0
Ch 2
A/D D/A
Converters
Block
P1
P2
Ch 3
A/D D/A
Converters
Block
Ch 4
A/D D/A
Converters
Block
SLIC4
gital
nal
ssor
FS
PCLK
DXA
PCM
Interface
and
Time Slot
Assigner
5
A/D A
Convert
Block
TSCA
DRA
SLIC5
SLIC
LIC7
LIC8
DXB
TSCB
DRB
Ch 6
A/D D/A
Converters
Block
IO1_0
IO1_1
IO2_0
IO2_1
IO3_0
IO3_1
IO4_0
IO4_1
IO5_0
IO5_1
IO6_0
IO6_1
IO7_0
IO7_1
IO8_0
IO8_1
Ch 7
A/D D/A
Converters
Block
Logic Interface
Ch 8
A/D D/A
Converters
Block
SLB
SHB
SPB
IREF
Global Circuitry
Figure 3 - Internal Block Diagram
10
Microsemi Corporation
Le79238
Data Sheet
1.3 Features of the NGCC
•
•
•
•
•
Performs all battery feed, ringing, signaling, hybrid
and test (BORSCHT) functions
•
Programmable metering cadencing
•
•
Smooth polarity reversal
Controlled state changes to eliminate transients
that could cause CRC errors
Supports both loop-start and ground-start
signaling
Two or three chip solution supports high density,
multi-channel architecture
•
•
SPI and PCM interfaces
Exceeds LSSGR and CCITT central
requirements
Supports two negative batteries and one positive
battery
•
•
•
On-hook transmission
Single hardware design meets multiple country
requirements through software programming of:
Power/service denial ode
•
•
•
•
•
•
•
•
•
•
•
•
Ringing waveform and frequency
DC loop-feed characteristics and current-limit
Loop-supervision detection thresholds
Off-hook debounce circuit
Line-feed charactiss independeof battery
voltage
•
•
•
Low idle-powper line
Compatible with expensive protection networks
Monio-wire intrface voltages and currents
for subriber line dostics
Ground-key and ring-trip filters
Off-hook detect de-bounce interval
Two-wire AC impedance
•
•
•
Can monitand/or drive A and B lead
independentl
Auomatic CID and Signaling and FSK and DTMF
odes
Transhybrid balance impedance
Transmit and receive gains
Equalization
Tne gneration
•
•
•
Howler
Digital I/O pins
Call Progress
DTMF
A-law/µ-law and linear selection
•
•
Supports wideband 7.0 kHz odec mode
Supports internal ringing ith DC bas
•
•
•
•
•
Modem support
DTMF tone detection
•
•
•
Programmed ringing canc
Dial Pulse and Flash detection
Power-cross, fault, and foreign voltage detection
Integrated line-test and self-test features
Self-contained ringig genetion and control
Integrated ring-trip filteand sofware enabled
manual or tomringip mode
•
•
•
GR-909 and GR-844 equivalent
Built-in voice path test modes
15 kHz noise filter
•
•
Supports externaringing (with ZL79258 SLAC)
Suing geration with envelope
s
11
Microsemi Corporation
Le79238
Data Sheet
2.0 Connection Diagrams
B
F
G
A
C
E
H
J
K
L
M
N
P
D
1
2
3
4
5
6
7
8
9
10
11
12
13
1
BOTTOM VIEW
Figure 4 - 196-Pin BGA Diagram
12
Microsemi Corporation
Le79238
Data Sheet
BGA
Pin#
BGA
Pin#
BGA
Pin#
BGA
Pin#
BGA
Pin#
Pin Name
VAC1
Pin Name
Pin Name
Pin Name
Pin Name
A1
A2
A3
A4
A5
A6
D1
D2
D3
D4
D5
D6
CANCEL2
SVB2
G1
G2
G3
G4
G5
G6
VAC2
DCA2
VREF2
IA2
K1
K2
K3
K4
K5
K6
VIMT3
N1
IMT4
VIMT1
DCB3
N2
N3
N4
N5
6
SVA4
VREF4
IMT1
VREF1
VREF3
CANCEL1
VDD18_4A
TSCB
RSVD_B1
AVDD12A
RSVD_B3
AVDD34A
DGND_2
AGND2
IO1_1
A
L
DEBUG_
CLK
A7
DRA
D7
TSCA
G7
IO2_0
IO8_1
IO7_1
SLB
K7
IO4_0
N7
P2
A8
PCLK
DIN
D8
DCLK
G8
K8
IO_0
N8
EL
A9
D9
RST
G9
K9
DGND_3
DD56
RSV_B6
RCV
SVA6
N9
LD6
A10
A11
A12
A13
A14
B1
VDD18_3
DCB8
DCA8
VAC8
VIMT8
DCA1
SVB1
RCVN1
IB1
D10
D11
D12
D13
D14
E1
AVDD78A
RSVD_B8
RCVN8
DCA7
G10
G11
G12
G13
G14
H1
K10
K11
12
K13
K14
L1
N0
N11
N12
N13
N14
P1
DGND_4
IB5
IB7
RCVN7
SVB
ANCEL7
CACE3
SVB3
N3
RCVN5
SVB5
DCA5
VIMT4
VAC4
DCA4
DCB4
VDD18_1
LD2
VAC7
MT6
IMT2
VAC3
B2
E2
SVA2
H
L
DCA3
P2
B3
E3
RCVN2
RSVD_B2
AVDD
DD33_2
DGND_6
IO_0
L3
RCVN4
RSVD_B4
AGND3
AGND4
VDD33_1
RSVD_O
AGND5
AVDD56A
RSVD_B5
VREF5
SVB6
P3
B4
E4
L4
P4
B5
VDD18_4
DRB
E5
H
D2A
O2_1
IO4_1
IO5_1
IO6_1
SPB
L5
P5
B6
E6
H6
L6
P6
B7
DXA
E7
7
L7
P7
LD4
B8
FS
E8
H8
L8
P8
LD5
B9
DOUT
DGND_5
IB8
E9
GND8
AVD78
RSVD_B7
VREF7
DCB7
H9
L9
P9
LD7
B10
B11
B12
B13
B1
E1
E11
E12
E13
E14
H10
H11
H12
H13
H14
L10
L11
L12
L13
L14
P10
P11
P12
P13
P14
VDD18_2
CANCEL5
IMT5
IA6
VREF8
VREF6
DCA6
VAC6
VIMT5
VAC5
VIMT7
CANCEL6
Table 1 - 196-Pin BGA Pin Numbers and Pin Names
13
Microsemi Corporation
Le79238
Data Sheet
BGA
Pin#
BGA
Pin#
BGA
Pin#
BGA
Pin#
BGA
Pin#
Pin Name
DCB1
Pin Name
Pin Name
Pin Name
Pin Name
C1
C2
C3
C4
C5
C6
F1
F2
F3
F4
F5
F6
VIMT2
DCB2
RCVP2
IB2
J1
J2
J3
J4
J5
J6
IMT3
M1
M2
M3
M4
M5
M6
CANCEL4
SVB4
SVA1
SVA3
RCVP3
IA3
RCVP1
IA1
RCVP4
IB4
DGND_1
IREF
AVDD34
IO3_1
AGND4A
LD1
DEBUG_
IO
AGND1
C7
DXB
F7
IO1_0
IO7_0
AGND7
RSVD_C
IA7
J7
IO3_0
IO6_0
AGND6
SHB
M7
P1
C8
CS
F8
J8
M8
P
C9
INT
F9
J9
M9
LD8
C10
C11
C12
C13
C14
AGND8A
IA8
F10
F11
F12
F13
F14
J10
J11
J12
J13
J14
M10
M11
12
M13
M14
ND5A
IA5
IB6
RCVP8
SVB8
CANCEL8
RCVP7
SVA7
RCVP6
DCB
MT6
RCV
SVA5
CB5
IMT7
Table 1 - 196-Pin BGA Pin umers and Pin Names
14
Microsemi Corporation
Le79238
Data Sheet
A1
A2
A66
A65
B1
B2
B57
B56
A3
A4
B3
B4
B55
B
A5
A6
62
1
B5
B6
B53
B52
A7
A8
A60
A59
B7
B8
B51
B
A9
A58
A57
A10
B9
B49
B48
A11
A12
A56
A55
B10
164-Pin LGA
B11
B12
B13
B47
B46
B45
A13
A14
A54
A53
A15
A16
A52
A51
B14
B44
B15
B16
B43
B42
A17
A18
A50
A49
B17
B18
B41
B40
A19
A20
A48
A47
osed Pad
B19
B39
A21
A22
A46
A45
TOP VIEW
Figure 5 - 164-Pin Land Grid Array (LGA) Diagram
15
Microsemi Corporation
Le79238
Data Sheet
LGA
Pin#
LGA
Pin#
LGA
Pin#
LGA
Pin#
LGA
Pin#
Pin Name
RCVN1
Pin Name
Pin Name
Pin Name
Pin Name
A1
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A
A56
57
A58
A59
A60
61
SEL
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A8
A87
A8
CANCEL8
IA8
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B
B24
B25
B2
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
SVB3
VIMT3
CANCEL3
DCA3
DCB3
RCVN3
IO3_1
SVA
IB4
B44
VREF6
RCVP6
IO6_0
B
A2
IO1_1
SVA2
IB2
LD6
B45
B46
B47
B48
49
B5
B51
B52
53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
A3
LD8
VREF8
RCVN8
IO8_1
IO8_0
INT
A4
SVA5
IB5
A5
VAC2
CANCEL2
IA2
I
A6
VAC5
IMT5
A7
VA7
IMT7
A8
DCA2
DCB2
RCVP2
IO2_0
SVA3
IB3
DCA5
VREF5
RCVN5
IO5_1
IO5_0
SVB6
VIMT6
AVDD56
IMT6
DOUT
DCLK
VDD33_2
PCLK
DXA
A9
DCA7
AVDD78
RCVP7
IO7_0
SVB8
VIMT8
IMT8
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A2
VAC4
IM4
VREF
RCVN4
IO4_1
VDD18_1
LD2
DXB
VAC3
IMT3
TSB
EBUG_I
SVA
IA3
DCA8
DCB8
RCVP8
RST
VREF3
AVDD34
RCVP3
IO3_0
SVB4
VIMT4
NC
DCA6
DCB6
RCVN6
IO6_1
SHB
1
LD4
P0
EL1
P2
LD5
VDD18_3
DIN
VREF1
NC
LD7
SLB
VDD18_2
SVB5
VIMT5
CANCEL5
IA5
CS
B7
VT7
CANCEL7
7
FS
CANCEL4
IA4
B1
B2
B3
B4
B5
RCVP1
IO1_0
DRA
VDD18_4
TSCA
DRB
DCA4
4
SVB2
VREF7
DCB7
VIMT2
AVDD12
DCB5
RCVP5
DEBUG_
CLK
A2
A30
A31
A32
A33
A62
A63
A64
A65
A66
RCVN7
IO7_1
SVA8
IB8
B6
B7
B8
B9
B10
IMT2
B39
B40
B41
B42
B43
SVA6
IB6
B72
B73
B74
B75
B76
SVB1
VIMT1
IMT1
VREF2
RCVN2
IO2_1
IREF
LD3
VAC6
CANCEL6
IA6
VDD33_1
P1
DCA1
DCB1
VAC8
The Exposed Pad is the AGND and DGND connection. Connect to a PCB ground plane using a thermal pad and a grid of
thermal vias. Refer to the Hardware Design Guide for use and considerations.
Table 2 - 164-Pin LGA Pin Numbers and Pin Names
16
Microsemi Corporation
Le79238
Data Sheet
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
132
1
2
RCVN1
RCVP1
VAC8
VIMT8
8
VA8
AGND7
IO7_0
IO7_1
3
IO1_1
IO1_0
AGND1
SVA2
SVB2
IB2
VIMT2
VAC2
AVDD12
CANCEL2
IMT2
IA2
DCA2
VREF2
DCB2
RCVN2
4
5
6
1
7
125
8
124
9
RCVP7
RCVN7
AVDD78
DCB7
VREF7
DCA7
IA7
IMT7
123
10
2
11
12
121
120
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
119
118
117
116
CANCEL7
VAC7
VIMT7
IB7
SVB7
SVA7
SLB
SHB
115
114
RCVP2
IO2_1
IO2_0
AGND2
IREF
113
112
111
176-pin QFP
110
109
SVA3
108
SPB
AGND6
IO6_0
IO6_1
RCVP6
RCVN6
DCB6
VREF6
DCA6
IA6
IMT6
CANCEL6
AVDD56
VAC6
VIMT6
IB6
SVB3
IB3
VIMT3
VAC3
107
106
105
104
CANCEL3
IMT3
103
102
IA3
DCA3
101
100
VREF3
DCB3
AVDD34
RCVN3
RCVP3
IO3_1
99
98
97
96
95
94
IO3_0
AGND3
93
92
SVB6
SVA4
SVB4
IB4
91
SVA6
AGND5
IO5_0
90
89
VIMT4
46 47 48 0 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Figure 6 - 176-Pin LQFP Diagram
17
Microsemi Corporation
Le79238
Data Sheet
3.0 Pin Descriptions
Pin Name
LQFP Pin #
LGA Pin #
BGA Pin #
Type
Description
5, 22, 40,
56, 90, 107,
127, 143
F6, G5, L5,
L6, L9, J9,
F9, E9
AGND[1:8]
EPAD
Analog ground. Separate analog and digital grounds are
provided to allow noise isolation, however the rounds must be
connected together on the circuit board.
Ground
AGND2A,
AGND4A,
AGND5A,
AGND8A
H5, M5,
M10, C10
—
—
AVDD12,
AVDD34,
AVDD56
AVDD78
11, 35, 96,
122
B5, A18,
A48, B53
E5, J5,
K10, E10
+3.3 VDC analog power ply inputs. For st perfmance,
all of the AVDD and V33 ower supply pins ould be
connected together t the dev. Four decoupling capacitors
should be used. Place a decouplcapacitor near AVDD12,
AVDD34, AVDD5and AVDD78. AD12A, AVDD34A,
AVDD56A, and AVD78A do not requitheir own decoupling
capacitors.
Supply
AVDD12A,
AVDD34A,
AVDD56A
AVDD78A
D5, K5,
L10, D10
—
—
A85, A6,
B13, A24,
B35, B42,
A58, A67
A4, D1,
H1, M1,
P11, L14,
G14, C14
171, 12, 29,
46, 80, 97,
116, 133
Metering cancation output. If metering is used, connect a
capacior from thpin to the respective channel’s IMT pin. If
meting is not used, let this pin float.
CANCEL[1:8]
CS
Outpu
ut
MPI interfachip select. A logic low placed on this pin enables
sal datransmission into DIN or out of the DOUT port.
151
B65
C8
B75, A8,
B14, A26,
A41, A50,
B52, B59
B1,
P3, N
H13, D13
A12
174, 15, 32,
49, 83, 100,
119, 136
DC feed and low-frequency voltage control of the SLIC device’s
A lead amplifiers.
DCA[1:8]
B7A9,
B5, A27,
7, A51,
A6B6
C1, F2, ,
P4, M14,
J13, E13,
A11
176, 17, 34,
51, 85, 102,
121, 138
DC feed and low-frequency voltage control of the SLIC device’s
B lead amplifiers.
DCB[1:8]
Output
MPI interface data clock. Provides data control for MPI interface
control.
DCLK
150
65
64
A75
A81
D8
D6
C6
Input
Input
DEBUG Clock. This node needs to be tied to VDD33 through a
0 Ω resistor.
DEBUG_CLK
Input/
DEBUG input output. This node needs to be tied to DGND
through a 0 Ω resistor.
DEB
Output
C5, K6,
K9, N10,
B10, E7
, 64,
6, 152
DGN
DGND2A
EPAD
—
Digital ground. Separate analog and digital grounds are
provided to allow noise isolation, however the grounds must be
connected together on the circuit board.
Ground
Input
—
N5
MPI interface control data input. Control data is serially written
into the Le79238 device via the DIN pin with the MSB first. DIN
can be tied to DOUT for a single bi-directional interface. The
data clock (DCLK) determines the data rate.
DIN
149
B64
A9
18
Microsemi Corporation
Le79238
Data Sheet
Pin Name
LQFP Pin #
LGA Pin #
BGA Pin #
Type
Description
MPI interface control data output. Control data is serially read
out of the Le79238 device via the DOUT pin with the MSB first.
DOUT can be tied to DIN for a single bi-directional inteace.
The data clock (DCLK) determines the data rate. DOUT iigh
impedance except when data is being transmitted from the
Le79238 device under control of CS.
DOUT
148
A74
B9
Output
PCM highway data receive ports. The receive input
serially through the DRA or DRB ports. Data is iv
with the most significant bit first. For compressed , 1 byte
of data is received every 125 µs at thPCLK rate. the Linear
mode, 2 consecutive bytes of ata for eh channare
received every 125 µs at thPCLK rate. In deband ode, the
frame sync stays at 8 khe Le79238 operes internally at
16 kHz and outputs da twiper frame in evespaced
timeslots. If an input is not usede to DGND.
DRA, DRB
156, 163
B67, B70
A7, B6
Input
PCM highway data ansmit ports. Thransmit PCM data is
transmitted serially thugh the DXA or DXB ports. Data is
always transmitted mosgnificant bit first. The output is
availaveµs and e data is shifted out in 8-bit (16-bit
in Linear de) bursts at thCLK rate. In Wideband mode, the
rame sync ys at 8 kHz, the Le79238 operates internally at
16 kHz and outs data twice per frame in evenly spaced
timesls. DXA anDXB are high impedance between bursts
anwhile the device is in the inactive mode. If an output is not
ed, let the pfloat.
DXA, DXB
157, 160
A78, A79
B7, C7
Output
M higway frame sync. PCM operation is selected by the
pree of an 8 kHz frame sync signal on this pin in
conjunction with the PCM clock on the PCLK pin. This 8 kHz
pulse identifies the beginning of a frame. The Le79238 device
references individual timeslots with respect to this input, which
must be synchronized to PCLK.
FS
154
B66
B
A86A7,
A, A25,
6, B43,
AA68
C4, G44,
N4, M11
H11, F11,
C11
173, 14, 31,
48, 82, 99,
118, 135
IA[1:8]
IB[1:8]
Input
Input
Input current is proportional to current in SLIC’s A lead.
Input current is proportional to current in SLIC’s B lead.
A83, A
13, B19,
A3B40,
B4965
B4, F4, H4,
M4, N11,
J11, G11,
B11
168, 8, 26,
43, 77, 93,
30
B74, B6,
A15, B21,
A40, A49,
B51, B58
A3, E1, J1,
N1, P12,
K14, F14,
B14
172, 13, ,
81, 98
134
Input current is proportional to the differential current in the
SLIC’s AD and BD leads. AGND on this node indicates a SLIC
thermal overload condition.
IMT[1
INT
Input
Interrupt. When a subscriber line requires service, this pin goes
to a logic 0 to interrupt a high level processor. Logic drive is
selectable between open drain and TTL-compatible outputs.
45
A73
C9
Output
General purpose logic input/output and relay driver port. These
pins can be programmed as an input or an output. These pins
can be programmed as an open drain 50 mA relay driver.
Unused pins should either be tied to AGND through a 10 KΩ
resistor or programmed as low outputs.
B2, A11,
A20, A29,
A45, B46,
B55, A72
4, 21, 39,
55, 89, 106,
126, 142
F7, G7, J7,
K7, K8, J8,
F8, E8
Input/
IO[1:80
Output
19
Microsemi Corporation
Le79238
Data Sheet
Pin Name
LQFP Pin #
LGA Pin #
BGA Pin #
Type
Description
A2, B9,
B17, B24,
A44, A53,
A63, A71
General purpose logic input/output. These pins can be
programmed as an input or an output. Unused pins should
either be tied to AGND through a 10 KΩ resistor or progrmmed
as low outputs.
3, 20, 38,
54, 88, 105,
125, 141
G6, H6, J6,
H7, H8,
H9, G9, G8
Input/
IO[1:8]_1
Output
External resistor (R
) connected between this pin and
REF
IREF
23
B10
F5
Input
analog ground generates an accurate, on-chence
current for the A/D’s and D/A’s on the Le7923
A30, B26,
A31, B27,
B30, A35,
B31, A36
M6, P6,
N6, P7,
P8, N9,
P9, M9
Logic output that controls data traner into the Sevice.
When LD is Low, the data on outputs PP2 is tranrred to the
respective data latches as dirted by thSEL pin. hen LD is
High, the data is locked in e latches.
59, 60, 61,
62, 69, 70,
71, 72
LD[1:8]
NC
Output
—
A23, A88
—
No connect. This pin not innally connected.
PCM highway clk. A valid PCLK iequired for overall device
operation. PCLK drmines the rate which PCM data is
serially shifted into or of the PCM ports. The minimum clock
frequey for linear/comnded data is 1.536 MHz.
PCLK
155
A77
A8
Input
B28, A33,
B29
M8, M7,
N7
bus. Cools the operating modes of the SLIC and LCAS
devices connted to the Le79238 device.
P[0:2]
RST
65, 66, 67
144
Output
Hardre reset. Tpin should be driven by a logic signal (0V
an+3.3 V) or else an external RC circuit (capacitor between
ST and DG, resistor between RST and VDD33) should be
sed to apy a low signal for enough time to guarantee that all
splies re valid before the reset is de-asserted.
B62
D9
Input
A1, B8,
B16, B23,
A43, A52,
A62, A70
B3
H3, L
N12, K12
G2, D12
1, 18, 36,
52, 86, 103,
123, 139
Receive signal output (Inverting). Voice and metering control
voltage signals for SLIC amplifiers.
RCVN[1:8]
RCVP[1:8]
Output
B110,
A9, A28,
8, B45,
B5B6
C3, F3, ,
M3, M12,
J12, F12,
C12
2, 19, 37,
53, 87, 104,
124, 140
Receive signal output (Noninverting). Voice and metering
control voltage signals for SLIC amplifiers.
D4, E4,
K4, L4,
L11, K11,
E11, D11,
F10, L8
RSVD_B[1:8],
RSVD_C,
RSVD_O
Reserved. These pins are internally connected. Pins must be
left floating.
—
Reserved
Output
Logic output that selects data outputs P0–P2 to either control
the SLIC’s operating modes or the SLIC’s switch states.
SEL
68
A34
N8
Battery sense leads. Resistors that sense the high, low, and
positive battery voltages connect here. If only one negative
battery is used, connect both negative battery resistors to the
same supply or leave SLB unconnected. If the positive battery
is not used, connect the SPB resistor to AGND or leave the pin
unconnected. These pins are current inputs into pins whose
voltage is held at VREF, do not short these pins together.
SHB, SL
SPB
09, 110,
108
A54, A55,
B47
J10, G10,
H10
Input
Input
A82, A3,
A12, B18,
A37, B39,
B48, A64
C2, E2, J2,
N2, M13,
K13, F13,
B13
166, 6, 24,
41, 75, 91,
111, 128
SVA[1:8]
Senses the voltages on A lead through external sense resistors.
20
Microsemi Corporation
Le79238
Data Sheet
Pin Name
LQFP Pin #
LGA Pin #
BGA Pin #
Type
Description
B72, B3,
B11, A21,
B33, A46,
A56, B56
B2, D2,
H2, M2,
N13, L13,
G13, C13
167, 7, 25,
42, 76, 92,
112, 129
SVB[1:8]
Input
Senses the voltages on B lead through external sense resistors.
PCM highway backplane driver enables. TSCA or TSCB are
active low when PCM data is output on the DDXB pins,
respectively. The outputs are open-drain and
inactive (high impedance). Pull-up loads should cted
to VDD33. If output not used, let thpin float.
TSCA, TSCB
VAC[1:8]
161, 162
B69, A80
D7, A6
Output
A84, A5,
A14, B20,
A39, B41,
B50, A66
A1, G1, L1,
P2, P14,
H14, D14,
A13
170, 10, 28,
45, 79, 95,
115, 132
Voice (AC only) signal prortional to the Icurreof the
SLIC.
Input
Supply
Supply
ut
57, 73, 147,
159
B25, B32,
B63, B68
P5, P10,
A10, B5
+1.8 VDC digitaower supply inpPlace a decoupling
capacitor near VDD_1, VDD18_2, D18_3, and VDD18_4.
VDD18_4A does not ruire its own decoupling capacitor. A
bulk doupling capacitos also advised.
VDD18_[1:4]
VDD18_4A
—
—
A5
3.3 VDC gital power supply inputs. For best performance, all
of the VDD3nd AVDD power supply pins should be
connected togeer at the device. A decoupling capacitor
shoulbe used on ach pin.
VDD33_[1:2]
VIMT[1:8]
63, 153
A32, A76
L7, E6
B73, B4,
B12, A22,
B34, A47,
A57, B57
A2, F1, K1,
P1, P13,
J14, E14
A1
169, 9, 27,
44, 78, 94,
114, 131
gnal proortional to the IMT current of the SLIC.
A87, B7,
A17, B22,
A42, B44,
A60, A9
D3, G
K3, N3,
L, H12,
E1B12
175, 16, 33,
50, 84, 101,
120, 137
This pin provides a +1.5 V, single-ended reference to the
respective SLIC. This pin requires an external capacitor to
AGND, whether the output is used or not.
VREF[1:8]
21
Microsemi Corporation
Le79238
Data Sheet
4.0 Absolute Maximum Ratings
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods
can affect device reliability.
Storage Temperature
–55ºC ≤ TA ≤ +125ºC
–40ºC ≤ TA ≤ +85ºC
Ambient Temperature, under Bias
Ambient relative humidity (non condensing)
VDD33 with respect to AGND or DGND
VDD18 with respect to AGND or DGND
AVDD with respect to AGND or DGND
5% to 95%
–0.4 V to +4.0 V
–0.4 V to +1.98 V
–0.4 V to +4.0 V
±0.4 V
AVDD with respect to VDD33
IMT, VIMT, VAC, IA, IB with respect to AGND or DGND
–0.4 V to (AD + 0.4 V)
75 mA
IO [1:8]_0 current
AGND
D±0.4 V
Latch up immunity (any pin)
Any other pin with respect to DGND
ESD Immunity (Human Body Model)
±100 A
–0.4 V to DD33 + 0.5 V)
JSD22 Class C compliant
4.1 Green Package Assembly
The green package devices are assembled wenviroental compatible lead-free, halogen-free, and
antimony-free materials. The leads posselating which is compatible with conventional board
assembly processes or newer lead-free by processes. Refer to IPC/JEDEC J-Std-020 for
recommended peak soldering temperate and stemperature profile.
The package referred to as a LaGrid Arra(LGA) ihis document uses a Cu Alloy Leadframe as the substrate
and its construction is such at it would be assified as a QFN per JEDEC Standard JESD30. Refer to the
Hardware Design Guide for B mouing of the GA.
22
Microsemi Corporation
Le79238
Data Sheet
5.0 Operating Ranges
Microsemi guarantees the performance of this device over commercial (0º to 70ºC) and industrial (−40º to 85ºC)
temperature ranges by conducting electrical characterization over each range and by conducting a production test
with single insertion coupled to periodic sampling. These characterization and test procedures comply with the
Telcordia GR-357-CORE Generic Requirements for Assuring the Reliability of Components Usd in
Telecommunications Equipment.
5.1 Environmental Ranges
Ambient Temperature
–40 to +85ºC
15 to 85%
Ambient Relative Humidity
5.2 Electrical Ranges
Analog Supply AVDD
Digital Supply VDD33
+3.3 V ±5%, VDD33 ±50 mV
+3.3 V ±5%
+1.8 V ±5%
Refer “Reset at Power-Up” on
page 35 r supply and reset
equencin
Digital Supply VDD18
DGND
AGND
0 V
DGND ±10 mV
6.0 Programming of the SLAC Parameters
The line circuit parameters are stored in a Devicfile. TDevie Profile files are generated by Microsemi’s
application support programs WinSLAC™ anrd. ThDevice Profile file is loaded into the Le79238
SLAC through the API-II software interface.
The Device Profile file consists of a Sstem-Dand a number of optional parameter profiles. If the
NGVCP is used, profiles for cadencing anCaller dded. The following optional files pertain to parameters
that are programmable in the SLC:
6.1 AC Parameters
•
•
•
•
•
•
Input impedance Z
D
2-4W Hybrid balance impdance
Test terminatimance
Transmit RelativLevel and frequency response equalization
Reve Lel and frequency response equalization
Abit linear, or wideband PCM encoding
23
Microsemi Corporation
Le79238
Data Sheet
6.2 DC Parameters
•
•
•
•
•
•
•
•
•
Loop current limit value
Feed resistance before current limit
Metallic voltage at transition between current limit and resistive feed
Anti-saturation headroom voltage
Abrupt or smooth reversal
Off-hook detection threshold
GND start threshold
DC fault detection threshold
AC fault detection threshold
6.3 Ringing Parameters
•
•
•
•
•
•
•
•
A lead DC voltage V
B lead DC voltage V
during internal ringing
during internal ringing
DCA
DCB
Balanced or unbalanced internal ringing
Amplitude of internal ringing
Frequency of internal ringing
Wave shape of internal ringing
Short loop ring trip threshold
Long loop ring trip threshold
6.4 Tone and Metering Signal Paramet
•
•
Frequency
Amplitude
For a complete description of aramters, consult the WinSLAC™ Software User’s Guide (Document ID 080779)
and the Profile Wizard Uer’s Gu(Document ID 127063).
24
Microsemi Corporation
Le79238
Data Sheet
7.0 Electrical Characteristics
7.1 AC/DC Specifications
Typical values are for TA = 25ºC and nominal supply voltage. Minimum and maximum values are oer the
temperature and supply voltage ranges as shown in “Operating Ranges” on page 23, except as noted. PCLand
FS are present and valid.
Refer to the Next Generation Carrier Chipset Hardware Design Guide (Document ID 126583) for e nodes
that have trace capacitance restrictions.
No.
Item
Condition
Min
Typ
x
t
Note
Input Low Voltage (VIL)
1
–0.50
—
0.80
V
Digital inputs and IO[1:8]_[0:1] programmed as
an input
Input High Voltage (VIH
)
VD3 +
0.5
2
2.0
—
V
Digital inputs and IO[1:8]_[0:1] programmed as
an input
Input Leakage Current, IO[1:8]_[0:1]
All other digital inputs
–1
—
+10
3
4
0 to VDD33
µA
V
–120
+180
Input hysteresis
PCLK, FS, DRA, DRB, DCLK, DIN and
IO[1:8]_[0:1] programmed as an input
0.15
—
—
0.30
0.4
2
Output Low Voltage (VOL
)
DXA, DXB, DOUT, IO[1:8]_[0:1], INT, TSCA,
TSCB
5
V
IO[1:8]_0 when programmed as relay river
P[0:2], LD, SEL
Iol
—
—
—
—
0.7
0.4
Output High Voltage (VOH
)
VDD33 –
0.4
6
7
h = 400 µA
—
—
1
V
All digital outputs excepNT in open rain
mode and TSCA, TSCB
Input Leakage Curre
IMT
–1
—
µA
Full scalltels, inpor output
DCA, DCB
VREF±1.2
Normal gain
High gain
VREF±0.6
VREF±1.2
VREF±0.6
VREF±1.2
See Note
N
8
—
—
V
Normal gain
High gain
VIMT
VAC
3
4
See Note
Load current
= 0 to 0.8 mA,
Source or
Sink
9
Output voltage, VREF[1:8]
1.47
1.50
1.53
V
Table 3 - AC/DC Specifications
25
Microsemi Corporation
Le79238
Data Sheet
No.
Item
Condition
Min
Typ
Max
Unit
Note
% of input
voltage
Battery read A/D relative error
Battery read A/D absolute error
–3%
—
+3%
10
2, 7
–0.5
—
—
—
—
—
—
—
—
—
—
—
80
27
43
14
72
2
5
+0.5
110
40
60
2
—
V
Active state
+3.3 V Supply Power Dissipation,
Nonoperational, Power per channel
Standby state
Active state
11
8
+1.8 V Supply Power Dissipation,
Nonoperational, Power per channel
Standby state
Active state
+3.3 V Supply Power Dissipation,
Operational, Power per channel
Standby state
Disabled state
Active state
—
—
12
mW
9, 10
36
2
+1.8 V Supply Power Dissipation,
Standby state
Disabled state
—
Operational, Mean power per channel
—
Table 3 - AC/DC Scifications
7.2 Transmission Specifications
Transmission specifications are tested with the X-filter, R-filtGX, and GR set to a gain of 1, the Z-filter, B-filter,
AISN, and DISN set to a gain of 0, the VDAC gadB, thDRgain set to 5/8, and the VAC gain set to 15.
The receive path 0 dB output level is defined ms per in on RCVP-RCVN (0.36944 Vrms differential)
and the transmit path 0 dB input level is de9 Vrms on the VAC pin. Supplies are as specified in
“Electrical Ranges” on page 23. PCLK and FS d valid.
No.
Item
Conition
Min
Typ
Max
Unit
Note
Input: 1014 Hz, 0 dBm0
GR = GX = 0 dB; AISN, R, X, B and Z
disabled
Insertion Loss
A-D, D-A
–0.25
0
+0.25
1
dB
7
Temperature = 25°C
–0.15
–0.1
0
0
+0.15
+0.1
A-D + D-A
Variation over temperature
Level set error rror between
d actuaalue)
2
3
A-D, D-A
–0.1
–0.3
0
0
0.1
dB
dB
7
7
DR Input: 1014 Hz, –10 dBm0
GR=GX=0 dB; AISN, R, X, B and Z
filters default
n full digital
+0.3
Table 4 - Transmission Specifications
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Microsemi Corporation
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Data Sheet
No.
Item
Condition
Min
Typ
Max
Unit
Note
A-D (DX output)
—
—
—
—
—
—
—
—
–69
–78
+19
+12
Idle Channel Noise
Psophometric Weighted (A-law)
dBm0p
dBrnC0
dBrn
D-A (RCVN, RCVP output)
A-D (DX output)
50
C Message weighted (µ-law)
4
D-A (RCVN, RCVP output)
A-A (VAC input any channel, RCVN,
RCVP output any other channel, DX
tied to DR)
15 kHz flat (Wideband linear mode)
—
16
—
1
PSRR Image frequency (VDDxx)
A-D
Input: 4.8 to 7.8 kHz,
200 mVp-p
37
37
—
—
—
—
5
µS
Measure at:
8000 Hz − Input frequency
D-A
1014 Hz, –10 dBm0;
B=Z=0; X=R=1
6
7
8
End-to-end absolute group delay
—
—
725
2, 6
—
—
—
—
—
—
—
–75
–75
–75
–75
Crosstalk
TX to RX
RX to TX
300 Hz to 3400 Hz, 0 dBm0
1014 Hz, 0 dBm0
same channel
dBm0
2
Crosstalk
TX or RX to TX
TX or RX to RX
other channel
Table 4 - Transmission Secificatons
Note 1: Not tested or partially tested in production. Tis guarteby characterization or correlation to other tests.
Note 2: Guaranteed by design.
Note 3: VIMT has an analog range of VREF ±1.2 V, F ±1.0 V is used by the A/D input.
Note 4: Full scale voltage level for VAC is VRF ± (1.0
Note 5: The specification holds for any etting oX gain f12 dB or GR from 0 to –12 dB when tested with a transmission
level point of 0 dBr.
Note 6: The end-to-end group delis the absolute grp delay at the echo path with the B-filter turned off. Refer to the Next
Generation Carrier Chipt DesigneGuide foore information. See Figure 9 for Group Delay Distortion versus frequency.
Note 7: Requires that the calibraticomand be performed to achieve this performance.
Note 8: Firmware and DC fd not optional.
Note 9: Firmware and DC feed perationbatteries applied.
Note 10: DSP Core Power Reductienable.
7.3 Transmit ad Receive Paths
In this tranmit path is defined as the analog input to the Le79238 device (VAC) to the PCM voice
outppath is defined as the PCM voice input to the Le79238 analog output (RCVN, RCVP). All limits
definn are tested with B = 0, Z = 0 and X = R = GR = GX = 1, unless otherwise specified. These
transeristics are valid for 0 to 70º C.
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Data Sheet
7.4 Attenuation Distortion
The attenuation of the signal in either path is nominally independent of the frequency. The deviations from nominal
attenuation will stay within the limits shown in Figure 7 and Figure 8 for narrowband operation and within the limits
shown in Table 5 for wideband operation when the calibration command is performed and equalized coefficients are
used.
The reference signal level is –10 dBm0. The minimum transmit attenuation at 60 Hz is 24 dB.
2
1
0.80
65
0.6
0.2
0.25
0.125
0
Acceptable Region
Frequen()
-0.125
0
Figure 7 - NarrowbaPath tenuation vs. Frequency
2
0.75
0.125
Acceptable Region
Frequency (Hz)
0
0
-0.125
0
Figure 8 - Narrowband Receive Path Attenuation vs. Frequency
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Microsemi Corporation
Le79238
Data Sheet
No.
Item
Condition
Min
Typ
Max
Unit
Relative to 1020 Hz:
50 Hz
+20
+20
—
—
—
—
—
—
—
—
—
—
—
—
60 Hz
200 Hz
0
+3.0
+0.5
+0.3
+0.3
+5
+0.75
+1.0
—
300 Hz
–0.25
–0.25
–0.25
–0.25
–0.2
0
500 Hz
1
Transmit Path Loss
4800 Hz
6000 Hz
6400 Hz
6800 Hz
8000 Hz
9200 Hz
Relative to 1020 Hz:
50 Hz
+14
+
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
60 Hz
0
200 Hz
0
+2.0
+0.5
+0.3
+0.3
+0.5
+0.75
+1.0
—
300 Hz
–0.25
–0.25
–0.25
–0.25
–0.25
0
600 Hz
2
Receive Path Loss
4
6
6400
800 Hz
80Hz
9200 H
12000 Hz
dB
+14
+28
+28
—
—
Tab5 - Wideband Attenuation vs. Frequency
Note:
Not tested or partiallsteoductioThese parameters are guaranteed by characterization or correlation to other tests.
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Data Sheet
7.5 Group Delay Distortion
For either transmission path, the group delay distortion is within the limits shown in Figure 9. The minimum value of
the group delay is taken as the reference. The signal level is –10 dBm0.
420
Delay (µS)
150
90
Acceptable
Region
0
uency (Hz)
FiguDelaistortion
7.6 Single Frequency Distortion
The output signal level, at any singe frequncy in te of 300 to 3400 Hz, other than that due to an applied 0
dBm0 sine wave signal with freqency f in thsame fruency range, is less than –46 dBm0. With f swept between
0 Hz to 300 Hz and 3.4 kHz 12 kHz, any geerated output signals other than f are less than –28 dBm0. This
specification is valid for eitheransmision path.
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Data Sheet
7.7 Gain Linearity
The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 10 (A-law) and Figure 11 (µ-
law) for either transmission path when the input is a sine wave signal of 1014 Hz.
1.5
0.55
0.25
Inp
Level
Acceptable Region
Gain (dB)
0
-55 -50
-40
-10
+3
(dBm0)
-0.25
-0.55
-1.5
Figure 10 - A-law Gaarity wth TonInput (Both Paths)
1.4
.45
0.25
Input
Level
Acceptable Region
Gain (d
0
+3
-55 -50
-37
-10
0
(dBm0)
-0.45
-1.4
Figure 11 - µ-law Gain Linearity with Tone Input (Both Paths)
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Data Sheet
7.8 Total Distortion Including Quantizing Distortion
The signal to total distortion ratio will exceed the limits shown in Figure 12 for either path when the input signal is a
sine wave signal of frequency 1014 Hz.
Acceptable Region
B
A
A-Law
µ-Law
A
B
C
D
35.5dB 35.5dB
35.5dB 35.5dB
C
D
30dB
25dB
31d
27dB
Sial-to-To
Distortion (dB)
-45 -40
-30
Input Level Bm0)
Figure 12 - Total Distortiowith Tone Input, Both Paths
7.9 Overload Compression
Figure 13 shows the acceptable region of ut signal levels above the reference input power (0
dBm0). The conditions for this figure are:
(1) With GX in the range of +1 dB < GX ≤ 12 dB y WinSLAC™; (2) GR in the range of –12 dB ≤ GR < –1
dB as set by WinSLAC™; (3) Dital voice otput concted to digital voice input; and (4) measurement analog to
analog.
9
8
7
6
Fundamental
Output Power
Acceptable
Region
5
4
3
(dBm0)
2.6
2
1
7
8
9
1
2
3
4
5
6
Fundamental Input Power (dBm0)
Figure 13 - A/A Overload Compression
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Le79238
Data Sheet
7.10 Discrimination Against Out-of-Band Input Signals
When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be
frequency components below 4 kHz at the digital output which are caused by the out-of-band signal. These
components are at least the specified dB level below the level of a signal at the same output originating from a
1014 Hz sine wave signal with a level of A dBm0 also applied to the analog input. The specificatios for
narrowband mode are shown below.
Frequency of Out-of-Band Signal
Amplitude of Out-of-Band Signal
Level belo
16.6 Hz < f < 45 Hz
45 Hz < f < 65 Hz
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
18 dB
5 dB
65 Hz < f < 100 Hz
3400 Hz < f < 4600 Hz
4600 Hz < f < 100 kHz
10
see Figure
32 dB
Table 6 - Minimum Specifications for Out-of-Band nput Signal
0
-10
-20
Level
below A
(dB)
-30
-
-50
3.4
4.0
4.6
Frequency (kHz)
Figure 14 - Discrimination Against Out-of-Band Signals
Note:
The ataveform elow amplitude A between 3400 Hz and 4000 Hz is given by the formula:
π(4000 – f)
⎛
⎝
⎞
⎠
----------------------------
Attenuation = 14 – 14sin
dB
1200
The atteation of the waveform below amplitude A between 4000 Hz and 4600 Hz is given by the formula:
π(4000 – f)
⎛
⎝
⎞
⎠
----------------------------
Attenuation = 14 – 18sin
dB
1200
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Microsemi Corporation
Le79238
Data Sheet
7.11 Spurious Out-of-Band Signals at the Analog Output
With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0
applied to the digital input, the level of the spurious out-of-band signals at the analog output for narrowband mode is
less than the limits shown below.
Frequency
Level
4.6 kHz to 40 kHz
40 kHz to 240 kHz
240 kHz to 1 MHz
–32 dBm0
–46 dBm0
–36 dBm0
Table 7 - Limits for Spurious Out-of-Band Signals
0
-10
-20
-28 dBm0
-32 dBm0
-30
-40
-50
Level (dBm0)
3.4
4.6
Frequency (kHz)
Figure 15 - Spurious Out-of-Band Signals
Note:
The amplitude of the spurious out-of-bd signals between 3400 Hz and 4600 Hz is given by the formula:
π(f – 4000)
⎛
⎝
⎞
dBm0
----------------------------
Level = – 14 – 14sin
⎠
1200
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Microsemi Corporation
Le79238
Data Sheet
8.0 Reset at Power-Up
This section discusses the handling of the reset signal at power-up. Two power-up sequences are presented.
If VDD33 and VDD18 power supplies are powered up separately, refer to Figure 16. For this sequence, VDD33 is
powered up shortly before VDD18 is powered up (period D). Reset can be held high or low at power-up; PCK can
be running or turned off initially. After VDD18 is powered up and stabilized, a short reset (B) needs to be assted
(within period A). When reset is de-asserted, PCLK must be running and main device initialization functions c
now proceed.
If VDD33 and VDD18 power supplies are powered up at the same time, refer to Figure 16. For this se, res
must be held low at power-up; PCLK can be running or turned off initially. After the suppliehave staed, reset
needs to be de-asserted (within period A). At this point PCLK must be running anmaidevice itialization
functions can now proceed.
Note: If the intent for either power-up sequence is to hold the line card in reset, apply the initial short set, -assert, then waieriod C before
re-asserting reset. Reset can then be held indefinitely, with or without PCLK operational.
D
VDD18
VDD33
PCLK
RST
C
B
Figure 16 - Ret Sequencwhen VDD33 and VDD18 are Powered Up Separately
VD33
A
DD18
PCLK
RST
C
Figure 17. Reset Sequence when VDD33 and VDD18 are Powered Up Together
Note: A valid reset should be applied as soon as possible after power-up.
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Microsemi Corporation
Le79238
Data Sheet
No.
Parameter
Min.
Typ
Max
Unit
A
B
Time after power supplies are stable until reset is de-asserted
Reset pulse width
300
1
—
—
See note
See note
µ
Time after reset is de-asserted until reset can be re-asserted. (Only applies
to initial power-up sequence.)
C
D
1000
500
—
—
—
Delay between VDD33 and VDD18 power-up
See not
Table 8 - Recommended Reset Sequence Timing
9.0 Host Bus Control Interface (HBI) Overview
The Host Bus Interface provides a means for exchanging control, configuration ad status iormatiwith an
external processor. This is accomplished by allowing the host to access regions oe DSP memo, and selected
hardware registers. Essentially, the host peeks and pokes internal memory to ehangdata.
This interface is implemented through a combination of hardware and firmwre. The desigis layered as shown in
Figure 18. Hardware provides a generic means for transporting data between he host and ternal memory. The
interpretation of the data is provided by firmware running on the DSP. This layerearchitecture allows the definition
of the application level interface to change by modifying the DSP fir
Prdes the plication pgrammer’s interface. Defines
the aninof payload data passed over the interface.
Firmware
Application Layer
oves 1bit data ords between the physical layer and
Transport Layer
al memry.
Hardware
Physical Layer
he pins, signal timing and electrical characteristics
terface.
MPI
Figure 18 - Host Bus Interface Layers
The transport layer movs 16-bit ta words between the physical interface and internal DSP memory or hardware
registers on an internal buIt defins the structure of a transport frame, which consists of a 16-bit command word
followed by 0 or more 16-bit pyload da words. It also defines the interface address model, and provides mapping
between interfainternal adresses.
The application laydefines the programmer’s interface, and is almost entirely implemented in firmware. The
exceptiandful f configuration registers implemented in hardware. This layer defines the meaning of the
payloered the transport layer. Because it is implemented in firmware, the definition of the
progce can change by providing new software.
The provides the functionality needed to electrically interface with a network processor. The
Microprerface (MPI) implements a common, industry standard 3-wire or 4-wire synchronous serial slave
interface included with many DSPs and microcontrollers.
9.1 ansport Layer
Thprimary responsibility of the transport layer is to move 16-bit data words between the physical interface and
locations on an internal bus, which includes DSP memory. Data is organized into transport frames, which consist of
a 16-bit command word followed by 0 or more data words. The command word provides address and length
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Microsemi Corporation
Le79238
Data Sheet
information to the transport hardware. In a sense, this hardware provides an internal DMA-like function, moving
data over the internal bus under host control.
9.1.1 Interface Addressing
The transport command word provides address information to the interface hardware.
The host interface address model is based on a paged memory scheme, as shown in Figure 19. The comman
design permits up to 257 pages, with up to 128 offset-addressable 16-bit wide register locationefore, an
interface address is composed of an 8-bit page number and a 7-bit register offset. Pages are selecg a
command to write the page register. All data access commands operate on the selected page. One exn is the
direct page, which can be accessed at any time without changing the page register.
127
118 - 127 Reserved
Notes:
1.
For NGCC SLAC, N = 15.
Offset
Address
16-Bit
Registers
Direct Page
Page 0
Page 1... N
CL Page
0
Figure nterfacAddress Mode
9.1.2 Command Structure
All transport frames start with a 16bit commnd worowed by 0 or more 16-bit data words.
Command Bit Position
Number of
Transport Command
5
14
6
13
5
12
4
11
3
10
2
9
1
8
0
16-bit
Data Words
0
Offset Address (0 - 127)
Length (0 - 127)
PageAccess
Length + 1
Length + 1
w1
1
Offset Addressb (0 - 118)
0
irect Pe
Acces
Lengthb (0 - 15)
r/w
1
0
1
0
1
1
1
0
0
1
0
1
0
r/w
r/w
0
ox Access
Length + 1
Length + 1
0
Length (0 - 255)
1
1
1
1
1
1
1
1
Continue Mailbox
Access
Length (0 - 255)
1
1
Reserved
Reserved
Table 9 - Host Bus Interface Transport Commands
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Microsemi Corporation
Le79238
Data Sheet
Command Bit Position
Number of
Transport Command
15
7
14
6
13
5
12
4
11
3
10
2
9
1
0
8
0
1
16-bit
Data Words
1
1
1
1
1
1
Configure Interfaces
Select Page
Select CL Page
Reserved
0
0
0
0
0
Interface Option Bits
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
0
Page Number (0 - 15)
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
NOP
Table 9 - Host Bus Interface Transpt mand
1. Read / Write select bit. 0 = Read. 1 = Write.
b. Addresses 120-127 on the Direct Page are reserved.
9.1.3 Paged Offset Access
This command accesses one or more contiguous 16-bit risters on the currently selected page; it must be
preceded by a page selection command. The 7pecifithe starting address on the page. The command
is followed by (Length + 1) 16-bit data wordsth field allows accessing between 1 and 128 locations
with a single transport frame. For nonzeraddress automatically increments, and consecutive
locations are accessed.
9.1.4 Direct Page Offset Acess
Direct Offset Access is the me as Pged OffsAccess, except that the direct page is the target. By using this
command, the direct page can e aessed at any time without modifying the page register. The 4-bit Length field
allows accessing betwen 1 an16 locations on a single transport frame. For nonzero Lengths, the address
automatically increments, ad consutive locations are accessed.
9.1.5 Start Mlbox ce
This commd acceses a contiguous stream of 16-bit data words starting from offset 0 on the currently selected
page. nd is flowed by (Length + 1) 16-bit data words. The 8-bit Length field allows accessing between
1 an(i.e., up to 512 bytes) with a single transport frame. Access always begins from offset 0, and
the cally increments.
9.1.6 e Mailbox Access
Contine Mailbox Access is the same as Start Mailbox Access, except that access starts from where the last
mailboaccess left off. By using this command, packets of arbitrary length can be supported. Note that Offset
Accescommands can be executed between multiple Mailbox Access commands. This gives the host the freedom
to spit data transfers into smaller sizes if desired.
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Data Sheet
9.1.7 Configure Interfaces
This global command is used to configure various physical interface options. It is a write only global command and
is followed by 0 data words.
Interface Configuration Register (Configure)
D7
D6
D5
D4
D3
D2
D1
D0
HBI
INT
Data Byte
RSVD
RSVD
RSVD
RSVD
RSV
VD
WAKE
DRIVE
INT_DRIVE:
INT pin drive mode.
0: open drain (default).
1: TTL.
HBI_WAKE:
Assert Wake to the DSP. This bit will be cleared by harware on the first HBI
clock after the DSP has responded.
0: No Wake event is present from HBI (defau
1: HBI is forcing a wake event to the DSP and ccks.
Note: RSVD pins need to bwritten s zero.
9.1.8 Select Page
This command selects the active interface page. It is a write ny commanand is followed by 0 data words. The 4-
bit page field allows up to 16 selectable pages per C to be efined.
9.1.9 Select CL Page
This command selects the special CL Code Lis a write only command and is followed by 0 data
words.
9.1.10 NOP
A command is reserved to servaa NOP. Note that all commands, except for the Offset Access commands, are
implemented by reservinan addrss from the direct page.
9.1.11 Assoted Regisers
The following regisrs are used by the HBI − CL Page Base Address Register (special type of base address
register code ading) and Mailbox Flag Register.
9.1.1e Base Address Register
Address:
Direct Page Offset 06 (High) and 07 (Low)
0000 0000h
Power Up Default:
This spcial base address register is used for code loading.
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Microsemi Corporation
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Data Sheet
D15
0
D14
0
D13
D12
D4
D11
D10
D9
D1
D8
Data Byte
Data Byte
BASE_ADDR[29:24]
D7
D6
D5
D3
D2
D
BASE_ADDR[23:16]
Table 10 - CL Page Base Address High Register (User)
D15
D7
D14
D6
D13
D5
D12
BASE_ADDR[15:8
D4 D3
D11
D10
D2
D9
D1
D8
D0
Data Byte
Data Byte
RSVD
Table 11 - CL Page Base AddLow Regier (User)
9.1.11.2 CL Page CRC
Address:
Direct Page Oset 04 (Hgh) and 0(Low)
Power Up Default:
0000 0000h
This special register is used to check code loagrity. Tis a witable and readable register. The booting
sequence should always write a predetermino this ster before loading the memory. Each write
through the CL page is fed into a CRC genunique code in this register. At the end of the booting
sequence, the user software should check for lue in this register.
D15
D7
14
D6
D13
D5
D12
D11
D10
D2
D9
D1
D8
D0
Data Byte
Data Byte
SEED[31:24]
D4
D3
SEED[23:16]
Table 12 - CL Page CRC High Register (User)
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Microsemi Corporation
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Data Sheet
D15
D7
D14
D6
D13
D12
D11
D3
D10
D2
D9
D1
D8
0
Data Byte
Data Byte
SEED[15:8]
D5
D4
SEED[7:0]
Table 13 - CL Page CRC Low Register (User)
SEED[31:0]: Current CRC value of data written to the CL page.
9.1.11.3 Mailbox Flag Register
Address:
Power Up Default:
Direct Page Offset 03
0000 0000h
This register is used to communicate the handshaking control flags betweethe DSP anthe host. There is one
flag for each mailbox in the system.
D15
D14
D13
D1
D1
D10
D9
D8
D0
Data Byte
Data Byte
MBOX_FAG[15:8]
D7
D6
5
4
MBOX_FAG[7:0]
Table 14 - Mailboegiste(Useand DSP, located in DSPIO)
D
D2
D1
MBOX_FLAG[15:0]: Mailbox flags. These bitd for downstream or upstream handshaking in order to
determine whether the host or the DSP owns box at any given point in time.
9.2 Code Loading
The NGCC SLAC device will aways come up n boot mode during a power-on reset or when the reset pin of the
chip is de-asserted. The DSwill hold f program execution until the on-chip CM location 0 has been written by the
host via the MPI interface. Thenaling or disabling of the boot operation during a hardware reset command is
controlled by the boot seuence ister bit in the Hardware Reset register. If the boot sequence is disabled when
the hardware reset commad is issud, the DSP immediately starts program execution from address 0 without any
boot operation.
The CL page basaddress regresides in the direct page and is accessible by the host. When the host writes
the upper 24-bits of he destination address to the CL page base address register and the lower 7-bits of the
addresset adress field of the paged offset command, the host can write up to 128 words of code/data
into addreses with the paged offset commands. The formula to compute the AMBA bus address
for pss commands with the CL page is:
AMBA address = base_addr * 256 + offset_ address * 2
9.2.1 Code Load Integrity
Code iegrity is guaranteed by CRC hardware which resides in this block. The CL Page CRC High and Low
regists are writable and readable registers. Any boot sequence should start with writing a seed into these
sters. Each subsequent write through the CL page will appropriately alter the value held in that register. It is
modified by both the address and the data of the write access. After all memory is loaded the user should read the
new value in the CL Page CRC register and compare it with the expected value. Any discrepancy indicates that the
code should be rebooted.
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Data Sheet
9.2.2 Host Boot Procedure
The sequence to perform the boot procedure through the MPI interface is outlined below.
1. Power-On Reset, hardware pin reset, or a hardware reset command with boot sequence enabled will put the
DSP into boot mode.
2. Initialize the CL Page CRC register with the desired seed.
3. Select the CL Page on an individual SLAC or to ALL SLAC devices.
4. Write the higher 24-bits of the destination bus address into the CL page base address registers, ae-
bits of the address into the offset address field of the paged offset access command. Usthe pageset
access command to write a block of code into DSP memory. Each access command can ite up to 28 16-bit
words of data.
5. Repeat step 4 for the next block of code into another block of DSP memory spc
6. After all the program codes are loaded, repeat steps 4-5 for PM data memory and DM data memory.
7. Check the CL Page CRC register to verify proper code load. If a loading err is present tn repeat starting at
step 2.
8. When all DSP memories are loaded, issue a paged offset access mnd to Caddress 0 in order to trigger
the DSP to start program execution.
9.2.3 Partial Code Load Procedure
After the boot procedure, the DSP will execute instructionconnuously. Ithe system wants to load a new codec
program, it requires a pre-defined mechanism between firmwe and thhost software so that the DSP would not
execute from the same code memory space this tryito ownload with new program code. There will
be a performance hit on the DSP, as each ite stels one cycle from the DSP operation. Since a
complete code load could take as long as 1host can not wait that long to process any interrupt.
Thus, the partial code load needs to patition thto manageable blocks in order to allow the system to
service an interrupt. The sequence to perrm paroading is outlined below.
1. Trigger the handshake betwn the DSP fmware and the host software to exchange information and ensure
the destination CM code emory is not being used by the DSP firmware. This mechanism is pre-defined by
firmware without any hardare asistance.
2. Initialize the CL Page RC witthe desired seed.
3. Select the CL Page registr on an dividual SLAC or on ALL SLAC devices.
4. Write the hig24-of thestined bus address into full access base register, and the lower 7-bit of the
address into the ffset address field of the paged offset access command. Use the paged offset access com-
mand te a blok of code into DSP memory. Each access command can write up to 128 16-bit words of
da
5. Rthe next block of code with size up to 128 16-bit words. Fill codes into different blocks of DSP
m
6. Finishe program code in the present block, then allow interrupts to be serviced by the host. At the end
of interrupt service routine or if no interrupt exists, go back to step 4 to load a new block of program code until all
the locks are loaded.
7. Chk the CL Page CRC registers to verify proper code load. If a loading error is present then repeat starting at
stp 2.
8. After all the program codes are loaded, trigger another predefined handshake between the DSP firmware and
the host software to indicate the end of partial code loading.
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Data Sheet
9.3 Application Layer
The application layer defines the programmer’s interface and is almost entirely implemented in firmware. The
exception is a handful of configuration registers implemented in hardware. This layer defines the meaning of the
payload data delivered by the transport layer. Because it is implemented in firmware, the definition of the host
programmer’s interface can change by providing a new ROM firmware image. The NG-SLAC programmer’s odel
is depicted in Figure 20.
The programmer’s model dedicates HBI pages 0 through 7 for channel specific registers, page 8 foCommand
Mailbox, and page 9 for the Response Mailbox. These register locations are all implemented in DSP
The direct page contains a small number of registers implemented by the hardware blocks n the AMbus. The
remainder of direct page registers are dedicated to global (not specific to a channel) registers, nd are iplemented
in DSP memory by the firmware.
Event Queue
Host Interface Address Spa(16-bit wo
Direct Page: Dict System Regers
Interrupt egister
Mailbox FlaRester
gisters
el (Indirect) Pages
External SPI Bus
Page mmand Mailbox
ge 9: Response Mailbox
INT
RAM Test Chip Code Memory
CL Page: Code Memory Window
Figure 20 - NGCC SLAC Programmer’s Mode
9.4 yer
9.4.1 Microprocessor Interface (MPI)
The mroprocessor Interface is an external interface of the NGCC SLAC device used by the external host to
commnicate with the device. The MPI interface is compatible with the SPI interface used by general DSPs, so that
thoschips can interface with the NGCC SLAC device without any glue logic.
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Data Sheet
9.4.1.1 MPI External Pins Connection
The MPI is a 3-wire or 4-wire synchronized serial interface used in many DSPs and micro controllers. The data is
transferred bidirectionally from master to slave and from slave to master. The master provides clock SCK to
synchronize the data transfer, and the signals SIMO and SOMI are for the data bit stream. SPI master can be a 3-
wire or 4-wire SPI master, depending on if the master drives the SS signal. If the master is a 3-wire SPI masr, the
master does not drive SS. Otherwise, the 4-wire SPI master pulls SS Low when transferring data. If the master a
3-wire SPI master, the SS pin at the slave can be tied Low in the single master/slave pair or connected to the GPI
output of the master in the multiple slaves system.
Signal Name
(SLAC MPI Pin Name)
SCK (DCLK)
SIMO (DIN)
Type
Description
I
SPI clock
I
SPI slave input/master output
SPI slave output/master input
SPI Slave select low
SOMI (DOUT)
SS (CS)
O
I
Table 15 - SPI Signals
The NGCC SLAC device will be the SPI slave, and the external ht will be I master. Signal SIMO will
connect to the DIN pin and signal SOMI will connect to the DOUT pin f the NGCC SLAC device. NGCC SLAC
devices sample the input signal DIN on the rising edge of he clock and hange the output signal DOUT on the
falling edge of the clock.
Figure 21 shows the SPI interface system with a 4-wire SPI mater. TI DSs and Motorola 68HC12s have a 4-wire
SPI master. For example, TI TMS320F28x chcan st the cip as the master (SPICTL[2]=1), 8-bit
(SPICCR[3:0]=7) transfer with clock polarity (1 fallig), lock phase (CPICTL[3]=0 no delay) or with
SPICCR[6]=0 (rising), CPICTL[3]=1 (delaythe NGCC SLAC device. Figure 22 shows the SPI
interface system with a 3-wire SPI master. MP/controllers, except 68HC12 and ADI DSP, have 3-
wire SPI masters. For example, Motora 68HCregister can set the Clock Phase (CPHA=0) with the
clock polarity (CPOL=0) or CPHA=1 with POL=1 ace with the NGCC SLAC device. One of the GPIO pins
is needed to drive the SS pin of te NGCC LAC dee. As the NGCC SLAC device supports command framing
on the SS pin, the GPIO pin of he master conncting to the SS pin of the slave is required, as shown in Figure 22.
SIMO
SOMI
SIMO
SOMI
DIN
SPI
DOUT
SPI Slave (MPI)
Master
SCK
SS
SCK
SS
DCLK
CS
NGCC SLAC device(s)
Figure 21 - 4-wire Master-Slave Connections
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Data Sheet
SIMO
SOMI
DIN
SIMO
SOMI
SPI
Master
DOUT
SPI Slave (MPI)
SCK
DCLK
CS
SCK
SS
GIO
NGCC SLAC device(s)
Figure 22 - 3-wire Master-Slave Connectios
9.4.1.2 MPI Features
In order to connect to different SPI masters, the MPI of the GCC SLAC dice has the following designs:
•
•
•
•
Separate input and output pins.
No daisy chain support.
No read latency: no latency between the reand wd ad the first data word.
CS pin supports byte/word framing, and ng mode, as shown in Figure 23. The SPI slave
state machine will reset if CS returns to Hmber of active DCLK pulses is not equal to 8 or 16.
If there is no clock, CS has to be Lw for mns to be recognized to reset SPI slave state
machine. In command framing modehe tranCS to High means the command has ended. This
event resets the SPI slave stae machi, and text falling edge of CS starts a new command.
Figure 23 shows three kinds oframing modes bsed on the behavior of CS. In byte/word framing mode, CS is Low
for 8/16 SCK clocks. For a tw-word cmmand, CS needs to toggle 4/2 times to complete the command transfer. In
command framing mode, CS Lw for the whole duration of the command transfer. When the command is
finished, CS will go back o Highf CS Low lasts shorter than the expected command length, the command is
aborted and the SPI slave tate mhine resets. However if the user pulls CS Low longer than the expected
command length, the extra wrds will start a new command sequence. In both byte/word framing mode and
command framinmode, K n be free-running or absent when CS is inactive High.
Every timreturnto High and the number of active DCLK pulses is not equal to 8 or 16, the SPI slave state
machiThe ext CS Low starts a new command sequence. In command framing mode, the transition
back the end of the command. If CS Low lasts less than 16 SCK clock cycles, no command byte is
proclasts more than 16 clock cycles, each 16-clock cycles triggers the SPI slave to process the
word back to High. The SPI slave will not reset state machine when CS Low lasts exactly 8 or 16
CK clo support byte/word framing mode. In byte/word framing mode, the user has to be aware of the
command length, as there is no indication of command boundary.
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Data Sheet
CS
DCLK
or
DCLK
cmd_wd byte hi
cmd_wd byte lo
Byte framing mode
data_wd byte low
DIN/
DOUT
data_wd byte hi
CS
DCLK
or
DCLK
command word
data wrd
DIN/
DOUT
Word framg mode
CS
DCLK
or
DCLK
DIN/
DOUT
commad word
data word
Command framing mode
Figure 23 - CS Framing Modes
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Data Sheet
The timing requirements for read and write accesses are shown in the following timing diagrams. The single data
word read and write command is shown in Figure 24 and Figure 25.
CS
DCLK
or
DCLK
DIN
cmd_wd[15:8]
cmd_wd[7:0]
data_wd[15:8]
data_wd[0]
DOUT
Figure 24 - One Data Word Write in Byte Framng Mode
CS
DCLK
or
DCLK
command
. . . .
DIN
DOUT
data word
Figu25 - One Data Word Read in Word Framing Mode
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Data Sheet
9.4.1.3 MPI Timing Specifications
Min and max values are valid for all digital outputs with a 150 pF load. Pictorial definitions for these parameters can
be found in Figure 26 and Figure 27.
Timing Diagram No.
Symbol
tDCY
Parameter
Data clock period
Min
Typ
Max
Unit
te
1
2
122
30
48
—
—
—
—
—
tDCH
Data clock HIGH pulse width
Data clock LOW pulse width
Rise time of clock
1
1
tDCL
3
—
—
tDCR
4
—
25
tDCF
5
Fall time of clock
—
—
25
tICSS
tICSH
tICSL
tICSO
tIDS
tDCY–10
tD–20
6
Chip select setup time, Input mode
Chip select hold time, Input mode
Chip select pulse width, Input mode
Chip select off time, Input mode
Input data setup time
30
0
—
7
—
CY
8
—
—
tDCY
9
—
—
1
tDCY–10
tDCY–10
tDCY–10
tDCH–20
10
11
13
14
15
16
17
18
19
20
5
30
30
0
ns
tIDH
Input data hold time
—
tOCSS
tOCSH
tOCSL
tOCSO
tODD
tODH
tODOF
tOD
Chip select setup time, Ouut mode
Chip select hold time, Outpumode
Chip select pulse Output mde
Chip select de
Output data
Outpdata hold
—
—
8tDCY
—
—
—
35
—
35
35
tDCY
—
—
—
—
—
1
2
—
3
Output daturn off d
Output data val
0
3
Table 16 - MPI Specifications
Note 1: DCLK may be stopped n the Higor Low state indefinitely without loss of information.
Note 2: The first data bit is enableon the fing edge of CS or on the falling edge of DCLK, whichever occurs last.
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Data Sheet
9.4.1.4 Timing Diagrams
1
2
5
VIH
VIH
DCLK
VIL
VIL
3
7
9
4
CS
6
8
10
11
Data
Valid
Data
Valid
Data
Valid
DIN
Figure 26 - r Interface (Input Mode)
VIH
VIL
DCLK
3
14
16
15
20
CS
18
19
VOH
VOL
Data
Valid
Data
Valid
Data
Valid
Three-State
Three-State
DOUT
Figure 27 - Microprocessor Interface (Output Mode)
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Data Sheet
10.0 PCM Highway
PCM interface features:
•
•
The PCM interface supports two transmit and receive PCM highways (A & B) using shared PCLK and FS
timing references.
The following PCLK (or highway) rates are supported for narrowband or wideband modes: 1.536 MHz, 2.08
MHz, 3.072 MHz, 4.096 MHz, 6.144 MHz, and 8.192 MHz (default). For narrowband mode, the following
PCLK rates are also supported: 1.544 MHz, 3.088 MHz, and 6.176 MHz. A valid PCLK is requr overall
device operation. These clock frequencies mean that 24 to 128 timeslots of 8 bits per highwale
in one frame of data. The timeslots are user programmable but are common for both highway cs. The
transmit data can be sent out either highway A or highway B or both highways simultaeously (ch is
programmable on a per channel basis).
•
•
An 8-kHz frame sync signal indicating the beginning of a transmit/receive framshall be suplied bthe
system and all timeslots shall be referenced to it.
The PCM interface can transmit/receive 8-bit compressed (A-law/µ-law) or 16-bit liar data with 8 kHz
sampling (narrowband), or 16-bit linear data with 16 kHz sampling (widand). Each te slot can carry one
A-law or µ-law PCM voice channel. Two timeslots are required to carry 16it linear data. n wideband mode,
two evenly spaced sets of 16-bit timeslots are exchanged in each frame. The ser programs the first timeslot
and the second set is generated automatically and placed 125om the fit timeslot (all wideband
supported PCLK frequencies exhibit an even number of timeslotsWhen progming transmit and receive
timeslots for wideband mode, the programmed timeslot must occur uring the first 62.5 µS of the frame.
•
•
Data can be transmitted on the positive or negative ege of PCLK. Recive data is always evaluated on the
negative edge of PCLK.
To avoid timing and clock skew problems, the PCM intee has a cck slot feature that allows the transmit
and receive data to be independently offset fre zero meslot efined in relation to the frame sync signal
applied. The clock slot permits 0-7 PCLK lay frote position defined by the applied frame
synchronization signal.
Pin Name
DXA
Type
Res
Description
O
O
O
O
Z
Z
Z
Z
Primarwnstream serial data output
Scondary downstream serial data output
Primary timeslot control signal (active low - open drain)
Secondary timeslot control signal (active low - open drain)
Primary upstream serial data input
DXB
TSCA
TSCB
DRA
DR
I
Secondary upstream serial data input
1.536 MHz - 8.192 MHz PCM Interface clock
8-kHz frame sync
PCLK
I
I
Table 17 - PCM Interface Pins
10.1 smit Interface
The PCM transmit interface controls the transmission of data onto the PCM highway through the output port
selectin circuitry and the time and clock slot control block. The timeslot control signals (TSCA/TSCB) go low
wheneer PCM data is transmitted on the DXA/DXB pin. These signals can be used for arbitration when there are
multipdevices connected to the PCM bus. The data can be transmitted on either edge of PCLK. The clock edge
hich the data is transmitted is selected by the XE bit in the PCM Configuration Register. The data is transmitted
with the most significant bit first.
The Frame Sync (FS) pulse identifies timeslot 0 of the transmit frame and all timeslots are referenced to it.
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Data Sheet
10.2 PCM Receive Interface
The PCM Receive interface logic controls the reception of the data bytes from the PCM highway. Each timeslot is
associated with one 8-bit data byte. The data is received with the most significant bit first. The received data coming
on the DR pin is latched at the falling edge of PCLK.
CASE 1 : DEFAULT: XE = RCS = TCS = 0 (8-bit TRANSFERS)
PCLK
FS
RX6
RX4
RX2
TX2
RX0
TX0
RX7
RX5
RX1
TX1
RX3
DR
TX5
TX4
DX
TX6
TX3
TX7
Timeslot 0
TSC
CASE 2 : XE = 1 RCS = 2 TCS = 4 (8-bit TSFERS)
PCLK
FS
DR
RX6
RX4
T
RX2
TX4
RX0
TX2
RX7
RX5
7
RX1
TX3
RX3
X5
DX
TSC
Timeslot 0
Fige 28 - hway 8-bit Transfers
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Data Sheet
CASE 1 : XE = RCS = TCS = 0 (16-BIT TRANSFERS)
PCLK
FS
DR
RX9
RX7
RX4
RX14 RX13 RX12 RX11 RX10
RX8
RX6 RX5
RX3 RX2 RX1 RX0
RX15
TX9
TX7
TX4
TX14 TX13 TX12 TX11 TX10
TX8
TX6 TX5
TX3 TX2 TX1 TX0
TX15
DX
timeslot1
timeslot0
TSC
CASE 2 : XE = 1 RCS = TCS = 0 (16-BIT TRANSFER
PCLK
FS
DR
RX9
TX9
RX7
TX7
RX4
TX4
RX14 RX13 RX12 RX11 RX10
RX8
TX8
RX6 RX5
TXTX5
RX3 RX2 RX1 RX0
TX3 TX2 TX1 TX0
RX15
TX14 TX13 TX12 TX11 TX10
TX15
DX
timeslot1
timeslot0
TSC
Figure 29 - PCM Highy 16-bit ransfers
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Data Sheet
10.3 PCM Interface Timing
Min and max values are valid for all digital outputs with a 150 pF load. Pictorial definitions for these parameters can
be found in Figure 30 and Figure 31. PCLK accuracy = ± 100 PPM.
Timing Diagram No.
Symbol
tPCY
Parameter
PCM clock period
Min.
Typ
Max
Unit
ote
22
23
24
25
26
27
122
48
48
—
—
—
—
—
—
—
651
1
tPCH
tPCL
PCM clock HIGH pulse width
PCM clock LOW pulse width
Fall time of clock
—
—
tPCF
8
tPCR
tFSS
Rise time of clock
—
tPCY–30
FS setup time
30
25000-
3t--30
tFSH
28
FS hold time
50
—
tTSD
tTSO
tDXD
tDXH
tDXZ
tDRS
tDRH
29
30
31
32
33
34
35
Delay to TSCX valid
5
—
—
—
—
—
—
25
10
2
3
ns
Delay to TSCX off
PCM data output delay
PCM data output hold time
PCM data output delay to hi-Z
PCM data input setup time
5
25
5
25
0
10
3
tPCY–10
tPCY–20
5
PCM data input
5
—
—
—
Narrowband itter time
Wideband PCLK r time
–60
–30
60
30
tFST
ble 18 pecifications
Note:
1. Supported PCM clock (PCLK) quencies ae listed in “CM Highway” on page 50.
2. TSCX is delayed from FS by a tyal ve of N • tPCY, where N is the value stored in the time/clock slot register.
3. TSCX is an open drain drir. The tTSis defined as the delay time the output driver turns off after the PCLK transaction. The actual delay
time is dependent on the loaircuitry. Tmaximum load capacitance on TSCX is 150 pF and the minimum pull-up resistance is 360 Ω.
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Data Sheet
Time Slot Zero, Clock Slot Zero
27
22
25
26
VIH
VIL
PCLK
23
24
28
FS
30
29
TSCA
See Note 4
31
32
33
VOH
First
DXA
DRA
Bit
VOL
35
Fi
Bit
d
Figure 30 PCM HighwTiming for XE = 0 (Transmit on Negative PCLK Edge)
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Data Sheet
Time Slot Zero, Clock Slot Zero
27
22
25
26
VIH
VIL
PCLK
23
24
FS
28
30
29
TSCA
DXA
See Note 4
31
32
33
VOH
First
Bit
VOL
First
Bit
DRA
Figure 31 - PM Highway ming for XE = 1 (Transmit on Positive PCLK Edge)
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Data Sheet
11.0 P-Bus and GPIO Interfaces
The SLAC utilizes a digital control bus (P-Bus) to send control signals to SLIC devices. The P-Bus interface uses a
4 bit parallel bus (SEL, P[2:0]) and eight individual load or chip select pins (LD[7:0]) to control the FXS state and
Switch state of up to eight SLIC devices. The SEL signal determines whether the P[2:0] value is assigned to the
FXS state (SEL=0) or the Switch state (SEL=1). The P[2:0] and SEL values are latched inside the SLIC n the
rising edge of the active low LD[n] signal. The P-Bus operates continuously so that each channel’s FXS and Swch
states are automatically refreshed every 128 msec or whenever a SLIC mode changes.
Each channel is assigned two general purpose SLAC IO pins, IOn_0 and IOn_1. IOn_0 can be confither
a CMOS input, a CMOS output, or an open drain 50 mA relay driver. IOn_1 can be configured as eCMOS
input or CMOS output.
State in
Reset
Pin Name
Type
Descrtion
P[2:0]
SEL
O
O
0
0
P-Bus for controlling SLIC FXS anSLIC Switch stes.
0 = P-Bus defines SLIC FXS state.
1 = P-Bus defines SLIC h state.
LD[7:0]
O
1
Active Low Load sinal for S and Switch states.
The P[2:0] and SL pin valuere latched inside the SLIC on the rising
edge of LD[n]
IO1_[1:0]
IO2_[1:0]
IO3_[1:0]
IO4_[1:0]
IO5_[1:0]
IO6_[1:0]
IO7_[1:0]
IO8_[1:0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/
Input
Input
Input
Input
Input
Input
Input
Int
SLAC Inpuutput foChannel 1
SLAC Input/Oufor Chann2
SOutput r Chnnel 3
put for Channel 4
These pins change state on
the rising edge of FS.
ut for Channel 5
SLAutput for Channel 6
LAC Input/Output for Channel 7
SLInput/Output for Channel 8
Table 19 - P-Bus and SLAC IO Pins
P-Bus timing is derived from n internl 49.152 MHz SLAC clock and the 8 kHz FS input. The clock is used to
generate the timfor P[2:0SEL, and LD[n] signals for each channel. The 8 kHz FS timing reference is used
to generate the 16 sec delay between channel loads (see Figure 32 and Figure 33).
When is wren which initiates a change to an FXS or Switch state, the new value is written to the SLIC
devi.
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Data Sheet
SEL
FXS State SW State
FXS State SW State
P0,P1,P2
LD1
LD2
5.2 us
5.2 us
10.4 us
16 ms
Figure 32 - Channel Timing for P-Bs SLIC Ince
128 s (7.8125 z)
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
16 ms
Figure 33 - Global Timing for SLIC Device Bus Interface
Note:
An additional P-bus interaction will occur in no more than 625 µs following a drive state change request. Then, the affected LD line will return to
its norm128 ms refresh cycle.
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Data Sheet
11.1 SLIC Device Bus Timing Specifications
Pictorial definitions for these parameters can be found in Figure 34.
Timing
Diagram No.
Symbol
trSLD
Signal
LD[1:8]
Parameter
Rise time
Min
Typ
Max
U
1
2
3
4
5
6
2
2
tfSLD
LD[1:8]
Fall time
tSLDPW
tSDXSU
tSDXHD
tSDXPW
LD[1:8]
Pulse width
Setup time
Hold time
Pulse width
3
2
2
7
s
P0, P1, P2, SEL
P0, P1, P2, SEL
P0, P1, P2, SEL
Table 20 - SLIC Device Bus Timing Specifications
SEL
FXS State SW State
FXS State SW State
P0,P1,P2
LD1
LD2
5.2 us
5.2 us
10.4 us
V
VOL
LD[1:8]
2
3
6
4
5
P0,P1,P2,SEL
Figure 34 - SLIC Device Bus Timing Waveform
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Data Sheet
12.0 Relay Drivers
The IO[1:8]_0 pins can be programmed as open drain relay drivers. They are capable of sinking 50 mA of current
@ 0.7 V.
Built-in integrated flyback diodes eliminate the need for external diodes across the relay coils.
The IO[1:8]_1 pins are capable of sinking 10 mA as an output. They can be used with an external transistor to dre
a relay.
+3.
sply
VDD33_[1;2]
Relay
coil
IO[1:8]_0
Le79238
DGND_[1:6]
Figuain Relay Drivers
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Data Sheet
13.0 Physical Dimensions
13.1 176-Pin LQFP
NoPackages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
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Data Sheet
13.2 164-Pin LGA
See 4.1, “Green Package Assembly“ for additional information on this package.
Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
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Data Sheet
13.3 196-Pin BGA
Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
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Microsemi Corporation
Le79238
Data Sheet
For more information about all Microsemi CMPG pducts
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Information relating to products and services furnished herein by Microsemi Coration its subsidiaries (collectively “Microsemi”) is believed to be reliable.
However, Microsemi assumes no liability for errors that may appear in this publicon, for liability oerwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual prty rights ownby third parties which may result from such application or
use. Neither the supply of such information or purchase of product or e conveys y license, ther express or implied, under patents or other intellectual
property rights owned by Microsemi or licensed from third parties by hatsoeveurchers of products are also hereby notified that the use of product
in certain ways or in combination with Microsemi, or non-Microseor servis ay infringe patents or other intellectual property rights owned by
Microsemi.
This publication is issued to provide information only and (unlen writing) may not be used, applied or reproduced for any purpose nor form
part of any order or contract nor to be regarded as a representatiucts or services concerned. The products, their specifications, services and
other information appearing in this publication are subjto changout notice. No warranty or guarantee express or implied is made regarding
the capability, performance or suitability of any product service. Ierning possible methods of use is provided as a guide only and does not
constitute any guarantee that such methods of use will satisfactocific piece of equipment. It is the user’s responsibility to fully determine the
performance and suitability of any equipment ug such infoation and re that any publication or data used is up to date and has not been superseded.
Manufacturing does not necessarily include ting of all functioor paramrs. These products are not suitable for use in any medical products whose failure to
perform may result in significant injury or deh to the user. All prodts and materials are sold and services provided subject to Microsemi’s conditions of sale which
are available on request.
Microsemi, the Microsemi logo, rlink, and binations thereof, Power Matters, SLAC, VeriVoice, VoiceEdge, VoicePort, and VoicePath are trademarks or
registered trademarks of Microsemi rporationl other trademarks mentioned in this document are the property of their respective owners.
Copyright © 2012. All Rights Reserved
TECHNICAL DOCUMENTATION - NOT FOR RESALE
Microsmi documents marked "Preliminary" relate to products which are not yet released to production and are identified with an "ENG" suffix in their part number.
products and their associated Preliminary Data Sheet specifications are supplied only for testing and on the express understanding that (i) such products have
not been fully tested or characterized under intended modes of operation and may contain defects; (ii) Microsemi makes no representation or warranty regarding such
products or Preliminary Data Sheets; and (iii) Microsemi disclaims any liability for claims,demands and damages, including and without limitation special, indirect and
consequential damages resulting from any loss arising out of the application, use or performance of such products or specifications. Such products and Preliminary
Data Sheets may be changed or discontinued by Microsemi at any time without notice.
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Microsemi Corporation
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