M25P40-VMC6Txx_技术文档

Micron M25P40 Serial Flash Embedded Memory

Features

Micron M25P40 Serial Flash Embedded

Memory

M25P40-VMB6Txx

M25P40-VMC6Gx; M25P40-VMC6Txx

M25P40-VMN3Px; M25P40-VMN3Txx

M25P40-VMN6Pxx; M25P40-VMN6Txxx

M25P40-VMP6Gx; M25P40-VMP6Txx

M25P40-VMS6Gx; M25P40-VMS6Tx

M25P40-VMW6Gx; M25P40-VMW6Txx

• Electronic signature

– JEDEC-standard 2-byte signature (2013h)

– Unique ID code (UID) with 16-byte read-only

space, available upon request

Features

• SPI bus-compatible serial interface

• 4Mb Flash memory

• 75 MHz clock frequency (maximum)

• 2.3V to 3.6V single supply voltage

• Page program (up to 256 bytes) in 0.8ms (TYP)

• Erase capability

– Sector erase: 512Kb in 0.6 s (TYP)

– Bulk erase: 4Mb in 4.5 s (TYP)

• Write protection

– RES command, one-byte signature (12h) for

backward compatibility

• More than 100,000 write cycles per sector

• Automotive-grade parts available

• Packages (RoHS-compliant)

– SO8N (MN) 150 mils

– SO8W (MW) 208 mils

– Hardware write protection: protected area size

defined by nonvolatile bits BP0, BP1, BP2

• Deep power-down: 1µA (TYP)

– DFN8 (MS) MLP8, 6mm x 5mm

– VFDFPN8 (MP) MLP8 6mm x 5mm

– UFDFPN8 (MC) MLP8 4mm x 3mm

– UFDFPN8 (MB) MLP8 2mm x 3mm

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Products and specifications discussed herein are subject to change by Micron without notice.

Micron M25P40 Serial Flash Embedded Memory

Features

Contents

Functional Description ..................................................................................................................................... 6

Signal Descriptions ........................................................................................................................................... 8

SPI Modes ........................................................................................................................................................ 9

Operating Features ......................................................................................................................................... 11

Page Programming ..................................................................................................................................... 11

Sector Erase, Bulk Erase .............................................................................................................................. 11

Polling during a Write, Program, or Erase Cycle ............................................................................................ 11

Active Power, Standby Power, and Deep Power-Down .................................................................................. 11

Status Register ............................................................................................................................................ 12

Data Protection by Protocol ........................................................................................................................ 12

Software Data Protection ............................................................................................................................ 12

Hardware Data Protection .......................................................................................................................... 12

Hold Condition .......................................................................................................................................... 13

Configuration and Memory Map ..................................................................................................................... 14

Memory Configuration and Block Diagram .................................................................................................. 14

Memory Map – 4Mb Density ........................................................................................................................... 15

Command Set Overview ................................................................................................................................. 16

WRITE ENABLE .............................................................................................................................................. 18

WRITE DISABLE ............................................................................................................................................. 19

READ IDENTIFICATION ................................................................................................................................. 20

READ STATUS REGISTER ................................................................................................................................ 22

WIP Bit ...................................................................................................................................................... 23

WEL Bit ...................................................................................................................................................... 23

Block Protect Bits ....................................................................................................................................... 23

SRWD Bit ................................................................................................................................................... 23

WRITE STATUS REGISTER .............................................................................................................................. 24

READ DATA BYTES ......................................................................................................................................... 26

READ DATA BYTES at HIGHER SPEED ............................................................................................................ 27

PAGE PROGRAM ............................................................................................................................................ 28

SECTOR ERASE .............................................................................................................................................. 29

BULK ERASE .................................................................................................................................................. 30

DEEP POWER-DOWN ..................................................................................................................................... 31

RELEASE from DEEP POWER-DOWN .............................................................................................................. 32

READ ELECTRONIC SIGNATURE .................................................................................................................... 33

Power-Up/Down and Supply Line Decoupling ................................................................................................. 34

Power-Up Timing and Write Inhibit Voltage Specifications ............................................................................... 36

Maximum Ratings and Operating Conditions .................................................................................................. 37

Electrical Characteristics ................................................................................................................................ 38

AC Characteristics .......................................................................................................................................... 40

Package Information ...................................................................................................................................... 48

Device Ordering Information .......................................................................................................................... 54

Standard Parts ............................................................................................................................................ 54

Automotive Parts ........................................................................................................................................ 55

Revision History ............................................................................................................................................. 56

Rev. Y – 8/12 ............................................................................................................................................... 56

Rev. X – 04/12 ............................................................................................................................................. 56

Rev. W – 03/12 ............................................................................................................................................ 56

Rev. V – 02/12 ............................................................................................................................................. 56

Rev. U – 09/2011 ......................................................................................................................................... 56

Rev. 20.0 – 04/2010 ..................................................................................................................................... 56

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Micron M25P40 Serial Flash Embedded Memory

Features

Rev. 19.0 – 02/2010 ..................................................................................................................................... 56

Rev. 18.0 – 05/2009 ..................................................................................................................................... 56

Rev. 17.0 – 02/2009 ..................................................................................................................................... 56

Rev. 16.0 – 10/2008 ..................................................................................................................................... 57

Rev. 15.0 – 12/2007 ..................................................................................................................................... 57

Rev. 14.0 – 06/2007 ..................................................................................................................................... 57

Rev. 13.0 – 05/2007 ..................................................................................................................................... 57

Rev. 12.0 – 01/2007 ..................................................................................................................................... 57

Rev. 11.0 – 12/2006 ..................................................................................................................................... 57

Rev. 10.0 – 06/2006 ..................................................................................................................................... 58

Rev. 9.0 – 04/2006 ....................................................................................................................................... 58

Rev. 8.0 – 12/2005 ....................................................................................................................................... 58

Rev. 7.0 – 10/2005 ....................................................................................................................................... 58

Rev. 6.0 – 08/2005 ....................................................................................................................................... 58

Rev. 5.0 – 01/2005 ....................................................................................................................................... 58

Rev. 4.0 – 08/2004 ....................................................................................................................................... 58

Rev. 3.0 – 03/2004 ....................................................................................................................................... 59

Rev. 2.0 – 11/2003 ....................................................................................................................................... 59

Rev. 1.0 – 06/2003 ....................................................................................................................................... 59

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Micron M25P40 Serial Flash Embedded Memory

Features

List of Figures

Figure 1: Logic Diagram ................................................................................................................................... 6

Figure 2: Pin Connections: SO8, MLP8 ............................................................................................................. 7

Figure 3: SPI Modes Supported ........................................................................................................................ 9

Figure 4: Bus Master and Memory Devices on the SPI Bus ............................................................................... 10

Figure 5: Hold Condition Activation ............................................................................................................... 13

Figure 6: Block Diagram ................................................................................................................................ 14

Figure 7: WRITE ENABLE Command Sequence .............................................................................................. 18

Figure 8: WRITE DISABLE Command Sequence ............................................................................................. 19

Figure 9: READ IDENTIFICATION Command Sequence ................................................................................. 21

Figure 10: READ STATUS REGISTER Command Sequence .............................................................................. 22

Figure 11: Status Register Format ................................................................................................................... 22

Figure 12: WRITE STATUS REGISTER Command Sequence ............................................................................. 24

Figure 13: READ DATA BYTES Command Sequence ........................................................................................ 26

Figure 14: READ DATA BYTES at HIGHER SPEED Command Sequence ........................................................... 27

Figure 15: PAGE PROGRAM Command Sequence ........................................................................................... 28

Figure 16: SECTOR ERASE Command Sequence ............................................................................................. 29

Figure 17: BULK ERASE Command Sequence ................................................................................................. 30

Figure 18: DEEP POWER-DOWN Command Sequence ................................................................................... 31

Figure 19: RELEASE from DEEP POWER-DOWN Command Sequence ............................................................. 32

Figure 20: READ ELECTRONIC SIGNATURE Command Sequence .................................................................. 33

Figure 21: Power-Up Timing .......................................................................................................................... 35

Figure 22: AC Measurement I/O Waveform ..................................................................................................... 40

Figure 23: Serial Input Timing ........................................................................................................................ 46

Figure 24: Write Protect Setup and Hold during WRSR when SRWD=1 Timing ................................................. 46

Figure 25: Hold Timing .................................................................................................................................. 47

Figure 26: Output Timing .............................................................................................................................. 47

Figure 27: SO8N 150 mils Body Width ............................................................................................................ 48

Figure 28: SO8W 208 mils Body Width ............................................................................................................ 49

Figure 29: DFN8 6mm x 5mm ........................................................................................................................ 50

Figure 30: VFDFPN8 (MLP8) 6mm x 5mm ...................................................................................................... 51

Figure 31: UFDFPN8 (MLP8) 4mm x 3mm ...................................................................................................... 52

Figure 32: UFDFPN8 (MLP8) 2mm x 3mm ...................................................................................................... 53

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Micron M25P40 Serial Flash Embedded Memory

Features

List of Tables

Table 1: Signal Names ...................................................................................................................................... 7

Table 2: Signal Descriptions ............................................................................................................................. 8

Table 3: Protected Area Sizes .......................................................................................................................... 12

Table 4: Sectors[7:0] ...................................................................................................................................... 15

Table 5: Command Set Codes ........................................................................................................................ 17

Table 6: READ IDENTIFICATION Data Out Sequence ..................................................................................... 20

Table 7: Status Register Protection Modes ...................................................................................................... 24

Table 8: Power-Up Timing and V_WIThreshold ................................................................................................. 36

Table 9: Absolute Maximum Ratings .............................................................................................................. 37

Table 10: Operating Conditions ...................................................................................................................... 37

Table 11: Data Retention and Endurance ........................................................................................................ 37

Table 12: DC Current Specifications (Device Grade 6) ..................................................................................... 38

Table 13: DC Voltage Specifications (Device Grade 6) ...................................................................................... 38

Table 14: DC Current Specifications (Device Grade 3) ..................................................................................... 38

Table 15: DC Voltage Specifications (Device Grade 3) ...................................................................................... 39

Table 16: Device Grade and AC Table Correlation ............................................................................................ 40

Table 17: AC Measurement Conditions ........................................................................................................... 40

Table 18: Capacitance .................................................................................................................................... 40

Table 19: Instruction Times, Process Technology 110nm ................................................................................. 41

Table 20: Instruction Times, Process Technology 150nm ................................................................................. 41

Table 21: AC Specifications (25 MHz, Device Grade 3, V_CC[min]=2.7V) ............................................................. 41

Table 22: AC Specifications (50 MHz, Device Grade 6, V_CC[min]=2.7V) ............................................................. 42

Table 23: AC Specifications (40 MHz, Device Grade 6, V_CC[min]=2.3V) ............................................................. 43

Table 24: AC Specifications (75MHz, Device Grade 3 and 6, V_CC[min]=2.7V) .................................................... 45

Table 25: Part Number Example ..................................................................................................................... 54

Table 26: Part Number Information Scheme ................................................................................................... 54

Table 27: Part Number Example ..................................................................................................................... 55

Table 28: Part Number Information Scheme ................................................................................................... 55

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Micron M25P40 Serial Flash Embedded Memory

Functional Description

The M25P40 is an 4Mb (512Kb x 8) serial Flash memory device with advanced write-

protection mechanisms accessed by a high-speed SPI-compatible bus. The device sup-

ports high-performance commands for clock frequency up to 75MHz.

The memory can be programmed 1 to 256 bytes at a time using the PAGE PROGRAM

command. It is organized as 8 sectors, each containing 256 pages. Each page is 256

bytes wide.

The entire memory can be erased using the BULK ERASE command, or it can be erased

one sector at a time using the SECTOR ERASE command.

This data sheet details the functionality of the M25P40 device based on either the

150nm process or on the current 110nm process. The most current device in the 110nm

process has the following additional features and is completely backward compatible

with the 150nm device:

• Maximum frequency (READ DATA BYTES at HIGHER SPEED operation) in the stand-

ard V_CCrange 2.7V to 3.6V equals 75MHz

• Maximum frequency (READ DATA BYTES at HIGHER SPEED operation) in the exten-

ded V_CCrange 2.3V to 2.7V equals 40MHz

• UID/CFD protection feature

Note:

75MHz operation is available only on the V_CCrange 2.7V to 3.6V and for 110nm process

technology devices, identified by process identification digit 4 in the device marking

and process letter B in the part number.

Figure 1: Logic Diagram

V

CC

DQ0

C

DQ1

S#

W#

HOLD#

V

SS

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Micron M25P40 Serial Flash Embedded Memory

Functional Description

Table 1: Signal Names

Signal Name

Function

Direction

Input

C

Serial clock

DQ0

DQ1

S#

Serial data input

Serial data output

Chip select

Input

Output

Input

W#

HOLD#

V_CC

V_SS

Write protect or enhanced program supply voltage

Input

Hold

Input

Supply voltage

Ground

–

Figure 2: Pin Connections: SO8, MLP8

V

1

2

3

4

8

7

6

5

S#

DQ1

W#

CC

HOLD#

C

V

DQ0

SS

There is an exposed central pad on the underside of the MLP8 package that is pulled

internally to V_SS, and must not be connected to any other voltage or signal line on the

PCB. The Package Mechanical section provides information on package dimensions

and how to identify pin 1.

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Micron M25P40 Serial Flash Embedded Memory

Signal Descriptions

Table 2: Signal Descriptions

Signal

Type

Description

DQ1

Output

Serial data: The DQ1 output signal is used to transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock (C).

DQ0

C

Input

Serial data: The DQ0 input signal is used to transfer data serially into the device. It

receives commands, addresses, and the data to be programmed. Values are latched on

the rising edge of the serial clock (C).

Clock: The C input signal provides the timing of the serial interface. Commands, ad-

dresses, or data present at serial data input (DQ0) is latched on the rising edge of the

serial clock (C). Data on DQ1 changes after the falling edge of C.

S#

Chip select: When the S# input signal is HIGH, the device is deselected and DQ1 is at

HIGH impedance. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cy-

cle is in progress, the device will be in the standby power mode (not the DEEP POWER-

DOWN mode). Driving S# LOW enables the device, placing it in the active power

mode. After power-up, a falling edge on S# is required prior to the start of any com-

mand.

HOLD#

W#

Input

Hold: The HOLD# signal is used to pause any serial communications with the device

without deselecting the device. During the hold condition, DQ1 is High-Z. DQ0 and C

are "Don’t Care." To start the hold condition, the device must be selected, with S#

driven LOW.

Write protect: The W# input signal is used to freeze the size of the area of memory

that is protected against program or erase commands as specified by the values in

BP2, BP1, and BP0 bits of the Status Register.

V_CC

V_SS

Input

Device core power supply: Source voltage.

Ground: Reference for the V_CCsupply voltage.

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Micron M25P40 Serial Flash Embedded Memory

SPI Modes

These devices can be driven by a microcontroller with its serial peripheral interface

(SPI) running in either of the following two SPI modes:

• CPOL=0, CPHA=0

• CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of serial clock (C), and

output data is available from the falling edge of C.

The difference between the two modes is the clock polarity when the bus master is in

STANDBY mode and not transferring data:

• C remains at 0 for (CPOL=0, CPHA=0)

• C remains at 1 for (CPOL=1, CPHA=1)

Figure 3: SPI Modes Supported

CPOL

0

CPHA

0

C

1

DQ0

DQ1

MSB

Because only one device is selected at a time, only one device drives the serial data out-

put (DQ1) line at a time, while the other devices are HIGH-Z. An example of three devi-

ces connected to an MCU on an SPI bus is shown here.

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Micron M25P40 Serial Flash Embedded Memory

SPI Modes

Figure 4: Bus Master and Memory Devices on the SPI Bus

V

SS

V

CC

R

SDO

SDI

SPI interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SCK

C

V

CC

C

CC

V

SS

SPI Bus Master

DQ1 DQ0

SPI memory

device

SPI memory

device

SPI memory

device

R

CS3

CS2

CS1

W#

HOLD#

S#

W# HOLD#

S#

W#

HOLD#

1. WRITE PROTECT (W#) and HOLD# should be driven HIGH or LOW as appropriate.

Notes:

2. Resistors (R) ensure that the memory device is not selected if the bus master leaves the

S# line HIGH-Z.

3. The bus master may enter a state where all I/O are HIGH-Z at the same time; for exam-

ple, when the bus master is reset. Therefore, the C must be connected to an external

pull-down resistor so that when all I/O are HIGH-Z, S# is pulled HIGH while C is pulled

LOW. This ensures that S# and C do not go HIGH at the same time and that the ^tSHCH

requirement is met.

4. The typical value of R is 100 kΩ, assuming that the time constant R × C_p(C_p= parasitic

capacitance of the bus line) is shorter than the time during which the bus master leaves

the SPI bus HIGH-Z.

5. Example: Given that C_p= 50 pF (R × C_p= 5μs), the application must ensure that the bus

master never leaves the SPI bus HIGH-Z for a time period shorter than 5μs.

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Micron M25P40 Serial Flash Embedded Memory

Operating Features

Page Programming

To program one data byte, two commands are required: WRITE ENABLE, which is one

byte, and a PAGE PROGRAM sequence, which is four bytes plus data. This is followed by

the internal PROGRAM cycle of duration t_PP. To spread this overhead, the PAGE PRO-

GRAM command allows up to 256 bytes to be programmed at a time (changing bits

from 1 to 0), provided they lie in consecutive addresses on the same page of memory. To

optimize timings, it is recommended to use the PAGE PROGRAM command to program

all consecutive targeted bytes in a single sequence than to use several PAGE PROGRAM

sequences with each containing only a few bytes.

Sector Erase, Bulk Erase

The PAGE PROGRAM command allows bits to be reset from 1 to 0. Before this can be

applied, the bytes of memory need to have been erased to all 1s (FFh). This can be ach-

ieved a sector at a time using the SECTOR ERASE command, or throughout the entire

memory using the BULK ERASE command. This starts an internal ERASE cycle of dura-

tion t_SSE, t_SEor t_BE. The ERASE command must be preceded by a WRITE ENABLE com-

mand.

Polling during a Write, Program, or Erase Cycle

An improvement in the time to complete the following commands can be achieved by

not waiting for the worst case delay (t_W, t_PP, t_SE, or t_BE).

• WRITE STATUS REGISTER

• PROGRAM

• ERASE (SECTOR ERASE, BULK ERASE)

The write in progress (WIP) bit is provided in the status register so that the application

program can monitor this bit in the status register, polling it to establish when the pre-

vious WRITE cycle, PROGRAM cycle, or ERASE cycle is complete.

Active Power, Standby Power, and Deep Power-Down

When chip select (S#) is LOW, the device is selected, and in the ACTIVE POWER mode.

When S# is HIGH, the device is deselected, but could remain in the ACTIVE POWER

mode until all internal cycles have completed (PROGRAM, ERASE, WRITE STATUS

REGISTER). The device then goes in to the STANDBY POWER mode. The device con-

sumption drops to I_CC1

.

The DEEP POWER-DOWN mode is entered when the DEEP POWER-DOWN command

is executed. The device consumption drops further to I_CC2. The device remains in this

mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While in

the DEEP POWER-DOWN mode, the device ignores all WRITE, PROGRAM, and ERASE

commands. This provides an extra software protection mechanism when the device is

not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or

ERASE operations. For further information, see the DEEP POWER DOWN command.

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Micron M25P40 Serial Flash Embedded Memory

Operating Features

Status Register

The status register contains a number of status and control bits that can be read or set

(as appropriate) by specific commands. For a detailed description of the status register

bits, see READ STATUS REGISTER (page 22).

Data Protection by Protocol

Non-volatile memory is used in environments that can include excessive noise. The fol-

lowing capabilities help protect data in these noisy environments.

Power on reset and an internal timer (t_PUW) can provide protection against inadvertent

changes while the power supply is outside the operating specification.

WRITE, PROGRAM, and WRITE STATUS REGISTER commands are checked before they

are accepted for execution to ensure they consist of a number of clock pulses that is a

multiple of eight.

All commands that modify data must be preceded by a WRITE ENABLE command to set

the write enable latch (WEL) bit.

In addition to the low power consumption feature, the DEEP POWER-DOWN mode of-

fers extra software protection since all WRITE, PROGRAM, and ERASE commands are

ignored when the device is in this mode.

Software Data Protection

Memory can be configured as read-only using the block protect bits (BP2, BP1, BP0) as

shown in the Protected Area Sizes table.

Hardware Data Protection

Hardware data protection is implemented using the write protect signal applied on the

W# pin. This freezes the status register in a read-only mode. In this mode, the block pro-

tect (BP) bits and the status register write disable bit (SRWD) are protected.

Table 3: Protected Area Sizes

Status Register Content

Memory Content

BP Bit 2

BP Bit 1

BP Bit 0

Protected Area

Unprotected Area

0

1

0

1

0

1

0

1

0

1

0

1

0

1

none

All sectors (sectors 0 to 7)

Upper 8th (sectors 7)

Lower 7/8ths (sectors 0 to 6)

Upper 4th (sectors 6 and 7)

Upper half (sectors 4 to 7)

All sectors (sectors 0 to 7)

Lower 3/4ths (sectors 0 to 5)

Lower half (sectors 0 to 3)

none

1. 0 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command

only if all block protect bits (BP2, BP1, BP0) are 0.

Note:

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Micron M25P40 Serial Flash Embedded Memory

Operating Features

Hold Condition

The HOLD# signal is used to pause any serial communications with the device without

resetting the clocking sequence. However, taking this signal LOW does not terminate

any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in progress.

To enter the hold condition, the device must be selected, with S# LOW. The hold condi-

tion starts on the falling edge of the HOLD# signal, if this coincides with serial clock (C)

being LOW. The hold condition ends on the rising edge of the HOLD# signal, if this co-

incides with C being LOW. If the falling edge does not coincide with C being LOW, the

hold condition starts after C next goes LOW. Similarly, if the rising edge does not coin-

cide with C being LOW, the hold condition ends after C next goes LOW.

During the hold condition, DQ1 is HIGH impedance while DQ0 and C are Don’t Care.

Typically, the device remains selected with S# driven LOW for the duration of the hold

condition. This ensures that the state of the internal logic remains unchanged from the

moment of entering the hold condition. If S# goes HIGH while the device is in the hold

condition, the internal logic of the device is reset. To restart communication with the

device, it is necessary to drive HOLD# HIGH, and then to drive S# LOW. This prevents

the device from going back to the hold condition.

Figure 5: Hold Condition Activation

C

HOLD#

HOLD condition (standard use)

HOLD condition (nonstandard use)

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Micron M25P40 Serial Flash Embedded Memory

Configuration and Memory Map

Memory Configuration and Block Diagram

Each page of memory can be individually programmed; bits are programmed from 1 to

0. The device is sector or bulk-erasable, but not page-erasable; bits are erased from 0 to

1. The memory is configured as follows:

• 524,288 bytes (8 bits each)

• 8 sectors (512Kb, 65KB each)

• 2048 pages (256 bytes each)

Figure 6: Block Diagram

HOLD#

W#

High Voltage

Generator

Control Logic

S#

C

DQ0

DQ1

I/O Shift Register

Status

Register

Address Register

and Counter

256 Byte

Data Buffer

7FFFFh

00000h

000FFh

256 bytes (page size)

X Decoder

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Micron M25P40 Serial Flash Embedded Memory

Memory Map – 4Mb Density

Table 4: Sectors[7:0]

Address Range

End

Sector

Start

7

6

5

4

3

2

1

0

0007 0000h

0006 0000h

0005 0000h

0004 0000h

0003 0000h

0002 0000h

0001 0000h

0000 0000h

0007 FFFFh

0006 FFFFh

0005 FFFFh

0004 FFFFh

0003 FFFFh

0002 FFFFh

0001 FFFFh

0000 FFFFh

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Micron M25P40 Serial Flash Embedded Memory

Command Set Overview

All commands, addresses, and data are shifted in and out of the device, most significant

bit first.

Serial data inputs DQ0 and DQ1 are sampled on the first rising edge of serial clock (C)

after chip select (S#) is driven LOW. Then, the one-byte command code must be shifted

in to the device, most significant bit first, on DQ0 and DQ1, each bit being latched on

the rising edges of C.

Every command sequence starts with a one-byte command code. Depending on the

command, this command code might be followed by address or data bytes, by address

and data bytes, or by neither address or data bytes. For the following commands, the

shifted-in command sequence is followed by a data-out sequence. S# can be driven

HIGH after any bit of the data-out sequence is being shifted out.

• READ DATA BYTES (READ)

• READ DATA BYTES at HIGHER SPEED

• READ STATUS REGISTER

• READ IDENTIFICATION

• RELEASE from DEEP POWER-DOWN

For the following commands, S# must be driven HIGH exactly at a byte boundary. That

is, after an exact multiple of eight clock pulses following S# being driven LOW, S# must

be driven HIGH. Otherwise, the command is rejected and not executed.

• PAGE PROGRAM

• SECTOR ERASE

• BULK ERASE

• WRITE STATUS REGISTER

• WRITE ENABLE

• WRITE DISABLE

All attempts to access the memory array are ignored during a WRITE STATUS REGISTER

command cycle, a PROGRAM command cycle, or an ERASE command cycle. In addi-

tion, the internal cycle for each of these commands continues unaffected.

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Micron M25P40 Serial Flash Embedded Memory

Command Set Overview

Table 5: Command Set Codes

Bytes

One-Byte

Command Name

Command Code

Address

Dummy

Data

WRITE ENABLE

0000

0110

06h

04h

9Fh

05h

01h

03h

0Bh

02h

D8h

C7h

B9h

ABh

0

WRITE DISABLE

0000

0100

0

3

0

1

0

1 to 20

1 to ∞

1

READ IDENTIFICATION

READ STATUS REGISTER

WRITE STATUS REGISTER

READ DATA BYTES

1001

1111

0000

0101

0000

0001

0000

0011

1 to ∞

1 to 256

0

READ DATA BYTES at HIGHER SPEED

PAGE PROGRAM

0000

1011

0000

0010

SECTOR ERASE

1101

1000

BULK ERASE

1100

0111

0

DEEP POWER-DOWN

RELEASE from DEEP POWER-DOWN

1011

1001

0

1010

1011

1 to ∞

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Micron M25P40 Serial Flash Embedded Memory

WRITE ENABLE

The WRITE ENABLE command sets the write enable latch (WEL) bit.

The WEL bit must be set before execution of every PROGRAM, ERASE, and WRITE com-

mand.

The WRITE ENABLE command is entered by driving chip select (S#) LOW, sending the

command code, and then driving S# HIGH.

Figure 7: WRITE ENABLE Command Sequence

0

1

2

3

4

5

6

7

C

S#

Command Bits

LSB

DQ[0]

DQ1

0

1

0

MSB

High-Z

Don’t Care

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Micron M25P40 Serial Flash Embedded Memory

WRITE DISABLE

The WRITE DISABLE command resets the write enable latch (WEL) bit.

The WRITE DISABLE command is entered by driving chip select (S#) LOW, sending the

command code, and then driving S# HIGH.

The WEL bit is reset under the following conditions:

• Power-up

• Completion of any ERASE operation

• Completion of any PROGRAM operation

• Completion of any WRITE REGISTER operation

• Completion of WRITE DISABLE operation

Figure 8: WRITE DISABLE Command Sequence

0

1

2

3

4

5

6

7

C

S#

Command Bits

LSB

DQ[0]

DQ1

0

1

0

MSB

High-Z

Don’t Care

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19

Micron M25P40 Serial Flash Embedded Memory

READ IDENTIFICATION

The READ IDENTIFICATION command reads the following device identification data:

• Manufacturer identification (1 byte): This is assigned by JEDEC.

• Device identification (2 bytes): This is assigned by device manufacturer; the first byte

indicates memory type and the second byte indicates device memory capacity.

• A Unique ID code (UID) (17 bytes,16 available upon customer request): The first byte

contains length of data to follow; the remaining 16 bytes contain optional Customized

Factory Data (CFD) content.

Table 6: READ IDENTIFICATION Data Out Sequence

Device Identification

UID

Manufacturer

Identification

Memory Type

Memory Capacity

CFD Length

CFD Content

20h

13h

10h

16 bytes

1. The CFD bytes are read-only and can be programmed with customer data upon demand.

If customers do not make requests, the devices are shipped with all the CFD bytes pro-

grammed to zero.

Note:

A READ IDENTIFICATION command is not decoded while an ERASE or PROGRAM cy-

cle is in progress and has no effect on a cycle in progress. The READ IDENTIFICATION

command must not be issued while the device is in DEEP POWER-DOWN mode.

The device is first selected by driving chip select (S#) LOW. Then the 8-bit command

code is shifted in and content is shifted out on serial data output (DQ1) as follows: the

24-bit device identification that is stored in the memory, the 8-bit CFD length, followed

by 16 bytes of CFD content. Each bit is shifted out during the falling edge of serial clock

(C).

The READ IDENTIFICATION command is terminated by driving S# HIGH at any time

during data output. When S# is driven HIGH, the device is put in the STANDBY POWER

mode and waits to be selected so that it can receive, decode, and execute commands.

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Micron M25P40 Serial Flash Embedded Memory

READ IDENTIFICATION

Figure 9: READ IDENTIFICATION Command Sequence

0

7

8

15

16

31

32

C

LSB

DQ0

Command

High-Z

MSB

LSB

D_OUT

MSB

D_OUT

MSB

D_OUT

MSB

D_OUT

DQ1

Manufacturer

identification

Device

identification

UID

Don’t Care

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Micron M25P40 Serial Flash Embedded Memory

READ STATUS REGISTER

The READ STATUS REGISTER command allows the status register to be read. The status

register may be read at any time, even while a PROGRAM, ERASE, or WRITE STATUS

REGISTER cycle is in progress. When one of these cycles is in progress, it is recommen-

ded to check the write in progress (WIP) bit before sending a new command to the de-

vice. It is also possible to read the status register continuously.

Figure 10: READ STATUS REGISTER Command Sequence

0

7

8

9

10

11

12

13

14

15

C

DQ0

DQ1

LSB

Command

High-Z

MSB

LSB

D_OUT

MSB

D_OUT

Don’t Care

Figure 11: Status Register Format

b7

b0

WIP

BP2

BP1

BP0

WEL

0

SRWD

status register write protect

block protect bits

write enable latch bit

write in progress bit

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Micron M25P40 Serial Flash Embedded Memory

READ STATUS REGISTER

WIP Bit

WEL Bit

The write in progress (WIP) bit indicates whether the memory is busy with a WRITE

STATUS REGISTER cycle, a PROGRAM cycle, or an ERASE cycle. When the WIP bit is set

to 1, a cycle is in progress; when the WIP bit is set to 0, a cycle is not in progress.

The write enable latch (WEL) bit indicates the status of the internal write enable latch.

When the WEL bit is set to 1, the internal write enable latch is set; when the WEL bit is

set to 0, the internal write enable latch is reset and no WRITE STATUS REGISTER, PRO-

GRAM, or ERASE command is accepted.

Block Protect Bits

The block protect bits are non-volatile. They define the size of the area to be software

protected against PROGRAM and ERASE commands. The block protect bits are written

with the WRITE STATUS REGISTER command.

When one or more of the block protect bits is set to 1, the relevant memory area, as de-

fined in the Protected Area Sizes table, becomes protected against PAGE PROGRAM and

SECTOR ERASE commands. The block protect bits can be written provided that the

HARDWARE PROTECTED mode has not been set. The BULK ERASE command is execu-

ted only if all block protect bits are 0.

SRWD Bit

The status register write disable (SRWD) bit is operated in conjunction with the write

protect (W#/V_PP) signal. When the SRWD bit is set to 1 and W#/V_PPis driven LOW, the

device is put in the hardware protected mode. In the hardware protected mode, the

non-volatile bits of the status register (SRWD, and the block protect bits) become read-

only bits and the WRITE STATUS REGISTER command is no longer accepted for execu-

tion.

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Micron M25P40 Serial Flash Embedded Memory

WRITE STATUS REGISTER

The WRITE STATUS REGISTER command allows new values to be written to the status

register. Before the WRITE STATUS REGISTER command can be accepted, a WRITE EN-

ABLE command must have been executed previously. After the WRITE ENABLE com-

mand has been decoded and executed, the device sets the write enable latch (WEL) bit.

The WRITE STATUS REGISTER command is entered by driving chip select (S#) LOW,

followed by the command code and the data byte on serial data input (DQ0). The

WRITE STATUS REGISTER command has no effect on b6, b5, b1 and b0 of the status

register. The status register b6 and b5 are always read as ‘0’. S# must be driven HIGH

after the eighth bit of the data byte has been latched in. If not, the WRITE STATUS REG-

ISTER command is not executed.

Figure 12: WRITE STATUS REGISTER Command Sequence

0

7

8

9

10

11

12

13

14

15

C

LSB

D

IN

DQ0

Command

IN

MSB

As soon as S# is driven HIGH, the self-timed WRITE STATUS REGISTER cycle is initi-

ated; its duration is t_W. While the WRITE STATUS REGISTER cycle is in progress, the sta-

tus register may still be read to check the value of the write in progress (WIP) bit. The

WIP bit is 1 during the self-timed WRITE STATUS REGISTER cycle, and is 0 when the

cycle is completed. Also, when the cycle is completed, the WEL bit is reset.

The WRITE STATUS REGISTER command allows the user to change the values of the

block protect bits (BP2, BP1, BP0). Setting these bit values defines the size of the area

that is to be treated as read-only, as defined in the Protected Area Sizes table.

The WRITE STATUS REGISTER command also allows the user to set and reset the status

register write disable (SRWD) bit in accordance with the write protect (W#/V_PP) signal.

The SRWD bit and the W#/V_PPsignal allow the device to be put in the HARDWARE PRO-

TECED (HPM) mode. The WRITE STATUS REGISTER command is not executed once

the HPM is entered. The options for enabling the status register protection modes are

summarized here.

Table 7: Status Register Protection Modes

Memory Content

W#/V_PP

Signal

SRWD

Bit

Protection

Mode (PM)

Status Register

Write Protection

Protected

Unprotected

Area

Notes

1, 2, 3

1

0

1

0

1

SOFTWARE

PROTECTED mode

(SPM)

Software protection

Commands not

accepted

Commands

accepted

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Micron M25P40 Serial Flash Embedded Memory

WRITE STATUS REGISTER

Table 7: Status Register Protection Modes (Continued)

Memory Content

W#/V_PP

Signal

SRWD

Bit

Protection

Mode (PM)

Status Register

Write Protection

Protected

Unprotected

Area

Notes

0

1

HARDWARE

PROTECTED mode

(HPM)

Hardware protection

Commands not

accepted

Commands

accepted

3, 4, 5,

1. Software protection: status register is writable (SRWD, BP2, BP1, and BP0 bit values can

be changed) if the WRITE ENABLE command has set the WEL bit.

Notes:

2. PAGE PROGRAM, SECTOR ERASE, AND BULK ERASE commands are not accepted.

3. PAGE PROGRAM and SECTOR ERASE commands can be accepted.

4. Hardware protection: status register is not writable (SRWD, BP2, BP1, and BP0 bit values

cannot be changed).

5. PAGE PROGRAM, SECTOR ERASE, AND BULK ERASE commands are not accepted.

When the SRWD bit of the status register is 0 (its initial delivery state), it is possible to

write to the status register provided that the WEL bit has been set previously by a WRITE

ENABLE command, regardless of whether the W#/V_PPsignal is driven HIGH or LOW.

When the status register SRWD bit is set to 1, two cases need to be considered depend-

ing on the state of the W#/V_PPsignal:

• If the W#/V_PPsignal is driven HIGH, it is possible to write to the status register provi-

ded that the WEL bit has been set previously by a WRITE ENABLE command.

• If the W#/V_PPsignal is driven LOW, it is not possible to write to the status register even

if the WEL bit has been set previously by a WRITE ENABLE command. Therefore, at-

tempts to write to the status register are rejected, and are not accepted for execution.

The result is that all the data bytes in the memory area that have been put in SPM by

the status register block protect bits (BP2, BP1, BP0) are also hardware protected

against data modification.

Regardless of the order of the two events, the HPM can be entered in either of the fol-

lowing ways:

• Setting the status register SRWD bit after driving the W#/V_PPsignal LOW

• Driving the W#/V_PPsignal LOW after setting the status register SRWD bit.

The only way to exit the HPM is to pull the W#/V_PPsignal HIGH. If the W#/V_PPsignal is

permanently tied HIGH, the HPM can never be activated. In this case, only the SPM is

available, using the status register block protect bits (BP2, BP1, BP0).

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Micron M25P40 Serial Flash Embedded Memory

READ DATA BYTES

The device is first selected by driving chip select (S#) LOW. The command code for

READ DATA BYTES is followed by a 3-byte address (A23-A0), each bit being latched-in

during the rising edge of serial clock (C). Then the memory contents at that address is

shifted out on serial data output (DQ1), each bit being shifted out at a maximum fre-

quency f_Rduring the falling edge of C.

The first byte addressed can be at any location. The address is automatically incremen-

ted to the next higher address after each byte of data is shifted out. Therefore, the entire

memory can be read with a single READ DATA BYTES command. When the highest ad-

dress is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The READ DATA BYTES command is terminated by driving S# HIGH. S# can be driven

HIGH at any time during data output. Any READ DATA BYTES command issued while

an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on

the cycle that is in progress.

Figure 13: READ DATA BYTES Command Sequence

0

7

8

C_x

C

LSB

A[MIN]

DQ[0]

DQ1

Command

High-Z

MSB

A[MAX]

LSB

D_OUTD_OUT

D_OUT

MSB

D_OUT

Don’t Care

1. Cx = 7 + (A[MAX] + 1).

Note:

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Micron M25P40 Serial Flash Embedded Memory

READ DATA BYTES at HIGHER SPEED

The device is first selected by driving chip select (S#) LOW. The command code for the

READ DATA BYTES at HIGHER SPEED command is followed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of serial clock

(C). Then the memory contents at that address are shifted out on serial data output

(DQ1) at a maximum frequency f_C, during the falling edge of C.

The first byte addressed can be at any location. The address is automatically incremen-

ted to the next higher address after each byte of data is shifted out. Therefore, the entire

memory can be read with a single READ DATA BYTES at HIGHER SPEED command.

When the highest address is reached, the address counter rolls over to 000000h, allow-

ing the read sequence to be continued indefinitely.

The READ DATA BYTES at HIGHER SPEED command is terminated by driving S# HIGH.

S# can be driven HIGH at any time during data output. Any READ DATA BYTES at

HIGHER SPEED command issued while an ERASE, PROGRAM, or WRITE cycle is in

progress is rejected without any effect on the cycle that is in progress.

Figure 14: READ DATA BYTES at HIGHER SPEED Command Sequence

0

7

8

C

x

C

LSB

A[MIN]

DQ0

Command

MSB

A[MAX]

LSB

D

OUT

DQ1

High-Z

OUT

MSB

Dummy cycles

Don’t Care

1. Cx = 7 + (A[MAX] + 1).

Note:

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Micron M25P40 Serial Flash Embedded Memory

PAGE PROGRAM

The PAGE PROGRAM command allows bytes in the memory to be programmed, which

means the bits are changed from 1 to 0. Before a PAGE PROGRAM command can be ac-

cepted a WRITE ENABLE command must be executed. After the WRITE ENABLE com-

mand has been decoded, the device sets the write enable latch (WEL) bit.

The PAGE PROGRAM command is entered by driving chip select (S#) LOW, followed by

the command code, three address bytes, and at least one data byte on serial data input

(DQ0).

If the eight least significant address bits (A7-A0) are not all zero, all transmitted data that

goes beyond the end of the current page are programmed from the start address of the

same page; that is, from the address whose eight least significant bits (A7-A0) are all

zero. S# must be driven LOW for the entire duration of the sequence.

If more than 256 bytes are sent to the device, previously latched data are discarded and

the last 256 data bytes are guaranteed to be programmed correctly within the same

page. If less than 256 data bytes are sent to device, they are correctly programmed at the

requested addresses without any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the PAGE PROGRAM command to

program all consecutive targeted bytes in a single sequence rather than to use several

PAGE PROGRAM sequences, each containing only a few bytes.

S# must be driven HIGH after the eighth bit of the last data byte has been latched in.

Otherwise the PAGE PROGRAM command is not executed.

As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cy-

cles's duration is t_PP. While the PAGE PROGRAM cycle is in progress, the status register

may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during

the self-timed PAGE PROGRAM cycle, and 0 when the cycle is completed. At some un-

specified time before the cycle is completed, the write enable latch (WEL) bit is reset.

A PAGE PROGRAM command is not executed if it applies to a page protected by the

block protect bits BP2, BP1, and BP0.

Figure 15: PAGE PROGRAM Command Sequence

0

7

8

C

x

C

LSB

A[MIN]

LSB

D

IN

DQ[0]

Command

IN

MSB

A[MAX]

MSB

1. Cx = 7 + (A[MAX] + 1).

Note:

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Micron M25P40 Serial Flash Embedded Memory

SECTOR ERASE

The SECTOR ERASE command sets to 1 (FFh) all bits inside the chosen sector. Before

the SECTOR ERASE command can be accepted, a WRITE ENABLE command must have

been executed previously. After the WRITE ENABLE command has been decoded, the

device sets the write enable latch (WEL) bit.

The SECTOR ERASE command is entered by driving chip select (S#) LOW, followed by

the command code, and three address bytes on serial data input (DQ0). Any address in-

side the sector is a valid address for the SECTOR ERASE command. S# must be driven

LOW for the entire duration of the sequence.

S# must be driven HIGH after the eighth bit of the last address byte has been latched in.

Otherwise the SECTOR ERASE command is not executed. As soon as S# is driven HIGH,

the self-timed SECTOR ERASE cycle is initiated; the cycle's duration is t_SE. While the

SECTOR ERASE cycle is in progress, the status register may be read to check the value of

the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SECTOR ERASE

cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is

completed, the WEL bit is reset.

A SECTOR ERASE command is not executed if it applies to a sector that is hardware or

software protected.

Figure 16: SECTOR ERASE Command Sequence

0

7

8

C

x

C

LSB

A[MIN]

DQ0

Command

MSB

A[MAX]

1. Cx = 7 + (A[MAX] + 1).

Note:

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Micron M25P40 Serial Flash Embedded Memory

BULK ERASE

The BULK ERASE command sets all bits to 1 (FFh). Before the BULK ERASE command

can be accepted, a WRITE ENABLE command must have been executed previously. Af-

ter the WRITE ENABLE command has been decoded, the device sets the write enable

latch (WEL) bit.

The BULK ERASE command is entered by driving chip select (S#) LOW, followed by the

command code on serial data input (DQ0). S# must be driven LOW for the entire dura-

tion of the sequence.

S# must be driven HIGH after the eighth bit of the command code has been latched in.

Otherwise the BULK ERASE command is not executed. As soon as S# is driven HIGH,

the self-timed BULK ERASE cycle is initiated; the cycle's duration is t_BE. While the BULK

ERASE cycle is in progress, the status register may be read to check the value of the write

In progress (WIP) bit. The WIP bit is 1 during the self-timed BULK ERASE cycle, and is 0

when the cycle is completed. At some unspecified time before the cycle is completed,

the WEL bit is reset.

The BULK ERASE command is executed only if all block protect (BP2, BP1, BP0) bits are

0. The BULK ERASE command is ignored if one or more sectors are protected.

Figure 17: BULK ERASE Command Sequence

0

7

C

LSB

DQ0

MSB

Command

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Micron M25P40 Serial Flash Embedded Memory

DEEP POWER-DOWN

Executing the DEEP POWER-DOWN command is the only way to put the device in the

lowest power consumption mode, the DEEP POWER-DOWN mode. The DEEP POWER-

DOWN command can also be used as a software protection mechanism while the de-

vice is not in active use because in the DEEP POWER-DOWN mode the device ignores

all WRITE, PROGRAM, and ERASE commands.

Driving chip select (S#) HIGH deselects the device, and puts it in the STANDBY POWER

mode if there is no internal cycle currently in progress. Once in STANDBY POWER

mode, the DEEP POWER-DOWN mode can be entered by executing the DEEP POWER-

DOWN command, subsequently reducing the standby current from I_CC1to I_CC2

.

To take the device out of DEEP POWER-DOWN mode, the RELEASE from DEEP POW-

ER-DOWN command must be issued. Other commands must not be issued while the

device is in DEEP POWER-DOWN mode. The DEEP POWER-DOWN mode stops auto-

matically at power-down. The device always powers up in STANDBY POWER mode.

The DEEP POWER-DOWN command is entered by driving S# LOW, followed by the

command code on serial data input (DQ0). S# must be driven LOW for the entire dura-

tion of the sequence.

S# must be driven HIGH after the eighth bit of the command code has been latched in.

Otherwise the DEEP POWER-DOWN command is not executed. As soon as S# is driven

HIGH, it requires a delay of t_DPbefore the supply current is reduced to I_CC2and the

DEEP POWER-DOWN mode is entered.

Any DEEP POWER-DOWN command issued while an ERASE, PROGRAM, or WRITE cy-

cle is in progress is rejected without any effect on the cycle that is in progress.

Figure 18: DEEP POWER-DOWN Command Sequence

0

7

C

^tDP

LSB

DQ0

Command

MSB

Standby Mode

Deep Power-Down Mode

Don’t Care

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Micron M25P40 Serial Flash Embedded Memory

RELEASE from DEEP POWER-DOWN

Once the device has entered DEEP POWER-DOWN mode, all commands are ignored ex-

cept RELEASE from DEEP POWER-DOWN and READ ELECTRONIC SIGNATURE. Exe-

cuting either of these commands takes the device out of the DEEP POWER-DOWN

mode.

The RELEASE from DEEP POWER-DOWN command is entered by driving chip select

(S#) LOW, followed by the command code on serial data input (DQ0). S# must be driven

LOW for the entire duration of the sequence.

The RELEASE from DEEP POWER-DOWN command is terminated by driving S# HIGH.

Sending additional clock cycles on serial clock C while S# is driven LOW causes the

command to be rejected and not executed.

After S# has been driven HIGH, followed by a delay, t_RES, the device is put in the STAND-

BY mode. S# must remain HIGH at least until this period is over. The device waits to be

selected so that it can receive, decode, and execute commands.

Any RELEASE from DEEP POWER-DOWN command issued while an ERASE, PRO-

GRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in

progress.

Figure 19: RELEASE from DEEP POWER-DOWN Command Sequence

0

7

C

DQ0

DQ1

^tRDP

LSB

Command

High-Z

MSB

Deep Power-Down Mode

Standby Mode

Don’t Care

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Micron M25P40 Serial Flash Embedded Memory

READ ELECTRONIC SIGNATURE

Once the device enters DEEP POWER-DOWN mode, all commands are ignored except

READ ELECTRONIC SIGNATURE and RELEASE from DEEP POWER-DOWN. Executing

either of these commands takes the device out of the DEEP POWER-DOWN mode.

The READ ELECTRONIC SIGNATURE command is entered by driving chip select (S#)

LOW, followed by the command code and three dummy bytes on serial data input

(DQ0) . Each bit is latched in on the rising edge of serial clock C. The 8-bit electronic

signature is shifted out on serial data output DQ1 on the falling edge of C; S# must be

driven LOW the entire duration of the sequence for the electronic signature to be read.

However, driving S# HIGH after the command code, but before the entire 8-bit electron-

ic signature has been output for the first time, still ensures that the device is put into

STANDBY mode.

Except while an ERASE, PROGRAM, or WRITE STATUS REGISTER cycle is in progress,

the READ ELECTRONIC SIGNATURE command provides access to the 8-bit electronic

signature of the device, and can be applied even if DEEP POWER-DOWN mode has not

been entered. The READ ELECTRONIC SIGNATURE command is not executed while an

ERASE, PROGRAM, or WRITE STATUS REGISTER cycle is in progress and has no effect

on the cycle in progress.

The READ ELECTRONIC SIGNATURE command is terminated by driving S# high after

the electronic signature has been read at least once. Sending additional clock cycles C

while S# is driven LOW causes the electronic signature to be output repeatedly.

If S# is driven HIGH, the device is put in STANDBY mode immediately unless it was pre-

viously in DEEP POWER-DOWN mode. If previously in DEEP POWER-DOWN mode, the

device transitions to STANDBY mode with delay as described here. Once in STANDBY

mode, the device waits to be selected so that it can receive, decode, and execute instruc-

tions.

• If S# is driven HIGH before the electronic signature is read, transition to STANDBY

mode is delayed by tRES1, as shown in the RELEASE from DEEP POWER-DOWN com-

mand sequence. S# must remain HIGH for at least tRES1(max).

• If S# is driven HIGH after the electronic signature is read, transition to STANDBY

mode is delayed by tRES2. S# must remain HIGH for at least tRES2(max).

Figure 20: READ ELECTRONIC SIGNATURE Command Sequence

0

7

8

C

x

C

^tRES2

LSB

DQ0

Command

High-Z

MSB

Electronic Signature

LSB

D

DQ1

OUT

MSB

Dummy cycles

Deep Power-Down

Standby

Don’t Care

1. Cx = 7 + (A[MAX] + 1).

Note:

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Micron M25P40 Serial Flash Embedded Memory

Power-Up/Down and Supply Line Decoupling

At power-up and power-down, the device must not be selected; that is, chip select (S#)

must follow the voltage applied on V_CCuntil V_CCreaches the correct value:

• V_CC,minat power-up, and then for a further delay of t_VSL

• V_SSat power-down

A safe configuration is provided in the SPI Modes section.

To avoid data corruption and inadvertent write operations during power-up, a power-

on-reset (POR) circuit is included. The logic inside the device is held reset while V_CCis

less than the POR threshold voltage, V_WI– all operations are disabled, and the device

does not respond to any instruction. Moreover, the device ignores the following instruc-

tions until a time delay of ^tPUW has elapsed after the moment that V_CCrises above the

V_WIthreshold:

• WRITE ENABLE

• PAGE PROGRAM

• SECTOR ERASE

• BULK ERASE

• WRITE STATUS REGISTER

However, the correct operation of the device is not guaranteed if, by this time, V_CCis still

below V_CC.min. No WRITE STATUS REGISTER, PROGRAM, or ERASE instruction should

be sent until:

t

• PUW after V_CChas passed the V_WIthreshold

t

• VSL after V_CChas passed the V_CC,minlevel

If the time, ^tVSL, has elapsed, after V_CCrises above V_CC,min, the device can be selected

for READ instructions even if the ^tPUW delay has not yet fully elapsed.

V_PPHmust be applied only when V_CCis stable and in the V_CC,minto V_CC,maxvoltage

range.

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Micron M25P40 Serial Flash Embedded Memory

Power-Up/Down and Supply Line Decoupling

Figure 21: Power-Up Timing

V

CC

V

CC,max

PROGRAM, ERASE, and WRITE commands are rejected by the device

Chip selection not allowed

V

CC,min

^tVSL

READ access allowed

Device fully

accessible

RESET state

of the

device

V

WI

^tPUW

Time

After power-up, the device is in the following state:

• Standby power mode (not the deep power-down mode)

• Write enable latch (WEL) bit is reset

• Write in progress (WIP) bit is reset

• Write lock bit = 0

• Lock down bit = 0

Normal precautions must be taken for supply line decoupling to stabilize the V_CCsup-

ply. Each device in a system should have the V_CCline decoupled by a suitable capacitor

close to the package pins; generally, this capacitor is of the order of 100 nF.

At power-down, when V_CCdrops from the operating voltage to below the POR threshold

voltage V_WI, all operations are disabled and the device does not respond to any instruc-

tion.

Note:If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress,

some data corruption may result.

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Micron M25P40 Serial Flash Embedded Memory

Power-Up Timing and Write Inhibit Voltage Specifications

Table 8: Power-Up Timing and V_WIThreshold

Symbol

t_VSL

Parameter

V_CC(min) to S# LOW

Min

10

Max

–

Unit

μs

t_PUW

V_WI

Time delay to write instruction

1.0

10

ms

V

Write Inhibit voltage (device grade 3)

Write Inhibit voltage (device grade 6)

2.1

V_WI

V

1. Parameters are characterized only.

Note:

If the time, t_VSL, has elapsed, after V_CCrises above V_CC(min), the device can be selected

for READ instructions even if the t_PUWdelay has not yet fully elapsed.

V_PPHmust be applied only when V_CCis stable and in the V_CCmin to V_CCmax voltage

range.

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Micron M25P40 Serial Flash Embedded Memory

Maximum Ratings and Operating Conditions

Caution: Stressing the device beyond the absolute maximum ratings may cause perma-

nent damage to the device. These are stress ratings only and operation of the device be-

yond any specification or condition in the operating sections of this data sheet is not

recommended. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

Table 9: Absolute Maximum Ratings

Symbol

T_STG

Parameter

Min

–65

—

Max

150

Units

°C

Notes

Storage temperature

Lead temperature during soldering

T_LEAD

V_IO

See note

V_CC+0.6

°C

1

2

Input and output voltage (with respect to

ground)

–0.6

V

V_CC

Supply voltage

–0.6

4.0

V

V_ESD

Electrostatic discharge voltage (human body

model)

–2000

2000

3

1. The T_LEADsignal is compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb as-

sembly), the Micron RoHS-compliant 7191395 specification, and the European directive

on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

Notes:

2. The minimum voltage may reach the value of –2V for no more than 20ns during transi-

tions; the maximum may reach the value of V_CC+2V for no more than 20ns during tran-

sitions.

3. The V_ESDsignal: JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

Table 10: Operating Conditions

Symbol

V_CC

Parameter

Min

2.3

Max

3.6

Unit

V

Supply voltage

T_A

Ambient operating temperature (grade 6)

Ambient operating temperature (grade 3)

–40

85

°C

T_A

125

°C

Table 11: Data Retention and Endurance

Parameter

Program/erase cycles Grade 6, Grade 3

Data retention at 55°C

Condition

Min

100,000

20

Max

Unit

–

Cycles per unit

Years

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Micron M25P40 Serial Flash Embedded Memory

Electrical Characteristics

Table 12: DC Current Specifications (Device Grade 6)

Symbol Parameter

Test Conditions

Min

Max

±2

50

10

8

Units

µA

I_LI

Input leakage current

–

I_LO

Output leakage current

Standby current

–

µA

I_CC1

I_CC2

I_CC3

S# = V_CC, V_IN= V_SSor V_CC

µA

Deep power-down current

Operating current (READ)

µA

C = 0.1V_CC/ 0.9V_CCat 40 MHz, 50 MHz,

and 75 MHz, DQ1 = open

mA

C = 0.1V_CC/ 0.9V_CCat 25 MHz and 33

MHz, DQ1 = open

–

4

mA

I_CC4

I_CC5

I_CC6

I_CC7

Operating current

(PAGE PROGRAM)

S# = V_CC

15

Operating current

(WRITE STATUS REGISTER)

Operating current

(SECTOR ERASE)

Operating current

(BULK ERASE)

Table 13: DC Voltage Specifications (Device Grade 6)

Symbol Parameter

Test Conditions

Min

Max

Units

V_IL

V_IH

Input LOW voltage

–

–0.5

0.3V_CC

V

Input HIGH voltage

Output LOW voltage

Output HIGH voltage

–

0.7V_CCV_CC+0.4

V_OL

V_OH

I_OL= 1.6mA

I_OH= –100µA

–

0.4

–

V_CC–0.2

Table 14: DC Current Specifications (Device Grade 3)

Symbol Parameter

Test Conditions

Min

Max

±2

Units

µA

I_LI

Input leakage current

–

I_LO

Output leakage current

Standby current

–

±2

µA

I_CC1

I_CC2

I_CC3

S# = V_CC, V_IN= V_SSor V_CC

100

50

µA

Deep power-down current

Operating current (READ)

µA

C = 0.1V_CC/ 0.9V_CCat 40 MHz, 50 MHz,

and 75 MHz, DQ1 = open

8

mA

C = 0.1V_CC/ 0.9V_CCat 25 MHz and 33

MHz, DQ1 = open

–

4

mA

I_CC4

Operating current

(PAGE PROGRAM)

S# = V_CC

15

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Micron M25P40 Serial Flash Embedded Memory

Electrical Characteristics

Table 14: DC Current Specifications (Device Grade 3) (Continued)

Symbol Parameter

Test Conditions

Min

Max

Units

I_CC5

I_CC6

I_CC7

Operating current

(WRITE STATUS REGISTER)

S# = V_CC

–

15

mA

Operating current

(SECTOR ERASE)

S# = V_CC

–

15

mA

Operating current

(BULK ERASE)

Table 15: DC Voltage Specifications (Device Grade 3)

Symbol Parameter

Test Conditions

Min

Max

Units

V_IL

V_IH

Input LOW voltage

–

–0.5

0.3V_CC

V

Input HIGH voltage

Output LOW voltage

Output HIGH voltage

–

0.7V_CCV_CC+0.4

V_OL

V_OH

I_OL= 1.6mA

I_OH= –100µA

–

0.4

–

V_CC–0.2

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Micron M25P40 Serial Flash Embedded Memory

AC Characteristics

In the following AC specifications, output HIGH-Z is defined as the point where data

out is no longer driven; however, this is not applicable to the M25PX64 device.

Table 16: Device Grade and AC Table Correlation

150nm

f[min]

110nm

f[min]

75MHz

Device Grade

V_CC[min]

AC Table

V_CC[min]

AC Table

Grade 3

2.7V

25MHz

40MHz

50MHz

Table 21

(page 41)

2.7V

Table 24

(page 45)

Grade 6

2.3V

2.7V

Table 23

(page 43)

2.3V

2.7V

40MHz

75MHz

Table 23

(page 43)

Table 22

Table 24

(page 42)

(page 45)

Table 17: AC Measurement Conditions

Symbol

Parameter

Min

30

Max

30

Unit

pF

ns

V

C_L

Load capacitance

Input rise and fall times

Input pulse voltages

–

5

0.2V_CC

0.3V_CC

V_CC/ 2

0.8V_CC

0.7V_CC

V_CC/ 2

Input timing reference voltages

Output timing reference voltages

V

Figure 22: AC Measurement I/O Waveform

Input levels

0.8V_CC

Input and output

timing reference levels

0.7V_CC

0.5V_CC

0.3V_CC

0.2V_CC

Table 18: Capacitance

Symbol Parameter

Test condition

V_OUT= 0 V

Min

Max

Unit

pF

Notes

C_OUT

C_IN

Output capacitance (DQ1)

–

8

6

1

Input capacitance (other pins)

V_IN= 0 V

pF

1. Values are sampled only, not 100% tested, at T_A=25°C and a frequency of 25MHz.

Note:

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Micron M25P40 Serial Flash Embedded Memory

AC Characteristics

Table 19: Instruction Times, Process Technology 110nm

Symbol Parameter

Min

Typ

1.3

0.8

Max

15

Units

ms

Notes

t_W

t_PP

WRITE STATUS REGISTER cycle time

–

PAGE PROGRAM cycle time (256 bytes)

5

ms

2

PAGE PROGRAM cycle time (n bytes)

int (n/8) x

0.025

t_SE

t_BE

SECTOR ERASE cycle time

BULK ERASE cycle time

–

0.6

4.5

3

s

10

1. Applies to the entire table: 110nm technology devices are identified by the process iden-

Notes:

tification digit 4 in the device marking and the process letter B in the part number.

2. When using the PAGE PROGRAM command to program consecutive bytes, optimized

timings are obtained in one sequence that includes all the bytes rather than in several

sequences of only a few bytes (1 < n < 256).

Table 20: Instruction Times, Process Technology 150nm

Symbol Parameter

Min

Typ

Max

15

Units

ms

Notes

t_W

t_PP

t_SE

t_BE

WRITE STATUS REGISTER cycle time

–

5

1.4

PAGE PROGRAM cycle time (256 bytes)

PAGE PROGRAM cycle time (n bytes)

SECTOR ERASE cycle time

5

ms

2

0.4+n*1/256

1.0

3

s

BULK ERASE cycle time

4.5

10

1. Applies to the entire table: 150nm technology devices are identified by the process iden-

Notes:

tification digit 4 in the device marking and the process letter B in the part number.

2. When using the PAGE PROGRAM command to program consecutive bytes, optimized

timings are obtained in one sequence that includes all the bytes rather than in several

sequences of only a few bytes (1 < n < 256).

Table 21: AC Specifications (25 MHz, Device Grade 3, V_CC[min]=2.7V)

Symbol

f_C

Alt.

f_C

Parameter

Clock frequency for commands (See note)

Clock frequency for READ command

Min

D.C.

18

Typ

–

Max

Unit

MHz

ns

Notes

25

20

–

1

f_R

–

t_CH

t_CLHClock HIGH time

t_CLLClock LOW time

–

2

t_CL

18

–

ns

2

t_CLCH

t_CHCL

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

–

Clock rise time (peak to peak)

Clock fall time (peak to peak)

0.1

10

–

V/ns

ns

3, 4

–

t_CSSS# active setup time (relative to C)

S# not active hold time (relative to C)

t_DSUData in setup time

–

—

10

–

ns

5

–

ns

t_DH

–

Data in hold time

5

–

ns

S# active hold time (relative to C)

S# not active setup time (relative to C)

10

–

ns

–

10

–

ns

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Micron M25P40 Serial Flash Embedded Memory

AC Characteristics

Table 21: AC Specifications (25 MHz, Device Grade 3, V_CC[min]=2.7V) (Continued)

Symbol

t_SHSL

Alt.

Parameter

Min

100

–

Typ

–

Max

–

Unit

ns

μs

Notes

t_CSHS# deselect time

t_SHQZ

t_CLQV

t_CLQX

t_HLCH

t_CHHH

t_HHCH

t_CHHL

t_HHQX

t_HLQZ

t_WHSL

t_SHWL

t_DP

t_DIS

t_V

t_HO

–

Output disable time

–

15

–

3

Clock LOW to output valid

–

Output hold time

0

–

HOLD# setup time (relative to C)

HOLD# hold time (relative to C)

HOLD# setup time (relative to C)

HOLD# hold time (relative to C)

HOLD# to output LOW-Z

10

–

t_LZ

t_HZ

–

15

20

–

3

5

3

HOLD# to output HIGH-Z

–

WRITE PROTECT setup time

20

100

–

WRITE PROTECT hold time

–

S# HIGH to DEEP POWER-DOWN mode

S# HIGH to STANDBY without electronic signature read

S# HIGH to STANDBY with electronic signature read

–

3

t_RES1

–

30

μs

t_RES2

–

μs

1. READ DATA BYTES at HIGHER SPEED, PAGE PROGRAM, SECTOR ERASE, BLOCK ERASE,

DEEP POWER-DOWN, READ ELECTRONIC SIGNATURE, WRITE ENABLE/DISABLE, READ ID,

READ/WRITE STATUS REGISTER

Notes:

2. The t_CHand t_CLsignals must be greater than or equal to 1/f_C.

3. The t_CLCH, t_CHCL, t_SHQZ, t_HHQX, t_HLQZ, t_DP, t_RES1, and t_RES2signal values are guaranteed by

characterization, not 100% tested in production.

4. The t_CLCHand t_CHCLsignals clock rise and fall time values are expressed as a slew-rate.

5. The t_WHSLand t_SHWLsignals are only applicable as a constraint for a WRITE STATUS REGIS-

TER command when SRWD bit is set at 1.

Table 22: AC Specifications (50 MHz, Device Grade 6, V_CC[min]=2.7V)

Symbol

f_C

Alt.

f_C

Parameter

Clock frequency for commands (See note)

Clock frequency for READ command

Min

D.C.

9

Typ

–

Max

Unit

MHz

ns

Notes

50

25

–

1

f_R

–

t_CH

t_CLHClock HIGH time

t_CLLClock LOW time

–

2

t_CL

9

–

ns

2

t_CLCH

t_CHCL

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

–

Clock rise time (peak to peak)

Clock fall time (peak to peak)

0.1

5

–

V/ns

ns

3, 4

–

t_CSSS# active setup time (relative to C)

S# not active hold time (relative to C)

t_DSUData in setup time

–

—

5

–

ns

2

–

ns

t_DH

–

Data in hold time

5

–

ns

S# active hold time (relative to C)

S# not active setup time (relative to C)

5

–

ns

–

5

–

ns

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Micron M25P40 Serial Flash Embedded Memory

AC Characteristics

Table 22: AC Specifications (50 MHz, Device Grade 6, V_CC[min]=2.7V) (Continued)

Symbol

t_SHSL

Alt.

Parameter

Min

100

–

Typ

–

Max

–

Unit

ns

μs

Notes

t_CSHS# deselect time

t_SHQZ

t_CLQV

t_CLQX

t_HLCH

t_CHHH

t_HHCH

t_CHHL

t_HHQX

t_HLQZ

t_WHSL

t_SHWL

t_DP

t_DIS

t_V

t_HO

–

Output disable time

–

8

3

Clock LOW to output valid

–

8

Output hold time

0

–

HOLD# setup time (relative to C)

HOLD# hold time (relative to C)

HOLD# setup time (relative to C)

HOLD# hold time (relative to C)

HOLD# to output LOW-Z

5

–

5

–

5

–

5

–

t_LZ

t_HZ

–

8

3

5

3

HOLD# to output HIGH-Z

–

8

WRITE PROTECT setup time

20

100

–

WRITE PROTECT hold time

–

S# HIGH to DEEP POWER-DOWN mode

S# HIGH to STANDBY without electronic signature read

S# HIGH to STANDBY with electronic signature read

–

3

t_RES1

–

30

μs

t_RES2

–

μs

1. READ DATA BYTES at HIGHER SPEED, PAGE PROGRAM, SECTOR ERASE, BLOCK ERASE,

DEEP POWER-DOWN, READ ELECTRONIC SIGNATURE, WRITE ENABLE/DISABLE, READ ID,

READ/WRITE STATUS REGISTER

Notes:

2. The t_CHand t_CLsignals must be greater than or equal to 1/f_C.

3. The t_CLCH, t_CHCL, t_SHQZ, t_HHQX, t_HLQZ, t_DP, t_RES1, and t_RES2signal values are guaranteed by

characterization, not 100% tested in production.

4. The t_CLCHand t_CHCLsignals clock rise and fall time values are expressed as a slew-rate.

5. The t_WHSLand t_SHWLsignals are only applicable as a constraint for a WRITE STATUS REGIS-

TER command when SRWD bit is set at 1.

Table 23: AC Specifications (40 MHz, Device Grade 6, V_CC[min]=2.3V)

Symbol

f_C

Alt.

f_C

Parameter

Clock frequency for commands (See note)

Clock frequency for READ command

Min

D.C.

11

0.1

5

Typ

–

Max

Unit

MHz

ns

Notes

40

25

–

2

f_R

–

t_CH

t_CLHClock HIGH time

t_CLLClock LOW time

–

3

t_CL

–

ns

3

t_CLCH

t_CHCL

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

–

Clock rise time (peak to peak)

Clock fall time (peak to peak)

–

V/ns

ns

4, 5

–

t_CSSS# active setup time (relative to C)

S# not active hold time (relative to C)

t_DSUData in setup time

–

—

5

–

ns

2

–

ns

t_DH

–

Data in hold time

5

–

ns

S# active hold time (relative to C)

S# not active setup time (relative to C)

5

–

ns

–

5

–

ns

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Micron M25P40 Serial Flash Embedded Memory

AC Characteristics

Table 23: AC Specifications (40 MHz, Device Grade 6, V_CC[min]=2.3V) (Continued)

Symbol

t_SHSL

Alt.

Parameter

Min

100

–

Typ

–

Max

–

Unit

ns

μs

Notes

t_CSHS# deselect time

t_SHQZ

t_CLQV

t_CLQX

t_HLCH

t_CHHH

t_HHCH

t_CHHL

t_HHQX

t_HLQZ

t_WHSL

t_SHWL

t_DP

t_DIS

t_V

t_HO

–

Output disable time

–

8

4

Clock LOW to output valid

–

8

Output hold time

0

–

HOLD# setup time (relative to C)

HOLD# hold time (relative to C)

HOLD# setup time (relative to C)

HOLD# hold time (relative to C)

HOLD# to output LOW-Z

5

–

5

–

5

–

5

–

t_LZ

t_HZ

–

8

4

6

4

HOLD# to output HIGH-Z

–

8

WRITE PROTECT setup time

20

100

–

WRITE PROTECT hold time

–

S# HIGH to DEEP POWER-DOWN mode

S# HIGH to STANDBY without electronic signature read

S# HIGH to STANDBY with electronic signature read

–

3

t_RES1

–

30

μs

t_RES2

–

μs

1. Applies to entire table: Maximum frequency in the VCC range 2.3V to 2.7V is 40MHz.

Notes:

2. READ DATA BYTES at HIGHER SPEED, PAGE PROGRAM, SECTOR ERASE, BLOCK ERASE,

DEEP POWER-DOWN, READ ELECTRONIC SIGNATURE, WRITE ENABLE/DISABLE, READ ID,

READ/WRITE STATUS REGISTER

3. The t_CHand t_CLsignals must be greater than or equal to 1/f_C.

4. The t_CLCH, t_CHCL, t_SHQZ, t_HHQX, t_HLQZ, t_DP, t_RES1, and t_RES2signal values are guaranteed by

characterization, not 100% tested in production.

5. The t_CLCHand t_CHCLsignals clock rise and fall time values are expressed as a slew-rate.

6. The t_WHSLand t_SHWLsignals are only applicable as a constraint for a WRITE STATUS REGIS-

TER command when SRWD bit is set at 1.

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Micron M25P40 Serial Flash Embedded Memory

AC Characteristics

Table 24: AC Specifications (75MHz, Device Grade 3 and 6, V_CC[min]=2.7V)

Symbol

f_C

Alt.

f_C

Parameter

Min

D.C.

6

Typ

–

Max

75

33

–

Unit

MHz

ns

Notes

Clock frequency for all commands (except READ)

Clock frequency for READ command

f_R

–

t_CH

t_CLHClock HIGH time

t_CLLClock LOW time

3

t_CL

6

–

ns

3, 4

5, 6

t_CLCH

t_CHCL

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

t_SHSL

t_SHQZ

t_CLQV

–

Clock rise time (peak to peak)

Clock fall time (peak to peak)

0.1

5

–

V/ns

ns

–

t_CSSS# active setup time (relative to C)

S# not active hold time (relative to C)

t_DSUData In setup time

–

5

–

ns

2

–

ns

t_DH

–

Data In hold time

5

–

ns

S# active hold time (relative to C)

S# not active setup time (relative to C)

5

–

ns

–

5

–

ns

t_CSHS# deselect time

100

–

ns

t_DIS

t_V

Output disable time

8

ns

5

Clock LOW to output valid under 30 pF

Clock LOW to output valid under 10 pF

Output hold time

–

8

ns

–

6

ns

t_CLQX

t_HLCH

t_CHHH

t_HHCH

t_CHHL

t_HHQX

t_HLQZ

t_WHSL

t_SHWL

t_DP

t_HO

–

0

–

ns

HOLD# setup time (relative to C)

HOLD# hold time (relative to C)

HOLD# setup time (relative to C)

HOLD# hold time (relative to C)

HOLD# to output LOW-Z

5

–

ns

–

5

–

ns

–

5

–

ns

–

5

–

ns

t_LZ

t_HZ

–

8

ns

5

7

5

HOLD# to output HIGH-Z

–

8

ns

WRITE PROTECT setup time

WRITE PROTECT hold time

20

100

–

ns

–

ns

–

S# HIGH to DEEP POWER-DOWN mode

3

μs

t_RES1

–

S# HIGH to STANDBY without READ ELECTRONIC SIGNA-

TURE

–

30

μs

t_RES2

–

S# HIGH to STANDBY with READ ELECTRONIC SIGNATURE

–

30

μs

5

1. Applies to entire table: 110nm technology devices are identified by the process identifi-

Notes:

cation digit 4 in the device marking and the process letter B in the part number.

2. Applies to entire table: the AC specification values shown here are allowed only on the

VCC range 2.7V to 3.6V. Maximum frequency in the VCC range 2.3V to 2.7V is 40MHz.

3. The t_CHand t_CLsignal values must be greater than or equal to 1/f_C.

4. Typical values are given for T_A= 25°C.

5. The t_CLCH, t_CHCL, t_SHQZ, t_HHQX, t_HLQZ, t_DP, and t_RDPsignal values are guaranteed by charac-

terization, not 100% tested in production.

6. The t_CLCHand t_CHCLsignals clock rise and fall time values are expressed as a slew-rate.

7. The t_WHSLand t_SHWLsignal values are only applicable as a constraint for a WRITE STATUS

REGISTER command when SRWD bit is set at 1.

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45

Micron M25P40 Serial Flash Embedded Memory

AC Characteristics

Figure 23: Serial Input Timing

tSHSL

S#

tCHSL

tSLCH

tCHSH

tSHCH

C

tDVCH

tCHCL

tCHDX

tCLCH

DQ0

DQ1

MSB IN

LSB IN

high impedance

Figure 24: Write Protect Setup and Hold during WRSR when SRWD=1 Timing

W#/V

PP

tSHWL

tWHSL

S#

C

DQ0

high impedance

DQ1

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Micron M25P40 Serial Flash Embedded Memory

AC Characteristics

Figure 25: Hold Timing

S#

tHLCH

tHHCH

tCHHL

C

tCHHH

tHLQZ

tHHQX

DQ1

DQ0

HOLD#

Figure 26: Output Timing

S#

tCH

C

tCLQV

tCL

tSHQZ

tCLQX

LSB OUT

DQ1

DQ0

tQLQH

tQHQL

ADDRESS

LSB IN

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Micron M25P40 Serial Flash Embedded Memory

Package Information

Figure 27: SO8N 150 mils Body Width

0.25 MIN/

x 45°

0.50 MAX

1.75 MAX/

1.25 MIN

0.17 MIN/

0.23 MAX

0.10 MAX

0.28 MIN/

0.48 MAX

1.27 TYP

0.25mm

Gauge plane

4.90 ±0.10

0^oMIN/

8^oMAX

8

1

6.00 ±0.20

3.90 ±0.10

0.10 MIN/

0.25 MAX

0.40 MIN/

1.27 MAX

1.04 TYP

1. The 1 that appears in the top view of the package indicates the position of pin 1.

Notes:

2. Drawing is not to scale.

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Micron M25P40 Serial Flash Embedded Memory

Package Information

Figure 28: SO8W 208 mils Body Width

1.51 MIN/

2.00 MAX

2.50 MAX

0.10 MIN/

0.35 MAX

-0.05

+0.11

0.40

0.10 MAX

1.27 TYP

6.05 MAX

7.62 MIN/

8.89 MAX

8

5.02 MIN/

6.22 MAX

1

0.00 MIN/

0.25 MAX

0^ºMIN/

0.50 MIN/

0.80 MAX

10^°MAX

1. Drawing is not to scale.

Note:

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49

Micron M25P40 Serial Flash Embedded Memory

Package Information

Figure 29: DFN8 6mm x 5mm

6 TYP

Pin 1 ID

laser marking

Pin 1 ID

option

Pin 1 ID

1.27

TYP

3.00 ±0.20

5 TYP

+0.08

-0.05

0.40

3.00 ±0.20

+0.15

-0.1

0.6

0.90 ±0.10

0.1

0.08 C

Leads coplinarity

C

Seating plane

C

0.20 TYP

+0.03

-0.02

0.02

1. Drawing is not to scale.

Note:

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50

Micron M25P40 Serial Flash Embedded Memory

Package Information

Figure 30: VFDFPN8 (MLP8) 6mm x 5mm

0.15 C A

6 TYP

A

0.10 MAX/

0 MIN

B

5.75 TYP

Pin one

indicator

4.75 TYP

5 TYP

+0.30

-0.20

1.27

TYP

4

2x

0.10 C B

+0.08

-0.05

0.40

3.40 ±0.20

0.10 C A

+0.15

-0.10

0.60

θ

12°

0.05

+0.15

-0.05

0.20 TYP

0.85

0.65 TYP

C

0 MIN/

0.05 MAX

1. Drawing is not to scale.

Note:

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51

Micron M25P40 Serial Flash Embedded Memory

Package Information

Figure 31: UFDFPN8 (MLP8) 4mm x 3mm

0.80 ±0.10

Datum A

4.00 ±0.10

A

1

2

3

4

B

8 x (0.60 ±0.05)

Datum B

0.20 ±0.10

0.20 DIA TYP

3.00 ±0.10

(See note 1)

8 x (0.30 ±0.05)

See detail A

2X

0.10

C

8

7

6

5

0.10 M C A B

0.05 M C

1

2

0.80 TYP

2X

0.10

C

Top View

Bottom View

Datum A or B

-0.10

+0.05

0.55

//

0.10

C

0.60 ±0.05

0.05

C

Seating Plane

-0.02

0.02

Terminal Tip

0.40 TYP

0.80 TYP

+0.03

0.127 MIN/

0.15 MAX

Side View

Even Terminal/Side

Detail A

1. The dimension 0.30 ±0.05 applies to the metallic terminal and is measured between

0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on

the other end of the terminal, the dimensions should not be measured in that radius

area.

Notes:

2. Maximum package warping is 0.05mm; maximum allowable burrs is 0.076mm in all di-

rections; the bilateral coplanarity zone applies to the exposed heat sink slug as well as

to the terminals.

3. Drawing is not to scale.

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Micron M25P40 Serial Flash Embedded Memory

Package Information

Figure 32: UFDFPN8 (MLP8) 2mm x 3mm

-0.10

2.00

-0.05

+0.05

0.50 TYP

0.25

+0.10

0.15 MAX

0.30 MIN

-0.10

3.00

-0.10

0.20

+0.10

-0.05

0.45

+0.05

-0.10

1.60

+0.10

-0.10

0.55

+0.05

0.08 MAX

-0.02

0.02

+0.03

1. Drawing is not to scale.

Note:

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53

Micron M25P40 Serial Flash Embedded Memory

Device Ordering Information

Standard Parts

For further information on line items not listed here or on any aspect of this device,

contact your nearest representative.

Table 25: Part Number Example

Part Number Category

Device Packing

Package Grade Option Technology Lithography

Device

Type Density Features

M25P 40

Security

Operating

Voltage

Plating

Automotive

Grade

–

V

MN

6

T

P

B

A

Table 26: Part Number Information Scheme

Part Number


型号：	M25P40-VMC6Txx
厂家：	MICRON TECHNOLOGY
描述：	Micron M25P40 Serial Flash Embedded Memory 美光M25P40串行闪存的嵌入式存储器闪存存储
文件：	总59页 (文件大小：785K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M25P40-VMC6Txx [MICRON]

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