USB2240-AEZG-XX [MICROCHIP]
FLASH MEMORY DRIVE CONTROLLER, QCC36, 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, QFN-36;型号: | USB2240-AEZG-XX |
厂家: | MICROCHIP |
描述: | FLASH MEMORY DRIVE CONTROLLER, QCC36, 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, QFN-36 数据传输 外围集成电路 |
文件: | 总53页 (文件大小:713K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
USB224x
Ultra Fast USB 2.0 Multi-Format, SD/MMC,
and MS Flash Media Controllers
Datasheet
PRODUCT FEATURES
GPIO configuration and polarity
General Description
—
—
Up to 8 GPIOs for special function use
One GPIO with up to 200 mA drive
The SMSC USB224x is a USB 2.0 compliant, Hi-Speed
1
bulk only mass storage class peripheral controller intended
On board 24 MHz crystal driver circuit
Optional external 24 MHz clock input
Internal card power FET
for reading and writing to popular flash media from the xD-
3
2
®
Picture CardTM (xD) , Memory Stick (MS), Secure Digital
(SD), and MultiMediaCardTM (MMC) families.
—
—
200 mA
"Fold-back" short circuit protection
The SMSC USB224x is a fully integrated, single chip
solution capable of ultra high performance operation.
Average sustained transfer rates exceeding 35 MB/s are
possible if the media and host can support those rates. The
USB2244/44i includes provisions to read/write secure
media formats.
8051 8-bit microprocessor
—
—
60 MHz - single cycle execution
64 KB ROM | 14 KB RAM
Supports a single external 3.3 V supply source; internal
regulators provide 1.8 V internal core voltage for
additional bill of materials and power savings
Optimized pinout improves signal routing which eases
implementation for improved signal integrity
General Features
Low pin count 36-pin QFN (6x6 mm) lead-free RoHS
compliant package
Flash Media Specification Compliance
USB2240/40i/41/41i
Secure Digital 2.0
—
Targeted for applications in which single or "combo"
media sockets are used
—
—
HS-SD, SDHC
TransFlashTM and reduced form factor media
Hardware-controlled data flow architecture for all self-
mapped media
Pipelined hardware support for access to non-self-
mapped media
Order number with “i” denote the products that support
the industrial temperature range of -40ºC to 85ºC
Support included for secure media format on a licensed,
customized basis
MultiMediaCard 4.2
1/4/8-bit MMC
Memory Stick Formats
—
—
—
MS 1.43, Pro 1.02, Duo 1.10
Pro-HG Duo 1.01
–
MS, MS Duo, HS-MS, MS Pro-HG, MS Pro
xD-Picture Card 1.2
—
—
USB2244/44i: SD Secure
Software Features
USB2242/42i: Sony MagicGateTM
Customizable vendor specific data
Optimized for low latency interrupt handling
Reduced memory footprint
Hardware Features
Single chip flash media controller with
—
USB2240/40i/41/4i: multiplexed interface for use with
“combo” card sockets
USB2242/42i: MS flash media reader/writer
USB2244/44i: SD/MMC flash media reader/writer
Applications
Flash media card reader/writers
Desktop and mobile PCs
Printers
—
—
Consumer A/V and media players/viewers
SDIO and MMC Streaming Mode support
Extended configuration options
—
—
Compatible with
®
–
–
–
–
Microsoft VistaTM and Vista ReadyBoostTM
Windows XP, ME, 2K SP4
Apple Mac OSx
Linux Mass Storage Class Drivers
xD player mode operation
Socket switch polarities, etc.
®
®
Media Activity LED
1.Bulk only is not applicable to USB2240/40i/41/41i.
2.xD-Picture Card is not applicable to USB2241/41i.
3.Only applicable to USB2240/40i/41/41i.
Revision 2.1 (02-07-13)
SMSC USB224x
DATASHEET
Ultra Fast USB 2.0 Multi-Format, SD/MMC, and MS Flash Media Controllers
Datasheet
Order Numbers:
LEAD-FREE
ROHS
COMPLIANT
PACKAGE
MS/
MS PRO/
OPERATING
MS PRO-HG TEMPERATURE
ORDER NUMBERS
TYPE / SIZE
SD/MMC
xD
USB2240-AEZG-XX
USB2240i-AEZG-XX
USB2241-AEZG-XX
USB2241i-AEZG-XX
USB2242-AEZG-XX
USB2242i-AEZG-XX
USB2244-AEZG-XX
USB2244i-AEZG-XX
0ºC to 70ºC
-40ºC to 85ºC
0ºC to 70ºC
-40ºC to 85ºC
0ºC to 70ºC
-40ºC to 85ºC
0ºC to 70ºC
-40ºC to 85ºC
36 QFN
6 x 6 x 0.5 mm
“XX” in the order number indicates the internal ROM firmware revision level.
Please contact your SMSC sales representative for more information.
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Please contact your SMSC sales representative for additional documentation related to this product
such as application notes, anomaly sheets, and design guidelines.
Copyright © 2013 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 2.1 (02-07-13)
2
SMSC USB224x
DATASHEET
Ultra Fast USB 2.0 Multi-Format, SD/MMC, and MS Flash Media Controllers
Datasheet
Table of Contents
Chapter 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2 Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 3 Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 4 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 5 Pin Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 USB224x 36-Pin QFN Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 7 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 Card Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2 System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.1 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.2 EEPROM Data Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.3 EEPROM Data Descriptor Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2.4 A0h-A7h: Device Power Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.5 Device ID Strings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.3 Default Configuration Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3.1 External Hardware RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3.2 USB Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 8 Pin Reset States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1 USB2240/40i/41/41i Pin Reset States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2 USB2242/42i Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3 USB2244/44i Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 9 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.3 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.4 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.5 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 10 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 Oscillator/Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 11 GPIO Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 12 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SMSC USB224x
3
Revision 2.1 (02-07-13)
DATASHEET
Ultra Fast USB 2.0 Multi-Format, SD/MMC, and MS Flash Media Controllers
Datasheet
List of Tables
Table 5.1 USB2240/2240i 36-Pin QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5.2 USB2241/2241i 36-Pin QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5.3 USB2242/2242i 36-Pin QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5.4 USB2244/2244i 36-Pin QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6.1 USB224x 36-PiN QFN Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6.2 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7.1 Internal Flash Media Controller Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7.2 RESET_N Timing for EEPROM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8.1 Legend for Pin Reset States Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8.2 USB2240/40i/41/41i 36-Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8.3 USB2242/42i 36-Pin Reset States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 8.4 USB2244/USB2244i 36-Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9.1 Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 9.2 36-Pin QFN Package Thermal Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 10.1 Crystal Circuit Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 11.1 USB2240/40i and USB2241/41i GPIO Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 11.2 USB2242/42i GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 11.3 USB2244/44i GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 12.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 12.2 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Revision 2.1 (02-07-13)
4
SMSC USB224x
DATASHEET
Ultra Fast USB 2.0 Multi-Format, SD/MMC, and MS Flash Media Controllers
Datasheet
List of Figures
Figure 3.1 USB2240/40i/41/41i Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3.2 USB2242/42i Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.3 USB2244/44i Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4.1 USB2240/USB2240i 36-Pin QFN Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4.2 USB2241/USB2241i 36-Pin QFN Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4.3 USB2242/USB2242i 36-Pin QFN Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4.4 USB2244/USB2244i 36-Pin QFN Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7.1 RESET_N Timing for EEPROM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 8.1 Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 9.1 Supply Rise Time Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 10.1 Typical Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 10.2 Capacitance Formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 10.3 Ceramic Resonator Usage with SMSC IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 12.1 USB224x 36-QFN, 6x6 mm Body, 0.5 mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 12.2 Additional Package Information and Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SMSC USB224x
5
Revision 2.1 (02-07-13)
DATASHEET
Ultra Fast USB 2.0 Multi-Format, SD/MMC, and MS Flash Media Controllers
Datasheet
Chapter 1 Overview
The SMSC USB224x is a flash media card reader solution fully compliant with the USB 2.0
specification. All required resistors on the USB ports are integrated into the device. This includes all
series termination resistors on D+ and D– pins and all required pull-down and pull-up resistors. The
over-current sense inputs for the downstream facing ports have internal pull-up resistors.
Hardware Features
Single chip flash media controller in low pin count 36-pin QFN, lead-free RoHS compliant package
Commercial temperature products support 0°C to +70°C: USB2240/41, USB2242 and USB2244
Industrial temperature products support -40°C to +85°C: USB2240i/41i, USB2242i and USB2244i
Up to 8 GPIOs
- Configuration and polarity for special function use such as LED indicators, button inputs, and
power control to memory devices
- The number of actual GPIOs depends on the implementation configuration used
One GPIO available with up to 200 mA drive and “fold-back” short circuit protection
8051 8-bit microprocessor
- 60 MHz - single cycle execution
- 64 KB ROM |14 KB RAM
Supports a single external 3.3 V supply source; internal regulators provide 1.8 V internal core
voltage for additional bill of materials and power savings
Compliance with the following flash media card specifications:
Secure Digital 2.0
- HS-SD and SDHC
- TransFlash™ and reduced form factor media
MultiMediaCard 4.2
- 1/4/8 bit MMC
Memory Stick 1.43
Memory Stick Pro Format 1.02
Memory Stick Pro-HG Duo Format 1.01
- Memory Stick, MS Duo, HS-MS, MS Pro-HG, MS Pro
Memory Stick Duo 1.10
xD-Picture Card 1.2
Software Features
If the OEM is using an external EEPROM, the following features are available:
- Customizable vendor, product, language, and device ID’s
- 12-hex digits maximum for the serial number string
- 28-character manufacturer ID and product strings for the flash media reader/writer
- LED blink interval or duration
Revision 2.1 (02-07-13)
6
SMSC USB224x
DATASHEET
Ultra Fast USB 2.0 Multi-Format, SD/MMC, and MS Flash Media Controllers
Datasheet
Chapter 2 Acronyms
ATA: Advanced Technology Attachment
FET: Field Effect Transistor
LUN: Logical Unit Number
MMC: MultiMediaCard1
MSC: Memory Stick Controller2
PLL: Phase-Locked Loop
QFN: Quad Flat No leads
RoHS: Restriction of Hazardous Substances Directive
RXD: Received eXchange Data
SDIO: Secure Digital Input/Output
SDC: Secure Digital Controller
SIE: Serial Interface Engine
TXD: Transmit eXchange Data
UART: Universal Asynchronous Receiver-Transmitter
UCHAR: Unsigned Character
UINT: Unsigned Integer
*Note: In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made
the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other
intellectual property rights from or through various persons or entities, including without limitation media standard companies,
forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations
include without limitation the following: Sony Corporation (Memory Stick, Memory Stick Pro); SD3 LLC (Secure Digital); MultiMedia
Card Association (MultiMediaCard); the SSFDC Forum (SmartMedia); the Compact Flash Association (Compact Flash); and Fuji
Photo Film Co., Ltd., Olympus Optical Co., Ltd., and Toshiba Corporation (xD-Picture Card). SMSC does not make such licenses
or technical information available; does not promise or represent that any such licenses or technical information will actually be
obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or
with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or
otherwise with respect to, any such technical information. SMSC's obligations (if any) under the Terms of Sale Agreement, or any
other agreement with any customer, or otherwise, with respect to infringement, including without limitation any obligations to defend
or settle claims, to reimburse for costs, or to pay damages, shall not apply to any of the devices made the subject of this document
or any software programs related to any of such devices, or to any combinations involving any of them, with respect to infringement
or claimed infringement of any existing or future patents related to solid state disk or other flash memory technology or applications
("Solid State Disk Patents"). By making any purchase of any of the devices made the subject of this document, the customer
represents, warrants, and agrees that it has obtained all necessary licenses under then-existing Solid State Disk Patents for the
manufacture, use and sale of solid state disk and other flash memory products and that the customer will timely obtain at no cost
or expense to SMSC all necessary licenses under Solid State Disk Patents; that the manufacture and testing by or for SMSC of
the units of any of the devices made the subject of this document which may be sold to the customer, and any sale by SMSC of
such units to the customer, are valid exercises of the customer's rights and licenses under such Solid State Disk Patents; that SMSC
shall have no obligation for royalties or otherwise under any Solid State Disk Patents by reason of any such manufacture, use, or
sale of such units; and that SMSC shall have no obligation for any costs or expenses related to the customer's obtaining or having
obtained rights or licenses under any Solid State Disk Patents.
SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER
VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES
AGAINST INFRINGEMENT AND THE LIKE.
No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask
work right, trade secret, or other intellectual property right.
**To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of
these Software License Agreements may be obtained by contacting SMSC.
1.MMC, SDIO, and SDC are not applicable to USB2242/42i.
2.Not applicable to USB2244/44i.
SMSC USB224x
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Datasheet
Chapter 3 Block Diagrams
USB2240/40i
USB2241/41i*
AUTO_CBW
SD/
MMC
PROC
USB
Host
FMI
SIE
CTL
BUS
INTFC
BUS FMDU
INTFC CTL
Multiplexed
Interface
MS
PHY
xD*
3.3 V
EP0 TX
EP0 RX
1.8 V Reg
BUS
RAM
VDD18
4K
total
INTFC
EP1 RX
EP1 TX
EP2 RX
EP2 TX
24 MHz
Crystal
PLL
XDATA BRIDGE
+ BUS ARBITER
VDD18PLL
3.3 V
1.8 V Reg
GPIO10/
CRD_PWR
PWR_FET1
GPIOs
8 pins
RAM
10 KB
ADDR
MAP
SPI
Interface
SPI
Program Memory I/O Bus
ROM
Interface
64 KB
Trace FIFO
Clock
Generation and
Control
SFR
RAM
8051
PROCESSOR
NOTE: xD-Picture Card is not applicable to USB2241/41i.
Figure 3.1 USB2240/40i/41/41i Block Diagram
Revision 2.1 (02-07-13)
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USB2242/USB2242i
AUTO_CBW
PROC
USB
Host
FMI
Media
Interface
SIE
CTL
BUS
INTFC
BUS FMDU
INTFC CTL
MS
PHY
3.3 V
EP0 TX
EP0 RX
1.8 V Reg
BUS
RAM
VDD18
4K
total
INTFC
EP1 RX
EP1 TX
EP2 RX
EP2 TX
24 MHz
Crystal
PLL
XDATA BRIDGE
+ BUS ARBITER
VDD18PLL
3.3 V
1.8 V Reg
GPIO10/
CRD_PWR
PWR_FET1
GPIOs
7 pins
RAM
10 KB
ADDR
MAP
SPI
Interface
SPI
Interface
ROM
Program Memory I/O Bus
64 KB
Trace FIFO
Clock
Generation and
Control
8051
SFR
RAM
PROCESSOR
Figure 3.2 USB2242/42i Block Diagram
SMSC USB224x
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USB2244/USB2244i
AUTO_CBW
PROC
USB
Host
FMI
SD/
MMC
Media
Interface
SIE
CTL
BUS
INTFC
BUS FMDU
INTFC CTL
PHY
3.3 V
EP0 TX
EP0 RX
1.8 V Reg
BUS
RAM
VDD18
4K
total
INTFC
EP1 RX
EP1 TX
EP2 RX
EP2 TX
24 MHz
Crystal
PLL
XDATA BRIDGE
+ BUS ARBITER
VDD18PLL
3.3 V
1.8 V Reg
GPIO10/
CRD_PWR
PWR_FET1
GPIOs
7 pins
RAM
10 KB
ADDR
MAP
SPI
Interface
SPI
Interface
ROM
Program Memory I/O Bus
64 KB
Trace FIFO
Clock
Generation and
Control
SFR
RAM
8051
PROCESSOR
Figure 3.3 USB2244/44i Block Diagram
Revision 2.1 (02-07-13)
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Chapter 4 Pin Configurations
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
TEST
RESET_N
xD_nB/R
xD_nRE
xD_nCE
VDD33
GPIO4
xD_D4 / GPIO6 (SD_WP) / MS_SCLK
GPIO7 / TXD / SCK / MS_SKT_SEL
SMSC
USB2240/2240i
(Top View QFN-36)
XTAL2
XTAL1 (CLKIN)
VDD18PLL
RBIAS
VDD18
xD_nWE
Ground Pad
(must be connected to VSS)
xD_CLE / SD_CMD / MS_D0
xD_ALE / SD_D5 / MS_D1
VDDA33
Indicates pins on the bottom of the device.
Figure 4.1 USB2240/USB2240i 36-Pin QFN Diagram
SMSC USB224x
11
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28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
TEST
RESET_N
NC
GPIO4
GPIO6 (SD_WP) / MS_SCLK
GPIO7 / TXD / SCK / MS_SKT_SEL
XTAL2
NC
NC
SMSC
USB2241/2241i
(Top View QFN-36)
VDD33
VDD18
NC
XTAL1 (CLKIN)
VDD18PLL
Ground Pad
(must be connected to VSS)
RBIAS
SD_CMD / MS_D0
SD_D5 / MS_D1
VDDA33
Indicates pins on the bottom of the device.
Figure 4.2 USB2241/USB2241i 36-Pin QFN Diagram
Revision 2.1 (02-07-13)
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28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
RESET_N
NC
TEST
GPIO4
NC
MS_SCLK
GPIO7 / TXD / SCK / MS_SKT_SEL
NC
SMSC
USB2242/2242i
(Top View QFN-36)
XTAL2
XTAL1 (CLKIN)
VDD18PLL
RBIAS
VDD33
VDD18
NC
Ground Pad
(must be connected to VSS)
MS_D0
MS_D1
VDDA33
Indicates pins on the bottom of the device.
Figure 4.3 USB2242/USB2242i 36-Pin QFN Diagram
SMSC USB224x
13
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28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
RESET_N
NC
TEST
GPIO4
NC
SD_WP
NC
GPIO7 / TXD / SCK
XTAL2
SMSC
USB2244/2244i
(Top View QFN-36)
VDD33
VDD18
NC
XTAL1 (CLKIN)
VDD18PLL
RBIAS
Ground Pad
(must be connected to VSS)
SD_CMD
SD_D5
VDDA33
Indicates pins on the bottom of the device.
Figure 4.4 USB2244/USB2244i 36-Pin QFN Diagram
Revision 2.1 (02-07-13)
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Chapter 5 Pin Tables
Table 5.1 USB2240/2240i 36-Pin QFN Package
xD/SD/MS INTERFACE (18 PINS)
xD_D3 /
SD_D1 /
MS_D5
xD_D2 /
SD_D0 /
MS_D4
xD_D1 /
SD_D7 /
MS_D6
xD_D0 /
SD_D6 /
MS_D7
xD_nWP /
SD_CLK /
MS_BS
xD_ALE /
SD_D5 /
MS_D1
xD_CLE /
SD_CMD /
MS_D0
xD_D7 /
SD_D4 /
MS_D2
xD_D6 /
SD_D3 /
MS_D3
xD_D5 / SD_D2
xD_nB/R
xD_nRE
xD_nCE
xD_nWE
xD_D4 /
GPIO6
(SD_WP) /
GPIO12 (MS_INS)
MS_SCLK
GPIO14 (xD_nCD)
GPIO15 (SD_nCD)
USB INTERFACE (5 PINS)
USB+
USB-
XTAL1 (CLKIN)
XTAL2
RBIAS
MISC (7 Pins)
GPIO7 /
TXD /
SCK /
GPIO2 /
RXD /
SDA
GPIO1 (LED)
GPIO4
MS_SKT_SEL
GPIO10 (CRD_PWR)
TEST
RESET_N
DIGITAL, POWER (6 PINS)
(3) VDD33
VDDA33
VDD18
VDD18PLL
TOTAL 36
SMSC USB224x
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Table 5.2 USB2241/2241i 36-Pin QFN Package
SD/MS INTERFACE (14 PINS)
SD_D1 /
MS_D5
SD_D0 /
MS_D4
SD_D7 /
MS_D6
SD_D6 /
MS_D7
SD_CLK /
MS_BS
SD_D5 /
MS_D1
SD_CMD /
MS_D0
SD_D4 /
MS_D2
GPIO6
(SD_WP) /
MS_SCLK
SD_D3 /
MS_D3
SD_D2
GPIO12 (MS_INS)
GPIO14
GPIO15 (SD_nCD)
USB INTERFACE (5 PINS)
USB+
USB-
XTAL1 (CLKIN)
XTAL2
RBIAS
MISC (11 Pins)
GPIO7 /
TXD /
SCK /
GPIO2 /
RXD /
SDA
GPIO1 (LED)
GPIO4
MS_SKT_SEL
GPIO10 (CRD_PWR)
TEST
RESET_N
(4) NC
DIGITAL, POWER (6 PINS)
(3) VDD33
VDDA33
VDD18
VDD18PLL
TOTAL 36
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Table 5.3 USB2242/2242i 36-Pin QFN Package
MS INTERFACE (11 PINS)
MS_D0
MS_D4
MS_BS
MS_D1
MS_D2
MS_D6
MS_D3
MS_D7
MS_D5
MS_SCLK
GPIO12 (MS_INS)
USB INTERFACE (5 PINS)
USB+
USB-
XTAL1 (CLKIN)
XTAL2
RBIAS
MISC (14 PINS)
GPIO7 /
TXD /
SCK /
GPIO2 /
RXD /
SDA
GPIO1 (LED)
GPIO4
MS_SKT_SEL
GPIO10 (CRD_PWR)
TEST
GPIO14
GPIO15
(5) NC
RESET_N
DIGITAL, POWER (6 PINS)
(3) VDD33
VDDA33
VDD18
VDD18PLL
TOTAL 36
SMSC USB224x
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Table 5.4 USB2244/2244i 36-Pin QFN Package
SD/MMC INTERFACE (12 Pins)
SD_D0
SD_D4
SD_D1
SD_D5
SD_D2
SD_D3
SD_D7
SD_D6
SD_CLK
SD_CMD
SD_WP
GPIO15 (SD_nCD)
USB INTERFACE (5 PINS)
USB+
USB-
XTAL1 (CLKIN)
XTAL2
RBIAS
MISC (13 PINS)
GPIO2 /
RXD /
SDA
GPIO7 /
TXD /
SCK
GPIO1 (LED)
GPIO10 (CRD_PWR)
TEST
GPIO4
GPIO12
GPIO14
(4) NC
RESET_N
DIGITAL, POWER (6 PINS)
(3)VDD33
VDDA33
VDD18
VDD18PLL
TOTAL 36
Revision 2.1 (02-07-13)
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Datasheet
Chapter 6 Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional
groups according to their associated interface. The pin descriptions are applied when using the internal
default firmware and can be referenced in Chapter 7, "Pin Configurations," on page 26. Please
reference Chapter 2, "Acronyms," on page 7 for a list of the acronyms used.
The “n” symbol in the signal name indicates that the active, or asserted, state occurs when the signal
is at a low voltage level. When “n” is not present in the signal name, the signal is asserted at the high
voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working
with a mixture of “active low” and “active high” signals. The term assert, or assertion, indicates that a
signal is active, independent of whether that level is represented by a high or low voltage. The term
negate, or negation, indicates that a signal is inactive.
6.1
USB224x 36-Pin QFN Pin Descriptions
Table 6.1 USB224x 36-PiN QFN Pin Descriptions
BUFFER
TYPE
SYMBOL
DESCRIPTION
xD-PICTURE CARD (xD) INTERFACE (APPLIES ONLY TO USB2240/USB2240i)
xD_D[7:0]
20
23
25
30
4
I/O12PD
xD Data
These bi-directional data signals have weak internal
pull-down resistors.
5
7
8
xD_nWP
xD_ALE
xD_CLE
9
O12PD
O12PD
O12PD
xD Write Protect
This pin is an active low write protect signal for the
xD device and has a weak pull-down resistor that is
permanently enabled.
10
11
xD Address Strobe
This pin is an active high Address Latch Enable
signal for the xD device and has a weak pull-down
resistor that is permanently enabled.
xD Command Strobe
This pin is an active high Command Latch Enable
signal for the xD device and has a weak pull-down
resistor that is permanently enabled.
SMSC USB224x
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Table 6.1 USB224x 36-PiN QFN Pin Descriptions (continued)
BUFFER
TYPE
SYMBOL
xD_nRE
DESCRIPTION
16
O12PU
xD Read Enable
This pin is an active low read strobe signal for the
xD device.
When using the internal FET, this pin has a weak
internal pull-up resistor that is tied to the output of
the internal power FET.
If an external FET is used (Internal FET is disabled),
then the internal pull-up is not available (external
pull-ups must be used).
xD_nWE
12
O12PU
xD Write Enable
This pin is an active low write strobe signal for the
xD device.
When using the internal FET, this pin has a weak
internal pull-up resistor that is tied to the output of
the internal power FET.
If an external FET is used (Internal FET is disabled),
then the internal pull-up is not available (external
pull-ups must be used).
xD_nB/R
17
IPU
xD Busy or Data Ready
This pin is connected to the BSY/RDY pin of the xD
device.
When using the internal FET, this pin has a weak
internal pull-up resistor that is tied to the output of
the internal power FET.
If an external FET is used (Internal FET is disabled),
then the internal pull-up is not available (external
pull-ups must be used).
GPIO14 (Note 6.1)
(xD_nCD)
19
15
I/O12
xD Card Detection GPIO
This is a GPIO designated by the default firmware as
the xD-Picture card detection pin.
Note: This pin can be left unconnected if the socket
is not used.
xD_nCE
O12PU
xD Chip Enable
This pin is the active low chip enable signal to the
xD device.
When using the internal FET, this pin has a weak
internal pull-up resistor that is tied to the output of
the internal power FET.
If an external FET is used (Internal FET is disabled),
then the internal pull-up is not available (external
pull-ups must be used).
Revision 2.1 (02-07-13)
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Table 6.1 USB224x 36-PiN QFN Pin Descriptions (continued)
BUFFER
TYPE
SYMBOL
DESCRIPTION
MEMORY STICK (MS) INTERFACE
MS_D[7:0]
8
7
I/O12PD
MS System Data In/Out
4
5
23
20
10
11
These pins are the bi-directional data signals for the
MS device. MS_D0, MS_D2, and MS_D3 have weak
pull-down resistors.
In serial mode, the most significant bit (MSB) of each
byte is transmitted first by either MSC or MS device
on MS_D0.
In parallel mode, MS_D1 has a pull-down resistor,
otherwise it is disabled.
In 4- or 8-bit parallel mode, there is a weak pull-down
resistor on all MS_D7 - 0 signals.
MS_BS
9
O12
MS Bus State
This pin is connected to the bus state (BS) pin of the
MS device. It is used to control the bus states 0, 1,
2 and 3 (BS0, BS1, BS2 and BS3) of the MS device.
MS_SCLK
30
24
O12
IPU
MS System CLK
This pin is an output clock signal to the MS device.
The clock frequency is software configurable.
GPIO12 (Note 6.1)
(MS_INS)
MS Card Insertion GPIO
This is a GPIO designated by the default firmware as
the Memory Stick card detection pin.
Note: This pin can be left unconnected if the socket
is not used.
SECURE DIGITAL (SD) / MULTIMEDIACARD (MMC) INTERFACE
SD_D[7:0]
7
8
7
8
I/O12PU
SD Data
The pins are bi-directional data signals SD_D0 -
SD_D7 and have weak pull-up resistors.
10
20
23
25
4
10
20
23
25
4
5
5
SD_CLK
SD_CMD
9
9
O12
SD Clock
This is an output clock signal to SD/MMC device.
The clock frequency is software configurable.
11
11
I/O12PU
SD Command
This is a bi-directional signal that connects to the
CMD signal of the SD/MMC device and has a weak
internal pull-up resistor.
SMSC USB224x
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Table 6.1 USB224x 36-PiN QFN Pin Descriptions (continued)
BUFFER
TYPE
SYMBOL
DESCRIPTION
GPIO6 (Note 6.1)
(SD_WP)
30
26
I/O12
SD Write Protect Detection GPIO
This is a GPIO designated by the default firmware as
the Secure Digital card mechanical write protect
detection pin.
GPIO15 (Note 6.1)
(SD_nCD)
I/O12
SD Card Detect GPIO
This is a GPIO designated by the default firmware as
the Secure Digital card detection pin.
USB INTERFACE
USB+
USB-
2
3
I/O-U
USB Bus Data
These pins connect to the USB bus data signals.
USB Transceiver Bias
RBIAS
35
33
32
I-R
A 12.0 kΩ, ± 1.0% resistor is attached from VSS to
this pin in order to set the transceiver's internal bias
currents.
XTAL1 (CLKIN)
XTAL2
ICLKx
24 MHz Crystal (External clock input)
This pin can be connected to one terminal of the
crystal or can be connected to an external 24 MHz
clock when a crystal is not used.
OCLKx
24 MHz Crystal
This is the other terminal of the crystal, or it is left
open when an external clock source is used to drive
XTAL1(CLKIN).
VDDA33
36
34
3.3 V Analog Power
1.8 V PLL Power
VDD18PLL
+1.8 V Filtered analog power for internal PLL. This
pin must have a 1.0 μF ± 20% (ESR < 0.1 Ω)
capacitor to VSS.
MISC
I/O12
GPIO1 (Note 6.1)
(LED)
1
General Purpose I/O (GPIO): This pin may be used
either as input, edge sensitive interrupt input, or
output. Custom firmware is required to activate this
function.
LED: GPIO1 can be used as an LED output.
Revision 2.1 (02-07-13)
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Table 6.1 USB224x 36-PiN QFN Pin Descriptions (continued)
BUFFER
TYPE
SYMBOL
DESCRIPTION
GPIO2 (Note 6.1)/
27
I/O12
GPIO: This pin may be used either as input, edge
sensitive interrupt input, or output. Custom firmware
is required to activate this function.
RXD /
I
RXD: This signal can be used as input to the RXD
of UART in the device. Custom firmware is required
to activate this function.
SDA
I/O12
I/O12
SDA: This is the data pin when used with an external
serial EEPROM.
GPIO4 (Note 6.1)
29
31
GPIO: This pin may be used either as input, edge
sensitive interrupt input, or output. Custom firmware
is required to activate this function.
For the USB2240/USB2240i only, this pin can be
used as the xD-Picture card detection pin.
GPIO7 (Note 6.1)/
TXD /
I/O12
O12
GPIO: This pin may be used either as input, edge
sensitive interrupt input, or output. Custom firmware
is required to activate this function.
TXD: The GPIO7 can be used as an output TXD of
UART in the device. Custom firmware is required to
activate this function.
O12
I
SCK: This is the clock output when used with an
external EEPROM.
SCK /
MS_SKT_SEL: On the positive edge of RESET_N,
this pin is sampled to determined the Memory Stick
socket size.
MS_SKT_SEL
1 = 8-bit
0 = 4-bit
GPIO10 (Note 6.1)
21
I/O200
GPIO: This pin may be used either as input, edge
sensitive interrupt input, or output. Custom firmware
is required to activate this function.
(CRD_PWR)
RESET_N
CRD_PWR: Card power drive of 3.3 V at either 100
mA or 200 mA.
18
28
IS
RESET Input: This active low signal is used by the
system to reset the chip. The active low pulse should
be at least 1 μs wide.
TEST
I
TEST Input: Tie this pin to ground for normal
operation.
GPIO12 (Note 6.1)
GPIO14 (Note 6.1)
GPIO15 (Note 6.1)
24
I/O12
I/O12
I/O12
This pin may be used either as input, edge sensitive
interrupt input, or output.
19
This pin may be used either as input, edge sensitive
interrupt input, or output.
26
This pin may be used either as input, edge sensitive
interrupt input, or output.
SMSC USB224x
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Table 6.1 USB224x 36-PiN QFN Pin Descriptions (continued)
BUFFER
TYPE
SYMBOL
DESCRIPTION
NC
12
15
16
17
12
15
16
17
25
12
15
16
17
No Connect. No trace or signal should be
routed/attached to these pins.
DIGITAL / POWER
VDD18
VDD33
13
+1.8 V core power. This pin must have a 1.0 μF
± 20% (ESR <0.1 Ω) capacitor to VSS.
6
14
3.3 V Power and Regulator Input
22
VSS
ePad
Ground Pad/ePad: the package slug is the only VSS
for the device and must be tied to ground with an
array of 3x3 vias.
Note 6.1 See Table 11.1, "USB2240/40i and USB2241/41i GPIO Usage", Table 11.2, "USB2242/42i
GPIO Usage", or Table 11.3, “USB2244/44i GPIO Usage,” on page 49 for GPIO pin usage
for the internal default configuration.
Revision 2.1 (02-07-13)
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Datasheet
6.2
Buffer Type Descriptions
Table 6.2 Buffer Type Descriptions
BUFFER
DESCRIPTION
I
Input
IPU
IS
Input with internal weak pull-up resistor
Input with Schmitt trigger
I/O12
I/O200
Input/output buffer with 12 mA sink and 12 mA source
Input/Output buffer 12 mA with FET disabled, 100/200 mA source only when the FET
is enabled
I/O12PD
Input/output buffer with 12 mA sink and 12 mA source with an internal weak pull-down
resistor
I/O12PU
O12
Input/output buffer with 12 mA sink and 12 mA source with a pull-up resistor
Output buffer with 12 mA source
O12PU
O12PD
ICLKx
OCLKx
I/O-U
Output buffer with 12 mA sink and 12 mA source, with a pull-up resistor
Output buffer with 12 mA sink and 12 mA source, with a pull-down resistor
XTAL clock input
XTAL clock output
Analog input/output as defined in the USB 2.0 Specification
RBIAS
I-R
Note: The DC characteristics are outlined in Section 9.3, on page 43.
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Chapter 7 Pin Configurations
7.1
Card Reader
The SMSC USB224x is fully compliant with the following flash media card reader specifications:
Secure Digital 2.0
- HS-SD and SDHC
- TransFlash™ and reduced form factor media
MultiMediaCard 4.2
- 1/4/8 bit MMC
Memory Stick 1.43
Memory Stick Pro Format 1.02
Memory Stick Pro-HG Duo Format 1.01
- Memory Stick, MS Duo, HS-MS, MS Pro-HG, MS Pro
Memory Stick Duo 1.10
xD-Picture Card 1.2
7.2
System Configurations
7.2.1
EEPROM
The USB224x can be configured via a 2-wire (I2C) EEPROM (512x8) flash device containing the
options for the USB224x. If an external configuration device does not exist the internal default values
will be used. If one of the external devices is used for configuration, the OEM can update the values
through the USB interface. The device will then “attach” to the upstream USB host.
The USBDM tool set is available in the USB224x/USB225x Card Reader software release package.
To download the software package from SMSC's website, please visit:
https://www2.smsc.com/mkt/CW_SFT_PUB.nsf/Agreements/OBJ+Card+Reader
to go to the OBJ Card Reader Software Download Agreement. Review the license, and if you agree,
check the "I agree" box and then select “Confirm”. You will then be able to download the
USB224x/USB225x Card reader combo release package zip file containing the USBDM tool set.
Please note that the following applies to the system values and descriptions when used:
N/A = Not applicable to this part
Reserved = For internal use
7.2.2
EEPROM Data Descriptor
Table 7.1 Internal Flash Media Controller Configurations
ADDRESS
REGISTER NAME
DESCRIPTION
INTERNAL DEFAULT VALUE
00h
01h
USB_SER_LEN
USB Serial String
Descriptor Length
1Ah
USB_SER_TYP
USB_SER_NUM
USB Serial String
Descriptor Type
03h
02h-19h
USB Serial Number
"000000225001"
(See Note 7.1)
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Table 7.1 Internal Flash Media Controller Configurations (continued)
ADDRESS
REGISTER NAME
DESCRIPTION
INTERNAL DEFAULT VALUE
1Ah-1Bh
1Ch-1Dh
1Eh
USB_VID
USB_PID
USB Vendor Identifier
USB Product Identifier
0424
2240
04h
USB_LANG_LEN
USB Language String
Descriptor Length
1Fh
20h
USB_LANG_TYP
USB_LANG_ID_LSB
USB_LANG_ID_MSB
USB_MFR_STR_LEN
USB_MFR_STR_TYP
USB_MFR_STR
USB Language String
Descriptor Type
03h
USB Language Identifier
Least Significant Byte
09h
(See Note 7.2)
21h
USB Language Identifier
Most Significant Byte
04h
(See Note 7.2)
22h
USB Manufacturer String
Descriptor Length
10h
23h
USB Manufacturer String
Descriptor Type
03h
24h-31h
USB Manufacturer String
“Generic”
(See Note 7.1)
32h-5Dh
5Eh
Reserved
-
00h
24h
USB_PRD_STR_LEN
USB Product String
Descriptor Length
5Fh
USB_PRD_STR_TYP
USB_PRD_STR
USB Product String
Descriptor Type
03h
60h-99h
USB Product String
“Ultra Fast Media Reader"
(See Note 7.1)
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
USB_BM_ATT
USB_MAX_PWR
ATT_LB
USB BmAttribute
USB Max Power
Attribute Lo byte
Attribute Hi Lo byte
Attribute Lo Hi byte
Attribute Hi byte
80h
30h (96 mA)
40h (Reverse SD_WP only)
ATT_HLB
00h
00h
00h
08h
ATT_LHB
ATT_HB
MS_PWR_LB
Memory Stick Device
Power Lo byte
A1h
MS_PWR_HB
Memory Stick Device
Power Hi byte
00h
A2h
A3h
A4h
Reserved
Reserved
-
-
80h
00h
00h
xD_PWR_LB
xD-Picture Card Device
Power Lo byte
A5h
xD_PWR_HB
xD-Picture Card Device
Power Hi byte
08h
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Table 7.1 Internal Flash Media Controller Configurations (continued)
ADDRESS
REGISTER NAME
DESCRIPTION
INTERNAL DEFAULT VALUE
A6h
SD_PWR_LB
Secure Digital Device
Power Lo byte
00h
A7h
SD_PWR_HB
Secure Digital Device
Power Hi byte
80h
A8h
LED_BLK_INT
LED_BLK_DUR
DEV0_ID_STR
DEV1_ID_STR
DEV2_ID_STR
LED Blink Interval
02h
28h
A9h
LED Blink After Access
Device 0 Identifier String
Device 1 Identifier String
Device 2 Identifier String
AAh - B0h
B1h - B7h
B8h - BEh
“COMBO”
“MS”
“SM”
(See Note 7.3)
BFh - C5h
C6h - CDh
CEh-D2h
D3h
DEV3_ID_STR
INQ_VEN_STR
INQ_PRD_STR
DYN_NUM_LUN
DEV_LUN_MAP
Reserved
Device 3 Identifier String
“SD/MMC”
“Generic”
Inquiry Vendor String
Inquiry Product String
2240
Dynamic Number of LUNs
FFh
D4h - D7h
D8h - DAh
DBh - DDh
DEh-FBh
FCh-FFh
Device to LUN Mapping
FFh, FFh, FFh, FFh
00h, 03h, 07h
5Ch, 56h, 97h
00h
-
Reserved
-
Not Applicable
NVSTORE_SIG
-
Non-Volatile Storage Signature
“ATA2”
Note 7.1 This value is a UNICODE UTF-16LE encoded string value that meets the USB 2.0
specification (Revision 2.0, 2000). Values in double quotations without this note are ASCII
values.
Note 7.2 For a list of the most current 16-bit language ID’s defined by the USB-IF, please visit
http://www.unicode.org or consult The Unicode Standard, Worldwide Character Encoding,
(Version 4.0), The Unicode Consortium, Addison-Wesley Publishing Company, Reading,
Massachusetts.
Note 7.3 The “SM” value will be overridden with “xD” once an xD-Picture Card has been identified.
7.2.3
EEPROM Data Descriptor Register Descriptions
7.2.3.1
BYTE
00h: USB Serial String Descriptor Length
NAME
DESCRIPTION
0
USB_SER_LEN
USB serial string descriptor length as defined by Section 9.6.7 “String” of the
USB 2.0 Specification (Revision 2.0, 2000). This field is the “bLength” which
describes the size of the string descriptor (in bytes).
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7.2.3.2
BYTE
01h: USB Serial String Descriptor Type
NAME
DESCRIPTION
1
USB_SER_TYP
USB serial string descriptor type as defined by Section 9.6.7 “String” of the
USB 2.0 Specification (Revision 2.0, 2000). This field is the
“bDescriptorType” which is a constant value associated with a string
descriptor type.
7.2.3.3
02h-19h: USB Serial Number Option
NAME
BYTE
DESCRIPTION
25:2
USB_SER_NUM
Maximum string length is 12 hex digits. Must be unique to each device.
7.2.3.4
1Ah-1Bh: USB Vendor ID Option
NAME
BYTE
DESCRIPTION
1:0
USB_VID
This ID is unique for every vendor. The vendor ID is assigned by the USB
Implementer’s Forum.
7.2.3.5
1Ch-1Dh: USB Product ID Option
NAME
BYTE
DESCRIPTION
1:0
USB_PID
This ID is unique for every product. The product ID is assigned by the vendor.
7.2.3.6
1Eh: USB Language Identifier Descriptor Length
BYTE
NAME
DESCRIPTION
0
USB_LANG_LEN
USB language ID string descriptor length as defined by Section 9.6.7 “String”
of the USB 2.0 Specification (Revision 2.0, 2000). This field is the “bLength”
which describes the size of the string descriptor (in bytes).
7.2.3.7
1Fh: USB Language Identifier Descriptor Type
NAME
BYTE
DESCRIPTION
1
USB_LANG_TYP
USB language ID string descriptor type as defined by Section 9.6.7 “String”
of the USB 2.0 Specification (Revision 2.0, 2000). This field is the
“bDescriptorType” which is a constant value associated with a string
descriptor type.
7.2.3.8
20h: USB Language Identifier Least Significant Byte
BYTE
NAME
DESCRIPTION
2
USB_LANG_ID
_LSB
English language code = ‘0409’. See Note 7.2 to reference additional
language ID’s defined by the USB-IF.
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7.2.3.9
BYTE
21h: USB Language Identifier Most Significant Byte
NAME
DESCRIPTION
3
USB_LANG_ID
_MSB
English language code = ‘0409’. See Note 7.2 to reference additional
language ID’s defined by the USB-IF.
7.2.3.10
22h: USB Manufacturer String Descriptor Length
BYTE
NAME
DESCRIPTION
0
USB_MFR_STR
_LEN
USB manufacturer string descriptor length as defined by Section 9.6.7 “String”
of the USB 2.0 Specification (Revision 2.0, 2000). This field is the “bLength”
which describes the size of the string descriptor (in bytes).
7.2.3.11
23h: USB Manufacturer String Descriptor Type
BYTE
NAME
DESCRIPTION
1
USB_MFR_STR
_TYP
USB manufacturer string descriptor type as defined by Section 9.6.7 “String”
of the USB 2.0 Specification (Revision 2.0, 2000). This field is the
“bDescriptorType” which is a constant value associated with a string
descriptor type.
7.2.3.12
24h-31h: USB Manufacturer String Option
NAME
BYTE
DESCRIPTION
15:2
USB_MFR_STR
The maximum string length is 29 characters.
7.2.3.13
32h-5Dh: Reserved
BYTE
NAME
DESCRIPTION
59:16
Reserved
Reserved.
7.2.3.14
5Eh: USB Product String Descriptor Length
NAME
BYTE
DESCRIPTION
0
USB_PRD_STR
_LEN
USB product string descriptor length as defined by Section 9.6.7 “String” of
the USB 2.0 Specification (Revision 2.0, 2000). This field is the “bLength”
which describes the size of the string descriptor (in bytes). Maximum string
length is 29 characters
7.2.3.15
5Fh: USB Product String Descriptor Type
NAME
BYTE
DESCRIPTION
1
USB_PRD_STR
_TYP
USB product string descriptor type as defined by Section 9.6.7 “String” of the
USB 2.0 Specification (Revision 2.0, 2000). This field is the
“bDescriptorType” which is a constant value associated with a string
descriptor type.
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7.2.3.16
60h-99h: USB Product String Option
BYTE
NAME
DESCRIPTION
59:2
USB_PRD_STR
This string will be used during the USB enumeration process in the
Windows® operating system. Maximum string length is 29 characters.
7.2.3.17
9Ah: USB BmAttribute (1 byte)
NAME
BIT
DESCRIPTION
7:0
USB_BM_ATT
Self- or Bus-Power: Selects between self- and bus-powered operation.
The hub is either self-powered (draws less than 2 mA of upstream bus
power) or bus-powered (limited to a 100 mA maximum of upstream power
prior to being configured by the host controller).
When configured as a bus-powered device, the SMSC device consumes
less than 100 mA of current prior to being configured. After configuration, the
bus-powered SMSC device (along with all associated device circuitry, any
embedded devices if part of a compound device, and 100 mA per externally
available downstream port) must consume no more than 500 mA of
upstream VBUS current. The current consumption is system dependent, and
the OEM must ensure that the USB 2.0 Specification is not violated.
When configured as a self-powered device, <1 mA of upstream VBUS
current is consumed and all ports are available, with each port being capable
of sourcing 500 mA of current.
80 = Bus-powered operation (default)
C0 = Self-powered operation
A0 = Bus-powered operation with remote wake-up
E0 = Self-powered operation with remote wake-up
7.2.3.18
9Bh: USB MaxPower (1 byte)
NAME
BIT
DESCRIPTION
7:0
USB_MAX_PWR
USB Max Power per the USB 2.0 Specification. Do NOT set this value
greater than 100 mA.
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7.2.3.19
9Ch-9Fh: Attribute Byte Descriptions
BYTE
NAME
BYTE
BIT
DESCRIPTION
0
ATT_LB
3:0
4
Always reads ‘0’.
Inquire Manufacturer and Product ID Strings
‘1’ - Use the Inquiry Manufacturer and Product ID Strings.
‘0’ (default) - Use the USB Descriptor Manufacturer and Product ID Strings.
Always reads ‘0’.
5
6
Reverse SD Card Write Protect Sense
‘1’ (default) - SD cards will be write protected when SW_nWP is high, and
writable when SW_nWP is low.
‘0’ - SD cards will be write protected when SW_nWP is low, and writable
when SW_nWP is high.
7
3:0
4
Reserved.
1
ATT_HLB
Always reads ‘0’.
Activity LED True Polarity
‘1’ - Activity LED to Low True.
‘0’ (default) - Activity LED polarity to High True.
Common Media Insert / Media Activity LED
5
‘1’ - The activity LED will function as a common media inserted/media
access LED.
‘0’ (default) - The activity LED will remain in its idle state until media is
accessed.
6
7
0
Always reads ‘0’.
Reserved.
2
ATT_LHB
Attach on Card Insert / Detach on Card Removal
‘1’ - Attach on Insert is enabled.
‘0’ (default) - Attach on Insert is disabled.
Always reads ‘0’.
1
2
Enable Device Power Configuration
‘1’ - Custom Device Power Configuration stored in the NVSTORE is used.
‘0’ (default) - Default Device Power Configuration is used.
Always reads ‘0’.
7:3
6:0
7
3
ATT_HB
Always reads ‘0’.
xD Player Mode
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7.2.4
A0h-A7h: Device Power Configuration
The USB224x has one internal FET which can be utilized for card power. This section describes the
default internal configuration. The settings are stored in NVSTORE and provide the following features:
1. A card can be powered by an external FET or by an internal FET.
2. The power limit can be set to 100 mA or 200 mA (Default) for the internal FET.
Each media uses two bytes to store its device power configuration. Bit 3 selects between internal or
external card power FET options. For internal FET card power control, bits 0 through 2 are used to
set the power limit. The “Device Power Configuration” bits are ignored unless the “Enable Device
Power Configuration” bit is set. See Section 7.2.3.19, "9Ch-9Fh: Attribute Byte Descriptions," on
page 32.
7.2.4.1
FET
A0h-A1h: Memory Stick Device Power Configuration
TYPE
BITS
BIT TYPE
Low Nibble
DESCRIPTION
0
1
2
FET Lo Byte
MS_PWR_LB
3:0
7:4
3:0
0000b Disabled
0000b Disabled
High Nibble
FET Hi Byte
Low Nibble
0001b External FET enabled
MS_PWR_HB
1000b Internal FET with 100 mA power limit
1010b Internal FET with 200 mA power limit
3
7:4
High Nibble
0000b Disabled
7.2.4.2
A2h-A3h: Not Applicable
NAME
BYTE
DESCRIPTION
1:0
Not Applicable
Not applicable.
7.2.4.3
A4h-A5h: xD-Picture Card Device Power Configuration
When applicable, the "SM" value will be overridden with “xD” once an xD-Picture Card has been
identified.
FET
TYPE
BITS
BIT TYPE
Low Nibble
DESCRIPTION
0
1
2
FET Lo Byte
xD_PWR_LB
3:0
7:4
3:0
0000b Disabled
0000b Disabled
High Nibble
FET Hi Byte
xD_PWR_HB
Low Nibble
0001b External FET enabled
1000b Internal FET with 100 mA power limit
1010b Internal FET with 200 mA power limit
3
7:4
High Nibble
0000b Disabled
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7.2.4.4
A6h-A7h: Secure Digital Device Power Configuration
FET
TYPE
BITS
BIT TYPE
Low Nibble
DESCRIPTION
0
1
2
FET Lo Byte
SD_PWR_LB
3:0
7:4
3:0
0000b Disabled
0000b Disabled
High Nibble
FET Hi Byte
SD_PWR_HB
Low Nibble
0001b External FET enabled
1000b Internal FET with 100 mA power limit
1010b Internal FET with 200 mA power limit
3
7:4
High Nibble
0000b Disabled
7.2.4.5
A8h: LED Blink Interval
NAME
BYTE
DESCRIPTION
0
LED_BLK_INT
The blink rate is programmable in 50 ms intervals. The high bit (7) indicates
an idle state:
‘0’ - Off
‘1’ - On
The remaining bits (6:0) are used to determine the blink interval up to a max
of 128 x 50 ms.
7.2.4.6
A9h: LED Blink Duration
NAME
BYTE
DESCRIPTION
1
LED_BLK_DUR
LED Blink After Access. This byte is used to designate the number of
seconds that the GPIO1 LED will continue to blink after a drive access.
Setting this byte to "05" will cause the GPIO 1 LED to blink for 5 seconds
after a drive access.
7.2.5
Device ID Strings
These bytes are used to specify the LUN descriptor returned by the device. These bytes are used in
combination with the device to LUN mapping bytes in applications where the OEM wishes to reorder
and rename the LUNs. If multiple devices are mapped to the same LUN (a COMBO LUN), then the
CLUN#_ID_STR will be used to name the COMBO LUN instead of the individual device strings. When
applicable, the "SM" value will be overridden with xD once an xD-Picture Card has been identified.
7.2.5.1
AAh-B0h: Device 0 Identifier String
BYTE
NAME
DESCRIPTION
6:0
DEV0_ID_STR
Not applicable.
7.2.5.2
B1h-B7h: Device 1 Identifier String
NAME
BYTE
DESCRIPTION
6:0
DEV1_ID_STR
This ID string is associated with the Memory Stick device.
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7.2.5.3
BYTE
B8h-BEh: Device 2 Identifier String
NAME
DESCRIPTION
6:0
DEV2_ID_STR
This ID string is associated with the xD-Picture Card device.
7.2.5.4
BFh-C5h: Device 3 Identifier String
NAME
BYTE
DESCRIPTION
6:0
DEV3_ID_STR
This ID string is associated with the Secure Digital / MultiMediaCard device.
7.2.5.5
C6h-CDh: Inquiry Vendor String
NAME
BYTE
DESCRIPTION
7:0
INQ_VEN_STR
If bit 4 of the 1st attribute byte is set, the device will use these strings in
response to a USB inquiry command, instead of the USB descriptor
manufacturer and product ID strings.
7.2.5.6
CEh-D2h: Inquiry Product String
NAME
BYTE
DESCRIPTION
4:0
INQ_PRD_STR
If bit 4 of the 1st attribute byte is set, the device will use these strings in
response to a USB inquiry command, instead of the USB descriptor
manufacturer and product ID strings.
7.2.5.7
D3h: Dynamic Number of LUNs
NAME
BIT
DESCRIPTION
7:0
DYN_NUM_LUN
These bytes are used to specify the number of LUNs the device exposes to
the host. These bytes are also used for icon sharing by assigning more than
one LUN to a single icon. This is used in applications where the device
utilizes a combo socket and the OEM wishes to have only a single icon
displayed for one or more interfaces.
If this field is set to "FF", the program assumes that you are using the default
value and icons will be configured per the default configuration.
7.2.5.8
D4h-D7h: Device to LUN Mapping
NAME
BYTE
DESCRIPTION
3:0
DEV_LUN_MAP
These registers map a device controller (SD/MMC, SM, and MS) to a Logical
Unit Number (LUN). The device reports the mapped LUNs to the USB host
in the USB descriptor during enumeration. The icon installer associates
custom icons with the LUNs specified in these fields.
Setting a register to "FF" indicates that the device is not mapped. Setting all
of the DEV_LUN_MAP registers for all devices to "FF" forces the use of the
default mapping configuration. Not all configurations are valid. Valid
configurations depend on the hardware, packaging, and OEM board layout.
The number of unique LUNs mapped must match the value in the Section
7.2.5.7, "D3h: Dynamic Number of LUNs," on page 35.
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7.2.5.9
BYTE
D8h-FBh: Not Applicable
NAME
DESCRIPTION
DESCRIPTION
35:0
Not Applicable
Not Applicable.
7.2.5.10
FCh-FFh: Non-Volatile Storage Signature
NAME
BYTE
3:0
NVSTORE_SIG
This signature is used to verify the validity of the data in the first 256 bytes of
the configuration area. The signature must be set to ‘ATA2’ for USB224x.
7.3
Default Configuration Option
The SMSC device can be configured via its internal default configuration. Please see Section 7.2.2,
"EEPROM Data Descriptor" for specific details on how to enable default configuration. Please refer to
Table 7.1 for the internal default values that are loaded when this option is selected.
7.3.1
External Hardware RESET_N
A valid hardware reset is defined as assertion of RESET_N for a minimum of 1 μs after all power
supplies are within operating range. While reset is asserted, the device (and its associated external
circuitry) consumes less than 500 μA of current from the upstream USB power source.
Assertion of RESET_N (external pin) causes the following:
1. The PHY is disabled and the differential pair will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
4. The external crystal oscillator is halted.
5. The PLL is halted.
6. The processor is reset.
7. All media interfaces are reset.
7.3.1.1
RESET_N for EEPROM Configuration
Start
completion
request
Hardware
reset
asserted
Device
Recovery/
Stabilization
8051 Sets
Configuration
Registers
Attach
USB
Upstream
USB Reset
recovery
Idle
response
t4
t6
t7
t1
t5
t2
t3
RESET_N
VSS
Figure 7.1 RESET_N Timing for EEPROM Mode
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Table 7.2 RESET_N Timing for EEPROM Mode
DESCRIPTION MIN TYP
NAME
MAX
UNITS
t1
t2
t3
t4
t5
t6
t7
RESET_N asserted
1
μsec
μsec
msec
msec
msec
msec
msec
Device recovery/stabilization
8051 programs device configuration
USB attach
500
50
20
100
Host acknowledges attach and signals USB reset
USB idle
100
Undefined
Ready to handle requests (with or without data)
5
Note: All power supplies must have reached the operating levels mandated in Chapter 9, DC
Parameters, prior to (or coincident with) the assertion of RESET_N.
7.3.2
USB Bus Reset
In response to the upstream port signaling a reset to the device, the device does the following:
1. Sets default address to ‘0’.
2. Sets configuration to: Unconfigured.
3. All transactions are stopped.
4. Processor reinitializes and restarts.
5. All media interfaces are disabled.
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Chapter 8 Pin Reset States
Hardware
Firmware
Initialization
Operational
Voltage
Signal
RESET
(v)
RESET
VDD33
Time
(t)
VSS
Figure 8.1 Pin Reset States
Table 8.1 Legend for Pin Reset States Table
SYMBOL DESCRIPTION
0
Output driven low
1
Output driven high
IP
PU
PD
--
Input enabled
Hardware enables pull-up
Hardware enables pull-down
Hardware disables function
Z
Hardware disables pad. Both output
driver and input buffers are disabled.
8.1
USB2240/40i/41/41i Pin Reset States
Table 8.2 USB2240/40i/41/41i 36-Pin Reset States
RESET STATE
INPUT/
OUT-
PUT
PU/
PD
PIN
PIN NAME
FUNCTION
8
7
xD_D0 / SD_D6 / MS_D7
xD_D1 / SD_D7 / MS_D6
xD_D2 / SD_D0 / MS_D4
xD_D3 / SD_D1 / MS_D5
xD_D4 / GPIO6 (SD_WP) / MS_SCLK
xD_D5 / SD_D2
none
none
z
z
--
--
5
none
z
--
4
none
z
--
30
25
26
SD_WP
none
0
z
--
--
GPIO15 (SD_nCD)
GPIO
IP
pu
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Table 8.2 USB2240/40i/41/41i 36-Pin Reset States (continued)
RESET STATE
INPUT/
OUT-
PUT
PU/
PD
PIN
PIN NAME
FUNCTION
24
23
20
9
GPIO12 (MS_INS)
xD_D6 / SD_D3 / MS_D3
xD_D7 / SD_D4 / MS_D2
xD_nWP / SD_CLK / MS_BS
xD_ALE / SD_D5 / MS_D1
xD_CLE / SD_CMD / MS_D0
GPIO14 (xD_nCD)
GPIO1 (LED)
GPIO
none
IP
z
pu
--
--
--
--
--
pu
--
--
--
--
--
--
--
--
--
--
--
--
--
none
z
none
z
10
11
19
1
none
z
none
z
GPIO
GPIO
none
IP
0
z
16
27
29
31
21
28
18
12
17
15
2
xD_nRE
GPIO2 / RXD / SDA
GPIO4
GPIO
GPIO
GPIO
GPIO
TEST
RESET_N
none
0
0
0
z
GPIO7 / TXD / SCK / MS_SKT_SEL
GPIO10 (CRD_PWR)
TEST
IP
IP
z
RESET_N
xD_nWE
xD_nB/R
none
z
xD_nCE
none
z
USB+
USB+
USB-
z
3
USB-
z
Note: xD signals only apply to USB2240/USB2240i.
8.2
USB2242/42i Pin Reset States
Table 8.3 USB2242/42i 36-Pin Reset States
POST-RESET STATE
MS MODE
RESET STATE
INPUT
PU/
OUT-
PUT
PU/
PD
IN-
PUT
PIN
PIN NAME
FUNCTION
/ OUT-
PUT
FUNCTION
PD
8
MS_D7
none
z
--
MS_D7
hw
pd
yes
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POST-RESET STATE
MS MODE
RESET STATE
INPUT
PU/
PD
OUT-
PUT
PU/
PD
IN-
PUT
PIN
PIN NAME
FUNCTION
/ OUT-
PUT
FUNCTION
7
MS_D6
MS_D4
none
none
z
z
--
--
MS_D6
MS_D4
MS_D5
MS_SCLK
none
hw
hw
hw
hw
z
pd
pd
hw
hw
--
yes
yes
yes
--
5
4
MS_D5
none
z
--
30
25
23
20
9
MS_SCLK
NC
SD_WP
none
0
z
--
--
--
MS_D3
none
z
--
MS_D3
MS_D2
MS_BS
MS_D1
MS_D0
hw
hw
hw
hw
hw
pd
pd
hw
hw
pd
yes
yes
--
MS_D2
none
z
--
MS_BS
none
z
--
10
11
19
26
24
27
29
31
MS_D1
none
z
--
yes
yes
MS_D0
none
z
--
GPIO14
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IP
IP
IP
0
0
0
pu
pu
pu
--
GPIO15
GPIO12 (MS_INS)
GPIO2 / RXD / SDA
GPIO4
--
GPIO7 / TXD / SCK /
MS_SKT_SEL
--
21
28
18
1
GPIO10 (CRD_PWR)
GPIO
TEST
RESET_N
GPIO
none
z
IP
IP
0
--
--
--
--
--
--
--
--
--
--
TEST
RESET_N
GPIO1 (LED)
NC
16
12
17
15
2
z
none
none
none
none
z
z
z
z
--
--
--
--
--
--
--
--
NC
none
z
NC
none
z
NC
none
z
USB+
USB+
USB-
z
3
USB-
z
35
33
32
RBIAS
XTAL1 (CLKIN)
XTAL2
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8.3
USB2244/44i Pin Reset States
Table 8.4 USB2244/USB2244i 36-Pin Reset States
Post-Reset State
SD Mode
RESET STATE
INPUT
/ OUT-
PUT
PU/
PD
OUT-
PUT
PU/
PD
IN-
PUT
PIN
PIN NAME
FUNCTION
FUNCTION
8
SD_D6
SD_D7
SD_D0
SD_D1
SD_WP
SD_D2
SD_D3
SD_D4
SD_CLK
SD_D5
SD_CMD
none
none
none
none
SD_WP
none
none
none
none
none
none
z
z
z
z
0
z
z
z
z
z
z
--
--
--
--
--
--
--
--
--
--
--
SD_D6
SD_D7
SD_D0
SD_D1
SD_WP
SD_D2
SD_D3
SD_D4
SD_CLK
SD_D5
SD_CMD
hw
hw
hw
hw
(fw)
hw
hw
hw
hw
hw
hw
pu
pu
pu
pu
(fw)
pu
pu
pu
--
yes
yes
yes
yes
(fw)
yes
yes
yes
yes
yes
yes
7
5
4
30
25
23
20
9
10
11
pu
pu
19
26
24
27
29
31
21
28
18
1
GPIO14
GPIO15 (SD_nCD)
GPIO12
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
TEST
RESET_N
GPIO
none
IP
IP
IP
0
pu
pu
pu
--
GPIO2 / RXD / SDA
GPIO4
RXD
z
pu
yes
0
--
GPIO7 / TXD / SCK
GPIO10 (CRD_PWR)
TEST
TXD
hw
--
--
--
--
0
--
PWR
VDD
z
--
IP
IP
--
RESET_N
GPIO1 (LED)
NC
--
0
z
--
--
17:15
12
2
none
none
z
z
--
--
--
--
NC
none
z
z
z
--
--
--
USB+
USB+
USB-
3
USB-
35
33
32
RBIAS
XTAL1 (CLKIN)
XTAL2
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Chapter 9 DC Parameters
9.1
Maximum Guaranteed Ratings
PARAMETER
SYMBOL
MIN
MAX
UNITS
COMMENTS
Storage
Temperature
TA
-55
150
°C
Lead
°C
V
Please refer to JEDEC
specification J-STD-020D.
Temperature
3.3 V supply
voltage
VDD33
-0.5
-0.5
4.0
Voltage on
USB+ and
USB- pins
(3.3 V supply voltage + 2) ≤ 6
V
Voltage on
GPIO10
-0.5
VDD33 + 0.3
V
When internal power FET
operation of this pin is enabled,
this pin may be simultaneously
shorted to ground or any
voltage up to 3.63 V
indefinitely, without damage to
the device as long as VDD33
and VDDA33 are less than 3.63
V and TA is less than 70oC.
Voltage on any
signal pin
-0.5
-0.5
-0.5
VDD33 + 0.3
3.6
V
V
V
Voltage on
XTAL1
Voltage on
XTAL2
VDD18 + 0.3
Note 9.1 Stresses above the specified parameters may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at any condition above
those indicated in the operation sections of this specification is not implied.
Note 9.2 When powering this device from laboratory or system power supplies, it is important that
the absolute maximum ratings not be exceeded or device failure can result. Some power
supplies exhibit voltage spikes on their outputs when the AC power is switched on or off.
In addition, voltage transients on the AC power line may appear on the DC output. When
this possibility exists, it is suggested that a clamp circuit be used.
Voltage
tRT
VDD33
3.3 V
100%
90%
10%
VSS
t90%
Time
t10%
Figure 9.1 Supply Rise Time Model
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9.2
Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
COMMENTS
Commercial Part
Industrial Part
TA
0
70
°C
°C
V
Operating Temperature
Ambient temperature in still air.
(Note 9.3)
TA
-40
3.0
0
85
3.3 V supply voltage
VDD33
3.6
400
5.5
3.3 V supply rise time tRT
μs
V
Voltage on
USB+ and USB- pins
-0.3
If any 3.3 V supply voltage drops
below 3.0 V, then the MAX
becomes:
(3.3 V supply voltage) + 0.5 ≤ 5.5
Voltage on any signal
pin
-0.3
VDD33
V
Voltage on XTAL1
Voltage on XTAL2
-0.3
-0.3
VDD33
VDD18
V
V
Note 9.3 A 3.3 V regulator with an output tolerance of 1% must be used if the output of the internal
power FETs must support a 5% tolerance.
9.3
DC Electrical Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
I, IPU, IPD Type Input Buffer
Low Input Level
VILI
VIHI
PD
PU
0.8
V
V
TTL Levels
High Input Level
2.0
Pull Down
72
58
μA
μA
Pull Up
IS Type Input Buffer
Low Input Level
High Input Level
VILI
VIHI
0.8
V
V
TTL Levels
2.0
Hysteresis
VHYSI
420
mV
ICLK Input Buffer
Low Input Level
High Input Level
Input Leakage
VILCK
VIHCK
IIL
0.5
V
V
1.4
-10
+10
μA
VIN = 0 to VDD33
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PARAMETER
Input Leakage
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
(All I and IS buffers)
Low Input Leakage
IIL
-10
-10
+10
+10
μA
μA
VIN = 0
High Input Leakage
IIH
VIN = VDD33
O12 Type Buffer
Low Output Level
High Output Level
Output Leakage
VOL
VOH
IOL
0.4
V
V
IOL = 12 mA @
VDD33= 3.3 V
VDD33
- 0.4
IOH = -12 mA @
VDD33= 3.3 V
-10
+10
0.4
μA
VIN = 0 to VDD33
(Note 9.4)
I/O12, I/O12PU & I/O12PD Type
Buffer
Low Output Level
High Output Level
Output Leakage
VOL
VOH
IOL
V
V
IOL = 12 mA @
VDD33= 3.3 V
VDD33
- 0.4
IOH = -12 mA @
VDD33= 3.3 V
-10
+10
μA
VIN = 0 to VDD33
(Note 9.4)
Pull Down
Pull Up
PD
PU
72
58
μA
μA
IO-U
(Note 9.5)
I-R
(Note 9.6)
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PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
I/O200
Integrated Power FET for
GPIO10
High Output Current Mode
IOUT
IOUT
200
100
mA
mA
VdropFET = 0.46 V
VdropFET = 0.23 V
Low Output Current Mode
(Note 9.7)
On Resistance
(Note 9.7)
RDSON
2.1
Ω
IFET = 70 mA
Output Voltage Rise Time
Supply Current Unconfigured
Supply Current Active
Full Speed
tDSON
800
90
μs
CLOAD = 10 μF
ICCINIT
80
mA
ICC
ICC
110
135
140
165
mA
mA
High Speed
Supply Current Suspend
Industrial Temperature Suspend
ICSBY
ICSBYI
350
350
700
900
µA
µA
Note 9.4 Output leakage is measured with the current pins in high impedance.
Note 9.5 See The USB 2.0 Specification, Chapter 7, for USB DC electrical characteristics
Note 9.6 RBIAS is a 3.3 V tolerant analog pin.
Note 9.7 Output current range is controlled by program software, software disables FET during short
circuit condition.
Note 9.8 The assignment of each Integrated Card Power FET to a designated Card Connector is
controlled by both firmware and the specific board implementation. Firmware will default to
the settings listed in Table 11.1, “USB2240/40i and USB2241/41i GPIO Usage,” on
page 49.
Note 9.9 The 3.3 V supply should be at least at 75% of its operating condition before the 1.8 V
supply is allowed to ramp up.
9.4
Capacitance
TA = 25°C; fc = 1 MHz; VDD, VDDP = 1.8 V
Table 9.1 Pin Capacitance
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
TEST CONDITION
Clock Input Capacitance
CXTAL
2
pF
All pins (except USB pins
and pins under test) are tied
to AC ground.
Input Capacitance
Output Capacitance
CIN
10
20
pF
pF
COUT
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9.5
Package Thermal Specifications
Table 9.2 36-Pin QFN Package Thermal Parameters
VELOCITY
(meters/sec)
PARAMETER
Thermal Resistance
SYMBOL
VALUE
UNIT
0
1
2
0
1
2
33.2
29
ΘJA
°C/W
26
Junction-to-Top-of-Package
2.6
2.6
2.6
ΨJT
°C/W
Note 9.10 Thermal parameters are measured or estimated for devices with the exposed pad soldered
to thermal vias in a multilayer 2S2P PCB per JESD51. Thermal resistance is measured
from the die to the ambient air.
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Chapter 10 AC Specifications
10.1
Oscillator/Crystal
Parallel Resonant, Fundamental Mode, 24 MHz 350 ppm.
XTAL1
(CS1 = CB1 + CXTAL1
)
C1
1 M
Crystal
CL
C0
C2
XTAL2
(CS2 = CB2 + CXTAL2
)
Figure 10.1 Typical Crystal Circuit
Table 10.1 Crystal Circuit Legend
SYMBOL
DESCRIPTION
IN ACCORDANCE WITH
C0
CL
CB
Crystal shunt capacitance
Crystal load capacitance
Crystal manufacturer’s specification (See Note 10.1)
OEM board design
Total board or trace
capacitance
CS
Stray capacitance
SMSC IC and OEM board design
SMSC IC
CXTAL
C1
XTAL pin input capacitance
Load capacitors installed on
OEM board
Calculated values based on Figure 10.2,
"Capacitance Formulas" (See Note 10.2)
C2
C1 = 2 x (CL – C0) – CS1
C2 = 2 x (CL – C0) – CS2
Figure 10.2 Capacitance Formulas
Note 10.1 C0 is usually included (subtracted by the crystal manufacturer) in the specification for CL
and should be set to ‘0’ for use in the calculation of the capacitance formulas in
Figure 10.2, "Capacitance Formulas". However, the OEM PCB itself may present a
parasitic capacitance between XTAL1 and XTAL2. For an accurate calculation of C1 and
C2, take the parasitic capacitance between traces XTAL1 and XTAL2 into account.
Note 10.2 Each of these capacitance values is typically approximately 18 pF.
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10.2
Ceramic Resonator
24 MHz 350 ppm
XTAL1
24 MHz
Ceramic
Resonator
1 M
XTAL2
Figure 10.3 Ceramic Resonator Usage with SMSC IC
10.3
External Clock
50% Duty cycle 10%, 24 MHz 350 ppm, Jitter < 100 ps rms.
The external clock is recommended to conform to the signaling level designated in the JESD76-2
specification on 1.8 V CMOS Logic. XTAL2 should be treated as a no connect or drive only a CMOS-
like buffer.
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Chapter 11 GPIO Usage
Table 11.1 USB2240/40i and USB2241/41i GPIO Usage
ACTIVE LEVEL SYMBOL DESCRIPTION AND NOTE
LED indicator
NAME
GPIO1
GPIO2
H
H
LED
RXD / SDA
Receive Port of Debugger / Serial
EEPROM Data
GPIO4
GPIO6
GPIO7
N/A
L
GPIO
Not used
SD_WP
SD Write Protect Detection
H
TXD / SCK / MS_SKT_SEL
Transmit Port of Debugger / Serial
EEPROM Clock / Memory Stick Socket
(1 = 8-bit; 0 = 4-bit)
GPIO10
GPIO12
GPIO14
L
L
L
CRD_PWR
MS_INS
Card Power Control
Memory Stick Card Insertion
xD_nCD
xD-Picture Card detect (USB2240/40i
only )
GPIO15
L
SD_nCD
Secure Digital card detect
Table 11.2 USB2242/42i GPIO Usage
SYMBOL
NAME
ACTIVE LEVEL
DESCRIPTION AND NOTE
GPIO1
GPIO2
H
H
LED
LED indicator
RXD / SDA
Receive Port of Debugger / Serial
EEPROM Data
GPIO4
GPIO6
GPIO7
N/A
L
GPIO
Not used
SD_WP
SD Write Protect Detection
H
TXD / SCK / MS_SKT_SEL
Transmit Port of Debugger / Serial
EEPROM Clock / Memory Stick Socket
(1 = 8-bit; 0 = 4-bit)
GPIO10
GPIO12
GPIO14
GPIO15
L
CRD_PWR
MS_INS
GPIO
Card Power Control
Memory Stick Card Insertion
Not used
L
N/A
N/A
GPIO
Not used
Table 11.3 USB2244/44i GPIO Usage
SYMBOL
NAME
ACTIVE LEVEL
DESCRIPTION AND NOTE
GPIO1
GPIO2
H
H
LED
LED indicator
RXD / SDA
Receive Port of Debugger / Serial
EEPROM Data
GPIO4
N/A
GPIO
Not used
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Table 11.3 USB2244/44i GPIO Usage (continued)
SD_WP SD Write Protect Detection
GPIO6
GPIO7
H
H
TXD / SCK / MS_SKT_SEL
Transmit Port of Debugger / Serial
EEPROM Clock / Memory Stick Socket
(1 = 8-bit; 0 = 4-bit)
GPIO10
GPIO12
GPIO14
GPIO15
L
CRD_PWR
GPIO
Card Power Control
Not used
N/A
N/A
L
GPIO
Not used
SD_nCD
Secure Digital card detect
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Chapter 12 Package Outline
Figure 12.1 USB224x 36-QFN, 6x6 mm Body, 0.5 mm Pitch
Table 12.1 Package Parameters
SYMBOL
MIN
NOMINAL
MAX
NOTE
REMARKS
A
A1
0.80
0
~
0.02
1.00
0.05
0.80
-
-
Overall Package Height
Standoff
A2
0.60
~
-
Mold Thickness
A3
0.20 REF
6.00
-
Leadframe Thickness
X/Y Overall Body Size
X/Y Mold Cap Size
X/Y Exposed Pad Size
Terminal Length
D/E
D1/E1
D2/E2
L
5.85
5.55
4.00
0.50
0.18
6.15
5.95
4.20
0.75
0.30
-
~
-
4.10
2
-
0.60
b
0.25
2
-
Terminal Width
e
0.50 BSC
Terminal Pitch
Note 12.1 All dimensions are in millimeters.
Note 12.2 Position tolerance of each terminal and exposed pad is ±0.05 mm at maximum material
condition.
Note 12.3 Dimension “b” applies to plated terminals and is measured between 0.15 mm and 0.30 mm
from the terminal tip.
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Note 12.4 Details of terminal #1 identifier are optional but must be located within the area indicated.
Note 12.5 Coplanarity zone applies to exposed pad and terminals.
Figure 12.2 Additional Package Information and Notes
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Datasheet Revision History
Table 12.2 Customer Revision History
SECTION/FIGURE/ENTRY
REVISION LEVEL & DATE
CORRECTION
Rev. 2.1
(02-07-13)
Document co-branded: Microchip logo added to cover; company disclaimer
modified.
Added the following to the ordering information: “Please contact your SMSC sales
representative for additional documentation related to this product such as
application notes, anomaly sheets, and design guidelines.”
Rev 2.1
(12-22-10)
Chapter 3, Figure 3.1, 3.2,
and 3.3
Upgraded to put the mux for the multiplexed
interface inside the part, put in a SPI interface for
outside access to the Program Memory I/O bus.
Rev 2.1
(11-23-10)
Chapter 6, Table 6.1
Removed “ It may not be used to drive any
external circuitry other than the crystal circuit” from
the XTAL2 description.
Rev. 2.1
Chapter 11, Table 11.3
Changed the active level from L to H for GPIO6.
(10-21-10)
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