TC9400EJD [MICROCHIP]
Voltage-to-Frequency/Frequency-to-Voltage Converters; 电压 - 频率/频率 - 电压转换器
| 型号： | TC9400EJD |
| 厂家： | 
MICROCHIP |
| 描述： | Voltage-to-Frequency/Frequency-to-Voltage Converters |
| 文件： | 总20页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC9400/9401/9402
Voltage-to-Frequency/Frequency-to-Voltage Converters
Features
General Description
The TC9400/TC9401/TC9402 are low cost voltage-to-
frequency (V/F) converters, utilizing low power CMOS
technology. The converters accept a variable analog
input signal and generate an output pulse train, whose
frequency is linearly proportional to the input voltage.
VOLTAGE-TO-FREQUENCY
• Choice of Linearity
- TC9401: 0.01%
- TC9400: 0.05%
The devices can also be used as highly accurate fre-
quency-to-voltage (F/V) converters, accepting virtually
any input frequency waveform and providing a linearly
proportional voltage output.
- TC9402: 0.25%
• DC to 100kHz (F/V) or 1Hz to 100kHz (V/F)
• Low Power Dissipation: 27mW (Typ.)
• Single/Dual Supply Operation
- +8V to +15V or ±4V to ±7.5V
• Gain Temperature Stability: ±25 ppm/°C (Typ.)
• Programmable Scale Factor
A complete V/F or F/V system only requires the addi-
tion of two capacitors, three resistors, and reference
voltage.
Package Type
FREQUENCY-TO-VOLTAGE
14-Pin Plastic DIP/CERDIP
• Operation: DC to 100kHz
• Choice of Linearity
- TC9401: 0.02%
I
BIAS
V
1
2
3
4
5
6
7
14
13
12
11
DD
ZERO ADJ
NC
- TC9400: 0.05%
- TC9402: 0.25%
I
AMPLIFIER OUT
IN
TC9400
TC9401
TC9402
• Programmable Scale Factor
THRESHOLD
DETECTOR
V
SS
Applications
V
OUT
GND
10 FREQ/2 OUT
REF
• µP Data Acquisition
9
8
OUTPUT COMMON
PULSE FREQ OUT
• 13-bit Analog-to-Digital Converters
• Analog Data Transmission and Recording
• Phase Locked Loops
V
REF
• Frequency Meters/Tachometer
• Motor Control
14-Pin SOIC
• FM Demodulation
I
BIAS
14
1
V
DD
Device Selection Table
ZERO ADJ
2
3
4
5
6
7
13
12
11
NC
I
IN
AMPLIFIER OUT
Part
Number
Linearity
(V/F)
Temperature
Range
Package
TC9400
TC9401
TC9402
V
THRESHOLD
DETECTOR
SS
TC9400COD
0.05%
14-Pin SOIC
(Narrow)
0°C to +70°C
V
OUT
GND
REF
FREQ/2 OUT
10
9
TC9400CPD
TC9400EJD
TC9401CPD
TC9401EJD
TC9402CPD
TC9402EJD
0.05%
0.05%
0.01%
0.01%
0.25%
0.25%
14-Pin PDIP
0°C to +70°C
OUTPUT COMMON
PULSE FREQ OUT
14-Pin CerDIP -40°C to +85°C
14-Pin PDIP 0°C to +70°C
14-Pin CerDIP -40°C to +85°C
V
REF
8
NC = No Internal Connection
14-Pin PDIP
0°C to +70°C
°C to +85°C
14-Pin CerDIP
2002 Microchip Technology Inc.
DS21483B-page 1
TC9400/9401/9402
Functional Block Diagram
Integrator
Integrator
Capacitor
Threshold
Detector
One
Shot
Op Amp
R
IN
Input
Voltage
I
IN
Pulse Output
÷2
Pulse/2 Output
Reference
Capacitor
TC9400
I
REF
Reference
Voltage
DS21483B-page 2
2002 Microchip Technology Inc.
TC9400/9401/9402
*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
V
– V
...........................................................+18V
DD
SS
I
........................................................................ 10mA
IN
V
V
OUTMAX – V
Common...................................... 23V
OUT
– V ..........................................................-1.5V
REF
SS
Storage Temperature Range.............. -65°C to +150°C
Operating Temperature Range:
C Device ........................................... 0°C to +70°C
E Device......................................... -40°C to +85°C
Package Dissipation (T ≤ 70°C):
A
8-Pin CerDIP..............................................800mW
8-Pin Plastic DIP ........................................730mW
8-Pin SOIC.................................................470mW
TC940X ELECTRICAL SPECIFICATIONS
Electrical Characteristics: VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100kΩ, Full Scale = 10kHz, unless otherwise
specified. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device).
Parameter
Min
Typ
Max Min
Typ
Max Min
Typ
Max
Units
Test Conditions
Voltage-to-Frequency
Accuracy
TC9400
TC9401
TC9402
Linearity 10kHz
—
0.01
0.05
0.25
—
—
0.004 0.01
—
—
0.05
0.25
0.5
%
Output Deviation from
Full Scale Straight Line Between
Normalized Zero and
Full Scale Input
Linearity 100kHz
—
0.1
0.04
0.08
0.25
%
Output Deviation from
Full Scale Straight Line Between
Normalized Zero Read-
ing and Full Scale Input
Gain Temperature
Drift (Note 1)
—
—
—
±25
±10
±10
±40
—
—
—
—
±25
±10
±10
±40
—
—
—
—
±50
±10
±20
±100
—
ppm/°C Variation in Gain A due
Full Scale to Temperature Change
Gain Variance
% of
Variation from Ideal
Nominal Accuracy
Zero Offset
±50
±50
±100
mV
Correction at Zero
(Note 2)
Adjust for Zero Output
when Input is Zero
Zero Temperature
Drift (Note 1)
—
±25
±50
—
±25
±50
—
±50
±100
µV/°C
Variation in Zero Offset
Due to Temperature
Change
Note 1: Full temperature range; not tested.
2: IIN = 0.
3: Full temperature range, IOUT = 10mA.
4: IOUT = 10µA.
5: Threshold Detect = 5V, Amp Out = 0V, full temperature range.
6: 10Hz to 100kHz; not tested.
7: 5µsec minimum positive pulse width and 0.5µsec minimum negative pulse width.
8: tR = tF = 20nsec.
9: RL ≥ 2kΩ, tested @ 10kΩ.
10: Full temperature range, VIN = -0.1V.
2002 Microchip Technology Inc.
DS21483B-page 3
TC9400/9401/9402
TC940X ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100kΩ, Full Scale = 10kHz, unless otherwise
specified. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device).
Parameter
Min
Typ
Max Min
Typ
Max Min
Typ
Max
Units
Test Conditions
Analog Input
IIN Full Scale
—
10
—
—
10
—
—
10
—
µA
Full Scale Analog Input
Current to achieve
Specified Accuracy
IIN Over Range
Response Time
—
—
—
2
50
—
—
—
—
2
50
—
—
—
—
2
50
—
µA
Over Range Current
Cycle
Settling Time to 0.1%
Full Scale
Digital Section
TC9400
TC9401
TC9402
VSAT @ IOL = 10mA
—
—
0.2
0.4
18
—
—
0.2
0.4
18
—
—
0.2
0.4
18
V
V
Logic "0" Output
Voltage (Note 3)
VOUTMAX – VOUT
Common (Note 4)
—
3
—
3
—
3
Voltage Range
Between Output and
Common
Pulse Frequency
Output Width
—
—
—
—
—
—
µsec
Frequency-to-Voltage
Supply Current
IDD Quiescent
(Note 5)
—
1.5
6
—
—
1.5
6
—
—
3
10
mA
mA
Current Required from
Positive Supply during
Operation
ISS Quiescent
(Note 5)
—
-1.5
-6
-1.5
-6
-3
-10
Current Required from
Negative Supply during
Operation
VDD Supply
VSS Supply
4
—
—
7.5
4
—
—
7.5
4
—
—
7.5
V
V
Operating Range of
Positive Supply
-4
-7.5
-4
-7.5
-4
-7.5
Operating Range of
Negative Supply
Reference Voltage
VREF – VSS
-2.5
—
—
—
-2.5
—
—
—
-2.5
—
—
—
V
Range of Voltage
Reference Input
Accuracy
Non-Linearity
0.02
0.05
0.01
0.02
0.05
0.25
%
Deviation from ideal
(Note 10)
Full Scale Transfer Function as a
Percentage Full Scale
Voltage
Input Frequency
Range
10
—
100k
10
—
100k
10
—
100k
Hz
Frequency Range for
Specified Non-Linearity
(Notes 7 and 8)
Note 1: Full temperature range; not tested.
2: IIN = 0.
3: Full temperature range, IOUT = 10mA.
4: IOUT = 10µA.
5: Threshold Detect = 5V, Amp Out = 0V, full temperature range.
6: 10Hz to 100kHz; not tested.
7: 5µsec minimum positive pulse width and 0.5µsec minimum negative pulse width.
8: tR = tF = 20nsec.
9: RL ≥ 2kΩ, tested @ 10kΩ.
10: Full temperature range, VIN = -0.1V.
DS21483B-page 4
2002 Microchip Technology Inc.
TC9400/9401/9402
TC940X ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100kΩ, Full Scale = 10kHz, unless otherwise
specified. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device).
Parameter
Min
Typ
Max Min
Typ
Max Min
Typ
Max
Units
Test Conditions
Frequency Input
Positive Excursion
0.4
—
VDD
0.4
-0.4
—
—
VDD
0.4
-0.4
—
—
VDD
V
Voltage Required to
Turn Threshold
Detector On
Negative Excursion
-0.4
—
-2
—
5
-2
—
5
-2
—
—
V
Voltage Required to
Turn Threshold
Detector Off
Minimum Positive
Pulse Width
(Note 8)
5
—
—
µsec
µsec
Time between
Threshold Crossings
Minimum Negative
Pulse Width
(Note 8)
—
0.5
—
—
0.5
—
—
0.5
Time Between
Threshold Crossings
Input Impedance
—
—
10
—
—
—
—
10
—
—
—
10
—
MΩ
Analog Outputs
TC9400
TC9401
VDD – 1
TC9402
VDD – 1
Output Voltage
(Note 9)
V
DD – 1
—
2
V
Voltage Range of Op
Amp Output for Speci-
fied Non-Linearity
Output Loading
2
—
—
2
—
—
—
—
kΩ
Resistive Loading at
Output of Op Amp
Supply Current
TC9400
TC9401
TC9402
IDD Quiescent
(Note 10)
—
—
1.5
6
—
1.5
6
—
—
3
10
mA
mA
Current Required from
Positive Supply During
Operation
ISS Quiescent
-1.5
-6
-1.5
-6
-3
-10
Current Required from
Negative Supply
(Note 10)
During Operation
VDD Supply
VSS Supply
4
—
—
7.5
4
—
—
7.5
4
—
—
7.5
V
V
Operating Range of
Positive Supply
-4
-7.5
-4
-7.5
-4
-7.5
Operating Range of
Negative Supply
Reference Voltage
VREF – VSS
-2.5
—
—
-2.5
—
—
-2.5
—
—
V
Range of Voltage
Reference Input
Note 1: Full temperature range; not tested.
2: IIN = 0.
3: Full temperature range, IOUT = 10mA.
4: IOUT = 10µA.
5: Threshold Detect = 5V, Amp Out = 0V, full temperature range.
6: 10Hz to 100kHz; not tested.
7: 5µsec minimum positive pulse width and 0.5µsec minimum negative pulse width.
8: tR = tF = 20nsec.
9: RL ≥ 2kΩ, tested @ 10kΩ.
10: Full temperature range, VIN = -0.1V.
2002 Microchip Technology Inc.
DS21483B-page 5
TC9400/9401/9402
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Pin No.
14-Pin PDIP/CERDIP
14-Pin SOIC (Narrow)
Symbol
Description
1
2
3
4
5
6
7
8
IBIAS
ZERO ADJ
IIN
This pin sets bias current in the TC9400. Connect to VSS through a 100kΩ resistor.
Low frequency adjustment input.
Input current connection for the V/F converter.
Negative power supply voltage connection, typically -5V.
Reference capacitor connection.
VSS
VREF OUT
GND
Analog ground.
VREF
Voltage reference input, typically -5V.
PULSE FREQ
OUT
Frequency output. This open drain output will pulse LOW each time the Freq.
Threshold Detector limit is reached. The pulse rate is proportional to input voltage.
9
OUTPUT
Source connection for the open drain output FETs.
COMMON
10
11
FREQ/2 OUT
This open drain output is a square wave at one-half the frequency of the pulse output
(Pin 8). Output transitions of this pin occur on the rising edge of Pin 8.
THRESHOLD
DETECTOR
Input to the Threshold Detector. This pin is the frequency input during F/V operation.
12
13
14
AMPLIFIER OUT Output of the integrator amplifier.
NC
No internal connection.
VDD
Positive power supply connection, typically +5V.
DS21483B-page 6
2002 Microchip Technology Inc.
TC9400/9401/9402
input is balanced out by fixed charges from the refer-
ence voltage. As the input voltage is increased, the
number of reference pulses required to maintain bal-
ance increases, which causes the output frequency to
also increase. Since each charge increment is fixed, the
increase in frequency with voltage is linear. In addition,
the accuracy of the output pulse width does not directly
affect the linearity of the V/F. The pulse must simply be
long enough for full charge transfer to take place.
3.0
3.1
DETAILED DESCRIPTION
Voltage-to-Frequency (V/F) Circuit
Description
The TC9400 V/F converter operates on the principal of
charge balancing. The operation of the TC9400 is eas-
ily understood by referring to Figure 3-1. The input volt-
age (V ) is converted to a current (I ) by the input
IN
IN
resistor. This current is then converted to a charge on
the integrating capacitor and shows up as a linearly
decreasing voltage at the output of the Op Amp. The
lower limit of the output swing is set by the threshold
detector, which causes the reference voltage to be
applied to the reference capacitor for a time period long
enough to charge the capacitor to the reference volt-
age. This action reduces the charge on the integrating
The TC9400 contains a "self-start" circuit to ensure the
V/F converter always operates properly when power is
first applied. In the event that, during power-on, the Op
Amp output is below the threshold and C
is already
REF
charged, a positive voltage step will not occur. The Op
Amp output will continue to decrease until it crosses the
-3.0V threshold of the "self-start" comparator. When
this happens, an internal resistor is connected to the
Op Amp input, which forces the output to go positive
until the TC9400 is in its Normal Operating mode.
capacitor by a fixed amount (q = C
x V
), causing
REF
REF
the Op Amp output to step up a finite amount.
At the end of the charging period, C is shorted out.
REF
The TC9400 utilizes low power CMOS processing for
low input bias and offset currents, with very low power
dissipation. The open drain N-channel output FETs
provide high voltage and high current sink capability.
This dissipates the charge stored on the reference
capacitor, so that when the output again crosses zero,
the system is ready to recycle. In this manner, the con-
tinued discharging of the integrating capacitor by the
FIGURE 3-1:
10Hz TO 10kHz V/F CONVERTER
+5V
+
5V
14
V
R
10kΩ
L
DD
F
Threshold
OUT
8
11
Detect
3µsec
Delay
+
5V
Threshold
Detector
R
10kΩ
L
F
/2
OUT
10
9
Self-
Start
÷2
-3V
12 AMP OUT
Output
Common
V
OUT
REF
5
20kΩ
C
INT
820pF
TC9400
TC9401
TC9402
C
180pF
REF
12pF
R
IN
1MΩ
INPUT
60pF
I
IN
3
V
IN
–
+5V
Op Amp
+
Zero Adjust
0V –10V
50kΩ
510kΩ
2
V
V
7
I
GND
6
SS
REF
BIAS
-5V
Offset
1
4
10kΩ
R
Adjust
BIAS
100kΩ
Reference Voltage
(Typically -5V)
-5V
2002 Microchip Technology Inc.
DS21483B-page 7
TC9400/9401/9402
3.2
Voltage-to-Time Measurements
4.0
4.1
PIN FUNCTIONS
The TC9400 output can be measured in the time
domain as well as the frequency domain. Some micro-
computers, for example, have extensive timing capabil-
ity, but limited counter capability. Also, the response
time of a time domain measurement is only the period
between two output pulses, while the frequency mea-
surement must accumulate pulses during the entire
counter time-base period.
Threshold Detector Input
In the V/F mode, this input is connected to the AMPLI-
FIER OUT output (Pin 12) and triggers a 3µsec pulse
when the input voltage passes through its threshold. In
the F/V mode, the input frequency is applied to this
input.
The nominal threshold of the detector is half way
Time measurements can be made from either the
TC9400's PULSE FREQ OUT output, or from the
FREQ/2 OUT output. The FREQ/2 OUT output
changes state on the rising edge of PULSE FREQ
OUT, so FREQ/2 OUT is a symmetrical square wave at
one-half the pulse output frequency. Timing measure-
ments can, therefore, be made between successive
PULSE FREQ OUT pulses, or while FREQ/2 OUT is
high (or low).
between the power supplies, or (V + V )/2 ±400mV.
DD
SS
The TC9400's charge balancing V/F technique is not
dependent on precision comparator threshold,
a
because the threshold only sets the lower limit of the
Op Amp output. The Op Amp's peak-to-peak output
swing, which determines the frequency, is only
influenced by external capacitors and by V
.
REF
4.2
Pulse Freq Out
This output is an open drain N-channel FET, which pro-
vides a pulse waveform whose frequency is propor-
tional to the input voltage. This output requires a pull-
up resistor and interfaces directly with MOS, CMOS,
and TTL logic (see Figure 4-1).
FIGURE 4-1:
OUTPUT WAVEFORMS
3µsec
Typ.
F
OUT
1/f
F /2
OUT
C
REF
C
INT
V
REF
0V
Amp Out
Notes: 1. To adjust F
, set V = 10mV and adjust the 50kΩ offset for 10Hz output.
IN
MIN
2. To adjust F
MAX
3. To increase F
, set V = 10V and adjust R or V
for 10kHz output.
IN
MAX to 100kHz, change C
IN
REF
to 2pF and C to 75pF.
INT
OUT
REF
4. For high performance applications, use high stability components for R , C (metal film
, V
IN REF REF
resistors and glass capacitors). Also, separate output ground (Pin 9) from input ground (Pin 6).
DS21483B-page 8
2002 Microchip Technology Inc.
TC9400/9401/9402
4.3
Freq/2 Out
4.8
IIN
This output is an open drain N-channel FET, which pro-
vides a square wave one-half the frequency of the
pulse frequency output. The FREQ/2 OUT output will
change state on the rising edge of PULSE FREQ OUT.
This output requires a pull-up resistor and interfaces
directly with MOS, CMOS, and TTL logic.
The inverting input of the operational amplifier and the
summing junction when connected in the V/F mode. An
input current of 10µA is specified, but an over range
current up to 50µA can be used without detrimental
effect to the circuit operation. I connects the summing
IN
junction of an operational amplifier. Voltage sources
cannot be attached directly, but must be buffered by
external resistors.
4.4
Output Common
The sources of both the FREQ/2 OUT and the PULSE
FREQ OUT are connected to this pin. An output level
4.9
VREF
swing from the drain voltage to ground, or to the V
A reference voltage from either a precision source, or
SS
supply, may be obtained by connecting this pin to the
appropriate point.
the V supply is applied to this pin. Accuracy of the
TC9400 is dependent on the voltage regulation and
temperature characteristics of the reference circuitry.
SS
4.5
RBIAS
Since the TC9400 is a charge balancing V/F converter,
the reference current will be equal to the input current.
For this reason, the DC impedance of the reference
voltage source must be kept low enough to prevent lin-
earity errors. For linearity of 0.01%, a reference imped-
ance of 200W or less is recommended. A 0.1µF bypass
An external resistor, connected to V , sets the bias
point for the TC9400. Specifications for the TC9400 are
based on R
noted.
SS
= 100kΩ ±10%, unless otherwise
BIAS
Increasing the maximum frequency of the TC9400
beyond 100kHz is limited by the pulse width of the
capacitor should be connected from V
to ground.
REF
pulse output (typically 3µsec). Reducing R
decrease the pulse width and increase the maximum
operating frequency, but linearity errors will also
will
BIAS
4.10 VREF Out
The charging current for C
is supplied through this
REF
increase. R
can be reduced to 20kΩ, which will
pin. When the Op Amp output reaches the threshold
level, this pin is internally connected to the reference
BIAS
typically produce a maximum full scale frequency of
500kHz.
voltage and a charge, equal to V
x C
, is removed
REF
REF
from the integrator capacitor. After about 3µsec, this pin
is internally connected to the summing junction of the
4.6
Amplifier Out
Op Amp to discharge C . Break-before-make switch-
ing ensures that the reference voltage is not directly
applied to the summing junction.
REF
This pin is the output stage of the operational amplifier.
During V/F operation, a negative going ramp signal is
available at this pin. In the F/V mode, a voltage
proportional to the frequency input is generated.
4.7
Zero Adjust
This pin is the non-inverting input of the operational
amplifier. The low frequency set point is determined by
adjusting the voltage at this pin.
2002 Microchip Technology Inc.
DS21483B-page 9
TC9400/9401/9402
FIGURE 5-1:
RECOMMENDED
VS. V
5.0
VOLTAGE-TO-FREQUENCY
(V/F) CONVERTER DESIGN
INFORMATION
C
REF
REF
500
400
300
V
V
= +5V
= -5V
= 1MΩ
= +10V
DD
SS
R
IN
IN
A
5.1
Input/Output Relationships
V
T
= +25°C
The output frequency (F
input voltage (V ) by the transfer equation:
) is related to the analog
OUT
10kHz
IN
EQUATION 5-1:
200
100
V
R
1
)(V
IN
, x
Frequency Out =
(V
)
REF
REF
IN
100kHz
-2 -3 -4
0
-5 -6
-7
-1
5.2
External Component Selection
V
(V)
REF
5.2.1
R
IN
5.2.4
V
, V
DD
SS
The value of this component is chosen to give a full
Power supplies of ±5V are recommended. For high
accuracy requirements, 0.05% line and load regulation
and 0.1µF disc decoupling capacitors, located near the
pins, are recommended.
scale input current of approximately 10µA:
EQUATION 5-2:
FULLSCALE
V
IN
R
≅
IN
10µA
5.3
Adjustment Procedure
Figure 3-1 shows a circuit for trimming the zero loca-
tion. Full scale may be trimmed by adjusting R , V
EQUATION 5-3:
,
IN REF
or C . Recommended procedure for a 10kHz full
scale frequency is as follows:
REF
10V
R
≅
= 1MΩ
IN
10µA
1. Set V to 10mV and trim the zero adjust circuit
IN
to obtain a 10Hz output frequency.
Note that the value is an approximation and the exact
relationship is defined by the transfer equation. In prac-
2. Set V to 10V and trim either R , V
, or C
REF
IN
IN REF
tice, the value of R typically would be trimmed to
to obtain a 10kHz output frequency.
IN
obtain full scale frequency at V
full scale (see
IN
If adjustments are performed in this order, there should
be no interaction and they should not have to be
repeated.
Section 5.3, Adjustment Procedure). Metal film resis-
tors with 1% tolerance or better are recommended for
high accuracy applications because of their thermal
stability and low noise generation.
5.4
Improved Single Supply V/F
Converter Operation
5.2.2
C
INT
A TC9400, which operates from a single 12 to 15V vari-
able power source, is shown in Figure 5-2. This circuit
uses two Zener diodes to set stable biasing levels for
the TC9400. The Zener diodes also provide the refer-
ence voltage, so the output impedance and tempera-
ture coefficient of the Zeners will directly affect power
supply rejection and temperature performance. Full
scale adjustment is accomplished by trimming the input
current. Trimming the reference voltage is not recom-
mended for high accuracy applications unless an
Op Amp is used as a buffer, because the TC9400
requires a low impedance reference (see Section 4.9,
The exact value is not critical but is related to C
the relationship:
by
REF
3C
≤ C
≤ 10C
INT REF
REF
Improved stability and linearity are obtained when
≤ 4C . Low leakage types are recommended,
C
INT
REF
although mica and ceramic devices can be used in
applications where their temperature limits are not
exceeded. Locate as close as possible to Pins 12
and 13.
5.2.3
C
REF
V
pin description, for more information).
REF
The exact value is not critical and may be used to trim
the full scale frequency (see Section 7.1, Input/Output
Relationships). Glass film or air trimmer capacitors are
recommended because of their stability and low leak-
age. Locate as close as possible to Pins 5 and 3 (see
Figure 5-1).
The circuit of Figure 5-2 will directly interface with
CMOS logic operating at 12V to 15V. TTL or 5V CMOS
logic can be accommodated by connecting the output
pull-up resistors to the +5V supply. An optoisolator can
also be used if an isolated output is required; also, see
Figure 5-3.
DS21483B-page 10
2002 Microchip Technology Inc.
TC9400/9401/9402
FIGURE 5-2:
VOLTAGE TO FREQUENCY
+12 to +15V
1.2k
14
V
DD
1µF
Threshold
Detect
11
12
5
R
910k
R
4
100k
1
C
INT
10k
10k
Amp Out
D
5.1VZ
2
C
REF
C
REF
R
3
TC9400
Gain
3
2
6
I
8
IN
F
OUT
Zero Adjust
100k
10
9
Output
Frequency
GND
F
/2
OUT
R
910k
R
5
2
D
1
5.1VZ
91k
0.1µ
Output
Common
7
1
V
REF
Rp
I
BIAS
Offset
20k
V
100k
SS
Digital
Ground
Input
Voltage
4
(0 to 10V)
Analog Ground
Component Selection
CREF
CINT
F/S FREQ.
2200pF 4700pF
1kHz
180pF
27pF
470pF
75pF
10kHz
100kHz
FIGURE 5-3:
FIXED VOLTAGE - SINGLE SUPPLY OPERATION
V+ = 8V to 15V (Fixed)
R
2
14
10kΩ
V
2
0.9
1
2
6
5V
R
8
F
OUT
0.01
µF
8.2
kΩ
Gain
Adjust
TC9400
10kΩ
7
10
F
/2
V
2
kΩ
OUT
REF
11
0.01
µF
Offset
Adjust
0.2
1
12
5
R
R
1MΩ
820
pF
IN
180
pF
3
I
IN
V
IN
0V–10V
I
1
4
9
IN
100kΩ
R
R
2
1
V+
1
F
= I
IN
OUT
–
(V
V ) (C
)
REF
10V
1MΩ 10kΩ
2
7
12V 1.4MΩ 14kΩ
15V
2MΩ 20kΩ
(V – V )
IN
(V+ – V )
2
2
+
=
I
IN
R
(0.9R + 0.2R )
1 1
IN
2002 Microchip Technology Inc.
DS21483B-page 11
TC9400/9401/9402
C
can be increased to lower the ripple. Values of 1µF
6.0
FREQUENCY-TO-VOLTAGE
(F/V) CIRCUIT DESCRIPTION
INT
to 100µF are perfectly acceptable for low frequencies.
When the TC9400 is used in the Single Supply mode,
When used as an F/V converter, the TC9400 generates
an output voltage linearly proportional to the input
frequency waveform.
V
is defined as the voltage difference between Pin 7
REF
and Pin 2.
7.2
Input Voltage Levels
Each zero crossing at the threshold detector's input
causes a precise amount of charge (q = C
∞ V
)
REF
REF
The input frequency is applied to the Threshold Detec-
tor input (Pin 11). As discussed in the V/F circuit section
of this data sheet, the threshold of Pin 11 is approxi-
to be dispensed into the Op Amp's summing junction.
This charge, in turn, flows through the feedback resis-
tor, generating voltage pulses at the output of the Op
mately (V
+ V )/2 ±400mV. Pin 11's input voltage
DD
SS
Amp. A capacitor (C ) across R
averages these
INT
INT
range extends from V to about 2.5V below the thresh-
DD
pulses into a DC voltage, which is linearly proportional
to the input frequency.
old. If the voltage on Pin 11 goes more than 2.5 volts
below the threshold, the V/F mode start-up comparator
will turn on and corrupt the output voltage. The Thresh-
old Detector input has about 200mV of hysteresis.
7.0
7.1
F/V CONVERTER DESIGN
INFORMATION
In ±5V applications, the input voltage levels for the
TC9400 are ±400mV, minimum. If the frequency
source being measured is unipolar, such as TTL or
CMOS operating from a +5V source, then an AC cou-
pled level shifter should be used. One such circuit is
shown in Figure 7-1(a).
Input/Output Relationships
The output voltage is related to the input frequency
(F ) by the transfer equation:
IN
The level shifter circuit in Figure 7-1(b) can be used in
single supply F/V applications. The resistor divider
ensures that the input threshold will track the supply
voltages. The diode clamp prevents the input from
going far enough in the negative direction to turn on the
start-up comparator. The diode's forward voltage
decreases by 2.1mV/°C, so for high ambient tempera-
ture operation, two diodes in series are recommended;
also, see Figure 7-2.
EQUATION 7-1:
V
= [V
C R ] F
REF REF INT IN
OUT
The response time to a change in F is equal to (R
IN
INT
C
). The amount of ripple on V
is inversely
INT
OUT
proportional to C
and the input frequency.
INT
FIGURE 7-1:
FREQUENCY INPUT LEVEL SHIFTER
+8V to +5V
14
+5V
14
V
V
DD
DD
10k
TC9400
TC9400
0.01µF
33k
0.01µF
33k
11
Frequency
Input
11
Frequency
Input
DET
DET
IN914
+5V
0V
1.0M
+5V
0V
IN914 1.0M
V
GND
6
V
SS
SS
10k
0.1µF
4
4
-5V
(b) Single Supply
(a) 5V Supply
DS21483B-page 12
2002 Microchip Technology Inc.
TC9400/9401/9402
FIGURE 7-2:
F/V SINGLE SUPPLY F/V CONVERTER
V+ = 10V to 15V
14
10k
V
DD
6
GND
.01µF
TC9400
6.2V
10k
5
3
V
OUT
REF
500k
2
Zero
Adjust
47pF
100k
V+
I
IN
Offset
Adjust
.001µF
1M
12
6
Amp Out
1.0k
0.01µF
33k
Frequency
11
V
OUT
DET
Input
GND
V
IN914
I
V
BIAS
1.0M
REF
7
SS
4
0.1µF
1.0k
100k
Note: The output is referenced to Pin 6, which is at 6.2V (Vz). For frequency meter applications,
a 1mA meter with a series scaling resistor can be placed across Pins 6 and 12.
FIGURE 7-3:
F/V DIGITAL OUTPUTS
7.3
Input Buffer
F
and F
/2 are not used in the F/V mode. How-
OUT
OUT
5.0µsec
Min
0.5µsec
ever, these outputs may be useful for some applica-
tions, such as a buffer to feed additional circuitry. Then,
F
Min
Input
will follow the input frequency waveform, except
OUT
that F
will go high 3µsec after F goes high;
OUT
IN
F
/2 will be square wave with a frequency of
F
OUT
OUT
one-half F
.
OUT
Delay = 3µsec
If these outputs are not used, Pins 8, 9 and 10 should be
connected to ground (see Figure 7-3 and Figure 7-4).
F
OUT
/2
2002 Microchip Technology Inc.
DS21483B-page 13
TC9400/9401/9402
FIGURE 7-4:
DC - 10kHz CONVERTER
+5V
14
V+
V+
V
DD
*
F
/2
OUT
10
9
TC9400A
TC9401A
TC9402A
42
Output
Common
See
*
Figure 7-1:
Threshold
Detect
*
"Frequency
Input Level
Shifter"
F
OUT
8
11
3µsec
Delay
F
IN
*Optional/If
Buffer is Needed
Threshold
Detector
V
REF
OUT
5
C
REF
56pF
12pF
60pF
Offset
Adjust
I
IN
3
R
INT
C
INT
1000pF
+
+5V
100kΩ
2.2kΩ
Amp
Out
1MΩ
–
12
Op
Amp
+
V
OUT
Zero Adjust
2
2kΩ
I
V
V
7
BIAS
SS
4
REF
GND
6
1
10kΩ
V
REF
(Typically -5V)
-5V
FIGURE 7-5:
RIPPLE FILTER
7.4
Output Filtering
The output of the TC9400 has a sawtooth ripple super-
imposed on a DC level. The ripple will be rejected if the
TC9400 output is converted to a digital value by an inte-
grating analog-to-digital converter, such as the TC7107
or TC7109. The ripple can also be reduced by increas-
ing the value of the integrating capacitor, although this
will reduce the response time of the F/V converter.
5
3
V
OUT
REF
47pF
TC9400
I
IN
.001µF
1M
200
12
AMP OUT
The sawtooth ripple on the output of an F/V can be
eliminated without affecting the F/V's response time by
using the circuit in Figure 7-5. The circuit is a capaci-
tance multiplier, where the output coupling capacitor is
multiplied by the AC gain of the Op Amp. A moderately
fast Op Amp, such as the TL071, should be used.
1M
0.1µF
.01µF
GND
+5
6
V
OUT
7
4
2
–
6
TL071
3
+
1M
-5
DS21483B-page 14
2002 Microchip Technology Inc.
TC9400/9401/9402
In some cases, however, the TC9400 output must be
zero at power-on without a frequency input. In such
8.0
F/V POWER-ON RESET
In F/V mode, the TC9400 output voltage will occasion-
ally be at its maximum value when power is first
applied. This condition remains until the first pulse is
applied to F . In most frequency measurement appli-
cations, this is not a problem because proper operation
begins as soon as the frequency input is applied.
cases, a capacitor connected from Pin 11 to V
will
DD
usually be sufficient to pulse the TC9400 and provide a
Power-on Reset (see Figure 8-1 (a) and (b)). Where
predictable power-on operation is critical, a more com-
plicated circuit, such as Figure 8-1 (b), may be
required.
IN
FIGURE 8-1:
POWER-ON OPERATION/RESET
(a)
(b)
V
DD
V
DD
14
16
5
2
1
1000pF
V
B
R
C
CC
3
4
CLRA
1kΩ
F
IN
Threshold
Detector
11
100kΩ
1µF
CD4538
6
To TC9400
Q
A
V
SS
F
IN
TC9400
8
2002 Microchip Technology Inc.
DS21483B-page 15
TC9400/9401/9402
9.0
9.1
PACKAGE INFORMATION
Package Marking Information
Package marking data is not available at this time.
9.2
Taping Form
Component Taping Orientation for 14-Pin SOIC (Narrow) Devices
User Direction of Feed
PIN 1
W
P
Standard Reel Component Orientation
for TR Suffix Device
Carrier Tape, Reel Size, and Number of Components Per Reel
Package
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
14-Pin SOIC (N)
12 mm
8 mm
2500
13 in
9.3
Package Dimensions
14-Pin CDIP (Narrow)
PIN 1
.300 (7.62)
.230 (5.84)
.098 (2.49) MAX.
.030 (0.76) MIN.
.780 (19.81)
.740 (18.80)
.320 (8.13)
.290 (7.37)
.040 (1.02)
.020 (0.51)
.200 (5.08)
.160 (4.06)
.015 (0.38)
.008 (0.20)
3° MIN.
.200 (5.08)
.125 (3.18)
.150 (3.81)
MIN.
.400 (10.16)
.320 (8.13)
.020 (0.51)
.016 (0.41)
.110 (2.79)
.090 (2.29)
.065 (1.65)
.045 (1.14)
Dimensions: inches (mm)
DS21483B-page 16
2002 Microchip Technology Inc.
TC9400/9401/9402
9.3
Package Dimensions (Continued)
14-Pin PDIP (Narrow)
PIN 1
.260 (6.60)
.240 (6.10)
.310 (7.87)
.290 (7.37)
.770 (19.56)
.745 (18.92)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.020 (0.51)
.015 (0.38)
3° MIN.
.150 (3.81)
.115 (2.92)
.008 (0.20)
.400 (10.16)
.310 (7.87)
.110 (2.79) .070 (1.78)
.090 (2.29) .045 (1.14)
.022 (0.56)
.015 (0.38)
Dimensions: inches (mm)
14-Pin SOIC (Narrow)
PIN 1
.157 (3.99) .244 (6.20)
.150 (3.81) .228 (5.79)
.050 (1.27) TYP.
.344 (8.74)
.337 (8.56)
.069 (1.75)
.053 (1.35)
.010 (0.25)
.007 (0.18)
8° MAX.
.010 (0.25)
.004 (0.10)
.050 (1.27)
.016 (0.40)
.018 (0.46)
.014 (0.36)
Dimensions: inches (mm)
2002 Microchip Technology Inc.
DS21483B-page 17
TC9400/9401/9402
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
DS21483B-page 18
2002 Microchip Technology Inc.
TC9400/9401/9402
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21483B-page 19
WORLDWIDE SALES AND SERVICE
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03/01/02
DS21483B-page 20
2002 Microchip Technology Inc.
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