TC9401E/OD_技术文档

TC9400/9401/9402

Voltage-to-Frequency/Frequency-to-Voltage Converters

Features:

General Description:

The TC9400/TC9401/TC9402 are low-cost Voltage-to-

Frequency (V/F) converters, utilizing low-power CMOS

technology. The converters accept a variable analog

input signal and generate an output pulse train, whose

frequency is linearly proportional to the input voltage.

VOLTAGE-TO-FREQUENCY

• Choice of Linearity:

- TC9401: 0.01%

- TC9400: 0.05%

- TC9402: 0.25%

The devices can also be used as highly accurate Fre-

quency-to-Voltage (F/V) converters, accepting virtually

any input frequency waveform and providing a linearly

proportional voltage output.

• DC to 100 kHz (F/V) or 1 Hz to 100 kHz (V/F)

• Low Power Dissipation: 27 mW (Typ.)

• Single/Dual Supply Operation:

- +8V to +15V or ±4V to ±7.5V

• Gain Temperature Stability: ±25 ppm/°C (Typ.)

• Programmable Scale Factor

A complete V/F or F/V system only requires the addi-

tion of two capacitors, three resistors, and reference

voltage.

Package Type

FREQUENCY-TO-VOLTAGE

• Operation: DC to 100 kHz

• Choice of Linearity:

- TC9401: 0.02%

14-Pin Plastic DIP/CERDIP

I

BIAS

V

1

2

3

4

5

6

7

14

13

12

11

DD

- TC9400: 0.05%

ZERO ADJ

NC

- TC9402: 0.25%

I

AMPLIFIER OUT

IN

• Programmable Scale Factor

TC9400

TC9401

TC9402

THRESHOLD

DETECTOR

V

SS

Applications:

V

OUT

GND

10 FREQ/2 OUT

REF

• μP Data Acquisition

9

8

OUTPUT COMMON

PULSE FREQ OUT

• 13-bit Analog-to-Digital Converters

• Analog Data Transmission and Recording

• Phase Locked Loops

V

REF

• Frequency Meters/Tachometer

• Motor Control

14-Pin SOIC

• FM Demodulation

I

BIAS

14

1

V

DD

Device Selection Table

ZERO ADJ

2

3

4

5

6

7

13

12

11

NC

Part

Number

Linearity

(V/F)

Temperature

Range

I

IN

Package

AMPLIFIER OUT

TC9400

TC9401

TC9402

V

THRESHOLD

DETECTOR

SS

TC9400COD

0.05%

14-Pin SOIC

(Narrow)

0°C to +70°C

V

OUT

GND

REF

FREQ/2 OUT

10

9

TC9400CPD

TC9400EJD

TC9401CPD

TC9401EJD

TC9402CPD

TC9402EJD

0.05%

0.01%

0.25%

14-Pin PDIP

0°C to +70°C

OUTPUT COMMON

PULSE FREQ OUT

14-Pin CerDIP -40°C to +85°C

14-Pin PDIP 0°C to +70°C

14-Pin CerDIP -40°C to +85°C

V

REF

8

NC = No Internal Connection

14-Pin PDIP

0°C to +70°C

°C to +85°C

14-Pin CerDIP

DS21483C-page 1

TC9400/9401/9402

Functional Block Diagram

Integrator

Capacitor

Integrator

Op Amp

Threshold

Detector

One

Shot

R

IN

Input

Voltage

I

IN

Pulse Output

÷2

Pulse/2 Output

Reference

Capacitor

TC9400

I

REF

Reference

Voltage

DS21483C-page 2

TC9400/9401/9402

*Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. These are stress ratings only and functional

operation of the device at these or any other conditions

above those indicated in the operation sections of the

specifications is not implied. Exposure to Absolute

Maximum Rating conditions for extended periods may

affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings*

V_DD– V_SS...........................................................+18V

I_IN.......................................................................10 mA

V_OUTMAX– V_OUTCommon......................................23V

V_REF– V_SS..........................................................-1.5V

Storage Temperature Range..............-65°C to +150°C

Operating Temperature Range:

C Device ........................................... 0°C to +70°C

E Device.........................................-40°C to +85°C

Package Dissipation (T_A≤ 70°C):

8-Pin CerDIP.............................................800 mW

8-Pin Plastic DIP.......................................730 mW

8-Pin SOIC................................................470 mW

TABLE 1-1:

TC940X ELECTRICAL SPECIFICATIONS

Electrical Characteristics: V = +5V, V = -5V, V

= 0V, V

= -5V, R

= 100 kΩ, Full Scale = 10 kHz, unless otherwise

BIAS

DD

SS

GND

REF

specified. T = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device).

A

Parameter

Min

Typ

Max Min

Typ

Max Min

Typ

Max

Units

Test Conditions

Voltage-to-Frequency

Accuracy

TC9400

TC9401

TC9402

Linearity 10 kHz

—

0.01

0.05

0.25

—

0.004 0.01

—

0.05

0.25

0.5

%

Output Deviation from

Full Scale Straight Line Between

Normalized Zero and

Full Scale Input

Linearity 100 kHz

—

0.1

0.04

0.08

0.25

%

Output Deviation from

Full Scale Straight Line Between

Normalized Zero Read-

ing and Full Scale Input

Gain Temperature

Drift (Note 1)

—

±25

±10

±40

—

±25

±10

±40

—

±50

±10

±20

±100

—

ppm/°C Variation in Gain A due

Full Scale to Temperature Change

Gain Variance

% of

Variation from Ideal

Nominal Accuracy

Zero Offset

±50

±100

mV

Correction at Zero

(Note 2)

Adjust for Zero Output

when Input is Zero

Zero Temperature

Drift (Note 1)

—

±25

±50

—

±25

±50

—

±50

±100

μV/°C

Variation in Zero Offset

Due to Temperature

Change

Note 1: Full temperature range; not tested.

2: = 0.

3: Full temperature range, I

I

IN

= 10 mA.

OUT

4:

I

= 10 μA.

OUT

5: Threshold Detect = 5V, Amp Out = 0V, full temperature range.

6: 10 Hz to 100 kHz; not tested.

7: 5μsec minimum positive pulse width and 0.5μsec minimum negative pulse width.

8: = t = 20nsec.

9: R ≥ 2 kΩ, tested @ 10 kΩ.

t

R

F

L

10: Full temperature range, V = -0.1V.

IN

DS21483C-page 3

TC9400/9401/9402

TABLE 1-1:

TC940X ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: V = +5V, V = -5V, V

= 0V, V

= -5V, R

= 100 kΩ, Full Scale = 10 kHz, unless otherwise

BIAS

DD

SS

GND

REF

specified. T = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device).

A

Parameter

Min

Typ

Max Min

Typ

Max Min

Typ

Max

Units

Test Conditions

Analog Input

I

Full Scale

—

10

—

10

—

10

—

μA

Full Scale Analog Input

Current to achieve

Specified Accuracy

IN

I

Over Range

—

2

50

—

2

50

—

2

50

—

μA

Over Range Current

IN

Response Time

Cycle

Settling Time to 0.1%

Full Scale

Digital Section

TC9400

TC9401

TC9402

V

@ I = 10mA

—

0.2

0.4

18

—

0.2

0.4

18

—

0.2

0.4

18

V

Logic “0” Output

Voltage (Note 3)

SAT

OL

V_OUTMAX– V

—

3

—

3

—

3

Voltage Range

Between Output and

Common

OUT

Common (Note 4)

Pulse Frequency

Output Width

—

μsec

Frequency-to-Voltage

Supply Current

I

Quiescent

—

1.5

6

—

1.5

6

—

3

10

mA

Current Required from

Positive Supply during

Operation

DD

(Note 5)

I

Quiescent

—

-1.5

-6

-1.5

-6

-3

-10

Current Required from

Negative Supply during

Operation

SS

(Note 5)

V

Supply

4

—

7.5

4

—

7.5

4

—

7.5

V

Operating Range of

Positive Supply

DD

SS

V

-4

-7.5

-4

-7.5

-4

-7.5

Operating Range of

Negative Supply

Reference Voltage

– V

V

-2.5

—

-2.5

—

-2.5

—

V

Range of Voltage

Reference Input

REF

SS

Accuracy

Non-Linearity

0.02

0.05

0.01

0.02

0.05

0.25

%

Deviation from ideal

(Note 10)

Full Scale Transfer Function as a

Percentage Full Scale

Voltage

Input Frequency

Range

10

—

100k

10

—

100k

10

—

100k

Hz

Frequency Range for

Specified Non-Linearity

(Notes 7 and 8)

Frequency Input

Note 1: Full temperature range; not tested.

2: = 0.

3: Full temperature range, I

I

IN

= 10 mA.

OUT

4:

I

= 10 μA.

OUT

5: Threshold Detect = 5V, Amp Out = 0V, full temperature range.

6: 10 Hz to 100 kHz; not tested.

7: 5μsec minimum positive pulse width and 0.5μsec minimum negative pulse width.

8: = t = 20nsec.

9: R ≥ 2 kΩ, tested @ 10 kΩ.

t

R

F

L

10: Full temperature range, V = -0.1V.

IN

DS21483C-page 4

TC9400/9401/9402

TABLE 1-1:

TC940X ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: V = +5V, V = -5V, V

= 0V, V

= -5V, R

= 100 kΩ, Full Scale = 10 kHz, unless otherwise

BIAS

DD

SS

GND

REF

specified. T = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device).

A

Parameter

Min

Typ

Max Min

Typ

Max Min

Typ

Max

Units

Test Conditions

Positive Excursion

0.4

—

V

0.4

-0.4

—

V

0.4

-0.4

—

V

DD

V

Voltage Required to

Turn Threshold

Detector On

DD

Negative Excursion -0.4

-2

—

5

-2

—

5

-2

—

V

Voltage Required to

Turn Threshold

Detector Off

Minimum Positive

Pulse Width

(Note 8)

—

5

μsec

Time between

Threshold Crossings

Minimum Negative

Pulse Width

(Note 8)

0.5

—

0.5

—

0.5

Time Between

Threshold Crossings

Input Impedance

—

10

—

10

—

10

—

MΩ

Analog Outputs

TC9400

TC9401

TC9402

Output Voltage

(Note 9)

V

– 1

V

– 1

—

2

V – 1

DD

V

Voltage Range of Op

Amp Output for Speci-

fied Non-Linearity

DD

Output Loading

2

—

2

—

kΩ

Resistive Loading at

Output of Op Amp

Supply Current

TC9400

TC9401

TC9402

I

Quiescent

—

1.5

6

—

1.5

6

—

3

10

mA

Current Required from

Positive Supply During

Operation

DD

(Note 10)

I

Quiescent

-1.5

-6

-1.5

-6

-3

-10

Current Required from

Negative Supply

SS

(Note 10)

During Operation

V

Supply

4

—

7.5

4

—

7.5

4

—

7.5

V

Operating Range of

Positive Supply

DD

SS

V

-4

-7.5

-4

-7.5

-4

-7.5

Operating Range of

Negative Supply

Reference Voltage

– V

V

-2.5

—

-2.5

—

-2.5

—

V

Range of Voltage

Reference Input

REF

SS

Note 1: Full temperature range; not tested.

2: = 0.

3: Full temperature range, I

I

IN

= 10 mA.

OUT

4:

I

= 10 μA.

OUT

5: Threshold Detect = 5V, Amp Out = 0V, full temperature range.

6: 10 Hz to 100 kHz; not tested.

7: 5μsec minimum positive pulse width and 0.5μsec minimum negative pulse width.

8: = t = 20nsec.

9: R ≥ 2 kΩ, tested @ 10 kΩ.

t

R

F

L

10: Full temperature range, V = -0.1V.

IN

DS21483C-page 5

TC9400/9401/9402

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

Pin No.

14-Pin PDIP/CERDIP

14-Pin SOIC (Narrow)

Symbol

Description

1

2

3

4

5

6

7

8

I

This pin sets bias current in the TC9400. Connect to V through a 100 kΩ resistor.

BIAS

SS

ZERO ADJ

Low frequency adjustment input.

I

Input current connection for the V/F converter.

Negative power supply voltage connection, typically -5V.

Reference capacitor connection.

IN

V

SS

V

OUT

REF

GND

Analog ground.

V

Voltage reference input, typically -5V.

REF

PULSE FREQ

OUT

Frequency output. This open drain output will pulse LOW each time the Freq.

Threshold Detector limit is reached. The pulse rate is proportional to input voltage.

9

OUTPUT

Source connection for the open drain output FETs.

COMMON

10

11

FREQ/2 OUT

This open drain output is a square wave at one-half the frequency of the pulse output

(Pin 8). Output transitions of this pin occur on the rising edge of Pin 8.

THRESHOLD

DETECTOR

Input to the Threshold Detector. This pin is the frequency input during F/V operation.

12

13

14

AMPLIFIER OUT Output of the integrator amplifier.

NC

No internal connection.

V

Positive power supply connection, typically +5V.

DD

DS21483C-page 6

TC9400/9401/9402

ence voltage. As the input voltage is increased, the

number of reference pulses required to maintain

balance increases, which causes the output frequency

to also increase. Since each charge increment is fixed,

the increase in frequency with voltage is linear. In addi-

tion, the accuracy of the output pulse width does not

directly affect the linearity of the V/F. The pulse must

simply be long enough for full charge transfer to take

place.

3.0

3.1

DETAILED DESCRIPTION

Voltage-to-Frequency (V/F) Circuit

Description

The TC9400 V/F converter operates on the principal of

charge balancing. The operation of the TC9400 is eas-

ily understood by referring to Figure 3-1. The input volt-

age (V_IN) is converted to a current (I_IN) by the input

resistor. This current is then converted to a charge on

the integrating capacitor and shows up as a linearly

decreasing voltage at the output of the op amp. The

lower limit of the output swing is set by the threshold

detector, which causes the reference voltage to be

applied to the reference capacitor for a time period long

enough to charge the capacitor to the reference volt-

age. This action reduces the charge on the integrating

capacitor by a fixed amount (q = C_REFx V_REF), causing

the op amp output to step up a finite amount.

The TC9400 contains a “self-start” circuit to ensure the

V/F converter always operates properly when power is

first applied. In the event that, during power-on, the op

amp output is below the threshold and C_REFis already

charged, a positive voltage step will not occur. The op

amp output will continue to decrease until it crosses the

-3.0V threshold of the “self-start” comparator. When

this happens, an internal resistor is connected to the op

amp input, which forces the output to go positive until

the TC9400 is in its normal Operating mode.

At the end of the charging period, C_REFis shorted out.

This dissipates the charge stored on the reference

capacitor, so that when the output again crosses zero,

the system is ready to recycle. In this manner, the con-

tinued discharging of the integrating capacitor by the

input is balanced out by fixed charges from the refer-

The TC9400 utilizes low-power CMOS processing for

low input bias and offset currents, with very low power

dissipation. The open drain N-channel output FETs

provide high voltage and high current sink capability.

+5V

+

5V

14

V

R

L

DD

10 kΩ

F

OUT

Threshold

8

11

Detect

3μsec

Delay

+

5V

Threshold

Detector

R

L

10 kΩ

F /2

OUT

10

9

Self-

Start

÷2

-3V

12 AMP OUT

Output

Common

V

REF

OUT

5

20 kΩ

C

INT

820 pF

TC9400

C

REF

12 pF

180 pF

TC9401

TC9402

R

IN

INPUT

60 pF

–

I

IN

1MΩ

3

V

IN

+5V

Op Amp

+

Zero Adjust

0V –10V

510 kΩ

2

50 kΩ

V

7

I

GND

6

SS

REF

BIAS

-5V

Offset

Adjust

1

4

10 kΩ

R

BIAS

100 kΩ

Reference Voltage

(Typically -5V)

-5V

FIGURE 3-1:

10 Hz to 10 kHz V/F Converter

DS21483C-page 7

TC9400/9401/9402

3.2

Voltage-to-Time Measurements

The TC9400 output can be measured in the time

domain as well as the frequency domain. Some micro-

computers, for example, have extensive timing capabil-

ity, but limited counter capability. Also, the response

time of a time domain measurement is only the period

between two output pulses, while the frequency mea-

surement must accumulate pulses during the entire

counter time-base period.

Time measurements can be made from either the

TC9400’s PULSE FREQ OUT output, or from the

FREQ/2 OUT output. The FREQ/2 OUT output

changes state on the rising edge of PULSE FREQ

OUT, so FREQ/2 OUT is a symmetrical square wave at

one-half the pulse output frequency. Timing measure-

ments can, therefore, be made between successive

PULSE FREQ OUT pulses, or while FREQ/2 OUT is

high (or low).

DS21483C-page 8

TC9400/9401/9402

4.2

Pulse Freq Out

4.0

4.1

PIN FUNCTIONS

This output is an open drain N-channel FET, which

provides a pulse waveform whose frequency is propor-

tional to the input voltage. This output requires a pull-

up resistor and interfaces directly with MOS, CMOS,

and TTL logic (see Figure 4-1).

Threshold Detector Input

In the V/F mode, this input is connected to the AMPLI-

FIER OUT output (Pin 12) and triggers a 3μsec pulse

when the input voltage passes through its threshold. In

the F/V mode, the input frequency is applied to this

input.

4.3

Freq/2 Out

The nominal threshold of the detector is half way

between the power supplies, or (V_DD+ V_SS)/2 ±400

mV. The TC9400’s charge balancing V/F technique is

not dependent on a precision comparator threshold,

because the threshold only sets the lower limit of the op

amp output. The op amp’s peak-to-peak output swing,

which determines the frequency, is only influenced by

This output is an open drain N-channel FET, which pro-

vides a square wave one-half the frequency of the

pulse frequency output. The FREQ/2 OUT output will

change state on the rising edge of PULSE FREQ OUT.

This output requires a pull-up resistor and interfaces

directly with MOS, CMOS, and TTL logic.

external capacitors and by V_REF

.

3msec

Typ.

F

OUT

1/f

F /2

OUT

C

REF

C

INT

V

REF

0V

Amp Out

Notes: 1. To adjust F

, set V = 10 mV and adjust the 50 kW offset for 10 Hz output.

MIN IN

2. To adjust F

, set V = 10V and adjust R or V

for 10 kHz output.

to 75 pF.

MAX IN IN REF

3. To increase F _MAXto 100 kHz, change C to 2pF and C

4. For high performance applications, use high stability components for R , C

OUT

REF

INT

, V

(metal film

IN REF REF

resistors and glass capacitors). Also, separate output ground (Pin 9) from input ground (Pin 6).

FIGURE 4-1:

Output Waveforms

4.4

Output Common

4.6

Amplifier Out

The sources of both the FREQ/2 OUT and the PULSE

FREQ OUT are connected to this pin. An output level

swing from the drain voltage to ground, or to the V_SS

supply, may be obtained by connecting this pin to the

appropriate point.

This pin is the output stage of the operational amplifier.

During V/F operation, a negative going ramp signal is

available at this pin. In the F/V mode, a voltage

proportional to the frequency input is generated.

4.7

Zero Adjust

4.5

R

BIAS

This pin is the non-inverting input of the operational

amplifier. The low frequency set point is determined by

adjusting the voltage at this pin.

An external resistor, connected to V_SS, sets the bias

point for the TC9400. Specifications for the TC9400 are

based on R_BIAS= 100 kΩ ±10%, unless otherwise

noted.

4.8

I

IN

Increasing the maximum frequency of the TC9400

beyond 100 kHz is limited by the pulse width of the

pulse output (typically 3μsec). Reducing R_BIASwill

decrease the pulse width and increase the maximum

operating frequency, but linearity errors will also

increase. R_BIAScan be reduced to 20 kΩ, which will

typically produce a maximum full scale frequency of

500 kHz.

The inverting input of the operational amplifier and the

summing junction when connected in the V/F mode. An

input current of 10 μA is specified, but an over range

current up to 50 μA can be used without detrimental

effect to the circuit operation. I_INconnects the summing

junction of an operational amplifier. Voltage sources

cannot be attached directly, but must be buffered by

external resistors.

DS21483C-page 9

TC9400/9401/9402

4.9

V

REF

5.0

5.1

VOLTAGE-TO-FREQUENCY

(V/F) CONVERTER DESIGN

INFORMATION

A reference voltage from either a precision source, or

the V_SSsupply is applied to this pin. Accuracy of the

TC9400 is dependent on the voltage regulation and

temperature characteristics of the reference circuitry.

Input/Output Relationships

Since the TC9400 is a charge balancing V/F converter,

the reference current will be equal to the input current.

For this reason, the DC impedance of the reference

voltage source must be kept low enough to prevent lin-

earity errors. For linearity of 0.01%, a reference imped-

ance of 200W or less is recommended. A 0.1 μF

bypass capacitor should be connected from V_REFto

ground.

The output frequency (F_OUT) is related to the analog

input voltage (V_IN) by the transfer equation:

EQUATION 5-1:

V_IN

R_IN

1

Frequency Out =

, x

(V_REF)(V_REF

)

4.10 V_REFOut

5.2

External Component Selection

The charging current for C_REFis supplied through this

pin. When the op amp output reaches the threshold

level, this pin is internally connected to the reference

voltage and a charge, equal to V_REFx C_REF, is removed

from the integrator capacitor. After about 3μsec, this pin

is internally connected to the summing junction of the

op amp to discharge C_REF. Break-before-make switch-

ing ensures that the reference voltage is not directly

applied to the summing junction.

5.2.1

R_IN

The value of this component is chosen to give a full

scale input current of approximately 10 μA:

EQUATION 5-2:

FULLSCALE

V_IN

R_IN

≅

10 μA

EQUATION 5-3:

10V

R_IN

≅

= 1 MΩ

10 μA

Note that the value is an approximation and the exact

relationship is defined by the transfer equation. In prac-

tice, the value of R_INtypically would be trimmed to

obtain full scale frequency at V_INfull scale (see

Section 5.3 “Adjustment Procedure”, Adjustment

Procedure). Metal film resistors with 1% tolerance or

better are recommended for high accuracy applications

because of their thermal stability and low noise gener-

ation.

5.2.2

C_INT

The exact value is not critical but is related to C_REFby

the relationship:

3C_REF≤ C_INT≤ 10C_REF

Improved stability and linearity are obtained when

C_INT≤ 4C_REF. Low leakage types are recommended,

although mica and ceramic devices can be used in

applications where their temperature limits are not

exceeded. Locate as close as possible to Pins 12

and 13.

DS21483C-page 10

TC9400/9401/9402

5.2.3

C_REF

5.3

Adjustment Procedure

The exact value is not critical and may be used to trim

the full scale frequency (see Section 7.1 “Input/Out-

put Relationships”, Input/Output Relationships).

Glass film or air trimmer capacitors are recommended

because of their stability and low leakage. Locate as

close as possible to Pins 5 and 3 (see Figure ).

Figure 3-1 shows a circuit for trimming the zero loca-

tion. Full scale may be trimmed by adjusting R_IN, V_REF

or C_REF. Recommended procedure for a 10 kHz full

scale frequency is as follows:

,

1. Set V_INto 10 mV and trim the zero adjust circuit

to obtain a 10 Hz output frequency.

2. Set V_INto 10V and trim either R_IN, V_REF, or C_REF

to obtain a 10 kHz output frequency.

500

V

= +5V

= -5V

DD

SS

If adjustments are performed in this order, there should

be no interaction and they should not have to be

repeated.

R

= 1MW

= +10V

400

300

200

100

IN

V

T

IN

= +25°C

A

10 kHz

5.4

Improved Single Supply V/F

Converter Operation

A TC9400, which operates from a single 12 to 15V vari-

able power source, is shown in Figure 5-2. This circuit

uses two Zener diodes to set stable biasing levels for

the TC9400. The Zener diodes also provide the refer-

ence voltage, so the output impedance and tempera-

ture coefficient of the Zeners will directly affect power

supply rejection and temperature performance. Full

scale adjustment is accomplished by trimming the input

current.

100 kHz

-2 -3 -4

0

-5 -6

-7

-1

V

(V)

REF

FIGURE 5-1:

Recommended C_REFvs.

V_REF

5.2.4

V_DD, V_SS

Trimming the reference voltage is not recommended

for high accuracy applications unless an op amp is

used as a buffer, because the TC9400 requires a low-

impedance reference (see Section 4.9 “VREF”, V_REF

pin description, for more information).

Power supplies of ±5V are recommended. For high

accuracy requirements, 0.05% line and load regulation

and 0.1 μF disc decoupling capacitors, located near the

pins, are recommended.

The circuit of Figure 5-2 will directly interface with

CMOS logic operating at 12V to 15V. TTL or 5V CMOS

logic can be accommodated by connecting the output

pull-up resistors to the +5V supply. An optoisolator can

also be used if an isolated output is required; also, see

Figure 5-3.

DS21483C-page 11

TC9400/9401/9402

+12 to +15V

14

1.2k

V

DD

1 μF

Threshold

Detect

Amp Out

11

12

5

R

4

1

C

INT

10k

910k

100k

D

2

C

5.1 VZ

REF

C

REF

R

3

TC9400

Gain

3

2

6

I

8

IN

F

OUT

Zero Adjust

100k

10

9

Output

Frequency

GND

F

/2

OUT

R

5

2

D

1

910k

91k

0.1μ

Output

5.1 VZ

Common

7

1

V

REF

Rp

I

BIAS

Offset

20k

V

100k

SS

Digital

Ground

Input

4

Voltage

(0 to 10V)

Analog Ground

Component Selection

C_REF

2200 pF 4700 pF

180 pF

27 pF

C_INT

F/S FREQ.

1 kHz

470 pF

75 pF

10 kHz

100 kHz

FIGURE 5-2:

Voltage-to-Frequency

DS21483C-page 12

TC9400/9401/9402

V+ = 8V to 15V (Fixed)

R

2

14

10 kΩ

V

2

0.9

2

6

5V

R

1

8

F

OUT

0.01

μF

8.2

Gain

TC9400

kΩ

Adjust

10 kΩ

7

11

10

F

/2

V

2

OUT

REF

kΩ

0.01

μF

Offset

Adjust

0.2

12

5

R

1

R

820

pF

IN

180

pF

1 MΩ

3

I

IN

V

IN

0V–10V

I

IN

1

4

9

100 kΩ

R

2

1

V+

10V

1

F

= I

IN

OUT

–

(V

V ) (C

)

1 MΩ 10 kΩ

2

7

REF

12V 1.4 MΩ 14 kΩ

15V

2 MΩ 20 kΩ

(V – V )

IN

(V+ – V )

2

+

=

I

IN

R

(0.9R + 0.2R )

1 1

IN

FIGURE 5-3:

Fixed Voltage – Single Supply Operation

DS21483C-page 13

TC9400/9401/9402

6.0

FREQUENCY-TO-VOLTAGE

(F/V) CIRCUIT DESCRIPTION

When used as an F/V converter, the TC9400 generates

an output voltage linearly proportional to the input

frequency waveform.

Each zero crossing at the threshold detector’s input

causes a precise amount of charge (q = C_REF∞ V_REF

)

to be dispensed into the op amp’s summing junction.

This charge, in turn, flows through the feedback resis-

tor, generating voltage pulses at the output of the op

amp. A capacitor (C_INT) across R_INTaverages these

pulses into a DC voltage, which is linearly proportional

to the input frequency.

DS21483C-page 14

TC9400/9401/9402

7.2

Input Voltage Levels

7.0

7.1

F/V CONVERTER DESIGN

INFORMATION

The input frequency is applied to the Threshold Detec-

tor input (Pin 11). As discussed in the V/F circuit section

of this data sheet, the threshold of Pin 11 is approxi-

mately (V_DD+ V_SS)/2 ±400 mV. Pin 11’s input voltage

range extends from V_DDto about 2.5V below the thresh-

old. If the voltage on Pin 11 goes more than 2.5 volts

below the threshold, the V/F mode start-up comparator

will turn on and corrupt the output voltage. The Thresh-

old Detector input has about 200 mV of hysteresis.

Input/Output Relationships

The output voltage is related to the input frequency

(F_IN) by the transfer equation:

EQUATION 7-1:

V_OUT= [V_REFC_REFR_INT] F_IN

In ±5V applications, the input voltage levels for the

TC9400 are ±400 mV, minimum. If the frequency

source being measured is unipolar, such as TTL or

CMOS operating from a +5V source, then an AC

coupled level shifter should be used. One such circuit

is shown in Figure 7-1(a).

The response time to a change in F_INis equal to (R_INT

C_INT). The amount of ripple on V_OUTis inversely

proportional to C_INTand the input frequency.

C_INTcan be increased to lower the ripple. Values of 1 μF

to 100 μF are perfectly acceptable for low frequencies.

The level shifter circuit in Figure 7-1(b) can be used in

single supply F/V applications. The resistor divider

ensures that the input threshold will track the supply

voltages. The diode clamp prevents the input from

going far enough in the negative direction to turn on the

start-up comparator. The diode’s forward voltage

decreases by 2.1mV/°C, so for high ambient tempera-

ture operation, two diodes in series are recommended;

also, see Figure .

When the TC9400 is used in the Single Supply mode,

V_REFis defined as the voltage difference between Pin 7

and Pin 2.

+8V to +5V

14

+5V

14

V

DD

10k

TC9400

0.01 μF

33k

0.01 μF

33k

11

Frequency

Input

11

Frequency

Input

DET

IN914

+5V

1.0M

+5V

0V

IN914 1.0M

0V

V

GND

6

V

SS

10k

0.1 μF

4

-5V

(b) Single Supply

(a) 5V Supply

FIGURE 7-1:

Frequency Input Level Shifter

DS21483C-page 15

TC9400/9401/9402

V+ = 10V to 15V

14

10k

V

DD

6

GND

.01 μF

TC9400

6.2V

10k

5

3

V

OUT

REF

500k

2

Zero

47 pF

100k

Adjust

V+

I

IN

Offset

Adjust

.001 μF

1M

12

6

Amp Out

1.0k

0.01 μF

33k

Frequency

Input

11

V

OUT

DET

GND

V

IN914

I

V

BIAS

1.0M

REF

7

SS

4

0.1 μF

1.0k

100k

Note: The output is referenced to Pin 6, which is at 6.2V (Vz). For frequency meter applications,

a 1mA meter with a series scaling resistor can be placed across Pins 6 and 12.

FIGURE 7-2:

7.3

F/V Single Supply F/V Converter

Input Buffer

F_OUTand F_OUT/2 are not used in the F/V mode. How-

ever, these outputs may be useful for some applica-

tions, such as a buffer to feed additional circuitry. Then,

F_OUTwill follow the input frequency waveform, except

that F_OUTwill go high 3μsec after F_INgoes high;

5.0msec

Min

0.5msec

Min

Input

F

OUT

F

_OUT/2 will be square wave with a frequency of

one-half F_OUT

.

Delay = 3msec

If these outputs are not used, Pins 8, 9 and 10 should be

connected to ground (see Figure 7-3 and Figure 7-4).

F /2

OUT

FIGURE 7-3:

F/V Digital Outputs

DS21483C-page 16

TC9400/9401/9402

+5V

14

V+

*

V

DD

F

/2

OUT

10

9

TC9400A

TC9401A

TC9402A

42

V+

Output

Common

See

Figure 7-1:

*

Threshold

Detect

*

"Frequency

Input Level

Shifter"

F

OUT

8

11

3msec

Delay

F

IN

*Optional/If

Buffer is Needed

Threshold

Detector

V

REF

OUT

5

C

REF

56 pF

12 pF

Offset

Adjust

I

IN

3

R

C

INT

1000 pF

60 pF

+

+5V

100 kΩ

Amp

Out

1 MΩ

–

12

Op

Amp

+

V

OUT

Zero Adjust

2

2 kΩ

2.2 kΩ

I

V

REF

BIAS

SS

4

GND

6

1

7

10 kΩ

V

REF

(Typically -5V)

-5V

FIGURE 7-4:

DC – 10 kHz Converter

FIGURE 7-1:

RIPPLE FILTER

7.4 Output Filtering

The output of the TC9400 has a sawtooth ripple super-

imposed on a DC level. The ripple will be rejected if the

TC9400 output is converted to a digital value by an inte-

grating Analog-to-Digital Converter, such as the

TC7107 or TC7109. The ripple can also be reduced by

increasing the value of the integrating capacitor,

although this will reduce the response time of the F/V

converter.

5

3

V

OUT

REF

47 pF

TC9400

I

IN

.001 μF

1M

200

12

AMP OUT

The sawtooth ripple on the output of an F/V can be

eliminated without affecting the F/V’s response time by

using the circuit in Figure 7-1. The circuit is a capaci-

tance multiplier, where the output coupling capacitor is

multiplied by the AC gain of the op amp. A moderately

fast op amp, such as the TL071, should be used.

1M

0.1 μF

.01 μF

GND

6

+5

V

OUT

7

4

2

3

–

6

TL071

+

1M

-5

FIGURE 7-5:

Ripple Filter

DS21483C-page 17

TC9400/9401/9402

In some cases, however, the TC9400 output must be

zero at power-on without a frequency input. In such

cases, a capacitor connected from Pin 11 to V_DDwill

usually be sufficient to pulse the TC9400 and provide a

Power-on Reset (see Figure 8-1 (a) and (b)). Where

predictable power-on operation is critical, a more

complicated circuit, such as Figure 8-1 (b), may be

required.

8.0

F/V POWER-ON RESET

In F/V mode, the TC9400 output voltage will occasion-

ally be at its maximum value when power is first

applied. This condition remains until the first pulse is

applied to F_IN. In most frequency measurement appli-

cations, this is not a problem because proper operation

begins as soon as the frequency input is applied.

(a)

(b)

V

DD

V

DD

14

16

5

2

1

1000 pF

V

CLRA

B

R

C

CC

3

4

1 kΩ

F

IN

Threshold

Detector

11

100 kΩ

1 μF

CD4538

6

To TC9400

Q

A

V

SS

8

F

IN

TC9400

FIGURE 8-1:

Power-On Operation/Reset

DS21483C-page 18

TC9400/9401/9402

9.0

9.1

PACKAGE INFORMATION

Package Marking Information

Package marking data is not available at this time.

9.2

Taping Form

Component Taping Orientation for 14-Pin SOIC (Narrow) Devices

User Direction of Feed

Pin 1

W

P

Standard Reel Component Orientation

for 713 Suffix Device

Carrier Tape, Reel Size, and Number of Components Per Reel

Package

Carrier Width (W)

Pitch (P)

Part Per Full Reel

Reel Size

14-Pin SOIC (N)

12 mm

8 mm

2500

13 in

9.3

Package Dimensions

14-Pin CDIP (Narrow)

Pin 1

.300 (7.62)

.230 (5.84)

.098 (2.49) Max.

.030 (0.76) Min.

.780 (19.81)

.740 (18.80)

.320 (8.13)

.290 (7.37)

.040 (1.02)

.020 (0.51)

.200 (5.08)

.160 (4.06)

.015 (0.38)

.008 (0.20)

3° Min.

.200 (5.08)

.125 (3.18)

.150 (3.81)

Min.

.400 (10.16)

.320 (8.13)

.020 (0.51)

.016 (0.41)

.110 (2.79)

.090 (2.29)

.065 (1.65)

.045 (1.14)

Dimensions: inches (mm)

DS21483C-page 19

TC9400/9401/9402

9.3

Package Dimensions (Continued)

14-Pin PDIP (Narrow)

Pin 1

.260 (6.60)

.240 (6.10)

.310 (7.87)

.290 (7.37)

.770 (19.56)

.745 (18.92)

.200 (5.08)

.140 (3.56)

.040 (1.02)

.020 (0.51)

.015 (0.38)

.008 (0.20)

3° Min.

.150 (3.81)

.115 (2.92)

.400 (10.16)

.310 (7.87)

.110 (2.79)

.070 (1.78)

.022 (0.56)

.015 (0.38)

.090 (2.29) .045 (1.14)

Dimensions: inches (mm)

14-Pin SOIC (Narrow)

Pin 1

.157 (3.99) .244 (6.20)

.150 (3.81) .228 (5.79)

.050 (1.27) Typ.

.344 (8.74)

.337 (8.56)

.069 (1.75)

.053 (1.35)

.010 (0.25)

.007 (0.18)

8° Max.

.010 (0.25)

.004 (0.10)

.050 (1.27)

.016 (0.40)

.018 (0.46)

.014 (0.36)

Dimensions: inches (mm)

DS21483C-page 20

TC9400/9401/9402

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

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DS21483C-page 21

TC9400/9401/9402

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

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TC9400/9401/9402

DS21483C

Literature Number:

Device:

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DS21483C-page 22

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

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Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

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DS21483C-page 23

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02/16/06

DS21483C-page 24


型号：	TC9401E/OD
厂家：	MICROCHIP
描述：	IC,VOLTAGE-TO-FREQUENCY CONVERTER,CMOS,SOP,14PIN 转换器
文件：	总24页 (文件大小：674K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC9401E/OD [MICROCHIP]

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