TC7129CJL_技术文档

TC7129

4-1/2 Digit Analog-to-Digital Converters with

On-Chip LCD Drivers

Features:

General Description:

• Count Resolution: ±19,999

The TC7129 is a 4-1/2 digit Analog-to-Digital Converter

(ADC) that directly drives a multiplexed Liquid Crystal

Display (LCD). Fabricated in high-performance, low-

power CMOS, the TC7129 ADC is designed specifi-

cally for high-resolution, battery-powered digital multi-

meter applications. The traditional dual-slope method

of A/D conversion has been enhanced with a succes-

sive integration technique to produce readings accu-

rate to better than 0.005% of full-scale and resolution

down to 10 μV per count.

• Resolution on 200 mV Scale: 10 μV

• True Differential Input and Reference

• Low Power Consumption: 500 μA at 9V

• Direct LCD Driver for 4-1/2 Digits, Decimal Points,

Low Battery Indicator, and Continuity Indicator

• Overrange and Underrange Outputs

• Range Select Input: 10:1

• High Common Mode Rejection Ratio: 110 dB

• External Phase Compensation Not Required

The TC7129 includes features important to multimeter

applications. It detects and indicates low battery condi-

tion. A continuity output drives an annunciator on the

display and can be used with an external driver to sound

an audible alarm. Overrange and underrange outputs,

along with a range-change input, provide the ability to

create auto-ranging instruments. For snapshot read-

ings, the TC7129 includes a latch-and-hold input to

freeze the present reading. This combination of features

makes the TC7129 the ideal choice for full-featured

multimeter and digital measurement applications.

Applications:

• Full-Featured Multimeters

• Digital Measurement Devices

Device Selection Table

Package

Code

Layout

Temperature

Range

Package

TC7129CPL

Normal

40-Pin PDIP

44-PinPQFP

44-PinPLCC

0°C to +70°C

TC7129CKW Formed

TC7129CLW

–

Typical Application

Low Battery

Continuity

V+

5 pF

20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

120 kHz

TC7129

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

330 kΩ

*

0.1 µF

10 pF

V+

0.1

+

µF

20

kΩ

0.1 µF

1 µF

150 kΩ

10 kΩ

+

100 kΩ

9V

+

–

V

IN

*Note: RC network between pins 26 and 28 is not required.

DS21459D-page 1

TC7129

Package Types

40-Pin PDIP

OSC1

OSC3

40 OSC2

1

2

39 DP

1

38 DP

2

ANNUNICATOR

B , C , CONT

3

37

4

RANGE

1

A , G , D

5

36 DGND

1

F , E , DP

6

REF LO

REF HI

IN HI

1

35

34

33

32

B , C , LO BATT

7

2

A , G , D

8

2

F , E , DP

9

2

IN LO

31 BUFF

10

11

12

13

14

15

16

17

18

19

20

B , C MINUS

TC7129CPL

3

,

Display

Output

Lines

A , G , D

C

-

30

29

28

3

5

4

REF

F , E , DP

+

3

REF

B , C BC

COMMON

4

,

A , G , D

27 CONTINUITY

26 INT OUT

25 INT IN

24 V+

4

F , E , DP

4

BP

3

2

1

23 V-

V

22

LATCH/HOLD

DISP

DP /OR

21 DP /UR

3

4

44-Pin QFP

44-Pin PLCC

6

5

4

3

2

1

44 43 42 41 40

44 43 42 41 40 39 38 37 36 35 34

F , E , DP

1

REF LO

33

32

31

30

29

28

27

26

25

24

23

7

39

38 REF HI

IN HI

1

2

3

4

REF LO

REF HI

1

8

B , C , BATT

2 2

2

A , G , D

2 2 2

9

37

36 IN LO

IN HI

IN LO

BUFF

NC

2

F , E , DP

2 2 2

10

11

12

13

14

15

16

2

B , C MINUS

35

34

33

32

31

30

29

BUFF

NC

5

6

3

,

3

,

NC

TC7129CKW

TC7129CLW

A , G , D

C

-

7

C

-

3

REF

F , E , DP

3 3

C

+

8

C

+

3

B , C BC

4 4 5

,

9

COMMON

CONTINUITY

INT OUT

4

5

COMMON

CONTINUITY

INT OUT

,

A , G , D

4 4 4

10

11

4

F , E , DP

F , E , DP 17

4 4 4

4

18 19 20 21 22 23 24 25 26 27 28

12 13 14 15 16 17 18 19 20 21 22

DS21459D-page 2

TC7129

*Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. These

are stress ratings only and functional operation of the device

at these or any other conditions above those indicated in the

operation sections of the specifications is not implied.

Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings*

Supply Voltage (V+ to V-).......................................15V

Reference Voltage (REF HI or REF LO) ........ V+ to V–

Input Voltage (IN HI or IN LO) (Note 1).......... V+ to V–

V_DISP.......................................... V+ to (DGND – 0.3V)

Digital Input (Pins 1, 2, 19, 20,

21, 22, 27, 37, 39, 40).......................... DGND to V+

Analog Input (Pins 25, 29, 30) ....................... V+ to V–

Package Power Dissipation (T_A≤ 70°C)

Plastic DIP .....................................................1.23W

PLCC .............................................................1.23W

Plastic QFP ....................................................1.00W

Operating Temperature Range ............... 0°C to +70°C

Storage Temperature Range..............-65°C to +150°C

TC7129 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: V+ to V– = 9V, V_REF= 1V, T_A= +25°C, f_CLK= 120 kHz, unless otherwise indicated.

Pin numbers refer to 40-pin DIP.

Symbol

Input

Parameter

Min

Typ

Max

Unit

Test Conditions

Zero Input Reading

–0000

—

0000

±0.5

—

+0000 Counts V_IN= 0V, 200 mV scale

μV/°C V_IN= 0V, 0°C < T_A< +70°C

Zero Reading Drift

—

Ratiometric Reading

9996

10000 Counts V_IN= V_REF= 1000 mV,

Range = 2V

Range Change Accuracy

0.9999

1.0000 1.0001

Ratio V_IN= 1V on High Range,

V_IN= 0.1V on Low Range

RE

NL

Rollover Error

Linearity Error

—

1

2

Counts V_IN– = V_IN+ = 199 mV

Counts 200mV Scale

—

CMRR Common Mode Rejection Ratio

110

dB

V_CM= 1V, V_IN= 0V,

200 mV scale

CMVR Common Mode Voltage Range

—

(V-) +

1.5

—

V

V_IN= 0V

—

(V+) – 1

14

—

V

200 mV scale

e_N

I_IN

Noise (Peak-to-Peak Value not

Exceeded 95% of Time)

μV_P-PV_IN= 0V

200 mV scale

V_IN= 0V, pins 32, 33

Input Leakage Current

—

1

2

10

7

pA

Scale Factor Temperature

Coefficient

ppm/°C V_IN= 199 mV,

0°C < T_A< +70°C

External V_REF= 0 ppm/°C

Note 1: Input voltages may exceed supply voltages, provided input current is limited to ±400 μA. Currents above

this value may result in invalid display readings, but will not destroy the device if limited to ±1 mA.

Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.

DS21459D-page 3

TC7129

TC7129 ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: V+ to V– = 9V, V_REF= 1V, T_A= +25°C, f_CLK= 120 kHz, unless otherwise indicated.

Pin numbers refer to 40-pin DIP.

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Power

V_COM

Common Voltage

2.8

—

4.5

—

6

3.2

0.6

10

3.5

—

V

mA

μA

V

V+ to pin 28

Common Sink Current

ΔCommon = +0.1V

ΔCommon = -0.1V

V+ to pin 36, V+ to V– = 9V

ΔDGND = +0.5V

V+ to V–

Common Source Current

—

DGND Digital Ground Voltage

Sink Current

5.3

1.2

9

5.8

—

mA

V

Supply Voltage Range

12

1.3

I_S

Supply Current Excluding

Common Current

—

0.8

mA

V+ to V– = 9V

f_CLK

Clock Frequency

V_DISPResistance

—

120

50

360

—

kHz

kΩ

V

V_DISPto V+

V+ to V–

Low Battery Flag Activation

Voltage

6.3

7.2

7.7

Digital

Continuity Comparator Threshold

Voltages

100

—

200

2

—

400

10

—

mV

μA

V_OUTpin 27 = High

V_OUTpin 27 = Low

Pins 37, 38, 39

Pull-down Current

“Weak Output” Current

Sink/Source

3/3

3/9

40

3

Pins 20, 21 sink/source

Pin 27 sink/source

—

Pin 22 Source Current

Pin 22 Sink Current

—

Note 1: Input voltages may exceed supply voltages, provided input current is limited to ±400 μA. Currents above

this value may result in invalid display readings, but will not destroy the device if limited to ±1 mA.

Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.

DS21459D-page 4

TC7129

2.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

Pin No.

Symbol

Function

40-Pin PDIP 44-Pin PQFP 44-Pin PLCC

1

2

3

4

5

6

7

40

41

42

43

44

1

2

3

4

5

6

7

8

OSC1

OSC3

Input to first clock inverter.

Output of second clock inverter.

ANNUNCIATOR Backplane square wave output for driving annunciators.

B , C , CONT

Output to display segments.

1

A , G , D

1

F , E , DP

1

2

B , C ,

2 2

LO BATT

8

3

4

9

A , G , D

Output to display segments.

Backplane #3 output to display.

Backplane #2 output to display.

Backplane #1 output to display.

Negative rail for display drivers.

2

9

10

11

13

14

15

16

17

18

19

20

21

22

F , E , DP

2 2

2

10

11

12

13

14

15

16

17

18

19

20

5

B , C , MINUS

3 3

7

A , G , D

3 3 3

8

F , E , DP

3 3 3

9

B , C , BC

4 4

5

10

11

12

13

14

15

16

A , D , G

4

F , E , DP

4

BP

3

2

1

BP

V

DISP

DP /OR

Input: When high, turns on most significant decimal point.

Output: Pulled high when result count exceeds ±19,999.

4

21

22

18

19

24

25

DP /UR

Input: Second-most significant decimal point on when high.

Output: Pulled high when result count is less than ±1000.

3

LATCH/HOLD

Input: When floating, ADC operates in Free Run mode. When

pulled high, the last displayed reading is held. When pulled low,

the result counter contents are shown incrementing during the

de-integrate phase of cycle.

Output: Negative going edge occurs when the data latches are

updated. Can be used for converter status signal.

23

24

20

21

26

27

V–

V+

Negative power supply terminal.

Positive power supply terminal and positive rail for display

drivers.

25

26

27

22

23

24

28

29

30

INT IN

INT OUT

Input to integrator amplifier.

Output of integrator amplifier.

CONTINUITY

Input: When low, continuity flag on the display is off. When high,

continuity flag is on.

Output: High when voltage between inputs is less than +200 mV.

Low when voltage between inputs is more than +200 mV.

28

25

31

COMMON

Sets common mode voltage of 3.2V below V+ for DE, 10X, etc.

Can be used as pre-regulator for external reference.

29

30

31

32

33

34

35

26

27

29

30

31

32

33

32

33

35

36

37

38

39

C

+

–

Positive side of external reference capacitor.

Negative side of external reference capacitor.

Output of buffer amplifier.

REF

BUFFER

IN LO

Negative input voltage terminal.

Positive input voltage terminal.

Positive reference voltage.

IN HI

REF HI

REF LO

Negative reference voltage

DS21459D-page 5

TC7129

TABLE 2-1:

PIN FUNCTION TABLE (CONTINUED)

Pin No.

Symbol

Function

40-Pin PDIP 44-Pin PQFP 44-Pin PLCC

36

34

40

DGND

Internal ground reference for digital section. See Section 4.2.1

“±5V Power Supply”.

37

35

41

RANGE

3 μA pull-down for 200 mV scale. Pulled high externally for 2V

scale.

38

39

40

—

36

37

38

42

43

44

DP

Internal 3 μA pull-down. When high, decimal point 2 will be on.

Internal 3 μA pull-down. When high, decimal point 1 will be on.

Output of first clock inverter. Input of second clock inverter.

No connection.

2

DP

1

OSC2

NC

6,17, 28, 39 12, 23, 34, 1

DS21459D-page 6

TC7129

The resistor and capacitor values are not critical; those

shown work for most applications. In some situations,

the capacitor values may have to be adjusted to

compensate for parasitic capacitance in the circuit. The

capacitors can be low-cost ceramic devices.

3.0

DETAILED DESCRIPTION

(All pin designations refer to 40-pin PDIP.)

The TC7129 is designed to be the heart of a high-

resolution analog measurement instrument. The only

additional components required are a few passive

elements: a voltage reference, a LCD and a power

source. Most component values are not critical;

substitutes can be chosen based on the information

given below.

Some applications can use a simple RC network

instead of a crystal oscillator. The RC oscillator has

more potential for jitter, especially in the least

significant digit. See Section 4.5 “RC Oscillator”.

The basic circuit for a digital multimeter application is

shown in Figure 3-1. See Section 4.0 “Typical Appli-

cations”, for variations. Typical values for each

component are shown. The sections below give

component selection criteria.

3.2

Integrating Resistor (R_INT)

The integrating resistor sets the charging current for

the integrating capacitor. Choose a value that provides

a current between 5 μA and 20 μA at 2V, the maximum

full-scale input. The typical value chosen gives a

charging current of 13.3 μA:

3.1

Oscillator (X

, C , C , R )

OSC O1 O2 O

EQUATION 3-1:

The primary criterion for selecting the crystal oscillator

is to choose a frequency that achieves maximum rejec-

tion of line frequency noise. To do this, the integration

phase should last an integral number of line cycles.

The integration phase of the TC7129 is 10,000 clock

cycles on the 200 mV range and 1000 clock cycles on

the 2V range. One clock cycle is equal to two oscillator

cycles. For 60 Hz rejection, the oscillator frequency

should be chosen so that the period of one line cycle

equals the integration time for the 2V range.

2V

150 kΩ

I_CHARGE

=

13.3 µA

Too high a value for R_INTincreases the sensitivity to

noise pickup and increases errors due to leakage

current. Too low a value degrades the linearity of the

integration, leading to inaccurate readings.

EQUATION 3-1:

1/60 second = 16.7 msec =

1000 clock cycles *2 OSC cycles/clock cycle

OSC Frequency

This equation gives an oscillator frequency of 120 kHz.

A similar calculation gives an optimum frequency of

100 kHz for 50 Hz rejection.

DS21459D-page 7

TC7129

Low Battery

Continuity

V+

C

5 pF

O1

20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Display Drive Outputs

TC7129

120

kHz

Crystal

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

330 kΩ

R

O

C

INT

0.1 µF

C

10 pF

O2

R

D

REF

C

+

0.1

µF

REF

20

kΩ

REF

1 µF

C

RF

0.1 µF

V+

150 kΩ

R

C

IF

INT

10 kΩ

BIAS

+

R

IF

100 kΩ

R

9V

–

+

V

IN

Figure 3-1:

Standard Circuit.

The capacitor should have low dielectric absorption to

ensure good integration linearity. Polypropylene and

Teflon^®capacitors are usually suitable. A good

measurement of the dielectric absorption is to connect

the reference capacitor across the inputs by

connecting:

3.3 Integrating Capacitor (C

)

INT

The charge stored in the integrating capacitor during

the integrate phase is directly proportional to the input

voltage. The primary selection criterion for C_INTis to

choose a value that gives the highest voltage swing

while remaining within the high-linearity portion of the

integrator output range. An integrator swing of 2V is the

recommended value. The capacitor value can be

calculated using the following equation:

Pin-to-Pin:

20 → 33 (C_REF+ to IN HI)

30 → 32 (C_REF– to IN LO)

EQUATION 3-1:

A reading between 10,000 and 9998 is acceptable;

anything lower indicates unacceptably high dielectric

absorption.

t_INTx I_INT

C_INT

=

V_SWING

Where t_INTis the integration time.

3.4

Reference Capacitor (C

)

REF

The reference capacitor stores the reference voltage

during several phases of the measurement cycle. Low

leakage is the primary selection criterion for this com-

ponent. The value must be high enough to offset the

effect of stray capacitance at the capacitor terminals. A

value of at least 1 μF is recommended.

Using the values derived above (assuming 60 Hz

operation), the equation becomes:

EQUATION 3-2:

16.7 msec x 13.3 μA

C_INT

=

= 0.1 μA

2V

DS21459D-page 8

TC7129

3.5

Voltage Reference

(D , R , R , C

+5V

)

RF

REF REF BIAS

TC7129

The reference potentiometer (R_REF) provides an

adjustment for adjusting the reference voltage; any

value above 20 kΩ is adequate. The bias resistor

(R_BIAS) limits the current through D_REFto less than

150 μA. The reference filter capacitor (C_RF) forms an

RC filter with R_BIASto help eliminate noise.

24

V+

34

REF HI

0.1 µF

35

REF LO

36

DGND

3.6

Input Filter (R , C )

IF IF

28

33

COMMON

0.1 µF

For added stability, an RC input noise filter is usually

included in the circuit. The input filter resistor value

should not exceed 100 kΩ. A typical RC time constant

value is 16.7 msec to help reject line frequency noise.

The input filter capacitor should have low leakage for a

high-impedance input.

+

–

IN HI

V

IN

32

0.1 µF

IN LO

V–

23

3.7

Battery

-5V

The typical circuit uses a 9V battery as a power source.

However, any value between 6V and 12V can be used.

For operation from batteries with voltages lower than

6V and for operation from power supplies, see

Section 4.2 “Powering the TC7129”.

Figure 4-1:

a ±5V Power Supply.

Powering the TC7129 From

4.2.2

Low Voltage Battery Source

A battery with voltage between 3.8V and 6V can be

used to power the TC7129 when used with a voltage

doubler circuit, as shown in Figure 4-2. The voltage

doubler uses the TC7660 DC-to-DC voltage converter

and two external capacitors.

4.0

4.1

TYPICAL APPLICATIONS

TC7129 as a Replacement Part

The TC7129 is a direct pin-for-pin replacement part for

the ICL7129. Note, however, that the ICL7129 requires

a capacitor and resistor between pins 26 and 28 for

phase compensation. Since the TC7129 uses internal

phase compensation, these parts are not required and,

in fact, must be removed from the circuit for stable

operation.

24

V+

34

REF HI

36

DGND

+

3.8V

to

6V

35

REF LO

28

33

32

COMMON

4.2

Powering the TC7129

TC7129

+

IN HI

While the most common power source for the TC7129

is a 9V battery, there are other possibilities. Some of

the more common ones are explained below.

V

IN

8

IN LO

V–

–

2

+

23

10 µF

4.2.1

±5V Power Supply

TC7660

4

5

Measurements are made with respect to power supply

ground. DGND (pin 36) is set internally to about 5V less

than V+ (pin 24); it is not intended to be a power supply

input and must not be tied directly to power supply

ground. It can be used as a reference for external logic,

as explained in Section 4.3 “Connecting to External

Logic”, (see Figure 4-1).

10 µF

+

3

Figure 4-2:

Powering the TC7129 From

a Low-Voltage Battery.

DS21459D-page 9

TC7129

4.2.3

+5V Power Supply

+

V

Measurements are made with respect to power supply

ground. COMMON (pin 28) is connected to REF LO

(pin 35). A voltage doubler is needed, since the supply

voltage is less than the 6V minimum needed by the

TC7129. DGND (pin 36) must be isolated from power

supply ground (see Figure 4-3).

24

External

Logic

TC7129

+5V

36

DGND

I

LOGIC

24

V+

34

23

V-

0.1 µF

TC7129

35

Figure 4-4:

Directly to DGND.

External Logic Referenced

36

DGND

28

33

32

0.1 µF

+

V

IN

V+

24

8

–

V+

2

V–

23

+

10 µF

TC7660

4

5

External

Logic

GND

3

10 µF

+

TC7129

–

Figure 4-3:

a +5V Power Supply.

Powering the TC7129 From

36

+

DGND

I

LOGIC

23

4.3

Connecting to External Logic

External logic can be directly referenced to DGND

(pin 36), provided that the supply current of the external

logic does not exceed the sink current of DGND

(Figure 4-4). A safe value for DGND sink current is

1.2 mA. If the sink current is expected to exceed this

value, a buffer is recommended (see Figure 4-5).

V–

Figure 4-5:

to DGND with Buffer.

External Logic Referenced

4.4

Temperature Compensation

For most applications, V_DISP(pin 19) can be connected

directly to DGND (pin 36). For applications with a wide

temperature range, some LCDs require that the drive

levels vary with temperature to maintain good viewing

angle and display contrast. Figure 4-6 shows two

circuits that can be adjusted to give temperature com-

pensation of about 10 mV/°C between V+ (pin 24) and

V_DISP. The diode between DGND and V_DISPshould

have a low turn-on voltage because V_DISPcannot

exceed 0.3V below DGND.

DS21459D-page 10

TC7129

V+

1N4148

39 kΩ

24

200 kΩ

TC7129

20 kΩ

2N2222

19

TC7129

–

+

19

36

V

DISP

V

DISP

5 kΩ

36

DGND

75 kΩ

18 kΩ

23

V–

Figure 4-6:

Temperature Compensating Circuits.

4.5 RC Oscillator

4.6

Measuring Techniques

For applications in which 3-1/2 digit (100 μV) resolution

is sufficient, an RC oscillator is adequate. A recom-

mended value for the capacitor is 51 pF. Other values

can be used as long as they are sufficiently larger than

the circuit parasitic capacitance. The resistor value is

calculated as:

Two important techniques are used in the TC7129:

successive integration and digital auto-zeroing.

Successive integration is a refinement to the traditional

dual-slope conversion technique.

4.7

Dual-Slope Conversion

EQUATION 4-1:

A dual-slope conversion has two basic phases: inte-

grate and de-integrate. During the integrate phase, the

input signal is integrated for a fixed period of time; the

integrated voltage level is thus proportional to the input

voltage. During the de-integrate phase, the integrated

voltage is ramped down at a fixed slope, and a counter

counts the clock cycles until the integrator voltage

crosses zero. The count is a measurement of the time

to ramp the integrated voltage to zero and is, therefore,

proportional to the input voltage being measured. This

count can then be scaled and displayed as a measure-

ment of the input voltage. Figure 4-8 shows the phases

of the dual-slope conversion.

0.45

R =

Freq * C

For 120 kHz frequency and C = 51 pF, the calculated

value of R is 75 kΩ. The RC oscillator and the crystal

oscillator circuits are shown in Figure 4-7.

TC7129

1

40

2

270 kΩ

10 pF

De-integrate

Integrate

5 pF

120 kHz

V+

Zero

Crossing

TC7129

Time

1

40

2

Figure 4-8:

Dual-Slope Conversion.

75 kΩ

51 pF

The dual-slope method has a fundamental limitation.

The count can only stop on a clock cycle, so that mea-

surement accuracy is limited to the clock frequency. In

addition, a delay in the zero-crossing comparator can

add to the inaccuracy. Figure 4-9 shows these errors in

an actual measurement.

Figure 4-7:

Oscillator Circuits.

DS21459D-page 11

TC7129

De-integrate

Integrate

Overshoot due to zero-crossing between

clock pulses

Time

Integrator Residue Voltage

Overshoot caused by comparator

delay of 1 clock pulse

Clock Pulses

Figure 4-9:

Accuracy Errors in Dual-Slope Conversion.

Zero Integrate

and Latch

INT

DE

1

De-integrate

1

REST X10

DE

REST X10

DE

Zero Integrate

Integrate

2

3

TC7129

Integrator

Note: Shaded area greatly expanded in time and amplitude.

Residual Voltage

Figure 4-10:

Integration Waveform.

DS21459D-page 12

TC7129

4.8

Successive Integration

4.9

Digital Auto-Zeroing

The successive integration technique picks up where

dual-slope conversion ends. The overshoot voltage

shown in Figure 4-9 (called the “integrator residue

voltage”) is measured to obtain a correction to the initial

count. Figure 4-10 shows the cycles in a successive

integration measurement.

To eliminate the effect of amplifier offset errors, the

TC7129 uses a digital auto-zeroing technique. After the

input voltage is measured as described above, the

measurement is repeated with the inputs shorted

internally. The reading with inputs shorted is a

measurement of the internal errors and is subtracted

from the previous reading to obtain a corrected

measurement. Digital auto-zeroing eliminates the need

for an external auto-zeroing capacitor used in other

ADCs.

The waveform shown is for a negative input signal. The

sequence of events during the measurement cycle is

shown in Table 4-1.

TABLE 4-1:

MEASUREMENT CYCLE

SEQUENCE

4.10 Inside the TC7129

Figure 4-11 shows a simplified block diagram of the

TC7129.

Phase

Description

INT

Input signal is integrated for fixed time (1000 clock

cycles on 2V scale, 10,000 on 200 mV).

1

DE

Integrator voltage is ramped to zero. Counter

counts up until zero-crossing to produce reading

accurate to 3-1/2 digits. Residue represents an

overshoot of the actual input voltage.

1

REST Rest; circuit settles.

X10 Residue voltage is amplified 10 times and

inverted.

DE

Integrator voltage is ramped to zero. Counter

counts down until zero-crossing to correct reading

to 4-1/2 digits. Residue represents an undershoot

of the actual input voltage.

2

REST Rest; circuit settles.

X10 Residue voltage is amplified 10 times and

inverted.

DE

Integrator voltage is ramped to zero. Counter

counts up until zero-crossing to correct reading to

5-1/2 digits. Residue is discarded.

3

DS21459D-page 13

TC7129

Low Battery

Continuity

Backplane

Drives

Segment Drives

Annunciator

Drive

TC7129

OSC1

OSC2

OSC3

V

Latch, Decode Display Multiplexer

DISP

Up/Down Results Counter

Sequence Counter/Decoder

Control Logic

RANGE

DP

1

2

L/H

CONT

UR/DP

3

OR/DP

4

V+

V–

Analog Section

REF HI

DGND

REF LO

INT OUT

INT IN

BUFF

COMMON

IN IN

HI LO

Figure 4-11:

TC7129 Functional Block Diagram.

C

REF

R

INT

REF HI

REF LO

DE

X10

Integrator

–

+

10

pF

Comparator 1

INT

1

IN HI

+

To Digital

Section

Buffer

DE-

DE+

DE–

+

–

100 pF

Comparator 2

DE+

ZI, X10

Common

IN LO

INT

REST

INT INT

1

,

2

–

^{500 k}Ω

TC7129

+

–

+

V

Continuity

Comparator

200 mV

Continuity

To Display Driver

Figure 4-12:

Integrator Block Diagram.

DS21459D-page 14

TC7129

4.11 Integrator Section

The integrator section includes the integrator, compar-

ator, input buffer amplifier and analog switches (see

Table 4-2) used to change the circuit configuration

during the separate measurement phases described

earlier. (See Figure 4-12).

–

+

IN HI

COM

Buffer

TABLE 4-2:

SWITCH LEGENDS

Label

Description

Label

DE

Meaning.

TC7129

Open during all de-integrate phases.

IN LO

DE–

Closed during all de-integrate phases when

input voltage is negative.

–

+

^{500 k}Ω

200 mV

V

To Display Driver

(Not Latched)

DE+

Closed during all de-integrate phases when

input voltage is positive.

CONT

INT

Closed during the first integrate phase

(measurement of the input voltage).

1

2

Closed during the second integrate phase

(measurement of the amplifier offset).

Figure 4-13:

Continuity Indicator Circuit.

INT

REST

ZI

Open during both integrate phases.

Closed during the rest phase.

TC7129

Closed during the zero integrate phase.

Closed during the X10 phase.

Open during the X10 phase.

X10

500 kΩ

DP /OR, Pin 20

4

The buffer amplifier has a common mode input voltage

range from 1.5V above V– to 1V below V+. The integra-

tor amplifier can swing to within 0.3V of the rails.

However, for best linearity, the swing is usually limited

to within 1V. Both amplifiers can supply up to 80 μA of

output current, but should be limited to 20 μA for good

linearity.

DP /UR, Pin 21

3

LATCH/HOLD Pin 22

CONTINUITY, Pin 27

Figure 4-14:

Input/Output Pin Schematic.

4.13 Common and Digital Ground

4.12 Continuity Indicator

The common and digital ground (DGND) outputs are

generated from internal Zener diodes. The voltage

between V+ and DGND is the internal supply voltage

for the digital section of the TC7129. Common can

source approximately 12 μA; DGND has essentially no

source capability (see Figure 4-15).

A comparator with a 200 mV threshold is connected

between IN HI (pin 33) and IN LO (pin 32). Whenever

the voltage between inputs is less than 200 mV, the

CONTINUITY output (pin 27) will be pulled high,

activating the continuity annunciator on the display.

The continuity pin can also be used as an input to drive

the continuity annunciator directly from an external

source (see Figure 4-13).

A schematic of the input/output nature of this pin is also

shown in Figure 4-14.

DS21459D-page 15

TC7129

4.17 LATCH/Hold

24

3.2V

28

V+

The L/H output goes low during the last 100 cycles of

each conversion. This pulse latches the conversion

data into the display driver section of the TC7129. This

pin can also be used as an input. When driven high, the

display will not be updated; the previous reading is

displayed. When driven low, the display reading is not

latched; the sequence counter reading will be

displayed. Since the counter is counting much faster

than the backplanes are being updated, the reading

shown in this mode is somewhat erratic.

12 µA

COM

–

N

5V

+

Logic

Section

36

23

DGND

P

TC7129

N

4.18 Display Driver

The TC7129 drives a triplexed LCD with three back-

planes. The LCD can include decimal points, polarity

sign and annunciators for continuity and low battery.

Figure 4-16 shows the assignment of the display

segments to the backplanes and segment drive lines.

The backplane drive frequency is obtained by dividing

the oscillator frequency by 1200. This results in a back-

plane drive frequency of 100 Hz for 60 Hz operation

(120 kHz crystal) and 83.3 Hz for 50 Hz operation

(100 kHz crystal).

V–

Figure 4-15:

Common Outputs.

Digital Ground (DGND) and

4.14 Low Battery

The low battery annunciator turns on when supply volt-

age between V– and V+ drops below 6.8V. The internal

zener diode has a threshold of 6.3V. When the supply

voltage drops below 6.8V, the transistor tied to V– turns

off pulling the “Low Battery” point high.

Backplane waveforms are shown in Figure 4-17.

These appear on outputs BP₁, BP₂, BP₃(pins 16, 17

and 18). They remain the same, regardless of the

segments being driven.

4.15 Sequence and Results Counter

Other display output lines (pins 4 through 15) have

waveforms that vary depending on the displayed

values. Figure 4-18 shows a set of waveforms for the

A, G, D outputs (pins 5, 8, 11 and 14) for several

combinations of “ON” segments.

A sequence counter and associated control logic pro-

vide signals that operate the analog switches in the

integrator section. The comparator output from the inte-

grator gates the results counter. The results counter is

a six-section up/down decade counter that holds the

intermediate results from each successive integration.

The ANNUNCIATOR DRIVE output (pin 3) is a square

wave, running at the backplane frequency (100 Hz or

83.3 Hz) with a peak-to-peak voltage equal to DGND

voltage. Connecting an annunciator to pin 3 turns it on;

connecting it to its backplane turns it off.

4.16 Overrange and Underrange

Outputs

When the results counter holds a value greater than

±19,999, the DP₄/OR output (Pin 20) is driven high.

When the results counter value is less than ±1000, the

DP₃/UR output (Pin 21) is driven high. Both signals are

valid on the falling edge of LATCH/HOLD (L/H) and do

not change until the end of the next conversion cycle.

The signals are updated at the end of each conversion,

unless the L/H input (Pin 22) is held high. Pins 20 and

21 can also be used as inputs for external control of

decimal points 3 and 4. Figure 4-14 shows a schematic

of the input/output nature of these pins.

DS21459D-page 16

TC7129

Low Battery

Continuity

BP

1

2

Backplane

Connections

BP

3

Low Battery

Continuity

F

E

DP

D

4

3

B

1

,

C

Continuity

,

1

,

A

G

4

A

1

,

F

1

,

B

2

,

A

2

,

G

D

,

1

,

B

C

BC

4

3

E

DP

1

,

1

,

F

E

DP

D

3

C

Low Battery

,

2

,

A

G

3

G

E

D

2

3

,

2

,

B

C

MINUS

3

F

2

,

DP

2

3

2

,

Figure 4-16:

Display Segment Assignments.

V

DD

H

b Segment

Line

All Off

BP

1

V

L

DISP

V

DD

H

a Segment

On

d, g Off

BP

2

V

L

DISP

V

DD

H

a, g On

d Off

BP

3

V

L

DISP

V

DD

H

Figure 4-17:

Backplane Waveforms.

All On

V

L

DISP

Figure 4-18:

Typical Display Output

Waveforms.

DS21459D-page 17

TC7129

5.0

PACKAGING INFORMATION

5.1

Package Marking Information

Package marking data not available a this time.

5.2

Taping Forms

User Direction of Feed

W, Width

of C arrier

Tape

P in 1

P , P itch

R everse R eel C omponent Orientation

S tandard R eel C omponent Orientation

Component Taping Orientation for 44-Pin PQFP Devices

User Direction of Feed

Pin 1

W

P

Standard Reel Component Orientation

for 713 Suffix Device

Carrier Tape, Number of Components Per Reel and Reel Size

Package

Carrier Width (W)

Pitch (P)

Part Per Full Reel

Reel Size

44-Pin PQFP

24 mm

16 mm

500

13 in

Note: Drawing does not represent total number of pins.

DS21459D-page 18

TC7129

40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)

E1

D

2

α

n

1

E

A2

A

L

c

B1

B

β

A1

p

eB

Units

INCHES*

NOM

40

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

40

MAX

n

p

Number of Pins

Pitch

.100

2.54

Top to Seating Plane

A

.160

.175

.190

.160

4.06

3.56

4.45

3.81

4.83

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.140

.015

.595

.530

2.045

.120

.008

.030

.014

.620

5

.150

4.06

0.38

15.11

13.46

51.94

3.05

0.20

0.76

0.36

15.75

5

.600

.545

2.058

.130

.012

.050

.018

.650

10

.625

.560

2.065

.135

.015

.070

.022

.680

15

15.24

13.84

52.26

3.30

0.29

1.27

0.46

16.51

10

15.88

14.22

52.45

3.43

0.38

1.78

0.56

17.27

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

§

eB

α

β

Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:

5

10

15

5

10

15

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MO-011

Drawing No. C04-016

DS21459D-page 19

TC7129

44-Lead Plastic Leaded Chip Carrier (LW) – Square (PLCC)

E

E1

#leads=n1

D

D1

n 1 2

CH2 x 45°

CH1 x 45°

α

A3

A2

A

35°

B1

B

c

A1

β

p

E2

D2

Units

INCHES*

NOM

44

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

44

MAX

n

p

Number of Pins

Pitch

.050

1.27

11

Pins per Side

Overall Height

n1

A

11

.173

.153

.028

.029

.045

.005

.690

.653

.620

.011

.029

.020

5

.165

.145

.020

.024

.040

.000

.685

.650

.590

.008

.026

.013

0

.180

4.19

3.68

0.51

0.61

1.02

0.00

17.40

16.51

14.99

0.20

0.66

0.33

0

4.39

3.87

0.71

0.74

1.14

0.13

17.53

16.59

15.75

0.27

0.74

0.51

5

4.57

Molded Package Thickness

A2

A1

A3

CH1

CH2

E

.160

.035

.034

.050

.010

.695

.656

.630

.013

.032

.021

10

4.06

0.89

0.86

1.27

0.25

17.65

16.66

16.00

0.33

0.81

0.53

10

Standoff

§

Side 1 Chamfer Height

Corner Chamfer 1

Corner Chamfer (others)

Overall Width

Overall Length

D

Molded Package Width

Molded Package Length

Footprint Width

E1

D1

E2

D2

c

Footprint Length

Lead Thickness

Upper Lead Width

Lower Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

B1

B

α

β

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MO-047

Drawing No. C04-048

DS21459D-page 20

TC7129

44-Lead Plastic Quad Flatpack (KW) 10x10x2.0 mm Body, 1.95/0.25 mm Lead Form (PQFP)

E

E1

p

D1

D

2

1

B

n

CHAMFER VARIES

α

c

φ

A2

A

β

L

F

A1

Units

INCHES

NOM

MILLIMETERS

*

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

44

.031 BSC

0.80 BSC

Overall Height

A

A2

A1

L

-

.096

.083

-

2.45

2.10

Molded Package Thickness

Standoff

.077

.010

.029

.079

1.95

2.00

§

-

0.25

0.73

-

Foot Length

.035

.077 REF.

3.5°

.547 BSC

.041

0.88

1.95 REF.

3.5°

13.90 BSC

1.03

Footprint

F

φ

Foot Angle

0°

7°

0°

7°

Overall Width

E

D

Overall Length

.547 BSC

.394 BSC

13.90 BSC

10.00 BSC

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

E1

D1

c

.004

.012

-

.009

.018

16°

0.11

0.30

-

0.23

0.45

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

5°

16°

*

Controlling Parameter

§

Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

JEDEC Equivalent: MO-112 AA-1

Drawing No. C04-119

Revised 07-21-05

DS21459D-page 21

TC7129

NOTES:

DS21459D-page 22

TC7129

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

X

XX

Examples:

a) TC7129CPL:

40-Pin PDIP

44-Pin PQFP

Tape and Reel

44-Pin PLCC

Device

Temp.

Pkg

Taping

Direction

b) TC7129CKW713:

c) TC7129CLW:

Device:

TC7129: 4-1/2 Digit Analog-to-Digital Converter

Temperature:

C

I

=

0°C to +70°C

-25°C to +85°C

Package:

PL

KW

LW

JL

=

40-Pin PDIP

40-Pin PQFP

44-Pin PLCC

40-Pin CDIP

Taping Direction:

713 = Standard Taping

DS21459D-page 23

TC7129

NOTES:

DS21459D-page 24

TC7129

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS21459D-page 25

TC7129

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

TC7129

DS21459D

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21459D-page 26

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi,

MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS21459D-page 27

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-5160-8631

Fax: 91-11-5160-8632

China - Chengdu

Tel: 86-28-8676-6200

Fax: 86-28-8676-6599

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Atlanta

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Alpharetta, GA

Tel: 770-640-0034

Fax: 770-640-0307

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shenzhen

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

San Jose

Mountain View, CA

Tel: 650-215-1444

Fax: 650-961-0286

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

02/16/06

DS21459D-page 28


型号：	TC7129CJL
厂家：	MICROCHIP
描述：	1-CH DUAL-SLOPE ADC, CDIP40, CERAMIC, DIP-40 CD 转换器
文件：	总28页 (文件大小：544K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC7129CJL [MICROCHIP]

相关型号：

TC7129CJL713

TC7129CKW

TC7129CKW

TC7129CKW713

TC7129CLW

TC7129CLW

TC7129CLW713

TC7129CPL

TC7129CPL

TC7129CPL713

TC7129IJL

TC7129IJL713