TC510IJE [MICROCHIP]
Precision Analog Front Ends; 精密模拟前端
| 型号： | TC510IJE |
| 厂家： | 
MICROCHIP |
| 描述： | Precision Analog Front Ends |
| 文件： | 总34页 (文件大小：635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC500/A/510/514
Precision Analog Front Ends
Features:
General Description:
• Precision (up to 17 bits) A/D Converter “Front
End”
TheTC500/A/510/514 family are precision analog front
ends that implement dual slope A/D converters having
a maximum resolution of 17 bits plus sign. As a
minimum, each device contains the integrator, zero
crossing comparator and processor interface logic. The
TC500 is the base (16-bit max) device and requires
both positive and negative power supplies. The
TC500A is identical to the TC500 with the exception
that it has improved linearity, allowing it to operate to a
maximum resolution of 17 bits. The TC510 adds an on-
board negative power supply converter for single-
supply operation. The TC514 adds both a negative
power supply converter and a 4-input differential
analog multiplexer.
• 3-Pin Control Interface to Microprocessor
• Flexible: User Can Trade-off Conversion Speed
for Resolution
• Single-Supply Operation (TC510/TC514)
• 4 Input, Differential Analog MUX (TC514)
• Automatic Input Voltage Polarity Detection
• Low Power Dissipation:
- (TC500/TC500A): 10 mW
- (TC510/TC514): 18 mW
• Wide Analog Input Range:
- ±4.2V (TC500A/TC510)
Each device has the same processor control interface
consisting of 3 wires: control inputs (A and B) and zero-
crossing comparator output (CMPTR). The processor
manipulates A, B to sequence the TC5XX through four
phases of conversion: auto-zero, integrate, de-inte-
grate and integrator zero. During the auto-zero phase,
offset voltages in the TC5XX are corrected by a closed
loop feedback mechanism. The input voltage is applied
to the integrator during the integrate phase. This
causes an integrator output dv/dt directly proportional
to the magnitude of the input voltage. The higher the
input voltage, the greater the magnitude of the voltage
stored on the integrator during this phase. At the start
of the de-integrate phase, an external voltage
reference is applied to the integrator and, at the same
time, the external host processor starts its on-board
timer. The processor maintains this state until a
transition occurs on the CMPTR output, at which time
the processor halts its timer. The resulting timer count
is the converted analog data. Integrator zero (the final
phase of conversion) removes any residue remaining
in the integrator in preparation for the next conversion.
• Directly Accepts Bipolar and Differential
Input Signals
Applications:
• Precision Analog Signal Processor
• Precision Sensor Interface
• High Accuracy DC Measurements
The TC500/A/510/514 offer high resolution (up to 17
bits), superior 50/60 Hz noise rejection, low-power
operation, minimum I/O connections, low input bias
currents and lower cost compared to other converter
technologies having similar conversion speeds.
© 2006 Microchip Technology Inc.
DS21428D-page 1
TC500/A/510/514
Package Types
16-Pin PDIP/SOIC/CERDIP
28-Pin PDIP/SOIC
C
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INT
V
–
CAP–
1
2
3
4
5
6
7
8
9
28
OUT
V
DGND
SS
C
27 DGND
26 CAP+
INT
C
CMPTR OUT
AZ
C
AZ
BUF
B
A
V
25
TC500/
BUF
DD
TC500A
ACOM
ACOM
24 OSC
C
C
V
–
+
−
V
V
V
+
–
REF
REF
REF
IN
C
C
V
V
–
23 CMPTR OUT
REF
IN
+
–
22
21
20
19
18
17
A
REF
REF
TC514
+
REF
B
+
A0
REF
24-Pin PDIP/SOIC
CH4– 10
CH3– 11
CH2– 12
CH1– 13
N/C 14
A1
V
–
CAP–
DGND
CAP+
OUT
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
CH1+
CH2+
C
INT
C
AZ
16 CH3+
V
BUF
ACOM
15
DD
CH4+
OSC
C
C
V
V
–
+
–
+
CMPTR OUT
REF
REF
REF
REF
TC510
A
B
V
+
–
IN
IN
V
N/C
N/C
N/C
10
11
12
N/C
N/C
Typical Application
Control Logic
Converter Sate
A
0
0
1
1
B
CINT
RINT
0
1
0
1
Zero Integrator Output
Auto-Zero
CREF
CAZ
Signal Integrate
De-integrate
VREF
-
VREF
+
A1
A0
CINT
CAZ
CREF
+
CREF
-
BUF
TC500
Buffer
-
SWR SWR
Integrator
+
TC500A
TC510
TC514
CH1+
CH2+
CH3+
CH4+
CH1-
CH2-
CH3-
CH4-
SWI
CMPTR 1
+
DIF.
CMPTR 2
+
+
MUX
(TC514)
SWRI-
SWRI
-
Level
Shift
CMPTR
Output
SWZ
SWIZ
SWZ
SWI
Polarity
SWRI
+
SWRI
-
Detection
ACOM
SW1
Analog
Phase
Decoding
Logic
DGND
Switch
Control
Signals
DC-TO-DC
Converter
VSS
(TC510 & TC514)
OSC
VOUT
-
CAP+
CAP-
VSS
A
B
1.0 μF
(TC500
TC500A)
Control Logic
COUT
-
1.0 μF
DS21428D-page 2
© 2006 Microchip Technology Inc.
TC500/A/510/514
† Stresses above those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional
operation of the device at these or any other conditions
above those indicated in the operation sections of the
specifications is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may
affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
TC510/TC514 Positive Supply Voltage
(VDD to GND) .........................................+10.5V
TC500/TC500A Supply Voltage
(VDD to VSS) ..............................................+18V
TC500/TC500A Positive Supply Voltage
(VDD to GND) ............................................+12V
TC500/TC500A Negative Supply Voltage
(VSS to GND)................................................-8V
Analog Input Voltage (VIN+ or VIN-) ............VDD to VSS
Logic Input Voltage...............VDD +0.3V to GND - 0.3V
Voltage on OSC:
........................... -0.3V to (VDD +0.3V) for VDD < 5.5V
Ambient Operating Temperature Range:
................................................................ 0°C to +70°C
Storage Temperature Range:.............-65°C to +150°C
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, TC510/TC514: V = +5V, TC500/TC500A: V = ±5V.
DD
SS
C
= C
= 0.47 μF.
REF
AZ
T
= +25°C
Typ.
T = 0°C to 70°C
A
A
Parameters
Sym
Units
Conditions
Min.
Max.
Min.
Typ.
Max.
Analog
Resolution
60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
μV
Note 1
Zero-scale Error with
Auto-zero Phase
ZSE
ENL
0.005
0.003
0.015
0.010
0.005
0.003
0.015
0.010
0.012
0.009
0.060
0.045
% F.S. TC500/TC510/TC514
TC500A
—
End Point Linearity
0.005
—
% F.S. TC500/TC510/TC514
Note 1, Note 2,
% F.S.
TC500A
Best-Case Straight
Line Linearity
NL
—
0.003
0.008
—
—
—
% F.S. TC500/TC510/TC514,
Note 1, Note 2
—
—
—
—
0.005
—
—
—
—
1
—
2
% F.S. TC500A
Zero-scale Temp.
Coefficient
ZS
μV/°C Over Operating
TC
Temperature Range
Full-scale Symmetry
Error (Rollover Error)
SYE
FS
—
—
0.01
—
—
—
—
—
0.03
10
—
—
% F.S. Note 1
Full-scale
Temperature
Coefficient
ppm/°C Over Operating
Temperature Range;
External Reference
TC = 0 ppm/°C
TC
Input Current
I
—
6
—
—
—
—
—
pA
V
V
= 0V
IN
IN
Common Mode
Voltage Range
V
V
V
V
+ 1.5
—
—
—
V
– 1.5
V
V
+ 1.5
+ 0.9
+ 1.5
V
V
– 1.5
CMR
SS
SS
SS
DD
DD
DD
SS
DD
SS
SS
Integrator Output
Swing
+ 0.9
+ 1.5
V
V
– 0.9
– 1.5
—
—
+ 0.9
+ 1.5
V
V
SS
Analog Input Signal
Range
V
V
ACOM = GND = 0V
SS
Note 1: Integrate time ≥ 66 msec, auto-zero time ≥ 66 msec, V
(peak) ≈ 4V.
INT
2: End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment.
3: Rollover error is related to C , C , C characteristics.
INT REF AZ
© 2006 Microchip Technology Inc.
DS21428D-page 3
TC500/A/510/514
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, TC510/TC514: V = +5V, TC500/TC500A: V = ±5V.
DD
SS
C
= C
= 0.47 μF.
REF
AZ
T
= +25°C
T = 0°C to 70°C
A
A
Parameters
Sym
Units
Conditions
- V
Min.
Typ.
Max.
– 1
Min.
Typ.
Max.
– 1
Voltage Reference
Range
V
V
+1
—
V
V
+1
—
V
V
V
+
REF
REF
SS
DD
SS
DD
REF
Digital
Comparator Logic 1,
Output High
V
4
—
—
—
—
—
4
—
—
—
—
—
V
V
V
V
I
= 400 μA
SOURCE
OH
Comparator Logic 0,
Output Low
V
—
3.5
—
0.4
—
1
—
3.5
—
0.4
—
1
I = 2.1 mA
SINK
OL
Logic 1, Input High
Voltage
V
IH
Logic 0, Input Low
V
IL
Voltage
Logic Input Current
Comparator Delay
I
—
—
—
2
—
—
—
—
0.3
3
μA
Logic ‘1’ or ‘0’
L
t
—
μsec
D
Multiplexer (TC514 Only)
Maximum Input
Voltage
-2.5
—
—
6
2.5
10
-2.5
—
—
—
2.5
—
V
V
V
= 5V
= 5V
DD
Drain/Source ON
Resistance
R
kΩ
DSON
DD
Power (TC510/TC514 Only)
Supply Current
I
—
—
1.8
18
—
2.4
—
—
—
—
—
—
3.5
—
mA
mW
V
V
V
= 5V, A = 1, B = 1
= 5V
S
DD
Power Dissipation
P
D
DD
Positive Supply
Operating Voltage
Range
V
4.5
5.5
4.5
5.5
DD
Operating Source
Resistance
R
—
60
85
—
—
100
Ω
I
= 10 mA
OUT
OUT
OUT
Oscillator Frequency
—
—
100
—
—
—
—
—
—
—
kHz
mA
Note 1
Maximum Current
Out
I
-10
-10
V
= 5V
DD
Power (TC500/TC500A Only)
Supply Current
I
—
—
1
1.5
—
—
—
—
—
—
2.5
—
mA
mW
V
V
V
= ±5V, A = B = 1
S
S
Power Dissipation
P
10
—
= 5V, V = -5V
DD SS
D
Positive Supply
V
4.5
7.5
4.5
7.5
DD
Operating Range
Negative Supply
Operating Range
V
-4.5
—
-7.5
- 4.5
—
-7.5
V
SS
Note 1: Integrate time ≥ 66 msec, auto-zero time ≥ 66 msec, V
(peak) ≈ 4V.
INT
2: End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment.
3: Rollover error is related to C , C , C characteristics.
INT REF AZ
DS21428D-page 4
© 2006 Microchip Technology Inc.
TC500/A/510/514
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-0
5
4
T
A
= +25 C
°
T
= +25 C
°
A
V+ = 5V
-1
-2
-3
-4
3
2
1
0
-1
-2
-3
-4
-5
-5
-6
-7
-8
Slope 60Ω
0
2
4
6
8
10 12 14 16 18 20
0
10
20
30 40
50
Load Current (mA)
60
70
80
Output Current (mA)
FIGURE 2-1:
Output Voltage vs. Load
FIGURE 2-4:
Output Voltage vs. Output
Current.
Current.
200
100
V+ = 5V
I
V+ = 5V, T = +25°C
A
Osc. Freq. = 100 kHz
= 10 mA
175
150
125
100
75
OUT
90
80
70
60
CAP = 1 µF
CAP = 10 µF
50
50
25
40
-50
0
0
25
50
75
100
0
1
2
3
4
5
6
7
8
9
10
-25
Temperature ( C)
°
Load Current (mA)
FIGURE 2-2:
Output Ripple vs. Load
FIGURE 2-5:
Output Source Resistance
Current.
vs. Temperature.
100
150
V+ = 5V
T
= +25°C
A
V+ = 5V
125
100
10
75
50
1
1
10
100
Oscillator Capacitance (pF)
-50
-25
0
25
50
Temperature (°C)
75
100 125
1000
FIGURE 2-3:
Oscillator Frequency vs.
FIGURE 2-6:
Oscillator Frequency vs.
Capacitance.
Temperature.
© 2006 Microchip Technology Inc.
DS21428D-page 5
TC500/A/510/514
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Pin No.
TC500,
TC500A
TC510
TC514
Symbol
Function
1
2
2
C
Integrator output. Integrator capacitor connection.
Negative power supply input (TC500/TC500A only).
Auto-zero input. The auto-zero capacitor connection.
Buffer output. The Integrator capacitor connection.
INT
2
3
4
5
Not Used Not Used
V
SS
3
4
5
3
4
5
C
AZ
BUF
ACOM This pin is grounded in most applications. It is recommended that ACOM and the
input common pin (Ve - or CH -) be within the analog Common Mode Range (CMR).
n
n
6
7
6
7
6
C
-
Input. Negative reference capacitor connection.
Input. Positive reference capacitor connection.
Input. External voltage reference (-) connection.
Input. External voltage reference (+) connection.
Negative analog input.
REF
7
C
+
REF
8
8
8
V
-
REF
9
9
9
Not Used
Not Used
22
V
+
REF
10
11
12
13
15
16
18
17
V -
IN
V
+
Positive analog input.
IN
A
Input. Converter phase control MSB. (See input B.)
21
B
Input. Converter phase control LSB. The states of A, B place the TC5XX in one of
four required phases. A conversion is complete when all four phases have been
executed:
Phase control input pins: AB = 00: Integrator zero
01: Auto-zero
10: Integrate
11: De-integrate
14
19
23
CMPTR Zero crossing comparator output. CMPTR is high during the integration phase when
OUT a positive input voltage is being integrated and is low when a negative input voltage
is being integrated. A high-to-low transition on CMPTR signals the processor that the
De-integrate phase is completed. CMPTR is undefined during the auto-zero phase. It
should be monitored to time the integrator zero phase.
15
16
—
—
—
23
21
22
24
1
27
25
26
28
1
DGND Input. Digital ground.
V
Input. Power supply positive connection.
DD
CAP+ Input. Negative power supply converter capacitor (+) connection.
CAP- Input. Negative power supply converter capacitor (-) connection.
V
-
Output. Negative power supply converter output and reservoir capacitor connection.
This output can be used to power other devices in the circuit requiring a negative
bias voltage.
OUT
—
20
24
OSC Oscillator control input. The negative power supply converter normally runs at a
frequency of 100 kHz. The converter oscillator frequency can be slowed down (to
reduce quiescent current) by connecting an external capacitor between this pin and
V
(see Section 2.0 “Typical Performance Curves”).
DD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18
13
17
12
16
11
15
10
20
19
CH1+ Positive analog input pin. MUX channel 1.
CH1- Negative analog input pin. MUX channel 1.
CH2+ Positive analog input pin. MUX channel 2.
CH2- Negative analog input pin. MUX channel 2.
CH3+ Positive analog input pin. MUX channel 3.
CH3- Negative analog input pin. MUX channel 3.
CH4+ Positive analog input pin. MUX channel 4.
CH4- Negative analog input pin. MUX channel 4
A0
A1
Multiplexer input channel select input LSB (see A1).
Multiplexer input channel select input MSB.
Phase control input pins: A1, A0 = 00 = Channel 1
01 = Channel 2
10 = Channel 3
11 = Channel 4
DS21428D-page 6
© 2006 Microchip Technology Inc.
TC500/A/510/514
multiples of the integration period are, theoretically,
completely removed, since the average value of a sine
wave of frequency (1/T) averaged over a period (T) is
zero.
4.0
4.1
DETAILED DESCRIPTION
Dual Slope Conversion Principles
Actual data conversion is accomplished in two
phases: input signal integration and reference voltage
de-integration.
Integrating converters often establish the integration
period to reject 50/60 Hz line frequency interference
signals. The ability to reject such signals is shown by a
normal mode rejection plot (Figure 4-1). Normal mode
rejection is limited in practice to 50 to 65 dB, since the
line frequency can deviate by a few tenths of a percent
(Figure 4-2).
The integrator output is initialized to 0V prior to the start
of integration. During integration, analog switch S1 con-
nects VIN to the integrator input where it is maintained
for a fixed time period (TINT). The application of VIN
causes the integrator output to depart 0V at a rate deter-
mined by the magnitude of VIN and a direction deter-
mined by the polarity of VIN. The de-integration phase is
30
Measurment
T =
Period
initiated immediately at the expiration of TINT
.
During de-integration, S1 connects a reference voltage
(having a polarity opposite that of VIN) to the integrator
input. At the same time, an external precision timer is
started. The de-integration phase is maintained until
the comparator output changes state, indicating the
integrator has returned to its starting point of 0V. When
this occurs, the precision timer is stopped. The de-
integration time period (TDEINT), as measured by the
precision timer, is directly proportional to the magnitude
of the applied input voltage (see Figure 4-3).
20
10
0
0.1/T
1/T
Input Frequency
10/T
A simple mathematical equation relates the input
signal, reference voltage and integration time:
FIGURE 4-1:
Normal Mode Rejection.
Integrating Converter
EQUATION 4-1:
80
70
60
50
VREFCDEINT
TINT
1
-----------------------
--------------------------------
VIN(T)DT =
∫
0
RINTCINT
RINTCINT
t = 0.1 sec
Where:
VREF = Reference Voltage
TINT = Signal Integration time (fixed)
tDEINT = Reference Voltage Integration time (variable)
40
DEV
SIN 60p t (1
60p t (1
)
100
DEV
100
For a constant VIN:
Normal Mode = 20 LOG
REJECTION
)
30
DEV = Deviation from 60 Hz
t = Integration Period
EQUATION 4-2:
20
0.01
Line Frequency Deviation from 60 Hz (%)
TDEINT
0.1
1.0
-----------------
VIN = VREF
TINT
FIGURE 4-2:
Line Frequency Deviation.
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle.
An inherent benefit is noise immunity. Input noise
spikes are integrated (averaged to zero) during the
integration periods. Integrating ADCs are immune to
the large conversion errors that plague successive
approximation converters in high noise environments.
Integrating converters provide inherent noise rejection
with at least
a 20dB/decade attenuation rate.
Interference signals with frequencies at integral
© 2006 Microchip Technology Inc.
DS21428D-page 7
TC500/A/510/514
CINT
TC510
Integrator
–
RINT
Analog
VINT
Input (VIN)
Comparator
–
+
CMPTR Out
+
S1
±
Phase
Control
Switch Driver
Ref
Voltage
Control
Logic
Polarity Control
A
B
I/O
Microcomputer
VSUPPLY
VINT
VIN ≈ VREF
VIN ≈ 1/2 VREF
ROM
RAM
Timer
Counter
TINT
FIGURE 4-3:
TDEINT
Basic Dual Slope Converter.
DS21428D-page 8
© 2006 Microchip Technology Inc.
TC500/A/510/514
The internal analog switch status for each of these
phases is summarized in Table 5-1. This table
references the Typical Application.
5.0
TC500/A/510/514 CONVERTER
OPERATION
The TC500/A/510/514 incorporates an auto-zero and
Integrator phase in addition to the input signal Integrate
and reference De-integrate phases. The addition of
these phases reduce system errors, calibration steps
and shorten overrange recovery time. A typical
measurement cycle uses all four phases in the
following order:
1. Auto-zero.
2. Input signal integration.
3. Reference de-integration.
4. Integrator output zero.
TABLE 5-1:
INTERNAL ANALOG GATE STATUS
Conversion Phase
SWI
SWR+
SWR-
SWZ
SWR
SW1
SWIZ
Auto-zero (A = 0, B = 1)
—
—
—
—
—
Closed
—
Closed
—
Closed
—
—
—
Input Signal Integration (A = 1, B = 0)
Closed
Reference Voltage De-integration
(A =1, B = 1)
*
—
—
Closed
—
—
—
—
—
Closed
—
Integrator Output Zero (A = 0, B = 0)
—
Closed
Closed Closed
* Assumes a positive polarity input signal. SW–RI would be closed for a negative input signal.
5.1
Auto-zero Phase (AZ)
5.3
Reference Voltage De-integration
Phase (D
)
INT
During this phase, errors due to buffer, integrator and
comparator offset voltages are nulled out by charging
CAZ (auto-zero capacitor) with a compensating error
voltage.
The previously charged reference capacitor is
connected with the proper polarity to ramp the
integrator output back to zero. An externally-provided,
precision timer is used to measure the duration of this
phase. The resulting time measurement is proportional
to the magnitude of the applied input voltage.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to analog common. The
reference capacitor is charged to the reference voltage
potential through SWR. A feedback loop, closed around
the integrator and comparator, charges the capacitor
(CAZ) with a voltage to compensate for buffer amplifier,
integrator and comparator offset voltages.
5.4
Integrator Output Zero Phase (IZ)
This phase ensures the integrator output is at 0V when
the auto-zero phase is entered, and that only system
offset voltages are compensated. This phase is used at
the end of the reference voltage de-integration phase
and MUST be used for ALL TC5XX applications having
resolutions of 12-bits or more. If this phase is not used,
the value of the auto-zero capacitor (CAZ) must be
about 2 to 3 times the value of the integration capacitor
(CINT) to reduce the effects of charge sharing. The inte-
grator output zero phase should be programmed to
operate until the output of the comparator returns high.
The overall timing system is shown in Figure 5-1.
5.2
Analog Input Signal Integration
Phase (INT)
The TC5XX integrates the differential voltage between
the VIN+ and VIN– inputs. The differential voltage must
be within the device’s Common mode range VCMR. The
input signal polarity is normally checked via software at
the end of this phase: CMPTR = 1 for positive polarity;
CMPTR = 0 for negative polarity.
© 2006 Microchip Technology Inc.
DS21428D-page 9
TC500/A/510/514
TTIME
Converter Status
Auto-zero
Integrate
Reference
Overshoot Integrator
De-integrate
Output
Zero
Full-scale Input
Integrator
0
Voltage VINT
Comparator Delay
Undefined
Comparator
Output
0 For Negative Input
1 For Positive Input
A
A = 1
B = 1
A = 1
B = 0
A = 0
B = 1
A = 0
B = 0
AB Inputs
B
Begin Conversion with
Auto-Zero Phase
Time Input
Integration
Phase
Capture
De-integration
Time
Integrator
Output
Zero Phase (Auto-Zero is
Ready for Next
Conversion
Controller
Operation
Complete
Idle State)
Sample Input Polarity
TINT
Minimizing
Overshoot
will Minimize
I.O.Z. Time
Typically = TINT
Comparator Delay +
Processor Latency
(Positive Input Shown)
Notes: The length of this phase is chosen almost arbitrarily
but needs to be long enough to null out worst case errors
(see text).
FIGURE 5-1:
Typical Dual Slope A/D Converter System Timing.
DS21428D-page 10
© 2006 Microchip Technology Inc.
TC500/A/510/514
The difference in reference for (+) or (-) input voltages
will cause a rollover error. This error can be minimized
by using a large reference capacitor in comparison to
the stray capacitance.
6.0
6.1
ANALOG SECTION
Differential Inputs (VIN+, VIN–)
The TC5XX operates with differential voltages within
the input amplifier Common mode range. The amplifier
Common mode range extends from 1.5V below
positive supply to 1.5V above negative supply. Within
this Common mode voltage range, Common mode
rejection is typically 80 dB. Full accuracy is maintained,
however, when the inputs are no less than 1.5V from
either supply.
6.4
Phase Control Inputs (A, B)
The A, B unlatched logic inputs select the TC5XX
operating phase. The A, B inputs are normally driven
by a microprocessor I/O port or external logic.
6.5
Comparator Output
The integrator output also follows the Common mode
voltage. The integrator output must not be allowed to
saturate. A worst-case condition exists, for example,
when a large, positive Common mode voltage, with a
near full-scale negative differential input voltage, is
applied. The negative input signal drives the integrator
positive when most of its swing has been used up by
the positive Common mode voltage. For these critical
applications, the integrator swing can be reduced. The
integrator output can swing within 0.9V of either supply
without loss of linearity.
By monitoring the comparator output during the fixed
signal integrate time, the input signal polarity can be
determined by the microprocessor controlling the
conversion. The comparator output is high for positive
signals and low for negative signals during the signal
integrate phase (see Figure 6-1).
During the reference de-integrate phase, the
comparator output will make a high-to-low transition as
the integrator output ramp crosses zero. The transition
is used to signal the processor that the conversion is
complete.
The internal comparator delay is 2 μsec, typically.
Figure 6-1 shows the comparator output for large
positive and negative signal inputs. For signal inputs at
or near zero volts, however, the integrator swing is very
small. If Common mode noise is present, the
comparator can switch several times during the
beginning of the signal integrate period. To ensure that
the polarity reading is correct, the comparator output
should be read and stored at the end of the signal
integrate phase.
6.2
Analog Common
Analog common is used as VIN return during system
zero and reference de-integrate. If VIN– is different from
analog common, a Common mode voltage exists in the
system. This signal is rejected by the excellent CMR of
the converter. In most applications, VIN– will be set at a
fixed known voltage (i.e., power supply common). A
Common mode voltage will exist when VIN– is not
connected to analog common.
The comparator output is undefined during the auto-
zero phase and is used to time the integrator output
zero phase. (See Section 8.6 “Integrator Output Zero
Phase”).
6.3
Differential Reference
(VREF+, VREF–)
The reference voltage can be anywhere within 1V of
the power supply voltage of the converter. Rollover
error is caused by the reference capacitor losing or
gaining charge due to stray capacitance on its nodes.
Signal
Integrate
Reference
Deintegrate
Signal
Integrate
Reference
De-integrate
Integrator
Output
Zero
Crossing
Integrator
Output
Zero
Crossing
Comparator
Output
Comparator
Output
A. Positive Input Signal
B. Negative Input Signal
FIGURE 6-1:
Comparator Output.
© 2006 Microchip Technology Inc.
DS21428D-page 11
TC500/A/510/514
TABLE 7-1:
CREF AND CAZ SELECTION
7.0
7.1
TYPICAL APPLICATIONS
Component Value Selection
Conversions
Per Second
Typical Value of
, C (μF)
Suggested* Part
Number
C
REF AZ
>7
0.1
SMR5 104K50J01L4
SMR5 224K50J02L4
SMR5 474K50J04L4
The procedure outlined below allows the user to arrive
at values for the following TC5XX design variables:
2 to 7
0.22
0.47
2 or less
1. Integration Phase Timing.
* Manufactured by Evox Rifa, Inc.
2. Integrator Timing Components (RINT, CINT).
3. Auto-zero and Reference Capacitors.
4. Voltage Reference.
7.6
Calculate Integrating Capacitor
(C
)
INT
7.2
Select Integration Time
The integrating capacitor must be selected to maximize
integrator output voltage swing. The integrator output
voltage swing is defined as the absolute value of VDD
(or VSS) less 0.9V (i.e., IVDD - 0.9VI or IVSS + 0.9VI).
Using the 20 μA buffer maximum output current, the
value of the integrating capacitor is calculated using the
following equation.
Integration time must be picked as a multiple of the
period of the line frequency. For example, TINT times of
33 msec, 66 msec and 132 msec maximize 60 Hz line
rejection.
7.3
DINT and IZ Phase Timing
EQUATION 7-2:
The duration of the DINT phase is a function of the
amount of voltage stored on the integrator during TINT
and the value of VREF. The DINT phase must be initiated
immediately following INT and terminated when an inte-
grator output zero-crossing is detected. In general, the
maximum number of counts chosen for DINT is twice
that of INT (with VREF chosen at VIN(MAX) /2).
(TINT)(20 × 10–6
)
--------------------------------------------
=
CINT
(VS – 0.9)
Where:
TINT = Integration Period
VS = IVDDI or IVSSI, whichever is less (TC500/A)
VS = IVDDI (TC510, TC514)
7.4
Calculate Integrating Resistor
(R
)
INT
It is critical that the integrating capacitor has a very low
dielectric absorption. Polypropylene capacitors are an
example of one such dialectic. Polyester and poly-
bicarbonate capacitors may also be used in less critical
applications. Table 7-2 summarizes recommended
The desired full-scale input voltage and amplifier output
current capability determine the value of RINT. The
buffer and integrator amplifiers each have a full-scale
current of 20 μA.
The value of RINT is, therefore, directly calculated in the
following equation:
capacitors for CINT
.
TABLE 7-2:
RECOMMENDED CAPACITOR
FOR CINT
EQUATION 7-1:
Suggested
Part Number*
VIN(MAX)
Value
----------------------
RINT(in MΩ) =
20
Where:
0.1
SMR5 104K50J01L4
SMR5 224K50J02L4
SMR5 334K50J03L4
SMR5 474K50J04L4
0.22
0.33
0.47
VIN(MAX) = Maximum input voltage (full count voltage)
RINT = Integrating Resistor (in MΩ)
For loop stability, RINT should be ≥ 50 kΩ.
* Manufactured by Evox Rifa, Inc.
7.5
Select Reference (C
) and Auto-
REF
7.7
Calculate V
REF
zero (C ) Capacitors
AZ
The reference de-integration voltage is calculated
using the following equation:
CREF and CAZ must be low leakage capacitors (such as
polypropylene). The slower the conversion rate, the
larger the value CREF must be. Recommended
capacitors for CREF and CAZ are shown in Table 7-1.
Larger values for CAZ and CREF may also be used to
limit rollover errors.
EQUATION 7-3:
(VS – 0.9)(CINT)(RINT
----------------------------------------------------------
V
)
VREF
=
2(RINT
)
DS21428D-page 12
© 2006 Microchip Technology Inc.
TC500/A/510/514
8.4
Input Signal Integrate Phase
8.0
8.1
DESIGN CONSIDERATIONS
Noise
The length of this phase is constant from one
conversion to the next and depends on system
parameters and component value selections. The
calculation of TINT is shown elsewhere in this data
sheet. At some point near the end of this phase, the
microcontroller should sample CMPTR to determine
the input signal polarity. This value is, in effect, the Sign
Bit for the overall conversion result. Optimally, CMPTR
should be sampled just before this phase is terminated
by changing AB from 10 to 11. The consideration here
is that, during the initial stage of input integration when
the integrator voltage is low, the comparator may be
affected by noise and its output unreliable. Once
integration is well underway, the comparator will be in a
defined state.
The threshold noise (NTH) is the algebraic sum of the
integrator and comparator noise and is typically 30 μV.
Figure 8-1 illustrates how the value of the reference
voltage can affect the final count. Such errors can be
reduced by increased integration times, in the same
way that 50/60 Hz noise is rejected. The signal-to-
noise ratio is related to the integration time (TINT) and
the integration time constant (RINT, CINT) as follows:
EQUATION 8-1:
VIN
tINT
(RINT) • (CINT
⎛
⎜
⎝
⎞
⎟
⎠
---------------------- --------------------------------------
S/N (dB) = 20 log
•
–6
)
30 × 10
8.5
Reference De-integration
8.2
System Timing
The length of this phase must be precisely measured
from the transition of AB from 10 to 11 to the falling-
edge of CMPTR. The comparator delay contributes
some error in timing this phase. The typical delay is
specified to be 2 μsec. This should be considered in the
context of the length of a single count when
determining overall system performance and possible
single count errors. Additionally, overshoot will result in
charge accumulating on the integrator once its output
crosses zero. This charge must be nulled during the
integrator output zero phase.
To obtain maximum performance from the TC5XX, the
overshoot at the end of the de-integration phase must
be minimized. Also, the integrator output zero phase
must be terminated as soon as the comparator output
returns high (see Figure 5-1).
Figure 5-1 shows the overall timing for a typical system
in which a TC5XX is interfaced to a microcontroller. The
microcontroller drives the A, B inputs with I/O lines and
monitors the comparator output (CMPTR) using an I/O
line or dedicated timer capture control pin. It may be
necessary to monitor the state of the CMPTR output in
addition to having it control a timer directly for the
Reference de-integration phase (this is further
explained below.)
The timing diagram in Figure 5-1 is not to scale, as the
timing in a real system depends on many system
parameters and component value selections. There
are four critical timing events (as shown in Figure 5-1):
sampling the input polarity, capturing the de-integration
time, minimizing overshoot and properly executing the
integrator output zero phase.
8.3
Auto-zero Phase
The length of this phase is usually set to be equal to the
input signal integration time. This decision is virtually
arbitrary since the magnitudes of the various system
errors are not known. Setting the auto-zero time equal
to the Input Integrate time should be more than
adequate to null out system errors. The system may
remain in this phase indefinitely (i.e., auto-zero is the
appropriate Idle state for a TC5XX device).
© 2006 Microchip Technology Inc.
DS21428D-page 13
TC500/A/510/514
S
S
S
30V
NTH
NTH
NTH
High VREF
Normal VREF
Low VREF
VREF
RINT CINT
Slope (S) =
NTH = Noise Threshold
FIGURE 8-1:
Noise Threshold.
8.6 Integrator Output Zero Phase
8.7
Using the TC510/TC514
The comparator delay and the controller’s response
latency may result in overshoot, causing charge
buildup on the integrator at the end of a conversion.
This charge must be removed or performance will
degrade. The integrator output zero phase should be
activated (AB = 00) until CMPTR goes high. It is
absolutely critical that this phase be terminated
immediately so that overshoot is not allowed to occur in
the opposite direction. At this point, it can be assured
that the integrator is near zero. Auto-zero should be
entered (AB = 01) and the TC5XX held in this state until
the next cycle is begun (see Figure 8-2).
8.7.1
NEGATIVE SUPPLY VOLTAGE
CONVERTER (TC510, TC514)
A capacitive charge pump is employed to invert the
voltage on VDD for negative bias within the TC510/
TC514. This voltage is also available on the VOUT- pin
to provide negative bias elsewhere in the system. Two
external capacitors are required to perform the
conversion.
Timing is generated by an internal state machine driven
from an on-board oscillator. During the first phase,
capacitor CF is switched across the power supply and
charged to VS+. This charge is transferred to capacitor
COUT- during the second phase. The oscillator normally
runs at 100 kHz to ensure minimum output ripple. This
frequency can be reduced by placing a capacitor from
OSC to VDD. The relationship between the capacitor
value is shown in Section 2.0 “Typical Performance
Curves”.
Integrator
Output
Zero
Crossing
Overshoot
8.7.2
ANALOG INPUT MULTIPLEXER
(TC514)
Comparator
Output Comp
The TC514 is equipped with a four-input differential
analog multiplexer. Input channels are selected using
select inputs (A1, A0). These are high-true control
signals (i.e., channel 0 is selected when (A1, A0 = 00).
De-integrate Phase
Integrator
Zero Phase
Integrate
Phase
FIGURE 8-2:
Overshoot.
DS21428D-page 14
© 2006 Microchip Technology Inc.
TC500/A/510/514
9.0
DESIGN EXAMPLES
Refer to Figures 9-1 to 9-4.
Given:
Required Resolution: 16 bits (65,536
counts).
Maximum VIN: ±2V
Power Supply Voltage: +5V
60 Hz System
Step 1.
Pick integration time (tINT) as a multiple
of the line frequency:
1/60 Hz = 16.6 msec. Use 4x line
frequency.
= 66 msec
Step 2.
Step 3.
Calculate RINT
INT = VIN(MAX) /20 μA 2 /20 μA
= 100 kΩ
:
R
Calculate CINT for maximum (4V)
integrator output swing.
CINT = (tINT) (20 x 10 –6) / (VS - 0.9)
= (.066) (20 x 10 –6) / (4.1)
= 0.32 μF (use closest value: 0.33 μF)
Note:
Microchip recommended capacitor:
Evox Rifa p/n: 5MR5 334K50J03L4.
Step 4.
Choose CREF and CAZ based on
conversion rate.
Conversions/sec:
= 1/(TAZ + TINT + 2 TINT + 2 msec)
= 1/(66 msec +66 msec
+132 msec +2 msec)
= 3.7 conversions/sec
From which CAZ = CREF = 0.22 μF
(see Table 7-1)
Note:
Microchip recommended capacitor:
Evox Rifa p/n: 5MR5 224K50J02L4
Step 5.
Calculate VREF
:
EQUATION 9-1:
(VS – 0.9)(CINT)(RINT
)
----------------------------------------------------------
=
VREF
2(TINT
)
= (4.1)(0.33 × 1–6)(105)
--------------------------------------------------------------
2(0.66)
= 1.025
© 2006 Microchip Technology Inc.
DS21428D-page 15
TC500/A/510/514
24
23
1
CAP-
VOUT
-
CINT
0.33 μF
1 μF
Typical Waveforms
Pin 2
2
DGND
CINT
+5V
1 μF
CAZ
0.22 μF
TC510
22
21
3
CAP+
VDD
CAZ
VIN
+
4
+5V
+5V
BUF
RINT
PICmicro®
Microcontroller
Pin 19
100 kΩ
5
6
ACOM
19
MCP1525
CMPTR
CREF
-
CREF
0.22 μF
R2
Pin 2
-
18
17
7
9
8
10 kΩ
R3, 10 kΩ
CREF
VREF
VREF
+
A
B
VIN
1 μF
Pin 19
+
-
16
15
C1
VIN+
INPUT+
INPUT-
0.01 μF
VIN
-
FIGURE 9-1:
TC510 Design Sample.
1
28
27
VOUT
-
CAP-
CINT
0.33 μF
1 μF
2
CINT
DGND
1 μF
+5V
CAZ
26
25
0.22 μF
3
4
CAP+
VDD
CAZ
+5V
TC514
+5V
BUF
RINT
22
19
23
A0
100 kΩ
PICmicro®
Microcontroller
Analog
Mux Logic
5
6
ACOM
A1
MCP1525
CMPTR
CREF
-
CREF
0.22 μF
10 kΩ
R3, 10 kΩ
R2
22
21
7
9
8
A
B
CREF
VREF
VREF
+
1 μF
+
-
18
13
C1
0.01 μF
CH1+
CH1-
INPUT 1+
INPUT 1-
Typical Waveforms
17
12
CH2+
CH2-
CH3+
CH3-
INPUT 2+
INPUT 2-
PIN 2
VIN
+
16
11
INPUT 3+
INPUT 3-
PIN 23
15
10
CH4+
CH4-
INPUT4+
INPUT4-
PIN 2
-
VIN
PIN 23
FIGURE 9-2:
TC514 Design Example.
DS21428D-page 16
© 2006 Microchip Technology Inc.
TC500/A/510/514
+5V
21
1
1 μF
VDD VOUT
-
24
CAP-
1 μF
22
7
CAP+
CREF
CREF
VREF
+
0.22 μF
0.01 μF
10 kΩ
10 kΩ
6
9
-
MCP1525
+
1 μF
TC510
8
VREF
-
100 kΩ
0.22 μF
PC
Printer
Port
4
BUF
CAZ
18
17
3
2
A
B
PORT
0378
Hex
0.33 μF
100 kΩ
3
2
CINT
VIN+
10
19
16
CMPTR
+
0.01 μF
Input
15
5
VIN-
–
ACOM
DGND
23
FIGURE 9-3:
TC510 To IBM® Compatible Printer Port.
© 2006 Microchip Technology Inc.
DS21428D-page 17
TC500/A/510/514
+5V
25
V
DD
1
28
26
1 μF
1 μF
18
VOUT
+
CH1+
CAP–
CAP+
Input 1
–
13
17
10 kΩ
CH1–
CH2+
+
Input 2
–
7
6
12
16
11
CREF
+
MCP1525
CH2–
CH3+
CH3–
0.22 μF
0.01 μF
+
CREF
-
10 kΩ
10 kΩ
Input 3
–
9
8
15
10
VREF
+
CH4+
+
Input 4
CH4– TC514
–
VREF
-
20
A0
Analog
Mux Control Logic
19
22
21
23
100 kΩ
IBM®
Printer Port
2
A1
4
3
BUF
CAZ
A
Port
0.22 μF
0.33 μF
2
3
0378
CINT
B
Hex
10
CMPTR
5
ACOM
DGND
27
FIGURE 9-4:
TC514 To IBM® Compatible Printer Port.
DS21428D-page 18
© 2006 Microchip Technology Inc.
TC500/A/510/514
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
16-Lead CERDIP (300 mil)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
TC500AIJE
0441256
YYWWNNN
16-Lead PDIP (300 mil)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
TC500CPE
0441256
YYWWNNN
16-Lead SOIC (300 mil)
Example:
XXXXXXXXXXXXX
XXXXXXXXXXXXX
TC500ACOE
0441256
YYWWNNN
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters for cus-
tomer specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code.
For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
© 2006 Microchip Technology Inc.
DS21428D-page 19
TC500/A/510/514
Package Marking Information (Continued)
24-Lead PDIP (300 mil)
Example:
Example:
XXXXXXXXXXXXX
YYWWNNN
TC510CPF
0441256
24-Lead SOIC (300 mil)
XXXXXXXXXXXXX
XXXXXXXXXXXXX
TC510COG
0441256
YYWWNNN
28-Lead PDIP (300 mil)
Example:
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
TC514CPJ
0441256
YYWWNNN
28-Lead SOIC (300 mil)
XXXXXXXXXXXXX
XXXXXXXXXXXXX
XXXXXXXXXXXXX
TC514COI
0441256
YYWWNNN
DS21428D-page 20
© 2006 Microchip Technology Inc.
TC500/A/510/514
16-Lead Ceramic Dual In-line (JE) – 300 mil (CERDIP)
E1
D
2
n
1
E
A2
A
L
c
A1
B1
eB
B
p
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
18
18
.100
.180
.030
.305
.288
.760
.163
.012
.055
.018
.360
2.54
4.57
0.76
7.75
7.32
19.30
4.14
0.30
1.40
0.46
9.14
Top to Seating Plane
Standoff §
A
.160
.200
4.06
5.08
A1
.015
.290
.280
.752
.125
.008
.045
.015
.325
.040
.325
.296
.780
.200
.014
.065
.021
.410
0.38
7.37
7.11
19.10
3.18
0.20
1.14
0.38
8.25
1.02
8.25
7.52
19.81
5.08
0.36
1.65
0.53
10.41
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
Tip to Seating Plane
Lead Thickness
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
*Controlling Parameter
JEDEC Equivalent: MS-030
Drawing No. C04-003
eB
© 2006 Microchip Technology Inc.
DS21428D-page 21
TC500/A/510/514
16-Lead Plastic Dual In-line (PE) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
A1
β
B1
eB
p
B
Units
INCHES
*
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
MIN
NOM
16
MAX
n
p
Number of Pins
16
.100
Pitch
2.54
3.94
3.30
Top to Seating Plane
A
A2
A1
E
.140
.155
.130
.170
3.56
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
.145
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
.036
7.87
3.68
.313
.250
.750
.130
.012
.058
.018
.370
.325
.260
.760
.135
.015
.070
.022
.430
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
8.26
6.60
E1
D
19.30
3.43
Tip to Seating Plane
Lead Thickness
L
c
0.38
Upper Lead Width
B1
B
1.78
Lower Lead Width
0.56
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
eB
α
10.92
5
5
10
10
15
15
5
10
10
15
15
β
5
*
Controlling Parameter
Notes
:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-017
Revised 07-21-05
DS21428D-page 22
© 2006 Microchip Technology Inc.
TC500/A/510/514
16-Lead Plastic Small Outline (OE) – Wide, 300 mil (SOIC)
E
p
E1
D
2
n
1
B
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
16
MAX
MIN
NOM
16
MAX
n
p
Number of Pins
Pitch
.050
.099
1.27
Overall Height
A
.093
.104
2.36
2.50
2.31
0.20
10.34
7.49
10.30
0.50
0.84
4
2.64
Molded Package Thickness
A2
A1
E
.088
.004
.394
.291
.398
.010
.016
0
.091
.008
.407
.295
.406
.020
.033
4
.094
.012
.420
.299
.413
.029
.050
8
2.24
0.10
10.01
7.39
10.10
0.25
0.41
0
2.39
0.30
10.67
7.59
10.49
0.74
1.27
8
Standoff
§
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
E1
D
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-102
© 2006 Microchip Technology Inc.
DS21428D-page 23
TC500/A/510/514
24-Lead Skinny Plastic Dual In-line (PF) – 300 mil (PDIP)
E1
D
2
1
n
α
E
A2
A
L
c
A1
B1
p
β
eB
B
Units
INCHES
*
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
MIN
NOM
24
MAX
n
p
Number of Pins
Pitch
24
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.115
.015
.295
.240
1.245
.120
.008
.045
.014
.310
5
.160
.145
3.56
2.92
0.38
7.49
6.10
31.62
3.05
0.20
1.14
0.36
7.87
5
4.06
3.68
.310
.250
1.250
.125
.012
.053
.018
.370
10
.325
.260
1.255
.130
.015
.060
.022
.430
15
7.87
6.35
31.75
3.18
0.29
1.33
0.46
9.40
10
8.26
6.60
31.88
3.30
0.38
1.52
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
eB
α
β
5
10
15
5
10
15
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MS-001 AF
Drawing No. C04-043
Revised 09-14-05
DS21428D-page 24
© 2006 Microchip Technology Inc.
TC500/A/510/514
24-Lead Plastic Small Outline (OG) – Wide, 300 mil (SOIC)
E
E1
e
D
B
2
n
1
α
h
h
c
A
φ
β
L
A1
A2
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
e
Number of Pins
Pitch
24
24
.050 BSC
--
1.27 BSC
Overall Height
A
.093
.104
2.35
--
2.65
Molded Package Thickness
Standoff
A2
A1
E
.081
.004
--
--
.100
.012
2.05
0.10
--
2.55
0.30
--
10.30 BSC
7.50 BSC
15.40 BSC
--
Overall Width
.406 BSC
Molded Package Width
Overall Length
E1
D
.295 BSC
.607 BSC
Chamfer Distance
Foot Length
h
.010
.016
--
.030
.050
0.25
0.40
0.75
1.27
L
φ
--
--
--
--
--
--
--
Foot Angle
0°
8°
0°
--
--
--
--
--
8°
c
Lead Thickness
Lead Width
.008
.012
.013
.020
0.20
0.31
0.33
0.51
15°
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
5°
5°
15°
15°
5°
5°
15°
*
Controlling Parameter per JEDEC MS-103 Revision C.
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEDEC Equivalent: MS-013 AD
Drawing No. C04-025
Revised 07-19-05
© 2006 Microchip Technology Inc.
DS21428D-page 25
TC500/A/510/514
28-Lead Skinny Plastic Dual In-line (PJ) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
p
B
Units
INCHES*
NOM
28
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
.100
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.150
.130
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
§
eB
α
5
β
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
5
10
15
5
10
15
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
DS21428D-page 26
© 2006 Microchip Technology Inc.
TC500/A/510/514
28-Lead Plastic Small Outline (OI) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
28
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
.050
1.27
Overall Height
A
.093
.099
.091
.008
.407
.295
.704
.020
.033
4
.104
2.36
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
2.64
Molded Package Thickness
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
Standoff
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
c
Foot Angle Top
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
© 2006 Microchip Technology Inc.
DS21428D-page 27
TC500/A/510/514
10.2 Product Tape and Reel Specifications
Component Taping Orientation for 16-Pin SOIC (Wide) Devices
User Direction of Feed
Pin 1
W
P
Standard Reel Component Orientation
for 713 Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
16-Pin SOIC (W)
16 mm
12 mm
1000
13 in
Component Taping Orientation for 24-Pin SOIC (Wide) Devices
User Direction of Feed
Pin 1
W
P
Standard Reel Component Orientation
for 713 Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
24-Pin SOIC (W)
24 mm
12 mm
1000
13 in
DS21428D-page 28
© 2006 Microchip Technology Inc.
TC500/A/510/514
Product Tape and Reel Specifications (Continued)
Component Taping Orientation for 28-Pin SOIC (Wide) Devices
User Direction of Feed
Pin 1
W
P
Standard Reel Component Orientation
for 713 Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
Carrier Width (W)
Pitch (P)
Part Per Full Reel
1000
Reel Size
28-Pin SOIC (W)
24 mm
12 mm
13 in
© 2006 Microchip Technology Inc.
DS21428D-page 29
TC500/A/510/514
NOTES:
DS21428D-page 30
© 2006 Microchip Technology Inc.
TC500/A/510/514
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
Examples:
Temperature
Range
Package
a)
b)
TC500ACOE:
Commercial Temp.,
16LD SOIC package.
TC500ACOE713: Commercial Temp.,
16LD SOIC package,
Tape and Reel.
Device
TC500 16 Bit Analog Processor
TC500A 16 Bit Analog Processor
TC510 Precision Analog Front End
TC514 Precision Analog Front End
c)
d)
TC500ACPE:
TC500AIJE:
Commercial Temp.,
16LD PDIP package.
Industrial Temp.,
16LD CERDIP package.
a)
b)
TC500COE:
Commercial Temp.,
16LD SOIC package.
Commercial Temp.,
16LD SOIC package,
Tape and Reel.
Commercial Temp.,
16LD PDIP package.
Industrial Temp.,
Temperature Range
Package:
C
I
=
=
0°C to +70°C (Commercial)
-25°C to +85°C (Industrial)
TC500COE713:
c)
d)
TC500CPE:
TC500IJE:
JE
PE
OE
OE713
=
=
=
=
Ceramic Dual In-line, (300 mil Body), 16-lead
Plastic DIP, (300 mil Body), 16-lead
Plastic SOIC, (300 mil Body), 16-lead
Plastic SOIC, (300 mil Body), 16-lead
(Tape and Reel)
Plastic DIP, (300 mil Body), 24-lead
Plastic SOIC, (300 mil Body), 24-lead
Plastic SOIC, (300 mil Body), 24-lead
(Tape and Reel)
Plastic DIP, (300 mil Body), 28-lead
Plastic SOIC, (300 mil Body), 28-lead
Plastic SOIC, (300 mil Body), 28-lead
(Tape and Reel)
16LD CERDIP package.
a)
b)
TC510COG:
Commercial Temp.,
24LD PDIP package.
Commercial Temp.,
24LD PDIP package,
Tape and Reel.
PF
OG
OG713
=
=
=
TC510COG713:
PJ
OI
OI713
=
=
=
c)
TC510CPF:
Commercial Temp.,
24LD PDIP package.
a)
b)
TC514COI:
Commercial Temp.,
28LD PDIP package.
Commercial Temp.,
28LD PDIP package,
Tape and Reel.
TC514COI713:
c)
TC514CPJ:
Commercial Temp.,
28LD PDIP package.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
© 2006 Microchip Technology Inc.
DS21428D-page 31
TC500/A/510/514
NOTES:
DS21428D-page 32
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and Zena are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21428D-page 33
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
Austria - Wels
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Atlanta
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
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Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
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Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
China - Shenzhen
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
San Jose
Mountain View, CA
Tel: 650-215-1444
Fax: 650-961-0286
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
10/31/05
DS21428D-page 34
© 2006 Microchip Technology Inc.
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