SY100E446JZTR [MICROCHIP]

Parallel In Serial Out, 100E Series, 4-Bit, Right Direction, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28;


型号：	SY100E446JZTR
厂家：	MICROCHIP
描述：	Parallel In Serial Out, 100E Series, 4-Bit, Right Direction, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28 逻辑集成电路触发器
文件：	总9页 (文件大小：82K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SY10E446

Micrel, Inc.

SY100E446

4-BIT PARALLEL-TO-SERIAL

CONVERTER

SY10E446

SY100E446

DESCRIPTION

FEATURES

■ On-chip clock ÷4 and ÷8

The SY10/100E446 are integrated 4-bit parallel-to-

serial data converters. These devices are designed to

operate for NRZ data rates of up to a minimum of 1.3Gb/

s. The chips generate a divide-by-4 and a divide-by-8

clock for both 4-bit conversion and a two-chip 8-bit

conversion function. The conversion sequence was

chosen to convert the parallel data into a serial stream

from bit D0 to D3. A serial input is provided to cascade

two E446 devices for 8-bit conversion applications.

The SYNC input will asynchronously reset the internal

clock circuitry. This pin allows the user to reset the internal

clock conversion unit and, thus, select the start of the

conversion process.

■ Extended 100E VEE range of –4.2V to –5.5V

■ 1.6Gb/s typical data rate capability

■ Differential clock and serial inputs

■ VBB output for single-ended use

■ Asynchronous data synchronization

■ Mode select to expand to 8 bits

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E446

■ Available in 28-pin PLCC package

The MODE input is used to select the conversion mode

of the device. With the MODE input LOW (or open) the

device will function as a 4-bit converter. When the mode

input is driven HIGH, the internal load clock will change

on every eighth clock cycle, thus allowing for an 8-bit

conversion scheme using two E446s. When cascaded in

an 8-bit conversion scheme, the devices will not operate

at the 1.3Gb/s data rate of a single device. Refer to the

applications section of this data sheet for more information

on cascading the E446.

For lower data rate applications, a VBB reference

voltage is supplied for single-ended inputs. When

operating at clock rates above 500MHz, differential input

signals are recommended. For single-ended inputs, the

VBB pin is tied to the inverting differential input and

bypassed via a 0.01µF capacitor. The VBB provides the

switching reference for the input differential amplifier. The

VBB can also be used to AC couple an input signal.

PIN NAMES

SIN, SIN

D0 – D3

Function

Differential Serial Data Input

Parallel Data Input

SOUT, SOUT

CLK, CLK

CL/4, CL/4

CL/8, CL/8

MODE

Differential Serial Data Output

Differential Clock Input

Differential 4 Clock Output

Differential 8 Clock Output

Conversion Mode, 4-bit/8-bit

Conversion Synchronizing Input

VCC to Output

SYNC

VCCO

Rev.: F

Amendment:/0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

SY10E446

SY100E446

Micrel, Inc.

PACKAGE/ORDERING INFORMATION

Ordering Information⁽¹⁾

Package Operating

Package

Marking

Lead

Finish

Part Number

Type

Range

24 23 22 21 20 19

SY10E446JC

SY10E446JCTR⁽²⁾

J28-1

Commercial

SY10E446JC

SY100E446JC

Sn-Pb

CLK

VBB

SY100E446JC

VCC

TOP VIEW

PLCC

J28-1

SOUT

VCCO

VEE

SY100E446JCTR⁽²⁾

SY10E446JZ⁽³⁾

J28-1

Commercial

SY100E446JC

Sn-Pb

SIN

SY10E446JZ with

Pb-Free bar-line indicator

Matte-Sn

Pb-Free

SIN

SYNC

10 11

SY10E446JZTR^{(2, 3)}

SY100E446JZ⁽³⁾

J28-1

Commercial

SY10E446JZ with

Pb-Free bar-line indicator

Matte-Sn

Pb-Free

SY100E446JZ with

Pb-Free bar-line indicator

Matte-Sn

Pb-Free

SY100E446JZTR^{(2, 3)}

J28-1

Commercial

SY100E446JZ with

Pb-Free bar-line indicator

Matte-Sn

Pb-Free

28-Pin PLCC (J28-1)

Notes:

1. Contact factory for die availability. Dice are guaranteed at T = 25°C, DC Electricals only.

2. Tape and Reel.

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

SY10E446

SY100E446

Micrel, Inc.

BLOCK DIAGRAM

SIN

CLK

SOUT

CLK

CL/8

MODE

CLK

÷4

÷8

DELAY

CL/4

SYNC

VBB

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

SY10E446

SY100E446

Micrel, Inc.

TRUTH TABLE

Mode

Conversion

4-Bit

8-Bit

DC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

IIH

Parameter

Input HIGH Current

Output HIGH Voltage

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Unit

µA

Condition

—

150

—

150

—

150

—

VOH

(SOUT Only) 10E –1020

(SOUT Only) 100E –1025

—

–790 –980

–830 –1025

—

–760 –910

–830 –1025

—

–670

–830

VBB

IEE

Output Reference Voltage

—

10E –1.38

100E –1.38

—

–1.27 –1.35

–1.26 –1.38

—

–1.25 –1.31

–1.26 –1.38

—

–1.19

–1.26

Power Supply Current

10E

100E

—

110

132

—

110

132

—

110

127

132

152

Note:

1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E

and 100E VOH levels.

AC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

Parameter

Min. Typ.

Max. Min.

1.3

Typ. Max. Min. Typ. Max. Unit

Condition

fMAX

Max. Conversion Frequency 1.3

1.6

—

1.6

—

1.3

1.6

—

Gb/s

NRZ

—

tPD

Propagation Delay to Output

—

CLK to SOUT

CLK to CL/4

CLK to CL/8

1000 1400 1700 1000 1400 1700 1000 1400 1700

500 800 1100 500 800 1100 500 800 1100

800 1100 1400 800 1100 1400 800 1100 1400

500 800 1100 500

SYNC to CL/4, CL/8

800 1100 500

800 1100

Set-up Time

SIN

—

–200 –400

—

–200 –400

—

–200 –400

—

Mode

–250

Hold Time

SIN

750

800

500

550

600

300

—

750

800

500

550

600

300

—

750

800

500

550

600

300

—

Mode

tRR

tPW

Reset Recovery Time

500

400

200

—

500

400

200

—

500

400

200

—

Minimum Pulse Width

CLK, MR

—

Rise/Fall Time

SOUT

Other

20–80%

100

200

225

425

350 100

650 200

225

425

350

650

100

200

225

425

350

650

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

SY10E446

SY100E446

Micrel, Inc.

TIMING DIAGRAMS

CLK

RESET

0–1

1–1

2–1

3–1

SOUT

CL/4

CL/8

Timing Diagram A. 4:1 Parallel-to-Serial Conversion

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

SY10E446

SY100E446

Micrel, Inc.

TIMING DIAGRAMS (CONTINUED)

CLK

RESET

0–1

1–1

2–1

3–1

4(D0B)

4–1

5–1

5(D1B)

6(D2B)

6–1

7–1

7(D3B)

SOUT

Timing Diagram B. 8:1 Parallel-to-Serial Conversion

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

SY10E446

SY100E446

Micrel, Inc.

APPLICATIONS INFORMATION

The SY10E/100E446 are integrated 4:1 parallel-to-serial serial input pins, must fit into a single clock period for the

converters. The chips are designed to work with the E445 cascade architecture to function properly. Using the worst

device to provide both transmission and receiving of a high- case values for these two parameters from the data sheet,

speed serial data path. The E446 can convert 4 bits of tPD CLK to SOUT = 1600ps and ts for SIN = –200ps, yields

data into a 1.3Gb/s NRZ data stream. The device features a minimum period of 1400ps or a clock frequency of

a SYNC input which allows the user to reset the internal 700MHz.

clock circuitry and restart the conversion sequence (see

Timing Diagram A). Note that SOUT is triggered by negative single converter. In order to increase this frequency, it is

clock edges. recommended that the clock edge feeding the E446A be

The E446 features a differential serial input and internal delayed with respect to the E446B, as shown in Figure 2.

divide-by-eight circuitry to facilitate the cascading of two Perhaps the easiest way to delay the second clock relative

The clock frequency is somewhat lower than that of a

devices to build an 8:1 multiplexer. Figure 1 illustrates the to the first is to take advantage of the differential clock

architecture for an 8:1 multiplexer using two E446s (see inputs of the E446. By connecting the clock for E446A to

Timing Diagram B). Notice the serial outputs (SOUT) of the the complimentary clock input pin, the device will clock a

lower order converter feed the serial inputs of the higher half a clock period after E446B (Figure 2). Utilizing this

order device. This feed through of the serial inputs bounds simple technique will raise the potential conversion frequency

the upper end of the frequency of operation. The clock-to- up to the maximum 1.3GHz of a stand-alone E446.

serial output propagation delay, plus the set-up time of the

CLK

E446B

E446A

SOUT

SIN

SOUT

SERIAL

DATA

PARALLEL DATA

1400ps

200ps

CLK

CLK to SOUT

1600ps

Figure 1. Cascaded 8:1 Converter Architecture

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

SY10E446

SY100E446

Micrel, Inc.

APPLICATIONS INFORMATION

CLK

E446B

E446A

SOUT

SIN

SOUT

SERIAL

DATA

PARALLEL DATA

1.3GHz

770ps

CLKB

CLKA

CLK to SOUT

Figure 2. Extended Frequency 8:1 Converter Architecture

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

SY10E446

SY100E446

Micrel, Inc.

28-PIN PLCC (J28-1)

Rev. 03

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can

reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into

the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s

use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

SY100E446JZTR [MICROCHIP]

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