PIC18F87J90 [MICROCHIP]
64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology; 八十〇分之六十四引脚，高性能微控制器与LCD驱动器和纳瓦技术
| 型号： | PIC18F87J90 |
| 厂家： | 
MICROCHIP |
| 描述： | 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology |
| 文件： | 总450页 (文件大小：3787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F87J90 Family
Data Sheet
64/80-Pin, High-Performance
Microcontrollers with LCD Driver
and nanoWatt Technology
2010 Microchip Technology Inc.
DS39933D
Note the following details of the code protection feature on Microchip devices:
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Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
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There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
32
PICtail, PIC logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39933D-page 2
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
64/80-Pin, High-Performance Microcontrollers with
LCD Driver and nanoWatt Technology
LCD Driver and Keypad Interface
Features:
• Direct LCD Panel Drive Capability:
- Can drive LCD panel while in Sleep mode
• Up to 48 Segments and 192 Pixels,
Software Selectable
• Programmable LCD Timing module:
- Multiple LCD timing sources available
- Up to four commons: static, 1/2, 1/3 or
1/4 multiplex
Peripheral Highlights:
• High-Current Sink/Source 25 mA/25 mA
(PORTB and PORTC)
• Up to Four External Interrupts
• Four 8-Bit/16-Bit Timer/Counter modules
• Two Capture/Compare/PWM (CCP) modules
• Master Synchronous Serial Port (MSSP) module
with Two Modes of Operation:
- 3-Wire/4-Wire SPI (supports all four SPI modes)
- I2C™ Master and Slave mode
- Static, 1/2 or 1/3 bias configuration
• On-Chip LCD Boost Voltage Regulator for
Contrast Control
• One Addressable USART module
• One Enhanced Addressable USART module:
- LIN/J2602 support
• Charge Time Measurement Unit (CTMU) for
Capacitive Touch Sensing
- Auto-wake-up on Start bit and Break character
- Auto-Baud Detect (ABD)
• ADC for Resistive Touch Sensing
• 10-Bit, up to 12-Channel A/D Converter:
- Auto-acquisition
Low-Power Features:
• Power-Managed modes:
- Run: CPU On, Peripherals On
- Idle: CPU Off, Peripherals On
- Sleep: CPU Off, Peripherals Off
• Two-Speed Oscillator Start-up
- Conversion available during Sleep
• Two Analog Comparators
• Programmable Reference Voltage for Comparators
• Hardware Real-Time Clock and Calendar (RTCC)
with Clock, Calendar and Alarm Functions
• Charge Time Measurement Unit (CTMU):
- Capacitance measurement
Flexible Oscillator Structure:
- Time measurement with 1 ns typical resolution
• Two Crystal modes, 4-25 MHz
• Two External Clock modes, up to 48 MHz
• 4x Phase Lock Loop (PLL)
• Internal Oscillator Block with PLL:
- Eight user-selectable frequencies from
31.25 kHz to 8 MHz
• Secondary Oscillator using Timer1 at 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock fails
Special Microcontroller Features:
• 10,000 Erase/Write Cycle Flash Program
Memory, Typical
• Flash Retention 20 Years, Minimum
• Self-Programmable under Software Control
• Word Write Capability for Flash Program Memory
for Data EEPROM Emulators
MSSP
Flash
Program
Memory Memory
(Bytes)
SRAM
Data
LCD
(Pixels)
Device
I/O
CCP
Master
SPI
2
I C™
(Bytes)
PIC18F66J90
PIC18F67J90
PIC18F86J90
PIC18F87J90
64K
128K
64K
3,923
3,923
3,923
3,923
51
51
67
67
132
132
192
192
1/3
1/3
1/3
1/3
2
2
2
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1/1
1/1
1/1
1/1
12
12
12
12
2
2
2
2
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
128K
2010 Microchip Technology Inc.
DS39933D-page 3
PIC18F87J90 FAMILY
• In-Circuit Serial Programming™ (ICSP™) via
Two Pins
Special Microcontroller Features
(Continued):
• In-Circuit Debug via Two Pins
• Priority Levels for Interrupts
• Operating Voltage Range: 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Selectable Open-Drain Configuration for Serial
Communication and CCP Pins for Driving Outputs
up to 5V
• On-Chip 2.5V Regulator
DS39933D-page 4
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
Pin Diagrams – PIC18F6XJ90
Pins are up to 5.5V tolerant.
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51
50 49
RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9/CTED1
RB3/INT3/SEG10/CTED2
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
RE1/LCDBIAS2
1
RE0/LCDBIAS1
2
RG0/LCDBIAS0
3
RG1/TX2/CK2
4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RG2/RX2/DT2/VLCAP1
5
RG3/VLCAP2
6
MCLR
7
PIC18F66J90
PIC18F67J90
RG4/SEG26/RTCC
VSS
VSS
8
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
9
VDDCORE/VCAP
10
11
12
13
14
15
16
RF7/AN5/SS/SEG25
RF6/AN11/SEG24/C1INA
RF5/AN10/CVREF/SEG23/C1INB
RF4/AN9/SEG22/C2INA
RF3/AN8/SEG21/C2INB
RF2/AN7/C1OUT/SEG20
RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17
RC2/CCP1/SEG13
17 18 19 20 21 22 23 24 25 26 27 28
29 30 31 32
Note 1: The CCP2 pin placement depends on the CCP2MX bit setting.
2010 Microchip Technology Inc.
DS39933D-page 5
PIC18F87J90 FAMILY
Pin Diagrams – PIC18F8XJ90
80-Pin TQFP
Pins are up to 5.5V tolerant.
80 79 78
77 76 75 74 73 72 71 70 69 68 67 66 65
64 63 62 61
RH2/SEG45
RH3/SEG44
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
RJ2/SEG34
2
RJ3/SEG35
3
RE1/LCDBIAS2
RE0/LCDBIAS1
RG0/LCDBIAS0
RG1/TX2/CK2
RG2/RX2/DT2/VLCAP1
RG3/VLCAP2
RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9/CTED1
RB3/INT3/SEG10/CTED2
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
VSS
4
5
6
7
8
MCLR
9
PIC18F86J90
PIC18F87J90
RG4/SEG26/RTCC
VSS
10
11
12
13
14
15
16
17
18
19
20
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
VDDCORE/VCAP
RF7/AN5/SS/SEG25
RF6/AN11/SEG24/C1INA
RF5/AN10/CVREF/SEG23/C1INB
RF4/AN9/SEG22/C2INA
RF3/AN8/SEG21/C2INB
RF2/AN7/C1OUT/SEG20
RH7/SEG43
RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17
RC2/CCP1/SEG13
RJ7/SEG36
RJ6/SEG37
RH6/SEG42
41
40
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Note 1: The CCP2 pin placement depends on the CCP2MX bit setting.
DS39933D-page 6
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 31
3.0 Oscillator Configurations ............................................................................................................................................................ 35
4.0 Power-Managed Modes ............................................................................................................................................................. 45
5.0 Reset.......................................................................................................................................................................................... 53
6.0 Memory Organization................................................................................................................................................................. 65
7.0 Flash Program Memory.............................................................................................................................................................. 89
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 99
9.0 Interrupts .................................................................................................................................................................................. 101
10.0 I/O Ports ................................................................................................................................................................................... 117
11.0 Timer0 Module ......................................................................................................................................................................... 139
12.0 Timer1 Module ......................................................................................................................................................................... 143
13.0 Timer2 Module ......................................................................................................................................................................... 149
14.0 Timer3 Module ......................................................................................................................................................................... 151
15.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 155
16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 173
17.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 183
18.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 211
19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 255
20.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) ........................................................... 275
21.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 289
22.0 Comparator Module.................................................................................................................................................................. 299
23.0 Comparator Voltage Reference Module................................................................................................................................... 305
24.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 309
25.0 Special Features of the CPU.................................................................................................................................................... 325
26.0 Instruction Set Summary.......................................................................................................................................................... 339
27.0 Development Support............................................................................................................................................................... 389
28.0 Electrical Characteristics.......................................................................................................................................................... 393
29.0 Packaging Information.............................................................................................................................................................. 427
Appendix A: Revision History............................................................................................................................................................. 433
Appendix B: Migration From PIC18F85J90 to PIC18F87J90 ............................................................................................................ 433
The Microchip Web Site..................................................................................................................................................................... 447
Customer Change Notification Service .............................................................................................................................................. 447
Customer Support.............................................................................................................................................................................. 447
Reader Response.............................................................................................................................................................................. 448
Product Identification System ............................................................................................................................................................ 449
2010 Microchip Technology Inc.
DS39933D-page 7
PIC18F87J90 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
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DS39933D-page 8
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• PIC18F66J90
• PIC18F67J90
• PIC18F86J90
• PIC18F87J90
This family combines the traditional advantages of all
PIC18 microcontrollers – namely, high computational
performance and a rich feature set – with a versatile,
on-chip LCD driver, while maintaining an extremely
competitive price point. These features make the
PIC18F87J90 family
high-performance applications where price is a primary
consideration.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
a logical choice for many
1.1.3
MEMORY OPTIONS
The PIC18F87J90 family provides ample room for
application code, from 64 Kbytes to 128 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 10,000 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 20 years.
1.1
Core Features
1.1.1
nanoWatt TECHNOLOGY
All of the devices in the PIC18F87J90 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key items include:
The Flash program memory is readable and writable.
During normal operation, the PIC18F87J90 family also
provides plenty of room for dynamic application data
with up to 3,923 bytes of data RAM.
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the Internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
1.1.4
EXTENDED INSTRUCTION SET
The PIC18F87J90 family implements the optional
extension to the PIC18 instruction set, adding 8 new
instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as ‘C’.
• On-the-Fly Mode Switching: The power-managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
1.1.5
EASY MIGRATION
1.1.2
OSCILLATOR OPTIONS AND
FEATURES
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
All of the devices in the PIC18F87J90 family offer six
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.
• Two Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
a divide-by-4 clock output.
The PIC18F87J90 family is also largely pin-compatible
with other PIC18 families, such as the PIC18F8720 and
PIC18F8722, the PIC18F85J11, and the PIC18F8490
and PIC18F85J90 families of microcontrollers with
LCD drivers. This allows a new dimension to the
evolution of applications, allowing developers to select
different price points within Microchip’s PIC18 portfolio,
while maintaining a similar feature set.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the External Oscillator modes which
allows clock speeds of up to 40 MHz. PLL can
also be used with the internal oscillator.
• An internal oscillator block which provides an
8 MHz clock (±2% accuracy) and an INTRC source
(approximately 31 kHz, stable over temperature
and VDD), as well as a range of six user-selectable
clock frequencies, between 125 kHz to 4 MHz, for a
total of eight clock frequencies. This option frees the
two oscillator pins for use as additional general
purpose I/O.
2010 Microchip Technology Inc.
DS39933D-page 9
PIC18F87J90 FAMILY
1.2
LCD Driver
1.4
Details on Individual Family
Members
The on-chip LCD driver includes many features that
make the integration of displays in low-power
applications easier. These include an integrated
voltage regulator with charge pump that allows contrast
control in software and display operation above device
VDD.
Devices in the PIC18F87J90 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in four
ways:
1. Flash program memory (two sizes, 64 Kbytes
for PIC18FX6J90 devices and 128 Kbytes for
PIC18FX7J90 devices).
1.3
Other Special Features
• Communications: The PIC18F87J90 family
incorporates a range of serial communication
peripherals, including an Addressable USART, a
separate Enhanced USART that supports
LIN/J2602 specification 1.2, and one Master SSP
module capable of both SPI and I2C™ (Master and
Slave) modes of operation.
2. Data RAM (3,923 bytes RAM for both
PIC18FX6J90 and PIC18FX7J90 devices).
3. I/O ports (7 bidirectional ports on PIC18F6XJ90
devices, 9 bidirectional ports on PIC18F8XJ90
devices).
4. LCD Pixels: 132 pixels (33 SEGs x 4 COMs) can
be driven by 64-pin devices; 192 pixels
(48 SEGs x 4 COMs) can be driven by 80-pin
devices.
• CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules. Up to
four different time bases may be used to perform
several different operations at once.
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reducing code overhead.
The pinouts for all devices are listed in Table 1-3 and
Table 1-4.
• Charge Time Measurement Unit (CTMU): The
CTMU is a flexible analog module that provides
accurate differential time measurement between
pulse sources, as well as asynchronous pulse
generation.
Together with other on-chip analog modules, the
CTMU can precisely measure time, measure
capacitance or relative changes in capacitance, or
generate output pulses that are independent of the
system clock.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 28.0 “Electrical Characteristics” for
time-out periods.
• Real-Time Clock and Calendar Module
(RTCC): The RTCC module is intended for appli-
cations requiring that accurate time be maintained
for extended periods of time with minimum to no
intervention from the CPU.
The module is a 100-year clock and calendar
with automatic leap year detection. The range of
the clock is from 00:00:00 (midnight) on
January 1, 2000 to 23:59:59 on
December 31, 2099.
DS39933D-page 10
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F6XJ90 (64-PIN DEVICES)
Features
PIC18F66J90
PIC18F67J90
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC – 48 MHz
64K
32,768
3,923
128K
65,536
3,923
29
I/O Ports
Ports A, B, C, D, E, F, G
LCD Driver (available pixels to drive)
Timers
132 (33 SEGs x 4 COMs)
4
Comparators
2
CTMU
Yes
RTCC
Yes
Capture/Compare/PWM Modules
Serial Communications
10-Bit Analog-to-Digital Module
Resets (and Delays)
2
MSSP, Addressable USART, Enhanced USART
12 Input Channels
POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set
Packages
75 Instructions, 83 with Extended Instruction Set Enabled
64-Pin TQFP
TABLE 1-2:
DEVICE FEATURES FOR THE PIC18F8XJ90 (80-PIN DEVICES)
Features
PIC18F86J90
PIC18F87J90
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC – 48 MHz
64K
32,768
3,923
128K
65,536
3,923
29
I/O Ports
Ports A, B, C, D, E, F, G, H, J
LCD Driver (available pixels to drive)
Timers
192 (48 SEGs x 4 COMs)
4
Comparators
2
CTMU
Yes
RTCC
Yes
Capture/Compare/PWM Modules
Serial Communications
10-Bit Analog-to-Digital Module
Resets (and Delays)
2
MSSP, Addressable USART, Enhanced USART
12 Input Channels
POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set
Packages
75 Instructions, 83 with Extended Instruction Set Enabled
80-Pin TQFP
2010 Microchip Technology Inc.
DS39933D-page 11
PIC18F87J90 FAMILY
FIGURE 1-1:
PIC18F6XJ90 (64-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
inc/dec logic
21
PORTA
Data Latch
8
RA0:RA7(1,2)
8
Data Memory
(2.0, 3.9
PCLATU PCLATH
Kbytes)
Address Latch
20
PCU PCH PCL
Program Counter
12
PORTB
Data Address<12>
RB0:RB7(1)
31-Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(96 Kbytes)
12
Data Latch
PORTC
RC0:RC7(1)
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
IR
Instruction Bus <16>
PORTD
RD0:RD7(1)
8
State Machine
Control Signals
Instruction
Decode and
Control
PORTE
RE0:RE1,
RE3:RE7(1)
PRODH PRODL
8 x 8 Multiply
3
Timing
Generation
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
BITOP
8
W
INTRC
Oscillator
8
Oscillator
Start-up Timer
8
8 MHz
Oscillator
PORTF
8
Power-on
Reset
8
RF1:RF7(1)
Precision
Band Gap
Reference
ALU<8>
8
Watchdog
Timer
ENVREG
BOR and
LVD(3)
Voltage
Regulator
PORTG
RG0:RG4(1)
VDDCORE/VCAP
VDD,VSS
MCLR
ADC
10-Bit
Timer0
CCP1
Timer1
Timer2
Timer3
CTMU
RTCC
Comparators
LCD
Driver
CCP2
MSSP
AUSART
EUSART
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for more
information
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
DS39933D-page 12
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 1-2:
PIC18F8XJ90 (80-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
inc/dec logic
21
PORTA
Data Latch
8
8
RA0:RA7(1,2)
Data Memory
(2.0, 3.9
PCLATU PCLATH
Kbytes)
Address Latch
20
PORTB
PCU PCH PCL
Program Counter
RB0:RB7(1)
12
Data Address<12>
31-Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
PORTC
Access
Bank
Program Memory
(96 Kbytes)
RC0:RC7(1)
12
Data Latch
inc/dec
logic
8
PORTD
Table Latch
RD0:RD7(1)
Address
Decode
ROM Latch
IR
Instruction Bus <16>
PORTE
RE0:RE1,
RE3:RE7(1)
8
State Machine
Control Signals
Instruction
Decode and
Control
PORTF
PRODH PRODL
8 x 8 Multiply
RF1:RF7(1)
3
Timing
Generation
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
BITOP
8
W
PORTG
INTRC
Oscillator
8
Oscillator
Start-up Timer
8
RG0:RG4(1)
8 MHz
Oscillator
8
Power-on
Reset
8
Precision
Band Gap
Reference
ALU<8>
8
PORTH
Watchdog
Timer
RH0:RH7(1)
ENVREG
BOR and
LVD(3)
Voltage
Regulator
PORTJ
RJ0:RJ7(1)
VDDCORE/VCAP
VDD,VSS
MCLR
ADC
10-Bit
Timer0
CCP1
Timer1
Timer2
Timer3
CTMU
RTCC
Comparators
LCD
Driver
CCP2
MSSP
AUSART
EUSART
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for
more information.
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
2010 Microchip Technology Inc.
DS39933D-page 13
PIC18F87J90 FAMILY
TABLE 1-3:
PIC18F6XJ90 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
MCLR
7
I
ST
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
OSC1/CLKI/RA7
OSC1
39
40
Oscillator crystal or external clock input.
Oscillator crystal input.
I
I
CMOS
CMOS
CLKI
External clock source input. Always associated
with pin function, OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
RA7
I/O
TTL
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
RA6
I/O
TTL
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
24
23
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
AN0
RA1/AN1/SEG18
RA1
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 1.
SEG18 output for LCD.
AN1
SEG18
RA2/AN2/VREF-
RA2
22
21
28
27
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
AN2
VREF-
RA3/AN3/VREF+
RA3
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA4/T0CKI/SEG14
RA4
I/O
I
O
ST
ST
Analog
Digital I/O.
Timer0 external clock input.
SEG14 output for LCD.
T0CKI
SEG14
RA5/AN4/SEG15
RA5
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 4.
SEG15 output for LCD.
AN4
SEG15
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39933D-page 14
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 1-3:
PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/SEG30
RB0
48
47
46
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 0.
SEG30 output for LCD.
INT0
SEG30
RB1/INT1/SEG8
RB1
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 1.
SEG8 output for LCD.
INT1
SEG8
RB2/INT2/SEG9/CTED1
RB2
INT2
CTED1
SEG9
I/O
I
I
TTL
ST
ST
Digital I/O.
External Interrupt 2.
CTMU Edge 1 input.
SEG9 output for LCD.
O
Analog
RB3/INT3/SEG10/CTED2
45
RB3
INT3
SEG10
CTED2
I/O
TTL
ST
Analog
ST
Digital I/O.
I
O
I
External Interrupt 3.
SEG10 output for LCD.
CTMU Edge 2 input.
RB4/KBI0/SEG11
RB4
44
43
42
37
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
KBI0
SEG11
RB5/KBI1/SEG29
RB5
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.
KBI1
SEG29
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39933D-page 15
PIC18F87J90 FAMILY
TABLE 1-3:
PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
30
29
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2/SEG32
RC1
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.
T1OSI
CCP2(1)
SEG32
Analog
RC2/CCP1/SEG13
RC2
33
34
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP1
SEG13
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
RC3/SCK/SCL/SEG17
RC3
SCK
SCL
SEG17
I/O
I/O
I/O
O
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
SEG17 output for LCD.
I2C
Analog
RC4/SDI/SDA/SEG16
35
RC4
SDI
SDA
SEG16
I/O
I
I/O
O
ST
ST
Digital I/O.
SPI data in.
I2C
I2C data I/O.
Analog
SEG16 output for LCD.
RC5/SDO/SEG12
RC5
36
31
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
SDO
SEG12
RC6/TX1/CK1/SEG27
RC6
TX1
CK1
SEG27
I/O
O
I/O
O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.
Analog
RC7/RX1/DT1/SEG28
32
RC7
RX1
DT1
SEG28
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.
Analog
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39933D-page 16
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 1-3:
PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTD is a bidirectional I/O port.
RD0/SEG0/CTPLS
RD0
58
I/O
O
O
ST
Analog
—
Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.
SEG0
CTPLS
RD1/SEG1
RD1
55
54
53
52
51
50
49
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
SEG1
RD2/SEG2
RD2
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
SEG2
RD3/SEG3
RD3
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
SEG3
RD4/SEG4
RD4
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
SEG4
RD5/SEG5
RD5
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
SEG5
RD6/SEG6
RD6
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
SEG6
RD7/SEG7
RD7
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
SEG7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39933D-page 17
PIC18F87J90 FAMILY
TABLE 1-3:
PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTE is a bidirectional I/O port.
RE0/LCDBIAS1
RE0
2
1
I/O
I
ST
Analog
Digital I/O.
BIAS1 input for LCD.
LCDBIAS1
RE1/LCDBIAS2
RE1
I/O
I
ST
Analog
Digital I/O.
BIAS2 input for LCD.
LCDBIAS2
LCDBIAS3
64
63
I
Analog
BIAS3 input for LCD.
RE3/COM0
RE3
I/O
O
ST
Analog
Digital I/O.
COM0 output for LCD.
COM0
RE4/COM1
RE4
62
61
60
59
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
COM1
RE5/COM2
RE5
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
COM2
RE6/COM3
RE6
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
COM3
RE7/CCP2/SEG31
RE7
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP2(2)
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
SEG31
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39933D-page 18
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 1-3:
PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT/SEG19
17
16
15
14
13
RF1
AN6
C2OUT
SEG19
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
SEG19 output for LCD.
Analog
RF2/AN7/C1OUT/SEG20
RF2
AN7
C1OUT
SEG20
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog Input 7.
Comparator 1 output.
SEG20 output for LCD.
Analog
RF3/AN8/SEG21/C2INB
RF3
AN8
SEG21
C2INB
I/O
ST
Digital I/O.
I
O
I
Analog
Analog
Analog
Analog Input 8.
SEG21 output for LCD.
Comparator 2 Input B.
RF4/AN9/SEG22/C2INA
RF4
AN9
SEG22
C2INA
I/O
ST
Digital I/O.
I
O
I
Analog
Analog
Analog
Analog Input 9.
SEG22 output for LCD
Comparator 2 Input A.
RF5/AN10/CVREF/
SEG23/C1INB
RF5
I/O
I
O
O
I
ST
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
SEG23 output for LCD.
Comparator 1 Input B.
AN10
CVREF
SEG23
C1INB
Analog
Analog
Analog
Analog
RF6/AN11/SEG24/C1INA
12
11
RF6
I/O
ST
Digital I/O.
AN11
SEG24
C1INA
I
O
I
Analog
Analog
Analog
Analog Input 11.
SEG24 output for LCD
Comparator 1 Input A.
RF7/AN5/SS/SEG25
RF7
AN5
SS
I/O
O
I
ST
Analog
TTL
Digital I/O.
Analog Input 5.
SPI slave select input.
SEG25 output for LCD.
SEG25
O
Analog
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39933D-page 19
PIC18F87J90 FAMILY
TABLE 1-3:
PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTG is a bidirectional I/O port.
RG0/LCDBIAS0
RG0
3
4
I/O
I
ST
Analog
Digital I/O.
BIAS0 input for LCD.
LCDBIAS0
RG1/TX2/CK2
RG1
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
RG2/RX2/DT2/VLCAP1
5
RG2
RX2
DT2
VLCAP1
I/O
ST
ST
ST
Digital I/O.
I
I/O
I
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
LCD charge pump capacitor input.
Analog
RG3/VLCAP2
RG3
6
8
I/O
I
ST
Analog
Digital I/O.
LCD charge pump capacitor input.
VLCAP2
RG4/SEG26/RTCC
RG4
I/O
O
O
ST
Analog
—
Digital I/O.
SEG26 output for LCD.
RTCC output
SEG26
RTCC
VSS
9, 25, 41, 56
P
P
P
P
I
—
—
—
—
ST
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
Enable for on-chip voltage regulator.
VDD
26, 38, 57
AVSS
AVDD
ENVREG
20
19
18
10
VDDCORE/VCAP
VDDCORE
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
P
P
—
—
VCAP
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39933D-page 20
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 1-4:
PIC18F8XJ90 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
MCLR
9
I
ST
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
OSC1/CLKI/RA7
OSC1
49
50
Oscillator crystal or external clock input.
Oscillator crystal input.
I
I
CMOS
CMOS
CLKI
External clock source input. Always associated
with pin function, OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
RA7
I/O
TTL
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
RA6
I/O
TTL
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
30
29
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
AN0
RA1/AN1/SEG18
RA1
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 1.
SEG18 output for LCD.
AN1
SEG18
RA2/AN2/VREF-
RA2
28
27
34
33
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
AN2
VREF-
RA3/AN3/VREF+
RA3
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA4/T0CKI/SEG14
RA4
I/O
I
O
ST
ST
Analog
Digital I/O.
Timer0 external clock input.
SEG14 output for LCD.
T0CKI
SEG14
RA5/AN4/SEG15
RA5
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 4.
SEG15 output for LCD.
AN4
SEG15
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39933D-page 21
PIC18F87J90 FAMILY
TABLE 1-4:
PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/SEG30
RB0
58
57
56
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 0.
SEG30 output for LCD.
INT0
SEG30
RB1/INT1/SEG8
RB1
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 1.
SEG8 output for LCD.
INT1
SEG8
RB2/INT2/SEG9/CTED1
RB2
INT2
SEG9
CTED1
I/O
TTL
ST
Analog
ST
Digital I/O.
I
O
I
External Interrupt 2.
SEG9 output for LCD.
CTMU Edge 1 input.
RB3/INT3/SEG10/
CTED2
55
RB3
INT3
SEG10
CTED2
I/O
TTL
ST
Analog
ST
Digital I/O.
I
O
I
External Interrupt 3.
SEG10 output for LCD.
CTMU Edge 2 input.
RB4/KBI0/SEG11
RB4
54
53
52
47
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
KBI0
SEG11
RB5/KBI1/SEG29
RB5
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.
KBI1
SEG29
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39933D-page 22
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 1-4:
PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
36
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2/SEG32
RC1
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.
T1OSI
CCP2(1)
SEG32
Analog
RC2/CCP1/SEG13
RC2
43
44
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP1
SEG13
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
RC3/SCK/SCL/SEG17
RC3
SCK
SCL
SEG17
I/O
I/O
I/O
O
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
SEG17 output for LCD.
I2C
Analog
RC4/SDI/SDA/SEG16
45
RC4
SDI
SDA
SEG16
I/O
I
I/O
O
ST
ST
Digital I/O.
SPI data in.
I2C
I2C data I/O.
Analog
SEG16 output for LCD.
RC5/SDO/SEG12
RC5
46
37
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
SDO
SEG12
RC6/TX1/CK1/SEG27
RC6
TX1
CK1
SEG27
I/O
O
I/O
O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.
Analog
RC7/RX1/DT1/SEG28
38
RC7
RX1
DT1
SEG28
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.
Analog
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39933D-page 23
PIC18F87J90 FAMILY
TABLE 1-4:
PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTD is a bidirectional I/O port.
RD0/SEG0/CTPLS
RD0
72
I/O
O
O
ST
Analog
ST
Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.
SEG0
CTPLS
RD1/SEG1
RD1
69
68
67
66
65
64
63
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
SEG1
RD2/SEG2
RD2
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
SEG2
RD3/SEG3
RD3
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
SEG3
RD4/SEG4
RD4
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
SEG4
RD5/SEG5
RD5
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
SEG5
RD6/SEG6
RD6
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
SEG6
RD7/SEG7
RD7
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
SEG7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39933D-page 24
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 1-4:
PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTE is a bidirectional I/O port.
RE0/LCDBIAS1
RE0
4
3
I/O
I
ST
Analog
Digital I/O.
BIAS1 input for LCD.
LCDBIAS1
RE1/LCDBIAS2
RE1
I/O
I
ST
Analog
Digital I/O.
BIAS2 input for LCD.
LCDBIAS2
LCDBIAS3
78
77
I
Analog
BIAS3 input for LCD.
RE3/COM0
RE3
I/O
O
ST
Analog
Digital I/O.
COM0 output for LCD.
COM0
RE4/COM1
RE4
76
75
74
73
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
COM1
RE5/COM2
RE5
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
COM2
RE6/COM3
RE6
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
COM3
RE7/CCP2/SEG31
RE7
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP2(2)
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
SEG31
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39933D-page 25
PIC18F87J90 FAMILY
TABLE 1-4:
PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT/SEG19
23
18
17
16
15
RF1
AN6
C2OUT
SEG19
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
SEG19 output for LCD.
Analog
RF2/AN7/C1OUT/SEG20
RF2
AN7
C1OUT
SEG20
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog Input 7.
Comparator 1 output.
SEG20 output for LCD.
Analog
RF3/AN8/SEG21/C2INB
RF3
AN8
SEG21
C2INB
I/O
ST
Digital I/O.
I
O
I
Analog
Analog
Analog
Analog Input 8.
SEG21 output for LCD.
Comparator 2 Input B.
RF4/AN9/SEG22/C2INA
RF4
AN9
SEG22
C2INA
I/O
ST
Digital I/O.
I
O
I
Analog
Analog
Analog
Analog Input 9.
SEG22 output for LCD.
Comparator 2 Input A.
RF5/AN10/CVREF/
SEG23/C1INB
RF5
I/O
I
O
O
I
ST
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
SEG23 output for LCD.
Comparator 1 Input B.
AN10
CVREF
SEG23
C1INB
Analog
Analog
Analog
Analog
RF6/AN11/SEG24/C1INA
14
13
RF6
I/O
ST
Digital I/O.
AN11
SEG24
C1INA
I
O
I
Analog
Analog
Analog
Analog Input 11.
SEG24 output for LCD.
Comparator 1 Input A.
RF7/AN5/SS/SEG25
RF7
AN5
SS
I/O
O
I
ST
Analog
TTL
Digital I/O.
Analog Input 5.
SPI slave select input.
SEG25 output for LCD.
SEG25
O
Analog
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39933D-page 26
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 1-4:
PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTG is a bidirectional I/O port.
RG0/LCDBIAS0
RG0
5
6
I/O
I
ST
Analog
Digital I/O.
BIAS0 input for LCD.
LCDBIAS0
RG1/TX2/CK2
RG1
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
RG2/RX2/DT2/VLCAP1
7
RG2
RX2
DT2
VLCAP1
I/O
ST
ST
ST
Digital I/O.
I
I/O
I
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
LCD charge pump capacitor input.
Analog
RG3/VLCAP2
RG3
8
I/O
I
ST
Analog
Digital I/O.
LCD charge pump capacitor input.
VLCAP2
RG4/SEG26/RTCC
RG4
10
I/O
O
O
ST
Analog
—
Digital I/O.
SEG26 output for LCD.
RTCC output.
SEG26
RTCC
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39933D-page 27
PIC18F87J90 FAMILY
TABLE 1-4:
PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTH is a bidirectional I/O port.
RH0/SEG47
RH0
79
80
1
I/O
O
ST
Analog
Digital I/O.
SEG47 output for LCD.
SEG47
RH1/SEG46
RH1
I/O
O
ST
Analog
Digital I/O.
SEG46 output for LCD.
SEG46
RH2/SEG45
RH2
I/O
O
ST
Analog
Digital I/O.
SEG45 output for LCD.
SEG45
RH3/SEG44
RH3
2
I/O
O
ST
Analog
Digital I/O.
SEG44 output for LCD.
SEG44
RH4/SEG40
RH4
22
21
20
19
I/O
O
ST
Analog
Digital I/O.
SEG40 output for LCD.
SEG40
RH5/SEG41
RH5
I/O
O
ST
Analog
Digital I/O.
SEG41 output for LCD.
SEG41
RH6/SEG42
RH6
I/O
O
ST
Analog
Digital I/O.
SEG42 output for LCD.
SEG42
RH7/SEG43
RH7
I/O
O
ST
Analog
Digital I/O.
SEG43 output for LCD.
SEG43
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39933D-page 28
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 1-4:
PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTJ is a bidirectional I/O port.
Digital I/O.
RJ0
62
61
I/O
ST
RJ1/SEG33
RJ1
I/O
O
ST
Analog
Digital I/O.
SEG33 output for LCD.
SEG33
RJ2/SEG34
RJ2
60
59
39
40
41
42
I/O
O
ST
Analog
Digital I/O.
SEG34 output for LCD.
SEG34
RJ3/SEG35
RJ3
I/O
O
ST
Analog
Digital I/O.
SEG35 output for LCD.
SEG35
RJ4/SEG39
RJ4
I/O
O
ST
Analog
Digital I/O.
SEG39 output for LCD.
SEG39
RJ5/SEG38
RJ5
I/O
O
ST
Analog
Digital I/O
SEG38 output for LCD.
SEG38
RJ6/SEG37
RJ6
I/O
O
ST
Analog
Digital I/O.
SEG37 output for LCD.
SEG37
RJ7/SEG36
RJ7
I/O
O
ST
Analog
Digital I/O.
SEG36 output for LCD.
SEG36
VSS
11, 31, 51, 70
P
P
P
P
I
—
—
—
—
ST
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
Enable for on-chip voltage regulator.
VDD
32, 48, 71
AVSS
AVDD
ENVREG
26
25
24
12
VDDCORE/VCAP
VDDCORE
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
P
P
—
—
VCAP
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39933D-page 29
PIC18F87J90 FAMILY
NOTES:
DS39933D-page 30
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
2.0
2.1
GUIDELINES FOR GETTING
STARTED WITH PIC18FJ
MICROCONTROLLERS
(2)
C2
VDD
Basic Connection Requirements
Getting started with the PIC18F87J90 family family of
8-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
(1)
(1)
R1
R2
ENVREG
MCLR
VCAP/VDDCORE
C1
The following pins must always be connected:
C7
PIC18FXXJXX
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
VDD
VSS
VSS
VDD
(2)
(2)
C3
C6
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
(2)
(2)
C4
C5
• ENVREG (if implemented) and VCAP/VDDCORE pins
(see Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)”)
Key (all values are recommendations):
These pins must also be connected if they are being
used in the end application:
C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 6.3V or greater, tantalum or ceramic
R1: 10 kΩ
• PGC/PGD pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
R2: 100Ω to 470Ω
Note 1: See Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)” for
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
explanation of ENVREG pin connections.
2: The example shown is for a PIC18F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
Additionally, the following pins may be required:
• VREF+/VREF- pins are used when external voltage
reference for analog modules is implemented
Note:
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
2010 Microchip Technology Inc.
DS39933D-page 31
PIC18F87J90 FAMILY
2.2
Power Supply Pins
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
2.2.1
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
not required in the end application,
a
direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
Consider the following criteria when using decoupling
capacitors:
voltage sags, may be beneficial.
A
typical
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci-
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
R1
R2
MCLR
PIC18FXXJXX
JP
C1
inductance.
Note 1: R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac-
itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
2: R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
DS39933D-page 32
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
2.4
Voltage Regulator Pins (ENVREG
and VCAP/VDDCORE)
2.5
ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
The on-chip voltage regulator enable pin, ENVREG,
must always be connected directly to either a supply
voltage or to ground. Tying ENVREG to VDD enables
the regulator, while tying it to ground disables the
regulator. Refer to Section 25.3 “On-Chip Voltage
Regulator” for details on connecting and using the
on-chip regulator.
Pull-up resistors, series diodes, and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communica-
tions to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alter-
natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
When the regulator is enabled, a low-ESR (< 5Ω)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and
must use a capacitor of 10 F connected to ground. The
type can be ceramic or tantalum. A suitable example is
the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or
equivalent. Designers may use Figure 2-3 to evaluate
ESR equivalence of candidate devices.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 28.0 “Electrical
Characteristics” for additional information.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins) programmed
into the device matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to Section 28.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
For more information on available Microchip
development tools connection requirements, refer
toSection 27.0 “Development Support”.
Note that the “LF” versions of some low pin count
PIC18FJ parts (e.g., the PIC18LF45J10) do not have
the ENVREG pin. These devices are provided with the
voltage regulator permanently disabled; they must
always be provided with a supply voltage on the
VDDCORE pin.
FIGURE 2-3:
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
10
1
0.1
0.01
0.001
0.01
0.1
1
10
100
1000 10,000
Frequency (MHz)
Note:
Data for Murata GRM21BF50J106ZE01 shown.
Measurements at 25°C, 0V DC bias.
2010 Microchip Technology Inc.
DS39933D-page 33
PIC18F87J90 FAMILY
FIGURE 2-4:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
2.6
External Oscillator Pins
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency
secondary
oscillator
(refer to
Single-Sided and In-Line Layouts:
Section 3.0 “Oscillator Configurations” for details).
Copper Pour
(tied to ground)
Primary Oscillator
Crystal
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
DEVICE PINS
Primary
OSC1
OSC2
GND
Oscillator
C1
C2
`
`
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
T1OSO
T1OS I
Timer1 Oscillator
Crystal
`
Layout suggestions are shown in Figure 2-4. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
T1 Oscillator: C2
T1 Oscillator: C1
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins and other signals
in close proximity to the oscillator are benign (i.e., free
of high frequencies, short rise and fall times, and other
similar noise).
Bottom Layer
Copper Pour
(tied to ground)
OSCO
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
C2
Oscillator
Crystal
GND
• AN826, “Crystal Oscillator Basics and Crystal
C1
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
OSCI
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
DEVICE PINS
2.7
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
DS39933D-page 34
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
All of these modes are selected by the user by
programming the FOSC<2:0> Configuration bits.
3.0
3.1
OSCILLATOR
CONFIGURATIONS
In addition, PIC18F87J90 family devices can switch
between different clock sources, either under software
control or automatically under certain conditions. This
allows for additional power savings by managing
device clock speed in real time without resetting the
application.
Oscillator Types
The PIC18F87J90 family of devices can be operated in
eight different oscillator modes:
1. ECPLL
OSC1/OSC2 as primary; ECPLL
oscillator with PLL enabled, CLKO on
RA6
The clock sources for the PIC18F87J90 family of
devices are shown in Figure 3-1.
2. EC
OSC1/OSC2 as primary; external
clock with FOSC/4 output
3. HSPLL
OSC1/OSC2 as primary; high-speed
crystal/resonator with software PLL
control
4. HS
OSC1/OSC2 as primary; high-speed
crystal/resonator
5. INTPLL1 Internal oscillator block with software
PLL control, FOSC/4 output on RA6
and I/O on RA7
6. INTIO1
Internal oscillator block with FOSC/4
output on RA6 and I/O on RA7
7. INTPLL2 Internal oscillator block with software
PLL control and I/O on RA6 and RA7
8. INTIO2
Internal oscillator block with I/O on
RA6 and RA7
FIGURE 3-1:
PIC18F87J90 FAMILY CLOCK DIAGRAM
Primary Oscillator
HS, EC
HSPLL, ECPLL, INTPLL
T1OSC
OSC2
OSCTUNE<6>
Sleep
4 x PLL
OSC1
Secondary Oscillator
Peripherals
T1OSO
T1OSCEN
Enable
Oscillator
T1OSI
OSCCON<6:4>
Internal Oscillator
CPU
OSCCON<6:4>
8 MHz
111
110
101
100
011
010
001
4 MHz
2 MHz
Internal
Oscillator
Block
IDLEN
Clock
1 MHz
Control
500 kHz
250 kHz
125 kHz
31 kHz
8 MHz
Source
8 MHz
(INTOSC)
FOSC<2:0>
OSCCON<1:0>
Clock Source Option
for Other Modules
1
0
000
INTRC
Source
OSCTUNE<7>
31 kHz (INTRC)
WDT, PWRT, FSCM
and Two-Speed Start-up
2010 Microchip Technology Inc.
DS39933D-page 35
PIC18F87J90 FAMILY
The OSCTUNE register (Register 3-2) controls the
tuning and operation of the internal oscillator block. It
also implements the PLLEN bits which control the
operation of the Phase Locked Loop (PLL) (see
Section 3.4.3 “PLL Frequency Multiplier”).
3.2
Control Registers
The OSCCON register (Register 3-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the oscillators.
REGISTER 3-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
IDLEN
bit 7
R/W-1
IRCF2(2)
R/W-1
IRCF1(2)
R/W-0
IRCF0(2)
R(1)
R-0
R/W-0
SCS1(4)
R/W-0
SCS0(4)
OSTS
IOFS
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
IDLEN: Idle Enable bit
1= Device enters an Idle mode when a SLEEPinstruction is executed
0= Device enters Sleep mode when a SLEEPinstruction is executed
bit 6-4
IRCF<2:0>: INTOSC Source Frequency Select bits(2)
111= 8 MHz (INTOSC drives clock directly)
110= 4 MHz (default)
101= 2 MHz
100= 1 MHz
011= 500 kHz
010= 250 kHz
001= 125 kHz
000= 31 kHz (from either INTOSC/256 or INTRC)(3)
bit 3
OSTS: Oscillator Start-up Timer Time-out Status bit(1)
1= Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running
0= Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready
bit 2
IOFS: INTOSC Frequency Stable bit
1= Fast RC oscillator frequency is stable
0= Fast RC oscillator frequency is not stable
bit 1-0
SCS<1:0>: System Clock Select bits(4)
11= Internal oscillator block
10= Primary oscillator
01= Timer1 oscillator
00= Default primary oscillator (as defined by the FOSC<2:0> Configuration bits)
Note 1: Reset state depends on the state of the IESO Configuration bit.
2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3: Source selected by the INTSRC bit (OSCTUNE<7>), see text.
4: Modifying these bits will cause an immediate clock source switch.
DS39933D-page 36
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 3-2:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0
INTSRC
bit 7
R/W-0
R/W-0
TUN5
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
PLLEN
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1= 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0= 31 kHz device clock derived from the INTRC 31 kHz oscillator
PLLEN: Frequency Multiplier PLL Enable bit
1= PLL enabled
0= PLL disabled
bit 5-0
TUN<5:0>: Fast RC Oscillator (INTOSC) Frequency Tuning bits
011111= Maximum frequency
•
•
•
•
000001
000000= Center frequency. Fast RC oscillator is running at the calibrated frequency.
111111
•
•
•
•
100000= Minimum frequency
controller is placed in a power-managed mode.
PIC18F87J90 family devices offer the Timer1 oscillator
as a secondary oscillator source. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock (RTC). The
Timer1 oscillator is discussed in greater detail in
Section 12.0 “Timer1 Module”.
3.3
Clock Sources and
Oscillator Switching
Essentially, PIC18F87J90 family devices have three
independent clock sources:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
In addition to being a primary clock source in some
circumstances, the internal oscillator is available as a
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor. The internal oscillator block is discussed in
more detail in Section 3.5 “Internal Oscillator
Block”.
The primary oscillators can be thought of as the main
device oscillators. These are any external oscillators
connected to the OSC1 and OSC2 pins, and include
the External Crystal and Resonator modes and the
External Clock modes. If selected by the FOSC<2:0>
Configuration bits, the internal oscillator block (either
the 31 kHz INTRC or the 8 MHz INTOSC source) may
be considered a primary oscillator. The particular mode
is defined by the FOSC Configuration bits. The details
of these modes are covered in Section 3.4 “External
Oscillator Modes”.
The PIC18F87J90 family includes features that allow
the device clock source to be switched from the main
oscillator, chosen by device configuration, to one of the
alternate clock sources. When an alternate clock
source is enabled, various power-managed operating
modes are available.
The secondary oscillators are external clock sources
that are not connected to the OSC1 or OSC2 pins.
These sources may continue to operate even after the
2010 Microchip Technology Inc.
DS39933D-page 37
PIC18F87J90 FAMILY
3.3.1
CLOCK SOURCE SELECTION
3.3.1.1
System Clock Selection and Device
Resets
The System Clock Select bits, SCS<1:0>
(OSCCON<1:0>), select the clock source. The avail-
able clock sources are the primary clock defined by the
FOSC<2:0> Configuration bits, the secondary clock
(Timer1 oscillator) and the internal oscillator. The clock
source changes after one or more of the bits is written
to, following a brief clock transition interval.
Since the SCS bits are cleared on all forms of Reset,
this means the primary oscillator defined by the
FOSC<2:0> Configuration bits is used as the primary
clock source on device Resets. This could either be the
internal oscillator block by itself or one of the other
primary clock source (HS, EC, HSPLL, ECPLL1/2 or
INTPLL1/2).
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in Primary
Clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in
Secondary Clock modes. In power-managed modes,
only one of these bits will be set at any time. If neither
of these bits is set, the INTRC is providing the clock, or
the internal oscillator has just started and is not yet
stable.
In those cases when the internal oscillator block, with-
out PLL, is the default clock on Reset, the Fast RC
oscillator (INTOSC) will be used as the device clock
source. It will initially start at 1 MHz; the postscaler
selection that corresponds to the Reset value of the
IRCF<2:0> bits (‘100’).
Regardless of which primary oscillator is selected,
INTRC will always be enabled on device power-up. It
serves as the clock source until the device has loaded
its configuration values from memory. It is at this point
that the FOSC Configuration bits are read and the
oscillator selection of the operational mode is made.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
Note that either the primary clock source, or the internal
oscillator, will have two bit setting options for the possible
values of the SCS<1:0> bits at any given time.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
3.3.2
OSCILLATOR TRANSITIONS
PIC18F87J90 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEPinstruction will be ignored.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEPinstruction or a very
long delay may occur while the Timer1
oscillator starts.
DS39933D-page 38
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 3-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
3.4
External Oscillator Modes
3.4.1
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS (HS MODES)
Typical Capacitor Values
Crystal
Freq.
Tested:
Osc Type
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 3-2 shows the pin
connections.
C1
C2
HS
4 MHz
8 MHz
20 MHz
27 pF
22 pF
15 pF
27 pF
22 pF
15 pF
The oscillator design requires the use of a crystal rated
for parallel resonant operation.
Capacitor values are for design guidance only.
Note:
Use of a crystal rated for series resonant
operation may give a frequency out of the
crystal manufacturer’s specifications.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
TABLE 3-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Refer to the Microchip application notes cited in
Table 3-1 for oscillator specific information. Also see
the notes following this table for additional
information.
Typical Capacitor Values Used:
Mode
Freq.
OSC1
OSC2
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application. Refer
to the following application notes for oscillator specific
information:
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
3: Rs may be required to avoid overdriving
• AN588, “PIC® Microcontroller Oscillator Design
Guide”
crystals with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC® and PIC® Devices”
• AN849, “Basic PIC® Oscillator Design”
• AN943, “Practical PIC® Oscillator Analysis and
Design”
FIGURE 3-2:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS OR HSPLL
• AN949, “Making Your Oscillator Work”
CONFIGURATION)
See the notes following Table 3-2 for additional
information.
(1)
C1
OSC1
To
Internal
Logic
XTAL
(3)
RF
Sleep
OSC2
(2)
RS
(1)
PIC18F87J90
C2
Note 1: See Table 3-1 and Table 3-2 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
2010 Microchip Technology Inc.
DS39933D-page 39
PIC18F87J90 FAMILY
3.4.2
EXTERNAL CLOCK INPUT
(EC MODES)
3.4.3.1
HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external
oscillating source to produce frequencies of up to
40 MHz.
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
The PLL is enabled by programming the FOSC<2:0>
Configuration bits to either ‘111’ (for ECPLL) or ‘101’
(for HSPLL). In addition, the PLLEN bit
(OSCTUNE<6>) must also be set. Clearing PLLEN
disables the PLL, regardless of the chosen oscillator
configuration. It also allows additional flexibility for
controlling the application’s clock speed in software.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-3:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
FIGURE 3-5:
PLL BLOCK DIAGRAM
HSPLL or ECPLL (CONFIG2L)
PLL Enable (OSCTUNE)
OSC1/CLKI
Clock from
Ext. System
PIC18F87J90
OSC2/CLKO
OSC2
OSC1
FOSC/4
Phase
Comparator
FIN
HS or EC
Mode
FOUT
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-4. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
Loop
Filter
VCO
4
SYSCLK
FIGURE 3-4:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
3.4.3.2
PLL and INTOSC
The PLL is also available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 32 MHz. The operation of INTOSC with the PLL is
described in Section 3.5.2 “INTPLL Modes”.
OSC1
Clock from
Ext. System
PIC18F87J90
(HS Mode)
OSC2
Open
3.4.3
PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
DS39933D-page 40
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 3-6: INTIO1 OSCILLATOR MODE
3.5
Internal Oscillator Block
The PIC18F87J90 family of devices includes an
internal oscillator block which generates two different
clock signals; either can be used as the micro-
controller’s clock source. This may eliminate the need
for an external oscillator circuit on the OSC1 and/or
OSC2 pins.
I/O (OSC1)
RA7
PIC18F87J90
OSC2
FOSC/4
The main output is the Fast RC oscillator or INTOSC,
an 8 MHz clock source which can be used to directly
drive the device clock. It also drives a postscaler, which
can provide a range of clock frequencies from 31 kHz
to 4 MHz. INTOSC is enabled when a clock frequency
from 125 kHz to 8 MHz is selected. The INTOSC out-
put can also be enabled when 31 kHz is selected,
depending on the INTSRC bit (OSCTUNE<7>).
FIGURE 3-7: INTIO2 OSCILLATOR MODE
RA7
RA6
I/O (OSC1)
PIC18F87J90
I/O (OSC2)
The other clock source is the Internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:
3.5.2
INTPLL MODES
The 4x Phase Locked Loop (PLL) can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with the internal
oscillator sources. When enabled, the PLL produces a
clock speed of 16 MHz or 32 MHz.
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
PLL operation is controlled through software. The con-
trol bit, PLLEN (OSCTUNE<6>), is used to enable or
disable its operation. The PLL is available only to
INTOSC when the device is configured to use one of
the INTPLL modes as the primary clock source
(FOSC<2:0> = 011or 001). Additionally, the PLL will
only function when the selected output frequency is
either 4 MHz or 8 MHz (OSCCON<6:4> = 111or 110).
• Two-Speed Start-up
These features are discussed in greater detail in
Section 25.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTOSC
with postscaler or INTRC direct) is selected by config-
uring the IRCF bits of the OSCCON register. The
default frequency on device Resets is 4 MHz.
Like the INTIO modes, there are two distinct INTPLL
modes available:
3.5.1
INTIO MODES
• In INTPLL1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output. Externally, this is identical in appearance
to INTIO1 (Figure 3-6).
Using the internal oscillator as the clock source elimi-
nates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
oscillator configurations, which are determined by the
FOSC Configuration bits, are available:
• In INTPLL2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output. Externally, this is identical to INTIO2
(Figure 3-7).
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 (see Figure 3-6) for
digital input and output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6 (see Figure 3-7), both for
digital input and output.
2010 Microchip Technology Inc.
DS39933D-page 41
PIC18F87J90 FAMILY
3.5.3
INTERNAL OSCILLATOR OUTPUT
FREQUENCY AND TUNING
3.5.4.2
Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8 MHz. It
can be adjusted in the user’s application by writing to
TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE
register (Register 3-2).
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
oscillator will stabilize within 1 ms. Code execution
continues during this shift and there is no indication that
the shift has occurred.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC or vice versa. The frequency of
INTRC is not affected by OSCTUNE.
3.5.4.3
Compensating with the CCP Module
in Capture Mode
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
3.5.4
INTOSC FREQUENCY DRIFT
The INTOSC frequency may drift as VDD or tempera-
ture changes, and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE
register. Depending on the device, this may have no
effect on the INTRC clock source frequency.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
3.5.4.1
Compensating with the EUSART
An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.
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Timer1 oscillator may be operating to support a Real-
Time Clock (RTC). Other features may be operating
that do not require a device clock source (i.e., MSSP
slave, INTx pins and others). Peripherals that may add
significant current consumption are listed in
Section 28.2 “DC Characteristics: Power-Down and
Supply Current PIC18F87J90 Family (Industrial)”.
3.6
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
3.7
Power-up Delays
In Secondary Clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 5.6 “Power-up Timer (PWRT)”.
In RC_RUN and RC_IDLE modes, the internal
oscillator provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 25.2 “Watchdog Timer (WDT)” through
Section 25.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 28-11); it is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
If Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
There is a delay of interval, TCSD (parameter 38,
Table 28-11), following POR, while the controller
becomes ready to execute instructions.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
TABLE 3-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
EC, ECPLL
HS, HSPLL
Floating, pulled by external clock
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
INTOSC, INTPLL1/2
I/O pin RA6, direction controlled by
TRISA<6>
I/O pin RA6, direction controlled by
TRISA<7>
Note:
See Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.
2010 Microchip Technology Inc.
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NOTES:
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PIC18F87J90 FAMILY
4.1.1
CLOCK SOURCES
4.0
POWER-MANAGED MODES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
The PIC18F87J90 family devices provide the ability to
manage power consumption by simply managing clock-
ing to the CPU and the peripherals. In general, a lower
clock frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power. For
the sake of managing power in an application, there are
three primary modes of operation:
• the primary clock, as defined by the FOSC<2:0>
Configuration bits
• the secondary clock (Timer1 oscillator)
• the internal oscillator
4.1.2
ENTERING POWER-MANAGED
MODES
• Run mode
• Idle mode
• Sleep mode
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 4.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources
(primary, secondary or internal oscillator block); the
Sleep mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous PIC®
devices. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC devices,
where all device clocks are stopped.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEPinstruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
4.1
Selecting Power-Managed Modes
Selecting
a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS<1:0> bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 4-1.
TABLE 4-1:
Mode
POWER-MANAGED MODES
OSCCON Bits Module Clocking
CPU Peripherals
Off Off
Available Clock and Oscillator Source
IDLEN<7>(1)
SCS<1:0>
Sleep
0
N/A
None – All clocks are disabled
PRI_RUN
N/A
10
Clocked Clocked Primary – HS, EC, HSPLL, ECPLL;
this is the normal full-power execution mode
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
N/A
N/A
1
01
11
10
01
11
Clocked Clocked Secondary – Timer1 Oscillator
Clocked Clocked Internal Oscillator
Off
Off
Off
Clocked Primary – HS, EC, HSPLL, ECPLL
Clocked Secondary – Timer1 Oscillator
Clocked Internal Oscillator
1
1
Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.
2010 Microchip Technology Inc.
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4.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
4.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
4.2.1
PRI_RUN MODE
Two bits indicate the current clock source and its
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 25.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set (see
Section 3.2 “Control Registers”).
status:
OSTS
(OSCCON<3>)
and
T1RUN
(T1CON<6>). In general, only one of these bits will be
set while in a given power-managed mode. When the
OSTS bit is set, the primary clock is providing the
device clock. When the T1RUN bit is set, the Timer1
oscillator is providing the clock. If neither of these bits
is set, INTRC is clocking the device.
4.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
Note:
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 4-1), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
4.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEPinstruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
DS39933D-page 46
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PIC18F87J90 FAMILY
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 4-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
FIGURE 4-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
T1OSI
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 4-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC + 4
PC
OSTS bit Set
SCS<1:0> bits Changed
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2010 Microchip Technology Inc.
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On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 4-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
4.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting the SCS bits to ‘11’.
When the clock source is switched to the INTRC (see
Figure 4-3), the primary oscillator is shut down and the
OSTS bit is cleared.
FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 4-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTRC
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC + 4
PC
SCS<1:0> bits Changed
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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4.3
Sleep Mode
4.4
Idle Modes
The power-managed Sleep mode is identical to the
legacy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 4-5). All
clock source status bits are cleared.
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEPinstruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS<1:0> bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source, selected by the SCS<1:0> bits,
becomes ready (see Figure 4-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor is enabled (see
Section 25.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 28-11) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT time-out
will result in a WDT wake-up to the Run mode currently
specified by the SCS<1:0> bits.
FIGURE 4-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 4-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2 Q3 Q4 Q1 Q2
Q1
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
PC + 6
Wake Event
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2010 Microchip Technology Inc.
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4.4.1
PRI_IDLE MODE
4.4.2
SEC_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEPinstruction. If
the device is in another Run mode, set IDLEN first, then
set SCS<1:0> to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then set the SCS bits to ‘10’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<1:0> Configuration bits. The OSTS bit
remains set (see Figure 4-7).
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD, following the wake event, the CPU begins exe-
cuting code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 4-8).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval, TCSD, is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 4-8).
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEPinstruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
FIGURE 4-7:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q3
Q4
Q1
Q1
Q2
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 4-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q3
Q4
Q2
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
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4.4.3
RC_IDLE MODE
4.5.2
EXIT BY WDT TIME-OUT
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator.
This mode allows for controllable power conservation
during Idle periods.
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 4.2 “Run
Modes” and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 25.2 “Watchdog
Timer (WDT)”).
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTRC, the primary oscillator
is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC. After a delay of TCSD,
following the wake event, the CPU begins executing
code being clocked by the INTOSC. The IDLEN and
SCS bits are not affected by the wake-up. The INTOSC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
The Watchdog Timer and postscaler are cleared by one
of the following events:
• executing a SLEEPor CLRWDTinstruction
• the loss of a currently selected clock source (if the
Fail-Safe Clock Monitor is enabled)
4.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
4.5
Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
mode sections (see Section 4.2 “Run Modes”,
Section 4.3 “Sleep Mode” and Section 4.4 “Idle
Modes”).
4.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is either the EC or
ECPLL mode.
4.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval, TCSD, following the wake event
is still required when leaving Sleep and Idle modes to
allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed delay of interval, TCSD, following the wake event,
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
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A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
5.0
RESET
The PIC18F87J90 family of devices differentiates
between various kinds of Reset:
5.1
RCON Register
• Power-on Reset (POR)
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 5.7 “Reset State of Registers”.
• MCLR Reset during normal operation
• MCLR Reset during power-managed modes
• Watchdog Timer (WDT) Reset (during
execution)
• Brown-out Reset (BOR)
• Configuration Mismatch (CM) Reset
• RESETInstruction
• Stack Full Reset
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
• Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.4.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 25.2 “Watchdog
Timer (WDT)”.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Configuration Word
Mismatch
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLR
IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
VDD
Brown-out
Reset
(1)
S
PWRT
Chip_Reset
32 s (typical)
65.5 ms (typical)
PWRT
11-Bit Ripple Counter
Q
R
INTRC
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
2010 Microchip Technology Inc.
DS39933D-page 53
PIC18F87J90 FAMILY
REGISTER 5-1:
RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
R/W-1
CM
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16XXXX Compatibility mode)
bit 6
bit 5
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
1= A configuration mismatch has not occurred
0= A configuration mismatch has occurred (must be set in software after a Configuration Mismatch
Reset occurs)
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware only)
0= The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-Down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Set by execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred (set by firmware only)
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent
Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 5.4.1 “Detecting
BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
DS39933D-page 54
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 5-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
5.2
Master Clear (MCLR)
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
VDD
VDD
D
R
The MCLR pin is not driven low by any internal Resets,
including the WDT.
R1
MCLR
PIC18F87J90
C
5.3
Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode, D, helps discharge the capacitor
quickly when VDD powers down.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 5-2.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 1 k will limit any current flowing into
MCLR from external capacitor, C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
5.4.1
DETECTING BOR
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
Power-on Reset events are captured by the POR bit
(RCON<1>). The state of the bit is set to ‘0’ whenever
a Power-on Reset occurs; it does not change for any
other Reset event. POR is not reset to ‘1’ by any
hardware event. To capture multiple events, the user
manually resets the bit to ‘1’ in software following any
Power-on Reset.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a Brown-out Reset event.
The BOR bit is still cleared by a Power-on Reset event.
5.4
Brown-out Reset (BOR)
The PIC18F87J90 family of devices incorporates a
simple BOR function when the internal regulator is
enabled (ENVREG pin is tied to VDD). The voltage reg-
ulator will trigger a Brown-out Reset when output of the
regulator to the device core approaches the voltage at
which the device is unable to run at full speed. The
BOR circuit also keeps the device in Reset as VDD
rises, until the regulator’s output level is sufficient for
full-speed operation.
5.5
Configuration Mismatch (CM)
The Configuration Mismatch (CM) Reset is designed to
detect, and attempt to recover from, random, memory
corrupting events. These include Electrostatic
Discharge (ESD) events that can cause widespread,
single bit changes throughout the device and result in
catastrophic failure.
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for TPWRT (parameter 33). If
VDD drops below the threshold for full-speed operation
while the Power-up Timer is running, the chip will go
back into a Brown-out Reset and the Power-up Timer
will be initialized. Once VDD rises to the point where the
regulator output is sufficient, the Power-up Timer will
execute the additional time delay.
In PIC18FXXJ Flash devices, the device Configuration
registers (located in the configuration memory space)
are continuously monitored during operation by com-
paring their values to complimentary shadow registers.
If a mismatch is detected between the two sets of
registers, a CM Reset automatically occurs. These
events are captured by the CM bit (RCON<5>). The
state of the bit is set to ‘0’ whenever a CM event occurs.
The bit does not change for any other Reset event.
2010 Microchip Technology Inc.
DS39933D-page 55
PIC18F87J90 FAMILY
5.6.1
TIME-OUT SEQUENCE
5.6
Power-up Timer (PWRT)
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 5-3, Figure 5-4,
Figure 5-5 and Figure 5-6 all depict time-out
sequences on power-up with the Power-up Timer
enabled.
PIC18F87J90 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F87J90 fam-
ily devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 s = 65.6 ms. While the
PWRT is counting, the device is held in Reset.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 for details.
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
DS39933D-page 56
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 5-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 5-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V
0V
1V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
2010 Microchip Technology Inc.
DS39933D-page 57
PIC18F87J90 FAMILY
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets, and WDT wake-ups.
5.7
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 5-1.
These bits are used in software to determine the nature
of the Reset.
TABLE 5-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Condition
Counter(1)
RI
TO
PD
POR
BOR
STKFUL STKUNF
Power-on Reset
RESETInstruction
Brown-out Reset
0000h
0000h
0000h
0000h
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
MCLR during power-managed
Run modes
MCLR during power-managed
Idle modes and Sleep mode
0000h
0000h
0000h
u
u
u
1
0
u
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
WDT time-out during full power
or power-managed Run modes
MCLR during full-power
execution
Stack Full Reset (STVREN = 1)
0000h
0000h
u
u
u
u
u
u
u
u
u
u
1
u
u
1
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u
u
u
0
u
0
u
u
u
u
u
u
1
u
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
Interrupt exit from
PC + 2
u
u
0
u
u
u
u
power-managed modes
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
DS39933D-page 58
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 5-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction
Stack Resets
TOSU
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
N/A
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 1111
1100 0000
N/A
---0 uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
uu-u uuuu(1)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
N/A
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific conditions.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
2010 Microchip Technology Inc.
DS39933D-page 59
PIC18F87J90 FAMILY
TABLE 5-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESETInstruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
FSR1H
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
---- xxxx
xxxx xxxx
---- 0000
N/A
---- uuuu
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0110 q000
-011 1100
0--- ---0
0-11 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0110 q000
-011 1000
0--- ---0
0-0q qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu quuu
-uuu uuuu
u--- ---u
u-uu qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LCDREG
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific conditions.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
DS39933D-page 60
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 5-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction
Stack Resets
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
LCDDATA4
LCDDATA4
LCDDATA3
LCDDATA2
LCDDATA1
LCDDATA0
LCDSE5
LCDSE4
LCDSE4
LCDSE3
LCDSE2
LCDSE1
CVRCON
CMCON
TMR3H
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
xxxx xxxx
xxxx xxxx
0-00 0000
0-00 0000
0-00 0000
---- ---x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
---- ---0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
000- 0000
---- ----
---0 x00-
uuuu uuuu
uuuu uuuu
0-00 0000
0-00 0000
0-00 0000
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0111
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
uuuu uuuu
000- 0000
---- ----
---0 u00-
uuuu uuuu
uuuu uuuu
u-uu uuuu
u-uu uuuu
u-uu uuuu
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- uuuu
---- ----
---0 u00-
TMR3L
T3CON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
LCDPS
LCDSE0
LCDCON
EECON2
EECON1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific conditions.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
2010 Microchip Technology Inc.
DS39933D-page 61
PIC18F87J90 FAMILY
TABLE 5-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESETInstruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
IPR3
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
-111 1111
-000 0000
-000 0000
11-- 111-
00-- 000-
00-- 000-
-111 1-11
-000 0-00
-000 0-00
0000 0000
1111 1111
1111 1111
0001 1111
1111 111-
1111 1-11
1111 1111
1111 1111
1111 1111
1111 1111(5)
xxxx xxxx
xxxx xxxx
00-x xxxx
xxxx xxx-
xxxx x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx(5)
xxxx xxxx
xxxx xxxx
000x xxxx
xxxx xxx-
-111 1111
-000 0000
-000 0000
11-- 111-
00-- 000-
00-- 000-
-111 1-11
-000 0-00
-000 0-00
0000 0000
1111 1111
1111 1111
0001 1111
1111 111-
1111 1-11
1111 1111
1111 1111
1111 1111
1111 1111(5)
uuuu uuuu
uuuu uuuu
00-u uuuu
uuuu uuu-
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
uuuu uuuu
uuuu uuuu
000u uuuu
uuuu uuu-
-uuu 1111
-uuu 0000(3)
-uuu 0000
uu-- uuu-
uu-- uuu-(3)
uu-- uuu-
-uuu u-uu
-uuu u-uu(3)
-uuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuu-
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
uuuu uuuu
uuuu uuuu
uu-u uuuu
uuuu uuu-
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
uuuu uuuu
uuuu uuuu
000u uuuu
uuuu uuu-
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA(5)
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA(5)
PORTJ
PORTH
PORTG
PORTF
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific conditions.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
DS39933D-page 62
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 5-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction
Stack Resets
PORTE
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
xxxx x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000(5)
0000 0000
0100 0-00
xxxx xxxx
---- ---x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- ---x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- ---x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu0u 0000(5)
0000 0000
0100 0-00
uuuu uuuu
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
uuuu uuuu
uuuu u-uu
uuuu uuuu
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
PORTD
PORTC
PORTB
PORTA(5)
SPBRGH1
BAUDCON1
LCDDATA23
LCDDATA22
LCDDATA22
LCDDATA21
LCDDATA20
LCDDATA19
LCDDATA18
LCDDATA17
LCDDATA16
LCDDATA16
LCDDATA15
LCDDATA14
LCDDATA13
LCDDATA12
LCDDATA11
LCDDATA10
LCDDATA10
LCDDATA9
LCDDATA8
LCDDATA7
LCDDATA6
LCDDATA5
CCPR1H
CCPR1L
CCP1CON
CCPR2H
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific conditions.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
2010 Microchip Technology Inc.
DS39933D-page 63
PIC18F87J90 FAMILY
TABLE 5-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESETInstruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
CCPR2L
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
PIC18F6XJ90 PIC18F8XJ90
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
0-00 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
0000 0000
---- -00-
uuuu uuuu
--00 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
0-00 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0-00 0000
0000 0000
0000 0000
---- -00-
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
---- -uu-
CCP2CON
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
RTCCFG
RTCCAL
RTCVALH
RTCVALL
ALRMCFG
ALRMRPT
ALRMVALH
ALRMVALL
CTMUCONH
CTMUCONL
CTMUICON
PADCFG1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific conditions.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
DS39933D-page 64
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
6.1
Program Memory Organization
6.0
MEMORY ORGANIZATION
PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOPinstruction).
There are two types of memory in PIC18 Flash
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
The entire PIC18F87J90 family offers a range of
on-chip Flash program memory sizes, from 64 Kbytes
(up to 16,384 single-word instructions) to 128 Kbytes
(65,536 single-word instructions). The program
memory maps for individual family members are shown
in Figure 6-1.
Additional detailed information on the operation of the
Flash program memory is provided in Section 7.0
“Flash Program Memory”.
FIGURE 6-1:
MEMORY MAPS FOR PIC18F87J90 FAMILY DEVICES
PC<20:0>
21
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
ADDULNK, SUBULNK
Stack Level 1
Stack Level 31
PIC18FX7J90
PIC18FX6J90
On-Chip
000000h
00FFFFh
01FFFFh
On-Chip
Memory
Memory
Config. Words
Config. Words
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
1FFFFFh
Note:
Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
2010 Microchip Technology Inc.
DS39933D-page 65
PIC18F87J90 FAMILY
6.1.1
HARD MEMORY VECTORS
6.1.2
FLASH CONFIGURATION WORDS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
program counter returns on all device Resets; it is
located at 0000h.
Because PIC18F87J90 family devices do not have per-
sistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
PIC18 devices also have two interrupt vector
addresses for the handling of high-priority and
low-priority interrupts. The high-priority interrupt vector
is located at 0008h and the low-priority interrupt vector
is at 0018h. Their locations in relation to the program
memory map are shown in Figure 6-2.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and end-
ing with the upper byte of CONFIG4. For these devices,
only Configuration Words, CONFIG1 through
CONFIG3, are used; CONFIG4 is reserved. The actual
addresses of the Flash Configuration Word for devices
in the PIC18F87J90 family are shown in Table 6-1.
Their location in the memory map is shown with the
other memory vectors in Figure 6-2.
FIGURE 6-2:
HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
Additional details on the device Configuration Words
are provided in Section 25.1 “Configuration Bits”.
PIC18F87J90 FAMILY
FAMILY DEVICES
TABLE 6-1:
FLASH CONFIGURATION
WORD FOR PIC18F87J90
FAMILY DEVICES
0000h
0008h
Reset Vector
High-Priority Interrupt Vector
Low-Priority Interrupt Vector 0018h
Program
Configuration Word
Memory
Device
Addresses
(Kbytes)
PIC18F66J90
PIC18F86J90
PIC18F67J90
PIC18F87J90
64
FFF8h to FFFFh
On-Chip
Program Memory
128
1FFF8h to 1FFFFh
(Top of Memory-7)
(Top of Memory)
Flash Configuration Words
Read ‘0’
1FFFFFh
Legend:
(Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 6-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
DS39933D-page 66
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable, and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from, the stack, using these
registers.
6.1.3
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
A CALLtype instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURNtype instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 6.1.6.1 “Computed
GOTO”).
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
6.1.4.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, holds the contents of the stack
location pointed to by the STKPTR register (Figure 6-3).
This allows users to implement a software stack, if nec-
essary. After a CALL, RCALLor interrupt (and ADDULNK
and SUBULNKinstructions if the extended instruction set
is enabled), the software can read the pushed value by
reading the TOSU:TOSH:TOSL registers. These values
can be placed on a user-defined software stack. At
return time, the software can return these values to
TOSU:TOSH:TOSL and do a return.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
6.1.4
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALLor RCALLinstruc-
tion is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLWor
a RETFIEinstruction (and on ADDULNKand SUBULNK
instructions if the extended instruction set is enabled).
PCLATU and PCLATH are not affected by any of the
RETURNor CALLinstructions.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 6-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack <20:0>
Stack Pointer
Top-of-Stack Registers
11111
11110
11101
STKPTR<4:0>
TOSU TOSH TOSL
00010
00h
1Ah
34h
00011
00010
00001
00000
001A34h
000D58h
Top-of-Stack
2010 Microchip Technology Inc.
DS39933D-page 67
PIC18F87J90 FAMILY
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and set the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
6.1.4.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 6-1) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and the
STKUNF (Stack Underflow) status bit. The value of the
Stack Pointer can be 0 through 31. The Stack Pointer
increments before values are pushed onto the stack and
decrements after values are popped off of the stack. On
Reset, the Stack Pointer value will be zero. The user
may read and write the Stack Pointer value. This feature
can be used by a Real-Time Operating System (RTOS)
for return stack maintenance.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset as the contents of
the SFRs are not affected.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
6.1.4.3
PUSHand POPInstructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execu-
tion, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) Configuration bit. (Refer to
Section 25.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
The PUSHinstruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
REGISTER 6-1:
STKPTR: STACK POINTER REGISTER
R/C-0
STKFUL(1)
R/C-0
STKUNF(1)
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
STKFUL: Stack Full Flag bit(1)
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit(1)
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP<4:0>: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
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2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
6.1.4.4
Stack Full and Underflow Resets
6.1.6
LOOK-UP TABLES IN PROGRAM
MEMORY
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 1L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
6.1.6.1
Computed GOTO
6.1.5
FAST REGISTER STACK
A computed GOTOis accomplished by adding an offset
to the program counter. An example is shown in
Example 6-2.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. This stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the Stack registers. The values in
the registers are then loaded back into the working
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nninstructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
If both low and high-priority interrupts are enabled, the
Stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the Stack
register values stored by the low-priority interrupt will
be overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
EXAMPLE 6-2:
COMPUTED GOTOUSING
AN OFFSET VALUE
OFFSET, W
TABLE
MOVF
CALL
ORG
TABLE
nn00h
ADDWF
RETLW
RETLW
RETLW
.
PCL
nnh
nnh
nnh
.
Example 6-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
.
6.1.6.2
Table Reads
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
EXAMPLE 6-1:
FAST REGISTER STACK
CODE EXAMPLE
CALL
SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
Look-up table data may be stored two bytes per
program word while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory, one byte at a time.
SUB1
RETURN FAST ;RESTORE VALUES SAVED
Table read operation is discussed further in
;IN FAST REGISTER STACK
Section 7.1 “Table Reads and Table Writes”.
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
6.2.2
INSTRUCTION FLOW/PIPELINING
6.2
PIC18 Instruction Cycle
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute take another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example 6-3).
6.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the
Instruction Register (IR) during Q4. The instruction is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow are
shown in Figure 6-4.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle, Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 6-4:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
Internal
Phase
Clock
PC
PC + 2
PC + 4
PC
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 6-3:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS39933D-page 70
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>
which accesses the desired byte address in program
memory. Instruction #2 in Figure 6-5 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 26.0 “Instruction Set Summary”
provides further details of the instruction set.
6.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte (LSB) of an
instruction word is always stored in a program memory
location with an even address (LSB = 0). To maintain
alignment with instruction boundaries, the PC
increments in steps of 2 and the LSB will always read
‘0’ (see Section 6.1.3 “Program Counter”).
Figure 6-5 shows an example of how instruction words
are stored in the program memory.
FIGURE 6-5:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
Program Memory
Byte Locations
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Instruction 3:
MOVFF
123h, 456h
used by the instruction sequence. If the first word is
skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 6-4 shows how this works.
6.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four, two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits (MSb); the other
12 bits are literal data, usually a data memory address.
Note:
See Section 6.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in the
extended instruction set.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence, immediately after the
first word, the data in the second word is accessed and
EXAMPLE 6-4:
CASE 1:
TWO-WORD INSTRUCTIONS
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
REG1
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
; continue code
; is RAM location 0?
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
CASE 2:
MOVFF
ADDWF
REG3
Object Code
Source Code
TSTFSZ
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
ADDWF
REG3
; continue code
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
6.3.1
BANK SELECT REGISTER
6.3
Data Memory Organization
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Note:
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 6.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4,096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. PIC18FX6J90
and PIC18FX7J90 devices implement all 16 complete
banks, for a total of 4 Kbytes. Figure 6-6 and Figure 6-7
show the data memory organization for the devices.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR<3:0>). The upper four bits
are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLBinstruction.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The value of the BSR indicates the bank in data
memory. The 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figure 6-7.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h, while the BSR
is 0Fh, will end up resetting the program counter.
To ensure that commonly used registers (select SFRs
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
select SFRs, and the lower portion of GPR Bank 0,
without using the BSR. Section 6.3.2 “Access Bank”
provides a detailed description of the Access RAM.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 6-6 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
DS39933D-page 72
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 6-6:
BSR<3:0>
= 0000
DATA MEMORY MAP FOR PIC18FX6J90 AND PIC18FX7J90 DEVICES
When a = 0:
Data Memory Map
The BSR is ignored and the
Access Bank is used.
00h
000h
05Fh
060h
0FFh
100h
Access RAM
GPR
The first 96 bytes are general
purpose RAM (from Bank 0).
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
FFh
00h
The second 160 bytes are
Special Function Registers
(from Bank 15).
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
GPR
GPR
GPR
GPR
GPR
GPR
GPR
1FFh
200h
FFh
00h
When a = 1:
The BSR specifies the bank
used by the instruction.
FFh
00h
2FFh
300h
3FFh
400h
FFh
00h
FFh
00h
4FFh
500h
FFh
00h
5FFh
600h
FFh
00h
6FFh
700h
Access Bank
00h
FFh
00h
7FFh
800h
Access RAM Low
5Fh
60h
= 1000
= 1001
Access RAM High
(SFRs)
GPR
Bank 8
FFh
FFh
00h
8FFh
900h
Bank 9
GPR
GPR
GPR
GPR
GPR
GPR
9FFh
A00h
FFh
00h
= 1010
= 1011
Bank 10
Bank 11
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
00h
= 1100
= 1101
Bank 12
Bank 13
Bank 14
Bank 15
CFFh
D00h
FFh
00h
DFFh
E00h
FFh
00h
= 1110
= 1111
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
GPR(1)
SFR
FFh
Note 1: Addresses, F54h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
Users must always use the complete address, or load the proper BSR value, to access these
registers.
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
FIGURE 6-7:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Data Memory
(2)
(1)
From Opcode
1 1
BSR
000h
100h
7
0
7
0
00h
Bank 0
0
0
0
0
0
0
1
0
1
1
1
1
1 1
FFh
00h
Bank 1
Bank 2
(2)
Bank Select
FFh
00h
200h
300h
FFh
00h
Bank 3
through
Bank 13
FFh
00h
E00h
Bank 14
Bank 15
FFh
00h
F00h
FFFh
FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>)
to the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
6.3.2
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of data
memory, it also means that the user must always ensure
that the correct bank is selected. Otherwise, data may
be read from, or written to, the wrong location. This can
be disastrous if a GPR is the intended target of an oper-
ation, but an SFR is written to instead. Verifying and/or
changing the BSR for each read or write to data memory
can become very inefficient.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 6-6).
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 6.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
6.3.3
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
DS39933D-page 74
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
6.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
more than the top half of Bank 15 (F60h to FFFh). A list
of these registers is given in Table 6-2 and Table 6-3.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 6-2:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J90 FAMILY DEVICES
Addr.
Name
Addr.
FDFh INDF2
FDEh POSTINC2
Name
Addr.
Name
Addr.
Name
Addr.
Name
Addr.
Name
(1)
(3)
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
TOSU
TOSH
FBFh LCDDATA4
F9Fh
IPR1
PIR1
PIE1
F7Fh SPBRGH1
F5Fh
RTCCFG
RTCCAL
RTCVALH
RTCVALL
(1)
(1)
FBEh LCDDATA3 F9Eh
FBDh LCDDATA2 F9Dh
FBCh LCDDATA1 F9Ch
F7Eh BAUDCON1 F5Eh
(3)
TOSL
FDDh POSTDEC2
F7Dh LCDDATA23
F7Ch LCDDATA22
F5Dh
F5Ch
(1)
(2)
(3)
STKPTR
PCLATU
PCLATH
PCL
FDCh PREINC2
—
(1)
FDBh PLUSW2
FBBh LCDDATA0 F9Bh OSCTUNE F7Bh LCDDATA21
F5Bh ALRMCFG
F5Ah ALRMRPT
F59h ALRMVALH
F58h ALRMVALL
F57h CTMUCONH
F56h CTMUCONL
F55h CTMUICON
F54h PADCFG1
(3)
(3)
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FSR2H
FSR2L
FBAh LCDSE5
FB9h LCDSE4
F9Ah TRISJ
F7Ah LCDDATA20
F79h LCDDATA19
F78h LCDDATA18
(3)
(3)
F99h TRISH
F98h TRISG
FF8h TBLPTRU
FF7h TBLPTRH
FF6h TBLPTRL
STATUS
TMR0H
TMR0L
T0CON
FB8h LCDSE3
FB7h LCDSE2
FB6h LCDSE1
FB5h CVRCON
FB4h CMCON
(3)
F97h
F96h
F95h
F94h
F93h
F92h
TRISF
TRISE
TRISD
TRISC
TRISB
F77h LCDDATA17
F76h LCDDATA16
(3)
FF5h
FF4h
FF3h
FF2h
TABLAT
PRODH
PRODL
INTCON
F75h LCDDATA15
F74h LCDDATA14
F73h LCDDATA13
F72h LCDDATA12
F71h LCDDATA11(3)
F70h LCDDATA10(3)
F6Fh LCDDATA9
F6Eh LCDDATA8
F6Dh LCDDATA7
F6Ch LCDDATA6
(2)
—
FD3h OSCCON
FD2h LCDREG
FD1h WDTCON
FB3h
FB2h
FB1h
FB0h
TMR3H
TMR3L
T3CON
TRISA
(3)
FF1h INTCON2
F91h LATJ
F90h LATH
(2)
(3)
FF0h INTCON3
FD0h
FCFh
FCEh
RCON
TMR1H
TMR1L
T1CON
TMR2
—
(1)
FEFh
INDF0
FAFh SPBRG1
FAEh RCREG1
FADh TXREG1
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
LATG
(1)
(1)
FEEh POSTINC0
LATF
LATE
LATD
LATC
LATB
LATA
FEDh POSTDEC0 FCDh
(1)
FECh PREINC0
FCCh
FCBh
FCAh
FACh
FABh RCSTA1
FAAh LCDPS
TXSTA1
(1)
(3)
FEBh PLUSW0
PR2
F6Bh LCDDATA5
FEAh
FE9h
FE8h
FE7h
FSR0H
FSR0L
WREG
T2CON
F6Ah
F69h
CCPR1H
CCPR1L
FC9h SSPBUF
FC8h SSPADD
FC7h SSPSTAT
FC6h SSPCON1
FC5h SSPCON2
FC4h ADRESH
FC3h ADRESL
FC2h ADCON0
FC1h ADCON1
FC0h ADCON2
FA9h LCDSE0
FA8h LCDCON
FA7h EECON2
FA6h EECON1
(3)
F88h PORTJ
F68h CCP1CON
(1)
(3)
INDF1
F87h PORTH
F86h PORTG
F85h PORTF
F84h PORTE
F83h PORTD
F82h PORTC
F81h PORTB
F80h PORTA
F67h
F66h
CCPR2H
CCPR2L
(1)
(1)
FE6h POSTINC1
FE5h POSTDEC1
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
F65h CCP2CON
(1)
FE4h PREINC1
F64h
F63h
F62h
F61h
F60h
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
(1)
FE3h PLUSW1
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available on PIC18F6XJ90 devices.
2010 Microchip Technology Inc.
DS39933D-page 75
PIC18F87J90 FAMILY
TABLE 6-3:
PIC18F87J90 FAMILY REGISTER FILE SUMMARY
Value on Detailson
POR, BOR page
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 59, 67
0000 0000 59, 67
0000 0000 59, 67
uu-0 0000 59, 68
---0 0000 59, 67
0000 0000 59, 67
0000 0000 59, 67
--00 0000 59, 92
0000 0000 59, 92
0000 0000 59, 92
0000 0000 59, 92
xxxx xxxx 59, 99
xxxx xxxx 59, 99
0000 000x 59, 103
1111 1111 59, 104
1100 0000 59, 105
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
Return Stack Pointer
bit 21(1) Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
INTCON
INTCON2
INTCON3
INDF0
GIE/GIEH PEIE/GIEL
TMR0IE
INTEDG1
INT3IE
INT0IE
INTEDG2
INT2IE
RBIE
INTEDG3
INT1IE
TMR0IF
TMR0IP
INT3IF
INT0IF
INT3IP
INT2IF
RBIF
RBIP
RBPU
INTEDG0
INT1IP
INT2IP
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
59, 83
59, 84
59, 84
59, 84
59, 84
POSTINC0
POSTDEC0
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- xxxx 59, 83
xxxx xxxx 59, 83
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
xxxx xxxx
N/A
59
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
59, 83
59, 84
59, 84
59, 84
59, 84
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- xxxx 60, 83
xxxx xxxx 60, 83
---- 0000 60, 72
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
60, 83
60, 84
60, 84
60, 84
60, 84
POSTINC2
POSTDEC2
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
FSR2H
FSR2L
STATUS
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- xxxx 60, 83
xxxx xxxx 60, 83
---x xxxx 60, 81
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV DC
Z
C
Legend:
Note 1:
2:
x
= unknown,
u
= unchanged,
-
= unimplemented,
q
= value depends on condition, r= reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘
0’. Reset states shown are
for 80-pin devices.
3:
4:
5:
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = ); otherwise, they are disabled and these bits read as ‘ ’.
0
0
DS39933D-page 76
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 6-3:
PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Value on Detailson
POR, BOR page
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0H
TMR0L
T0CON
OSCCON
LCDREG
WDTCON
RCON
Timer0 Register High Byte
Timer0 Register Low Byte
0000 0000 60, 141
xxxx xxxx 60, 141
1111 1111 60, 141
0110 q000 36, 60
TMR0ON
IDLEN
—
T08BIT
IRCF2
CPEN
—
T0CS
IRCF1
BIAS2
—
T0SE
IRCF0
BIAS1
—
PSA
OSTS
BIAS0
—
T0PS2
IOFS
MODE13
—
T0PS1
SCS1
CKSEL1
—
T0PS0
SCS0
CKSEL0 -011 1100 60, 189
SWDTEN 0--- ---0 60, 332
REGSLP
IPEN
—
CM
RI
TO
PD
POR
BOR
0-11 11q0 54, 60
xxxx xxxx 60, 147
xxxx xxxx 60, 147
TMR1H
TMR1L
T1CON
TMR2
Timer1 Register High Byte
Timer1 Register Low Byte
RD16
T1RUN
T1CKPS1
T1CKPS0 T1OSCEN
T1SYNC
TMR1CS
T2CKPS1
TMR1ON 0000 0000 60, 143
0000 0000 60, 150
Timer2 Register
PR2
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON
MSSP Receive Buffer/Transmit Register
1111 1111 60, 150
T2CON
SSPBUF
—
T2CKPS0 -000 0000 60, 149
xxxx xxxx 60, 219,
254
SSPADD
SSPSTAT
MSSP Address Register in I2C™ Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode.
0000 0000 60, 254
SMP
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 60, 212,
221
SSPCON1
SSPCON2
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM1
SSPM0
0000 0000 60, 213,
222
GCEN
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
RSEN
SEN
SEN
0000 0000 60, 223,
224
ACKSTAT ADMSK5(3) ADMSK4(3) ADMSK3(3) ADMSK2(3) ADMSK1(3)
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
LCDDATA4
LCDDATA3
LCDDATA2
LCDDATA1
LCDDATA0
LCDSE5(2)
LCDSE4
LCDSE3
LCDSE2
LCDSE1
CVRCON
CMCON
A/D Result Register High Byte
A/D Result Register Low Byte
xxxx xxxx 61, 297
xxxx xxxx 61, 297
0-00 0000 61, 289
0-00 0000 61, 290
0-00 0000 61, 291
xxxx xxxx 61, 187
xxxx xxxx 61, 187
xxxx xxxx 61, 187
xxxx xxxx 61, 187
xxxx xxxx 61, 187
0000 0000 61, 187
0000 0000 61, 187
0000 0000 61, 187
0000 0000 61, 187
0000 0000 61, 187
0000 0000 61, 305
0000 0111 61, 299
xxxx xxxx 61, 153
xxxx xxxx 61, 153
ADCAL
TRIGSEL
ADFM
S39C0(2)
S31C0
S23C0
S15C0
S07C0
SE47
—
—
CHS3
VCFG1
ACQT2
S37C0(2)
S29C0
S21C0
S13C0
S05C0
SE45
CHS2
VCFG0
ACQT1
S36C0(2)
S28C0
S20C0
S12C0
S04C0
SE44
CHS1
PCFG3
ACQT0
S35C0(2)
S27C0
S19C0
S11C0
S03C0
SE43
CHS0
PCFG2
ADCS2
S34C0(2)
S26C0
S18C0
S10C0
S02C0
SE42
GO/DONE
PCFG1
ADCS1
S33C0(2)
S25C0
S17C0
S09C0
S01C0
SE41
ADON
PCFG0
ADCS0
S32C0
S24C0
S16C0
S08C0
S00C0
SE40
—
S38C0(2)
S30C0
S22C0
S14C0
S06C0
SE46
SE39(2)
SE38(2)
S37(2)
SE36(2)
SE35(2)
SE34(2)
SE33(2)
SE32
SE31
SE30
SE29
SE28
SE27
SE26
SE25
SE24
SE23
SE22
SE21
SE20
SE19
SE18
SE17
SE16
SE15
SE14
SE13
SE12
SE11
SE10
SE09
SE08
CVREN
C2OUT
CVROE
C1OUT
CVRR
C2INV
CVRSS
C1INV
CVR3
CIS
CVR2
CVR1
CVR0
CM0
CM2
CM1
TMR3H
Timer3 Register High Byte
Timer3 Register Low Byte
TMR3L
T3CON
RD16
= unknown,
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON 0000 0000 61, 151
Legend:
Note 1:
2:
x
u
= unchanged, -= unimplemented, q= value depends on condition, r= reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘
0’. Reset states shown are
for 80-pin devices.
3:
4:
5:
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = ); otherwise, they are disabled and these bits read as ‘ ’.
0
0
2010 Microchip Technology Inc.
DS39933D-page 77
PIC18F87J90 FAMILY
TABLE 6-3:
PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Value on Detailson
POR, BOR page
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
LCDPS
LCDSE0
LCDCON
EECON2
EECON1
IPR3
EUSART Baud Rate Generator Low Byte
EUSART Receive Register
0000 0000 61, 259
0000 0000 61, 267
0000 0000 61, 265
0000 0010 61, 256
0000 000x 61, 257
0000 0000 61, 185
0000 0000 61, 186
000- 0000 61, 184
---- ---- 61, 90
--00 x00- 61, 90
-111 1111 62, 114
-000 0000 62, 108
-000 0000 62, 111
11-- 111- 62, 113
00-- 000- 62, 107
00-- 000- 62, 110
-111 1-11 62, 112
-000 0-00 62, 106
-000 0-00 62, 109
0000 0000 37, 62
1111 1111 62, 138
1111 1111 62, 136
0001 1111 62, 134
1111 111- 62, 132
1111 1-11 62, 129
1111 1111 62, 127
1111 1111 62, 125
1111 1111 62, 122
1111 1111 62, 119
xxxx xxxx 62, 138
xxxx xxxx 62, 136
00-x xxxx 62, 134
xxxx xxx- 62, 132
xxxx x-xx 62, 129
xxxx xxxx 62, 127
xxxx xxxx 62, 125
xxxx xxxx 62, 122
xxxx xxxx 62, 119
EUSART Transmit Register
CSRC
SPEN
WFT
TX9
RX9
TXEN
SREN
LCDA
SE05
SYNC
CREN
WA
SENDB
ADDEN
LP3
BRGH
FERR
LP2
TRMT
OERR
LP1
TX9D
RX9D
LP0
BIASMD
SE06
SE07
SE04
—
SE03
CS1
SE02
CS0
SE01
SE00
LMUX0
LCDEN
SLPEN
WERR
LMUX1
EEPROM Control Register 2 (not a physical register)
—
—
—
WPROG
RC2IP
RC2IF
RC2IE
—
FREE
TX2IP
TX2IF
TX2IE
—
WRERR
CTMUIP
CTMUIF
CTMUIE
BCLIP
WREN
CCP2IP
CCP2IF
CCP2IE
LVDIP
LVDIF
LVDIE
—
WR
—
LCDIP
LCDIF
LCDIE
CMIP
CCP1IP
CCP1IF
CCP1IE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
RTCCIP
RTCCIF
RTCCIE
—
PIR3
—
PIE3
—
IPR2
OSCFIP
OSCFIF
OSCFIE
—
PIR2
CMIF
—
—
BCLIF
—
PIE2
CMIE
—
—
BCLIE
—
IPR1
ADIP
RC1IP
RC1IF
RC1IE
TUN5
TX1IP
TX1IF
TX1IE
TUN4
SSPIP
SSPIF
TMR1IP
TMR1IF
TMR1IE
TUN0
PIR1
—
ADIF
—
PIE1
—
ADIE
SSPIE
TUN3
—
OSCTUNE
TRISJ(2)
TRISH(2)
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ(2)
LATH(2)
LATG
INTSRC
TRISJ7
TRISH7
SPIOD
TRISF7
TRISE7
TRISD7
TRISC7
TRISB7
TRISA7(5)
LATJ7
LATH7
U2OD
LATF7
LATE7
LATD7
LATC7
LATB7
LATA7(5)
PLLEN(4)
TRISJ6
TRISH6
CCP2OD
TRISF6
TRISE6
TRISD6
TRISC6
TRISB6
TRISA6(5)
LATJ6
TUN2
TRISJ2
TRISH2
TRISG2
TRISF2
—
TRISJ5
TRISH5
CCP1OD
TRISF5
TRISE5
TRISD5
TRISC5
TRISB5
TRISA5
LATJ5
TRISJ4
TRISH4
TRISG4
TRISF4
TRISE4
TRISD4
TRISC4
TRISB4
TRISA4
LATJ4
LATH4
LATG4
LATF4
LATE4
LATD4
LATC4
LATB4
LATA4
TRISJ3
TRISH3
TRISG3
TRISF3
TRISE3
TRISD3
TRISC3
TRISB3
TRISA3
LATJ3
TRISJ1
TRISH1
TRISG1
TRISF1
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
LATJ1
TRISJ0
TRISH0
TRISG0
—
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
LATJ0
LATH0
LATG0
—
TRISD2
TRISC2
TRISB2
TRISA2
LATJ2
LATH2
LATG2
LATF2
—
LATH6
U1OD
LATH5
—
LATH3
LATG3
LATF3
LATH1
LATG1
LATF1
LATF
LATF6
LATE6
LATD6
LATC6
LATB6
LATA6(5)
LATF5
LATE5
LATD5
LATC5
LATB5
LATA5
= unimplemented,
LATE
LATE3
LATD3
LATC3
LATB3
LATA3
LATE1
LATE0
LATD0
LATC0
LATB0
LATA0
LATD
LATD2
LATC2
LATB2
LATA2
LATD1
LATC1
LATB1
LATC
LATB
LATA
LATA1
Legend:
Note 1:
2:
x
= unknown,
u
= unchanged,
-
q= value depends on condition, r= reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘
0
’. Reset states shown are
for 80-pin devices.
3:
4:
5:
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = ); otherwise, they are disabled and these bits read as ‘ ’.
0
0
DS39933D-page 78
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 6-3:
PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Value on Detailson
POR, BOR page
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTJ(2)
PORTH(2)
RJ7
RH7
RJ6
RH6
RJ5
RH5
RJPU(2)
RJ4
RH4
RG4
RF4
RE4
RD4
RC4
RB4
RA4
RJ3
RH3
RG3
RF3
RE3
RD3
RC3
RB3
RA3
RJ2
RH2
RG2
RF2
—
RJ1
RH1
RG1
RF1
RE1
RD1
RC1
RB1
RA1
RJ0
RH0
RG0
—
xxxx xxxx 62, 138
xxxx xxxx 62, 136
000x xxxx 62, 134
xxxx xxx- 62, 132
xxxx x-xx 63, 129
xxxx xxxx 63, 127
xxxx xxxx 63, 125
xxxx xxxx 63, 122
xx0x 0000 63, 119
0000 0000 63, 259
0100 0-00 63, 258
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 187
xxxx xxxx 63, 174
xxxx xxxx 63, 174
PORTG
RDPU
RF7
REPU
RF6
PORTF
RF5
PORTE
RE7
RE6
RE5
RE0
RD0
RC0
RB0
RA0
PORTD
RD7
RD6
RD5
RD2
RC2
RB2
RA2
PORTC
RC7
RC6
RC5
PORTB
RB7
RA7(5)
RB6
RA6(5)
RB5
PORTA
RA5
SPBRGH1
BAUDCON1
LCDDATA23(2)
LCDDATA22
LCDDATA21
LCDDATA20
LCDDATA19
LCDDATA18
LCDDATA17(2)
LCDDATA16
LCDDATA15
LCDDATA14
LCDDATA13
LCDDATA12
LCDDATA11(2)
LCDDATA10
LCDDATA9
LCDDATA8
LCDDATA7
LCDDATA6
LCDDATA5(2)
CCPR1H
EUSART Baud Rate Generator High Byte
ABDOVF
S47C3
S39C3(2)
S31C3
S23C3
S15C3
S07C3
S47C2
S39C2(2)
S31C2
S23C2
S15C2
S07C2
S47C1
S39C1(2)
S31C1
S23C1
S15C1
S07C1
S47C0
RCIDL
S46C3
S38C3(2)
S30C3
S22C3
S14C3
S06C3
S46C2
S38C2(2)
S30C2
S22C2
S14C2
S06C2
S46C1
S38C1(2)
S30C1
S22C1
S14C1
S06C1
S46C0
RXDTP
S45C3
S37C3(2)
S29C3
S21C3
S13C3
S05C3
S45C2
S37C2(2)
S29C2
S21C2
S13C2
S05C2
S45C1
S37C1(2)
S29C1
S21C1
S13C1
S05C1
S45C0
TXCKP
S44C3
S36C3(2)
S28C3
S20C3
S12C3
S04C3
S44C2
S36C2(2)
S28C2
S20C2
S12C2
S04C2
S44C1
S36C1(2)
S28C1
S20C1
S12C1
S04C1
S44C0
BRG16
S43C3
S35C3(2)
S27C3
S19C3
S11C3
S03C3
S43C2
S35C2(2)
S27C2
S19C2
S11C2
S03C2
S43C1
S35C1(2)
S27C1
S19C1
S11C1
S03C1
S43C0
—
WUE
S41C3
S33C3(2)
S25C3
S17C3
S09C3
S01C3
S41C2
S33C2(2)
S25C2
S17C2
S09C2
S01C2
S41C1
S33C1(2)
S25C1
S17C1
S09C1
S01C1
S41C0
ABDEN
S40C3
S32C3
S24C3
S16C3
S08C3
S00C3
S40C2
S32C2
S24C2
S16C2
S08C2
S00C2
S40C1
S32C1
S24C1
S16C1
S08C1
S00C1
S40C0
S42C3
S34C3(2)
S26C3
S18C3
S10C3
S02C3
S42C2
S34C2(2)
S26C2
S18C2
S10C2
S02C2
S42C1
S34C1(2)
S26C1
S18C1
S10C1
S02C1
S42C0
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
CCPR1L
CCP1CON
CCPR2H
—
—
DC1B1
DC1B0
CCP1M3
CCP2M3
CCP1M2
CCP2M2
CCP1M1
CCP2M1
CCP1M0 --00 0000 63, 173
xxxx xxxx 63, 174
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
CCPR2L
xxxx xxxx 64, 174
CCP2CON
SPBRG2
—
—
DC2B1
DC2B0
CCP2M0 --00 0000 64, 173
0000 0000 64, 278
AUSART Baud Rate Generator Register
AUSART Receive Register
RCREG2
0000 0000 64, 283
TXREG2
AUSART Transmit Register
0000 0000 64, 281
TXSTA2
CSRC
SPEN
RTCEN
CAL7
TX9
RX9
—
TXEN
SREN
SYNC
CREN
—
BRGH
FERR
RTCOE
CAL2
TRMT
OERR
TX9D
RX9D
0000 -010 64, 276
0000 000x 64, 277
RCSTA2
ADDEN
RTCCFG
RTCWREN RTCSYNC HALFSEC
CAL5 CAL4 CAL3
RTCPTR1 RTCPTR0 0-00 0000 64, 157
RTCCAL
CAL6
CAL1
CAL0
0000 0000 64, 158
xxxx xxxx 64, 160
RTCVALH
RTCC Value High Register Window based on RTCPTR<1:0>
= unknown, = unchanged, = unimplemented, = value depends on condition,
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
Legend:
Note 1:
2:
x
u
-
q
r= reserved, do not modify
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘
0
’. Reset states shown are
for 80-pin devices.
3:
4:
5:
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = ); otherwise, they are disabled and these bits read as ‘ ’.
0
0
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TABLE 6-3:
PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Value on Detailson
POR, BOR page
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RTCVALL
RTCC Value Low Register Window based on RTCPTR<1:0>
xxxx xxxx 64, 160
AMASK0 ALRMPTR1 ALRMPTR0 0000 0000 64, 159
ALRMCFG
ALRMRPT
ALRMVALH
ALRMVALL
CTMUCONH
CTMUCONL
CTMUICON
PADCFG1
ALRMEN
ARPT7
CHIME
ARPT6
AMASK3
ARPT5
AMASK2
ARPT4
AMASK1
ARPT3
ARPT2
ARPT1
ARPT0
0000 0000 64, 160
xxxx xxxx 64, 163
xxxx xxxx 64, 163
0-00 0000 64, 321
Alarm Value High Register Window based on ALRMPTR<1:0>
Alarm Value Low Register Window based on ALRMPTR<1:0>
CTMUEN
—
CTMUSIDL
TGEN
EDGEN EDGSEQEN IDISSEN
CTTRIG
EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 0000 64, 322
ITRIM5
—
ITRIM4
—
ITRIM3
—
ITRIM2
—
ITRIM1
—
ITRIM0
IRNG1
IRNG0
—
0000 0000 64, 323
---- -00- 64, 158
RTSECSEL1 RTSECSEL0
Legend:
Note 1:
2:
x
= unknown,
u
= unchanged,
-
= unimplemented,
q
= value depends on condition,
r
= reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘
0’. Reset states shown are
for 80-pin devices.
3:
4:
5:
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 18.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = ); otherwise, they are disabled and these bits read as ‘ ’.
0
0
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register then reads back as ‘000u u1uu’. It is recom-
mended, therefore, that only BCF, BSF, SWAPF,
MOVFF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C, DC, OV or N bits in the STATUS
register.
6.3.5
STATUS REGISTER
The STATUS register, shown in Register 6-2, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled.
For other instructions not affecting any Status bits, see
the instruction set summaries in Table 26-2 and
Table 26-3.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUSwill set the Z bit
but leave the other bits unchanged. The STATUS
Note: The C and DC bits operate as a borrow and
digit borrow bit, respectively, in subtraction.
REGISTER 6-2:
STATUS REGISTER
U-0
—
U-0
U-0
—
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC(1)
R/W-x
C(2)
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit(1)
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
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The Access RAM bit, ‘a’, determines how the address
is interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 6.3.1 “Bank Select Register”) are used with
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘0’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
6.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 6.6 “Data Memory
and the Extended Instruction Set” for
more information.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
While the program memory can be addressed in only
one way, through the program counter, information in
the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The destination of the operation’s results is determined
by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
The addressing modes are:
• Inherent
• Literal
• Direct
6.4.3
INDIRECT ADDRESSING
• Indirect
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures, such as
tables and arrays in data memory.
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 6.6.1 “Indexed
Addressing with Literal Offset”.
6.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as Inherent
Addressing. Examples include: SLEEP, RESETand DAW.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 6-5. It also enables users to perform
Indexed Addressing and other Stack Pointer
operations for program memory in data memory.
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode, because they
require some literal value as an argument. Examples
include: ADDLWand MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
EXAMPLE 6-5:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
6.4.2
DIRECT ADDRESSING
LFSR
FSR0, 100h
;
NEXT
CLRF
POSTINC0
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
BTFSS
BRA
FSR0H, 1
NEXT
; NO, clear next
; YES, continue
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 6.3.3 “General
Purpose Register File”) or a location in the Access
Bank (Section 6.3.2 “Access Bank”) as the data
source for the instruction.
CONTINUE
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the SFR space but are not physically implemented.
Reading or writing to a particular INDF register actually
accesses its corresponding FSR register pair. A read
from INDF1, for example, reads the data at the address
indicated by FSR1H:FSR1L. Instructions that use the
INDF registers as operands actually use the contents
of their corresponding FSR as a pointer to the instruc-
tion’s target. The INDF operand is just a convenient
way of using the pointer.
6.4.3.1
FSR Registers and the
INDF Operand
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Because Indirect Addressing uses a full, 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Indirect Addressing is accomplished with a set of Indi-
rect File Operands, INDF0 through INDF2. These can
be thought of as “virtual” registers: they are mapped in
FIGURE 6-8:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
Indirect Addressing registers as the
operand....
Bank 0
Bank 1
ADDWF, INDF1, 1
100h
200h
300h
Bank 2
FSR1H:FSR1L
...uses the 12-bit address stored in
the FSR pair associated with that
register....
7
0
7
0
x x x x 1 1 1 1
1 1 0 0 1 1 0 0
Bank 3
through
Bank 13
...to determine the data memory
location to be used in that operation.
E00h
In this case, the FSR1 pair contains
FCCh. This means the contents of
location, FCCh, will be added to that
of the W register and stored back in
FCCh.
Bank 14
Bank 15
F00h
FFFh
Data Memory
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6.4.3.2
FSR Registers and POSTINC,
6.4.3.3
Operations by FSRs on FSRs
POSTDEC, PREINC and PLUSW
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that the FSR0H:FSR0L regis-
ters contain FE7h, the address of INDF1. Attempts to
read the value of INDF1, using INDF0 as an operand,
will return 00h. Attempts to write to INDF1, using INDF0
as the operand, will result in a NOP.
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L registers.
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Similarly, operations by Indirect Addressing are gener-
ally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
6.5
Program Memory and the
Extended Instruction Set
The operation of program memory is unaffected by the
use of the extended instruction set.
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 6.2.4 “Two-Word Instructions”.
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Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of FSR2
are added to obtain the target address of the operation.
6.6
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core PIC18
instructions is different; this is due to the introduction of
a new addressing mode for the data memory space.
This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
6.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions or almost
one-half of the standard PIC18 instruction set. Instruc-
tions that only use Inherent or Literal Addressing
modes are unaffected.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing modes. Inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’) or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the dif-
ferent possible addressing modes when the extended
instruction set is enabled is shown in Figure 6-9.
6.6.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 26.2.1
“Extended Instruction Syntax”.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
and
• The file address argument is less than or equal to
5Fh.
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FIGURE 6-9:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When a = 0and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations, F60h to FFFh
(Bank 15), of data memory.
060h
100h
Bank 0
00h
60h
Bank 1
through
Bank 14
Valid range
for ‘f’
Locations below 060h are not
available in this addressing
mode.
FFh
F00h
Access RAM
Bank 15
F40h
FFFh
SFRs
Data Memory
When a = 0and f5Fh:
000h
060h
100h
Bank 0
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
F40h
Note that in this mode, the
correct syntax is now:
Bank 15
ADDWF [k], d
SFRs
where ‘k’ is the same as ‘f’.
FFFh
Data Memory
BSR
000h
060h
100h
00000000
When a = 1(all values of f):
Bank 0
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
001001da ffffffff
Bank 1
through
Bank 14
F00h
F40h
Bank 15
SFRs
FFFh
Data Memory
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Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any Indirect or
Indexed Addressing operation that explicitly uses any
of the indirect file operands (including FSR2) will con-
tinue to operate as standard Indirect Addressing. Any
instruction that uses the Access Bank, but includes a
register address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
6.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 6.3.2 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 6-10.
6.6.4
BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
FIGURE 6-10:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Example Situation:
000h
ADDWF f, d, a
Not Accessible
05Fh
FSR2H:FSR2L = 120h
Bank 0
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
100h
120h
17Fh
Window
Bank 1
00h
Bank 1 “Window”
200h
5Fh
60h
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 2
through
Bank 14
SFRs
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
FFh
Access Bank
F00h
Bank 15
SFRs
F60h
FFFh
Data Memory
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NOTES:
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7.1
Table Reads and Table Writes
7.0
FLASH PROGRAM MEMORY
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
• Table Read (TBLRD)
• Table Write (TBLWT)
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time or two bytes at a time. Pro-
gram memory is erased in blocks of 1024 bytes at a
time. A bulk erase operation may not be issued from
user code.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 7-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 7.5 “Writing
to Flash Program Memory”. Figure 7-2 shows the
operation of a table write with program memory and data
RAM.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 7-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: The Table Pointer register points to a byte in program memory.
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FIGURE 7-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program Memory”.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
7.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set, and cleared
when the internal programming timer expires and the
write operation is complete.
7.2.1
EECON1 AND EECON2 REGISTERS
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
a
Reset or
a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
The WPROG bit, when set, allows the user to program
a single word (two bytes) upon the execution of the WR
command. If this bit is cleared, the WR command
programs a block of 64 bytes.
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REGISTER 7-1:
EECON1: EEPROM CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
FREE
R/W-x
WRERR(1)
R/W-0
WREN
R/S-0
WR
U-0
—
WPROG
bit 7
bit 0
Legend:
S = Settable bit (cannot be cleared in software)
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
WPROG: One Word-Wide Program bit
1= Program 2 bytes on the next WR command
0= Program 64 bytes on the next WR command
bit 4
bit 3
FREE: Flash Erase Enable bit
1= Performs an erase operation on the next WR command (cleared by completion of erase operation)
0= Perform write-only
WRERR: Flash Program Error Flag bit(1)
1= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0= The write operation completed
bit 2
bit 1
WREN: Flash Program Write Enable bit
1= Allows write cycles to Flash program memory
0= Inhibits write cycles to Flash program memory
WR: Write Control bit
1= Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.)
0= Write cycle is complete
bit 0
Unimplemented: Read as ‘0’
Note 1: When a WRERR error occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
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7.2.2
TABLE LATCH REGISTER (TABLAT)
7.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRDis executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
7.2.3
TABLE POINTER REGISTER
(TBLPTR)
When a TBLWT is executed, the seven LSbs of the
Table Pointer register (TBLPTR<6:0>) determine which
of the 64 program memory holding registers is written
to. When the timed write to program memory begins
(via the WR bit), the 12 MSbs of the TBLPTR
(TBLPTR<21:10>) determine which program memory
block of 1024 bytes is written to. For more detail, see
Section 7.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID, the user ID and the Configuration bits.
When an erase of program memory is executed, the
12 MSbs of the Table Pointer register point to the
1024-byte block that will be erased. The Least
Significant bits are ignored.
The Table Pointer register, TBLPTR, is used by the
TBLRDand TBLWTinstructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 7-1. These operations on the TBLPTR only affect
the low-order 21 bits.
Figure 7-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 7-1:
Example
TABLE POINTER OPERATIONS WITH TBLRDAND TBLWTINSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 7-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
ERASE: TBLPTR<20:10>
TABLE WRITE: TBLPTR<20:6>
TABLE READ: TBLPTR<21:0>
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TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
7.3
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 7-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 7-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
TABLAT
Read Register
FETCH
TBLRD
(IR)
EXAMPLE 7-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_EVEN
; read into TABLAT and increment
; get data
TABLAT, W
WORD_ODD
MOVWF
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7.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
7.4
Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer register with address being
erased.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased. The
TBLPTR<9:0> bits are ignored.
2. Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
6. Set the WR bit. This will begin the erase cycle.
7. The CPU will stall for the duration of the erase
for TIW (see parameter D133B).
8. Re-enable interrupts.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 7-2:
ERASING FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; enable Erase operation
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
BSF
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The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
7.5
Writing to Flash Program Memory
The programming block is 32 words or 64 bytes.
Programming one word or two bytes at a time is also
supported.
Note 1: Unlike previous PIC18 Flash devices,
members of the PIC18F87J90 family do
not reset the holding registers after a
write occurs. The holding registers must
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
be cleared or overwritten before
programming sequence.
a
Since the Table Latch (TABLAT) is only a single byte, the
TBLWTinstruction may need to be executed 64 times for
each programming operation (if WPROG = 0). All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 64 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
2: To maintain the endurance of the program
memory cells, each Flash byte should not
be programmed more than one time
between erase operations. Before
attempting to modify the contents of the
target cell a second time, an erase of the
target, or a bulk erase of the entire
memory, must be performed.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
FIGURE 7-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
TBLPTR = xxxx3F
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
8. Disable interrupts.
7.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
The sequence of events for programming an internal
program memory location should be:
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for the duration of the write for
TIW (parameter D133A).
1. Read 1024 bytes into RAM.
2. Update data values in RAM as necessary.
13. Re-enable interrupts.
3. Load Table Pointer register with the address
being erased.
14. Repeat steps 6 through 13 until all 1024 bytes
are written to program memory.
4. Execute the erase procedure.
15. Verify the memory (table read).
5. Load the Table Pointer register with the address
of the first byte being written, minus 1.
An example of the required code is shown in
Example 7-3 on the following page.
6. Write the 64 bytes into the holding registers with
auto-increment.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
7. Set the WREN bit (EECON1<2>) to enable byte
writes.
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EXAMPLE 7-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base address
; of the memory block, minus 1
ERASE_BLOCK
BSF
BSF
BCF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
; enable write to memory
; enable Erase operation
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
; write 55h
EECON2
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
EECON1, WR
INTCON, GIE
D'16'
WRITE_COUNTER
; Need to write 16 blocks of 64 to write
; one erase block of 1024
RESTART_BUFFER
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
; point to buffer
FILL_BUFFER
...
; read the new data from I2C, SPI,
; USART, etc.
WRITE_BUFFER
MOVLW
MOVWF
D’64
COUNTER
; number of bytes in holding register
WRITE_BYTE_TO_HREGS
MOVFF
MOVWF
TBLWT+*
POSTINC0, WREG
TABLAT
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
DECFSZ COUNTER
BRA WRITE_BYTE_TO_HREGS
PROGRAM_MEMORY
BSF
BCF
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
; enable write to memory
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
Required
Sequence
; write 55h
EECON2
; write 0AAh
EECON1, WR
INTCON, GIE
EECON1, WREN
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
BSF
BCF
DECFSZ WRITE_COUNTER
BRA RESTART_BUFFER
; done with one write cycle
; if not done replacing the erase block
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3. Set WPROG to enable single-word write.
4. Set WREN to enable write to memory.
5. Disable interrupts.
7.5.2
FLASH PROGRAM MEMORY WRITE
SEQUENCE (WORD
PROGRAMMING).
6. Write 55h to EECON2.
The PIC18F87J90 family of devices has a feature that
allows programming a single word (two bytes). This
feature is enabled when the WPROG bit is set. If the
memory location is already erased, the following
sequence is required to enable this feature:
7. Write 0AAh to EECON2.
8. Set the WR bit. This will begin the write cycle.
9. The CPU will stall for the duration of the write for
TIW (see parameter D133A).
1. Load the Table Pointer register with the address
of the data to be written
10. Re-enable interrupts.
2. Write the 2 bytes into the holding registers and
perform a table write
EXAMPLE 7-4:
SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base address
MOVLW
DATA0
MOVWF
TABLAT
TBLWT*+
MOVLW
DATA1
MOVWF
TABLAT
TBLWT*
PROGRAM_MEMORY
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, WPROG
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
; enable single word write
; enable write to memory
; disable interrupts
Required
Sequence
; write 55h
EECON2
; write 0AAh
EECON1, WR
INTCON, GIE
EECON1, WPROG
EECON1, WREN
; start program (CPU stall)
; re-enable interrupts
; disable single word write
; disable write to memory
BSF
BCF
BCF
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7.5.3
WRITE VERIFY
7.6
Flash Program Operation During
Code Protection
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
See Section 25.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
7.5.4
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Values on
Page:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
59
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
59
59
59
59
61
61
TABLAT
INTCON
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
WREN
INT0IF
WR
RBIF
—
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1 WPROG FREE WRERR
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access.
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EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8.0
8.1
8 x 8 HARDWARE MULTIPLIER
Introduction
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
MOVF
MULWF
ARG1, W
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
8.2
Operation
Example 8-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the argu-
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Program
Memory
(Words)
Time
Cycles
(Max)
Multiply Method
@ 48 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
5.7 s
83.3 ns
7.5 s
27.6 s
400 ns
36.4 s
2.4 s
69 s
1 s
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 s
6 s
500 ns
20.1 s
2.3 s
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 s
11.2 s
102.6 s
16.0 s
242 s
28 s
254 s
40 s
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
21.6 s
3.3 s
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Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0= ARG1H:ARG1L ARG2H:ARG2L
16
=
(ARG1H ARG2H 2 ) +
8
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
(ARG1H ARG2L 2 ) +
(ARG1L ARG2H 2 ) +
(ARG1L ARG2L) +
(-1 ARG2H<7> ARG1H:ARG1L 2 ) +
8
16
RES3:RES0
=
=
ARG1H:ARG1L ARG2H:ARG2L
16
(-1 ARG1H<7> ARG2H:ARG2L 2
)
16
(ARG1H ARG2H 2 ) +
8
(ARG1H ARG2L 2 ) +
8
(ARG1L ARG2H 2 ) +
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
(ARG1L ARG2L)
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
MOVF
MULWF
ARG1H, W
ARG2L
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
;
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
ARG1H, W
SUBWFB RES3
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS39933D-page 100
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address,
0008h, in Compatibility mode.
9.0
INTERRUPTS
Members of the PIC18F87J90 family of devices have
multiple interrupt sources and an interrupt priority
feature that allows most interrupt sources to be
assigned a high-priority level or a low-priority level. The
high-priority interrupt vector is at 0008h and the
low-priority interrupt vector is at 0018h. High-priority
interrupt events will interrupt any low-priority interrupts
that may be in progress.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
There are thirteen registers which are used to control
interrupt operation. These registers are:
• RCON
High-priority interrupt sources can interrupt
a
• INTCON
low-priority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
• INTCON2
• INTCON3
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files,
supplied with MPLAB® IDE, be used for the symbolic bit
names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
In general, interrupt sources have three bits to control
their operation. They are:
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Note:
Do not use the MOVFFinstruction to modify
any of the Interrupt Control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address, 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
2010 Microchip Technology Inc.
DS39933D-page 101
PIC18F87J90 FAMILY
FIGURE 9-1:
PIC18F87J90 FAMILY INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
Interrupt to CPU
Vector to Location
0008h
PIR1<6:3,1:0>
PIE1<6:3,1:0>
IPR1<6:3,1:0>
GIE/GIEH
PIR2<7:6,3:1>
PIE2<7:6 3:1>
IPR2<7:6,3:1>
IPEN
PIR3<6:0>
PIE3<6:0>
IPR3<6:0>
IPEN
PEIE/GIEL
IPEN
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PIR1<6:3,1:0>
PIE1<6:3,1:0>
IPR1<6:3,1:0>
PIR2<7:6,3:1>
PIE2<7:6,3:1>
IPR2<7:6,3:1>
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
IPEN
PIR3<6:0>
PIE3<6:0>
IPR3<6:0>
RBIF
RBIE
RBIP
GIE/GIEH
PEIE/GIEL
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
DS39933D-page 102
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
9.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 9-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
PEIE/GIEL
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF(1)
GIE/GIEH
bit 7
TMR0IE
INT0IE
TMR0IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high-priority interrupts
0= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low-priority peripheral interrupts
0= Disables all low-priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit(1)
1= At least one of the RB<7:4> pins changed state (must be cleared in software)
0= None of the RB<7:4> pins have changed state
Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction
cycle, will end the mismatch condition and allow the bit to be cleared.
2010 Microchip Technology Inc.
DS39933D-page 103
PIC18F87J90 FAMILY
REGISTER 9-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-1
INTEDG0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBIP
RBPU
bit 7
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG3: External Interrupt 3 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
INT3IP: INT3 External Interrupt Priority bit
1= High priority
0= Low priority
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
DS39933D-page 104
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 9-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
INT2IP
bit 7
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
INT3IF
R/W-0
INT2IF
R/W-0
INT1IF
INT1IP
INT3IE
INT2IE
INT1IE
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
INT3IE: INT3 External Interrupt Enable bit
1= Enables the INT3 external interrupt
0= Disables the INT3 external interrupt
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
INT3IF: INT3 External Interrupt Flag bit
1= The INT3 external interrupt occurred (must be cleared in software)
0= The INT3 external interrupt did not occur
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
2010 Microchip Technology Inc.
DS39933D-page 105
PIC18F87J90 FAMILY
9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
U-0
—
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
U-0
—
R/W-0
R/W-0
RC1IF
TX1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
bit 5
bit 4
bit 3
RC1IF: EUSART Receive Interrupt Flag bit
1= The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0= The EUSART receive buffer is empty
TX1IF: EUSART Transmit Interrupt Flag bit
1= The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0= The EUSART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
DS39933D-page 106
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
bit 7
R/W-0
CMIF
U-0
—
U-0
—
R/W-0
BCLIF
R/W-0
LVDIF
R/W-0
U-0
—
TMR3IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIF: Oscillator Fail Interrupt Flag bit
1= Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= Device clock operating
CMIF: Comparator Interrupt Flag bit
1= Comparator input has changed (must be cleared in software)
0= Comparator input has not changed
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
bit 2
bit 1
bit 0
LVDIF: Low-Voltage Detect Interrupt Flag bit
1= A low-voltage condition occurred (must be cleared in software)
0= The device voltage is above the regulator’s low-voltage trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
Unimplemented: Read as ‘0’
2010 Microchip Technology Inc.
DS39933D-page 107
PIC18F87J90 FAMILY
REGISTER 9-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
U-0
—
R/W-0
LCDIF
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
RTCCIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
LCDIF: LCD Interrupt Flag bit (valid when Type-B waveform with Non-Static mode is selected)
1= LCD data of all COMs is output (must be cleared in software)
0= LCD data of all COMs is not yet output
bit 5
bit 4
bit 3
bit 2
RC2IF: AUSART Receive Interrupt Flag bit
1= The AUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0= The AUSART receive buffer is empty
TX2IF: AUSART Transmit Interrupt Flag bit
1= The AUSART transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0= The AUSART transmit buffer is full
CTMUIF: CTMU Interrupt Flag bit
1= CTMU interrupt occured (must be cleared in software)
0= No CTMU interrupt occured
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 0
RTCCIF: RTCC Interrupt Flag bit
1= RTCC interrupt occured (must be cleared in software)
0= No RTCC interrupt occured
DS39933D-page 108
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0
—
R/W-0
ADIE
R/W-0
RC1IE
R/W-0
TX1IE
R/W-0
SSPIE
U-0
—
R/W-0
R/W-0
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
bit 5
bit 4
bit 3
RC1IE: EUSART Receive Interrupt Enable bit
1= Enables the EUSART receive interrupt
0= Disables the EUSART receive interrupt
TX1IE: EUSART Transmit Interrupt Enable bit
1= Enables the EUSART transmit interrupt
0= Disables the EUSART transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
2010 Microchip Technology Inc.
DS39933D-page 109
PIC18F87J90 FAMILY
REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSCFIE
bit 7
R/W-0
CMIE
U-0
—
U-0
—
R/W-0
BCLIE
R/W-0
LVDIE
R/W-0
U-0
—
TMR3IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
CMIE: Comparator Interrupt Enable bit
1= Enabled
0= Disabled
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCLIE: Bus Collision Interrupt Enable bit
1= Enabled
0= Disabled
bit 2
bit 1
bit 0
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enabled
0= Disabled
Unimplemented: Read as ‘0’
DS39933D-page 110
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
—
R/W-0
LCDIE
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
RTCCIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
LCDIE: LCD Interrupt Enable bit (valid when Type-B waveform with Non-Static mode is selected)
1= Enabled
0= Disabled
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RC2IE: AUSART Receive Interrupt Enable bit
1= Enabled
0= Disabled
TX2IE: AUSART Transmit Interrupt Enable bit
1= Enabled
0= Disabled
CTMUIE: CTMU Interrupt Enable bit
1= Enabled
0= Disabled
CCP2IE: CCP2 Interrupt Enable bit
1= Enabled
0= Disabled
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
RTCCIE: RTCC Interrupt Enable bit
1= Enabled
0= Disabled
2010 Microchip Technology Inc.
DS39933D-page 111
PIC18F87J90 FAMILY
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0
—
R/W-1
ADIP
R/W-1
RC1IP
R/W-1
TX1IP
R/W-1
SSPIP
U-0
—
R/W-1
R/W-1
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
RC1IP: EUSART Receive Interrupt Priority bit
1= High priority
0= Low priority
TX1IP: EUSART Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
DS39933D-page 112
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
CMIP
U-0
—
U-0
—
R/W-1
BCLIP
R/W-1
LVDIP
R/W-1
U-0
—
OSCFIP
TMR3IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
CMIP: Comparator Interrupt Priority bit
1= High priority
0= Low priority
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
bit 2
bit 1
bit 0
LVDIP: Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Unimplemented: Read as ‘0’
2010 Microchip Technology Inc.
DS39933D-page 113
PIC18F87J90 FAMILY
REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
—
R/W-1
LCDIP
R-1
R-1
R/W-1
R/W-1
R/W-1
R/W-1
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
RTCCIP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
LCDIP: LCD Interrupt Priority bit (valid when Type-B waveform with Non-Static mode is selected)
1= High priority
0= Low priority
bit 5
bit 4
bit 3
bit
RC2IP: AUSART Receive Priority Flag bit
1= High priority
0= Low priority
TX2IP: AUSART Transmit Interrupt Priority bit
1= High priority
0= Low priority
CTMUIP: CTMU Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
bit
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
bit 0
RTCCIP: RTCC Interrupt Priority bit
1= High priority
0= Low priority
DS39933D-page 114
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
9.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-13: RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
R/W-1
CM
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
bit 5
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
1= A Configuration Mismatch Reset has not occurred
0= A Configuration Mismatch Reset has occurred (must be subsequently set in software)
bit 4
bit 3
bit 2
bit 1
bit 0
RI: RESETInstruction Flag bit
For details of bit operation, see Register 5-1.
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 5-1.
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 5-1.
POR: Power-on Reset Status bit
For details of bit operation, see Register 5-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 5-1.
2010 Microchip Technology Inc.
DS39933D-page 115
PIC18F87J90 FAMILY
9.6
INTx Pin Interrupts
9.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh 0000h) will set TMR0IF. The interrupt can
be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt priority
bit, TMR0IP (INTCON2<2>). See Section 11.0 “Timer0
Module” for further details on the Timer0 module.
9.8
PORTB Interrupt-on-Change
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit, INTxIE, was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit, GIE, is set, the processor will branch to the interrupt
vector following wake-up.
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the Interrupt Priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high-priority
interrupt source.
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 6.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine (ISR). Depending on
the user’s application, other registers may also need to
be saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
DS39933D-page 116
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
10.1 I/O Port Pin Capabilities
10.0 I/O PORTS
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
10.1.1
INPUT PINS AND VOLTAGE
CONSIDERATIONS
Each port has three memory mapped registers for its
operation:
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to VDD. Voltage excursions
beyond VDD on these pins should be avoided.
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register writes to
the Output Latch (LAT) register.
Table 10-1 summarizes the input voltage capabilities.
Refer to Section 28.0 “Electrical Characteristics” for
more details.
Setting a TRIS bit (= 1) makes the corresponding port
pin an input (i.e., puts the corresponding output driver
in a high-impedance mode). Clearing a TRIS bit (= 0)
makes the corresponding port pin an output (i.e., puts
the contents of the corresponding LAT bit on the
selected pin).
TABLE 10-1: INPUT VOLTAGE TOLERANCE
Tolerated
PORT or Pin
Description
Input
PORTA<7:0>
PORTC<1:0>
PORTF<7:1>
PORTG<3:2>
PORTB<7:0>
PORTC<7:2>
PORTD<7:0>
PORTE<7:3>
PORTG<4,1>
PORTH<7:0>(1)
PORTJ<7:0>(1)
Only VDD input levels
tolerated.
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
VDD
Tolerates input
levels above VDD,
useful for most
standard logic.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
5.5V
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
RD LAT
Note 1: Not available on PIC18F6XJ90 devices.
Data
Bus
D
Q
10.1.2 PIN OUTPUT DRIVE
I/O pin
WR LAT
or PORT
CKx
When used as digital I/O, the output pin drive strengths
vary for groups of pins intended to meet the needs for
a variety of applications. In general, there are three
classes of output pins in terms of drive capability.
Data Latch
D
Q
PORTB and PORTC, as well as PORTA<7:6>, are
designed to drive higher current loads, such as LEDs.
PORTD, PORTE and PORTJ can also drive LEDs but
only those with smaller current requirements. PORTF,
PORTG and PORTH, along with PORTA<5:0>, have
the lowest drive level but are capable of driving normal
digital circuit loads with a high input impedance.
Regardless of which port it is located on, all output pins
in LCD Segment or Common mode have sufficient
output to directly drive a display.
WR TRIS
RD TRIS
CKx
TRIS Latch
Input
Buffer
Q
D
EN
RD PORT
Table 10-2 summarizes the output capabilities of the
ports. Refer to the “Absolute Maximum Ratings” in
Section 28.0 “Electrical Characteristics” for more
details.
2010 Microchip Technology Inc.
DS39933D-page 117
PIC18F87J90 FAMILY
TABLE 10-2: OUTPUT DRIVE LEVELS FOR
VARIOUS PORTS
10.2 PORTA, TRISA and
LATA Registers
Low
Medium
PORTD
High
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISA and LATA.
PORTA<5:0>
PORTF
PORTA<7:6>
PORTB
PORTE
RA4/T0CKI is a Schmitt Trigger input. All other PORTA
pins have TTL input levels and full CMOS output
drivers.
PORTG
PORTH(1)
PORTJ(1)
PORTC
Note 1: Not available on PIC18F6XJ90 devices.
The RA4 pin is multiplexed with the Timer0 clock input
and one of the LCD segment drives. RA5 and RA<3:0>
are multiplexed with analog inputs for the A/D
Converter.
10.1.3 PULL-UP CONFIGURATION
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level
without the use of external resistors.
The operation of the analog inputs as A/D Converter
inputs is selected by clearing or setting the PCFG<3:0>
control bits in the ADCON1 register. The corresponding
TRISA bits control the direction of these pins, even
when they are being used as analog inputs. The user
must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2<7>) for PORTB, and RDPU,
REPU and PJPU (PORTG<7:5>) for the other ports.
Note:
RA5 and RA<3:0> are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
10.1.4
OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally
serve as the external circuit connections for the exter-
nal (primary) oscillator circuit (HS Oscillator modes), or
the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O and their corresponding TRIS and LAT
bits are read as ‘0’. When the device is configured to
use INTOSC or INTRC as the default oscillator mode
(FOSC2 Configuration bit is ‘0’), RA6 and RA7 are
automatically configured as digital I/O. The oscillator
and clock in/clock out functions are disabled.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. This option is selectively enabled by
setting the open-drain control bit for the corresponding
module in TRISG and LATG. Their configuration is dis-
cussed in more detail in Section 10.4 “PORTC, TRISC
and LATC Registers”, Section 10.6 “PORTE, TRISE
and LATE Registers” and Section 10.8 “PORTG,
TRISG and LATG Registers”.
RA1, RA4 and RA5 are multiplexed with LCD segment
drives, controlled by bits in the LCDSE1 and LCDSE2
registers. I/O port functionality is only available when
the LCD segments are disabled.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor,
provided by the user to a higher voltage level, up to 5V
(Figure 10-2). When a digital logic high signal is output,
it is pulled up to the higher voltage level.
EXAMPLE 10-1:
INITIALIZING PORTA
CLRF
PORTA
LATA
07h
; Initialize PORTA by
; clearing output latches
; Alternate method to
; clear output data latches
; Configure A/D
CLRF
FIGURE 10-2:
USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
MOVLW
MOVWF
MOVLW
ADCON1 ; for digital inputs
0BFh
; Value used to initialize
; data direction
3.3V
+5V
MOVWF
TRISA
; Set RA<7, 5:0> as inputs,
; RA<6> as output
PIC18F87J90
3.3V
VDD
TXX
5V
(at logic ‘1’)
DS39933D-page 118
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 10-3:
Pin Name
PORTA FUNCTIONS
TRIS
I/O
Type
Function
I/O
Description
Setting
RA0/AN0
RA0
0
1
1
O
I
DIG
TTL
ANA
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
AN0
RA1
I
A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
RA1/AN1/SEG18
0
1
1
O
I
DIG
TTL
ANA
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
AN1
I
A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
SEG18
RA2
x
0
1
1
1
0
1
1
1
0
1
x
x
0
1
1
x
x
x
0
1
x
x
0
1
O
O
I
ANA
DIG
TTL
ANA
ANA
DIG
TTL
ANA
ANA
DIG
ST
LCD Segment 18 output; disables all other pin functions.
LATA<2> data output; not affected by analog input.
PORTA<2> data input; disabled when analog functions enabled.
A/D Input Channel 2. Default input configuration on POR.
A/D and comparator low reference voltage input.
RA2/AN2/VREF-
RA3/AN3/VREF+
AN2
VREF-
RA3
I
I
O
I
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D Input Channel 3. Default input configuration on POR.
A/D and comparator high reference voltage input.
AN3
VREF+
RA4
I
I
RA4/T0CKI/
SEG14
O
I
LATA<4> data output.
PORTA<4> data input. Default configuration on POR.
Timer0 clock input.
T0CKI
SEG14
RA5
I
ST
O
O
I
ANA
DIG
TTL
ANA
ANA
ANA
DIG
DIG
TTL
ANA
ANA
DIG
TTL
LCD Segment 14 output; disables all other pin functions.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D Input Channel 4. Default configuration on POR.
LCD Segment 15 output; disables all other pin functions.
Main oscillator feedback output connection (HS and HSPLL modes).
System cycle clock output (FOSC/4) (EC and ECPLL modes).
LATA<6> data output; disabled when FOSC2 Configuration bit is set.
PORTA<6> data input; disabled when FOSC2 Configuration bit is set.
Main oscillator input connection (HS and HSPLL modes).
Main external clock source input (EC and ECPLL modes).
LATA<7> data output; disabled when FOSC2 Configuration bit is set.
PORTA<7> data input; disabled when FOSC2 Configuration bit is set.
RA5/AN4/SEG15
OSC2/CLKO/RA6
OSC1/CLKI/RA7
AN4
SEG15
OSC2
CLKO
RA6
I
O
O
O
O
I
OSC1
CLKI
RA7
I
I
O
I
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
PORTA
LATA
RA7
RA6
RA5
LATA5
TRISA5
VCFG1
SE13
RA4
LATA4
TRISA4
VCFG0
SE12
RA3
LATA3
TRISA3
PCFG3
SE11
RA2
LATA2
TRISA2
PCFG2
SE10
RA1
LATA1
TRISA1
PCFG1
SE09
RA0
LATA0
TRISA0
PCFG0
SE08
63
62
62
61
61
61
(1)
(1)
LATA7
LATA6
(1)
(1)
TRISA
TRISA7
TRISA6
—
ADCON1
LCDSE1
LCDSE2
Legend:
TRIGSEL
SE15
SE14
SE22
SE23
SE21
SE20
SE19
SE18
SE17
SE16
— = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are
disabled and read as ‘x’.
2010 Microchip Technology Inc.
DS39933D-page 119
PIC18F87J90 FAMILY
Four of the PORTB pins (RB<7:4>) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB<7:4> pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB<7:4>) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB<7:4> are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
10.3 PORTB, TRISB and
LATB Registers
PORTB is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISB and LATB. All pins on PORTB are digital only
and tolerate voltages up to 5.5V.
EXAMPLE 10-2:
INITIALIZING PORTB
This interrupt can wake the device from
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
CLRF
LATB
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTBinstruction). This will end
the mismatch condition.
MOVLW
MOVWF
0CFh
b) Wait one instruction cycle (such as executing a
TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
NOPinstruction).
c) Clear flag bit, RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after one TCY delay.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB<3:2> are multiplexed as CTMU edge inputs.
RB<5:0> are also multiplexed with LCD segment
drives, controlled by bits in the LCDSE1 and LCDSE3
registers. I/O port functionality is only available when
the LCD segments are disabled.
DS39933D-page 120
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 10-5: PORTB FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RB0/INT0/SEG30
RB0
0
1
1
x
0
1
1
x
0
1
1
x
x
0
1
1
x
x
0
1
1
x
0
1
1
x
0
1
1
x
0
1
1
x
x
O
I
DIG
TTL
ST
LATB<0> data output.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 0 input.
INT0
SEG30
RB1
I
O
O
I
ANA
DIG
TTL
ST
LCD Segment 30 output; disables all other pin functions.
LATB<1> data output.
RB1/INT1/SEG8
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 1 input.
INT1
SEG8
RB2
I
O
O
I
ANA
DIG
TTL
ST
LCD Segment 8 output; disables all other pin functions.
LATB<2> data output.
RB2/INT2/SEG9/
CTED1
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 2 input.
INT2
SEG9
CTED1
RB3
I
O
I
ANA
ST
LCD Segment 9 output; disables all other pin functions.
CTMU Edge 1 input.
RB3/INT3/SEG10/
CTED2
O
I
DIG
TTL
ST
LATB<3> data output.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 3 input.
INT3
SEG10
CTED2
RB4
I
O
I
ANA
ST
LCD Segment 10 output; disables all other pin functions.
CTMU Edge 2 input.
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
RB7/KBI3/PGD
O
I
DIG
TTL
TTL
ANA
DIG
TTL
TTL
ANA
DIG
TTL
TTL
ST
LATB<4> data output.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
KBI0
SEG11
RB5
I
O
O
I
LCD Segment 11 output; disables all other pin functions.
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
KBI1
SEG29
RB6
I
O
O
I
LCD Segment 29 output; disables all other pin functions.
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
KBI2
PGC
RB7
I
I
Serial execution (ICSP™) clock input for ICSP and ICD operation.
LATB<7> data output.
O
I
DIG
TTL
TTL
DIG
ST
PORTB<7> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
KBI3
PGD
I
O
I
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2010 Microchip Technology Inc.
DS39933D-page 121
PIC18F87J90 FAMILY
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
Valueson
page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
LATB
RB7
RB6
RB5
RB4
RB3
LATB3
TRISB3
RBIE
RB2
RB1
LATB1
TRISB1
INT0IF
INT3IP
INT2IF
SE09
RB0
LATB0
TRISB0
RBIF
63
62
62
59
59
59
61
61
LATB7
TRISB7
LATB6
TRISB6
LATB5
TRISB5
LATB4
TRISB4
INT0IE
LATB2
TRISB2
TMR0IF
TRISB
INTCON
INTCON2
INTCON3
LCDSE1
LCDSE3
GIE/GIEH PEIE/GIEL TMR0IE
RBPU
INT2IP
SE15
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
RBIP
INT1IP
SE14
SE30
INT3IE
SE13
SE29
INT2IE
SE12
SE28
INT1IE
SE11
INT3IF
SE10
SE26
INT1IF
SE08
SE31
SE27
SE25
SE24
Legend: Shaded cells are not used by PORTB.
DS39933D-page 122
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
10.4 PORTC, TRISC and
LATC Registers
PORTC is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISC and LATC. Only PORTC pins, RC2 through
RC7, are digital only pins and can tolerate input voltages
up to 5.5V.
RC<7:1> pins are multiplexed with LCD segment
drives, controlled by bits in the LCDSE1, LCDSE2,
LCDSE3 and LCDSE4 registers. I/O port functionality
is only available when the LCD segments are disabled.
PORTC is multiplexed with CCP, MSSP and EUSART
peripheral functions (Table 10-7). The pins have
Schmitt Trigger input buffers. The pins for CCP, SPI
and EUSART are also configurable for open-drain out-
put whenever these functions are active. Open-drain
configuration is selected by setting the SPIOD,
CCPxOD and U1OD control bits (TRISG<7:5> and
LATG<6>, respectively).
EXAMPLE 10-3:
INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
LATC
MOVLW
MOVWF
0CFh
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
RC1 is normally configured as the default peripheral
pin for the CCP2 module. Assignment of CCP2 is
controlled by Configuration bit, CCP2MX (default state,
CCP2MX = 1).
TRISC
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
Note:
These pins are configured as digital inputs
on any device Reset.
2010 Microchip Technology Inc.
DS39933D-page 123
PIC18F87J90 FAMILY
TABLE 10-7: PORTC FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RC0/T1OSO/
T13CKI
RC0
0
1
x
O
I
DIG LATC<0> data output.
ST
PORTC<0> data input.
T1OSO
O
ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables
digital I/O and LCD segment driver.
T13CKI
RC1
1
0
1
x
0
1
x
0
1
0
1
x
0
1
0
1
0
1
x
0
1
I
O
I
ST
DIG LATC<1> data output.
ST PORTC<1> data input.
Timer1/Timer3 counter input.
RC1/T1OSI/
CCP2/SEG32
T1OSI
I
ANA Timer1 oscillator input.
(1)
CCP2
O
I
DIG CCP2 compare/PWM output.
ST
CCP2 capture input.
SEG32
RC2
O
O
I
ANA LCD Segment 32 output; disables all other pin functions.
DIG LATC<2> data output.
RC2/CCP1/
SEG13
ST
DIG CCP1 compare/PWM output; takes priority over port data.
ST CCP1 capture input.
PORTC<2> data input.
CCP1
O
I
SEG13
RC3
O
O
I
ANA LCD Segment 13 output; disables all other pin functions.
DIG LATC<3> data output.
RC3/SCK/SCL/
SEG17
ST
PORTC<3> data input.
SCK
SCL
O
I
DIG SPI clock output (MSSP module); takes priority over port data.
ST
SPI clock input (MSSP module).
2
O
I
DIG I C™ clock output (MSSP module); takes priority over port data.
2
I2C I C clock input (MSSP module); input type depends on module setting.
SEG17
RC4
O
O
I
ANA LCD Segment 17 output; disables all other pin functions.
DIG LATC<4> data output.
RC4/SDI/SDA/
SEG16
ST
ST
PORTC<4> data input.
SDI
I
SPI data input (MSSP module).
2
SDA
1
1
x
0
1
0
x
0
1
1
1
1
x
0
1
1
1
1
x
O
I
DIG I C data output (MSSP module); takes priority over port data.
2
I2C I C data input (MSSP module); input type depends on module setting.
SEG16
RC5
O
O
I
ANA LCD Segment 16 output; disables all other pin functions.
DIG LATC<5> data output.
RC5/SDO/
SEG12
ST
PORTC<5> data input.
SDO
SEG12
RC6
O
O
O
I
DIG SPI data output (MSSP module).
ANA LCD Segment 12 output; disables all other pin functions.
DIG LATC<6> data output.
RC6/TX1/CK1/
SEG27
ST
PORTC<6> data input.
TX1
CK1
O
O
I
DIG Synchronous serial data output (EUSART module); takes priority over port data.
DIG Synchronous serial data input (EUSART module); user must configure as an input.
ST
Synchronous serial clock input (EUSART module).
SEG27
RC7
O
O
I
ANA LCD Segment 27 output; disables all other pin functions.
DIG LATC<7> data output.
RC7/RX1/DT1/
SEG28
ST
ST
PORTC<7> data input.
RX1
DT1
I
Asynchronous serial receive data input (EUSART module).
O
I
DIG Synchronous serial data output (EUSART module); takes priority over port data.
ST Synchronous serial data input (EUSART module); user must configure as an input.
ANA LCD Segment 28 output; disables all other pin functions.
SEG28
O
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input,
I2C = I C/SMBus Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2
Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set.
DS39933D-page 124
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
63
62
62
62
62
61
61
61
61
LATC
LATC7
LATBC6
LATC5
LATCB4
LATC3
LATC2
LATC1
LATC0
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
U2OD U1OD LATG4 LATG3 LATG2 LATG1 LATG0
SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
LATG
—
TRISG
LCDSE1
LCDSE2
LCDSE3
LCDSE4
SE15
SE23
SE14
SE22
SE13
SE21
SE12
SE20
SE11
SE19
SE10
SE18
SE09
SE17
SE08
SE16
SE24
SE32
SE31
SE39(1)
SE30
SE38(1)
SE29
SE37(1)
SE28
SE36(1)
SE27
SE35(1)
SE26
SE34(1)
SE25
SE33(1)
Legend: Shaded cells are not used by PORTC.
Note 1: Unimplemented on PIC18F6XJ90 devices, read as ‘0’.
2010 Microchip Technology Inc.
DS39933D-page 125
PIC18F87J90 FAMILY
All of the PORTD pins are multiplexed with LCD
segment drives, controlled by bits in the LCDSE0
register. RD0 is multiplexed with the CTMU pulse
generator output.
10.5 PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISD and LATD. All pins on PORTD are digital only
and tolerate voltages up to 5.5V.
I/O port functionality is only available when the LCD
segments are disabled.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
EXAMPLE 10-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
Note:
These pins are configured as digital inputs
on any device Reset.
CLRF
LATD
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, RDPU (PORTG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
MOVLW
MOVWF
0CFh
TRISD
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
DS39933D-page 126
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 10-9: PORTD FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RD0/SEG0/
CTPLS
RD0
0
1
x
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
O
I
DIG
ST
LATD<0> data output.
PORTD<0> data input.
SEG0
CTPLS
RD1
O
O
O
I
ANA
DIG
DIG
ST
LCD Segment 0 output; disables all other pin functions.
CTMU pulse generator output
RD1/SEG1
RD2/SEG2
RD3/SEG3
RD4/SEG4
RD5/SEG5
RD6/SEG6
RD7/SEG7
LATD<1> data output.
PORTD<1> data input.
SEG1
RD2
O
O
I
ANA
DIG
ST
LCD Segment 1 output; disables all other pin functions.
LATD<2> data output.
PORTD<2> data input.
SEG2
RD3
O
O
I
ANA
DIG
ST
LCD Segment 2 output; disables all other pin functions.
LATD<3> data output.
PORTD<3> data input.
SEG3
RD4
O
O
I
ANA
DIG
ST
LCD Segment 3 output; disables all other pin functions.
LATD<4> data output.
PORTD<4> data input.
SEG4
RD5
O
O
I
ANA
DIG
ST
LCD Segment 4 output; disables all other pin functions.
LATD<5> data output.
PORTD<5> data input.
SEG5
RD6
O
O
I
ANA
DIG
ST
LCD Segment 5 output; disables all other pin functions.
LATD<6> data output.
PORTD<6> data input.
SEG6
RD7
O
O
I
ANA
DIG
ST
LCD Segment 6 output; disables all other pin functions.
LATD<7> data output.
PORTD<7> data input.
SEG7
I
ANA
LCD Segment 7 output; disables all other pin functions.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
LATD7
TRISD7
RDPU
SE07
RD6
LATD6
TRISD6
REPU
SE06
RD5
RD4
LATD4
TRISD4
RG4
RD3
LATD3
TRISD3
RG3
RD2
LATD2
TRISD2
RG2
RD1
LATD1
TRISD1
RG1
RD0
LATD0
TRISD0
RG0
63
62
62
62
61
LATD5
TRISD5
RJPU(1)
SE05
TRISD
PORTG
LCDSE0
SE04
SE03
SE02
SE01
SE00
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on PIC18F6XJ90 devices, read as ‘0’.
2010 Microchip Technology Inc.
DS39933D-page 127
PIC18F87J90 FAMILY
Pins, RE1 and RE0, are multiplexed with the functions
of LCDBIAS2 and LCDBIAS1. When LCD bias genera-
tion is required (i.e., any application where the device
is connected to an external LCD), these pins cannot be
used as digital I/O.
10.6 PORTE, TRISE and
LATE Registers
PORTE is
a 7-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISE and LATE. All pins on PORTE are digital only
and tolerate voltages up to 5.5V.
Note: The pin corresponding to RE2 of other
PIC18F parts has the function of
LCDBIAS3 in this device. It cannot be used
as digital I/O.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output. The RE7 pin is also
configurable for open-drain output when CCP2 is active
on this pin. Open-drain configuration is selected by
setting the CCP2OD control bit (TRISG<6>)
RE7 is multiplexed with the LCD segment drive
(SEG31) controlled by the LCDSE3<7> bit. I/O port
function is only available when the segment is disabled.
RE7 can also be configured as the alternate peripheral
pin for the CCP2 module. This is done by clearing the
CCP2MX Configuration bit.
Note:
These pins are configured as digital inputs
on any device Reset.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PORTG<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
EXAMPLE 10-5:
INITIALIZING PORTE
CLRF
PORTE
LATE
03h
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
CLRF
Pins, RE<6:3>, are multiplexed with the LCD common
drives. I/O port functions are only available on those
PORTE pins depending on which commons are active.
The configuration is determined by the LMUX<1:0>
control bits (LCDCON<1:0>). The availability is
summarized in Table 10-11.
MOVLW
MOVWF
TRISE
; Set RE<1:0> as inputs
; RE<7:2> as outputs
TABLE 10-11: PORTE PINS AVAILABLE IN
DIFFERENT LCD DRIVE
CONFIGURATIONS
LCDCON
<1:0>
Active LCD
Commons
PORTE Available
for I/O
00
01
10
COM0
RE6, RE5, RE4
RE6, RE5
RE6
COM0, COM1
COM0, COM1
and COM2
11
All (COM0
None
through COM3)
DS39933D-page 128
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 10-12: PORTE FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RE0/LCDBIAS1
RE0
0
1
—
0
1
—
0
1
x
0
1
x
0
1
x
0
1
x
0
1
0
1
x
O
I
DIG
ST
LATE<0> data output.
PORTE<0> data input.
LCDBIAS1
RE1
I
ANA
DIG
ST
LCD module bias voltage input.
LATE<1> data output.
RE1/LCDBIAS2
RE3/COM0
RE4/COM1
RE5/COM2
RE6/COM3
O
I
PORTE<1> data input.
LCDBIAS2
RE3
I
ANA
DIG
ST
LCD module bias voltage input.
LATE<3> data output.
O
I
PORTE<3> data input.
COM0
RE4
O
O
I
ANA
DIG
ST
LCD Common 0 output; disables all other outputs.
LATE<4> data output.
PORTE<4> data input.
COM1
RE5
O
O
I
ANA
DIG
ST
LCD Common 1 output; disables all other outputs.
LATE<5> data output.
PORTE<5> data input.
COM2
RE6
O
O
I
ANA
DIG
ST
LCD Common 2 output; disables all other outputs.
LATE<6> data output.
PORTE<6> data input.
COM3
RE7
O
O
I
ANA
DIG
ST
LCD Common 3 output; disables all other outputs.
LATE<7> data output.
RE7/CCP2/
SEG31
PORTE<7> data input.
(1)
CCP2
O
I
DIG
ST
CCP2 compare/PWM output; takes priority over port data.
CCP2 capture input.
SEG31
O
ANA
Segment 31 analog output for LCD; disables digital output.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
TABLE 10-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTE
LATE
RE7
RE6
RE5
RE4
LATE4
TRISE4
RG4
RE3
LATE3
TRISE3
RG3
—
—
RE1
LATE1
TRISE1
RG1
RE0
LATE0
TRISE0
RG0
63
62
62
62
62
61
61
LATE7
TRISE7
RDPU
SPIOD
LCDEN
SE31
LATE6
TRISE6
REPU
LATE5
TRISE5
RJPU(1)
TRISE
—
PORTG
TRISG
LCDCON
LCDSE3
RG2
TRISG2
CS0
SE26
CCP2OD CCP1OD TRISG4
TRISG3
CS1
TRISG1
LMUX1
SE25
TRISG0
LMUX0
SE24
SLPEN
SE30
WERR
SE29
—
SE28
SE27
Legend: Shaded cells are not used by PORTE.
Note 1: Unimplemented on PIC18F6XJ90 devices, read as ‘0’.
2010 Microchip Technology Inc.
DS39933D-page 129
PIC18F87J90 FAMILY
PORTF is also multiplexed with LCD segment drives
controlled by bits in the LCDSE2 and LCDSE3
registers. I/O port functions are only available when the
segments are disabled.
10.7 PORTF, LATF and TRISF Registers
PORTF is
a 7-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISF and LATF. All pins on PORTF are
implemented with Schmitt Trigger input buffers. Each pin
is individually configurable as an input or output.
EXAMPLE 10-6:
INITIALIZING PORTF
CLRF
PORTF
; Initialize PORTF by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
;
PORTF is multiplexed with analog peripheral functions,
as well as LCD segments. Pins, RF1 through RF6, may
be used as comparator inputs or outputs by setting the
appropriate bits in the CMCON register. To use
RF<6:3> as digital inputs, it is also necessary to turn off
the comparators.
CLRF
LATF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
07h
CMCON
0Fh
; Turn off comparators
;
Note 1: On device Resets, pins, RF<6:1>, are
configured as analog inputs and are read
as ‘0’.
ADCON1 ; Set PORTF as digital I/O
0CEh
; Value used to
; initialize data
; direction
2: To configure PORTF as digital I/O, turn off
the comparators and set the ADCON1
value.
MOVWF
TRISF
; Set RF3:RF1 as inputs
; RF5:RF4 as outputs
; RF7:RF6 as inputs
DS39933D-page 130
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 10-14: PORTF FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RF1/AN6/C2OUT/
SEG19
RF1
0
1
1
0
x
0
1
1
0
x
0
1
1
O
I
DIG
ST
LATF<1> data output; not affected by analog input.
PORTF<1> data input; disabled when analog input is enabled.
A/D Input Channel 6. Default configuration on POR.
Comparator 2 output; takes priority over port data.
LCD Segment 19 output; disables all other pin functions.
LATF<2> data output; not affected by analog input.
PORTF<2> data input; disabled when analog input is enabled.
A/D Input Channel 7. Default configuration on POR.
Comparator 1 output; takes priority over port data.
LCD Segment 20 output; disables all other pin functions.
LATF<3> data output; not affected by analog input.
PORTF<3> data input; disabled when analog input is enabled.
AN6
C2OUT
SEG19
RF2
I
ANA
DIG
ANA
DIG
ST
O
O
O
I
RF2/AN7/C1OUT/
SEG20
AN7
C1OUT
SEG20
RF3
I
ANA
DIG
ANA
DIG
ST
O
O
O
I
RF3/AN8/SEG21/
C2INB
AN8
I
ANA
A/D Input Channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
SEG21
C2INB
RF4
x
1
0
1
1
O
I
ANA
ANA
DIG
ST
LCD Segment 21 output; disables all other pin functions.
Comparator 2 Input B.
RF4/AN9/SEG22/
C2INA
O
I
LATF<4> data output; not affected by analog input.
PORTF<4> data input; disabled when analog input is enabled.
AN9
I
ANA
A/D Input Channel 9 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
SEG22
C2INA
RF5
x
1
0
O
I
ANA
ANA
DIG
LCD Segment 22 output; disables all other pin functions.
Comparator 2 Input A.
RF5/AN10/CVREF/
SEG23/C1INB
O
LATF<5> data output; not affected by analog input. Disabled when
CVREF output is enabled.
1
1
x
I
I
ST
PORTF<5> data input; disabled when analog input is enabled.
Disabled when CVREF output is enabled.
AN10
ANA
ANA
A/D Input Channel 10 and Comparator C1+ input. Default input
configuration on POR.
CVREF
O
Comparator voltage reference output. Enabling this feature disables
digital I/O.
SEG23
C1INB
RF6
x
1
0
1
1
O
I
ANA
ANA
DIG
ST
LCD Segment 23 output; disables all other pin functions.
Comparator 1 Input B.
RF6/AN11/SEG24/
C1INA
O
I
LATF<6> data output; not affected by analog input.
PORTF<6> data input; disabled when analog input is enabled.
AN11
I
ANA
A/D Input Channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
SEG24
C1INA
RF7
x
1
0
1
1
1
x
O
I
ANA
ANA
DIG
ST
LCD Segment 24 output; disables all other pin functions.
Comparator 1 Input A.
RF7/AN5/SS/
SEG25
O
I
LATF<7> data output; not affected by analog input.
PORTF<7> data input; disabled when analog input is enabled.
A/D Input Channel 5. Default configuration on POR.
Slave select input for MSSP module.
AN5
SS
I
ANA
TTL
ANA
I
SEG25
O
LCD Segment 25 output; disables all other pin functions.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2010 Microchip Technology Inc.
DS39933D-page 131
PIC18F87J90 FAMILY
TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTF
LATF
RF7
LATF7
TRISF7
TRIGSEL
C2OUT
CVREN
SE23
RF6
LATF6
TRISF6
—
RF5
LATF5
TRISF5
VCFG1
C2INV
CVRR
SE21
RF4
RF3
LATF3
TRISF3
PCFG3
CIS
RF2
LATF2
TRISF2
PCFG2
CM2
RF1
LATF1
TRISF1
PCFG1
CM1
—
—
62
62
62
61
61
61
61
61
LATF4
TRISF4
VCFG0
C1INV
CVRSS
SE20
TRISF
—
ADCON1
CMCON
CVRCON
LCDSE2
LCDSE3
PCFG0
CM0
CVR0
SE16
SE24
C1OUT
CVROE
SE22
CVR3
SE19
CVR2
SE18
CVR1
SE17
SE31
SE30
SE29
SE28
SE27
SE26
SE25
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
DS39933D-page 132
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
Although the port itself is only five bits wide, the
PORTG<7:5> bits are still implemented to control the
weak pull-ups on the I/O ports associated with PORTD,
PORTE and PORTJ. Clearing these bits enables the
respective port pull-ups. All pull-ups are disabled by
default on all device Resets.
10.8 PORTG, TRISG and
LATG Registers
PORTG is
a 5-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISG and LATG. All pins on PORTG are digital only
and tolerate voltages up to 5.5V.
Most of the corresponding TRISG and LATG bits are
implemented as open-drain control bits for CCP1,
CCP2 and SPI (TRISG<7:5>), and the USARTs
(LATG<7:6>). Setting these bits configures the output
pin for the corresponding peripheral for open-drain
operation. LATG<5> is not implemented.
PORTG is multiplexed with both AUSART and LCD
functions (Table 10-16). When operating as I/O, all
PORTG pins have Schmitt Trigger input buffers. The
RG1 pin is also configurable for open-drain output
when the AUSART is active. Open-drain configuration
is selected by setting the U2OD control bit (LATG<7>).
EXAMPLE 10-7:
INITIALIZING PORTG
RG4 is multiplexed with LCD segment drives controlled
by bits in the LCDSE2 register and as the RTCC pin.
The I/O port function is only available when the
segments are disabled.
CLRF
PORTG
LATG
04h
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
CLRF
RG3 and RG2 are multiplexed with the VLCAP pins for
the LCD charge pump and RG0 is multiplexed with the
LCDBIAS0 bias voltage input. When these pins are
used for LCD bias generation, the I/O and other
functions are unavailable.
MOVLW
MOVWF
TRISG
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS bit
settings. The pin override value is not loaded into the
TRIS register. This allows read-modify-write of the TRIS
register without concern due to peripheral overrides.
2010 Microchip Technology Inc.
DS39933D-page 133
PIC18F87J90 FAMILY
TABLE 10-16: PORTG FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RG0/LCDBIAS0
RG0
0
1
x
0
1
1
O
I
DIG
ST
LATG<0> data output.
PORTG<0> data input.
LCDBIAS0
RG1
I
ANA
DIG
ST
LCD module bias voltage input.
LATG<1> data output.
RG1/TX2/CK2
O
I
PORTG<1> data input.
TX2
CK2
O
DIG
Synchronous serial data output (AUSART module); takes priority over
port data.
1
O
DIG
Synchronous serial data input (AUSART module); user must configure
as an input.
1
0
1
1
1
I
O
I
ST
DIG
ST
Synchronous serial clock input (AUSART module).
LATG<2> data output.
RG2/RX2/DT2/
VLCAP1
RG2
PORTG<2> data input.
RX2
DT2
I
ST
Asynchronous serial receive data input (AUSART module).
O
DIG
Synchronous serial data output (AUSART module); takes priority over
port data.
1
I
ST
Synchronous serial data input (AUSART module); user must configure
as an input.
VLCAP1
RG3
x
0
1
x
0
1
x
x
I
O
I
ANA
DIG
ST
LCD charge pump capacitor input.
LATG<3> data output.
RG3/VLCAP2
PORTG<3> data input.
VLCAP2
RG4
I
ANA
DIG
ST
LCD charge pump capacitor input.
LATG<4> data output.
RG4/SEG26/
RTCC
O
I
PORTG<4> data input.
SEG26
RTCC
O
O
ANA
DIG
LCD Segment 26 output; disables all other pin functions.
RTCC output.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Reset
Values on
page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTG
RDPU
U2OD
REPU
U1OD
RJPU(1)
—
RG4
RG3
RG2
RG1
RG0
62
62
62
61
LATG
LATG4
LATG3
LATG2
LATG1
LATG0
TRISG
LCDSE3
SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Unimplemented on PIC18F6XJ90 devices, read as ‘0’.
DS39933D-page 134
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
EXAMPLE 10-8:
INITIALIZING PORTH
10.9 PORTH, LATH and
TRISH Registers
CLRF
PORTH
; Initialize PORTH by
; clearing output
; data latches
Note: PORTH is available only on PIC18F8XJ90
CLRF
LATH
; Alternate method
; to clear output
; data latches
; Configure PORTH as
; digital I/O
devices.
PORTH is an 8-bit wide, bidirectional I/O port. The
corresponding Data Direction and Output Latch registers
are TRISH and LATH. All pins are digital only and
tolerate voltages up to 5.5V.
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
; Value used to
; initialize data
; direction
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
MOVWF
TRISH
All PORTH pins are multiplexed with LCD segment
drives controlled by the LCDSE5 register. I/O port
functions are only available when the segments are
disabled.
2010 Microchip Technology Inc.
DS39933D-page 135
PIC18F87J90 FAMILY
TABLE 10-18: PORTH FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RH0/SEG47
RH0
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
O
I
DIG
ST
LATH<0> data output.
PORTH<0> data input.
SEG47
RH1
O
O
I
ANA
DIG
ST
LCD Segment 47 output; disables all other pin functions.
LATH<1> data output.
RH1/SEG46
RH2/SEG45
RH3/SEG44
RH4/SEG40
RH5/SEG41
RH6/SEG42
RH7/SEG43
PORTH<1> data input.
SEG46
RH2
O
O
I
ANA
DIG
ST
LCD Segment 46 output; disables all other pin functions.
LATH<2> data output.
PORTH<2> data input.
SEG45
RH3
O
O
I
ANA
DIG
ST
LCD Segment 45 output; disables all other pin functions.
LATH<3> data output.
PORTH<3> data input.
SEG44
RH4
O
O
I
ANA
DIG
ST
LCD Segment 44 output; disables all other pin functions.
LATH<4> data output.
PORTH<4> data input.
SEG40
RH5
O
O
I
ANA
DIG
ST
LCD Segment 40 output; disables all other pin functions.
LATH<5> data output.
PORTH<5> data input.
SEG41
RH6
O
O
I
ANA
DIG
ST
LCD Segment 41 output; disables all other pin functions.
LATH<6> data output.
PORTH<6> data input.
SEG42
RH7
O
O
I
ANA
DIG
ST
LCD Segment 42 output; disables all other pin functions.
LATH<7> data output.
PORTH<7> data input.
SEG43
O
ANA
LCD Segment 43 output; disables all other pin functions.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-19: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTH
LATH
RH7
LATH7
TRISH7
SE47
RH6
LATH6
TRISH6
SE46
RH5
LATH5
TRISH5
SE45
RH4
LATH4
TRISH4
SE44
RH3
LATH3
TRISH3
SE43
RH2
RH1
RH0
62
62
62
61
LATH2
LATH1
LATH0
TRISH
LCDSE5
TRISH2 TRISH1 TRISH0
SE42 SE41 SE40
DS39933D-page 136
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
Each of the PORTJ pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit, RJPU (PORTG<5>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
10.10 PORTJ, TRISJ and
LATJ Registers
Note: PORTJ is available only on PIC18F8XJ90
devices.
PORTJ is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISJ and LATJ. All pins on PORTJ are digital only
and tolerate voltages up to 5.5V.
EXAMPLE 10-9:
INITIALIZING PORTJ
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
CLRF
CLRF
MOVLW
PORTJ
LATJ
0CFh
; Initialize PORTJ by
; clearing output latches
; Alternate method
; to clear output latches
; Value used to
Note:
These pins are configured as digital inputs
on any device Reset.
; initialize data
; direction
All PORTJ pins, except RJ0, are multiplexed with LCD
segment drives controlled by the LCDSE4 register. I/O
port functions are only available on these pins when the
segments are disabled.
MOVWF
TRISJ
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
2010 Microchip Technology Inc.
DS39933D-page 137
PIC18F87J90 FAMILY
TABLE 10-20: PORTJ FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RJ0
Function
I/O
Description
RJ0
0
1
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
O
I
DIG
ST
LATJ<0> data output.
PORTJ<0> data input.
LATJ<1> data output.
PORTJ<1> data input.
RJ1/SEG33
RJ2/SEG34
RJ3/SEG35
RJ4/SEG39
RJ5/SEG38
RJ6/SEG37
RJ7/SEG36
Legend:
RJ1
O
I
DIG
ST
SEG33
RJ2
O
O
I
ANA
DIG
ST
LCD Segment 33 output; disables all other pin functions.
LATJ<2> data output.
PORTJ<2> data input.
SEG34
RJ3
O
O
I
ANA
DIG
ST
LCD Segment 34 output; disables all other pin functions.
LATJ<3> data output.
PORTJ<3> data input.
SEG35
RJ4
O
O
I
ANA
DIG
ST
LCD Segment 35 output; disables all other pin functions.
LATJ<4> data output.
PORTJ<4> data input.
SEG39
RJ5
O
O
I
ANA
DIG
ST
LCD Segment 39 output; disables all other pin functions.
LATJ<5> data output.
PORTJ<5> data input.
SEG38
RJ6
O
O
I
ANA
DIG
ST
LCD Segment 38 output; disables all other pin functions.
LATJ<6> data output.
PORTJ<6> data input.
SEG37
RJ7
O
O
I
ANA
DIG
ST
LCD Segment 37 output; disables all other pin functions.
LATJ<7> data output.
PORTJ<7> data input.
SEG36
O
ANA
LCD Segment 36 output; disables all other pin functions.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-21: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTJ
RJ7
LATJ7
TRISJ7
RDPU
SE39
RJ6
LATJ6
TRISJ6
REPU
SE38
RJ5
RJ4
LATJ4
TRISJ4
RG4
RJ3
LATJ3
TRISJ3
RG3
RJ2
LATJ2
TRISJ2
RG2
RJ1
LATJ1
TRISJ1
RG1
RJ0
LATJ0
TRISJ0
RG0
62
62
62
62
61
LATJ
LATJ5
TRISJ5
RJPU(1)
SE37
TRISJ
PORTG
LCDSE4
SE36
SE35
SE34
SE33
SE32
Legend: Shaded cells are not used by PORTJ.
Note 1: Unimplemented on PIC18F6XJ90 devices, read as ‘0’.
DS39933D-page 138
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
prescale selection; it is both readable and writable.
11.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 11-1. Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
TMR0ON
T08BIT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-Bit/16-Bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
T0PS<2:0>: Timer0 Prescaler Select bits
111= 1:256 Prescale value
110= 1:128 Prescale value
101= 1:64 Prescale value
100= 1:32 Prescale value
011= 1:16 Prescale value
010= 1:8 Prescale value
001= 1:4 Prescale value
000= 1:2 Prescale value
2010 Microchip Technology Inc.
DS39933D-page 139
PIC18F87J90 FAMILY
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
11.1 Timer0 Operation
Timer0 can operate as either a timer or a counter. The
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 11.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
11.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor writ-
able (refer to Figure 11-2). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin, RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit, T0SE (T0CON<4>); clearing this bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
An external clock source can be used to drive Timer0,
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
1
0
Set
TMR0IF
on Overflow
Sync with
Internal
Clocks
TMR0L
8
Programmable
Prescaler
T0CKI pin
(2 TCY Delay)
T0SE
T0CS
3
T0PS<2:0>
PSA
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0
FOSC/4
1
Sync with
Internal
Clocks
Set
TMR0
High Byte
1
TMR0L
TMR0IF
Programmable
Prescaler
on Overflow
0
T0CKI pin
8
(2 TCY Delay)
T0SE
T0CS
3
Read TMR0L
Write TMR0L
T0PS<2:0>
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39933D-page 140
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
11.3.1
SWITCHING PRESCALER
ASSIGNMENT
11.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS<2:0> bits
(T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4 Timer0 Interrupt
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, are
selectable.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0L
Timer0 Register Low Byte
Timer0 Register High Byte
60
60
59
60
62
TMR0H
INTCON
T0CON
TRISA
GIE/GIEH PEIE/GIEL TMR0IE
TMR0ON T08BIT T0CS
TRISA7(1) TRISA6(1) TRISA5
INT0IE
T0SE
RBIE
PSA
TMR0IF
T0PS2
INT0IF
T0PS1
TRISA1
RBIF
T0PS0
TRISA0
TRISA4
TRISA3
TRISA2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
2010 Microchip Technology Inc.
DS39933D-page 141
PIC18F87J90 FAMILY
NOTES:
DS39933D-page 142
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
A simplified block diagram of the Timer1 module is
shown in Figure 12-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 12-2.
12.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
• Reset on CCP Special Event Trigger
• Device clock status flag (T1RUN)
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of TImer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
bit 6
T1RUN: Timer1 System Clock Status bit
1= Device clock is derived from Timer1 oscillator
0= Device clock is derived from another source
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
2010 Microchip Technology Inc.
DS39933D-page 143
PIC18F87J90 FAMILY
cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM (8-BIT MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
On/Off
1
T1OSO/T13CKI
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
0
2
Sleep Input
T1OSCEN(1)
Timer1
On/Off
TMR1CS
T1CKPS<1:0>
T1SYNC
TMR1ON
Set
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
TMR1IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
T1OSO/T13CKI
T1OSI
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T1CKPS<1:0>
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39933D-page 144
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 12-1: CAPACITOR SELECTION FOR
THE TIMER1
12.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
OSCILLATOR(2,3,4)
Oscillator
Freq.
C1
C2
Type
LP
32.768 kHz
27 pF(1)
27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
components.
4: Capacitor values are for design guidance
only.
12.3.1
USING TIMER1 AS A
CLOCK SOURCE
12.3 Timer1 Oscillator
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the System
Clock Select bits, SCS<1:0> (OSCCON<1:0>), to ‘01’,
the device switches to SEC_RUN mode; both the CPU
and peripherals are clocked from the Timer1 oscillator.
If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 4.0
“Power-Managed Modes”.
An on-chip crystal oscillator circuit is incorporated
between pins, T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is shown in Figure 12-3.
Table 12-1 shows the capacitor selection for the Timer1
oscillator.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 System Clock Status Flag, T1RUN
(T1CON<6>), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
27 pF
PIC18F87J90
T1OSI
XTAL
32.768 kHz
T1OSO
C2
27 pF
Note:
See the Notes with Table 12-1 for additional
information about capacitor selection.
2010 Microchip Technology Inc.
DS39933D-page 145
PIC18F87J90 FAMILY
12.3.2
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
12.5 Resetting Timer1 Using the CCP
Special Event Trigger
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
If CCP1 or CCP2 is configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timer3.
The trigger from CCP2 will also start an A/D conversion
if the A/D module is enabled (see Section 16.3.4
“Special Event Trigger” for more information).
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a period register for Timer1.
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
FIGURE 12-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
Note:
The Special Event Triggers from the CCPx
module will not set the TMR1IF interrupt
flag bit (PIR1<0>).
VDD
VSS
12.6 Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.3 “Timer1 Oscillator”)
gives users the option to include RTC functionality to
their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
OSC1
OSC2
RC0
RC1
RC2
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter, at one-second intervals, using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow, triggers the interrupt and calls
the routine which increments the seconds counter by
one. Additional counters for minutes and hours are
incremented as the previous counter overflows.
Note: Not drawn to scale.
12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
DS39933D-page 146
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
80h
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1CON
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
BSF
BCF
INCF
MOVLW
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
CPFSGT secs
RETURN
; No, done
CLRF
INCF
MOVLW
secs
mins, F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
CPFSGT mins
RETURN
; No, done
CLRF
INCF
MOVLW
mins
hours, F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
CPFSGT hours
RETURN
; No, done
; Reset hours
; Done
CLRF
hours
RETURN
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
59
62
62
62
60
60
60
—
—
—
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
—
—
—
TMR1IF
TMR1IE
TMR1IP
PIE1
IPR1
TMR1L
TMR1H
T1CON
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: Shaded cells are not used by the Timer1 module.
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
NOTES:
DS39933D-page 148
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
13.1 Timer2 Operation
13.0 TIMER2 MODULE
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options. These are selected by the
prescaler control bits, T2CKPS<1:0> (T2CON<1:0>).
The value of TMR2 is compared to that of the Period
register, PR2, on each clock cycle. When the two
values match, the comparator generates a match
signal as the timer output. This signal also resets the
value of TMR2 to 00h on the next cycle and drives the
output counter/postscaler (see Section 13.2 “Timer2
Interrupt”).
The Timer2 module incorporates the following features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler
(1:1, 1:4 and 1:16)
• Software programmable postscaler
(1:1 through 1:16)
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the
MSSP module
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
The module is controlled through the T2CON register
(Register 13-1) which enables or disables the timer,
and configures the prescaler and postscaler. Timer2
can be shut off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
• a write to the TMR2 register
• a write to the T2CON register
A simplified block diagram of the module is shown in
Figure 13-1.
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS<3:0>: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
2010 Microchip Technology Inc.
DS39933D-page 149
PIC18F87J90 FAMILY
13.2 Timer2 Interrupt
13.3 Timer2 Output
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 18.0
“Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR2IF
Postscaler
T2OUTPS<3:0>
T2CKPS<1:0>
2
TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Match
Reset
1:1, 1:4, 1:16
Prescaler
FOSC/4
TMR2
Comparator
PR2
8
8
8
Internal Data Bus
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
59
62
62
62
60
60
60
PIR1
—
—
—
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
—
—
—
TMR1IF
TMR1IE
TMR1IP
PIE1
IPR1
TMR2
T2CON
PR2
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
DS39933D-page 150
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
A simplified block diagram of the Timer3 module is
shown in Figure 14-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 14-2.
14.0 TIMER3 MODULE
The Timer3 timer/counter module incorporates these
features:
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the CCP modules. See Section 16.2.2
“Timer1/Timer3 Mode Selection” for more
information.
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
• Module Reset on CCP Special Event Trigger
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
bit 6,3
T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits
1x= Timer3 is the capture/compare clock source for the CCP modules
01= Timer3 is the capture/compare clock source for CCP2;
Timer1 is the capture/compare clock source for CCP1
00= Timer1 is the capture/compare clock source for the CCP modules
bit 5-4
bit 2
T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Does not synchronize the external clock input
0= Synchronizes the external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
2010 Microchip Technology Inc.
DS39933D-page 151
PIC18F87J90 FAMILY
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
As
with
Timer1,
the
RC1/T1OSI
and
RC0/T1OSO/T13CKI pins become inputs when the
Timer1 oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM (8-BIT MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
1
0
T1OSO/T13CKI
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T3CKPS<1:0>
T3SYNC
Timer3
On/Off
TMR3CS
TMR3ON
CCPx Special Event Trigger
Clear TMR3
Set
TMR3
High Byte
TMR3L
TMR3IF
CCPx Select from T3CON<6,3>
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
1
0
T13CKI/T1OSO
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T3CKPS<1:0>
T3SYNC
Timer3
On/Off
TMR3CS
TMR3ON
CCPx Special Event Trigger
Clear TMR3
Set
TMR3IF
on Overflow
TMR3
High Byte
TMR3L
CCPx Select from T3CON<6,3>
8
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39933D-page 152
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
14.2 Timer3 16-Bit Read/Write Mode
14.4 Timer3 Interrupt
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5 Resetting Timer3 Using the CCP
Special Event Trigger
If CCP1 or CCP2 is configured to use Timer3 and to
generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timer3.
The trigger from CCP2 will also start an A/D conversion
if the A/D module is enabled (see Section 16.3.4
“Special Event Trigger” for more information).
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a period register for Timer3.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
14.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
Note:
The Special Event Triggers from the CCPx
module will not set the TMR3IF interrupt
flag bit (PIR2<1>).
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
—
RBIE
BCLIF
BCLIE
BCLIP
TMR0IF
LVDIF
LVDIE
LVDIP
INT0IF
TMR3IF
TMR3IE
TMR3IP
RBIF
—
59
62
62
62
61
61
60
61
OSCFIF
OSCFIE
OSCFIP
CMIF
CMIE
CMIP
—
—
—
PIE2
—
—
IPR2
—
—
TMR3L
TMR3H
T1CON
T3CON
Timer3 Register Low Byte
Timer3 Register High Byte
RD16
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
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NOTES:
DS39933D-page 154
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The RTCC module is intended for applications where
accurate time must be maintained for an extended
period, with minimum to no intervention from the CPU.
The module is optimized for low-power usage in order
to provide extended battery life while keeping track of
time.
15.0 REAL-TIME CLOCK AND
CALENDAR (RTCC)
The key features of the Real-Time Clock and Calendar
(RTCC) module are:
• Time: hours, minutes and seconds
• 24-hour format (military time)
The module is a 100-year clock and calendar with auto-
matic leap year detection. The range of the clock is
from 00:00:00 (midnight) on January 1, 2000 to
23:59:59 on December 31, 2099. Hours are measured
in 24-hour (military time) format. The clock provides a
granularity of one second with half-second visibility to
the user.
• Calendar: weekday, date, month and year
• Alarm configurable
• Year range: 2000 to 2099
• Leap year correction
• BCD format for compact firmware
• Optimized for low-power operation
• User calibration with auto-adjust
• Calibration range: 2.64 seconds error per month
• Requirements: external 32.768 kHz clock crystal
• Alarm pulse or seconds clock output on RTCC pin
FIGURE 15-1:
RTCC BLOCK DIAGRAM
CPU Clock Domain
RTCC Clock Domain
32.768 kHz Input
from Timer1 Oscillator
RTCCFG
RTCC Prescalers
0.5s
ALRMRPT
YEAR
Internal RC
MTHDY
RTCVALx
WKDYHR
RTCC Timer
Alarm
MINSEC
Event
Comparator
ALMTHDY
Compare Registers
with Masks
ALRMVALx
ALWDHR
ALMINSEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
RTCC Pin
RTCOE
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Alarm Value Registers
15.1 RTCC MODULE REGISTERS
• ALRMVALH and ALRMVALL – Can access the
following registers:
The RTCC module registers are divided into following
categories:
- ALRMMNTH
- ALRMDAY
- ALRMWD
- ALRMHR
RTCC Control Registers
• RTCCFG
• RTCCAL
- ALRMMIN
- ALRMSEC
• PADCFG1
• ALRMCFG
• ALRMRPT
Note:
The RTCVALH and RTCVALL registers
can be accessed through RTCRPT<1:0>.
ALRMVALH and ALRMVALL can be
accessed through ALRMPTR<1:0>.
RTCC Value Registers
• RTCVALH and RTCVALL – Can access the fol-
lowing registers
- YEAR
- MONTH
- DAY
- WEEKDAY
- HOUR
- MINUTE
- SECOND
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15.1.1
RTCC CONTROL REGISTERS
REGISTER 15-1:
RTCCFG: RTCC CONFIGURATION REGISTER(1)
R/W-0
RTCEN(2)
bit 7
U-0
—
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
RTCWREN RTCSYNC HALFSEC(3)
RTCOE
RTCPTR1
RTCPTR0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
(2)
bit 7
RTCEN: RTCC Enable bit
1= RTCC module is enabled
0= RTCC module is disabled
bit 6
bit 5
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1= RTCVALH and RTCVALL registers can be written to by the user
0= RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 4
RTCSYNC: RTCC Value Registers Read Synchronization bit
1= RTCVALH, RTCVALL and ALRMRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
0= RTCVALH, RTCVALL and ALCFGRPT registers can be read without concern over a rollover
ripple
bit 3
HALFSEC: Half-Second Status bit(3)
1= Second half period of a second
0= First half period of a second
bit 2
RTCOE: RTCC Output Enable bit
1= RTCC clock output enabled
0= RTCC clock output disabled
bit 1-0
RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH<7:0> until it reaches ‘00’.
RTCVALH:
00= Minutes
01= Weekday
10= Month
11= Reserved
RTCVALL:
00= Seconds
01= Hours
10= Day
11= Year
Note 1: The RTCCFG register is only affected by a POR. For resets other than POR, RTCC will continue to run
even if the device is in Reset.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
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REGISTER 15-2:
RTCCAL: RTCC CALIBRATION REGISTER
R/W-0
CAL7
R/W-0
CAL6
R/W-0
CAL5
R/W-0
CAL4
R/W-0
CAL3
R/W-0
CAL2
R/W-0
CAL1
R/W-0
CAL0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
CAL<7:0>: RTC Drift Calibration bits
01111111= Maximum positive adjustment; adds 508 RTC clock pulses every minute
.
.
.
00000001= Minimum positive adjustment; adds four RTC clock pulses every minute
00000000= No adjustment
11111111= Minimum negative adjustment; subtracts four RTC clock pulses every minute
.
.
.
10000000= Maximum negative adjustment; subtracts 512 RTC clock pulses every minute
REGISTER 15-3: PADCFG1: PAD CONFIGURATION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
RTSECSEL1(1) RTSECSEL0(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-3
bit 2-1
Unimplemented: Read as ‘0’
RTSECSEL<1:0>: RTCC Seconds Clock Output Select bit(1)
11= Reserved; do not use
10= RTCC source clock is selected for the RTCC pin (pin can be INTOSC or Timer1 oscillator, depending
on the RTCOSC (CONFIG3L<1>) bit setting)(2)
01= RTCC seconds clock is selected for the RTCC pin
00= RTCC alarm pulse is selected for the RTCC pin
bit 0
Unimplemented: Read as ‘0’
Note 1: To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set.
2: If the Timer1 oscillator is the clock source for RTCC, the T1OSCEN bit should be set (T1CON<3> = 1).
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REGISTER 15-4: ALRMCFG: ALARM CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
AMASK0
ALRMPTR1 ALRMPTR0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ALRMEN: Alarm Enable bit
1= Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00
and CHIME = 0)
0= Alarm is disabled
bit 6
CHIME: Chime Enable bit
1= Chime is enabled; ALRMPTR<1:0> bits are allowed to roll over from 00h to FFh
0= Chime is disabled; ALRMPTR<1:0> bits stop once they reach 00h
bit 5-2
AMASK<3:0>: Alarm Mask Configuration bits
0000= Every half second
0001= Every second
0010= Every 10 seconds
0011= Every minute
0100= Every 10 minutes
0101= Every hour
0110= Once a day
0111= Once a week
1000= Once a month
1001= Once a year (except when configured for February 29th, once every four years)
101x= Reserved – do not use
11xx= Reserved – do not use
bit 1-0
ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL
registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches
‘00’.
ALRMVALH:
00= ALRMMIN
01= ALRMWD
10= ALRMMNTH
11= Unimplemented
ALRMVALL:
00= ALRMSEC
01= ALRMHR
10= ALRMDAY
11= Unimplemented
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REGISTER 15-5: ALRMRPT: ALARM REPEAT REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
ARPT<7:0>: Alarm Repeat Counter Value bits
11111111= Alarm will repeat 255 more times
.
.
.
00000000= Alarm will not repeat
The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to
FFh unless CHIME = 1.
15.1.2
RTCVALH AND RTCVALL
REGISTER MAPPINGS
REGISTER 15-6: RESERVED REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
Unimplemented: Read as ‘0’
REGISTER 15-7: YEAR: YEAR VALUE REGISTER(1)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
bit 3-0
YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.
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REGISTER 15-8: MONTH: MONTH VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MTHONE0
bit 0
MTHTEN0 MTHONE3
MTHONE2
MTHONE1
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 3-0
MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 15-9: DAY: DAY VALUE REGISTER(1)
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
DAYONE0
bit 0
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DAYTEN<1:0>: Binary Coded Decimal value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 15-10: WEEKDAY: WEEKDAY VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
WDAY0
bit 0
WDAY2
WDAY1
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
Note 1: A write to this register is only allowed when RTCWREN = 1.
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REGISTER 15-11: HOUR: HOUR VALUE REGISTER(1)
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 15-12: MINUTE: MINUTE VALUE REGISTER
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
REGISTER 15-13: SECOND: SECOND VALUE REGISTER
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SECTEN2
SECTEN1
SECTEN0 SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
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15.1.3
ALRMVALH AND ALRMVALL
REGISTER MAPPINGS
REGISTER 15-14: ALRMMNTH: ALARM MONTH VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MTHONE0
bit 0
MTHTEN0 MTHONE3
MTHONE2
MTHONE1
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 3-0
MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 15-15: ALRMDAY: ALARM DAY VALUE REGISTER(1)
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
DAYONE0
bit 0
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 15-16: ALRMWD: ALARM WEEKDAY VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
WDAY0
bit 0
WDAY2
WDAY1
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
Note 1: A write to this register is only allowed when RTCWREN = 1.
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REGISTER 15-17: ALRMHR: ALARM HOURS VALUE REGISTER(1)
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 15-18: ALRMMIN: ALARM MINUTES VALUE REGISTER
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
REGISTER 15-19: ALRMSEC: ALARM SECONDS VALUE REGISTER
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SECTEN2
SECTEN1
SECTEN0 SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
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15.1.4
RTCEN BIT WRITE
15.2 Operation
An attempt to write to the RTCEN bit while
RTCWREN = 0 will be ignored. RTCWREN must be
set before a write to RTCEN can take place.
15.2.1
REGISTER INTERFACE
The register interface for the RTCC and alarm values is
implemented using the Binary Coded Decimal (BCD)
format. This simplifies the firmware when using the
module as each of the digits is contained within its own
4-bit value (see Figure 15-2 and Figure 15-3).
Like the RTCEN bit, the RTCVALH and RTCVALL
registers can only be written to when RTCWREN = 1.
A write to these registers, while RTCWREN = 0, will be
ignored.
FIGURE 15-2:
TIMER DIGIT FORMAT
Year
Day
Day Of Week
0-6
Month
0-9
0-9
0-3
0-9
0-1
0-9
Hours
1/2 Second Bit
Minutes
Seconds
(24-hour format)
(binary format)
0/1
0-2
0-9
0-5
0-9
0-5
0-9
FIGURE 15-3:
ALARM DIGIT FORMAT
Day
Day Of Week
0-6
Month
0-3
0-9
0-1
0-9
Hours
(24-hour format)
Minutes
Seconds
0-2
0-9
0-5
0-9
0-5
0-9
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Calibration of the crystal can be done through this
module to yield an error of 3 seconds or less per month.
(For further details, see Section 15.2.9 “Calibration”.)
15.2.2
CLOCK SOURCE
As mentioned earlier, the RTCC module is intended to
be clocked by an external Real-Time Clock crystal,
oscillating at 32.768 kHz, but can also be an internal
oscillator. The RTCC clock selection is decided by the
RTCOSC bit (CONFIG3L<1>).
FIGURE 15-4:
CLOCK SOURCE MULTIPLEXING
32.768 kHz XTAL
from SOSC
Half Second
1:16384
Clock Prescaler(1)
Clock
One Second Clock
Half second(1)
Internal RC
CONFIG 3L<1>
Day
Second
Hour:Minute
Month
Year
Day of Week
Note 1: Writing to the lower half of the MINSEC register resets all counters, allowing fraction of a second
synchronization; clock prescaler is held in Reset when RTCEN = 0.
15.2.2.1
Real-Time Clock Enable
TABLE 15-1: DAY OF WEEK SCHEDULE
Day of Week
The RTCC module can be clocked by an external,
32.768 kHz crystal (Timer1 oscillator) or the Internal RC
oscillator, which can be selected in CONFIG3L<1>.
Sunday
Monday
0
1
2
3
4
5
6
If the external clock is used, the Timer1 oscillator
should be enabled by setting the T1OSCEN bit
(T1CON<3> = 1). If INTRC is providing the clock, the
INTRC clock can be brought out to the RTCC pin by the
RTSECSEL<1:0> bits in the PADCFG register.
Tuesday
Wednesday
Thursday
Friday
15.2.3
DIGIT CARRY RULES
Saturday
This section explains which timer values are affected
when there is a rollover.
TABLE 15-2: DAY TO MONTH ROLLOVER
SCHEDULE
• Time of Day: from 23:59:59 to 00:00:00 with a
carry to the Day field
Month
Maximum Day Field
• Month: from 12/31 to 01/01 with a carry to the
Year field
01 (January)
02 (February)
03 (March)
31
28 or 29(1)
• Day of Week: from 6 to 0 with no carry (see
Table 15-1)
31
30
31
30
31
31
30
31
30
31
04 (April)
• Year Carry: from 99 to 00; this also surpasses the
use of the RTCC
05 (May)
For the day to month rollover schedule, see Table 15-2.
06 (June)
Considering that the following values are in BCD for-
mat, the carry to the upper BCD digit will occur at a
count of 10 and not at 16 (SECONDS, MINUTES,
HOURS, WEEKDAY, DAYS and MONTHS).
07 (July)
08 (August)
09 (September)
10 (October)
11 (November)
12 (December)
Note 1: See Section 15.2.4 “Leap Year”.
DS39933D-page 166
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15.2.4
LEAP YEAR
15.2.7
WRITE LOCK
Since the year range on the RTCC module is 2000 to
2099, the leap year calculation is determined by any year
divisible by 4 in the above range. Only February is
effected in a leap year.
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RTCCFG<5>) must be set.
To avoid accidental writes to the RTCC Timer register,
it is recommended that the RTCWREN bit
(RTCCFG<5>) be kept clear at any time other than
while writing to it. For the RTCWREN bit to be set, there
is only one instruction cycle time window allowed
between the 55h/AA sequence and the setting of
RTCWREN. For that reason, it is recommended that
users follow the code example in Example 15-1.
February will have 29 days in a leap year and 28 days in
any other year.
15.2.5
GENERAL FUNCTIONALITY
All Timer registers containing a time value of seconds or
greater are writable. The user configures the time by
writing the required year, month, day, hour, minutes and
seconds to the Timer registers, via register pointers (see
Section 15.2.8 “Register Mapping”).
EXAMPLE 15-1:
SETTING THE RTCWREN
BIT
movlw
movwf
movlw
movwf
bsf
0x55
EECON2
0xAA
EECON2
The timer uses the newly written values and proceeds
with the count from the required starting point.
The RTCC is enabled by setting the RTCEN bit
(RTCCFG<7>). If enabled while adjusting these regis-
ters, the timer still continues to increment. However, any
time the MINSEC register is written to, both of the timer
prescalers are reset to ‘0’. This allows fraction of a
second synchronization.
RTCCFG,RTCWREN
15.2.8
REGISTER MAPPING
To limit the register interface, the RTCC Timer and
Alarm Timer registers are accessed through
corresponding register pointers. The RTCC Value
register window (RTCVALH and RTCVALL) uses the
RTCPTR bits (RTCCFG<1:0>) to select the required
Timer register pair.
The Timer registers are updated in the same cycle as
the write instruction’s execution by the CPU. The user
must ensure that when RTCEN = 1, the updated
registers will not be incremented at the same time. This
can be accomplished in several ways:
By reading or writing to the RTCVALH register, the
RTCC Pointer value (RTCPTR<1:0>) decrements by ‘1’
until it reaches ‘00’. Once it reaches ‘00’, the MINUTES
and SECONDS value will be accessible through
RTCVALH and RTCVALL until the pointer value is
manually changed.
• By checking the RTCSYNC bit (RTCCFG<4>)
• By checking the preceding digits from which a
carry can occur
• By updating the registers immediately following
the seconds pulse (or alarm interrupt)
The user has visibility to the half-second field of the
counter. This value is read-only and can be reset only
by writing to the lower half of the SECONDS register.
TABLE 15-3: RTCVALH AND RTCVALL
REGISTER MAPPING
RTCC Value Register Window
RTCPTR<1:0>
15.2.6
SAFETY WINDOW FOR REGISTER
READS AND WRITES
RTCVALH
RTCVALL
00
01
10
11
MINUTES
WEEKDAY
MONTH
—
SECONDS
HOURS
DAY
The RTCSYNC bit indicates a time window during
which the RTCC clock domain registers can be safely
read and written without concern about a rollover.
When RTCSYNC = 0, the registers can be safely
accessed by the CPU.
YEAR
Whether RTCSYNC = 1or 0, the user should employ a
firmware solution to ensure that the data read did not
fall on a rollover boundary, resulting in an invalid or
partial read. This firmware solution would consist of
reading each register twice and then comparing the two
values. If the two values matched, then a rollover did
not occur.
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits (ALRMCFG<1:0>)
to select the desired Alarm register pair.
By reading or writing to the ALRMVALH register, the
Alarm Pointer value, ALRMPTR<1:0>, decrements by ‘1’
until it reaches ‘00’. Once it reaches ‘00’, the ALRMMIN
and ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
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Writes to the RTCCAL register should occur only when
the timer is turned off or immediately after the rising
edge of the seconds pulse.
TABLE 15-4: ALRMVAL REGISTER
MAPPING
Alarm Value Register Window
ALRMPTR<1:0>
Note:
In determining the crystal’s error value, it
is the user’s responsibility to include the
crystal’s initial error from drift due to
temperature or crystal aging.
ALRMVALH
ALRMVALL
00
01
10
11
ALRMMIN
ALRMWD
ALRMMNTH
—
ALRMSEC
ALRMHR
ALRMDAY
—
15.3 Alarm
The alarm features and characteristics are:
• Configurable from half a second to one year
15.2.9
CALIBRATION
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than three
seconds per month.
• Enabled using the ALRMEN bit (ALRMCFG<7>,
Register 15-4)
• Offers one-time and repeat alarm options
To perform this calibration, find the number of error
clock pulses and store the value into the lower half of
the RTCCAL register. The 8-bit, signed value, loaded
into RTCCAL, is multiplied by 4 and will either be added
or subtracted from the RTCC timer, once every minute.
15.3.1
CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. The bit will
not be cleared if the CHIME bit = 1or if ALRMRPT 0.
The interval selection of the alarm is configured
through the ALRMCFG (AMASK<3:0>) bits (see
Figure 15-5). These bits determine which and how
many digits of the alarm must match the clock value for
the alarm to occur.
To calibrate the RTCC module:
1. Use another timer resource on the device to find
the error of the 32.768 kHz crystal.
2. Convert the number of error clock pulses per
minute (see Equation 15-1).
The alarm can also be configured to repeat based on a
preconfigured interval. The number of times this
occurs, after the alarm is enabled, is stored in the
ALRMRPT register.
EQUATION 15-1: CONVERTING ERROR,
CLOCK PULSES
(Ideal Frequency (32,758) – Measured Frequency) * 60 =
Error Clocks per Minute
Note:
While the alarm is enabled (ALRMEN = 1),
changing any of the registers, other than
the RTCCAL, ALRMCFG and ALRMRPT
registers and the CHIME bit, can result in
a false alarm event leading to a false
alarm interrupt. To avoid this, only change
the timer and alarm values while the alarm
is disabled (ALRMEN = 0). It is recom-
mended that the ALRMCFG and
ALRMRPT registers and CHIME bit be
changed when RTCSYNC = 0.
• If the oscillator is faster than ideal (negative result
from step 2), the RCFGCALL register value
needs to be negative. This causes the specified
number of clock pulses to be subtracted from the
timer counter once every minute.
• If the oscillator is slower than ideal (positive
result from step 2), the RCFGCALL register
value needs to be positive. This causes the
specified number of clock pulses to be added to
the timer counter once every minute.
3. Load the RTCCAL register with the correct value.
DS39933D-page 168
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FIGURE 15-5:
ALARM MASK SETTINGS
Alarm Mask Setting
Day of the
Week
AMASK<3:0>
Month
Day
Hours
Minutes
Seconds
0000– Every half second
0001– Every second
0010– Every 10 seconds
0011– Every minute
0100– Every 10 minutes
0101– Every hour
s
s
s
s
s
s
s
s
s
s
s
m
m
m
m
m
m
m
m
m
m
m
0110– Every day
h
h
h
h
h
h
h
h
0111– Every week
1000– Every month
1001– Every year(1)
d
d
d
d
s
s
s
s
m
m
d
Note 1: Annually, except when configured for February 29.
When ALRMCFG = 00 and the CHIME bit = 0
(ALRMCFG<6>), the repeat function is disabled and
only a single alarm will occur. The alarm can be
repeated up to 255 times by loading the ALRMRPT
register with FFh.
15.3.2
ALARM INTERRUPT
At every alarm event, an interrupt is generated. Addi-
tionally, an alarm pulse output is provided that operates
at half the frequency of the alarm.
The alarm pulse output is completely synchronous with
the RTCC clock and can be used as a trigger clock to
other peripherals. This output is available on the RTCC
pin. The output pulse is a clock with a 50% duty cycle
and a frequency, half that of the alarm event (see
Figure 15-6).
After each alarm is issued, the ALRMRPT register is
decremented by one. Once the register has reached
‘00’, the alarm will be issued one last time.
After the alarm is issued a last time, the ALRMEN bit is
cleared automatically and the alarm turned off. Indefinite
repetition of the alarm can occur if the CHIME bit = 1.
The RTCC pin also can output the seconds clock. The
user can select between the alarm pulse, generated by
the RTCC module, or the seconds clock output.
When CHIME = 1, the alarm is not disabled when the
ALRMRPT register reaches ‘00’, but it rolls over to FF
and continues counting indefinitely.
The RTSECSEL<1:0> (PADCFG1<2:1>) bits select
between these two outputs:
• Alarm Pulse – RTSECSEL<1:0> = 00
• Seconds Clock – RTSECSEL<1:0> = 01
2010 Microchip Technology Inc.
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FIGURE 15-6:
TIMER PULSE GENERATION
RTCEN bit
ALRMEN bit
RTCC Alarm Event
RTCC Pin
15.4 Sleep Mode
15.5 Reset
The timer and alarm continue to operate while in Sleep
mode. The operation of the alarm is not affected by
Sleep, as an alarm event can always wake-up the
CPU.
15.5.1
DEVICE RESET
When a device Reset occurs, the ALCFGRPT register
is forced to its Reset state causing the alarm to be
disabled (if enabled prior to the Reset). If the RTCC
was enabled, it will continue to operate when a basic
device Reset occurs.
The Idle mode does not affect the operation of the timer
or alarm.
15.5.2
POWER-ON RESET (POR)
The RTCCFG and ALRMRPT registers are reset only
on a POR. Once the device exits the POR state, the
clock registers should be reloaded with the desired
values.
The timer prescaler values can be reset only by writing
to the SECONDS register. No device Reset can affect
the prescalers.
DS39933D-page 170
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15.6 Register Maps
Table 15-5, Table 15-6 and Table 15-7 summarize the
registers associated with the RTCC module.
TABLE 15-5: RTCC CONTROL REGISTERS
All
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Resets
on Page
RTCCFG
RTCCAL
RTCEN
CAL7
—
RTCWREN RTCSYNC HALFSEC
RTCOE
CAL2
RTCPTR1 RTCPTR0
64
64
64
64
64
CAL6
—
CAL5
—
CAL4
—
CAL3
—
CAL1
CAL0
—
PADCFG1
ALRMCFG
ALRMRPT
Legend:
—
RTSECSEL1 RTSECSEL0
ALRMEN
ARPT7
CHIME
ARPT6
AMASK3
ARPT5
AMASK2
ARPT4
AMASK1
ARPT3
AMASK0
ARPT2
ALRMPTR1 ALRMPTR0
ARPT1 ARPT0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 80-pin devices.
TABLE 15-6: RTCC VALUE REGISTERS
All Resets
on Page
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RTCVALH RTCC Value High Register Window Based on RTCPTR<1:0>
RTCVALL RTCC Value Low Register Window Based on RTCPTR<1:0>
64
64
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 80-pin devices.
TABLE 15-7: ALARM VALUE REGISTERS
All
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Resets
on Page
ALRMVALH Alarm Value High Register Window Based on ALRMPTR<1:0>
ALRMVALL Alarm Value Low Register Window Based on ALRMPTR<1:0>
64
64
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 80-pin devices.
2010 Microchip Technology Inc.
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NOTES:
DS39933D-page 172
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Each CCP module contains two 8-bit registers that can
operate as two 8-bit Capture registers, two 8-bit
Compare registers or two PWM Master/Slave Duty
Cycle registers. For the sake of clarity, all CCP module
operation in the following sections is described with
respect to CCP2, but is equally applicable to CCP1.
16.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F87J90 family devices have two CCP
(Capture/Compare/PWM) modules, designated CCP1
and CCP2. Both modules implement standard capture,
compare and Pulse-Width Modulation (PWM) modes.
REGISTER 16-1: CCPxCON: CCPx CONTROL REGISTER (CCP1, CCP2 MODULES)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM<3:0>: CCPx Module Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Reserved
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit
is set)
1001= Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit
is set)
1010= Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
reflects I/O state)
1011= Compare mode: Special Event Trigger; reset timer; start A/D conversion on CCPx match
(CCPxIF bit is set)(1)
11xx= PWM mode
Note 1: CCPxM<3:0> = 1011will only reset the timer and not start an A/D conversion on a CCP1 match.
2010 Microchip Technology Inc.
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Depending on the configuration selected, up to four
timers may be active at once, with modules in the same
configuration (Capture/Compare or PWM) sharing
timer resources. The possible configurations are
shown in Figure 16-1.
16.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
16.1.2
OPEN-DRAIN OUTPUT OPTION
When operating in Output mode (i.e., in Compare or
PWM modes), the drivers for the CCPx pins can be
optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled
to a higher level through an external pull-up resistor
and allows the output to communicate with external
circuits without the need for additional level shifters.
16.1.1
CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize timers 1, 2 or 3, depending on
the mode selected. Timer1 and Timer3 are available to
modules in Capture or Compare modes, while Timer2
is available for modules in PWM mode.
The open-drain output option is controlled by the
CCP2OD and CCP1OD bits (TRISG<6:5>). Setting the
appropriate bit configures the pin for the corresponding
module for open-drain operation.
TABLE 16-1: CCP MODE – TIMER
RESOURCE
CCP Mode
Timer Resource
16.1.3
CCP2 PIN ASSIGNMENT
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
The pin assignment for CCP2 (capture input, compare
and PWM output) can change, based on device config-
uration. The CCP2MX Configuration bit determines
which pin CCP2 is multiplexed to. By default, it is
assigned to RC1 (CCP2MX = 1). If the Configuration bit
is cleared, CCP2 is multiplexed with RE7.
The assignment of a particular timer to a module is
determined by the Timer to CCP enable bits in the
T3CON register (Register 14-1). Both modules may be
active at any given time and may share the same timer
resource if they are configured to operate in the same
mode (Capture/Compare or PWM) at the same time.
The interactions between the two modules are
summarized in Table 16-2.
Changing the pin assignment of CCP2 does not
automatically change any requirements for configuring
the port pin. Users must always verify that the appropri-
ate TRIS register is configured correctly for CCP2
operation, regardless of where it is located.
FIGURE 16-1:
CCP AND TIMER INTERCONNECT CONFIGURATIONS
T3CCP<2:1> = 00
T3CCP<2:1> = 01
T3CCP<2:1> = 1x
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
CCP1
CCP2
CCP1
CCP1
CCP2
CCP2
TMR2
TMR2
TMR2
Timer1 is used for all capture
and compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Timer1 is used for capture
and compare operations for
CCP1 and Timer 3 is used for
CCP2.
Timer3 is used for all capture
and compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Both the modules use Timer2
as a common time base if they
are in PWM modes.
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TABLE 16-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP1 Mode CCP2 Mode
Interaction
Capture
Capture
Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.
Capture
Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on a trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare
Compare
Capture
CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Operation of CCP2 could be affected if it is
using the same timer as a time base.
Compare Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on a CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture
Compare
PWM
PWM
PWM
None
None
None
Capture
PWM
Compare None
PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
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16.2.3
SOFTWARE INTERRUPT
16.2 Capture Mode
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP2IE bit (PIE3<2>) clear to avoid false interrupts
and should clear the flag bit, CCP2IF, following any
such change in operating mode.
In Capture mode, the CCPR2H:CCPR2L register pair
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the CCP2 pin (RC1 or RE7,
depending on device configuration). An event is
defined as one of the following:
• Every falling edge
• Every rising edge
16.2.4
CCP PRESCALER
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCP2M<3:0>).
Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter
is cleared. This means that any Reset will clear the
prescaler counter.
• Every 4th rising edge
• Every 16th rising edge
The event is selected by the mode select bits,
CCP2M<3:0> (CCP2CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP2IF (PIR3<2>), is
set; it must be cleared in software. If another capture
occurs before the value in register, CCPR2, is read, the old
captured value is overwritten by the new captured value.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
16.2.1
CCP PIN CONFIGURATION
a
non-zero prescaler. Example 16-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
Note:
If RC1/CCP2 or RE7/CCP2 is configured
as an output, a write to the port can cause
a capture condition.
EXAMPLE 16-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF CCP2CON
; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
16.2.2
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 16.1.1 “CCP Modules and Timer
Resources”).
; value and CCP ON
MOVWF CCP2CON
; Load CCP2CON with
; this value
FIGURE 16-2:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
Set CCP1IF
T3CCP2
TMR3
Enable
CCP1 Pin
Prescaler
1, 4, 16
and
Edge Detect
CCPR1H
CCPR1L
TMR1
Enable
T3CCP2
TMR1H
TMR1L
TMR3L
4
4
CCP1CON<3:0>
Q1:Q4
Set CCP2IF
4
CCP2CON<3:0>
TMR3H
T3CCP1
T3CCP2
TMR3
Enable
CCP2 Pin
Prescaler
1, 4, 16
and
Edge Detect
CCPR2H
CCPR2L
TMR1L
TMR1
Enable
T3CCP2
T3CCP1
TMR1H
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16.3.3
SOFTWARE INTERRUPT MODE
16.3 Compare Mode
When the Generate Software Interrupt mode is chosen
(CCP2M<3:0> = 1010), the CCP2 pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCP2IE bit is set.
In Compare mode, the 16-bit CCPR2 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP2
pin can be:
• driven high
16.3.4
SPECIAL EVENT TRIGGER
• driven low
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP2M<3:0> = 1011).
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCP2M<3:0>). At the same time, the
interrupt flag bit, CCP2IF, is set.
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
16.3.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D Converter
must already be enabled.
Note:
Clearing the CCP2CON register will force
the RC1 or RE7 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTC or
PORTE I/O data latch.
Note:
The Special Event Trigger of CCP1 only
resets Timer1/Timer3 and cannot start an
A/D conversion, even when the A/D
Converter is enabled.
16.3.2
TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
FIGURE 16-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
(Timer1 Reset)
Set CCP1IF
CCPR1H
CCPR1L
CCP1 Pin
S
R
Q
Output
Logic
Compare
Match
Comparator
TRIS
Output Enable
4
CCP1CON<3:0>
TMR1H
TMR3H
TMR1L
TMR3L
0
0
1
1
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
T3CCP1
T3CCP2
Set CCP2IF
CCP2 Pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
CCPR2H
CCPR2L
CCP2CON<3:0>
2010 Microchip Technology Inc.
DS39933D-page 177
PIC18F87J90 FAMILY
TABLE 16-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page
INTCON
RCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
59
60
62
62
62
62
62
62
62
62
62
60
60
60
61
61
61
63
63
63
64
63
64
IPEN
—
—
CM
RC2IF
RC2IE
RC2IP
—
PIR3
LCDIF
LCDIE
LCDIP
CMIF
TX2IF
TX2IE
TX2IP
—
CTMUIF CCP2IF
CCP1IF RTCCIF
PIE3
—
CTMUIE CCP2IE CCP1IE RTCCIE
CTMUIP CCP2IP CCP1IP RTCCIP
IPR3
—
PIR2
OSCFIF
OSCFIE
OSCFIP
TRISC7
TRISE7
SPIOD
BCLIF
BCLIE
LVDIF
LVDIE
LVDIP
TRISC2
—
TMR3IF
TMR3IE
TMR3IP
TRISC1
TRISE1
—
—
PIE2
CMIE
—
—
IPR2
CMIP
—
—
BCLIP
—
TRISC
TRISE
TRISC6
TRISE6
TRISC5
TRISE5
TRISC4
TRISE4
TRISC3
TRISE3
TRISG3
TRISC0
TRISE0
TRISG
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
CCP2OD CCP1OD TRISG4
TRISG2 TRISG1 TRISG0
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer3 Register High Byte
Timer3 Register Low Byte
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
—
—
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
Capture/Compare/PWM Register 2 Low Byte
Capture/Compare/PWM Register 2 High Byte
—
—
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
DS39933D-page 178
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
A PWM output (Figure 16-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
16.4 PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCP2 pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTC or PORTE
data latch, the appropriate TRIS bit must be cleared to
make the CCP2 pin an output.
FIGURE 16-5:
PWM OUTPUT
Period
Note:
Clearing the CCP2CON register will force
the RC1 or RE7 output latch (depending
on the device configuration) to the default
low level. This is not the PORTC or
PORTE I/O data latch.
Duty Cycle
TMR2 = PR2
Figure 16-4 shows a simplified block diagram of the
CCP1 module in PWM mode.
TMR2 = Duty Cycle
TMR2 = PR2
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 16.4.3
“Setup for PWM Operation”.
16.4.1
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
FIGURE 16-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers
EQUATION 16-1:
CCPR1L
PWM Period = (PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
CCPR1H (Slave)
Comparator
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Q
R
RC2/CCP1
• TMR2 is cleared
(Note 1)
TMR2
• The CCP2 pin is set (exception: if PWM duty
cycle = 0%, the CCP2 pin will not be set)
S
• The PWM duty cycle is latched from CCPR2L into
CCPR2H
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
Note:
The Timer2 postscalers (see Section 13.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
2010 Microchip Technology Inc.
DS39933D-page 179
PIC18F87J90 FAMILY
The CCPR2H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
16.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR2L register and to the CCP2CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR2L contains
the eight MSbs and the CCP2CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR2L:CCP2CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
When the CCPR2H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP2 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 16-2:
PWM Duty Cycle = (CCPR2L:CCP2CON<5:4>) •
TOSC • (TMR2 Prescale Value)
EQUATION 16-3:
FOSC
log ---------------
FPWM
= ----------------------------- b i t s
log2
PWM Resolution (max)
CCPR2L and CCP2CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR2H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR2H is a read-only register.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP2 pin will not be
cleared.
TABLE 16-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
14
4
1
1
3Fh
8
1
1Fh
7
1
FFh
12
FFh
10
17h
6.58
Maximum Resolution (bits)
DS39933D-page 180
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
3. Make the CCP2 pin an output by clearing the
appropriate TRIS bit.
16.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
1. Set the PWM period by writing to the PR2
register.
5. Configure the CCP2 module for PWM operation.
2. Set the PWM duty cycle by writing to the
CCPR2L register and CCP2CON<5:4> bits.
TABLE 16-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
59
60
62
62
62
62
62
62
60
60
60
63
63
63
64
63
64
IPEN
—
—
CM
ADIF
RC1IF
RC1IE
RC1IP
TRISC5
TRISE5
TX1IF
TX1IE
TX1IP
TRISC4
TRISE4
TRISG4
SSPIF
SSPIE
SSPIP
TRISC3
TRISE3
TRISG3
—
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
ADIE
—
IPR1
—
ADIP
—
TRISC
TRISE
TRISG
TMR2
PR2
TRISC7
TRISE7
SPIOD
TRISC6
TRISE6
TRISC2 TRISC1 TRISC0
TRISE1 TRISE0
TRISG2 TRISG1 TRISG0
—
CCP2OD CCP1OD
Timer2 Register
Timer2 Period Register
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
CCPR1L Capture/Compare/PWM Register 1 Low Byte
CCPR1H Capture/Compare/PWM Register 1 High Byte
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCPR2L Capture/Compare/PWM Register 2 Low Byte
CCPR2H Capture/Compare/PWM Register 2 High Byte
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
2010 Microchip Technology Inc.
DS39933D-page 181
PIC18F87J90 FAMILY
NOTES:
DS39933D-page 182
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
The LCD driver module supports these features:
• Direct driving of LCD panel
17.0 LIQUID CRYSTAL DISPLAY
(LCD) DRIVER MODULE
• On-chip bias generator with dedicated charge
pump to support a range of fixed and variable bias
options
The Liquid Crystal Display (LCD) driver module
generates the timing control to drive a static or
multiplexed LCD panel. It also provides control of the
LCD pixel data. The module can drive panels of up to
• Up to four commons, with four Multiplexing modes
• Up to 48 (PIC18F8XJ90 devices) or 33
(PIC18F6XJ90 devices) segments
192 pixels (48 segments by
PIC18F8XJ90 devices and 132 pixels (33 segments by
4 commons) in PIC18F6XJ90 devices.
4
commons) in
• Three LCD clock sources with selectable prescaler,
with a fourth source available for use with the LCD
charge pump
A simplified block diagram of the module is shown in
Figure 17-1.
FIGURE 17-1:
LCD DRIVER MODULE BLOCK DIAGRAM
Data Bus
LCD DATA
24 x 8 (= 4 x 48)
LCDDATA23
LCDDATA22
192
to
48
.
.
.
48
SEG<47:0>
MUX
LCDDATA1
LCDDATA0
8
Bias
Voltage
To I/O Pins
Timing Control
4
LCDCON
LCDPS
LCDSEx
COM<3:0>
LCD Bias Generation
FOSC/4
T13CKI
INTRC Oscillator
INTOSC Oscillator
LCD Clock
LCD
Charge Pump
Source Select
2010 Microchip Technology Inc.
DS39933D-page 183
PIC18F87J90 FAMILY
The LCDPS register, shown in Register 17-2,
configures the LCD clock source prescaler and the type
of waveform: Type-A or Type-B. Details on these
features are provided in Section 17.2 “LCD Clock
Source”, Section 17.3 “LCD Bias Generation” and
Section 17.8 “LCD Waveform Generation”.
17.1 LCD Registers
The LCD driver module has 33 registers:
• LCD Control Register (LCDCON)
• LCD Phase Register (LCDPS)
• LCDREG Register (LCD Regulator Control)
The LCDREG register is described in Section 17.3
“LCD Bias Generation”.
• Six LCD Segment Enable Registers
(LCDSE5:LCDSE0)
The LCD Segment Enable registers (LCDSEx)
configure the functions of the port pins. Setting the
segment enable bit for a particular segment configures
that pin as an LCD driver. The prototype LCDSE register
is shown in Register 17-3. There are six LCDSE
registers (LCDSE5:LCDSE0) listed in Table 17-1.
• 24 LCD Data Registers
(LCDDATA23:LCDDATA0)
17.1.1
LCD CONTROL REGISTERS
The LCDCON register, shown in Register 17-1,
controls the overall operation of the module. Once the
module is configured, the LCDEN (LCDCON<7>) bit is
used to enable or disable the LCD module. The LCD
panel can also operate during Sleep by clearing the
SLPEN (LCDCON<6>) bit.
REGISTER 17-1: LCDCON: LCD CONTROL REGISTER
R/W-0
R/W-0
R/C-0
U-0
—
R/W-0
CS1
R/W-0
CS0
R/W-0
R/W-0
LCDEN
SLPEN
WERR
LMUX1
LMUX0
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
LCDEN: LCD Driver Enable bit
1= LCD driver module is enabled
0= LCD driver module is disabled
SLPEN: LCD Driver Enable in Sleep mode bit
1= LCD driver module is disabled in Sleep mode
0= LCD driver module is enabled in Sleep mode
WERR: LCD Write Failed Error bit
1= LCDDATAx register written while LCDPS<4> = 0(must be cleared in software)
0= No LCD write error
bit 4
Unimplemented: Read as ‘0’
bit 3-2
CS<1:0>: Clock Source Select bits
1x= INTRC (31 kHz)
01= T13CKI (Timer1)
00= System clock (FOSC/4)
bit 1-0
LMUX<1:0>: Commons Select bits
Maximum Number of Pixels:
LMUX<1:0>
Multiplex Type
Bias Type
PIC18F6XJ90
PIC18F8XJ90
00
01
10
11
Static (COM0)
33
66
48
96
Static
1/2 or 1/3
1/2 or 1/3
1/3
1/2 (COM1:COM0)
1/3 (COM2:COM0)
1/4 (COM3:COM0)
99
144
192
132
DS39933D-page 184
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 17-2: LCDPS: LCD PHASE REGISTER
R/W-0
WFT
R/W-0
R-0
R-0
WA
R/W-0
LP3
R/W-0
LP2
R/W-0
LP1
R/W-0
LP0
BIASMD
LCDA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
WFT: Waveform Type Select bit
1= Type-B waveform (phase changes on each frame boundary)
0= Type-A waveform (phase changes within each common type)
BIASMD: Bias Mode Select bit
When LMUX<1:0> = 00:
0= Static Bias mode (do not set this bit to ‘1’)
When LMUX<1:0> = 01 or 10:
1= 1/2 Bias mode
0= 1/3 Bias mode
When LMUX<1:0> = 11:
0= 1/3 Bias mode (do not set this bit to ‘1’)
bit 5
LCDA: LCD Active Status bit
1= LCD driver module is active
0= LCD driver module is inactive
bit 4
WA: LCD Write Allow Status bit
1= Write into the LCDDATAx registers is allowed
0= Write into the LCDDATAx registers is not allowed
bit 3-0
LP<3:0>: LCD Prescaler Select bits
1111= 1:16
1110= 1:15
1101= 1:14
1100= 1:13
1011= 1:12
1010= 1:11
1001= 1:10
1000= 1:9
0111= 1:8
0110= 1:7
0101= 1:6
0100= 1:5
0011= 1:4
0010= 1:3
0001= 1:2
0000= 1:1
2010 Microchip Technology Inc.
DS39933D-page 185
PIC18F87J90 FAMILY
REGISTER 17-3: LCDSEx: LCD SEGMENT ENABLE REGISTERS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SE(n)
SE(n + 7)
SE(n + 6)
SE(n + 5)
SE(n + 4)
SE(n + 3)
SE(n + 2)
SE(n + 1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-0
SEG(n + 7):SEG(n): Segment Enable bits
For LCDSE0: n = 0
For LCDSE1: n = 8
For LCDSE2: n = 16
For LCDSE3: n = 24
For LCDSE4: n = 32
For LCDSE5: n = 40
1= Segment function of the pin is enabled, digital I/O disabled
0= I/O function of the pin is enabled
TABLE 17-1: LCDSE REGISTERS AND ASSOCIATED SEGMENTS
Register
Segments
LCDSE0
LCDSE1
7:0
15:8
LCDSE2
23:16
31:24
39:32
47:40
LCDSE3
LCDSE4(1)
LCDSE5(2)
Note 1: LCDSE4<7:1> (SEG<39:33>) registers are not implemented in PIC18F6XJ90 devices.
2: LCDSE5 is not implemented in PIC18F6XJ90 devices.
DS39933D-page 186
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
Individual LCDDATA bits are named by the convention
“SxxCy”, with “xx” as the segment number and “y” as
the common number. The relationship is summarized
in Table 17-2. The prototype LCDDATA register is
shown in Register 17-4.
17.1.2
LCD DATA REGISTERS
Once the module is initialized for the LCD panel, the
individual bits of the LCDDATA23:LCDDATA0 registers
are cleared or set to represent a clear or dark pixel,
respectively. Specific sets of LCDDATA registers are
used with specific segments and common signals.
Each bit represents a unique combination of a specific
segment connected to a specific common.
Note:
In 64-pin devices, writing into the registers
LCDDATA5, LCDDATA11, LCDDATA17
and LCDDATA23, will not affect the status
of any pixels.
REGISTER 17-4: LCDDATAx: LCD DATA REGISTERS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n + 3)Cy
R/W-0
R/W-0
R/W-0
S(n + 7)Cy
S(n + 6)Cy
S(n + 5)Cy
S(n + 4)Cy
S(n + 2)Cy
S(n + 1)Cy
S(n)Cy
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
S(n + 7)Cy:S(n)Cy: Pixel On bits
For LCDDATA0 through LCDDATA5: n = (8x), y = 0
For LCDDATA6 through LCDDATA11: n = (8(x – 6)), y = 1
For LCDDATA12 through LCDDATA17: n = (8(x – 12)), y = 2
For LCDDATA18 through LCDDATA23: n = (8(x – 18)), y = 3
1= Pixel on (dark)
0= Pixel off (clear)
TABLE 17-2: LCDDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS
COM Lines
Segments
0
1
2
3
LCDDATA0
S00C0:S07C0
LCDDATA1
LCDDATA6
S00C1:S07C1
LCDDATA7
LCDDATA12
S00C2:S07C2
LCDDATA13
LCDDATA18
S00C3:S07C3
LCDDATA19
0 through 7
8 through 15
16 through 23
24 through 31
32 through 39
40 through 47
S08C0:S15C0
LCDDATA2
S08C1:S15C1
LCDDATA8
S08C2:S15C2
LCDDATA14
S08C0:S15C3
LCDDATA20
S16C0:S23C0
LCDDATA3
S16C1:S23C1
LCDDATA9
S16C2:S23C2
LCDDATA15
S16C3:S23C3
LCDDATA21
S24C0:S31C0
LCDDATA4(1)
S32C0:S39C0
LCDDATA5(2)
S40C0:S47C0
S24C1:S31C1
LCDDATA10(1)
S32C1:S39C1
LCDDATA11(2)
S40C1:S47C1
S24C2:S31C2
LCDDATA16(1)
S32C2:S39C2
LCDDATA17(2)
S40C2:S47C2
S24C3:S31C3
LCDDATA22(1)
S32C3:S39C3
LCDDATA23(2)
S40C3:S47C3
Note 1: Bits<7:1> of these registers are not implemented in PIC18F6XJ90 devices. Bit 0 of these registers
(SEG32Cy) is always implemented.
2: These registers are not implemented on PIC18F6XJ90 devices.
2010 Microchip Technology Inc.
DS39933D-page 187
PIC18F87J90 FAMILY
The charge pump clock can use either the Timer1
oscillator or the INTRC source, as well as the 8 MHz
INTOSC source (after being divided by 256 by a
prescaler). The charge pump clock source is configured
using the CKSEL<1:0> bits (LCDREG<1:0>).
17.2
LCD Clock Source
The LCD driver module generates its internal clock
from 3 possible sources:
• System clock (FOSC/4)
• Timer1 oscillator
• INTRC source
17.2.2
CLOCK SOURCE
CONSIDERATIONS
The LCD clock generator uses
a configurable
When using the system clock as the LCD clock source,
it is assumed that the system clock frequency is a nom-
inal 32 MHz (for a FOSC/4 frequency of 8 MHz).
Because the prescaler option for the FOSC/4 clock
selection is fixed at divide-by-8192, system clock
speeds that differ from 32 MHz will produce frame
frequencies and refresh rates different than discussed
in this chapter. The user will need to keep this in mind
when designing the display application.
divide-by-32/divide-by-8192 postscaler to produce a
baseline frequency of about 1 kHz nominal, regardless
of the source selected. The clock source selection and
the postscaler configuration are determined by the
Clock Source Select bits, CS<1:0> (LCDCON<3:2>).
An additional programmable prescaler is used to derive
the LCD frame frequency from the 1 kHz baseline. The
prescaler is configured using the LP<3:0> bits
(LCDPS<3:0>) for any one of 16 options, ranging from
1:1 to 1:16.
The Timer1 and INTRC sources can be used as LCD
clock sources when the device is in Sleep mode. To
use the Timer1 oscillator, it is necessary to set the
T1OSCEN bit (T1CON<3>). Selecting either Timer1 or
INTRC as the LCD clock source will not automatically
activate these sources.
Proper timing for waveform generation is set by the
LMUX<1:0> bits (LCDCON<1:0>). These bits
determine which Commons Multiplexing mode is to be
used and divide down the LCD clock source as
required. They also determine the configuration of the
ring counter that is used to switch the LCD commons
on or off.
Similarly, selecting the INTOSC as the charge pump
clock source will not turn the oscillator on. To use
INTOSC, it must be selected as the system clock
source by using the FOSC2 Configuration bit.
17.2.1
LCD VOLTAGE REGULATOR
CLOCK SOURCE
If Timer1 is used as a clock source for the device, either
as an LCD clock source or for any other purpose, LCD
segment 32 become unavailable.
In addition to the clock source for LCD timing, a
separate 31 kHz nominal clock is required for the LCD
charge pump. This is provided from a distinct branch of
the LCD clock source.
FIGURE 17-2:
LCD CLOCK GENERATION
2
LCDCON<3:2>
LCDPS<3:0>
4
÷4
÷2
00
01
10
11
00
01
System Clock (FOSC/4)
Timer1 Oscillator
COM0
1:1 to 1:16
Programmable
Prescaler
÷32
or
÷1, 2, 3, 4
COM1
COM2
COM3
Ring Counter
÷8192
Internal 31 kHz Source
1x
2
LCDCON<1:0>
LCDREG<1:0>
2
11
10
01
31 kHz Clock
to LCD Charge Pump
INTOSC 8 MHz Source
÷256
DS39933D-page 188
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
17.3.2
LCD VOLTAGE REGULATOR
17.3 LCD Bias Generation
The purpose of the LCD regulator is to provide proper
bias voltage and good contrast for the LCD, regardless
of VDD levels. This module contains a charge pump and
internal voltage reference. The regulator can be config-
ured by using external components to boost bias
voltage above VDD. It can also operate a display at a
constant voltage below VDD. The regulator can also be
selectively disabled to allow bias voltages to be
generated by an external resistor network.
The LCD driver module is capable of generating the
required bias voltages for LCD operation with a mini-
mum of external components. This includes the ability
to generate the different voltage levels required by the
different bias types that are required by the LCD. The
driver module can also provide bias voltages, both
above and below microcontroller VDD, through the use
of an on-chip LCD voltage regulator.
17.3.1
LCD BIAS TYPES
The LCD regulator is controlled through the LCDREG
register (Register 17-5). It is enabled or disabled using
the CKSEL<1:0> bits, while the charge pump can be
selectively enabled using the CPEN bit. When the reg-
ulator is enabled, the MODE13 bit is used to select the
bias type. The peak LCD bias voltage, measured as a
difference between the potentials of LCDBIAS3 and
LCDBIAS0, is configured with the BIAS bits.
PIC18F87J90 family devices support three bias types
based on the waveforms generated to control
segments and commons:
• Static (two discrete levels)
• 1/2 Bias (three discrete levels
• 1/3 Bias (four discrete levels)
The use of different waveforms in driving the LCD is dis-
cussed in more detail in Section 17.8 “LCD Waveform
Generation”.
REGISTER 17-5: LCDREG: VOLTAGE REGULATOR CONTROL REGISTER
U-0
—
RW-0
RW-1
RW-1
RW-1
RW-1
RW-0
RW-0
CPEN
BIAS2
BIAS1
BIAS0
MODE13
CKSEL1
CKSEL0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
CPEN: LCD Charge Pump Enable bit
1= Charge pump enabled; highest LCD bias voltage is 3.6V
0= Charge pump disabled; highest LCD bias voltage is AVDD
bit 5-3
BIAS<2:0>: Regulator Voltage Output Control bits
111= 3.60V peak (offset on LCDBIAS0 of 0V)
110= 3.47V peak (offset on LCDBIAS0 of 0.13V)
101= 3.34V peak (offset on LCDBIAS0 of 0.26V)
100= 3.21V peak (offset on LCDBIAS0 of 0.39V)
011= 3.08V peak (offset on LCDBIAS0 of 0.52V)
010= 2.95V peak (offset on LCDBIAS0 of 0.65V)
001= 2.82V peak (offset on LCDBIAS0 of 0.78V)
000= 2.69V peak (offset on LCDBIAS0 of 0.91V)
bit 2
MODE13: 1/3 LCD Bias Enable bit
1= Regulator output supports 1/3 LCD Bias mode
0= Regulator output supports static LCD Bias mode
bit 1-0
CKSEL<1:0>: Regulator Clock Source Select bits
11= INTRC
10= INTOSC 8 MHz source
01= Timer1 oscillator
00= LCD regulator disabled
2010 Microchip Technology Inc.
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M0 is enabled by selecting a valid regulator clock
source (CKSEL<1:0> set to any value except ‘00’) and
setting the CPEN bit. If Static Bias type is required, the
MODE13 bit must be cleared.
17.3.3
BIAS CONFIGURATIONS
PIC18F87J90 family devices have four distinct circuit
configurations for LCD bias generation:
• M0: Regulator with Boost
17.3.3.2
M1 (Regulator without Boost)
• M1: Regulator without Boost
• M2: Resistor Ladder with Software Contrast
• M3: Resistor Ladder with Hardware Contrast
M1 operation is similar to M0, but does not use the LCD
charge pump. It can provide VBIAS up to the voltage
level supplied directly to LCDBIAS3. It can be used in
cases where VDD for the application is expected to
never drop below a level that can provide adequate
contrast for the LCD. The connection of external com-
ponents is very similar to M0, except that LCDBIAS3
must be tied directly to VDD (Figure 17-3).
17.3.3.1
M0 (Regulator with Boost)
In M0 operation, the LCD charge pump feature is
enabled. This allows the regulator to generate voltages
up to +3.6V to the LCD (as measured at LCDBIAS3).
M0 uses a flyback capacitor connected between
VLCAP1 and VLCAP2, as well as filter capacitors on
LCDBIAS0 through LCDBIAS3, to obtain the required
voltage boost (Figure 17-3). The output voltage (VBIAS)
is the difference of potential between LCDBIAS3 and
LCDBIAS0. It is set by the BIAS<2:0> bits which adjust
the offset between LCDBIAS0 and VSS. The flyback
capacitor (CFLY) acts as a charge storage element for
large LCD loads. This mode is useful in those cases
where the voltage requirements of the LCD are higher
than the microcontroller’s VDD. It also permits software
control of the display’s contrast, by adjustment of bias
voltage, by changing the value of the BIAS bits.
Note:
When the device is put to Sleep while oper-
ating in mode M0 or M1, make sure that the
bias capacitors are fully discharged to get
the lowest Sleep current.
The BIAS<2:0> bits can still be used to adjust contrast
in software by changing VBIAS. As with M0, changing
these bits changes the offset between LCDBIAS0 and
VSS. In M1, this is reflected in the change between the
LCDBIAS0 and the voltage tied to LCDBIAS3. Thus, if
VDD should change, VBIAS will also change; where in
M0, the level of VBIAS is constant.
Like M0, M1 supports Static and 1/3 Bias types.
Generation of the voltage levels for 1/3 Bias is handled
automatically but must be configured in software.
M0 supports Static and 1/3 Bias types. Generation of
the voltage levels for 1/3 Bias is handled automatically,
but must be configured in software.
M1 is enabled by selecting a valid regulator clock
source (CKSEL<1:0> set to any value except ‘00’) and
clearing the CPEN bit. If 1/3 Bias type is required, the
MODE13 bit should also be set.
FIGURE 17-3:
LCD REGULATOR CONNECTIONS FOR M0 AND M1 CONFIGURATIONS
VDD
VDD
PIC18F87J90
AVDD
VLCAP1
CFLY
0.47 F
CFLY
0.47 F
(1)
(1)
(1)
VLCAP2
VDD
LCDBIAS3
C3
0.47 F
LCDBIAS2
LCDBIAS1
LCDBIAS0
C2
0.47 F
C2
0.47 F
(1)
(1)
(1)
(1)
(1)
(1)
C1
0.47 F
C1
0.47 F
C0
0.47 F
C0
0.47 F
Mode 0 (VBIAS up to 3.6V)
Mode 1 (VBIAS VDD)
Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer
based on the actual LCD specifications.
DS39933D-page 190
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
configuration of the resistor ladder. Most applications
using M2 will use a 1/3 or 1/2 Bias type. While Static
Bias can also be used, it offers extremely limited
contrast range and additional current consumption
over other bias generation modes.
17.3.3.3
M2 (Resistor Ladder with
Software Contrast)
M2 operation also uses the LCD regulator but disables
the charge pump. The regulator’s internal voltage refer-
ence remains active as a way to regulate contrast. It is
used in cases where the current requirements of the
LCD exceed the capacity of the regulator’s charge
pump.
Like M1, the LCDBIAS bits can be used to control con-
trast, limited by the level of VDD supplied to the device.
Also, since there is no capacitor required across
VLCAP1 and VLCAP2, these pins are available as digital
I/O ports, RG2 and RG3.
In this configuration, the LCD bias voltage levels are
created by an external resistor voltage divider,
connected across LCDBIAS0 through LCDBIAS3, with
the top of the divider tied to VDD (Figure 17-4). The
potential at the bottom of the ladder is determined by
the LCD regulator’s voltage reference, tied internally to
LCDBIAS0. The bias type is determined by the volt-
ages on the LCDBIAS pins, which are controlled by the
M2 is selected by clearing the CKSEL<1:0> bits and
setting the CPEN bit.
FIGURE 17-4:
RESISTOR LADDER CONNECTIONS FOR M2 CONFIGURATION
PIC18F87J90
VDD
AVDD
LCDBIAS3
(1)
(1)
(1)
(1)
10 k
10 k
10 k
10 k
10 k
LCDBIAS2
LCDBIAS1
(1)
LCDBIAS0
1/2 Bias
1/3 Bias
Bias Type
Bias Level at Pin
1/2 Bias
1/3 Bias
LCDBIAS0
LCDBIAS1
LCDBIAS2
LCDBIAS3
(Internal Low Reference Voltage)
1/2 VBIAS
(Internal Low Reference Voltage)
1/3 VBIAS
1/2 VBIAS
2/3 VBIAS
VBIAS (up to AVDD)
VBIAS (up to AVDD)
Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer
based on the actual LCD specifications.
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
Depending on the bias type required, resistors are
connected between some or all of the pins. A potentio-
meter can also be connected between LCDBIAS3 and
VDD to allow for hardware controlled contrast
adjustment.
17.3.3.4
M3 (Hardware Contrast)
In M3, the LCD regulator is completely disabled. Like
M2, LCD bias levels are tied to AVDD and are generated
using an external divider. The difference is that the inter-
nal voltage reference is also disabled and the bottom of
the ladder is tied to ground (VSS); see Figure 17-5. The
value of the resistors, and the difference between VSS
and VDD, determine the contrast range; no software
adjustment is possible. This configuration is also used
where the LCD’s current requirements exceed the
capacity of the charge pump and software contrast
control is not needed.
M3 is selected by clearing the CKSEL<1:0> and CPEN
bits.
FIGURE 17-5:
RESISTOR LADDER CONNECTIONS FOR M3 CONFIGURATION
PIC18F87J90
VDD
AVDD
(2)
LCDBIAS3
(1)
(1)
(1)
(1)
10 k
10 k
10 k
10 k
10 k
LCDBIAS2
LCDBIAS1
(1)
LCDBIAS0
Static Bias
Static
1/2 Bias
1/3 Bias
Bias Type
1/2 Bias
Bias Level at Pin
1/3 Bias
LCDBIAS0
LCDBIAS1
LCDBIAS2
LCDBIAS3
AVSS
AVSS
AVDD
AVDD
AVSS
1/2 AVDD
1/2 AVDD
AVDD
AVSS
1/3 AVDD
2/3 AVDD
AVDD
Note 1: These values are provided for design guidance only; they should be optimized for the application by the
designer based on the actual LCD specifications.
2: A potentiometer for manual contrast adjustment is optional; it may be omitted entirely.
DS39933D-page 192
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17.3.4
DESIGN CONSIDERATIONS FOR
THE LCD CHARGE PUMP
17.4 LCD Multiplex Types
The LCD driver module can be configured into four
multiplex types:
When designing applications that use the LCD regula-
tor with the charge pump enabled, users must always
consider both the dynamic current and RMS (static)
current requirements of the display, and what the
charge pump can deliver. Both dynamic and static
current can be determined by Equation 17-1:
• Static (only COM0 used)
• 1/2 Multiplex (COM0 and COM1 are used)
• 1/3 Multiplex (COM0, COM1 and COM2 are used)
• 1/4 Multiplex (all COM0, COM1, COM2 and COM3
are used)
EQUATION 17-1:
The number of active commons used is configured by
the LMUX<1:0> bits (LCDCON<1:0>), which deter-
mines the function of the PORTE<6:4> pins (see
Table 17-3 for details). If the pin is configured as a COM
drive, the port I/O function is disabled and the TRIS
setting of that pin is overridden.
dV
I = C x
dT
For dynamic current, C is the value of the capacitors
attached to LCDBIAS3 and LCDBIAS2. The variable,
dV, is the voltage drop allowed on C2 and C3 during a
voltage switch on the LCD display, and dT is the dura-
tion of the transient current after a clock pulse occurs.
For practical design purposes, these will be assumed
to be 0.047 F for C, 0.1V for dV and 1 s for dT. This
yields a dynamic current of 4.7 mA for 1 s.
Note:
On a Power-on Reset, the LMUX<1:0>
bits are ‘00’.
TABLE 17-3: PORTE<6:4> FUNCTION
LMUX<1:0> PORTE<6> PORTE<5> PORTE<4>
00
01
10
11
Digital I/O
Digital I/O
Digital I/O
Digital I/O
RMS current is determined by the value of CFLY for C,
the voltage across VLCAP1 and VLCAP2 for dV and the
regulator clock period (TPER) for dT. Assuming a CFLY
value of 0.047 F, a value of 1.02V across CFLY and
TPER of 30 s, the maximum theoretical static current
will be 1.8 mA. Since the charge pump must charge
five capacitors, the maximum current becomes 360 A.
For a real-world assumption of 50% efficiency, this
yields a practical current of 180 A.
Digital I/O COM1 Driver
Digital I/O COM2 Driver COM1 Driver
COM3 Driver COM2 Driver COM1 Driver
17.5 Segment Enables
The LCDSEx registers are used to select the pin
function for each segment pin. Setting a bit configures
the corresponding pin to function as a segment driver.
LCDSEx registers do not override the TRIS bit settings,
so the TRIS bits must be configured as inputs for that
pin.
Users should compare the calculated current capacity
against the requirements of the LCD. While dV and dT
are relatively fixed by device design, the values of CFLY
and the capacitors on the LCDBIAS pins can be
changed to increase or decrease current. As always,
any changes should be evaluated in the actual circuit
for their impact on the application.
Note:
On a Power-on Reset, these pins are
configured as digital I/O.
17.6 Pixel Control
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Table 17-2 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals. Any LCD pixel location not being
used for display can be used as general purpose RAM.
2010 Microchip Technology Inc.
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17.7 LCD Frame Frequency
17.8 LCD Waveform Generation
The rate at which the COM and SEG outputs change is
called the LCD frame frequency. Frame frequency is
set by the LP<3:0> bits (LCDPS<3:0>) and is also
affected by the Multiplex mode being used. The rela-
tionship between the Multiplex mode, LP bits setting
and frame rate is shown in Table 17-4 and Table 17-5.
LCD waveform generation is based on the principle
that the net AC voltage across the dark pixel should be
maximized and the net AC voltage across the clear
pixel should be minimized. The net DC voltage across
any pixel should be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data. The
pixel signal (COM-SEG) will have no DC component
and it can take only one of the two rms values. The
higher rms value will create a dark pixel and a lower
rms value will create a clear pixel.
TABLE 17-4: FRAME FREQUENCY
FORMULAS
Multiplex
Frame Frequency (Hz)
Mode
As the number of commons increases, the delta
between the two rms values decreases. The delta
represents the maximum contrast that the display can
have.
Static
1/2
Clock Source/(4 x 1 x (LP<3:0> + 1))
Clock Source/(2 x 2 x (LP<3:0> + 1))
Clock Source/(1 x 3 x (LP<3:0> + 1))
Clock Source/(1 x 4 x (LP<3:0> + 1))
1/3
1/4
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In the Type-A waveform, the
phase changes within each common type, whereas in
the Type-B waveform, the phase changes on each
frame boundary. Thus, the Type-A waveform maintains
0 VDC over a single frame, whereas the Type-B
waveform takes two frames.
TABLE 17-5: APPROXIMATE FRAME
FREQUENCY (IN Hz) FOR LP
PRESCALER SETTINGS
Multiplex Mode
LP<3:0>
Static
1/2
1/3
1/4
Note 1: If the power-managed Sleep mode is
invoked while the LCD Sleep bit (SLPEN)
is set (LCDCON<6> is ‘1’), take care to
execute Sleep only when the VDC on all
the pixels is ‘0’.
1
2
3
4
5
6
7
125
83
62
50
42
36
31
125
83
62
50
42
36
31
167
111
83
125
83
62
50
42
36
31
67
2: When the LCD clock source is the system
clock, the LCD module will go to Sleep if
the microcontroller goes into Sleep mode,
regardless of the setting of the SLPEN bit.
Thus, always take care to see that the VDC
on all pixels is ‘0’ whenever Sleep mode is
invoked.
56
48
42
Figure 17-6 through Figure 17-16 provide waveforms
for static, half multiplex, one-third multiplex and quarter
multiplex drives for Type-A and Type-B waveforms.
DS39933D-page 194
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FIGURE 17-6:
TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE
V
V
1
COM0
0
COM0
V
1
SEG0
V
0
V
1
SEG1
V
0
V
V
1
COM0-SEG0
0
-V
1
COM0-SEG1
V
0
1 Frame
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FIGURE 17-7:
TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V
V
V
2
1
0
COM0
COM1
COM1
COM0
V
V
V
2
1
0
V
V
V
2
1
0
SEG0
V
V
V
2
1
0
SEG1
V
V
V
2
1
0
COM0-SEG0
-V
-V
1
2
V
V
V
2
1
0
COM0-SEG1
-V
-V
1
2
1 Frame
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FIGURE 17-8:
TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V
V
V
2
1
0
COM0
COM1
COM0
V
V
V
2
1
0
COM1
SEG0
V
V
V
2
1
0
V
V
V
2
1
0
SEG1
V
V
V
2
1
0
COM0-SEG0
-V
-V
1
2
V
V
V
2
1
0
COM0-SEG1
-V
-V
1
2
2 Frames
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FIGURE 17-9:
TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V
V
V
V
V
V
V
V
V
V
V
V
3
2
1
0
3
2
1
0
3
2
1
0
COM0
COM1
COM0
COM1
SEG0
SEG1
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
COM0-SEG0
-V
-V
-V
1
2
3
V
V
V
V
3
2
1
0
COM0-SEG1
-V
-V
-V
1
2
3
1 Frame
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FIGURE 17-10:
TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3
2
1
0
3
2
1
0
3
2
1
0
COM0
COM1
COM0
COM1
SEG0
3
2
1
0
SEG1
V
V
V
V
3
2
1
0
COM0-SEG0
-V
-V
-V
1
2
3
V
V
V
V
3
2
1
0
COM0-SEG1
-V
-V
-V
1
2
3
2 Frames
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FIGURE 17-11:
TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V
V
V
2
1
0
COM0
COM2
V
V
V
2
1
0
COM1
COM2
COM1
COM0
V
V
V
2
1
0
V
V
V
2
1
0
SEG0
SEG2
V
V
V
2
1
0
SEG1
V
V
V
2
1
0
COM0-SEG0
-V
-V
1
2
V
V
V
2
1
0
COM0-SEG1
-V
-V
1
2
1 Frame
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FIGURE 17-12:
TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V
V
V
2
1
0
COM0
COM1
COM2
SEG0
SEG1
COM2
V
V
V
2
1
0
COM1
COM0
V
V
V
2
1
0
V
V
V
2
1
0
V
V
V
2
1
0
V
V
V
2
1
0
COM0-SEG0
-V
-V
1
2
V
V
V
2
1
0
COM0-SEG1
-V
-V
1
2
2 Frames
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FIGURE 17-13:
TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V
V
V
V
V
V
V
V
3
2
1
0
3
2
1
0
COM0
COM1
COM2
COM2
COM1
COM0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
SEG0
SEG2
SEG1
COM0-SEG0
-V
-V
-V
1
2
3
V
V
V
V
3
2
1
0
COM0-SEG1
-V
-V
-V
1
2
3
1 Frame
DS39933D-page 202
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 17-14:
TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V
V
V
V
V
V
V
V
3
2
1
0
3
2
1
0
COM0
COM1
COM2
SEG0
SEG1
COM2
COM1
COM0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
COM0-SEG0
-V
-V
-V
1
2
3
V
V
V
V
3
2
1
0
COM0-SEG1
-V
-V
-V
1
2
3
2 Frames
2010 Microchip Technology Inc.
DS39933D-page 203
PIC18F87J90 FAMILY
FIGURE 17-15:
TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
COM3
COM2
V
V
V
V
3
2
1
0
COM0
COM1
V
V
V
V
3
2
1
0
COM1
COM0
V
V
V
V
3
2
1
0
COM2
COM3
SEG0
SEG1
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
-V
-V
-V
3
2
1
0
COM0-SEG0
COM0-SEG1
1
2
3
V
V
V
V
-V
-V
-V
3
2
1
0
1
2
3
1 Frame
DS39933D-page 204
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 17-16:
TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
COM3
COM2
V
V
V
V
3
2
1
0
COM0
COM1
V
V
V
V
3
2
1
0
COM1
COM0
V
V
V
V
3
2
1
0
COM2
COM3
SEG0
SEG1
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
-V
-V
-V
3
2
1
0
COM0-SEG0
COM0-SEG1
1
2
3
V
V
V
V
-V
-V
-V
3
2
1
0
1
2
3
2 Frames
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
When the LCD driver is running with Type-B wave-
forms, and the LMUX<1:0> bits are not equal to ‘00’,
there are some additional issues that must be
addressed. Since the DC voltage on the pixel takes two
frames to maintain zero volts, the pixel data must not
change between subsequent frames. If the pixel data
was allowed to change, the waveform for the odd
frames would not necessarily be the complement of the
waveform generated in the even frames and a DC
component would be introduced into the panel. There-
fore, when using Type-B waveforms, the user must
synchronize the LCD pixel updates to occur within a
subframe after the frame interrupt.
17.9 LCD Interrupts
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame. Writing pixel data at the frame
boundary allows a visually crisp transition of the image.
This interrupt can also be used to synchronize external
events to the LCD. For example, the interface to an
external segment driver can be synchronized for a
segment data update to the LCD frame.
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(TFINT), as shown in Figure 17-17. The LCD controller
will begin to access data for the next frame within the
interval from the interrupt to when the controller begins
to access data after the interrupt (TFWR). New data
must be written within TFWR, as this is when the LCD
controller will begin to access the data for the next
frame.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If
the user attempts to write when the write is disabled,
the WERR (LCDCON<5>) bit is set.
Note: The interrupt is not generated when the
Type-A waveform is selected and when the
Type-B with no multiplex (static) is
selected.
FIGURE 17-17:
EXAMPLE WAVEFORMS AND INTERRUPT TIMING
IN QUARTER DUTY CYCLE DRIVE
LCD
Interrupt
Occurs
Controller Accesses
Next Frame Data
V
V
V
V
3
2
1
0
COM0
COM1
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
COM2
COM3
V
V
V
V
3
2
1
0
2 Frames
TFINT
TFWR
Frame
Frame
Frame
Boundary
Boundary
Boundary
TFWR = TFRAME/2 * (LMUX<1:0> + 1) + TCY/2
TFINT = (TFWR/2 – (2 TCY + 40 ns)) Minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)
(TFWR/2 – (1 TCY + 40 ns)) Maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)
DS39933D-page 206
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
internal oscillators (either INTRC or INTOSC as the
default system clock). While in Sleep, the LCD data
cannot be changed. The LCD module current
consumption will not decrease in this mode; however,
the overall consumption of the device will be lower due
to shut down of the core and other peripheral functions.
17.10 Operation During Sleep
The LCD module can operate during Sleep. The selec-
tion is controlled by the SLPEN bit (LCDCON<6>).
Setting the SLPEN bit allows the LCD module to go to
Sleep. Clearing the SLPEN bit allows the module to
continue to operate during Sleep.
If the system clock is selected, and the module is not
configured for Sleep operation, the module will ignore
the SLPEN bit and stop operation immediately. The
minimum LCD voltage will then be driven onto the
segments and commons
If a SLEEPinstruction is executed and SLPEN = 1, the
LCD module will cease all functions and go into a very
low-current consumption mode. The module will stop
operation immediately and drive the minimum LCD
voltage on both segment and common lines.
Figure 17-18 shows this operation.
17.10.1 USING THE LCD REGULATOR
DURING SLEEP
To ensure that no DC component is introduced on the
panel, the SLEEPinstruction should be executed imme-
diately after a LCD frame boundary. The LCD interrupt
can be used to determine the frame boundary. See
Section 17.9 “LCD Interrupts” for the formulas to
calculate the delay.
Applications that use the LCD regulator for bias
generation may not achieve the same degree of power
reductions in Sleep mode when compared to applica-
tions using Mode 3 (resistor ladder) biasing. This is
particularly true with Mode 0 operation, where the
charge pump is active.
If a SLEEPinstruction is executed and SLPEN = 0, the
module will continue to display the current contents of
the LCDDATA registers. To allow the module to
continue operation while in Sleep, the clock source
must be either the Timer1 oscillator or one of the
If Modes 0, 1 or 2 are used for bias generation,
software contrast control will not be available.
FIGURE 17-18:
SLEEP ENTRY/EXIT WHEN SLPEN = 1OR CS<1:0> = 00
V
V
V
V
3
2
1
0
COM0
V
V
V
V
3
2
1
0
COM1
V
V
V
V
3
2
1
0
COM2
SEG0
V
V
V
V
3
2
1
0
2 Frames
Wake-up
SLEEPInstruction Execution
2010 Microchip Technology Inc.
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6. Configure the LCD regulator:
17.11 Configuring the LCD Module
a) If M2 or M3 bias configuration is to be used,
turn off the regulator by setting
CKSEL<1:0> (LCDREG<1:0>) to ‘00’. Set
or clear the CPEN bit (LCDREG<6>) to
select Mode 2 or Mode 3, as appropriate.
The following is the sequence of steps to configure the
LCD module.
1. Select the frame clock prescale using bits,
LP<3:0> (LCDPS<3:0>).
2. Configure the appropriate pins to function as
segment drivers using the LCDSEx registers.
b) If M0 or M1 bias generation is to be used:
• Set the VBIAS level using the BIAS<2:0>
bits (LCDREG<5:3>).
3. Configure the appropriate pins as inputs using
the TRISx registers.
• Set or clear the CPEN bit to enable or
disable the charge pump.
4. Configure the LCD module for the following
using the LCDCON register:
• Set or clear the MODE13 bit
(LCDREG<2>) to select the Bias mode.
•
•
•
Multiplex and Bias mode (LMUX<1:0>)
Timing source (CS<1:0>)
• Select a regulator clock source using the
CKSEL<1:0> bits.
Sleep mode (SLPEN)
7. Clear LCD Interrupt Flag, LCDIF (PIR3<6>),
and if desired, enable the interrupt by setting the
LCDIE bit (PIE3<6>).
5. Write initial values to pixel data registers,
LCDDATA0 through LCDDATA23.
8. Enable the LCD module by setting the LCDEN
bit (LCDCON<7>).
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2010 Microchip Technology Inc.
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TABLE 17-6: REGISTERS ASSOCIATED WITH LCD OPERATION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
RI
RBIE
TMR0IF
INT0IF
RBIF
59
62
62
62
60
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
61
61
61
61
61
61
61
61
61
61
61
61
61
60
PIR3
PIE3
—
—
LCDIF
LCDIE
LCDIP
—
RC2IF
RC2IE
RC2IP
CM
CTMUIF CCP2IF
CTMUIE CCP2IE
CTMUIP CCP2IP
CCP1IF
RTCCIF
CCP1IE RTCCIE
CCP1IP RTCCIP
IPR3
—
RCON
LCDDATA23(1) S47C3
IPEN
TO
PD
POR
BOR
S40C3
S32C3
S24C3
S16C3
S08C3
S00C3
S40C2
S32C2
S24C2
S16C2
S08C2
S00C2
S40C1
S32C1
S24C1
S16C1
S08C1
S00C1
S40C0
S32C0
S24C0
S16C0
S08C0
S00C0
SE40
S46C3
S45C3
S44C3
S43C3
S42C3
S41C3
LCDDATA22
LCDDATA21
LCDDATA20
LCDDATA19
LCDDATA18
S39C3(1) S38C3(1) S37C3(1) S36C3(1) S35C3(1) S34C3(1) S33C3(1)
S31C3
S23C3
S15C3
S07C3
S30C3
S22C3
S14C3
S06C3
S46C2
S29C3
S21C3
S13C3
S05C3
S45C2
S28C3
S20C3
S12C3
S04C3
S44C2
S27C3
S19C3
S11C3
S03C3
S43C2
S26C3
S18C3
S10C3
S02C3
S42C2
S25C3
S17C3
S09C3
S01C3
S41C2
LCDDATA17(1) S47C2
LCDDATA16
LCDDATA15
LCDDATA14
LCDDATA13
LCDDATA12
S39C2(1) S38C2(1) S37C2(1) S36C2(1) S35C2(1) S34C2(1) S33C2(1)
S31C2
S23C2
S15C2
S07C2
S30C2
S22C2
S14C2
S06C2
S46C1
S29C2
S21C2
S13C2
S05C2
S45C1
S28C2
S20C2
S12C2
S04C2
S44C1
S27C2
S19C2
S11C2
S03C2
S43C1
S26C2
S18C2
S10C2
S02C2
S42C1
S25C2
S17C2
S09C2
S01C2
S41C1
LCDDATA11(1) S47C1
LCDDATA10
LCDDATA9
LCDDATA8
LCDDATA7
LCDDATA6
LCDDATA5(1)
LCDDATA4
LCDDATA3
LCDDATA2
LCDDATA1
LCDDATA0
LCDSE5(1)
LCDSE4
S39C1(1) S38C1(1) S37C1(1) S36C1(1) S35C1(1) S34C1(1) S33C1(1)
S31C1
S23C1
S15C1
S07C1
S47C0
S30C1
S22C1
S14C1
S06C1
S46C0
S29C1
S21C1
S13C1
S05C1
S45C0
S28C1
S20C1
S12C1
S04C1
S44C0
S27C1
S19C1
S11C1
S03C1
S43C0
S26C1
S18C1
S10C1
S02C1
S42C0
S25C1
S17C1
S09C1
S01C1
S41C0
S39C0(1) S38C0(1) S37C0(1) S36C0(1) S35C0(1) S34C0(1) S33C0(1)
S31C0
S23C0
S15C0
S07C0
SE47
SE39(1)
SE31
SE23
SE15
SE07
LCDEN
WFT
S30C0
S22C0
S14C0
S06C0
SE46
S29C0
S21C0
S13C0
S05C0
SE45
S28C0
S20C0
S12C0
S04C0
SE44
SE36(1)
SE28
SE20
SE12
SE04
—
S27C0
S19C0
S11C0
S03C0
SE43
SE35(1)
SE27
SE19
SE11
S26C0
S18C0
S10C0
S02C0
SE42
SE34(1)
SE26
SE18
SE10
SE02
CS0
S25C0
S17C0
S09C0
S01C0
SE41
SE38(1)
SE37(1)
SE33(1)
SE32
LCDSE3
SE30
SE29
SE25
SE24
LCDSE2
SE22
SE21
SE17
SE16
LCDSE1
SE14
SE13
SE09
SE08
LCDSE0
SE06
SE05
SE03
CS1
SE01
SE00
LCDCON
LCDPS
SLPEN
BIASMD
CPEN
WERR
LCDA
BIAS2
LMUX1
LP1
LMUX0
LP0
WA
LP3
LP2
LCDREG
—
BIAS1
BIAS0
MODE13 CKSEL1 CKSEL0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for LCD operation.
Note 1: These registers or individual bits are unimplemented on PIC18F6XJ90 devices.
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
NOTES:
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18.3 SPI Mode
18.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
18.1 Master SSP (MSSP) Module
Overview
• Serial Data Out (SDO) – RC5/SDO/SEG12
• Serial Data In (SDI) – RC4/SDI/SDA/SEG16
• Serial Clock (SCK) – RC3/SCK/SCL/SEG17
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D Converters, etc. The MSSP
module can operate in one of two modes:
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RF7/AN5/SS/SEG25
Figure 18-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
FIGURE 18-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
• Master mode
• Multi-Master mode
• Slave mode
Read
Write
SSPBUF reg
18.2 Control Registers
SDI
Each MSSP module has three associated control
registers. These include a status register (SSPSTAT)
and two control registers (SSPCON1 and SSPCON2).
The use of these registers and their individual bits differ
significantly depending on whether the MSSP module
is operated in SPI or I2C mode.
SSPSR reg
Shift
Clock
bit 0
SDO
Additional details are provided under the individual
sections.
SS
Control
Enable
SS
Edge
Select
2
Clock Select
SSPM<3:0>
SMP:CKE
4
TMR2 Output
(
)
2
2
SCK
Edge
Select
TOSC
Prescaler
4, 16, 64
Data to TXx/RXx in SSPSR
TRIS bit
2010 Microchip Technology Inc.
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SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
18.3.1
REGISTERS
Each MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPSR and SSPBUF together,
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
During
transmission,
the
SSPBUF
is
not
double-buffered. A write to SSPBUF will write to both,
SSPBUF and SSPSR.
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 18-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
SMP
R/W-0
CKE(1)
R-0
D/A
R-0
P
R-0
S
R-0
R0
UA
R-0
BF
R/W
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
SMP: Sample bit
SPI Master mode:
1= Input data sampled at the end of data output time
0= Input data sampled at the middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit(1)
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D/A: Data/Address bit
Used in I2C™ mode only.
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled; SSPEN is cleared.
S: Start bit
Used in I2C mode only.
R/W: Read/Write Information bit
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete; SSPBUF is full
0= Receive not complete; SSPBUF is empty
Note 1: Polarity of the clock state is set by the CKP bit (SSPCON1<4>).
DS39933D-page 212
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REGISTER 18-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0
WCOL
R/W-0
SSPOV(1)
R/W-0
SSPEN(2)
R/W-0
CKP
R/W-0
SSPM3(3)
R/W-0
SSPM2(3)
R/W-0
SSPM1(3)
R/W-0
SSPM0(3)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0= No overflow
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(2)
1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3)
0101= SPI Slave mode; clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100= SPI Slave mode; clock = SCK pin, SS pin control enabled
0011= SPI Master mode; clock = TMR2 output/2
0010= SPI Master mode; clock = FOSC/64
0001= SPI Master mode; clock = FOSC/16
0000= SPI Master mode; clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as inputs or outputs.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed successfully.
18.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data (trans-
mission is complete). When the SSPBUF is read, the BF
bit is cleared. This data may be irrelevant if the SPI is
only a transmitter. Generally, the MSSP interrupt is used
to determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 18-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the SSPSTAT register indicates the
various status conditions.
EXAMPLE 18-1:
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP
BTFSS
BRA
SSPSTAT, BF
LOOP
;Has data been received (transmit complete)?
;No
MOVF
MOVWF
MOVF
MOVWF
SSPBUF, W
RXDATA
TXDATA, W
SSPBUF
;WREG reg = contents of SSPBUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
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to a higher level through an external pull-up resistor,
and allows the output to communicate with external
circuits without the need for additional level shifters.
18.3.3
ENABLING SPI I/O
To enable the serial port, the MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
The open-drain output option is controlled by the
SPIOD bit (TRISG<7>). Setting this bit configures both
pins for open-drain operation.
18.3.5
TYPICAL CONNECTION
Figure 18-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISF<7> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
18.3.4
OPEN-DRAIN OUTPUT OPTION
The drivers for the SDO output and SCK clock pins can
be optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled
FIGURE 18-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
SPI Slave SSPM<3:0> = 010x
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
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The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This, then,
would give waveforms for SPI communication, as
shown in Figure 18-3, Figure 18-5 and Figure 18-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user-programmable to be one
of the following:
18.3.6
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 18-2) will
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if it was a normal received byte (interrupts and status
bits appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 18-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 18-3:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
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pin is driven. When the SS pin goes high, the SDO pin
is no longer driven, even if in the middle of a transmitted
18.3.7
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
byte, and becomes
a floating output. External
pull-up/pull-down resistors may be desirable
depending on the application.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1<4>).
Note 1: When the SPI is in Slave mode with
the SS
(SSPCON1<3:0> = 0100),
pin
control
enabled
the SPI
module will reset if the SS pin is set to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
18.3.8
SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). When the SS pin is low,
transmission and reception are enabled and the SDO
FIGURE 18-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 7
bit 7
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
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FIGURE 18-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
FIGURE 18-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 7
SDI
(SMP = 0)
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
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mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set,
and if enabled, will wake the device.
18.3.9
OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of Sleep mode, all clocks are halted.
18.3.10 EFFECTS OF A RESET
In Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTRC source. See Section 3.3 “Clock Sources
and Oscillator Switching” for additional information.
A Reset disables the MSSP module and terminates the
current transfer.
18.3.11 BUS MODE COMPATIBILITY
Table 18-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
TABLE 18-1: SPI BUS MODES
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the device wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
There is also an SMP bit which controls when the data
is sampled.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
TABLE 18-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
RBIE
SSPIF
TMR0IF
—
INT0IF
RBIF
59
62
62
62
62
62
62
60
60
60
—
—
ADIF
ADIE
RC1IF
RC1IE
RC1IP
TRISC5
TRISF5
TMR2IF
TMR1IF
PIE1
TX1IE
SSPIE
SSPIP
TRISC3
TRISF3
TRISG3
—
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
—
ADIP
TX1IP
—
TRISC
TRISF
TRISC7
TRISF7
SPIOD
TRISC6
TRISF6
TRISC4
TRISF4
TRISC2
TRISF2
TRISG2
TRISC1
TRISF1
TRISG1
TRISC0
—
TRISG
SSPBUF
SSPCON1
SSPSTAT
CCP2OD CCP1OD TRISG4
TRISG0
MSSP Receive Buffer/Transmit Register
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
Legend: Shaded cells are not used by the MSSP module in SPI mode.
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2
18.4.1
REGISTERS
18.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support), and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
Two pins are used for data transfer:
• MSSP Shift Register (SSPSR) – Not directly
accessible
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
• MSSP Address Register (SSPADD)
The user must configure these pins as inputs by setting
the TRISC<4:3> bits.
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
FIGURE 18-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
Internal
Many of the bits in SSPCON2 assume different
functions, depending on whether the module is operat-
ing in Master or Slave mode. The SSPCON2<5:2> bits
also assume different names in Slave mode. The differ-
ent aspects of SSPCON2 are shown in Register 18-5
(for Master mode) and Register 18-6 (Slave mode).
Data Bus
Read
Write
SSPBUF reg
SCL
SDA
Shift
Clock
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPSR reg
LSb
MSb
The SSPADD register holds the slave device address
when the MSSP is configured in I2C Slave mode. When
the MSSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate Generator
reload value.
Match Detect
Addr Match
Address Mask
In receive operations, SSPSR and SSPBUF together,
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
SSPADD reg
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit Detect
During
transmission,
the
SSPBUF
is
not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
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REGISTER 18-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P(1)
R-0
S(1)
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for High-Speed mode (400 kHz)
bit 6
bit 5
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: Stop bit(1)
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
S: Start bit(1)
1= Indicates that a Start bit has been detected last
0= Start bit was not detected last
R/W: Read/Write Information bit (I2C™ mode only)
In Slave mode:(2)
1= Read
0= Write
In Master mode:(3)
1= Transmit is in progress
0= Transmit is not in progress
bit 1
bit 0
UA: Update Address bit (10-Bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1= SSPBUF is full
0= SSPBUF is empty
In Receive mode:
1= SSPBUF is full (does not include the ACK and Stop bits)
0= SSPBUF is empty (does not include the ACK and Stop bits)
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
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REGISTER 18-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE)
R/W-0
WCOL
R/W-0
R/W-0
SSPEN(1)
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPBUF register was attempted while the I2C™ conditions were not valid for a
transmission to be started (must be cleared in software)
0= No collision
In Slave Transmit mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in
software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Master Synchronous Serial Port Enable bit(1)
1= Enables the serial port and configures the SDA and SCL pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
CKP: SCK Release Control bit
In Slave mode:
1= Release clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011= I2C Firmware Controlled Master mode (slave Idle)
1000= I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Note 1: When enabled, the SDA and SCL pins must be configured as inputs.
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REGISTER 18-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE)
R/W-0
GCEN
R/W-0
R/W-0
ACKDT(1)
R/W-0
ACKEN(2)
R/W-0
RCEN(2)
R/W-0
PEN(2)
R/W-0
RSEN(2)
R/W-0
SEN(2)
ACKSTAT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
GCEN: General Call Enable bit
Unused in Master mode.
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit(2)
1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit; automatically
cleared by hardware
0= Acknowledge sequence Idle
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (Master Receive mode only)(2)
1= Enables Receive mode for I2C™
0= Receive Idle
PEN: Stop Condition Enable bit(2)
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
RSEN: Repeated Start Condition Enable bit(2)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable bit(2)
1= Initiate Start condition on SDA and SCL pins; automatically cleared by hardware
0= Start condition Idle
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written to
(or writes to the SSPBUF are disabled).
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REGISTER 18-6: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ SLAVE MODE)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEN(1)
ACKSTAT
ADMSK5
ADMSK4
ADMSK3
ADMSK2
ADMSK1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
GCEN: General Call Enable bit
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
bit 5-2
ADMSK<5:2>: Slave Address Mask Select bits
1= Masking of corresponding bits of SSPADD is enabled
0= Masking of corresponding bits of SSPADD is disabled
bit 1
ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Addressing mode:
1= Masking of SSPADD<1> only is enabled
0= Masking of SSPADD<1> only is disabled
In 10-Bit Addressing mode:
1= Masking of SSPADD<1:0> is enabled
0= Masking of SSPADD<1:0> is disabled
bit 0
SEN: Stretch Enable bit(1)
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: If the I2C™ module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
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The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
18.4.2
OPERATION
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I2C modes to be selected:
18.4.3.1
Addressing
• I2C Master mode,
clock = (FOSC/4) x (SSPADD + 1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode,
slave is Idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCL and SDA pins.
Once the MSSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition, the
8 bits are shifted into the SSPSR register. All incoming
bits are sampled with the rising edge of the clock (SCL)
line. The value of register, SSPSR<7:1>, is compared to
the value of the SSPADD register. The address is com-
pared on the falling edge of the eighth clock (SCL) pulse.
If the addresses match, and the BF and SSPOV bits are
clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. The MSSP Interrupt Flag bit, SSPIF, is set (and
an interrupt is generated, if enabled) on the
falling edge of the ninth SCL pulse.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. The R/W (SSPSTAT<2>) bit must specify a
write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the
two MSbs of the address. The sequence of events for
10-bit addressing is as follows, with steps 7 through 9
for the slave-transmitter:
18.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an exact address match. In addition,
address masking will also allow the hardware to gener-
ate an interrupt for more than one address (up to 31 in
7-bit addressing and up to 63 in 10-bit addressing).
Through the mode select bits, the user can also choose
to interrupt on Start and Stop bits.
1. Receive first (high) byte of address (bits, SSPIF,
BF and UA (SSPSTAT<1>), are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit, UA, and releases the
SCL line).
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPBUF register with the received value
currently in the SSPSR register.
3. Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
4. Receive second (low) byte of address (SSPIF,
BF and UA bits are set).
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear the UA bit.
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
6. Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
• The overflow bit, SSPOV (SSPCON1<6>), was
set before the transfer was received.
7. Receive Repeated Start condition.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit, SSPIF, is set. The BF bit is
cleared by reading the SSPBUF register, while bit,
SSPOV, is cleared through software.
8. Receive first (high) byte of address (SSPIF and
BF bits are set).
9. Read the SSPBUF register (clears BF bit) and
clear flag bit, SSPIF.
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In 10-Bit Addressing mode, the ADMSK<5:2> bits
mask the corresponding address bits in the SSPADD
register. In addition, ADMSK1 simultaneously masks
the two LSbs of the address (SSPADD<1:0>). For any
ADMSK bits that are active (ADMSK<n> = 1), the cor-
responding address bit is ignored (SSPADD<n> = x).
Also note, that although in 10-Bit Addressing mode, the
upper address bits reuse part of the SSPADD register
bits. The address mask bits do not interact with those
bits. They only affect the lower address bits.
18.4.3.2
Address Masking
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to
63 addresses in 10-bit mode (see Example 18-2).
The I2C slave behaves the same way, whether address
masking is used or not. However, when address
masking is used, the I2C slave can Acknowledge
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking SSPBUF.
Note 1: ADMSK1 masks the two Least Significant
bits of the address.
2: The two Most Significant bits of the
address are not affected by address
masking.
In 7-Bit Addressing mode, address mask bits,
ADMSK<5:1> (SSPCON<5:1>), mask the correspond-
ing address bits in the SSPADD register. For any ADMSK
bits that are set (ADMSK<n> = 1), the corresponding
address bit is ignored (SSPADD<n> = x). For the module
to issue an address Acknowledge, it is sufficient to match
only on addresses that do not have an active address
mask.
EXAMPLE 18-2:
7-Bit Addressing:
ADDRESS MASKING EXAMPLES
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
10-Bit Addressing:
SSPADD<7:0> = A0h (10100000) (the two MSbs of the address are ignored in this example, since they are
not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh
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18.4.3.3
Reception
18.4.3.4
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin, RC3, is held low,
regardless of SEN (see Section 18.4.4 “Clock
Stretching” for more details). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
which also loads the SSPSR register. Then, pin, RC3,
should be enabled by setting bit, CKP (SSPCON1<4>).
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 18-10).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPSTAT<0>), is
set or bit, SSPOV (SSPCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPIF, must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), SCK/SCL will
be held low (clock stretch) following each data
transfer. The clock must be released by setting bit,
CKP (SSPCON1<4>). See Section 18.4.4 “Clock
Stretching” for more details.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset and the slave monitors for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, pin, RC3, must be
enabled by setting bit, CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
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2
FIGURE 18-8:
I C™ SLAVE MODE TIMING WITH SEN = 0(RECEPTION, 7-BIT ADDRESSING)
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2
FIGURE 18-9:
I C™ SLAVE MODE TIMING WITH SEN = 0AND ADMSK<5:1> = 01011
(RECEPTION, 7-BIT ADDRESSING)
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2
FIGURE 18-10:
I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING)
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FIGURE 18-11:
I2C™ SLAVE MODE TIMING WITH SEN = 0(RECEPTION, 10-BIT ADDRESSING)
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FIGURE 18-12:
I2C™ SLAVE MODE TIMING WITH SEN = 0AND ADMSK<5:1> = 01001
(RECEPTION, 10-BIT ADDRESSING)
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2
FIGURE 18-13:
I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING)
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18.4.4
CLOCK STRETCHING
18.4.4.3
Clock Stretching for 7-Bit Slave
Transmit Mode
Both 7-Bit and 10-Bit Slave modes implement
automatic clock stretching during a transmit sequence.
The 7-Bit Slave Transmit mode implements clock
stretching by clearing the CKP bit after the falling edge
of the ninth clock if the BF bit is clear. This occurs
regardless of the state of the SEN bit.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 18-10).
18.4.4.1
Clock Stretching for 7-Bit Slave
Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 18-15).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
18.4.4.4
Clock Stretching for 10-Bit Slave
Transmit Mode
In 10-Bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-Bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set. The module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-Bit Slave Transmit mode (see Figure 18-13).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software regard-
less of the state of the BF bit. The user
should be careful to clear the BF bit in the
ISR before the next receive sequence in
order to prevent an overflow condition.
18.4.4.2
Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address, and following the receive of the second
byte of the 10-bit address, with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs, and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a data
sequence, not an address sequence.
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already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 18-14).
18.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already
sampled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
FIGURE 18-14:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX – 1
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPCON
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2
FIGURE 18-15:
I C™ SLAVE MODE TIMING WITH SEN = 1(RECEPTION, 7-BIT ADDRESSING)
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FIGURE 18-16:
I2C™ SLAVE MODE TIMING WITH SEN = 1(RECEPTION, 10-BIT ADDRESSING)
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If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF interrupt flag bit is set.
18.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device-specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-Bit Addressing mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 18-17).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit, GCEN, is enabled
(SSPCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPSR and the address is
compared against the SSPADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 18-17:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESSING MODE)
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
ACK
R/W = 0
General Call Address
SDA
SCL
ACK D7 D6
D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
‘0’
‘1’
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18.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set, or the
bus is Idle, with both the S and P bits clear.
The following events will cause the MSSP Interrupt
Flag bit, SSPIF, to be set (and an MSSP interrupt, if
enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start condition
Once Master mode is enabled, the user has six
options.
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
2
FIGURE 18-18:
MSSP BLOCK DIAGRAM (I C™ MASTER MODE)
Internal
Data Bus
SSPM<3:0>
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
SCL In
Bus Collision
Set/Reset S, P, WCOL (SSPSTAT, SSPCON1)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
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I2C Master Mode Operation
A typical transmit sequence would go as follows:
18.4.6.1
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted, 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
4. The address is shifted out on the SDA pin until
all 8 bits are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received, 8 bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out on the SDA pin until all 8 bits
are transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 18.4.7 “Baud Rate” for more detail.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. An interrupt is generated once the Stop condition
is complete.
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Table 18-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
18.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 18-19). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
18.4.7.1
Baud Rate Generation in
Power-Managed Modes
When the device is operating in one of the
power-managed modes, the clock source to the BRG
may change frequency, or even stop, depending on the
mode and clock source selected. Switching to a Run or
Idle mode from either the secondary clock or internal
oscillator is likely to change the clock rate to the BRG.
In Sleep mode, the BRG will not be clocked at all.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
FIGURE 18-19:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control
Reload
BRG Down Counter
CLKO
FOSC/4
TABLE 18-3: I2C™ CLOCK RATE w/BRG
FSCL
FCY
FCY * 2
BRG Value
(2 Rollovers of BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
18h
1Fh
63h
09h
0Ch
27h
02h
09h
00h
400 kHz
312.5 kHz
100 kHz
400 kHz
308 kHz
100 kHz
333 kHz
100 kHz
1 MHz
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SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 18-20).
18.4.7.2
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 18-20:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX – 1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
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18.4.8
I2C MASTER MODE START
CONDITION TIMING
Note:
If, at the beginning of the Start condition,
the SDA and SCL pins are already
sampled low, or if during the Start condi-
tion, the SCL line is sampled low before
the SDA line is driven low, a bus collision
occurs. The Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is aborted
and the I2C module is reset into its Idle
state.
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high when
the Baud Rate Generator times out (TBRG), the SDA
pin is driven low. The action of the SDA pin being driven
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by
hardware. The Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
18.4.8.1
WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL bit is set and the contents of
the buffer are unchanged (the write doesn’t occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
FIGURE 18-21:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
At completion of Start bit,
Write to SEN bit occurs here
SDA = 1,
SCL = 1
hardware clears SEN bit
and sets SSPIF bit
TBRG
TBRG
Write to SSPBUF occurs here
1st bit 2nd bit
SDA
TBRG
SCL
TBRG
S
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18.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<6:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins
counting. SDA and SCL must be sampled high for one
TBRG. This action is then followed by assertion of the
SDA pin (SDA = 0) for one TBRG while SCL is high.
Following this, the RSEN bit (SSPCON2<1>) will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDA pin held low. As soon
as a Start condition is detected on the SDA and SCL
pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit
will not be set until the Baud Rate Generator has timed
out.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
18.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL flag is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 18-22:
REPEATED START CONDITION WAVEFORM
S bit set by hardware
SDA = 1,
SCL = 1
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
Write to SSPCON2 occurs here:
SDA = 1,
SCL (no change)
TBRG
TBRG
TBRG
1st bit
SDA
RSEN bit set by hardware
on falling edge of ninth clock,
end of XMIT
Write to SSPBUF occurs here
TBRG
SCL
TBRG
Sr = Repeated Start
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18.4.10 I2C MASTER MODE
TRANSMISSION
The user should verify that the WCOL is clear after
each write to SSPBUF to ensure the transfer is correct.
In all cases, WCOL must be cleared in software.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full bit, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification,
parameter 106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time
specification, parameter 107). When the SCL pin is
released high, it is held that way for TBRG. The data on
the SDA pin must remain stable for that duration and
some hold time after the next falling edge of SCL. After
the eighth bit is shifted out (the falling edge of the eighth
clock), the BF flag is cleared and the master releases
SDA. This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared; if not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 18-23).
18.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
18.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
The Baud Rate Generator begins counting, and on
each rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable bit,
ACKEN (SSPCON2<4>).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDA pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPCON2<6>). Following the falling edge of the ninth
clock transmission of the address, the SSPIF is set, the
BF flag is cleared and the Baud Rate Generator is
turned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
18.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
18.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
18.4.11.3 WCOL Status Flag
18.4.10.1 BF Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
18.4.10.2 WCOL Status Flag
If the user writes to the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write doesn’t occur) for
2 TCY after the SSPBUF write. If SSPBUF is rewritten
within 2 TCY, the WCOL bit is set and SSPBUF is
updated. This may result in a corrupted transfer.
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2
FIGURE 18-23:
I C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESSING)
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2
FIGURE 18-24:
I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING)
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18.4.12 ACKNOWLEDGE SEQUENCE
TIMING
18.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 18-25).
a
receive/transmit, the SCL line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDA line low. When the SDA line
is sampled low, the Baud Rate Generator is reloaded
and counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is
sampled high while SCL is high, the
(SSPSTAT<4>) is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 18-26).
P
bit
18.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
18.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 18-25:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2,
ACKEN automatically cleared
TBRG
ACKEN = 1, ACKDT = 0
TBRG
SDA
SCL
D0
8
ACK
9
SSPIF
Cleared in
software
SSPIF set at
the end of receive
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 18-26:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2,
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
set PEN
Falling edge of
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
9th clock
ACK
TBRG
SCL
SDA
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
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18.4.14 SLEEP OPERATION
18.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high, and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I2C port to its Idle state (Figure 18-27).
18.4.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
18.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine, and if the I2C bus
is free, the user can resume communication by asserting
a Start condition.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are
deasserted and the respective control bits in the
SSPCON2 register are cleared. When the user services
the bus collision Interrupt Service Routine, and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register or the bus is Idle and the S and P bits are
cleared.
FIGURE 18-27:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Data changes
while SCL = 0
SDA line pulled low
by another source
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
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If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 18-30). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0. If the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
18.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 18-28).
b) SCL is sampled low before SDA is asserted low
(Figure 18-29).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted;
• the BCLIF flag is set; and
• the MSSP module is reset to its Idle state
(Figure 18-28).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 18-28:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
MSSP module reset into Idle state.
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
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FIGURE 18-29:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
‘0’
‘0’
SSPIF
FIGURE 18-30:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
‘0’
BCLIF
S
SSPIF
Interrupts cleared
in software
SDA = 0, SCL = 1,
set SSPIF
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If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’; see
Figure 18-31). If SDA is sampled high, the BRG is
reloaded and begins counting. If SDA goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDA at
exactly the same time.
18.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from a low level to a high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
If SCL goes from high-to-low before the BRG times out,
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition
(see Figure 18-32).
When the user deasserts SDA, and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>
and counts down to 0. The SCL pin is then deasserted,
and when sampled high, the SDA pin is sampled.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete.
FIGURE 18-31:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
‘0’
S
‘0’
SSPIF
FIGURE 18-32:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
BCLIF
RSEN
Interrupt cleared
in software
‘0’
S
SSPIF
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The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 18-33). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 18-34).
18.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 18-33:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
FIGURE 18-34:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
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TABLE 18-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
—
RBIE
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TRISC3
TMR0IF
—
INT0IF
RBIF
59
62
62
62
62
62
62
62
60
60
—
ADIF
ADIE
RC1IF
RC1IE
RC1IP
—
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
—
IPR1
—
ADIP
—
PIR2
OSCFIF
OSCFIE
OSCFIP
TRISC7
CMIF
CMIE
CMIP
TRISC6
LVDIF
LVDIE
LVDIP
TRISC2
TMR3IF
TMR3IE
TMR3IP
—
—
—
PIE2
—
—
IPR2
—
—
TRISC
TRISC5
TRISC4
TRISC1 TRISC0
SSPBUF MSSP Receive Buffer/Transmit Register
SSPADD MSSP Address Register (I2C™ Slave mode),
MSSP Baud Rate Reload Register (I2C Master mode)
SSPCON1
SSPCON2
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
PEN
SSPM1
RSEN
SSPM0
SEN
SEN
BF
60
60
60
GCEN ACKSTAT ACKDT
GCEN ACKSTAT ADMSK5(1) ADMSK4(1) ADMSK3(1) ADMSK2(1) ADMSK1(1)
ACKEN
RCEN
SSPSTAT
SMP CKE D/A R/W UA
P
S
Legend: —= unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.
Note 1: Alternate bit definitions for use in I2C Slave mode operations only.
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The pins of the EUSART are multiplexed with the
functions of PORTC (RC6/TX1/CK1/SEG27 and
RC7/RX1/DT1/SEG28). In order to configure these
pins as an EUSART:
19.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• bit, SPEN (RCSTA1<7>), must be set (= 1)
• bit, TRISC<7>, must be set (= 1)
• bit, TRISC<6>, must be set (= 1)
PIC18F87J90 family devices have three serial I/O
modules: the MSSP module, discussed in the previous
chapter and two Universal Synchronous Asynchronous
Receiver Transmitter (USART) modules. (Generically,
the USART is also known as a Serial Communications
Interface or SCI.) The USART can be configured as a
full-duplex, asynchronous system that can communi-
cate with peripheral devices, such as CRT terminals
and personal computers. It can also be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The driver for the TX1 output pin can also be optionally
configured as an open-drain output. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor, and allows the out-
put to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the U1OD
bit (LATG<6>). Setting the bit configures the pin for
open-drain operation.
There are two distinct implementations of the USART
module in these devices: the Enhanced USART
(EUSART) discussed here and the Addressable
USART discussed in the next chapter. For this device
family, USART1 always refers to the EUSART, while
USART2 is always the AUSART.
19.1 Control Registers
The operation of the Enhanced USART module is
controlled through three registers:
The EUSART and AUSART modules implement the
same core features for serial communications; their
basic operation is essentially the same. The EUSART
module provides additional features, including Auto-
matic Baud Rate Detection and calibration, automatic
wake-up on Sync Break reception, and 12-bit Break
character transmit. These features make it ideally
suited for use in Local Interconnect Network bus
(LIN/J2602 bus) systems.
• Transmit Status and Control Register 1 (TXSTA1)
• Receive Status and Control Register 1 (RCSTA1)
• Baud Rate Control Register 1 (BAUDCON1)
The registers are described in Register 19-1,
Register 19-2 and Register 19-3.
The EUSART can be configured in the following
modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half-duplex) with
selectable clock polarity
• Synchronous – Slave (half-duplex) with selectable
clock polarity
2010 Microchip Technology Inc.
DS39933D-page 255
PIC18F87J90 FAMILY
REGISTER 19-1: TXSTA1: EUSART TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN(1)
R/W-0
SYNC
R/W-0
R/W-0
BRGH
R-1
R/W-0
TX9D
SENDB
TRMT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
bit 4
bit 3
TX9: 9-Bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit(1)
1= Transmit enabled
0= Transmit disabled
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS39933D-page 256
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 19-2: RCSTA1: EUSART RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX1/DT1 and TX1/CK1 pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-Bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and the ninth bit can be used as a parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG1 register and receiving next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit, CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
2010 Microchip Technology Inc.
DS39933D-page 257
PIC18F87J90 FAMILY
REGISTER 19-3: BAUDCON1: BAUD RATE CONTROL REGISTER 1
R/W-0
R-1
R/W - 0
RXDTP
R/W-0
R/W-0
U-0
—
R/W-0
WUE
R/W-0
ABDOVF
RCIDL
TXCKP
BRG16
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
ABDOVF: Auto-Baud Acquisition Rollover Status bit
1= A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0= No BRG rollover has occurred
RCIDL: Receive Operation Idle Status bit
1= Receive operation is Idle
0= Receive operation is active
RXDTP: Received Data Polarity Select bit
Asynchronous mode:
1= RXx data is inverted
0= RXx data is not inverted
Synchronous mode:
1= CKx clocks are inverted
0= CKx clocks are not inverted
bit 4
TXCKP: Clock and Data Polarity Select bit
Asynchronous mode:
1= TXx data is inverted
0= TXx data is not inverted
Synchronous mode:
1= CKx clocks are inverted
0= CKx clocks are not inverted
bit 3
BRG16: 16-Bit Baud Rate Register Enable bit
1= 16-bit Baud Rate Generator – SPBRGH1 and SPBRG1
0= 8-bit Baud Rate Generator – SPBRG1 only (Compatible mode), SPBRGH1 value ignored
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= EUSART will continue to sample the RX1 pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0= RX1 pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0= Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
DS39933D-page 258
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
are shown in Table 19-2. It may be advantageous to use
the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
for a fast oscillator frequency.
19.2 EUSART Baud Rate Generator
(BRG)
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>)
selects 16-bit mode.
Writing a new value to the SPBRGH1:SPBRG1 regis-
ters causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
The SPBRGH1:SPBRG1 register pair controls the
period of a free-running timer. In Asynchronous mode,
the BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>)
bits also control the baud rate. In Synchronous mode,
BRGH is ignored. Table 19-1 shows the formula for com-
putation of the baud rate for different EUSART modes
that only apply in Master mode (internally generated
clock).
19.2.1
OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG1 register pair.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH1:SPBRG1 registers can
be calculated using the formulas in Table 19-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 19-1. Typical baud rates
and error values for the various Asynchronous modes
19.2.2
SAMPLING
The data on the RX1 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX1 pin.
TABLE 19-1: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[4 (n + 1)]
Legend: x= Don’t care, n = Value of SPBRGH1:SPBRG1 register pair
EXAMPLE 19-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = FOSC/(64 ([SPBRGH1:SPBRG1] + 1))
Solving for SPBRGH1:SPBRG1:
X = ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
TABLE 19-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Reset Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTA1
RCSTA1
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
61
61
63
63
61
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
ABDEN
SPBRGH1
SPBRG1
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
2010 Microchip Technology Inc.
DS39933D-page 259
PIC18F87J90 FAMILY
TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
103
25
12
—
0.300
1.201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
%
Error
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
—
—
—
—
—
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.403
9.615
19.230
55.555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.6
9.766
19.231
58.140
113.636
1.73
0.16
0.94
-1.36
255
129
42
9.615
19.231
56.818
113.636
0.16
0.16
-1.36
-1.36
129
64
21
10
19.2
57.6
115.2
21
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
DS39933D-page 260
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
0.02
-0.03
-0.03
0.16
4165
1041
520
129
64
0.300
1.200
0.02
-0.03
0.16
0.16
1.73
-1.36
8.51
2082
520
259
64
0.300
1.201
2.403
9.615
19.230
55.555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
2.4
2.402
2.399
2.404
9.6
9.615
9.615
9.615
19.2
57.6
115.2
19.231
58.140
113.636
19.231
56.818
113.636
0.16
19.531
56.818
125.000
31
25
-1.36
-1.36
21
10
8
21
10
4
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.04
0.16
0.16
0.16
0.16
8.51
8.51
832
207
103
25
12
3
0.300
1.201
2.403
9.615
—
-0.16
-0.16
-0.16
-0.16
—
415
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 10.000 MHz
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG Actual
value
SPBRG
value
(decimal)
%
Error
%
%
%
Error
value
(decimal)
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.00
0.02
0.06
-0.03
0.35
-0.22
33332
8332
4165
1040
520
0.300
1.200
0.00
0.02
0.02
-0.03
0.16
-0.22
0.94
16665
4165
2082
520
259
86
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
-0.01
-0.04
-0.04
-0.16
-0.16
0.79
6665
1665
832
207
103
34
2.4
2.400
2.400
2.402
2.400
9.6
9.606
9.596
9.615
9.615
19.2
57.6
115.2
19.193
57.803
114.943
19.231
57.471
116.279
19.231
58.140
113.636
19.230
57.142
117.647
172
86
42
21
-2.12
16
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.01
0.04
0.16
0.16
0.16
2.12
-3.55
3332
832
415
103
51
0.300
1.201
2.403
9.615
19.230
55.555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
0.300
1.201
2.403
9.615
19.230
—
-0.04
-0.16
-0.16
-0.16
-0.16
—
832
207
103
25
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
58.824
111.111
25
12
16
8
—
8
—
—
—
—
2010 Microchip Technology Inc.
DS39933D-page 261
PIC18F87J90 FAMILY
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RC1IF interrupt is set
once the fifth rising edge on RX1 is detected. The value
in the RCREG1 needs to be read to clear the RC1IF
interrupt. The contents of RCREG1 should be
discarded.
19.2.3
AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 19-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system
timing and communication baud rates
must be taken into consideration when
using the Auto-Baud Rate Detection
feature.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX1 signal, the RX1 signal is timing the BRG.
In ABD mode, the internal Baud Rate Generator is
used as a counter to time the bit period of the incoming
serial byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value, 55h (ASCII
“U”, which is also the LIN/J2602 bus Sync character),
in order to calculate the proper bit rate. The measure-
ment is taken over both a low and a high bit time in
order to minimize any effects caused by asymmetry of
the incoming signal. After a Start bit, the SPBRG1
begins counting up, using the preselected clock source
on the first rising edge of RX1. After eight bits on the
RX1 pin, or the fifth rising edge, an accumulated value
totalling the proper BRG period is left in the
SPBRGH1:SPBRG1 register pair. Once the 5th edge is
seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
TABLE 19-4: BRG COUNTER CLOCK
RATES
BRG16 BRGH
BRG Counter Clock
0
0
1
0
1
FOSC/512
FOSC/128
FOSC/128
FOSC/32
0
1
1
Note:
During the ABD sequence, SPBRG1 and
SPBRGH1 are both used as a 16-bit
counter, independent of the BRG16 setting.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status bit
(BAUDCON1<7>). It is set in hardware by BRG rollovers
and can be set or cleared by the user in software. ABD
mode remains active after rollover events and the
ABDEN bit remains set (Figure 19-2).
19.2.3.1
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG1 cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock can be configured by the
BRG16 and BRGH bits. The BRG16 bit must be set to
use both SPBRG1 and SPBRGH1 as a 16-bit counter.
This allows the user to verify that no carry occurred for
8-bit modes by checking for 00h in the SPBRGH1
register. Refer to Table 19-4 for counter clock rates to
the BRG.
DS39933D-page 262
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 19-1:
AUTOMATIC BAUD RATE CALCULATION
BRG Value
XXXXh
0000h
001Ch
Edge #5
Stop bit
Edge #1
Edge #2
bit 3
Edge #3
bit 5
Edge #4
Start
bit 7
RX1 pin
bit 1
bit 0
bit 2
bit 4
bit 6
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RC1IF bit
(Interrupt)
Read
RCREG1
XXXXh
XXXXh
1Ch
00h
SPBRG1
SPBRGH1
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 19-2:
BRG OVERFLOW SEQUENCE
BRG Clock
ABDEN bit
RX1 pin
Start
bit 0
ABDOVF bit
BRG Value
FFFFh
XXXXh
0000h
0000h
2010 Microchip Technology Inc.
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Once the TXREG1 register transfers the data to the
TSR register (occurs in one TCY), the TXREG1 register
is empty and the TX1IF flag bit (PIR1<4>) is set. This
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF
will be set regardless of the state of TX1IE; it cannot be
cleared in software. TX1IF is also not cleared immedi-
ately upon loading TXREG1, but becomes valid in the
second instruction cycle following the load instruction.
Polling TX1IF immediately following a load of TXREG1
will return invalid results.
19.3 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA1<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ) for-
mat (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be
used to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate, depending on the BRGH
and BRG16 bits (TXSTA1<2> and BAUDCON1<3>).
Parity is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
While TX1IF indicates the status of the TXREG1
register, another bit, TRMT (TXSTA1<1>), shows the
status of the TSR register. TRMT is a read-only bit
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
Note 1: The TSR register is not mapped in data
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
memory, so it is not available to the user.
2: Flag bit, TX1IF, is set when enable bit,
• Baud Rate Generator
TXEN, is set.
• Sampling Circuit
To set up an Asynchronous Transmission:
• Asynchronous Transmitter
• Asynchronous Receiver
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
• Auto-Wake-up on Sync Break Character
• 12-Bit Break Character Transmit
• Auto-Baud Rate Detection
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
19.3.1
EUSART ASYNCHRONOUS
TRANSMITTER
3. If interrupts are desired, set enable bit, TX1IE.
4. If 9-bit transmission is desired, set transmit bit,
TX9; can be used as address/data bit.
The EUSART transmitter block diagram is shown in
Figure 19-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer Register,
TXREG1. The TXREG1 register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG1 register (if available).
5. Enable the transmission by setting bit, TXEN,
which will also set bit, TX1IF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Load data to the TXREG1 register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-3:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TX1IF
TXREG1 Register
8
TX1IE
MSb
(8)
LSb
0
Pin Buffer
and Control
TSR Register
TX1 pin
Interrupt
Baud Rate CLK
TXEN
TRMT
SPEN
BRG16
SPBRGH1 SPBRG1
Baud Rate Generator
TX9
TX9D
DS39933D-page 264
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 19-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREG1
Word 1
BRG Output
(Shift Clock)
TX1 (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TX1IF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 19-5:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG1
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX1 (pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 1
TX1IF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 19-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
59
62
62
62
61
61
61
63
63
61
62
—
—
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF
TMR1IF
PIE1
—
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
—
—
RCSTA1
TXREG1
TXSTA1
SPEN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGH1
SPBRG1
LATG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
U2OD
U1OD
—
LATG4
LATG3
LATG2
LATG1
LATG0
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
2010 Microchip Technology Inc.
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19.3.2
EUSART ASYNCHRONOUS
RECEIVER
19.3.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 19-6.
The data is received on the RX1 pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter, operating at x16 times the baud
rate, whereas the main receive serial shifter operates
at the bit rate or at FOSC. This mode would typically be
used in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RC1IP
bit.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
3. If interrupts are desired, set enable bit, RC1IE.
4. If 9-bit reception is desired, set bit, RX9.
5. Enable the reception by setting bit, CREN.
7. The RC1IF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RC1IE and GIE bits are set.
6. Flag bit, RC1IF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RC1IE, was set.
8. Read the RCSTA1 register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG1 to determine if the device is
being addressed.
8. Read the 8-bit received data by reading the
RCREG1 register.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-6:
EUSART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
64
RSR Register
MSb
Stop
LSb
Start
BRG16
SPBRGH1 SPBRG1
or
16
(8)
7
1
0
or
Baud Rate Generator
4
RX9
Pin Buffer
and Control
Data
Recovery
RX1
RX9D
RCREG1 Register
FIFO
SPEN
8
Interrupt
RC1IF
RC1IE
Data Bus
DS39933D-page 266
2010 Microchip Technology Inc.
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FIGURE 19-7:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX1 (pin)
bit 0 bit 1
bit 7/8
Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
bit 7/8
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREG1
Word 1
RCREG1
RCREG1
Read Rcv
Buffer Reg
RC1IF
(Interrupt Flag)
OERR bit
CREN bit
Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 19-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
59
62
62
62
61
61
61
63
61
61
—
—
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
IPR1
—
—
RCSTA1
RCREG1
TXSTA1
SPEN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGH1
SPBRG1
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
2010 Microchip Technology Inc.
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End-Of-Character (EOF) and cause data or framing
errors. Therefore, to work properly, the initial character
in the transmission must be all ‘0’s. This can be 00h
(8 bytes) for standard RS-232 devices or 000h (12 bits)
for LIN/J2602 bus.
19.3.4
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up, due to activity on the RX1/DT1 line, while
the EUSART is operating in Asynchronous mode.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX1/DT1 is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX1/DT1
line. (This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN/J2602 protocol.)
19.3.4.2
Special Considerations Using
the WUE Bit
The timing of WUE and RC1IF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes
a receive interrupt by setting the RC1IF bit. The WUE
bit is cleared after this when a rising edge is seen on
RX1/DT1. The interrupt condition is then cleared by
reading the RCREG1 register. Ordinarily, the data in
RCREG1 will be dummy data and should be discarded.
Following a wake-up event, the module generates an
RC1IF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 19-8), and asynchronously, if the device is in
Sleep mode (Figure 19-9). The interrupt condition is
cleared by reading the RCREG1 register.
The WUE bit is automatically cleared once a low-to-high
transition is observed on the RX1 line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
The fact that the WUE bit has been cleared (or is still
set), and the RC1IF flag is set, should not be used as
an indicator of the integrity of the data in RCREG1.
Users should consider implementing a parallel method
in firmware to verify received data integrity.
19.3.4.1
Special Considerations Using
Auto-Wake-up
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
Since auto-wake-up functions by sensing rising edge
transitions on RX1/DT1, information with any state
changes before the Stop bit may signal a false
FIGURE 19-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(1)
RX1/DT1 Line
RC1IF
Bit set by user
Auto-Cleared
Cleared due to user read of RCREG1
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 19-9:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(2)
RX1/DT1 Line
RC1IF
Bit set by user
Auto-Cleared
Note 1
Cleared due to user read of RCREG1
Sleep Ends
SLEEPCommand Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
DS39933D-page 268
2010 Microchip Technology Inc.
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3. Load the TXREG1 with a dummy character to
initiate transmission (the value is ignored).
19.3.5
BREAK CHARACTER SEQUENCE
The Enhanced USART module has the capability of
sending the special Break character sequences that are
required by the LIN/J2602 bus standard. The Break
character transmit consists of a Start bit, followed by
twelve ‘0’ bits and a Stop bit. The Frame Break character
is sent whenever the SENDB and TXEN bits
(TXSTA<3> and TXSTA<5>) are set while the Transmit
Shift register is loaded with data. Note that the value of
data written to TXREG1 will be ignored and all ‘0’s will be
transmitted.
4. Write ‘55h’ to TXREG1 to load the Sync
character into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREG1 becomes empty, as indicated by the
TX1IF, the next data byte can be written to TXREG1.
19.3.6
RECEIVING A BREAK CHARACTER
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN/J2602 specification).
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
Note that the data value written to the TXREG1 for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The second method uses the auto-wake-up feature
described in Section 19.3.4 “Auto-Wake-up On Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on
RX1/DT1, cause an RC1IF interrupt and receive the
next data byte followed by another interrupt.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 19-10 for the timing of the Break
character sequence.
19.3.5.1
Break and Sync Transmit Sequence
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
once the TX1IF interrupt is observed.
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN/J2602 bus
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to set up the
Break character.
FIGURE 19-10:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG1
Dummy Write
BRG Output
(Shift Clock)
TX1 (pin)
Start bit
bit 0
bit 1
Break
bit 11
Stop bit
TX1IF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto-Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)
2010 Microchip Technology Inc.
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Once the TXREG1 register transfers the data to the
TSR register (occurs in one TCYCLE), the TXREG1 is
empty and the TX1IF flag bit (PIR1<4>) is set. The
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF is
set regardless of the state of enable bit TX1IE; it cannot
be cleared in software. It will reset only when new data
is loaded into the TXREG1 register.
19.4 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA<4>). In addition, enable bit, SPEN
(RCSTA1<7>), is set in order to configure the TX1 and
RX1 pins to CK1 (clock) and DT1 (data) lines,
respectively.
While flag bit, TX1IF, indicates the status of the TXREG1
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
The Master mode indicates that the processor trans-
mits the master clock on the CK1 line. Clock polarity is
selected with the SCKP bit (BAUDCON<4>). Setting
SCKP sets the Idle state on CK1 as high, while clearing
the bit, sets the Idle state as low. This option is provided
to support Microwire devices with this module.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
baud rate.
19.4.1
EUSART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
The EUSART transmitter block diagram is shown in
Figure 19-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer Register,
TXREG1. The TXREG1 register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG1 (if available).
3. If interrupts are desired, set enable bit, TX1IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREG1 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-11:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1/SEG28
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX1/CK1/SEG27 pin
(SCKP = 0)
RC6/TX1/CK1/SEG27 pin
(SCKP = 1)
Write to
TXREG1 Reg
Write Word 1
Write Word 2
TX1IF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode, SPBRG1 = 0; continuous transmission of two 8-bit words.
DS39933D-page 270
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 19-12:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX1/DT1/SEG28 pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX1/CK1/SEG27 pin
Write to
TXREG1 Reg
TX1IF bit
TRMT bit
TXEN bit
TABLE 19-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
59
62
62
62
61
61
61
63
63
61
62
—
—
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
IPR1
—
—
RCSTA1
TXREG1
TXSTA1
SPEN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGH1 EUSART Baud Rate Generator Register High Byte
SPBRG1
LATG
EUSART Baud Rate Generator Register Low Byte
U2OD U1OD LATG4 LATG3
—
LATG2
LATG1
LATG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
2010 Microchip Technology Inc.
DS39933D-page 271
PIC18F87J90 FAMILY
3. Ensure bits, CREN and SREN, are clear.
4. If interrupts are desired, set enable bit, RC1IE.
5. If 9-bit reception is desired, set bit, RX9.
19.4.2
EUSART SYNCHRONOUS
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA1<5>), or the Continuous Receive
Enable bit, CREN (RCSTA1<4>). Data is sampled on
the RX1 pin on the falling edge of the clock.
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RC1IF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RC1IE, was set.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
8. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG1 register.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH1:SPBRG1 registers for the
appropriate baud rate. Set or clear the BRG16 bit,
as required, to achieve the desired baud rate.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
FIGURE 19-13:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1/
SEG28 Pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX1/CK1/SEG27
Pin (SCKP = 0)
RC6/TX1/CK1/SEG27
Pin (SCKP = 1)
Write to
SREN bit
SREN bit
CREN bit
‘0’
‘0’
RC1IF bit
(Interrupt)
Read
RCREG1
Note: Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0.
TABLE 19-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
59
62
62
62
61
61
61
63
63
61
—
—
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
IPR1
—
—
RCSTA1
RCREG1
TXSTA1
SPEN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGH1 EUSART Baud Rate Generator Register High Byte
SPBRG1 EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
DS39933D-page 272
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
To set up a Synchronous Slave Transmission:
19.5 EUSART Synchronous Slave Mode
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK1 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
Low-Power mode.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TX1IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
19.5.1
EUSART SYNCHRONOUS SLAVE
TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep mode.
7. Start transmission by loading data to the
TXREG1 register.
If two words are written to the TXREG1 and then the
SLEEPinstruction is executed, the following will occur:
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG1
register.
c) Flag bit, TX1IF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG1 register will transfer the second
word to the TSR and flag bit, TX1IF, will now be
set.
e) If enable bit, TX1IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 19-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
59
62
62
62
61
61
61
63
63
61
62
—
—
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
IPR1
—
—
RCSTA1
TXREG1
TXSTA1
SPEN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGH1 EUSART Baud Rate Generator Register High Byte
SPBRG1
LATG
EUSART Baud Rate Generator Register Low Byte
U2OD U1OD LATG4 LATG3
—
LATG2
LATG1
LATG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
2010 Microchip Technology Inc.
DS39933D-page 273
PIC18F87J90 FAMILY
To set up a Synchronous Slave Reception:
19.5.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode, and bit, SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit, RC1IE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this Low-Power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG1 register. If the RC1IE enable bit is set, the
interrupt generated will wake the chip from the
Low-Power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
5. Flag bit, RC1IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC1IE, was set.
6. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG1 register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
59
62
62
62
61
61
61
63
63
61
—
—
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
IPR1
—
—
RCSTA1
RCREG1
TXSTA1
SPEN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGH1 EUSART Baud Rate Generator Register High Byte
SPBRG1 EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
DS39933D-page 274
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
20.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
Note:
The AUSART control will automatically
reconfigure the pin from input to output as
needed.
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The driver for the TX2 output pin can also be optionally
configured as an open-drain output. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor, and allows the
output to communicate with external circuits without the
need for additional level shifters.
The Addressable Universal Synchronous Asynchro-
nous Receiver Transmitter (AUSART) module is very
similar in function to the Enhanced USART module,
discussed in the previous chapter. It is provided as an
additional channel for serial communication with
external devices, for those situations that do not require
auto-baud detection or LIN/J2602 bus support.
The open-drain output option is controlled by the U2OD
bit (LATG<7>). Setting the bit configures the pin for
open-drain operation.
The AUSART can be configured in the following modes:
• Asynchronous (full-duplex)
20.1 Control Registers
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The operation of the Addressable USART module is
controlled through two registers, TXSTA2 and
RXSTA2. These are detailed in Register 20-1 and
Register 20-2, respectively.
The pins of the AUSART module are multiplexed with
the functions of PORTG (RG1/TX2/CK2 and
RG2/RX2/DT2/VLCAP1, respectively). In order to
configure these pins as an AUSART:
• bit, SPEN (RCSTA2<7>), must be set (= 1)
• bit, TRISG<2>, must be set (= 1)
• bit, TRISG<1>, must be cleared (= 0) for
Asynchronous and Synchronous Master modes
• bit, TRISG<1>, must be set (= 1) for Synchronous
Slave mode
2010 Microchip Technology Inc.
DS39933D-page 275
PIC18F87J90 FAMILY
REGISTER 20-1: TXSTA2: AUSART TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN(1)
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
TRMT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-Bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit(1)
1= Transmit enabled
0= Transmit disabled
bit 4
SYNC: AUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as ‘0’
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS39933D-page 276
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 20-2: RCSTA2: AUSART RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX2/DT2 and TX2/CK2 (TXEN = 1) pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-Bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be cleared by reading the RCREGx register and receiving the next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
2010 Microchip Technology Inc.
DS39933D-page 277
PIC18F87J90 FAMILY
Writing a new value to the SPBRG2 register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting
the new baud rate.
20.2 AUSART Baud Rate Generator
(BRG)
The BRG is a dedicated, 8-bit generator that supports
both the Asynchronous and Synchronous modes of the
AUSART.
20.2.1
OPERATION IN POWER-MANAGED
MODES
The SPBRG2 register controls the period of a
free-running timer. In Asynchronous mode, the BRGH
bit (TXSTA<2>) also controls the baud rate. In
Synchronous mode, BRGH is ignored. Table 20-1
shows the formula for computation of the baud rate for
different AUSART modes, which only apply in Master
mode (internally generated clock).
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG2 register.
20.2.2
SAMPLING
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG2 register can be calculated
using the formulas in Table 20-1. From this, the error in
baud rate can be determined. An example calculation is
shown in Example 20-1. Typical baud rates and error
values for the various Asynchronous modes are shown
in Table 20-2. It may be advantageous to use the high
baud rate (BRGH = 1) to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
The data on the RX2 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX2 pin.
TABLE 20-1: BAUD RATE FORMULAS
Configuration Bits
BRG/AUSART Mode
Baud Rate Formula
SYNC
BRGH
0
0
1
0
1
x
Asynchronous
Asynchronous
Synchronous
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
Legend: x= Don’t care, n = Value of SPBRG2 register
EXAMPLE 20-1:
CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:
Desired Baud Rate
Solving for SPBRG2:
X
=
FOSC/(64 ([SPBRG2] + 1))
=
=
=
((FOSC/Desired Baud Rate)/64) – 1
((16000000/9600)/64) – 1
[25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
=
=
=
9615
Error
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
TABLE 20-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Reset
Values on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTA2
RCSTA2
SPBRG2
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
64
64
64
AUSART Baud Rate Generator Register
Legend: Shaded cells are not used by the BRG.
DS39933D-page 278
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES
BRGH = 0
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
%
Error
value
Rate
(K)
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
BRGH = 0
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
103
25
12
—
0.300
1.201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
BRGH = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
—
—
—
—
—
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.403
9.615
19.230
55.555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.6
9.766
19.231
58.140
113.636
1.73
0.16
0.94
-1.36
255
129
42
9.615
19.231
56.818
113.636
0.16
0.16
-1.36
-1.36
129
64
21
10
19.2
57.6
115.2
21
—
BRGH = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
2010 Microchip Technology Inc.
DS39933D-page 279
PIC18F87J90 FAMILY
Once the TXREG2 register transfers the data to the
TSR register (occurs in one TCY), the TXREG2 register
is empty and the TX2IF flag bit (PIR3<4>) is set. This
interrupt can be enabled or disabled by setting or
clearing the interrupt enable bit, TX2IE (PIE3<4>).
TX2IF will be set regardless of the state of TX2IE; it
cannot be cleared in software. TX2IF is also not
cleared immediately upon loading TXREG2, but
becomes valid in the second instruction cycle following
the load instruction. Polling TX2IF immediately
following a load of TXREG2 will return invalid results.
20.3 AUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA2<4>). In this mode, the
AUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is 8 bits. An
on-chip, dedicated, 8-bit Baud Rate Generator can be
used to derive standard baud rate frequencies from the
oscillator.
The AUSART transmits and receives the LSb first. The
AUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock,
either x16 or x64 of the bit shift rate, depending on the
BRGH bit (TXSTA2<2>). Parity is not supported by the
hardware but can be implemented in software and
stored as the 9th data bit.
While TX2IF indicates the status of the TXREG2
register, another bit, TRMT (TXSTA2<1>), shows the
status of the TSR register. TRMT is a read-only bit
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit so the user has to poll this bit
in order to determine if the TSR register is empty.
Note 1: The TSR register is not mapped in data
When operating in Asynchronous mode, the AUSART
module consists of the following important elements:
memory so it is not available to the user.
2: Flag bit, TX2IF, is set when enable bit,
• Baud Rate Generator
• Sampling Circuit
TXEN, is set.
To set up an Asynchronous Transmission:
• Asynchronous Transmitter
• Asynchronous Receiver
1. Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH bit, as required,
to achieve the desired baud rate.
20.3.1
AUSART ASYNCHRONOUS
TRANSMITTER
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
The AUSART transmitter block diagram is shown in
Figure 20-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer Register,
TXREG2. The TXREG2 register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG2 register (if available).
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set transmit bit,
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit, TXEN,
which will also set bit, TX2IF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Load data to the TXREG2 register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-1:
AUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TX2IF
TXREG2 Register
8
TX2IE
MSb
(8)
LSb
Pin Buffer
and Control
TX2 pin
0
TSR Register
Interrupt
Baud Rate CLK
TXEN
TRMT
SPEN
SPBRG2
Baud Rate Generator
TX9
TX9D
DS39933D-page 280
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 20-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG2
Word 1
BRG Output
(Shift Clock)
TX2 (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TX2IF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 20-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG2
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX2 (pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 1
TX2IF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 20-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
INT0IF
RBIF
59
62
62
62
64
64
64
64
62
—
—
LCDIF
LCDIE
LCDIP
RX9
RC2IF
RC2IE
RC2IP
SREN
CTMUIF CCP2IF
CTMUIE CCP2IE
CTMUIP CCP2IP
CCP1IF
RTCCIF
PIE3
CCP1IE RTCCIE
CCP1IP RTCCIP
IPR3
—
RCSTA2
TXREG2
TXSTA2
SPBRG2
LATG
SPEN
ADDEN
FERR
BRGH
LATG2
OERR
TRMT
LATG1
RX9D
AUSART Transmit Register
CSRC TX9 TXEN
SYNC
—
TX9D
AUSART Baud Rate Generator Register
U2OD U1OD LATG4
—
LATG3
LATG0
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
2010 Microchip Technology Inc.
DS39933D-page 281
PIC18F87J90 FAMILY
20.3.2
AUSART ASYNCHRONOUS
RECEIVER
20.3.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 20-4.
The data is received on the RX2 pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH and BRG16
bits, as required, to achieve the desired baud
rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH bit, as required,
to achieve the desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RC2IP
bit.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
3. If interrupts are desired, set enable bit, RC2IE.
4. If 9-bit reception is desired, set bit, RX9.
5. Enable the reception by setting bit, CREN.
7. The RC2IF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RC2IE and GIE bits are set.
6. Flag bit, RC2IF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RC2IE, was set.
8. Read the RCSTA2 register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG2 to determine if the device is
being addressed.
8. Read the 8-bit received data by reading the
RCREG2 register.
10. If any error occurred, clear the CREN bit.
9. If any error occurred, clear the error by clearing
enable bit, CREN.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-4:
AUSART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
SPBRG2
64
or
MSb
Stop
RSR Register
LSb
Start
16
(8)
7
1
0
or
4
Baud Rate Generator
RX9
Pin Buffer
and Control
Data
Recovery
RX2
RX9D
RCREG2 Register
FIFO
SPEN
8
Interrupt
RC2IF
RC2IE
Data Bus
DS39933D-page 282
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 20-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX2 (pin)
bit 0 bit 1
bit 7/8
Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
bit 7/8
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREG2
Word 1
RCREG2
Read Rcv
Buffer Reg
RCREG2
RC2IF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer Register 2) is read after the third
word causing the OERR (Overrun) bit to be set.
TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
INT0IF
RBIF
59
62
62
62
64
64
64
64
—
—
LCDIF
LCDIE
LCDIP
RX9
RC2IF
RC2IE
RC2IP
SREN
CTMUIF CCP2IF
CCP1IF RTCCIF
PIE3
CTMUIE CCP2IE CCP1IE RTCCIE
CTMUIP CCP2IP CCP1IP RTCCIP
IPR3
—
RCSTA2
RCREG2
TXSTA2
SPBRG2
SPEN
ADDEN
FERR
OERR
RX9D
AUSART Receive Register
CSRC TX9 TXEN
SYNC
—
BRGH
TRMT
TX9D
AUSART Baud Rate Generator Register
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
2010 Microchip Technology Inc.
DS39933D-page 283
PIC18F87J90 FAMILY
Once the TXREG2 register transfers the data to the
TSR register (occurs in one TCYCLE), the TXREG2 is
empty and the TX2IF flag bit (PIR3<4>) is set. The
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF is
set regardless of the state of enable bit, TX2IE; it
cannot be cleared in software. It will reset only when
new data is loaded into the TXREG2 register.
20.4 AUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA2<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA2<4>). In addition, enable bit, SPEN
(RCSTA2<7>), is set in order to configure the TX2 and
RX2 pins to CK2 (clock) and DT2 (data) lines,
respectively.
While flag bit, TX2IF, indicates the status of the TXREG2
register, another bit, TRMT (TXSTA2<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
The Master mode indicates that the processor transmits
the master clock on the CK2 line.
To set up a Synchronous Master Transmission:
20.4.1
AUSART SYNCHRONOUS MASTER
TRANSMISSION
1. Initialize the SPBRG2 register for the appropriate
baud rate.
The AUSART transmitter block diagram is shown in
Figure 20-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer Register,
TXREG2. The TXREG2 register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG2 (if available).
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREG2 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-6:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RX2/DT2 pin
TX2/CK2 pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
Write to
TXREG2 Reg
Write Word 1
Write Word 2
TX2IF bit
(Interrupt Flag)
TRMT bit
TXEN bit
‘1’
‘1’
Note: Sync Master mode, SPBRG2 = 0; continuous transmission of two 8-bit words.
DS39933D-page 284
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 20-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX2/DT2 pin
bit 0
bit 2
bit 1
bit 6
bit 7
TX2/CK2 pin
Write to
TXREG2 Reg
TX2IF bit
TRMT bit
TXEN bit
TABLE 20-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
INT0IF
RBIF
59
62
62
62
64
64
64
64
62
—
—
LCDIF
LCDIE
LCDIP
RX9
RC2IF
RC2IE
RC2IP
SREN
CTMUIF CCP2IF
CCP1IF RTCCIF
PIE3
CTMUIE CCP2IE CCP1IE RTCCIE
CTMUIP CCP2IP CCP1IP RTCCIP
IPR3
—
RCSTA2
TXREG2
TXSTA2
SPBRG2
LATG
SPEN
ADDEN
FERR
BRGH
LATG2
OERR
TRMT
LATG1
RX9D
AUSART Transmit Register
CSRC TX9 TXEN
SYNC
—
TX9D
AUSART Baud Rate Generator Register
U2OD U1OD LATG4
—
LATG3
LATG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
2010 Microchip Technology Inc.
DS39933D-page 285
PIC18F87J90 FAMILY
4. If interrupts are desired, set enable bit, RC2IE.
5. If 9-bit reception is desired, set bit, RX9.
20.4.2
AUSART SYNCHRONOUS
MASTER RECEPTION
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA2<5>), or the Continuous Receive
Enable bit, CREN (RCSTA2<4>). Data is sampled on
the RX2 pin on the falling edge of the clock.
7. Interrupt flag bit, RC2IF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RC2IE, was set.
8. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
9. Read the 8-bit received data by reading the
RCREG2 register.
To set up a Synchronous Master Reception:
10. If any error occurred, clear the error by clearing
bit, CREN.
1. Initialize the SPBRG2 register for the appropriate
baud rate.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. Ensure bits, CREN and SREN, are clear.
FIGURE 20-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RX2/DT2 pin
TX2/CK2 pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RC2IF bit
(Interrupt)
Read
RCREG2
Note: Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0.
TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
CCP2IF
CCP2IE
CCP2IP
FERR
INT0IF
CCP1IF
CCP1IE
CCP1IP
OERR
RBIF
59
62
62
62
64
64
64
64
—
—
LCDIF
LCDIE
LCDIP
RX9
RC2IF
RC2IE
RC2IP
SREN
CTMUIF
CTMUIE
CTMUIP
ADDEN
RTCCIF
RTCCIE
RTCCIP
RX9D
PIE3
IPR3
—
RCSTA2
SPEN
RCREG2 AUSART Receive Register
TXSTA2 CSRC TX9 TXEN
SYNC
—
BRGH
TRMT
TX9D
SPBRG2 AUSART Baud Rate Generator Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
DS39933D-page 286
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
To set up a Synchronous Slave Transmission:
20.5 AUSART Synchronous Slave Mode
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA2<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK2 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
Low-Power mode.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
20.5.1
AUSART SYNCHRONOUS
SLAVE TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
7. Start transmission by loading data to the
TXREG2 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
If two words are written to the TXREG2 and then the
SLEEPinstruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG2
register.
c) Flag bit, TX2IF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG2 register will transfer the second
word to the TSR and flag bit, TX2IF, will now be
set.
e) If enable bit, TX2IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
INT0IF
RBIF
59
62
62
62
64
64
64
64
62
—
—
LCDIF
LCDIE
LCDIP
RX9
RC2IF
RC2IE
RC2IP
SREN
CTMUIF CCP2IF
CTMUIE CCP2IE
CTMUIP CCP2IP
CCP1IF RTCCIF
CCP1IE RTCCIE
CCP1IP RTCCIP
PIE3
IPR3
—
RCSTA2
TXREG2
TXSTA2
SPBRG2
LATG
SPEN
ADDEN
FERR
BRGH
LATG2
OERR
TRMT
LATG1
RX9D
AUSART Transmit Register
CSRC TX9 TXEN
SYNC
—
TX9D
AUSART Baud Rate Generator Register
U2OD U1OD LATG4
—
LATG3
LATG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
2010 Microchip Technology Inc.
DS39933D-page 287
PIC18F87J90 FAMILY
To set up a Synchronous Slave Reception:
20.5.2
AUSART SYNCHRONOUS
SLAVE RECEPTION
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep or any
Idle mode, and bit, SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit, RC2IE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep, or any Idle mode, then a word may be
received while in this Low-Power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG2 register; if the RC2IE enable bit is set, the
interrupt generated will wake the chip from Low-Power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
5. Flag bit, RC2IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC2IE, was set.
6. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG2 register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
INT0IF
RBIF
59
62
62
62
64
64
64
64
—
—
LCDIF
LCDIE
LCDIP
RX9
RC2IF
RC2IE
RC2IP
SREN
CTMUIF CCP2IF
CCP1IF
RTCCIF
PIE3
CTMUIE CCP2IE CCP1IE RTCCIE
CTMUIP CCP2IP CCP1IP RTCCIP
IPR3
—
RCSTA2
RCREG2
TXSTA2
SPBRG2
SPEN
ADDEN
FERR
OERR
RX9D
AUSART Receive Register
CSRC TX9 TXEN
SYNC
—
BRGH
TRMT
TX9D
AUSART Baud Rate Generator Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
DS39933D-page 288
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
The ADCON0 register, shown in Register 21-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 21-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 21-3, configures the A/D clock
source, programmed acquisition time and justification.
21.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
12 inputs for all PIC18F87J90 family devices. This
module allows conversion of an analog input signal to
a corresponding 10-bit digital number.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
ADCAL
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADCAL: A/D Calibration bit
1= Calibration is performed on next A/D conversion
0= Normal A/D Converter operation (no calibration is performed)
bit 6
Unimplemented: Read as ‘0’
bit 5-2
CHS<3:0>: Analog Channel Select bits
0000= Channel 00 (AN0)
0001= Channel 01 (AN1)
0010= Channel 02 (AN2)
0011= Channel 03 (AN3)
0100= Channel 04 (AN4)
0101= Channel 05 (AN5)
0110= Channel 06 (AN6)
0111= Channel 07 (AN7)
1000= Channel 08 (AN8)
1001= Channel 09 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
11xx= Unused
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D Converter module is enabled
0= A/D Converter module is disabled
2010 Microchip Technology Inc.
DS39933D-page 289
PIC18F87J90 FAMILY
REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRIGSEL
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
TRIGSEL: Special Trigger Select bit
1= Selects the special trigger from the CTMU
0= Selects the special trigger from the CCP2
bit 6
bit 5
Unimplemented: Read as ‘0’
VCFG1: Voltage Reference Configuration bit (VREF- source)
1= VREF- (AN2)
0= AVSS
bit 4
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1= VREF+ (AN3)
0= AVDD
bit 3-0
PCFG<3:0>: A/D Port Configuration Control bits:
PCFG<3:0> AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
DS39933D-page 290
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 21-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT<2:0>: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS<2:0>: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEPinstruction to be executed before starting a conversion.
2010 Microchip Technology Inc.
DS39933D-page 291
PIC18F87J90 FAMILY
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF- pins.
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
cleared and the A/D Interrupt Flag bit, ADIF, is set.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s Internal RC oscillator.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
The block diagram of the A/D module is shown in
Figure 21-1.
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
FIGURE 21-1:
A/D BLOCK DIAGRAM(1,2)
CHS<3:0>
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
0011
(Input Voltage)
10-Bit
A/D
Converter
AN3
0010
AN2
0001
VCFG<1:0>
AN1
0000
AN0
AVDD
VREF+
VREF-
Reference
Voltage
AVSS
Note 1: Channels, AN15 through AN12, are not available on PIC18F6XJ90 devices.
2: I/O pins have diode protection to VDD and VSS.
DS39933D-page 292
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine acquisition time, see Section 21.1 “A/D
Acquisition Requirements”. After this acquisition
time has elapsed, the A/D conversion can be started.
An acquisition time can be programmed to occur
between setting the GO/DONE bit and the actual start
of the conversion.
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0<1>)
5. Wait for the A/D conversion to complete, by
either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear the ADIF bit, if required.
The following steps should be followed to do an A/D
conversion:
7. For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear the ADIF bit
• Set the ADIE bit
• Set the GIE bit
FIGURE 21-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC 1k
RSS
RS
CPIN
VAIN
ILEAKAGE
±100 nA
CHOLD = 25 pF
VT = 0.6V
5 pF
VSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to
various junctions
VDD
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
RSS
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
1
2
3
4
Sampling Switch (k)
2010 Microchip Technology Inc.
DS39933D-page 293
PIC18F87J90 FAMILY
To calculate the minimum acquisition time,
Equation 21-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
21.1 A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 21-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor, CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
Equation 21-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
=
=
25 pF
2.5 k
1/2 LSb
3V Rss = 2 k
85C (system max.)
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 21-1: A/D ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 21-2: A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
)
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
0.2 s
(Temp – 25C)(0.02 s/C)
(85C – 25C)(0.02 s/C)
1.2 s
Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048) s
-(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s
1.05 s
TACQ
=
0.2 s + 1 s + 1.2 s
2.4 s
DS39933D-page 294
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 21-1: TAD vs. DEVICE OPERATING
FREQUENCIES
21.2 Selecting and Configuring
Automatic Acquisition Time
AD Clock Source (TAD)
Maximum
Device
Frequency
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Operation
ADCS<2:0>
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(2)
000
100
001
101
010
110
x11
2.86 MHz
5.71 MHz
11.43 MHz
22.86 MHz
40.0 MHz
40.0 MHz
1.00 MHz(1)
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT<2:0> bits
(ADCON2<5:3>) remain in their Reset state (‘000’) and
is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a pro-
grammable acquisition time for the A/D module. When
the GO/DONE bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisi-
tion time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit.
Note 1: The RC source has a typical TAD time of
4 s.
2: For device frequencies above 1 MHz, the
device must be in Sleep mode for the entire
conversion or the A/D accuracy may be out
of specification.
21.4 Configuring Analog Port Pins
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
21.3 Selecting the A/D Conversion
Clock
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
There are seven possible options for TAD:
• 2 TOSC
• 4 TOSC
• 8 TOSC
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum, TAD (see parameter 130 in Table 28-25 for
more information).
Table 21-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
2010 Microchip Technology Inc.
DS39933D-page 295
PIC18F87J90 FAMILY
21.5 A/D Conversions
21.6 Use of the CCP2 Trigger
Figure 21-3 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time is selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
Figure 21-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT<2:0>
bits are set to ‘010’ and selecting a 4 TAD acquisition
time before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
conversion
sample.
This
means
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 21-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD
TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7
b4
b1
b0
b9
b8
b7
b6
b5
b3
b2
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 21-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
7
8
9
10
b1
11
b0
1
2
3
4
1
2
3
4
5
6
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
DS39933D-page 296
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
If the A/D is expected to operate while the device is in
21.7 A/D Converter Calibration
a
power-managed mode, the ACQT<2:0> and
The A/D Converter, in the PIC18F87J90 family of
devices, includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for the offset. Thus, subsequent offsets
will be compensated.
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits, ACQT<2:0>, are set to ‘000’ and a
conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCSx bits in the OSCCON register must have already
been cleared prior to starting the conversion.
21.8 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined, in part, by the clock
source and frequency while in a power-managed
mode.
TABLE 21-2: SUMMARY OF A/D REGISTERS
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
TMR2IF
TMR2IE
TMR2IP
CCP1IF
CCP1IE
CCP1IP
RBIF
59
62
62
62
62
62
62
61
61
61
61
61
64
63
62
62
62
—
—
—
—
—
—
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
—
—
—
TMR1IF
TMR1IE
TMR1IP
RTCCIF
RTCCIE
RTCCIP
PIE1
IPR1
ADIP
PIR3
LCDIF
LCDIE
LCDIP
CTMUIF CCP2IF
CTMUIE CCP2IE
CTMUIP CCP2IP
PIE3
IPR3
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCP2CON
PORTA
TRISA
A/D Result Register High Byte
A/D Result Register Low Byte
ADCAL
TRIGSEL
ADFM
—
—
—
CHS3
VCFG1
ACQT2
DC2B1
RA5
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0 GO/DONE ADON
PCFG2
ADCS2
PCFG1
ADCS1
PCFG0
ADCS0
—
—
RA6(1)
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
RA7(1)
RA4
TRISA4
RF4
RA3
TRISA3
RF3
RA2
TRISA2
RF2
RA1
TRISA1
RF1
RA0
TRISA0
—
TRISA7(1) TRISA6(1) TRISA5
PORTF
TRISF
RF7
RF6
RF5
TRISF5
TRISF4
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
2010 Microchip Technology Inc.
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NOTES:
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The CMCON register (Register 22-1) selects the
comparator input and output configuration. Block
diagrams of the various comparator configurations are
shown in Figure 22-1.
22.0 COMPARATOR MODULE
The analog comparator module contains two
comparators that can be configured in a variety of
ways. The inputs can be selected from the analog
inputs multiplexed with pins, RF1 through RF6, as well
as the on-chip voltage reference (see Section 23.0
“Comparator Voltage Reference Module”). The digi-
tal outputs (normal or inverted) are available at the pin
level and can also be read through the control register.
REGISTER 22-1: CMCON: COMPARATOR MODULE CONTROL REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-1
CM2
R/W-1
CM1
R/W-1
CM0
C2OUT
C1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM<2:0> = 110:
1= C1 VIN- connects to RF5/AN10/CVREF/SEG23/C1INB
C2 VIN- connects to RF3/AN8/SEG21/C2INB
0= C1 VIN- connects to RF6/AN11/SEG24/C1INA
C2 VIN- connects to RF4/AN9/SEG22/C2INA
bit 2-0
CM<2:0>: Comparator Mode bits
Figure 22-1 shows the Comparator modes and the CM<2:0> bit settings.
2010 Microchip Technology Inc.
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mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 28.0 “Electrical Characteristics”.
22.1 Comparator Configuration
There are eight modes of operation for the compara-
tors, shown in Figure 22-1. Bits, CM<2:0>, of the
CMCON register are used to select these modes. The
TRISF register controls the data direction of the
comparator pins for each mode. If the Comparator
Note:
Comparator interrupts should be disabled
during Comparator mode change;
otherwise, a false interrupt may occur.
a
FIGURE 22-1:
COMPARATOR I/O OPERATING MODES
Comparator Outputs Disabled
Comparators Off (POR Default Value)
CM<2:0> = 000
CM<2:0> = 111
A
D
VIN-
VIN-
C1INA
C1INA
C1INB
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
C1
C2
C1
C2
VIN+
VIN+
A
D
C1INB
A
A
D
VIN-
VIN-
C2INA
C2INB
C2INA
VIN+
VIN+
D
C2INB
Two Independent Comparators
Two Independent Comparators with Outputs
CM<2:0> = 010
CM<2:0> = 011
A
A
VIN-
VIN-
C1INA
C1INB
C1INA
C1INB
C1OUT
C2OUT
C1OUT
C2OUT
C1
C2
C1
C2
VIN+
VIN+
A
A
RF2/AN7/C1OUT*/SEG20
A
A
VIN-
C2INA
C2INB
A
A
VIN-
C2INA
C2INB
VIN+
VIN+
RF1/AN6/C2OUT*/SEG19
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
CM<2:0> = 100
CM<2:0> = 101
A
A
VIN-
VIN-
C1INA
C1INB
C1INA
C1INB
C1OUT
C2OUT
C1OUT
C1
C2
C1
C2
VIN+
VIN+
A
A
RF2/AN7/C1OUT*/
SEG20
A
D
VIN-
C2INA
C2INB
A
VIN-
C2INA
VIN+
C2OUT
VIN+
D
C2INB
RF1/AN6/C2OUT*/SEG19
Four Inputs Multiplexed to Two Comparators
One Independent Comparator with Output
CM<2:0> = 110
CM<2:0> = 001
A
C1INA
A
A
VIN-
C1INA
C1INB
CIS = 0
CIS = 1
VIN-
A
C1OUT
C1
C1INB
VIN+
C1OUT
C2OUT
C1
C2
VIN+
A
A
RF2/AN7/C1OUT*/SEG20
C2INA
C2INB
VIN-
CIS = 0
CIS = 1
VIN+
D
D
VIN-
C2INA
C2INB
Off (Read as ‘0’)
C2
VIN+
CVREF
From VREF module
A = Analog Input, port reads zeros always
D = Digital Input
CIS (CMCON<3>) is the Comparator Input Switch
* Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs.
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22.3.2
INTERNAL REFERENCE SIGNAL
22.2 Comparator Operation
The comparator module also allows the selection of an
internally generated voltage reference from the
comparator voltage reference module. This module is
described in more detail in Section 23.0 “Comparator
Voltage Reference Module”.
A single comparator is shown in Figure 22-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input, VIN-, the output of the
comparator is a digital low level. When the analog input
at VIN+ is greater than the analog input, VIN-, the output
of the comparator is a digital high level. The shaded
areas of the output of the comparator in Figure 22-2
represent the uncertainty due to input offsets and
response time.
The internal reference is only available in the mode
where four inputs are multiplexed to two comparators
(CM<2:0> = 110). In this mode, the internal voltage
reference is applied to the VIN+ pin of both
comparators.
22.3 Comparator Reference
22.4 Comparator Response Time
Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at VIN- is compared to the
signal at VIN+ and the digital output of the comparator
is adjusted accordingly (Figure 22-2).
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (see Section 28.0
“Electrical Characteristics”).
FIGURE 22-2:
SINGLE COMPARATOR
22.5 Comparator Outputs
VIN+
VIN-
+
Output
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RF1 and RF2
I/O pins. When enabled, multiplexors in the output path
of the RF1 and RF2 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 22-3 shows the comparator output block
diagram.
–
VIN-
VIN+
The TRISF bits will still function as an output enable/
disable for the RF1 and RF2 pins while in this mode.
Output
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4>).
22.3.1
EXTERNAL REFERENCE SIGNAL
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
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FIGURE 22-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
To RF1 or
RF2 pin
D
Q
Bus
Data
CxINV
EN
Read CMCON
D
Q
Set
CMIF
bit
EN
CL
From
Other
Comparator
Reset
22.6 Comparator Interrupts
22.7 Comparator Operation
During Sleep
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2<6>) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current, as shown in the comparator specifications. To
minimize power consumption while in Sleep mode, turn
off the comparators (CM<2:0> = 111) before entering
Sleep. If the device wakes up from Sleep, the contents
of the CMCON register are not affected.
Both the CMIE bit (PIE2<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
condition occurs.
22.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator modules to be turned off
(CM<2:0> = 111). However, the input pins (RF3
through RF6) are configured as analog inputs by
default on device Reset. The I/O configuration for these
pins is determined by the setting of the PCFG<3:0> bits
(ADCON1<3:0>). Therefore, device current is
minimized when analog inputs are present at Reset
time.
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2<6>)
interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit, CMIF.
A mismatch condition will continue to set flag bit, CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit, CMIF, to be cleared.
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range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
22.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 22-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
FIGURE 22-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
Comparator
Input
ILEAKAGE
±100 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend: CPIN
=
=
Input Capacitance
Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
—
RBIE
BCLIF
BCLIE
BCLIP
CIS
TMR0IF
LVDIF
LVDIE
LVDIP
CM2
INT0IF
TMR3IF
TMR3IE
TMR3IP
CM1
RBIF
—
59
62
62
62
61
61
62
62
62
OSCFIF
OSCFIE
OSCFIP
C2OUT
CVREN
RF7
CMIF
CMIE
—
—
PIE2
—
—
IPR2
CMIP
—
—
—
CMCON
CVRCON
PORTF
LATF
C1OUT
CVROE
RF6
C2INV
CVRR
RF5
C1INV
CVRSS
RF4
CM0
CVR0
—
CVR3
RF3
CVR2
RF2
CVR1
RF1
LATF7
LATF6
TRISF6
LATF5
TRISF5
LATF4
TRISF4
LATF3
TRISF3
LATF2
TRISF2
LATF1
TRISF1
—
TRISF
TRISF7
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
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NOTES:
DS39933D-page 304
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The range to be used is selected by the CVRR bit
(CVRCON<5>). The primary difference between the
ranges is the size of the steps selected by the CVREF
Selection bits (CVR<3:0>), with one range offering finer
resolution. The equations used to calculate the output
of the comparator voltage reference are as follows:
23.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
If CVRR = 1:
CVREF = ((CVR<3:0>)/24) x (CVRSRC)
A block diagram of the module is shown in Figure 23-1.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either the device VDD/VSS or an external voltage
reference.
If CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) x
(CVRSRC)
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
23.1 Configuring the Comparator
Voltage Reference
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 28-3 in Section 28.0 “Electrical
Characteristics”).
The comparator voltage reference module is controlled
through the CVRCON register (Register 23-1). The
comparator voltage reference provides two ranges of
output voltage, each with 16 distinct levels.
REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
CVROE(1)
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVRSS
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit(1)
1= CVREF voltage level is also output on the RF5/AN10/CVREF/SEG23/C1INB pin
0= CVREF voltage is disconnected from the RF5/AN10/CVREF/SEG23/C1INB pin
CVRR: Comparator VREF Range Selection bit
1= 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0= Comparator reference source, CVRSRC = VDD – VSS
CVR<3:0>: Comparator VREF Value Selection bits (0 (CVR<3:0>) 15)
When CVRR = 1:
CVREF = ((CVR<3:0>)/24) (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) (CVRSRC)
Note 1: CVROE overrides the TRISF<5> bit setting.
2010 Microchip Technology Inc.
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FIGURE 23-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSS = 0
VREF+
VDD
8R
CVR<3:0>
R
CVREN
R
R
R
16 Steps
CVREF
R
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
23.2 Voltage Reference Accuracy/Error
23.4 Effects of a Reset
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 23-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 28.0 “Electrical Characteristics”.
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>), and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
23.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA2 when it is configured as a digital input will
increase current consumption. Connecting RF5 as a
digital output with CVRSS enabled will also increase
current consumption.
23.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 23-2 shows an example buffering technique.
DS39933D-page 306
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FIGURE 23-2:
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F87J90
CVREF
Module
(1)
R
+
–
CVREF Output
RF5
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Comparator Voltage Reference bits, CVRCON<5> and CVRCON<3:0>.
TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVRCON
CMCON
TRISF
CVREN
C2OUT
TRISF7
CVROE
C1OUT
TRISF6
CVRR
C2INV
CVRSS
C1INV
CVR3
CIS
CVR2
CM2
CVR1
CM1
CVR0
CM0
—
61
61
62
TRISF5 TRISF4
TRISF3
TRISF2
TRISF1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.
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NOTES:
DS39933D-page 308
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• Control of edge sequence
24.0 CHARGE TIME
MEASUREMENT UNIT (CTMU)
• Control of response to edges
• Time measurement resolution of 1 nanosecond
• High-precision time measurement
The Charge Time Measurement Unit (CTMU) is a
flexible analog module that provides accurate differen-
tial time measurement between pulse sources, as well
as asynchronous pulse generation. By working with
other on-chip analog modules, the CTMU can be used
to precisely measure time, measure capacitance,
measure relative changes in capacitance or generate
output pulses with a specific time delay. The CTMU is
ideal for interfacing with capacitive-based sensors.
• Time delay of external or internal signal
asynchronous to the system clock
• Accurate current source suitable for capacitive
measurement
The CTMU works in conjunction with the A/D Converter
to provide up to 13 channels for time or charge
measurement, depending on the specific device and the
number of A/D channels available. When configured for
time delay, the CTMU is connected to one of the analog
comparators. The level-sensitive input edge sources
can be selected from four sources: two external inputs or
the CCP1/CCP2 Special Event Triggers.
The module includes the following key features:
• Up to 13 channels available for capacitive or time
measurement input
• On-chip precision current source
• Four-edge input trigger sources
• Polarity control for each edge source
Figure 24-1 provides a block diagram of the CTMU.
FIGURE 24-1:
CTMU BLOCK DIAGRAM
CTMUCON
CTMUICON
ITRIM<5:0>
EDGEN
EDGSEQEN
EDG1SELx
EDG1POL
EDG2SELx
EDG2POL
TGEN
IDISSEN
CTTRIG
IRNG<1:0>
EDG1STAT
EDG2STAT
Current Source
Edge
Control
Logic
CTEDG1
CTEDG2
CTMU
Control
Logic
A/D Trigger
CTPLS
Current
Control
CCP2
CCP1
Pulse
Generator
A/D Converter
Comparator 2
Input
Comparator 2 Output
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Current trim is provided by the ITRIM<5:0> bits
(CTMUICON<7:2>). These six bits allow trimming of
the current source in steps of approximately 2% per
step. Note that half of the range adjusts the current
source positively and the other half reduces the current
source. A value of ‘000000’ is the neutral position (no
change). A value of ‘100000’ is the maximum negative
adjustment (approximately -62%) and ‘011111’ is the
maximum positive adjustment (approximately +62%).
24.1 CTMU Operation
The CTMU works by using a fixed current source to
charge a circuit. The type of circuit depends on the type
of measurement being made. In the case of charge
measurement, the current is fixed and the amount of
time the current is applied to the circuit is fixed. The
amount of voltage read by the A/D is then a measure-
ment of the capacitance of the circuit. In the case of
time measurement, the current, as well as the capaci-
tance of the circuit, are fixed. In this case, the voltage
read by the A/D is then representative of the amount of
time elapsed from the time the current source starts
and stops charging the circuit.
24.1.3
EDGE SELECTION AND CONTROL
CTMU measurements are controlled by edge events
occurring on the module’s two input channels. Each
channel, referred to as Edge 1 and Edge 2, can be con-
figured to receive input pulses from one of the edge
input pins (CTEDG1 and CTEDG2) or the CCPx
Special Event Triggers. The input channels are level-
sensitive, responding to the instantaneous level on the
channel rather than a transition between levels. The
inputs are selected using the EDG1SEL and EDG2SEL
bit pairs (CTMUCONL<3:2, 6:5>).
If the CTMU is being used as a time delay, both capaci-
tance and current source are fixed, as well as the voltage
supplied to the comparator circuit. The delay of a signal
is determined by the amount of time it takes the voltage
to charge to the comparator threshold voltage.
24.1.1
THEORY OF OPERATION
The operation of the CTMU is based on the equation
for charge:
In addition to source, each channel can be configured for
event polarity using the EDGE2POL and EDGE1POL
bits (CTMUCONL<7,4>). The input channels can also
be filtered for an edge event sequence (Edge 1 occur-
ring before Edge 2) by setting the EDGSEQEN bit
(CTMUCONH<2>).
dV
C = I •
dT
More simply, the amount of charge measured in
coulombs in a circuit is defined as current in amperes
(I) multiplied by the amount of time in seconds that the
current flows (t). Charge is also defined as the capaci-
tance in farads (C) multiplied by the voltage of the
circuit (V). It follows that:
24.1.4
EDGE STATUS
The CTMUCON register also contains two status bits,
EDG2STAT and EDG1STAT (CTMUCONL<1:0>).
Their primary function is to show if an edge response
has occurred on the corresponding channel. The
CTMU automatically sets a particular bit when an edge
response is detected on its channel. The level-sensitive
nature of the input channels also means that the status
bits become set immediately if the channel’s configura-
tion is changed and is the same as the channel’s
current state.
I • t = C • V
The CTMU module provides a constant, known current
source. The A/D Converter is used to measure (V) in
the equation, leaving two unknowns: capacitance (C)
and time (t). The above equation can be used to calcu-
late capacitance or time, by either relationship using
the known fixed capacitance of the circuit:
The module uses the edge status bits to control the cur-
rent source output to external analog modules (such as
the A/D Converter). Current is only supplied to external
modules when only one (but not both) of the status bits
is set, and shuts current off when both bits are either
set or cleared. This allows the CTMU to measure cur-
rent only during the interval between edges. After both
status bits are set, it is necessary to clear them before
another measurement is taken. Both bits should be
cleared simultaneously, if possible, to avoid re-enabling
the CTMU current source.
t = (C • V)/I
or by:
C = (I • t)/V
using a fixed time that the current source is applied to
the circuit.
24.1.2
CURRENT SOURCE
At the heart of the CTMU is a precision current source,
designed to provide a constant reference for measure-
ments. The level of current is user-selectable across
three ranges or a total of two orders of magnitude, with
the ability to trim the output in ±2% increments
(nominal). The current range is selected by the
IRNG<1:0> bits (CTMUICON<1:0>), with a value of
‘00’ representing the lowest range.
In addition to being set by the CTMU hardware, the
edge status bits can also be set by software. This is
also the user’s application to manually enable or dis-
able the current source. Setting either one (but not
both) of the bits enables the current source. Setting or
clearing both bits at once disables the source.
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Depending on the type of measurement or pulse
generation being performed, one or more additional
modules may also need to be initialized and configured
with the CTMU module:
24.1.5
INTERRUPTS
The CTMU sets its interrupt flag (PIR3<2>) whenever
the current source is enabled, then disabled. An inter-
rupt is generated only if the corresponding interrupt
enable bit (PIE3<2>) is also set. If edge sequencing is
not enabled (i.e., Edge 1 must occur before Edge 2), it
is necessary to monitor the edge status bits, and
determine which edge occurred last and caused the
interrupt.
• Edge Source Generation: In addition to the
external edge input pins, CCPx Special Event
Triggers can be used as edge sources for the
CTMU.
• Capacitance or Time Measurement: The CTMU
module uses the A/D Converter to measure the
voltage across a capacitor that is connected to one
of the analog input channels.
24.2 CTMU Module Initialization
The following sequence is a general guideline used to
initialize the CTMU module:
• Pulse Generation: When generating system clock
independent output pulses, the CTMU module
uses Comparator 2 and the associated
comparator voltage reference.
1. Select the current source range using the IRNG
bits (CTMUICON<1:0>).
2. Adjust the current source trim using the ITRIM
bits (CTMUICON<7:2>).
24.3 Calibrating the CTMU Module
3. Configure the edge input sources for Edge 1 and
Edge 2 by setting the EDG1SEL and EDG2SEL
bits (CTMUCONL<3:2 and 6:5>).
The CTMU requires calibration for precise measure-
ments of capacitance and time, as well as for accurate
time delay. If the application only requires measurement
of a relative change in capacitance or time, calibration is
usually not necessary. An example of this type of appli-
cation would include a capacitive touch switch, in which
the touch circuit has a baseline capacitance and the
added capacitance of the human body changes the
overall capacitance of a circuit.
4. Configure the input polarities for the edge inputs
using the EDG1POL and EDG2POL bits
(CTMUCONL<4,7>). The default configuration
is for negative edge polarity (high-to-low
transitions).
5. Enable edge sequencing using the EDGSEQEN
bit (CTMUCONH<2>). By default, edge
sequencing is disabled.
If actual capacitance or time measurement is required,
two hardware calibrations must take place: the current
source needs calibration to set it to a precise current,
and the circuit being measured needs calibration to
measure and/or nullify all other capacitance other than
that to be measured.
6. Select the operating mode (Measurement or
Time Delay) with the TGEN bit. The default
mode is Time/Capacitance Measurement.
7. Configure the module to automatically trigger
an A/D conversion, when the second edge
event has occurred, using the CTTRIG bit
(CTMUCONH<0>). The conversion trigger is
disabled by default.
24.3.1
CURRENT SOURCE CALIBRATION
The current source on board the CTMU module has a
range of ±60% nominal for each of three current
ranges. Therefore, for precise measurements, it is
possible to measure and adjust this current source by
placing a high-precision resistor, RCAL, onto an unused
analog channel. An example circuit is shown in
Figure 24-2. The current source measurement is
performed using the following steps:
8. Discharge the connected circuit by setting the
IDISSEN bit (CTMUCONH<1>); after waiting a
sufficient time for the circuit to discharge, clear
IDISSEN.
9. Disable the module by clearing the CTMUEN bit
(CTMUCONH<7>).
10. Clear the Edge Status bits, EDG2STAT and
EDG1STAT (CTMUCONL<1:0>).
1. Initialize the A/D Converter.
2. Initialize the CTMU.
11. Enable both edge inputs by setting the EDGEN
bit (CTMUCONH<3>).
3. Enable the current source by setting EDG1STAT
(CTMUCONL<0>).
12. Enable the module by setting the CTMUEN bit.
4. Issue settling time delay.
5. Perform A/D conversion.
6. Calculate the current source current using
I = V/RCAL, where RCAL is a high-precision
resistance and V is measured by performing an
A/D conversion.
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The CTMU current source may be trimmed with the
trim bits in CTMUICON using an iterative process to get
an exact desired current. Alternatively, the nominal
value without adjustment may be used; it may be
stored by the software for use in all subsequent
capacitive or time measurements.
A value of 70% of full-scale voltage is chosen to make
sure that the A/D Converter is in a range that is well
above the noise floor. Keep in mind that if an exact cur-
rent is chosen to incorporate the trimming bits from
CTMUICON, the resistor value of RCAL may need to be
adjusted accordingly. RCAL may be also adjusted to
allow for available resistor values. RCAL should be of
the highest precision available, keeping in mind the
amount of precision needed for the circuit that the
CTMU will be used to measure. A recommended
minimum would be 0.1% tolerance.
To calculate the value for RCAL, the nominal current
must be chosen and then the resistance can be
calculated. For example, if the A/D Converter reference
voltage is 3.3V, use 70% of full scale or 2.31V as the
desired approximate voltage to be read by the A/D
Converter. If the range of the CTMU current source is
selected to be 0.55 A, the resistor value needed is cal-
culated as RCAL = 2.31V/0.55 A for a value of 4.2 MΩ.
Similarly, if the current source is chosen to be 5.5 A,
RCAL would be 420,000Ω, and 42,000Ω if the current
source is set to 55 A.
The following examples show one typical method for
performing a CTMU current calibration. Example 24-1
demonstrates how to initialize the A/D Converter and the
CTMU; this routine is typical for applications using both
modules. Example 24-2 demonstrates one method for
the actual calibration routine. Note that this method
manually triggers the A/D Converter. This is done to
demonstrate the entire stepwise process. It is also
possible to automatically trigger the conversion by
setting the CTMU’s CTTRIG bit (CTMUCONH<0>).
FIGURE 24-2:
CTMU CURRENT SOURCE
CALIBRATION CIRCUIT
PIC18F87J90
CTMU
Current Source
A/D
Trigger
A/D Converter
ANx
A/D
RCAL
MUX
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EXAMPLE 24-1:
SETUP FOR CTMU CALIBRATION ROUTINES
#include "p18cxxx.h"
/**************************************************************************/
/*Setup CTMU *****************************************************************/
/**************************************************************************/
void setup(void)
{ //CTMUCON - CTMU Control register
CTMUCONH = 0x00;
CTMUCONL = 0X90;
//make sure CTMU is disabled
//CTMU continues to run when emulator is stopped,CTMU continues
//to run in idle mode,Time Generation mode disabled, Edges are blocked
//No edge sequence order, Analog current source not grounded, trigger
//output disabled, Edge2 polarity = positive level, Edge2 source =
//source 0, Edge1 polarity = positive level, Edge1 source = source 0,
// Set Edge status bits to zero
//CTMUICON - CTMU Current Control Register
CTMUICON = 0x01;
//0.55uA, Nominal - No Adjustment
/**************************************************************************/
//Setup AD converter;
/**************************************************************************/
TRISA=0x04;
//set channel 2 as an input
// ADCON2
ADCON2bits.ADFM=1;
ADCON2bits.ACQT=1;
ADCON2bits.ADCS=2;
// Resulst format 1= Right justified
// Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD
// Clock conversion bits 6= FOSC/64 2=FOSC/32
// ADCON1
ADCON1bits.ADCAL=0;
ADCON1bits.PCFG=0xC;
// Normal A/D conversion operation
// Configures AN0 to AN2 as analog
// ADCON0
ADCON0bits.VCFG0 =0;
ADCON0bits.VCFG1 =0;
ADCON0bits.CHS=2;
// Vref+ = AVdd
// Vref- = AVss
// Select ADC channel
ADCON0bits.ADON=1;
// Turn on ADC
}
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EXAMPLE 24-2:
CURRENT CALIBRATION ROUTINE
#include "p18cxxx.h"
#define COUNT 500
//@ 8MHz = 125uS.
#define DELAY for(i=0;i<COUNT;i++)
#define RCAL .027
//R value is 4200000 (4.2M)
//scaled so that result is in
//1/100th of uA
#define ADSCALE 1023
#define ADREF 3.3
//for unsigned conversion 10 sig bits
//Vdd connected to A/D Vr+
int main(void)
{
int i;
int j = 0; //index for loop
unsigned int Vread = 0;
double VTot = 0;
float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs
//assume CTMU and A/D have been setup correctly
//see Example 25-1 for CTMU & A/D setup
setup();
CTMUCONHbits.CTMUEN = 1;
//Enable the CTMU
for(j=0;j<10;j++)
{
CTMUCONHbits.IDISSEN = 1;
DELAY;
//drain charge on the circuit
//wait 125us
CTMUCONHbits.IDISSEN = 0;
//end drain of circuit
CTMUCONLbits.EDG1STAT = 1;
//Begin charging the circuit
//using CTMU current source
//wait for 125us
DELAY;
CTMUCONLbits.EDG1STAT = 0;
//Stop charging circuit
PIR1bits.ADIF = 0;
ADCON0bits.GO=1;
//make sure A/D Int not set
//and begin A/D conv.
while(!PIR1bits.ADIF);
//Wait for A/D convert complete
Vread = ADRES;
PIR1bits.ADIF = 0;
VTot += Vread;
//Get the value from the A/D
//Clear A/D Interrupt Flag
//Add the reading to the total
}
Vavg = (float)(VTot/10.000);
Vcal = (float)(Vavg/ADSCALE*ADREF);
CTMUISrc = Vcal/RCAL;
//Average of 10 readings
//CTMUISrc is in 1/100ths of uA
}
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This measured value is then stored and used for
calculations of time measurement or subtracted for
capacitance measurement. For calibration, it is
expected that the capacitance of CSTRAY + CAD is
approximately known; CAD is approximately 4 pF.
24.3.2
CAPACITANCE CALIBRATION
There is a small amount of capacitance from the inter-
nal A/D Converter sample capacitor as well as stray
capacitance from the circuit board traces and pads that
affect the precision of capacitance measurements. A
measurement of the stray capacitance can be taken by
making sure the desired capacitance to be measured
has been removed. The measurement is then
performed using the following steps:
An iterative process may need to be used to adjust the
time, t, that the circuit is charged to obtain a reasonable
voltage reading from the A/D Converter. The value of t
may be determined by setting COFFSET to a theoretical
value, then solving for t. For example, if CSTRAY is
theoretically calculated to be 11 pF, and V is expected
to be 70% of VDD, or 2.31V, then t would be:
1. Initialize the A/D Converter and the CTMU.
2. Set EDG1STAT (= 1).
3. Wait for a fixed delay of time, t.
4. Clear EDG1STAT.
(4 pF + 11 pF) • 2.31V/0.55 A
5. Perform an A/D conversion.
or 63 s.
6. Calculate the stray and A/D sample capacitances:
See Example 24-3 for a typical routine for CTMU
capacitance calibration.
COFFSET = CSTRAY + CAD = (I • t)/V
where I is known from the current source measurement
step, t is a fixed delay and V is measured by performing
an A/D conversion.
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EXAMPLE 24-3:
CAPACITANCE CALIBRATION ROUTINE
#include "p18cxxx.h"
#define COUNT 25
//@ 8MHz INTFRC = 62.5 us.
//time in uS
#define ETIME COUNT*2.5
#define DELAY for(i=0;i<COUNT;i++)
#define ADSCALE 1023
#define ADREF 3.3
//for unsigned conversion 10 sig bits
//Vdd connected to A/D Vr+
//R value is 4200000 (4.2M)
//scaled so that result is in
//1/100th of uA
#define RCAL .027
int main(void)
{
int i;
int j = 0;
//index for loop
unsigned int Vread = 0;
float CTMUISrc, CTMUCap, Vavg, VTot, Vcal;
//assume CTMU and A/D have been setup correctly
//see Example 25-1 for CTMU & A/D setup
setup();
CTMUCONHbits.CTMUEN = 1;
//Enable the CTMU
for(j=0;j<10;j++)
{
CTMUCONHbits.IDISSEN = 1;
DELAY;
//drain charge on the circuit
//wait 125us
CTMUCONHbits.IDISSEN = 0;
//end drain of circuit
CTMUCONLbits.EDG1STAT = 1;
//Begin charging the circuit
//using CTMU current source
//wait for 125us
DELAY;
CTMUCONLbits.EDG1STAT = 0;
//Stop charging circuit
PIR1bits.ADIF = 0;
ADCON0bits.GO=1;
//make sure A/D Int not set
//and begin A/D conv.
while(!PIR1bits.ADIF);
//Wait for A/D convert complete
Vread = ADRES;
PIR1bits.ADIF = 0;
VTot += Vread;
//Get the value from the A/D
//Clear A/D Interrupt Flag
//Add the reading to the total
}
Vavg = (float)(VTot/10.000);
Vcal = (float)(Vavg/ADSCALE*ADREF);
CTMUISrc = Vcal/RCAL;
//Average of 10 readings
//CTMUISrc is in 1/100ths of uA
CTMUCap = (CTMUISrc*ETIME/Vcal)/100;
}
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24.4.2
RELATIVE CHARGE
MEASUREMENT
24.4 Measuring Capacitance with the
CTMU
An application may not require precise capacitance
measurements. For example, when detecting a valid
press of a capacitance-based switch, detecting a relative
change of capacitance is of interest. In this type of appli-
cation, when the switch is open (or not touched), the total
capacitance is the capacitance of the combination of the
board traces, the A/D Converter, etc. A larger voltage will
be measured by the A/D Converter. When the switch is
closed (or is touched), the total capacitance is larger due
to the addition of the capacitance of the human body to
the above listed capacitances and a smaller voltage will
be measured by the A/D Converter.
There are two separate methods of measuring capaci-
tance with the CTMU. The first is the absolute method,
in which the actual capacitance value is desired. The
second is the relative method, in which the actual
capacitance is not needed, rather an indication of a
change in capacitance is required.
24.4.1
ABSOLUTE CAPACITANCE
MEASUREMENT
For absolute capacitance measurements, both the
current and capacitance calibration steps found in
Section 24.3 “Calibrating the CTMU Module” should
be followed. Capacitance measurements are then
performed using the following steps:
Detecting capacitance changes is easily accomplished
with the CTMU using these steps:
1. Initialize the A/D Converter and the CTMU.
2. Set EDG1STAT.
1. Initialize the A/D Converter.
2. Initialize the CTMU.
3. Set EDG1STAT.
3. Wait for a fixed delay.
4. Clear EDG1STAT.
4. Wait for a fixed delay, T.
5. Clear EDG1STAT.
5. Perform an A/D conversion.
The voltage measured by performing the A/D conver-
sion is an indication of the relative capacitance. Note
that in this case, no calibration of the current source or
circuit capacitance measurement is needed. See
Example 24-4 for a sample software routine for a
capacitive touch switch.
6. Perform an A/D conversion.
7. Calculate the total capacitance, CTOTAL = (I * T)/V,
where I is known from the current source
measurement step (Section 24.3.1 “Current
Source Calibration”), T is a fixed delay and V is
measured by performing an A/D conversion.
8. Subtract the stray and A/D capacitance
(COFFSET from Section 24.3.2 “Capacitance
Calibration”) from CTOTAL to determine the
measured capacitance.
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EXAMPLE 24-4:
ROUTINE FOR CAPACITIVE TOUCH SWITCH
#include "p18cxxx.h"
#define COUNT 500
//@ 8MHz = 125uS.
#define DELAY for(i=0;i<COUNT;i++)
#define OPENSW 1000
#define TRIP 300
//Un-pressed switch value
//Difference between pressed
//and un-pressed switch
//amount to change
#define HYST 65
//from pressed to un-pressed
#define PRESSED 1
#define UNPRESSED 0
int main(void)
{
unsigned int Vread;
unsigned int switchState;
int i;
//storage for reading
//assume CTMU and A/D have been setup correctly
//see Example 25-1 for CTMU & A/D setup
setup();
CTMUCONHbits.CTMUEN = 1;
//Enable the CTMU
CTMUCONHbits.IDISSEN = 1;
DELAY;
//drain charge on the circuit
//wait 125us
CTMUCONHbits.IDISSEN = 0;
//end drain of circuit
CTMUCONLbits.EDG1STAT = 1;
//Begin charging the circuit
//using CTMU current source
//wait for 125us
DELAY;
CTMUCONLbits.EDG1STAT = 0;
//Stop charging circuit
PIR1bits.ADIF = 0;
ADCON0bits.GO=1;
//make sure A/D Int not set
//and begin A/D conv.
while(!PIR1bits.ADIF);
//Wait for A/D convert complete
Vread = ADRES;
//Get the value from the A/D
if(Vread < OPENSW - TRIP)
{
switchState = PRESSED;
}
else if(Vread > OPENSW - TRIP + HYST)
{
switchState = UNPRESSED;
}
}
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It is assumed that the time measured is small enough
that the capacitance, COFFSET, provides a valid voltage
to the A/D Converter. For the smallest time measure-
ment, always set the A/D Channel Select register
(AD1CHS) to an unused A/D channel; the correspond-
ing pin for which is not connected to any circuit board
trace. This minimizes added stray capacitance,
keeping the total circuit capacitance close to that of the
A/D Converter itself (25 pF). To measure longer time
intervals, an external capacitor may be connected to an
A/D channel and this channel selected when making a
time measurement.
24.5 Measuring Time with the CTMU
Module
Time can be precisely measured after the ratio (C/I) is
measured from the current and capacitance calibration
step by following these steps:
1. Initialize the A/D Converter and the CTMU.
2. Set EDG1STAT.
3. Set EDG2STAT.
4. Perform an A/D conversion.
5. Calculate the time between edges as T = (C/I) * V,
where I is calculated in the current calibration step
(Section 24.3.1 “Current Source Calibration”),
C is calculated in the capacitance calibration step
(Section 24.3.2 “Capacitance Calibration”) and
V is measured by performing the A/D conversion.
FIGURE 24-3:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR
TIME MEASUREMENT
PIC18F87J90
CTMU
CTEDG1
CTEDG2
EDG1
Current Source
EDG2
Output
Pulse
A/D Converter
ANX
RPR
CAD
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An example use of this feature is for interfacing with
variable capacitive-based sensors, such as a humidity
sensor. As the humidity varies, the pulse-width output
on CTPLS will vary. The CTPLS output pin can be
connected to an input capture pin and the varying pulse
width is measured to determine the humidity in the
application.
24.6 Creating a Delay with the CTMU
Module
A unique feature on board the CTMU module is its ability
to generate system clock independent output pulses
based on an external capacitor value. This is accom-
plished using the internal comparator voltage reference
module, Comparator 2 input pin and an external capaci-
tor. The pulse is output onto the CTPLS pin. To enable
this mode, set the TGEN bit.
Follow these steps to use this feature:
1. Initialize Comparator 2.
2. Initialize the comparator voltage reference.
See Figure 24-4 for an example circuit. CPULSE is
chosen by the user to determine the output pulse width
on CTPLS. The pulse width is calculated by
T = (CPULSE/I)*V, where I is known from the current
source measurement step (Section 24.3.1 “Current
Source Calibration”) and V is the internal reference
voltage (CVREF).
3. Initialize the CTMU and enable time delay
generation by setting the TGEN bit.
4. Set EDG1STAT.
5. When CPULSE charges to the value of the voltage
reference trip point, an output pulse is generated
on CTPLS.
FIGURE 24-4:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
PIC18F87J90
CTMU
CTEDG1
EDG1
CTPLS
Current Source
Comparator
C2
C2INB
CDELAY
CVREF
24.7 Operation During Sleep/Idle Modes
24.8 Effects of a Reset on CTMU
Upon Reset, all registers of the CTMU are cleared. This
leaves the CTMU module disabled, its current source is
turned off and all configuration options return to their
default settings. The module needs to be re-initialized
following any Reset.
24.7.1
SLEEP MODE AND DEEP SLEEP
MODES
When the device enters any Sleep mode, the CTMU
module current source is always disabled. If the CTMU
is performing an operation that depends on the current
source when Sleep mode is invoked, the operation may
not terminate correctly. Capacitance and time
measurements may return erroneous values.
If the CTMU is in the process of taking a measurement
at the time of Reset, the measurement will be lost. A
partial charge may exist on the circuit that was being
measured and should be properly discharged before
the CTMU makes subsequent attempts to make a
measurement. The circuit is discharged by setting and
then clearing the IDISSEN bit (CTMUCONH<1>) while
the A/D Converter is connected to the appropriate
channel.
24.7.2
IDLE MODE
The behavior of the CTMU in Idle mode is determined
by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL
is cleared, the module will continue to operate in Idle
mode. If CTMUSIDL is set, the module’s current source
is disabled when the device enters Idle mode. If the
module is performing an operation when Idle mode is
invoked, in this case, the results will be similar to those
with Sleep mode.
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The CTMUCONH and CTMUCONL registers
(Register 24-1 and Register 24-2) contain control bits
for configuring the CTMU module edge source selec-
tion, edge source polarity selection, edge sequencing,
A/D trigger, analog circuit capacitor discharge and
enables. The CTMUICON register (Register 24-3) has
bits for selecting the current source range and current
source trim.
24.9 Registers
There are three control registers for the CTMU:
• CTMUCONH
• CTMUCONL
• CTMUICON
REGISTER 24-1: CTMUCONH: CTMU CONTROL HIGH REGISTER
R/W-0
U-0
—
R/W-0
R/W-0
TGEN
R/W-0
R/W-0
R/W-0
R/W-0
CTMUEN
CTMUSIDL
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CTMUEN: CTMU Enable bit
1= Module is enabled
0= Module is disabled
bit 6
bit 5
Unimplemented: Read as ‘0’
CTMUSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 4
bit 3
bit 2
bit 1
bit 0
TGEN: Time Generation Enable bit
1= Enables edge delay generation
0= Disables edge delay generation
EDGEN: Edge Enable bit
1= Edges are not blocked
0= Edges are blocked
EDGSEQEN: Edge Sequence Enable bit
1= Edge 1 event must occur before Edge 2 event can occur
0= No edge sequence is needed
IDISSEN: Analog Current Source Control bit
1= Analog current source output is grounded
0= Analog current source output is not grounded
CTTRIG: Trigger Control bit
1= Trigger output is enabled
0= Trigger output is disabled
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REGISTER 24-2: CTMUCONL: CTMU CONTROL LOW REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG2POL
EDG2SEL1 EDG2SEL0
EDG1POL
EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EDG2POL: Edge 2 Polarity Select bit
1= Edge 2 programmed for a positive edge response
0= Edge 2 programmed for a negative edge response
bit 6-5
EDG2SEL<1:0>: Edge 2 Source Select bits
11= CTEDG1 pin
10= CTEDG2 pin
01= CCP1 Special Event Trigger
00= CCP2 Special Event Trigger
bit 4
EDG1POL: Edge 1 Polarity Select bit
1= Edge 1 programmed for a positive edge response
0= Edge 1 programmed for a negative edge response
bit 3-2
EDG1SEL<1:0>: Edge 1 Source Select bits
11= CTEDG1 pin
10= CTEDG2 pin
01= CCP1 Special Event Trigger
00= CCP2 Special Event Trigger
bit 1
bit 0
EDG2STAT: Edge 2 Status bit
1= Edge 2 event has occurred
0= Edge 2 event has not occurred
EDG1STAT: Edge 1 Status bit
1= Edge 1 event has occurred
0= Edge 1 event has not occurred
DS39933D-page 322
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 24-3: CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRNG1
R/W-0
IRNG0
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-2
ITRIM<5:0>: Current Source Trim bits
011111= Maximum positive change from nominal current
011110
.
.
.
000001= Minimum positive change from nominal current
000000= Nominal current output specified by IRNG<1:0>
111111= Minimum negative change from nominal current
.
.
.
100010
100001= Maximum negative change from nominal current
bit 1-0
IRNG<1:0>: Current Source Range Select bits
11= 100 x Base current
10= 10 x Base current
01= Base current level (0.55 A nominal)
00= Current source disabled
TABLE 24-1: REGISTERS ASSOCIATED WITH CTMU MODULE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page:
CTMUCONH CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN IDISSEN
CTTRIG
—
—
—
CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
CTMUICON
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
2010 Microchip Technology Inc.
DS39933D-page 323
PIC18F87J90 FAMILY
NOTES:
DS39933D-page 324
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
25.1.1
CONSIDERATIONS FOR
CONFIGURING PIC18F87J90
FAMILY DEVICES
25.0 SPECIAL FEATURES OF THE
CPU
PIC18F87J90 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
Devices of the PIC18F87J90 family do not use persis-
tent memory registers to store configuration information.
The configuration bytes are implemented as volatile
memory which means that configuration data must be
programmed each time the device is powered up.
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Configuration data is stored in the four words at the top
of the on-chip program memory space, known as the
Flash Configuration Words. It is stored in program
memory in the same order shown in Table 25-2, with
CONFIG1L at the lowest address and CONFIG3H at
the highest. The data is automatically loaded in the
proper Configuration registers during device power-up.
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 3.0
“Oscillator Configurations”.
The volatile memory cells used for the Configuration
bits always reset to ‘1’ on Power-on Resets. For all
other types of Reset events, the previously
programmed values are maintained and used without
reloading from program memory.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
The four Most Significant bits of CONFIG1H,
CONFIG2H and CONFIG3H in program memory
should also be ‘1111’. This makes these Configuration
Words appear to be NOP instructions in the remote
event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F87J90 family of
devices have a configurable Watchdog Timer which is
controlled in software.
The inclusion of an Internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
TABLE 25-1: MAPPING OF THE FLASH
CONFIGURATION WORDS TO
THE CONFIGURATION
25.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped, starting
at program memory location, 300000h. A complete list
is shown in Table 25-2. A detailed explanation of the
various bit functions is provided in Register 25-1
through Register 25-6.
REGISTERS
Configuration
Configuration
Byte
Code Space
Address
Register
Address
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3L
CONFIG3H
XXXF8h
XXXF9h
XXXFAh
XXXFBh
XXXFCh
XXXFDh
300000h
300001h
300002h
300003h
300004h
300005h
2010 Microchip Technology Inc.
DS39933D-page 325
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TABLE 25-2: CONFIGURATION BITS AND DEVICE IDs
Default/
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unprogrammed
(1)
Value
300000h CONFIG1L DEBUG
XINST
STVREN
—
—
—
—
—
WDTEN
—
111- ---1
---- 01--
11-1 1111
(2)
(2)
(2)
(2)
(3)
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300004h CONFIG3L
300005h CONFIG3H
3FFFFEh DEVID1
—
—
—
—
—
CP0
IESO
(2)
FCMEN
—
LPT1OSC T1DIG
FOSC2
FOSC1
FOSC0
(2)
(2)
(2)
—
—
—
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111
(2)
(2)
(2)
(2)
(2)
—
—
—
—
—
RTCOSC
—
—
---- --1-
(2)
(2)
(2)
—
—
—
—
—
CCP2MX ---- ---1
(4)
(4)
DEV2
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
0000 10x1
3FFFFFh DEVID2
DEV10
Legend:
x= unknown, -= unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset
states, the configuration bytes maintain their previously programmed states.
2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOPif it
is accidentally executed.
3: This bit should always be maintained as ‘0’.
4: See Register 25-7 and Register 25-8 for DEVID values. These registers are read-only and cannot be programmed by
the user.
DS39933D-page 326
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 25-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1
DEBUG
R/WO-1
XINST
R/WO-1
U-0
—
U-0
—
U-0
—
U-0
—
R/WO-1
WDTEN
STVREN
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
DEBUG: Background Debugger Enable bit
1= Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1= Instruction set extension and Indexed Addressing mode enabled
0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
STVREN: Stack Overflow/Underflow Reset Enable bit
1= Reset on stack overflow/underflow enabled
0= Reset on stack overflow/underflow disabled
bit 4-1
bit 0
Unimplemented: Read as ‘0’
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on SWDTEN bit)
REGISTER 25-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-0
U-0
U-0
U-0
U-0
R/WO-1
CP0
U-0
—
U-0
—
(1)
(1)
(1)
(1)
(2)
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7-3
bit 2
Unimplemented: Read as ‘0’
CP0: Code Protection bit
1= Program memory is not code-protected
0= Program memory is code-protected
bit 1-0
Unimplemented: Read as ‘0’
Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOPif it is accidentally executed.
2: This bit should always be maintained as ‘0’.
2010 Microchip Technology Inc.
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REGISTER 25-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
R/WO-1
IESO
R/WO-1
FCMEN
U-0
—
R/WO-1
R/WO-1
T1DIG
R/WO-1
FOSC2
R/WO-1
FOSC1
R/WO-1
FOSC0
LPT1OSC
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7
bit 6
IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1= Two-Speed Start-up enabled
0= Two-Speed Start-up disabled
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
bit 5
bit 4
Unimplemented: Read as ‘0’
LPT1OSC: T1OSC/SOSC Power Selection Configuration bit
1= High-power T1OSC/SOSC circuit selected
0= Low-power T1OSC/SOSC circuit selected
bit 3
T1DIG: T1CKI for Digital Input Clock Enable bit
1= T1CKI is available as a digital input without enabling T1OSCEN
0= T1CKI is not available as a digital input without enabling T1OSCEN
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111= ECPLL OSC1/OSC2 as primary; ECPLL oscillator with PLL enabled; CLKO on RA6
110= EC OSC1/OSC2 as primary; external clock with FOSC/4 output
101= HSPLL OSC1/OSC2 as primary; high-speed crystal/resonator with software PLL control
100= HS OSC1/OSC2 as primary; high-speed crystal/resonator
011= INTPLL1 internal oscillator block with software PLL control; FOSC/4 output
010= INTIO1 internal oscillator block with FOSC/4 output on RA6 and I/O on RA7
001= INTPLL2 internal oscillator block with software PLL control and I/O on RA6 and RA7
000= INTIO2 internal oscillator block with I/O on RA6 and RA7
DS39933D-page 328
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
REGISTER 25-4:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
U-0
U-0
U-0
R/WO-1
R/WO-1
R/WO-1
R/WO-1
(1)
(1)
(1)
(1)
—
—
—
—
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOPif it is accidentally executed.
REGISTER 25-5:
CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)
U-0
U-0
U-0
U-0
U-0
—
U-0
—
R/WO-1
U-0
—
(1)
(1)
(1)
(1)
—
—
—
—
RTCOSC
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7-2
bit 1
Unimplemented: Read as ‘0’
RTCOSC: RTCC Reference Clock Select bit
1= RTCC uses T1OSC/T1CKI as the reference clock
0= RTCC uses INTRC as the reference clock
bit 0
Unimplemented: Read as ‘0’
Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOPif it is accidentally executed.
2010 Microchip Technology Inc.
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REGISTER 25-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-0
U-0
U-0
U-0
U-0
—
U-0
—
U-0
—
R/WO-1
(1)
(1)
(1)
(1)
—
—
—
—
CCP2MX
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7-1
bit 0
Unimplemented: Read as ‘0’
CCP2MX: CCP2 MUX bit
1= CCP2 is multiplexed with RC1
0= CCP2 is multiplexed with RE7
Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOPif it is accidentally executed.
REGISTER 25-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F87J90 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 0
bit 7
Legend:
R = Read-only bit
bit 7-5
DEV<2:0>: Device ID bits
101= PIC18F87J90
100= PIC18F86J90
001= PIC18F67J90
000= PIC18F66J90
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 25-8: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F87J90 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV10(1)
DEV9(1)
DEV8(1)
DEV7(1)
DEV6(1)
DEV5(1)
DEV4(1)
DEV3(1)
bit 7
bit 0
Legend:
R = Read-only bit
bit 7-0
DEV<10:3>: Device ID bits(1)
These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
0101 0000= PIC18F87J90 family devices
Note 1: The values for DEV<10:3> may be shared with other device families. The specific device is always
identified by using the entire DEV<10:0> bit sequence.
DS39933D-page 330
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
25.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F87J90 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period is
4 ms and has the same stability as the INTRC oscillator.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEPor
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
25.2.1
CONTROL REGISTER
The WDTCON register (Register 25-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
FIGURE 25-1:
WDT BLOCK DIAGRAM
Enable WDT
SWDTEN
INTRC Control
WDT Counter
Wake-up from
Power-Managed
Modes
128
INTRC Oscillator
WDT
Reset
Reset
CLRWDT
All Device Resets
Programmable Postscaler
1:1 to 1:32,768
WDT
4
WDTPS<3:0>
Sleep
2010 Microchip Technology Inc.
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REGISTER 25-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
REGSLP(1)
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN(2)
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
REGSLP: Voltage Regulator Low-Power Operation Enable bit(1)
1= On-chip regulator enters low-power operation when device enters Sleep mode
0= On-chip regulator continues to operate normally in Sleep mode
bit 6-1
bit 0
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit(2)
1= Watchdog Timer is on
0= Watchdog Timer is off
Note 1: The REGSLP bit is automatically cleared when a Low-Voltage Detect condition occurs.
2: This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 25-3: SUMMARY OF WATCHDOG TIMER REGISTERS
ResetValues
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCON
WDTCON
IPEN
—
—
CM
—
RI
—
TO
—
PD
—
POR
—
BOR
60
60
REGSLP
SWDTEN
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
DS39933D-page 332
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 25-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
25.3 On-Chip Voltage Regulator
All of the PIC18F87J90 family devices power their core
digital logic at a nominal 2.5V. For designs that are
required to operate at a higher typical voltage, such as
3.3V, all devices in the PIC18F87J90 family incorporate
an on-chip regulator that allows the device to run its
core logic from VDD.
Regulator Enabled (ENVREG tied to VDD):
3.3V
PIC18F87J90
VDD
ENVREG
VDDCORE/VCAP
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn, pro-
vides power to the core from the other VDD pins. When
the regulator is enabled, a low-ESR filter capacitor
must be connected to the VDDCORE/VCAP pin
(Figure 25-2). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Section 28.3 “DC Characteristics:
PIC18F87J90 Family (Industrial)”.
CF
VSS
Regulator Disabled (ENVREG tied to ground):
(1)
(1)
2.5V
3.3V
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic at a nomi-
nal 2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 25-2 for possible
configurations.
PIC18F87J90
VDD
ENVREG
VDDCORE/VCAP
VSS
25.3.1
VOLTAGE REGULATION AND
LOW-VOLTAGE DETECTION
Regulator Disabled (VDD tied to VDDCORE):
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic. The regulator can provide this level from a VDD of
about 2.5V, all the way up to the device’s VDDMAX. It
does not have the capability to boost VDD levels below
2.5V.
(1)
2.5V
PIC18F87J90
VDD
ENVREG
VDDCORE/VCAP
VSS
In order to prevent “brown-out” conditions when the
voltage drops too low for the regulator, the regulator
enters Tracking mode. In Tracking mode, the regulator
output follows VDD with a typical voltage drop of
100 mV.
The on-chip regulator includes a simple Low-Voltage
Detect (LVD) circuit. If VDD drops too low to maintain
approximately 2.45V on VDDCORE, the circuit sets the
Low-Voltage Detect Interrupt Flag, LVDIF (PIR2<2>),
and clears the REGSLP (WDTCON<7>) bit, if it was
set.
Note 1: These are typical operating voltages. For the
full operating ranges of VDD and VDDCORE,
refer to Section 28.1 “DC Characteristics:
Supply Voltage PIC18F87J90 Family
(Industrial)”.
This can be used to generate an interrupt and put the
application into a low-power operational mode, or trig-
ger an orderly shutdown. Low-Voltage Detection is only
available when the regulator is enabled.
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
The REGSLP bit is automatically cleared by hardware
when a Low-Voltage Detect condition occurs. The
REGSLP bit can be set again in software, which would
continue to keep the voltage regulator in Low-Power
mode. This, however, is not recommended if any write
operations to the Flash will be performed.
25.3.2
ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled, PIC18F87J90
family devices also have a simple Brown-out Reset
capability. If the voltage supplied to the regulator falls to
a level that is inadequate to maintain a regulated output
for full-speed operation, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR flag bit (RCON<0>).
25.4 Two-Speed Start-up
The operation of the BOR is described in more detail in
Section 5.4 “Brown-out Reset (BOR)” and
Section 5.4.1 “Detecting BOR”.
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
25.3.3
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
Two-Speed Start-up should be enabled only if the
Primary Oscillator mode is HS or HSPLL
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an OST start-up delay,
Two-Speed Start-up should be disabled.
25.3.4
OPERATION IN SLEEP MODE
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
When enabled, the on-chip regulator always consumes
a small incremental amount of current over IDD. This
includes when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be configured
to automatically disable itself whenever the device
goes into Sleep mode. This feature is controlled by the
REGSLP bit (WDTCON<7>). Setting this bit disables
the regulator in Sleep mode, and reduces its current
consumption to a minimum.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
Substantial Sleep mode power savings can be
obtained by setting the REGSLP bit, but device
wake-up time will increase in order to ensure the
regulator has enough time to stabilize.
FIGURE 25-3:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTRC
OSC1
(1)
(1)
TOST
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
Wake from Interrupt Event
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39933D-page 334
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Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 25-5). This causes the following:
25.4.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 4.1.4 “Multiple Sleep Commands”). In prac-
tice, this means that user code can change the
SCS<1:0> bits setting or issue SLEEP instructions
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
• the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);
• the device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the Fail-Safe
condition); and
• the WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing-sensitive applications. In these cases, it may
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 4.1.4 “Multiple
Sleep Commands” and Section 25.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
25.5 Fail-Safe Clock Monitor
The FSCM will detect failures of the primary or secondary
clock sources only. If the internal oscillator block fails, no
failure would be detected, nor would any action be
possible.
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN Configuration
bit.
25.5.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provides
a backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 25-4) is accomplished by
creating a sample clock signal which is the INTRC out-
put divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor
(CM) latch. The CM is set on the falling edge of the
device clock source but cleared on the rising edge of
the sample clock.
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected; this may
mean a substantial change in the speed of code execu-
tion. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
Fail-Safe Clock Monitor events also reset the WDT and
postscaler, allowing it to start timing from when execu-
tion speed was changed and decreasing the likelihood
of an erroneous time-out.
FIGURE 25-4:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTRC source.
Peripheral
Clock
S
C
Q
Q
INTRC
Source
÷ 64
488 Hz
(2.048 ms)
(32 s)
Clock
Failure
Detected
2010 Microchip Technology Inc.
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FIGURE 25-5:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
Device
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
25.5.2
EXITING FAIL-SAFE OPERATION
25.5.4
POR OR WAKE-UP FROM SLEEP
The Fail-Safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 2H (with any
required start-up delays that are required for the oscil-
lator mode, such as the OST or PLL timer). The INTRC
oscillator provides the device clock until the primary
clock source becomes ready (similar to a Two-Speed
Start-up). The clock source is then switched to the
primary clock (indicated by the OSTS bit in the
OSCCON register becoming set). The Fail-Safe Clock
Monitor then resumes monitoring the peripheral clock.
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is either EC or INTRC mode, monitoring
can begin immediately following these events.
For HS or HSPLL modes, the situation is somewhat dif-
ferent. Since the oscillator may require a start-up time
considerably longer than the FSCM sample clock time,
a false clock failure may be detected. To prevent this,
the internal oscillator block is automatically configured
as the device clock and functions until the primary clock
is stable (the OST and PLL timers have timed out). This
is identical to Two-Speed Start-up mode. Once the
primary clock is stable, the INTRC returns to its role as
the FSCM source.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTOSC multiplexor. The OSCCON register will remain
in its Reset state until a power-managed mode is
entered.
Note:
The same logic that prevents false
oscillator failure interrupts on POR, or
wake from Sleep, will also prevent the
detection of the oscillator’s failure to start
at all following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
25.5.3
FSCM INTERRUPTS IN
POWER-MANAGED MODES
By entering a power-managed mode, the clock
multiplexor selects the clock source selected by the
OSCCON register. Fail-Safe Clock Monitoring of the
power-managed clock source resumes in the
power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTRC multiplexor. An automatic transition back
to the failed clock source will not occur.
As noted in Section 25.4.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
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25.6 Program Verification and
Code Protection
25.7
In-Circuit Serial Programming
PIC18F87J90 family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
For all devices in the PIC18F87J90 family of devices,
the on-chip program memory space is treated as a
single block. Code protection for this block is controlled
by one Configuration bit, CP0. This bit inhibits external
reads and writes to the program memory space. It has
no direct effect in normal execution mode.
25.6.1
CONFIGURATION REGISTER
PROTECTION
25.8 In-Circuit Debugger
The Configuration registers are protected against
untoward changes or reads in two ways. The primary
protection is the write-once feature of the Configuration
bits which prevents reconfiguration once the bit has
been programmed during a power cycle. To safeguard
against unpredictable events, Configuration bit
changes resulting from individual cell-level disruptions
(such as ESD events) will cause a parity error and
trigger a device Reset.
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 25-4 shows which resources are
required by the background debugger.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the CP0 bit set, the source data for device
configuration is also protected as a consequence.
TABLE 25-4: DEBUGGER RESOURCES
I/O pins:
RB6, RB7
2 levels
Stack:
Program Memory:
Data Memory:
512 bytes
10 bytes
2010 Microchip Technology Inc.
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NOTES:
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2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
The literal instructions may use some of the following
operands:
26.0 INSTRUCTION SET SUMMARY
The PIC18F87J90 family of devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimiza-
tion of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
26.1 Standard Instruction Set
The control instructions may use some of the following
operands:
The standard PIC18 MCU instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from these
PIC MCU instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 26-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 26-1 shows the opcode field
descriptions.
The double-word instructions execute in two instruction
cycles.
Most byte-oriented instructions have three operands:
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
1. The file register (specified by ‘f’)
2. The destination of the result (specified by ‘d’)
3. The accessed memory (specified by ‘a’)
The file register designator, ‘f’, specifies which file reg-
ister is to be used by the instruction. The destination
designator, ‘d’, specifies where the result of the
operation is to be placed. If ‘d’ is zero, the result is
placed in the WREG register. If ‘d’ is one, the result is
placed in the file register specified in the instruction.
Figure 26-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 26-2,
lists the standard instructions recognized by the
Microchip MPASMTM Assembler.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
Section 26.1.1 “Standard Instruction Set” provides
a description of each instruction.
2. The bit in the file register (specified by ‘b’)
3. The accessed memory (specified by ‘a’)
The bit field designator, ‘b’, selects the number of the bit
affected by the operation, while the file register desig-
nator, ‘f’, represents the number of the file in which the
bit is located.
2010 Microchip Technology Inc.
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TABLE 26-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
C, DC, Z, OV, N
d
Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination: either the WREG register or the specified register file location.
8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h).
12-bit Register file address (000h to FFFh). This is the source address.
12-bit Register file address (000h to FFFh). This is the destination address.
Global Interrupt Enable bit.
f
f
s
d
GIE
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No Change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Power-Down bit.
PCH
PCLATH
PCLATU
PD
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
TABLAT
TO
21-bit Table Pointer (points to a Program Memory location).
8-bit Table Latch.
Time-out bit.
TOS
u
Top-of-Stack.
Unused or Unchanged.
Watchdog Timer.
WDT
WREG
x
Working register (accumulator).
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
z
z
{
7-bit offset value for Indirect Addressing of register files (source).
7-bit offset value for Indirect Addressing of register files (destination).
Optional argument.
s
d
}
[text]
(text)
[expr]<n>
Indicates an Indexed Address.
The contents of text.
Specifies bit nof the register indicated by the pointer expr.
Assigned to.
< >
Register bit field.
In the set of.
italics
User-defined term (font is Courier New).
DS39933D-page 340
2010 Microchip Technology Inc.
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FIGURE 26-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10
Example Instruction
9
8
7
0
ADDWF MYREG, W, B
OPCODE
d
a
f (FILE #)
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
MOVFF MYREG1, MYREG2
OPCODE
f (Source FILE #)
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 7Fh
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTOand Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
S
n<7:0> (literal)
0
1111
S = Fast bit
n<19:8> (literal)
15
15
11 10
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
n<7:0> (literal)
8 7
OPCODE
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
TABLE 26-2: PIC18F87J90 FAMILY INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and Carry bit to f
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
1
1
1
1
ANDWF
CLRF
COMF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
CPFSEQ
CPFSGT
CPFSLT
DECF
f, a
f, a
f, a
Compare f with WREG, Skip =
Compare f with WREG, Skip >
Compare f with WREG, Skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
4
1, 2
f, d, a Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ
DCFSNZ
INCF
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4
1, 2
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
fs, fd Move fs (source) to 1st word
fd (destination) 2nd word
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
0101 01da ffff ffff C, DC, Z, OV, N
1, 2
1, 2
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
RRNCF
SETF
f, a
Set f
1, 2
SUBFWB f, d, a Subtract f from WREG with
Borrow
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N 1, 2
0101 10da ffff ffff C, DC, Z, OV, N
SUBWFB f, d, a Subtract WREG from f with
Borrow
SWAPF
TSTFSZ
XORWF
f, d, a Swap Nibbles in f
f, a Test f, Skip if 0
f, d, a Exclusive OR WREG with f
1
0011 10da ffff ffff None
4
1, 2
1 (2 or 3) 0110 011a ffff ffff None
0001 10da ffff ffff Z, N
1
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
DS39933D-page 342
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TABLE 26-2: PIC18F87J90 FAMILY INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, b, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
Call Subroutine 1st word
2nd word
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust WREG
Go to Address 1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111 C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS) 1
Relative Call
Software Device Reset
Return from Interrupt Enable
1
1
1
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
4
2
1
2
s
RETLW
RETURN
SLEEP
k
s
—
Return with Literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
2010 Microchip Technology Inc.
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TABLE 26-2: PIC18F87J90 FAMILY INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add Literal and WREG
AND Literal with WREG
Inclusive OR Literal with WREG 1
Move literal (12-bit) 2nd word
to FSR(f) 1st word
Move Literal to BSR<3:0>
Move Literal to WREG
Multiply Literal with WREG
Return with Literal in WREG
Subtract WREG from Literal
1
1
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
2
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
Exclusive OR Literal with WREG 1
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with Post-Increment
Table Read with Post-Decrement
Table Read with Pre-Increment
Table Write
Table Write with Post-Increment
Table Write with Post-Decrement
Table Write with Pre-Increment
2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
DS39933D-page 344
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
26.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
ADDLW
k
Syntax:
ADDWF
f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 k 255
Operands:
0 f 255
d [0,1]
a [0,1]
(W) + k W
N, OV, C, DC, Z
Operation:
(W) + (f) dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
ADDLW
15h
Before Instruction
10h
After Instruction
25h
W
=
Words:
Cycles:
1
1
W
=
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
REG, 0, 0
Before Instruction
W
REG
=
=
17h
0C2h
After Instruction
W
REG
=
=
0D9h
0C2h
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
ADDWFC
f {,d {,a}}
Syntax:
ANDLW
k
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 k 255
(W) .AND. k W
N, Z
Operation:
(W) + (f) + (C) dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
ANDLW
05Fh
Before Instruction
W
=
A3h
03h
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
REG, 0, 1
Before Instruction
Carry bit =
1
02h
4Dh
REG
W
=
=
After Instruction
Carry bit =
0
02h
50h
REG
W
=
=
DS39933D-page 346
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ANDWF
AND W with f
BC
Branch if Carry
BC
Syntax:
ANDWF
f {,d {,a}}
Syntax:
n
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
-128 n 127
if Carry bit is ‘1’,
(PC) + 2 + 2n PC
Operation:
(W) .AND. (f) dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ’1’, then the program
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Words:
Cycles:
1
1
No
No
No
operation
No
operation
operation
operation
Q Cycle Activity:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
ANDWF
REG, 0, 0
Example:
HERE
BC
5
Before Instruction
Before Instruction
W
REG
=
=
17h
C2h
PC
=
address (HERE)
1;
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
W
REG
=
=
02h
C2h
address (HERE + 12)
0;
address (HERE + 2)
2010 Microchip Technology Inc.
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BCF
Bit Clear f
BN
Branch if Negative
BN
Syntax:
BCF f, b {,a}
Syntax:
n
Operands:
0 f 255
0 b 7
a [0,1]
Operands:
Operation:
-128 n 127
if Negative bit is ‘1’,
(PC) + 2 + 2n PC
Operation:
0 f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
Description:
Bit ‘b’ in register ‘f’ is cleared.
program will branch.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BCF
FLAG_REG, 7, 0
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
Example:
HERE
BN Jump
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
DS39933D-page 348
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BNC
Branch if Not Carry
BNC
BNN
Branch if Not Negative
BNN
Syntax:
n
Syntax:
n
Operands:
Operation:
-128 n 127
Operands:
Operation:
-128 n 127
if Carry bit is ‘0’,
(PC) + 2 + 2n PC
if Negative bit is ‘0’,
(PC) + 2 + 2n PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the program
Description:
If the Negative bit is ‘0’, then the
will branch.
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNC Jump
Example:
HERE
BNN Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
0;
If Negative
PC
If Negative
PC
=
=
=
=
0;
address (Jump)
1;
address (Jump)
1;
address (HERE + 2)
address (HERE + 2)
2010 Microchip Technology Inc.
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BNOV
Branch if Not Overflow
BNOV
BNZ
Branch if Not Zero
BNZ
Syntax:
n
Syntax:
n
Operands:
Operation:
-128 n 127
Operands:
Operation:
-128 n 127
if Overflow bit is ‘0’,
(PC) + 2 + 2n PC
if Zero bit is ‘0’,
(PC) + 2 + 2n PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
Description:
If the Zero bit is ‘0’, then the program
program will branch.
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNOV Jump
Example:
HERE
BNZ Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
0;
If Zero
PC
If Zero
PC
=
=
=
=
0;
address (Jump)
1;
address (Jump)
1;
address (HERE + 2)
address (HERE + 2)
DS39933D-page 350
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BRA
Unconditional Branch
BRA
BSF
Bit Set f
Syntax:
n
Syntax:
BSF f, b {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 n 1023
(PC) + 2 + 2n PC
None
Operands:
0 f 255
0 b 7
a [0,1]
Operation:
1 f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
Cycles:
1
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
HERE
BRA Jump
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
Example:
BSF
FLAG_REG, 7, 1
0Ah
8Ah
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
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BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 f 255
0 b 7
a [0,1]
Operands:
0 f 255
0 b < 7
a [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
1;
address (FALSE)
address (TRUE)
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BTG
Bit Toggle f
BOV
Branch if Overflow
BOV
Syntax:
BTG f, b {,a}
Syntax:
n
Operands:
0 f 255
0 b < 7
a [0,1]
Operands:
Operation:
-128 n 127
if Overflow bit is ‘1’,
(PC) + 2 + 2n PC
Operation:
(f<b>) f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted.
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC
After Instruction:
PORTC
=
0111 0101 [75h]
0110 0101 [65h]
Example:
HERE
BOV Jump
Before Instruction
=
PC
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
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BZ
Branch if Zero
BZ
CALL
Subroutine Call
Syntax:
n
Syntax:
CALL k {,s}
Operands:
Operation:
-128 n 127
Operands:
0 k 1048575
s [0,1]
if Zero bit is ‘1’,
(PC) + 2 + 2n PC
Operation:
(PC) + 4 TOS,
k PC<20:1>;
if s = 1
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) WS,
(STATUS) STATUSS,
(BSR) BSRS
Description:
If the Zero bit is ‘1’, then the program
will branch.
Status Affected:
None
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return address
Words:
Cycles:
1
(PC+ 4) is pushed onto the return stack.
If ‘s’ = 1, the W, STATUS and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs. Then, the 20-bit value ‘k’
is loaded into PC<20:1>. CALLis a
two-cycle instruction.
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal Push PC to Read literal
‘k’<7:0>,
stack
’k’<19:8>,
Write to PC
Example:
HERE
BZ Jump
No
No
No
No
Before Instruction
operation
operation
operation
operation
PC
=
address (HERE)
After Instruction
Example:
HERE
CALL THERE,1
If Zero
PC
If Zero
PC
=
=
=
=
1;
address (Jump)
0;
Before Instruction
PC
After Instruction
=
address (HERE)
address (HERE + 2)
PC
=
address (THERE)
TOS
WS
=
=
=
address (HERE + 4)
W
BSR
STATUS
BSRS
STATUSS =
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CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
CLRF f {,a}
Syntax:
CLRWDT
None
Operands:
0 f 255
a [0,1]
Operands:
Operation:
000h WDT,
000h WDT postscaler,
1 TO,
Operation:
000h f,
1 Z
1 PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the post-
scaler of the WDT. Status bits, TO and
PD, are set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
Cycles:
1
1
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
Process
Data
No
operation
operation
Words:
Cycles:
1
1
Example:
CLRWDT
Before Instruction
Q Cycle Activity:
Q1
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
=
?
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
=
=
=
=
00h
0
1
PD
1
Example:
CLRF
FLAG_REG,1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
5Ah
00h
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CPFSEQ
Compare f with W, Skip if f = W
COMF
Complement f
Syntax:
CPFSEQ f {,a}
Syntax:
COMF f {,d {,a}}
Operands:
0 f 255
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Operation:
f dest
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
If ‘f’ = W, then the fetched instruction is
discarded and a NOPis executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
Q2
Q3
Q4
1(2)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Example:
COMF
REG, 0, 0
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Before Instruction
Decode
REG
=
13h
After Instruction
If skip:
Q1
REG
W
=
=
13h
ECh
Q2
No
Q3
No
Q4
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
Q2
No
Q3
No
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
Example:
HERE
CPFSEQ REG, 0
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
=
=
HERE
?
?
W
REG
After Instruction
If REG
PC
If REG
PC
=
=
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
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CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
CPFSGT f {,a}
Syntax:
CPFSLT f {,a}
Operands:
0 f 255
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) –W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) –W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
Process
Data
No
operation
1(2)
register ‘f’
Note: 3 cycles if skip and followed
by a 2-word instruction.
If skip:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Decode
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
No
Q3
No
Q4
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
operation
No
Q2
No
operation
No
Q3
No
operation
No
Q4
No
operation
No
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
operation
operation
operation
operation
Before Instruction
PC
W
=
=
Address (HERE)
?
Example:
HERE
CPFSGT REG, 0
NGREATER
GREATER
:
:
After Instruction
If REG
PC
If REG
PC
<
=
=
W;
Address (LESS)
W;
Before Instruction
PC
W
=
=
Address (HERE)
?
Address (NLESS)
After Instruction
If REG
PC
If REG
PC
=
=
W;
Address (GREATER)
W;
Address (NGREATER)
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DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
None
Syntax:
DECF f {,d {,a}}
Operands:
Operation:
Operands:
0 f 255
d [0,1]
a [0,1]
If [W<3:0> > 9] or [DC = 1], then
(W<3:0>) + 6 W<3:0>;
else
Operation:
(f) – 1 dest
(W<3:0>) W<3:0>
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> > 9] or [C = 1], then
(W<7:4>) + 6 W<7:4>;
C =1;
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
else
(W<7:4>) W<7:4>
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Status Affected:
Encoding:
C
0000
0000
0000
0111
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Description:
DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register W
Process
Data
Write
W
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
DAW
Before Instruction
Example:
DECF
CNT,
1, 0
W
=
=
=
A5h
0
C
Before Instruction
DC
0
CNT
Z
=
01h
0
After Instruction
=
W
=
=
=
05h
1
0
After Instruction
C
CNT
Z
=
=
00h
1
DC
Example 2:
Before Instruction
W
=
=
=
CEh
0
0
C
DC
After Instruction
W
=
=
=
34h
1
0
C
DC
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DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if Not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ f {,d {,a}}
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – 1 dest,
skip if result = 0
Operation:
(f) – 1 dest,
skip if result 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
Process
Data
Write to
destination
register ‘f’
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
CONTINUE
Before Instruction
PC
After Instruction
Before Instruction
TEMP
After Instruction
=
Address (HERE)
=
?
CNT
=
CNT – 1
0;
If CNT
=
=
=
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
=
TEMP – 1,
0;
PC
Address (CONTINUE)
0;
If CNT
PC
Address (ZERO)
0;
Address (HERE + 2)
Address (NZERO)
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GOTO
Unconditional Branch
GOTO
INCF
Increment f
Syntax:
k
Syntax:
INCF f {,d {,a}}
Operands:
Operation:
Status Affected:
0 k 1048575
k PC<20:1>
None
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
kkk
k kkk
kkkk
kkkk
kkkk
7
0
8
k
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional branch
Description:
The contents of register ‘f’ are
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC<20:1>. GOTOis always a two-cycle
instruction.
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
Cycles:
2
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
1
Example:
GOTO THERE
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
PC
=
Address (THERE)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
=
FFh
0
=
=
=
C
?
DC
?
After Instruction
CNT
Z
=
00h
1
=
=
=
C
1
DC
1
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INFSNZ
Increment f, Skip if Not 0
INCFSZ
Increment f, Skip if 0
Syntax:
INFSNZ f {,d {,a}}
Syntax:
INCFSZ f {,d {,a}}
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest,
skip if result 0
Operation:
(f) + 1 dest,
skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0100
10da
ffff
ffff
0011
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
After Instruction
Before Instruction
PC
After Instruction
=
Address (HERE)
=
Address (HERE)
REG
If REG
PC
If REG
PC
=
REG + 1
CNT
If CNT
PC
If CNT
PC
=
CNT + 1
=
=
=
0;
=
=
=
0;
Address (NZERO)
0;
Address (ZERO)
Address (ZERO)
0;
Address (NZERO)
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IORLW
Inclusive OR Literal with W
IORLW
IORWF
Inclusive OR W with f
Syntax:
k
Syntax:
IORWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 k 255
(W) .OR. k W
N, Z
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(W) .OR. (f) dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
IORLW
35h
Before Instruction
W
=
9Ah
BFh
After Instruction
Words:
Cycles:
1
1
W
=
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT =
13h
91h
W
=
After Instruction
RESULT =
13h
93h
W
=
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LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF f {,d {,a}}
Operands:
0 f 2
0 k 4095
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
k FSRf
Operation:
f dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
k kkk
11
kkkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. Location, ‘f’,
can be anywhere in the 256-byte bank.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
Words:
Cycles:
1
1
FSR2H
FSR2L
=
=
03h
ABh
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
W
Example:
MOVF
REG, 0, 0
Before Instruction
REG
W
=
=
22h
FFh
After Instruction
REG
W
=
=
22h
22h
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MOVFF
Move f to f
MOVFF f ,f
MOVLB
Move Literal to Low Nibble in BSR
MOVLW
Syntax:
Syntax:
k
s
d
Operands:
0 f 4095
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 k 255
k BSR
None
s
0 f 4095
d
Operation:
(f ) f
s
d
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’
1100
1111
ffff
ffff
ffff
ffff
ffff
ffff
s
d
Description:
The contents of source register ‘f ’ are
regardless of the value of k :k .
s
7 4
moved to destination register ‘f ’.
d
Words:
Cycles:
1
1
Location of source ‘f ’ can be anywhere
s
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f ’
can also be anywhere from 000h to
FFFh.
d
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
Either source or destination can be W
(a useful special situation).
MOVFFis particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
Example:
MOVLB
5
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
The MOVFFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
33h
11h
After Instruction
REG1
REG2
=
=
33h
33h
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MOVLW
Move Literal to W
MOVLW
MOVWF
Move W to f
Syntax:
k
Syntax:
MOVWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
0 k 255
k W
None
Operands:
0 f 255
a [0,1]
Operation:
(W) f
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight-bit literal ‘k’ is loaded into W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
1
1
Cycles:
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
MOVLW
5Ah
After Instruction
W
=
5Ah
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG, 0
Before Instruction
W
REG
=
=
4Fh
FFh
After Instruction
W
REG
=
=
4Fh
4Fh
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MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
MULLW
k
Syntax:
MULWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 k 255
Operands:
0 f 255
a [0,1]
(W) x k PRODH:PRODL
Operation:
(W) x (f) PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
Description:
An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
W is unchanged.
None of the Status flags are affected.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULLW
0C4h
E2h
Words:
Cycles:
1
1
Before Instruction
W
PRODH
PRODL
=
=
=
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write
W
PRODH
PRODL
=
=
=
E2h
ADh
08h
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W
=
=
=
=
C4h
REG
B5h
?
PRODH
PRODL
?
After Instruction
W
=
=
=
=
C4h
B5h
8Ah
94h
REG
PRODH
PRODL
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NEGF
Negate f
NOP
No Operation
Syntax:
NEGF f {,a}
Syntax:
NOP
Operands:
0 f 255
a [0,1]
Operands:
Operation:
Status Affected:
Encoding:
None
No operation
None
Operation:
(f) + 1 f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
Description:
Words:
No operation.
1
1
Cycles:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Q1
Q2
Q3
No
operation
Q4
Decode
No
operation
No
operation
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
None.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
After Instruction
REG
=
0011 1010 [3Ah]
1100 0110 [C6h]
=
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POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
(TOS) bit bucket
(PC + 2) TOS
None
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
PUSH
No
No
Decode
No
operation
POP TOS
value
No
operation
PC + 2 onto
return stack
operation
operation
Example:
POP
Example:
PUSH
GOTO
NEW
Before Instruction
Before Instruction
TOS
Stack (1 level down)
TOS
PC
=
=
345Ah
0124h
=
=
0031A2h
014332h
After Instruction
After Instruction
PC
=
=
=
0126h
0126h
345Ah
TOS
TOS
PC
=
=
014332h
NEW
Stack (1 level down)
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RCALL
Relative Call
RCALL
RESET
Reset
Syntax:
n
Syntax:
RESET
None
Operands:
Operation:
-1024 n 1023
Operands:
Operation:
(PC) + 2 TOS,
(PC) + 2 + 2n PC
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
Words:
Cycles:
1
2
Example:
RESET
Q Cycle Activity:
Q1
After Instruction
Registers =
Q2
Q3
Q4
Reset Value
Reset Value
Flags*
=
Decode
Read literal
‘n’
Process
Data
Write to PC
PUSH PC
to stack
No
No
No
No
operation
operation
operation
operation
Example:
HERE
RCALL Jump
Before Instruction
PC
After Instruction
PC
TOS =
=
Address (HERE)
=
Address (Jump)
Address (HERE + 2)
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RETFIE
Return from Interrupt
RETLW
Return Literal to W
RETLW
Syntax:
RETFIE {s}
Syntax:
k
Operands:
Operation:
s [0,1]
Operands:
Operation:
0 k 255
(TOS) PC,
k W,
1 GIE/GIEH or PEIE/GIEL;
if s = 1,
(TOS) PC,
PCLATU, PCLATH are unchanged
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged
Description:
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers W,
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
write to W
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs.
No
operation
No
No
No
Words:
Cycles:
1
2
operation
operation
operation
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE ; W contains table
; offset value
Decode
No
operation
No
operation
POP PC
from stack
; W now has
; table value
Set GIEH or
GIEL
:
No
operation
No
operation
No
operation
No
operation
TABLE
ADDWF PCL ; W = offset
RETLW k0
RETLW k1
:
; Begin table
;
Example:
RETFIE
1
After Interrupt
:
PC
=
=
=
=
=
TOS
WS
RETLW kn
; End of table
W
BSR
STATUS
BSRS
STATUSS
1
Before Instruction
GIE/GIEH, PEIE/GIEL
W
=
07h
After Instruction
W
=
value of kn
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RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF f {,d {,a}}
Operands:
Operation:
s [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
(TOS) PC;
if s = 1,
(WS) W,
Operation:
(f<n>) dest<n + 1>,
(f<7>) C,
(C) dest<0>
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’.
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
POP PC
register f
C
from stack
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
RETURN
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction:
PC = TOS
Example:
RLCF
REG, 0, 0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
1100 1100
1
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RLNCF
Rotate Left f (No Carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF f {,d {,a}}
Syntax:
RRCF f {,d {,a}}
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f<n>) dest<n + 1>,
(f<7>) dest<0>
Operation:
(f<n>) dest<n – 1>,
(f<0>) C,
(C) dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
register f
C
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG
After Instruction
Example:
RRCF
REG, 0, 0
=
1010 1011
0101 0111
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
0111 0011
0
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RRNCF
Rotate Right f (No Carry)
SETF
Set f
Syntax:
RRNCF f {,d {,a}}
Syntax:
SETF f {,a}
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
FFh f
Operation:
(f<n>) dest<n – 1>,
(f<0>) dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified register
are set to FFh.
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
Example:
SETF
REG,1
Q Cycle Activity:
Q1
Before Instruction
REG
After Instruction
REG
=
=
5Ah
FFh
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG, 1, 0
Before Instruction
REG
After Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
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SLEEP
Enter Sleep Mode
SUBFWB
Subtract f from W with Borrow
Syntax:
SLEEP
None
Syntax:
SUBFWB f {,d {,a}}
Operands:
Operation:
Operands:
0 f 255
d [0,1]
a [0,1]
00h WDT,
0 WDT postscaler,
1 TO,
Operation:
(W) – (f) – (C) dest
0 PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored in
W. If ‘d’ is ‘1’, the result is stored in
register ‘f’.
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. The Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
Cycles:
1
1
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Q Cycle Activity:
Q1
Q2
Q3
Q4
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
No
operation
Process
Data
Go to
Sleep
Words:
Cycles:
1
1
Example:
SLEEP
Before Instruction
TO
PD
=
=
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
TO
PD
=
=
1†
0
Example 1:
SUBFWB
REG, 1, 0
†
If WDT causes wake-up, this bit is cleared.
Before Instruction
REG
W
C
=
=
=
3
2
1
After Instruction
REG
W
C
=
FF
2
=
=
=
=
0
Z
0
1
N
; result is negative
Example 2:
Before Instruction
SUBFWB
REG, 0, 0
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
=
2
3
1
0
0
=
=
=
=
Z
N
; result is positive
Example 3:
Before Instruction
SUBFWB
REG, 1, 0
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
=
0
2
1
1
0
=
=
=
=
Z
; result is zero
N
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SUBLW
Subtract W from Literal
SUBLW
SUBWF
Subtract W from f
Syntax:
k
Syntax:
SUBWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 k 255
Operands:
0 f 255
d [0,1]
a [0,1]
k – (W) W
N, OV, C, DC, Z
Operation:
(f) – (W) dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
Words:
Cycles:
1
1
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’.
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example 1:
SUBLW 02h
Before Instruction
W
C
=
=
01h
?
After Instruction
W
C
Z
=
01h
=
=
=
1
0
0
; result is positive
Words:
Cycles:
1
1
N
Example 2:
SUBLW 02h
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
W
C
=
=
02h
?
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
C
Z
=
00h
Example 1:
SUBWF
REG, 1, 0
=
=
=
1
1
0
; result is zero
Before Instruction
N
REG
W
C
=
=
=
3
2
?
Example 3:
SUBLW 02h
Before Instruction
After Instruction
W
C
=
=
03h
?
REG
W
C
=
1
2
1
0
0
=
=
=
=
; result is positive
After Instruction
Z
W
C
Z
=
FFh ; (2’s complement)
N
=
=
=
0
0
1
; result is negative
Example 2:
Before Instruction
SUBWF
REG, 0, 0
N
REG
W
C
=
=
=
2
2
?
After Instruction
REG
W
C
=
2
0
1
1
0
=
=
=
=
; result is zero
Z
N
Example 3:
Before Instruction
SUBWF
REG, 1, 0
REG
W
C
=
=
=
1
2
?
After Instruction
REG
W
C
=
FFh ;(2’s complement)
2
0
0
1
=
=
=
=
; result is negative
Z
N
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SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
SUBWFB f {,d {,a}}
Syntax:
SWAPF f {,d {,a}}
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – (W) – (C) dest
Operation:
(f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected:
Encoding:
N, OV, C, DC, Z
0101
10da
ffff
ffff
Status Affected:
Encoding:
None
Description:
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Decode
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBWFB REG, 1, 0
Before Instruction
REG
W
C
=
=
=
19h
0Dh
1
(0001 1001)
(0000 1101)
Example:
SWAPF
REG, 1, 0
Before Instruction
REG
After Instruction
=
53h
35h
After Instruction
REG
W
=
0Ch
0Dh
1
(0000 1011)
(0000 1101)
=
=
=
=
REG
=
C
Z
0
N
0
; result is positive
Example 2:
Before Instruction
SUBWFB REG, 0, 0
REG
W
C
=
=
=
1Bh
1Ah
0
(0001 1011)
(0001 1010)
After Instruction
REG
W
C
=
1Bh
00h
1
(0001 1011)
=
=
=
=
Z
1
; result is zero
N
0
Example 3:
Before Instruction
SUBWFB REG, 1, 0
REG
W
C
=
=
=
03h
0Eh
1
(0000 0011)
(0000 1101)
After Instruction
REG
=
F5h
(1111 0100)
; [2’s comp]
W
=
=
=
=
0Eh
0
0
1
(0000 1101)
C
Z
N
; result is negative
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TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
None
Example 1:
TBLRD *+ ;
Operands:
Operation:
Before Instruction
TABLAT
TBLPTR
MEMORY(00A356h)
=
=
=
55h
00A356h
34h
if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR – No Change
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) – 1 TBLPTR
if TBLRD +*,
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT
After Instruction
TABLAT
TBLPTR
=
=
34h
00A357h
Example 2:
TBLRD +* ;
Before Instruction
TABLAT
TBLPTR
MEMORY(01A357h)
MEMORY(01A358h)
After Instruction
=
=
=
=
AAh
01A357h
12h
34h
TABLAT
TBLPTR
=
=
34h
01A358h
Status Affected: None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte of
Program Memory Word
TBLPTR[0] = 1: Most Significant Byte of
Program Memory Word
The TBLRDinstruction can modify the value
of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
No
No operation
No
No operation
(Write
TABLAT)
operation (Read Program operation
Memory)
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TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
None
Example 1:
TBLWT *+;
Operands:
Operation:
Before Instruction
if TBLWT*,
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A356h
(TABLAT) Holding Register;
TBLPTR – No Change
if TBLWT*+,
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR
if TBLWT*-,
(TABLAT) Holding Register;
(TBLPTR) – 1 TBLPTR
if TBLWT+*,
(TBLPTR) + 1 TBLPTR;
(TABLAT) Holding Register
=
FFh
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A357h
=
55h
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
=
=
34h
01389Ah
HOLDING REGISTER
(01389Ah)
Status Affected: None
=
=
FFh
FFh
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
HOLDING REGISTER
(01389Bh)
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
=
=
34h
01389Bh
Description:
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 6.0 “Memory
Organization” for additional details on
programming Flash memory.)
=
=
FFh
34h
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
No
Decode
operation operation operation
No
No No No
operation operation operation operation
(Read
TABLAT)
(Write to
Holding
Register)
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TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
XORLW
Syntax:
TSTFSZ f {,a}
Syntax:
k
Operands:
0 f 255
a [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 k 255
(W) .XOR. k W
N, Z
Operation:
skip if f = 0
Status Affected:
Encoding:
None
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Description:
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOPis executed,
making this a two-cycle instruction.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
XORLW
0AFh
Before Instruction
W
=
B5h
1Ah
After Instruction
Words:
Cycles:
1
W
=
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
=
00h,
Address (ZERO)
00h,
Address (NZERO)
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XORWF
Exclusive OR W with f
Syntax:
XORWF f {,d {,a}}
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(W) .XOR. (f) dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG, 1, 0
Before Instruction
REG
W
=
=
AFh
B5h
After Instruction
REG
W
=
=
1Ah
B5h
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A summary of the instructions in the extended instruc-
tion set is provided in Table 26-3. Detailed descriptions
are provided in Section 26.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 26-1
(page 340) apply to both the standard and extended
PIC18 instruction sets.
26.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, the PIC18F87J90 family family of
devices also provide an optional extension to the core
CPU functionality. The added features include eight
additional instructions that augment Indirect and
Indexed Addressing operations and the implementa-
tion of Indexed Literal Offset Addressing for many of
the standard PIC18 instructions.
Note:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is
provided as a reference for users who may
be reviewing code that has been
generated by a compiler.
The additional features of the extended instruction set
are enabled by default on unprogrammed devices.
Users must properly set or clear the XINST Configura-
tion bit during programming to enable or disable these
features.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for Indexed
Addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
26.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed argu-
ments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
Indexed Addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 26.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
• Dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• Function Pointer invocation
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
• Software Stack Pointer manipulation
• Manipulation of variables located in a software
stack
TABLE 26-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
ADDFSR
ADDULNK
CALLW
f, k
k
Add Literal to FSR
Add Literal to FSR2 and Return
Call Subroutine using WREG
1
2
2
2
1110 1000 ffkk kkkk
1110 1000 11kk kkkk
0000 0000 0001 0100
1110 1011 0zzz zzzz
1111 ffff ffff ffff
1110 1011 1zzz zzzz
1111 xxxx xzzz zzzz
1110 1010 kkkk kkkk
None
None
None
None
MOVSF
zs, fd Move zs (source) to 1st word
fd (destination) 2nd word
zs, zd Move zs (source) to 1st word
zd (destination) 2nd word
MOVSS
PUSHL
2
1
None
None
k
Store Literal at FSR2,
Decrement FSR2
SUBFSR
SUBULNK
f, k
k
Subtract Literal from FSR
Subtract Literal from FSR2 and
Return
1
2
1110 1001 ffkk kkkk
1110 1001 11kk kkkk
None
None
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26.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Add Literal to FSR2 and Return
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 k 63
f [ 0, 1, 2 ]
Operands:
Operation:
0 k 63
FSR2 + k FSR2,
(TOS) PC
Operation:
FSR(f) + k FSR(f)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
1000
ffkk
kkkk
1110
1000
11kk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Description:
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Words:
1
1
Cycles:
The instruction takes two cycles to
execute; a NOPis performed during
the second cycle.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
This may be thought of as a special
case of the ADDFSRinstruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Example:
ADDFSR 2, 23h
Words:
1
2
Before Instruction
FSR2
After Instruction
FSR2
Cycles:
=
03FFh
0422h
Q Cycle Activity:
Q1
Q2
Q3
Q4
=
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
No
No
No
No
Operation
Operation
Operation
Operation
Example:
ADDULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
0422h
(TOS)
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
DS39933D-page 382
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
CALLW
Subroutine Call Using WREG
MOVSF
Move Indexed to f
Syntax:
CALLW
None
Syntax:
MOVSF [z ], f
s
d
Operands:
Operation:
Operands:
0 z 127
s
0 f 4095
d
(PC + 2) TOS,
(W) PCL,
Operation:
((FSR2) + z ) f
s
d
(PCLATH) PCH,
(PCLATU) PCU
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
Status Affected:
Encoding:
None
1110
1111
1011
ffff
0zzz
ffff
zzzz
ffff
s
d
0000
0000
0001
0100
Description
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOPinstruction while the
new next instruction is fetched.
Description:
The contents of the source register are
moved to destination register ‘f ’. The
d
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z ’, in the first word, to the value
s
of FSR2. The address of the destination
register is specified by the 12-bit literal
‘f ’ in the second word. Both addresses
d
can be anywhere in the 4096-byte data
space (000h to FFFh).
Unlike CALL, there is no option to
update W, STATUS or BSR.
The MOVSFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words:
Cycles:
1
2
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
WREG
Push PC to
stack
No
operation
Words:
Cycles:
2
2
No
No
No
No
Q Cycle Activity:
Q1
operation
operation
operation
operation
Q2
Q3
Q4
Decode
Determine
source addr source addr source reg
Determine
Read
Example:
HERE
CALLW
Before Instruction
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
PC
=
address (HERE)
PCLATH =
PCLATU =
10h
00h
06h
No dummy
read
W
=
After Instruction
PC
=
001006h
TOS
=
address (HERE + 2)
Example:
MOVSF
[05h], REG2
PCLATH =
PCLATU =
W
10h
00h
06h
Before Instruction
=
FSR2
=
80h
33h
Contents
of 85h
REG2
=
=
11h
After Instruction
FSR2
=
80h
Contents
of 85h
REG2
=
=
33h
33h
2010 Microchip Technology Inc.
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MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [z ], [z ]
Syntax:
PUSHL k
s
d
Operands:
0 z 127
s
Operands:
Operation:
0k 255
0 z 127
d
k (FSR2),
FSR2 – 1 FSR2
Operation:
((FSR2) + z ) ((FSR2) + z )
s d
Status Affected:
None
Status Affected:
Encoding:
None
Encoding:
1st word (source)
2nd word (dest.)
1111
1010
kkkk
kkkk
1110
1111
1011
xxxx
1zzz
xzzz
zzzz
zzzz
s
d
Description:
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2.
FSR2 is decremented by 1 after the
operation.
Description
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
This instruction allows users to push
values onto a software stack.
7-bit literal offsets, ‘z ’ or ‘z ’,
s
d
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
The MOVSSinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Q2
Q3
Q4
Decode
Read ‘k’
Process
data
Write to
destination
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the
Example:
PUSHL 08h
resultant destination address points to
an Indirect Addressing register, the
instruction will execute as a NOP.
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
Words:
2
2
After Instruction
Cycles:
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Decode
Determine
dest addr
Determine
dest addr
Write
to dest reg
Example:
MOVSS [05h], [06h]
Before Instruction
FSR2
=
=
=
80h
33h
11h
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
=
=
=
80h
33h
33h
Contents
of 85h
Contents
of 86h
DS39933D-page 384
2010 Microchip Technology Inc.
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SUBFSR
Subtract Literal from FSR
SUBULNK
Subtract Literal from FSR2 and Return
Syntax:
SUBFSR f, k
0 k 63
Syntax:
SUBULNK k
Operands:
Operands:
Operation:
0 k 63
f [ 0, 1, 2 ]
FSRf – k FSRf
None
FSR2 – k FSR2,
(TOS) PC
Operation:
Status Affected: None
Status Affected:
Encoding:
Encoding:
1110
1001
11kk
kkkk
1110
1001
ffkk
kkkk
Description:
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Description:
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified
by ‘f’.
Words:
1
1
The instruction takes two cycles to
execute; a NOPis performed during the
second cycle.
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
This may be thought of as a special case
of the SUBFSRinstruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Decode
Read
register ‘f’
Process
Data
Write to
destination
Words:
1
2
Example:
SUBFSR 2, 23h
03FFh
Cycles:
Before Instruction
FSR2
After Instruction
FSR2
Q Cycle Activity:
Q1
=
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
=
03DCh
No
No
No
No
Operation
Operation
Operation
Operation
Example:
SUBULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
03DCh
(TOS)
2010 Microchip Technology Inc.
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26.2.3
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
26.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument, ‘f’, in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value, ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within the brackets, will
generate an error in the MPASM Assembler.
Note: Enabling the PIC18 instruction set exten-
sion may cause legacy applications to
behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing (Section 6.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embed-
ded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0) or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a file register argument of 5Fh or less is interpreted as
an offset from the pointer value in FSR2 and not as a
literal address. For practical purposes, this means that
all instructions that use the Access RAM bit as an
argument – that is, all byte-oriented and bit-oriented
instructions, or almost half of the core PIC18 instruc-
tions – may behave differently when the extended
instruction set is enabled.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled), when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument ‘d’ functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
When the content of FSR2 is 00h, the boundaries of
the Access RAM are essentially remapped to their
original values. This may be useful in creating
backward-compatible code. If this technique is used, it
may be necessary to save the value of FSR2 and
restore it when moving back and forth between C and
assembly routines in order to preserve the Stack
Pointer. Users must also keep in mind the syntax
requirements of the extended instruction set (see
Section 26.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”).
26.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Although the Indexed Literal Offset mode can be very
useful for dynamic stack and pointer manipulation, it
can also be very annoying if a simple arithmetic opera-
tion is carried out on the wrong register. Users who are
accustomed to the PIC18 programming must keep in
mind that, when the extended instruction set is
enabled, register addresses of 5Fh or less are used for
Indexed Literal Offset Addressing.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
mode are provided on the following page to show how
execution is affected. The operand conditions shown in
the examples are applicable to all instructions of these
types.
When porting an application to the PIC18F87J90 family
family, it is very important to consider the type of code.
A large, re-entrant application that is written in C and
would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.
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2010 Microchip Technology Inc.
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ADD W to Indexed
(Indexed Literal Offset mode)
Bit Set Indexed
BSF
ADDWF
(Indexed Literal Offset mode)
Syntax:
ADDWF
[k] {,d}
Syntax:
BSF [k], b
Operands:
0 k 95
d [0,1]
Operands:
0 f 95
0 b 7
Operation:
(W) + ((FSR2) + k) dest
Operation:
1 ((FSR2) + k)<b>
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
None
0010
01d0
kkkk
kkkk
1000
bbb0
kkkk
kkkk
Description:
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words:
Cycles:
1
1
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Example:
BSF
[FLAG_OFST], 7
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write to
destination
Before Instruction
FLAG_OFST
FSR2
=
=
0Ah
0A00h
Contents
of 0A0Ah
After Instruction
Example:
ADDWF
[OFST],0
=
55h
D5h
Before Instruction
W
OFST
FSR2
=
=
=
17h
Contents
of 0A0Ah
2Ch
=
0A00h
Contents
of 0A2Ch
=
20h
After Instruction
Set Indexed
(Indexed Literal Offset mode)
SETF
W
=
=
37h
20h
Contents
of 0A2Ch
Syntax:
SETF [k]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 k 95
FFh ((FSR2) + k)
None
0110
1000
kkkk
kkkk
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
[OFST]
2Ch
Before Instruction
OFST
FSR2
=
=
0A00h
Contents
of 0A2Ch
=
00h
After Instruction
Contents
of 0A2Ch
=
FFh
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To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
26.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set for the PIC18F87J90 family family. This includes
the MPLAB C18 C Compiler, MPASM assembly
language and MPLAB Integrated Development
Environment (IDE).
• A menu option or dialog box within the
environment that allows the user to configure the
language tool and its settings for the project
• A command line option
When selecting
a
target device for software
• A directive in the source code
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘1’, enabling the
extended instruction set and Indexed Literal Offset
Addressing. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompany-
ing their development systems for the appropriate
information.
DS39933D-page 388
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27.1 MPLAB Integrated Development
Environment Software
27.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2010 Microchip Technology Inc.
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27.2 MPLAB C Compilers for Various
Device Families
27.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
27.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
27.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
27.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
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27.7 MPLAB SIM Software Simulator
27.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
27.10 PICkit 3 In-Circuit Debugger/
Programmer and
27.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.
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27.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
27.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
27.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS39933D-page 392
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
28.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ........................................... -0.3V to 6.0V
Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)...... -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 3.6V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin..............................................................................................................................250 mA
Maximum output current sunk by PORTA<7:6> and any PORTB and PORTC I/O pins.........................................25 mA
Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins ..........................................................8 mA
Maximum output current sunk by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins ............................2 mA
Maximum output current sourced by PORTA<7:6> and any PORTB and PORTC I/O pins ...................................25 mA
Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins.....................................................8 mA
Maximum output current sourced by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins .......................2 mA
Maximum current sunk byall ports combined.......................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2010 Microchip Technology Inc.
DS39933D-page 393
PIC18F87J90 FAMILY
FIGURE 28-1:
VOLTAGE-FREQUENCY GRAPH,
REGULATOR ENABLED (INDUSTRIAL)(1)
4.0V
3.5V
3.6V
PIC18F6XJ90/PIC18F8XJ90
3.0V
2.5V
2.0V
2.35V
0
8 MHz
48 MHz
Frequency
Note 1: When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset
before VDD reaches a level at which full-speed operation is not possible.
FIGURE 28-2:
VOLTAGE-FREQUENCY GRAPH,
REGULATOR DISABLED (INDUSTRIAL)(1,2)
3.00V
2.75V
2.50V
2.7V
PIC18F6XJ90/PIC18F8XJ90
2.35V
2.25V
2.00V
48 MHz
8 MHz
Frequency
Note 1: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCORE VDD 3.6V.
DS39933D-page 394
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
28.1 DC Characteristics: Supply Voltage
PIC18F87J90 Family (Industrial)
PIC18F87J90 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Param
Symbol
No.
Characteristic
Supply Voltage
Min
Typ
Max
Units
Conditions
D001
VDD
VDDCORE
—
—
3.6
3.6
V
V
ENVREG tied to VSS
ENVREG tied to VDD
2.0
D001B VDDCORE External Supply for
2.0
—
2.70
V
ENVREG tied to VSS
Microcontroller Core
D001C AVDD
D001D AVSS
Analog Supply Voltage
VDD – 0.3
—
—
—
VDD + 0.3
VSS + 0.3
—
V
V
V
Analog Ground Potential VSS – 0.3
D002
VDR
RAM Data Retention
Voltage(1)
1.5
D003
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
—
—
0.7
—
V
See Section 5.3 “Power-on
Reset (POR)” for details
D004
D005
SVDD
VBOR
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
V/ms See Section 5.3 “Power-on
Reset (POR)” for details
Brown-out Reset Voltage
1.8
—
V
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
2010 Microchip Technology Inc.
DS39933D-page 395
PIC18F87J90 FAMILY
28.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J90 Family (Industrial)
PIC18F87J90 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Param
No.
Device
Typ
Max Units
Conditions
(1)
Power-Down Current (IPD)
All devices
0.4
0.1
0.8
5.5
0.5
0.1
1
1.4
1.4
6
A
A
A
A
A
A
A
A
A
A
A
A
-40°C
+25°C
+60°C
+85°C
-40°C
+25°C
+60°C
+85°C
-40°C
+25°C
+60°C
+85°C
(4)
VDD = 2.0V
(Sleep mode)
10.2
1.5
1.5
8
All devices
All devices
(4)
VDD = 2.5V
(Sleep mode)
6.8
2.9
3.6
4.1
9.6
12.6
7
(5)
7
VDD = 3.3V
(Sleep mode)
10
19
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39933D-page 396
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
28.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J90 Family (Industrial) (Continued)
PIC18F87J90 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
5
14.2
14.2
19.0
16.5
16.5
22.4
84
A
A
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
5.5
10
(4)
(4)
A
6.8
7.6
14
A
FOSC = 31 kHz
(RC_RUN mode,
internal oscillator source)
VDD = 2.5V,
VDDCORE = 2.5V
A
A
37
A
(5)
51
84
A
VDD = 3.3V
72
108
A
0.43
0.47
0.52
0.52
0.57
0.63
0.59
0.65
0.72
0.88
1
0.82
0.82
0.95
0.98
0.98
1.10
0.96
0.96
1.18
1.45
1.45
1.58
1.72
1.72
1.85
2.87
2.87
2.96
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 2.0V,
VDDCORE = 2.0V
(4)
(4)
FOSC = 1 MHz
(RC_RUN mode,
internal oscillator source)
VDD = 2.5V,
VDDCORE = 2.5V
(5)
VDD = 3.3V
VDD = 2.0V,
VDDCORE = 2.0V
(4)
(4)
1.1
1.2
1.3
1.4
1.3
1.4
1.5
FOSC = 4 MHz
(RC_RUN mode,
internal oscillator source)
VDD = 2.5V,
VDDCORE = 2.5V
(5)
VDD = 3.3V
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
2010 Microchip Technology Inc.
DS39933D-page 397
PIC18F87J90 FAMILY
28.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J90 Family (Industrial) (Continued)
PIC18F87J90 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Param
No.
Device
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD) Cont.
All devices
3
9.4
A
A
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
3.3
9.4
(4)
(4)
8.5
17.2
10.5
10.5
19.5
82
A
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
4
A
FOSC = 31 kHz
(RC_IDLE mode,
VDD = 2.5V,
VDDCORE = 2.5V
4.3
A
internal oscillator source)
10.3
34
A
A
(5)
48
82
A
VDD = 3.3V
69
105
A
0.33
0.37
0.41
0.39
0.42
0.47
0.43
0.48
0.54
0.53
0.57
0.61
0.63
0.67
0.72
0.7
0.75
0.75
0.84
0.78
0.78
0.91
0.82
0.82
0.95
0.98
0.98
1.12
1.14
1.14
1.25
1.27
1.27
1.45
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 2.0V,
VDDCORE = 2.0V
(4)
(4)
FOSC = 1 MHz
(RC_IDLE mode,
VDD = 2.5V,
VDDCORE = 2.5V
internal oscillator source)
(5)
VDD = 3.3V
VDD = 2.0V,
VDDCORE = 2.0V
(4)
(4)
FOSC = 4 MHz
(RC_IDLE mode,
VDD = 2.5V,
VDDCORE = 2.5V
internal oscillator source)
(5)
0.76
0.82
VDD = 3.3V
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39933D-page 398
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
28.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J90 Family (Industrial) (Continued)
PIC18F87J90 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Param
No.
Device
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD) Cont.
All devices
0.17
0.18
0.20
0.29
0.31
0.34
0.59
0.44
0.42
0.70
0.75
0.79
1.10
1.10
1.12
1.55
1.47
1.54
9.9
0.35
0.35
0.42
0.52
0.52
0.61
1.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
(4)
(4)
All devices
All devices
All devices
All devices
All devices
All devices
All devices
FOSC = 1 MHZ
(PRI_RUN mode,
EC oscillator)
VDD = 2.5V,
VDDCORE = 2.5V
(5)
0.85
0.85
1.25
1.25
1.36
1.7
VDD = 3.3V
VDD = 2.0V,
VDDCORE = 2.0V
(4)
(4)
FOSC = 4 MHz
(PRI_RUN mode,
EC oscillator)
VDD = 2.5V,
VDDCORE = 2.5V
1.7
1.82
1.95
1.89
1.92
14.8
14.8
15.2
23.2
22.7
22.7
(5)
VDD = 3.3V
VDD = 2.5V,
VDDCORE = 2.5V
9.5
(4)
FOSC = 48 MHZ
(PRI_RUN mode,
EC oscillator)
10.1
13.3
12.2
12.1
(5)
VDD = 3.3V
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
2010 Microchip Technology Inc.
DS39933D-page 399
PIC18F87J90 FAMILY
28.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J90 Family (Industrial) (Continued)
PIC18F87J90 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Param
No.
Device
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD) Cont.
All devices
4.5
4.4
5.2
5.2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.5V,
VDDCORE = 2.5V
(4)
FOSC = 4 MHZ,
16 MHz internal
(PRI_RUN HSPLL mode)
4.5
5.2
All devices
All devices
All devices
5.7
6.7
(5)
5.5
6.3
VDD = 3.3V
5.3
6.3
10.8
10.8
9.9
13.5
13.5
13.0
24.1
20.2
19.5
VDD = 2.5V,
VDDCORE = 2.5V
(4)
FOSC = 10 MHZ,
40 MHz internal
(PRI_RUN HSPLL mode)
13.4
12.3
11.2
(5)
VDD = 3.3V
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39933D-page 400
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
28.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J90 Family (Industrial) (Continued)
PIC18F87J90 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Param
No.
Device
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD) Cont.
All devices
0.10
0.07
0.09
0.25
0.13
0.10
0.45
0.26
0.30
0.36
0.33
0.35
0.52
0.45
0.46
0.80
0.66
0.65
5.2
0.26
0.18
0.22
0.48
0.30
0.26
0.68
0.45
0.54
0.60
0.56
0.56
0.81
0.70
0.70
1.15
0.98
0.98
6.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
(4)
(4)
All devices
All devices
All devices
All devices
All devices
All devices
All devices
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 2.5V,
VDDCORE = 2.5V
(5)
VDD = 3.3V
VDD = 2.0V,
VDDCORE = 2.0V
(4)
(4)
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 2.5V,
VDDCORE = 2.5V
(5)
VDD = 3.3V
VDD = 2.5V,
VDDCORE = 2.5V
4.9
5.9
(4)
FOSC = 48 MHz
(PRI_IDLE mode,
EC oscillator)
3.4
4.5
6.2
12.4
11.5
11.5
(5)
5.9
VDD = 3.3V
5.8
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
2010 Microchip Technology Inc.
DS39933D-page 401
PIC18F87J90 FAMILY
28.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J90 Family (Industrial) (Continued)
PIC18F87J90 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Param
No.
Device
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD) Cont.
All devices
18
19
35
35
µA
µA
µA
µA
µA
µA
mA
mA
mA
µA
µA
µA
µA
µA
µA
mA
mA
mA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
(4)
(4)
28
49
All devices
All devices
All devices
All devices
All devices
20
45
(3)
FOSC = 32 kHz
VDD = 2.5V,
VDDCORE = 2.5V
21
45
(SEC_RUN mode,
Timer1 as clock)
32
61
0.06
0.07
0.09
14
0.11
0.11
0.15
28
(5)
VDD = 3.3V
VDD = 2.0V,
VDDCORE = 2.0V
15
28
(4)
(4)
24
43
15
31
(3)
FOSC = 32 kHz
VDD = 2.5V,
VDDCORE = 2.5V
16
31
(SEC_IDLE mode,
Timer1 as clock)
27
50
0.05
0.06
0.08
0.10
0.10
0.14
(5)
VDD = 3.3V
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39933D-page 402
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
28.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J90 Family (Industrial) (Continued)
PIC18F87J90 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Param
No.
Device
Typ
Max Units
Conditions
D022
Module Differential Currents (IWDT, IOSCB, IAD)
Watchdog Timer
2.1
2.2
4.3
3.0
3.1
5.5
5.9
6.2
7.0
7.0
9.5
8.0
8.0
10.4
12.1
12.1
13.6
5
A
A
A
A
A
A
A
A
A
µA
µA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+25°C
+25°C
VDD = 2.0V,
VDDCORE = 2.0V
(4)
(4)
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 3.3V
6.9
(6,7)
D024
(ILCD)
LCD Module
2
VDD = 2.0V
VDD = 2.5V
Resistive Ladder
CPEN = 0;
(6,7)
(6,7)
2.7
3.5
5
CKSEL<1:0> = 00;
CS<1:0> = 10;
LP<3:0> = 0100
7
µA
+25°C
VDD = 3.0V
(7)
16
17
24
25
25
40
µA
µA
µA
+25°C
+25°C
+25°C
VDD = 2.0V
VDD = 2.5V
Charge Pump
BIAS<2:0> = 111;
CPEN = 1;
CKSEL<1:0> = 11;
CS<1:0> = 10
(7)
(7)
VDD = 3.0V
D025
(IOSCB)
RTCC + Timer1 Osc. with
0.9
4.0
4.5
4.5
4.5
5.0
5.0
6.5
6.5
8.0
10.0
A
A
A
A
A
A
A
A
A
A
-10°C
+25°C
+85°C
-10°C
+25°C
+85°C
-10°C
+25°C
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
(6)
(3)
32 kHz Crystal
32 kHz on Timer1
32 kHz on Timer1
32 kHz on Timer1
1.0
1.1
1.1
1.2
1.2
1.6
1.6
2.1
3.0
(4)
(4)
VDD = 2.5V,
VDDCORE = 2.5V
(3)
(3)
VDD = 3.3V
D026
(IAD)
A/D Converter
VDD = 2.0V,
VDDCORE = 2.0V
-40°C to +85°C
(4)
A/D on, not converting
3.0
10.0
A
-40°C to +85°C
VDD = 2.5V,
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
2010 Microchip Technology Inc.
DS39933D-page 403
PIC18F87J90 FAMILY
28.3 DC Characteristics: PIC18F87J90 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VIL
Input Low Voltage
All I/O Ports:
with TTL Buffer
D030
VSS
—
0.15 VDD
0.8
V
V
V
V
V
V
V
V
VDD < 3.3V
D030A
D031
3.3V VDD 3.6V
with Schmitt Trigger Buffer
with RC3 and RC4
VSS
VSS
VSS
VSS
VSS
VSS
0.2 VDD
0.3 VDD
0.8
D031A
D031B
D032
I2C™ enabled
SMBus enabled
MCLR
0.2 VDD
0.3 VDD
0.2 VDD
D033
OSC1
OSC1
HS, HSPLL modes
EC, ECPLL modes
D033A
D034
T13CKI
VSS
0.3
V
VIH
Input High Voltage
I/O Ports with non 5.5V Tolerance:
with TTL Buffer
D040
0.25 VDD + 0.8V
2.0
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
VDD < 3.3V
D040A
D041
3.3V VDD 3.6V
with Schmitt Trigger Buffer
RC3 and RC4
0.8 VDD
0.7 VDD
2.1
D041A
D041B
I2C enabled
SMBus enabled
I/O Ports with 5.5V Tolerance:
with TTL Buffer
0.25 VDD + 0.8V
2.0
5.5
5.5
V
V
V
V
V
V
VDD < 3.3V
3.3V VDD 3.6V
with Schmitt Trigger Buffer
0.8 VDD
0.8 VDD
0.7 VDD
0.8 VDD
5.5
D042
D043
D043A
MCLR
OSC1
OSC1
VDD
VDD
VDD
HS, HSPLL modes
EC, ECPLL modes
D044
T13CKI
1.6
VDD
V
IIL
Input Leakage Current(1)
D060
I/O Ports with Analog Functions
—
200
nA VSS VPIN VDD,
Pin at high-impedance
Digital Only I/O Ports
MCLR
—
—
—
200
1
nA VSS VPIN V
A Vss VPIN VDD
A Vss VPIN VDD
D061
D063
OSC1
1
IPU
Weak Pull-up Current
PORTB Weak Pull-up Current
D070
IPURB
30
400
A VDD = 3.3V, VPIN = VSS
Note 1: Negative current is defined as current sourced by the pin.
DS39933D-page 404
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
28.3 DC Characteristics: PIC18F87J90 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VOL
Output Low Voltage
I/O Ports:
D080
PORTA, PORTF, PORTG,
PORTH
—
—
—
—
0.4
0.4
0.4
0.4
V
V
V
V
IOL = 2 mA, VDD = 3.3V,
-40C to +85C
PORTD, PORTE, PORTJ
IOL = 3.4 mA, VDD = 3.3V,
-40C to +85C
PORTB, PORTC
IOL = 3.4 mA, VDD = 3.3V,
-40C to +85C
D083
D090
OSC2/CLKO
IOL = 1.6 mA, VDD = 3.3V,
(EC, ECPLL modes)
Output High Voltage(1)
I/O Ports:
-40C to +85C
VOH
V
V
PORTA, PORTF, PORTG,
PORTH
2.4
2.4
2.4
2.4
—
—
—
—
IOH = -2 mA, VDD = 3.3V,
-40C to +85C
PORTD, PORTE, PORTJ
V
V
V
IOH = -2 mA, VDD = 3.3V,
-40C to +85C
PORTB, PORTC
IOH = -2 mA, VDD = 3.3V,
-40C to +85C
D092
OSC2/CLKO
IOH = -1 mA, VDD = 3.3V,
(INTOSC, EC, ECPLL modes)
-40C to +85C
Capacitive Loading Specs
on Output Pins
D100(4) COSC2 OSC2 Pin
—
15
pF In HS mode when
external clock is used to
drive OSC1
D101
D102
CIO
CB
All I/O Pins and OSC2
SCL, SDA
—
—
50
pF To meet the AC Timing
Specifications
pF I2C™ Specification
400
Note 1: Negative current is defined as current sourced by the pin.
28.4 DC Characteristics: CTMU Current Source Specifications
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
IOUT1 CTMU Current Source,
Base Range
—
550
—
nA
CTMUICON<1:0> = 01
IOUT2 CTMU Current Source,
10x Range
—
—
5.5
55
—
—
A
A
CTMUICON<1:0> = 10
CTMUICON<1:0> = 11
IOUT3 CTMU Current Source,
100x Range
Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000).
2010 Microchip Technology Inc.
DS39933D-page 405
PIC18F87J90 FAMILY
TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
10K
—
—
—
E/W -40C to +85C
VPR
VDD for Read
VMIN
3.6
V
VMIN = Minimum operating
voltage
D132B VPEW Voltage for Self-Timed Erase or
Write operations
VDD
VDDCORE
2.35
2.25
—
—
3.6
2.7
V
V
ENVREG tied to VDD
ENVREG tied to VSS
D133A TIW
D133B TIE
Self-Timed Write Cycle Time
—
—
2.8
33
—
—
ms
ms
Self-Timed Block Erased Cycle
Time
D134 TRETD Characteristic Retention
20
—
—
—
3
—
14
1
Year Provided no other
specifications are violated
D135
D140
IDDP
Supply Current during
Programming
mA
TWE
Writes per Erase Cycle
—
For each physical address
†
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS39933D-page 406
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 28-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V VDD 3.6V, -40°C TA +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
D300
VIOFF
—
0
±5.0
—
±25
AVDD – 1.5
—
mV
V
D301
D302
D303
D304
VICM
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time(1)
CMRR
TRESP
55
—
—
—
dB
ns
s
150
—
400
TMC2OV Comparator Mode Change to
Output Valid*
10
Note 1: Response time measured with one comparator input at (AVDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 28-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V VDD 3.6V, -40°C TA +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Resolution
Min
Typ
Max
Units
Comments
D310
VRES
VDD/24
—
—
—
2k
—
VDD/32
1/2
LSb
LSb
D311
D312
D313
VRAA
VRUR
TSET
Absolute Accuracy
Unit Resistor Value (R)
Settling Time(1)
—
—
—
10
s
Note 1: Settling time measured while CVRR = 1and CVR<3:0> transitions from ‘0000’ to ‘1111’.
TABLE 28-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C TA +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
Comments
VRGOUT Regulator Output Voltage
External Filter Capacitor Value
—
2.5
10
—
—
V
CEFC
4.7
F
Capacitor must be
low-ESR, a low series
resistance (< 5)
TABLE 28-5: INTERNAL LCD VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Fly Back Capacitor
Min
Typ
Max
Units
Comments
CFLY
VBIAS
0.47
—
4.7
—
3.6
—
—
—
—
—
—
—
F
V
V
V
V
V
V
V
V
Capacitor must be low-ESR
BIAS<2:0> = 111
BIAS<2:0> = 110
BIAS<2:0> = 101
BIAS<2:0> = 100
BIAS<2:0> = 011
BIAS<2:0> = 010
BIAS<2:0> = 001
BIAS<2:0> = 000
VPK-PK between LCDBIAS0 &
LCDBIAS3
3.40
3.27
3.14
3.01
2.88
2.75
2.62
2.49
—
—
—
—
—
—
—
2010 Microchip Technology Inc.
DS39933D-page 407
PIC18F87J90 FAMILY
28.5 AC (Timing) Characteristics
28.5.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T13CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
L
Invalid (High-impedance)
Low
Valid
High-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
Start condition
STO
Stop condition
DS39933D-page 408
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
28.5.2
TIMING CONDITIONS
The temperature and voltages specified in Table 28-6
apply to all timing specifications unless otherwise
noted. Figure 28-3 specifies the load conditions for the
timing specifications.
TABLE 28-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for industrial
Operating voltage VDD range as described in Section 28.1 and Section 28.3.
FIGURE 28-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1
VDD/2
Load Condition 2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464
CL = 50 pF for all pins except OSC2/CLKO/RA6
and including D and E outputs as ports
CL = 15 pF for OSC2/CLKO/RA6
2010 Microchip Technology Inc.
DS39933D-page 409
PIC18F87J90 FAMILY
28.5.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 28-4:
EXTERNAL CLOCK TIMING
Q4
Q1
1
Q2
Q3
Q4
4
Q1
OSC1
CLKO
3
3
4
2
TABLE 28-7: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
FOSC
External CLKI Frequency(1)
DC
DC
4
48
10
25
10
—
MHz EC Oscillator mode
ECPLL Oscillator mode
MHz HS Oscillator mode
HSPLL Oscillator mode
Oscillator Frequency(1)
External CLKI Period(1)
Oscillator Period(1)
4
1
TOSC
TCY
20.8
100
40.0
100
83.3
10
ns
EC Oscillator mode
—
ECPLL Oscillator mode
HS Oscillator mode
250
250
—
ns
HSPLL Oscillator mode
TCY = 4/FOSC, Industrial
HS Oscillator mode
2
3
Instruction Cycle Time(1)
ns
ns
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
—
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
—
7.5
ns
HS Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39933D-page 410
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 28-8: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.15V TO 3.6V)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
F10
F11
F12
F13
FOSC Oscillator Frequency Range
4
—
—
—
—
10
40
2
MHz HS mode only
FSYS On-Chip VCO System Frequency
16
—
-2
MHz HS mode only
trc
PLL Start-up Time (Lock Time)
ms
%
CLK CLKO Stability (Jitter)
+2
†
Data in “Typ” column is at 3.3V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 28-9: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)
PIC18F87J90 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Param
No.
Device
Min
Typ
Max
Units
Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1)
All Devices
-2
-5
+/-1
—
2
5
%
%
%
+25°C
VDD = 2.7-3.3V
VDD = 2.0-3.3V
VDD = 2.0-3.3V
-10°C to +85°C
-40°C to +85°C
-10
+/-1
10
INTRC Accuracy @ Freq = 31 kHz(1)
All Devices 21.7
—
40.3
kHz
-40°C to +85°C
VDD = 2.0-3.3V
Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given
time. When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’,
use the INTRC accuracy specification.
2010 Microchip Technology Inc.
DS39933D-page 411
PIC18F87J90 FAMILY
FIGURE 28-5:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
14
12
19
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Refer to Figure 28-3 for load conditions.
Note:
TABLE 28-10: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TOSH2CKL OSC1 to CLKO
TOSH2CKH OSC1 to CLKO
—
75
75
15
15
—
—
—
50
—
200
200
30
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
11
12
13
14
15
16
17
18
—
TCKR
TCKF
CLKO Rise Time
CLKO Fall Time
—
—
30
TCKL2IOV CLKO to Port Out Valid
TIOV2CKH Port In Valid before CLKO
TCKH2IOI Port In Hold after CLKO
TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid
—
0.5 TCY + 20 ns
0.25 TCY + 25
—
—
ns
ns
ns
ns
0
—
150
—
TOSH2IOI OSC1 (Q2 cycle) to Port Input Invalid
100
(I/O in hold time)
19
TIOV2OSH Port Input Valid to OSC1
0
—
—
ns
(I/O in setup time)
20
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
Port Output Fall Time
INTx pin High or Low Time
—
—
—
—
—
—
6
5
ns
ns
ns
ns
21
22†
23†
TCY
TCY
—
—
RB<7:4> Change INTx High or Low
Time
†
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC.
DS39933D-page 412
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 28-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 28-3 for load conditions.
TABLE 28-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
(Note 1)
30
TMCL
MCLR Pulse Width (low)
2 TCY
10
—
TCY
31
TWDT
Watchdog Timer Time-out Period
(no postscaler)
3.4
4.0
4.6
ms
32
33
34
TOST
Oscillation Start-up Timer Period
1024 TOSC
45.8
—
65.5
2
1024 TOSC
85.2
TOSC = OSC1 period
TPWRT Power-up Timer Period
ms
µs
TIOZ
I/O High-Impedance from MCLR
—
—
Low or Watchdog Timer Reset
38
TCSD
CPU Start-up Time
—
10
—
µs
200
µs Voltage Regulator
enabled and put to
sleep
39
TIOBST Time for INTOSC to Stabilize
—
1
—
µs
Note 1: To ensure device Reset, MCLR must be low for at least 2 TCY or 400 s, whichever is lower.
2010 Microchip Technology Inc.
DS39933D-page 413
PIC18F87J90 FAMILY
FIGURE 28-7:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 28-3 for load conditions.
TABLE 28-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
40
TT0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4,..., 256)
45
46
47
TT1H
TT1L
TT1P
T13CKI High Synchronous, no prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Time
Synchronous, with prescaler
10
Asynchronous
30
0.5 TCY + 5
10
T13CKI Low Synchronous, no prescaler
Time
Synchronous, with prescaler
Asynchronous
30
T13CKI Input Synchronous
Period
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
FT1
T13CKI Oscillator Input Frequency Range
48
TCKE2TMRI Delay from External T13CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
DS39933D-page 414
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 28-8:
CAPTURE/COMPARE/PWM TIMINGS (CCP1, CCP2 MODULES)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Note:
Refer to Figure 28-3 for load conditions.
TABLE 28-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1, CCP2 MODULES)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TCCL
CCPx Input Low No prescaler
0.5 TCY + 20
—
—
—
—
—
ns
ns
ns
ns
ns
Time
With prescaler
10
0.5 TCY + 20
10
51
52
TCCH
TCCP
CCPx Input
High Time
No prescaler
With prescaler
CCPx Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
53
54
TCCR
TCCF
CCPx Output Fall Time
CCPx Output Fall Time
—
—
25
25
ns
ns
2010 Microchip Technology Inc.
DS39933D-page 415
PIC18F87J90 FAMILY
FIGURE 28-9:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
70
SCK
(CKP = 0)
78
79
79
78
SCK
(CKP = 1)
80
bit 6 - - - - - - 1
MSb
LSb
SDO
SDI
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
73
Note: Refer to Figure 28-3 for load conditions.
TABLE 28-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
20
—
—
—
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
40
ns
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDO Data Output Rise Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDO Data Output Fall Time
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39933D-page 416
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 28-10:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
81
SCK
(CKP = 0)
79
78
73
SCK
(CKP = 1)
80
bit 6 - - - - - - 1
LSb
MSb
SDO
SDI
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
Note: Refer to Figure 28-3 for load conditions.
TABLE 28-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
20
—
—
—
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
40
ns
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDO Data Output Rise Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDO Data Output Fall Time
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
81
TDOV2SCH, SDO Data Output Setup to SCK Edge
TDOV2SCL
TCY
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
2010 Microchip Technology Inc.
DS39933D-page 417
PIC18F87J90 FAMILY
FIGURE 28-11:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
LSb
SDO
SDI
bit 6 - - - - - - 1
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
73
Note:
Refer to Figure 28-3 for load conditions.
TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS to SCK or SCK Input
3 TCY
—
ns
TSSL2SCL
70A
71
TSSL2WB SS to write to SSPBUF
3 TCY
—
—
—
—
—
—
ns
TSCH
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
ns
71A
72
40
ns (Note 1)
TSCL
SCK Input Low Time
(Slave mode)
1.25 TCY + 30
ns
72A
73
40
20
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
40
ns
75
76
77
78
79
80
TDOR
TDOF
SDO Data Output Rise Time
SDO Data Output Fall Time
—
—
10
—
—
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TSSH2DOZ SS to SDO Output High-Impedance
TSCR
TSCF
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
83
TSCH2SSH, SS after SCK Edge
1.5 TCY + 40
—
ns
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39933D-page 418
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 28-12:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
bit 6 - - - - - - 1
LSb
SDO
SDI
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
Note: Refer to Figure 28-3 for load conditions.
TABLE 28-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS to SCK or SCK Input
3 TCY
—
ns
TSSL2SCL
70A
71
TSSL2WB SS to write to SSPBUF
3 TCY
1.25 TCY + 30
40
—
—
—
—
—
—
—
ns
TSCH
TSCL
TB2B
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
ns
71A
72
ns (Note 1)
ns
SCK Input Low Time
(Slave mode)
1.25 TCY + 30
40
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
40
75
76
77
78
79
80
TDOR
TDOF
SDO Data Output Rise Time
SDO Data Output Fall Time
—
—
10
—
—
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TSSH2DOZ SS to SDO Output High-Impedance
TSCR
TSCF
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
82
83
TSSL2DOV SDO Data Output Valid after SS Edge
—
50
—
ns
ns
TSCH2SSH, SS after SCK Edge
1.5 TCY + 40
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
2010 Microchip Technology Inc.
DS39933D-page 419
PIC18F87J90 FAMILY
FIGURE 28-13:
I2C™ BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 28-3 for load conditions.
TABLE 28-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
Start condition
91
92
93
THD:STA Start Condition
Hold Time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO Stop Condition
Setup Time
4700
600
THD:STO Stop Condition
Hold Time
4000
600
DS39933D-page 420
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
FIGURE 28-14:
I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 28-3 for load conditions.
TABLE 28-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock High Time
Clock Low Time
4.0
0.6
—
—
s
s
400 kHz mode
MSSP Module
100 kHz mode
400 kHz mode
MSSP Module
1.5 TCY
4.7
—
101
TLOW
—
s
s
1.3
—
1.5 TCY
—
—
102
103
TR
SDA and SCL Rise Time 100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
TF
SDA and SCL Fall Time
100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
90
TSU:STA
Start Condition Setup Time 100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
s
s
s
s
ns
s
ns
ns
s
s
ns
ns
s
s
pF
Only relevant for Repeated
Start condition
91
THD:STA Start Condition Hold Time 100 kHz mode
400 kHz mode
—
After this period, the first clock
pulse is generated
—
106
107
92
THD:DAT Data Input Hold Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT Data Input Setup Time
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO Stop Condition Setup Time 100 kHz mode
400 kHz mode
—
—
109
110
D102
TAA
TBUF
CB
Output Valid from Clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
—
Bus Free Time
4.7
1.3
—
—
Time the bus must be free before
a new transmission can start
—
Bus Capacitive Loading
400
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2
2
2: A Fast mode I C™ bus device can be used in a Standard mode I C bus system, but the requirement, TSU:DAT 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
2
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCL line
is released.
2010 Microchip Technology Inc.
DS39933D-page 421
PIC18F87J90 FAMILY
FIGURE 28-15:
MSSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
SCL
93
91
90
92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 28-3 for load conditions.
TABLE 28-20: MSSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start
condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
FIGURE 28-16:
MSSP I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 28-3 for load conditions.
DS39933D-page 422
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 28-21: MSSP I2C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100
101
102
103
90
THIGH
Clock High
Time
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
—
TLOW
TR
Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
—
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
SDA and SCL 100 kHz mode
Rise Time
—
1000
300
300
300
300
100
—
CB is specified to be from
10 to 400 pF
400 kHz mode
20 + 0.1 CB
ns
1 MHz mode(1)
—
ns
TF
SDA and SCL 100 kHz mode
Fall Time
—
20 + 0.1 CB
—
ns
CB is specified to be from
10 to 400 pF
400 kHz mode
1 MHz mode(1)
ns
ns
TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1)
ms Only relevant for Repeated
Setup Time
Start condition
400 kHz mode 2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
91
THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1)
—
ms After this period, the first
Hold Time
clock pulse is generated
400 kHz mode 2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ns
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
0
—
0
0.9
—
ms
TSU:DAT Data Input
Setup Time
250
100
ns
ns
(Note 2)
—
TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1)
—
ms
ms
ms
ns
Setup Time
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
109
TAA
Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
—
3500
1000
—
ns
—
ns
110
TBUF
CB
Bus Free Time 100 kHz mode
400 kHz mode
4.7
1.3
—
ms Time the bus must be free
before a new transmission
—
ms
can start
pF
D102
Bus Capacitive Loading
—
400
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.
2010 Microchip Technology Inc.
DS39933D-page 423
PIC18F87J90 FAMILY
FIGURE 28-17:
EUSART/AUSART SYNCHRONOUSTRANSMISSION (MASTER/SLAVE)TIMING
TXx/CKx
pin
121
121
RXx/DTx
pin
120
Note: Refer to Figure 28-3 for load conditions.
122
TABLE 28-22: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TCKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid
—
—
—
40
20
20
ns
ns
ns
121
122
TCKRF
TDTRF
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
FIGURE 28-18:
EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TXx/CKx
pin
125
RXx/DTx
pin
126
Note: Refer to Figure 28-3 for load conditions.
TABLE 28-23: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx (DTx hold time)
10
15
—
—
ns
ns
126
TCKL2DTL Data Hold after CKx (DTx hold time)
DS39933D-page 424
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
TABLE 28-24: A/D CONVERTER CHARACTERISTICS: PIC18F87J90 FAMILY (INDUSTRIAL)
Param
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
No.
A01
NR
Resolution
—
—
—
—
—
—
10
bits
A03
A04
A06
A07
A10
A20
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
—
<±1
<±1
<±3
<±3
LSb VREF 3.0V
LSb VREF 3.0V
LSb VREF 3.0V
LSb VREF 3.0V
EDL
EOFF
EGN
—
—
—
Gain Error
—
Monotonicity
Guaranteed(1)
—
VSS VAIN VREF
VREF Reference Voltage Range
2.0
2.0
—
—
—
—
V
V
VDD 3.0V
VDD 3.0V
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VSS + VREF
VSS – 0.3V
VREFL
—
—
—
—
VDD
VDD – 3.0V
VREFH
V
V
VREFL
VAIN
Reference Voltage Low
Analog Input Voltage
V
ZAIN
Recommended Impedance of
Analog Voltage Source
—
2.5
k
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
A During VAIN acquisition.
A During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
2010 Microchip Technology Inc.
DS39933D-page 425
PIC18F87J90 FAMILY
FIGURE 28-19:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
OLD_DATA
TCY (Note 1)
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction to
be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 28-25: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
0.7
—
25.0(1)
s TOSC based, VREF 3.0V
s A/D RC mode
TAD
1
131
TCNV
Conversion Time
11
12
(not including acquisition time)(2)
132
135
136
TACQ
TSWC
TDIS
Acquisition Time(3)
1.4
—
—
(Note 4)
—
s -40C to +85C
Switching Time from Convert Sample
Discharge Time
0.2
s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
4: On the following cycle of the device clock.
DS39933D-page 426
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
29.0 PACKAGING INFORMATION
29.1 Package Marking Information
64-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
18F65J90
-I/PT
1010017
e
3
80-Lead TQFP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC18F85J90
-I/PT
1010017
e
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2010 Microchip Technology Inc.
DS39933D-page 427
PIC18F87J90 FAMILY
29.2 Package Details
The following sections give the technical details of the
packages.
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ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ
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D1
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e
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b
1 2 3
NOTE 1
c
NOTE 2
α
A
φ
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A1
β
L
L1
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ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅꢘꢍꢃꢌ4ꢄꢈ!!
ꢗ&ꢆꢄ#ꢋ%%ꢅꢅ
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ꢈ
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9 ꢈꢉꢆꢇꢇꢅ?ꢃ#&ꢍ
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ꢓꢁꢓꢛ
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ꢎꢁ +ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢏ&ꢃꢋꢄꢆꢇ,ꢅ!ꢃ-ꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ
ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ
ꢔꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢕꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢕꢅꢏꢈꢉꢅꢖꢗꢒ.ꢅ0ꢀꢔꢁ/ꢒꢁ
1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢓ@/1
DS39933D-page 428
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘꢙꢚꢘꢙꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
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2010 Microchip Technology Inc.
DS39933D-page 429
PIC18F87J90 FAMILY
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D
D1
E
e
E1
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b
NOTE 1
12 3
α
NOTE 2
A
c
φ
A2
β
A1
L1
L
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9 ꢈꢉꢆꢇꢇꢅ<ꢈꢃꢕꢍ&
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ꢓꢁꢓꢛ
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ꢁ
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' ꢋꢄꢊ(
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ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ
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DS39933D-page 430
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
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2010 Microchip Technology Inc.
DS39933D-page 431
PIC18F87J90 FAMILY
NOTES:
DS39933D-page 432
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
APPENDIX A: REVISION HISTORY
APPENDIX B: MIGRATION FROM
PIC18F85J90 TO
Revision A (October 2008)
PIC18F87J90
Original data sheet for PIC18F87J90 family devices.
Devices in the PIC18F87J90 and PIC18F85J90 fami-
lies are almost similar in their functions and features.
Code can be migrated from the 18F85J90 to the
PIC18F87J90 without many changes. The differences
between the two device families are listed in Table B-1.
Revision B (December 2008)
Changes to Section 28.2 “DC Characteristics:
Power-Down and Supply Current PIC18F87J90
Family (Industrial)” and removal of Section 27.5 “DC
Characteristics: RTCC Power-Down Current (IPD)”.
Revision C (February 2009)
Added register CONFIG3L to Section 25.0 “Special
Features of the CPU” and made minor corrections.
Revision D (January 2010)
Added 60°C IPD specification to Section 28.0 “Electri-
cal Characteristics”. Removed Preliminary condition
tag. Minor edits to text throughout the document.
TABLE B-1:
NOTABLE DIFFERENCES BETWEEN PIC18F87J90 AND PIC18F85J90 FAMILIES
Characteristic
18F85J90 Family
PIC18F87J90 Family
Max Operating Frequency
Max Program Memory
Data Memory
48 MHz
40 MHz
128 Kbytes
32 Kbytes
3,923 Bytes
2,048 Bytes
Program Memory Endurance
Single-Word Write for Flash
Oscillator Options
CTMU
10,000 Write/Erase (minimum)
1,000 Write/Erase (minimum)
Yes
No
PLL can be used with INTOSC
PLL cannot be used with INTOSC
Yes
Yes
No
No
No
RTCC
Timer1 Oscillator Options
Low-power oscillator option for
Timer1
TICKI Clock
T1CKI can be used as a clock without
enabling the Timer1 oscillator
No
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
NOTES:
DS39933D-page 434
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
INDEX
Baud Rates, Asynchronous Modes .................. 279
High Baud Rate Select (BRGH Bit) .................. 278
Operation in Power-Managed Modes............... 278
Sampling .......................................................... 278
Synchronous Master Mode....................................... 284
Associated Registers, Receive......................... 286
Associated Registers, Transmit........................ 285
Reception ......................................................... 286
Transmission .................................................... 284
Synchronous Slave Mode......................................... 287
Associated Registers, Receive......................... 288
Associated Registers, Transmit........................ 287
Reception ......................................................... 288
Transmission .................................................... 287
A
A/D.................................................................................... 289
A/D Converter Interrupt, Configuring ........................ 293
Acquisition Requirements ......................................... 294
ADCAL Bit................................................................. 297
ADCON0 Register..................................................... 289
ADCON1 Register..................................................... 289
ADCON2 Register..................................................... 289
ADRESH Register............................................. 289, 292
ADRESL Register ..................................................... 289
Analog Port Pins, Configuring................................... 295
Associated Registers ................................................ 297
Automatic Selecting and Configuring
Acquisition Time ............................................... 295
Configuring the Module............................................. 293
Conversion Clock (TAD) ............................................ 295
Conversion Requirements ........................................ 426
Conversion Status (GO/DONE Bit)........................... 292
Conversions.............................................................. 296
Converter Calibration................................................ 297
Converter Characteristics ......................................... 425
Operation in Power-Managed Modes ....................... 297
Special Event Trigger (CCP)..................................... 296
Use of the CCP2 Trigger........................................... 296
Absolute Maximum Ratings .............................................. 393
AC (Timing) Characteristics.............................................. 408
Load Conditions for Device
Timing Specifications....................................... 409
Parameter Symbology .............................................. 408
Temperature and Voltage Specifications.................. 409
Timing Conditions ..................................................... 409
ACKSTAT ......................................................................... 245
ACKSTAT Status Flag ...................................................... 245
ADCAL Bit......................................................................... 297
ADCON0 Register............................................................. 289
GO/DONE Bit............................................................ 292
ADCON1 Register............................................................. 289
ADCON2 Register............................................................. 289
ADDFSR ........................................................................... 382
ADDLW ............................................................................. 345
Addressable Universal Synchronous Asynchronous
Receiver Transmitter (AUSART). See AUSART.
B
Baud Rate Generator ....................................................... 241
BC..................................................................................... 347
BCF .................................................................................. 348
BF ..................................................................................... 245
BF Status Flag.................................................................. 245
Bias Generation (LCD)
Charge Pump Design Considerations ...................... 193
Block Diagrams
A/D............................................................................ 292
Analog Input Model................................................... 293
AUSART Receive..................................................... 282
AUSART Transmit.................................................... 280
Baud Rate Generator ............................................... 241
Capture Mode Operation.......................................... 176
Clock Source Multiplexing ........................................ 166
Comparator Analog Input Model............................... 303
Comparator I/O Operating Modes ............................ 300
Comparator Output................................................... 302
Comparator Voltage Reference................................ 306
Comparator Voltage Reference
Output Buffer Example ..................................... 307
Compare Mode Operation........................................ 177
Connections for On-Chip Voltage Regulator ............ 333
CTMU ....................................................................... 309
CTMU Current Source Calibration Circuit ................ 312
CTMU Typical Connections and Internal
Configuration for Pulse Delay Generation........ 320
CTMU Typical Connections and Internal
ADDULNK......................................................................... 382
ADDWF............................................................................. 345
ADDWFC .......................................................................... 346
ADRESH Register............................................................. 289
ADRESL Register ..................................................... 289, 292
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................. 346
ANDWF............................................................................. 347
Assembler
Configuration for Time Measurement............... 319
Device Clock............................................................... 35
EUSART Receive..................................................... 266
EUSART Transmit.................................................... 264
External Power-on Reset Circuit
(Slow VDD Power-up) ......................................... 55
Fail-Safe Clock Monitor ............................................ 335
Generic I/O Port Operation....................................... 117
Interrupt Logic........................................................... 102
LCD Clock Generation.............................................. 188
LCD Driver Module................................................... 183
LCD Regulator Connections (M0 and M1) ............... 190
MPASM Assembler................................................... 390
AUSART
Asynchronous Mode ................................................. 280
Associated Registers, Receive ......................... 283
Associated Registers, Transmit ........................ 281
Receiver............................................................ 282
Setting up 9-Bit Mode with
2
MSSP (I C Master Mode)......................................... 239
2
MSSP (I C Mode)..................................................... 220
MSSP (SPI Mode) .................................................... 211
On-Chip Reset Circuit................................................. 53
PIC18F6XJ90 (64-Pin) ............................................... 12
PIC18F8XJ90 (80-Pin) ............................................... 13
PLL ............................................................................. 40
PWM Operation (Simplified)..................................... 179
Address Detect ......................................... 282
Transmitter........................................................ 280
Baud Rate Generator (BRG)..................................... 278
Associated Registers........................................ 278
Baud Rate Error, Calculating ............................ 278
2010 Microchip Technology Inc.
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Reads From Flash Program Memory..........................93
Resistor Ladder Connections for
M2 Configuration...............................................191
Resistor Ladder Connections for
Measuring Capacitance with the CTMU ................... 317
Measuring Time........................................................ 319
Module Initialization .................................................. 311
Operation.................................................................. 310
During Sleep and Idle Modes ........................... 320
Clock Sources..................................................................... 37
Default System Clock on Reset.................................. 38
Selection Using OSCCON Register............................ 38
CLRF ................................................................................ 355
CLRWDT .......................................................................... 355
Code Examples
M3 Configuration...............................................192
RTCC ........................................................................155
Single Comparator ....................................................301
SPI Master/Slave Connection ...................................215
Table Read Operation.................................................89
Table Write Operation.................................................90
Table Writes to Flash Program Memory .....................95
Timer0 in 16-Bit Mode...............................................140
Timer0 in 8-Bit Mode.................................................140
Timer1 (16-Bit Read/Write Mode) .............................144
Timer1 (8-Bit Mode)..................................................144
Timer2.......................................................................150
Timer3 (16-Bit Read/Write Mode) .............................152
Timer3 (8-Bit Mode)..................................................152
Watchdog Timer........................................................331
BN .....................................................................................348
BNC...................................................................................349
BNN...................................................................................349
BNOV................................................................................350
BNZ...................................................................................350
BOR. See Brown-out Reset.
16 x 16 Signed Multiply Routine ............................... 100
16 x 16 Unsigned Multiply Routine ........................... 100
8 x 8 Signed Multiply Routine ..................................... 99
8 x 8 Unsigned Multiply Routine ................................. 99
Capacitance Calibration Routine .............................. 316
Changing Between Capture Prescalers.................... 176
Computed GOTO Using an Offset Value.................... 69
Current Calibration Routine ...................................... 314
Erasing Flash Program Memory................................. 94
Fast Register Stack .................................................... 69
How to Clear RAM (Bank 1) Using Indirect Addressing .
82
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service................................... 147
Initializing PORTA..................................................... 118
Initializing PORTB..................................................... 120
Initializing PORTC .................................................... 123
Initializing PORTD .................................................... 126
Initializing PORTE..................................................... 128
Initializing PORTF..................................................... 130
Initializing PORTG .................................................... 133
Initializing PORTH .................................................... 135
Initializing PORTJ ..................................................... 137
Loading the SSPBUF (SSPSR) Register.................. 214
Reading a Flash Program Memory Word ................... 93
Routine for Capacitive Touch Switch........................ 318
Saving STATUS, WREG and BSR
BOV...................................................................................353
BRA...................................................................................351
Break Character (12-Bit) Transmit and Receive ...............269
BRG. See Baud Rate Generator.
BRGH Bit
TXSTA1 Register......................................................259
TXSTA2 Register......................................................278
Brown-out Reset (BOR) ......................................................55
and On-Chip Voltage Regulator................................334
Detecting.....................................................................55
BSF ...................................................................................351
BTFSC ..............................................................................352
BTFSS...............................................................................352
BTG...................................................................................353
BZ......................................................................................354
Registers in RAM.............................................. 116
Setting the RTCWREN Bit........................................ 167
Setup for CTMU Calibration Routines ...................... 313
Single-Word Write to Flash Program Memory............ 97
Writing to Flash Program Memory.............................. 96
Code Protection................................................................ 325
COMF ............................................................................... 356
Comparator....................................................................... 299
Analog Input Connection Considerations ................. 303
Associated Registers................................................ 303
Configuration ............................................................ 300
Effects of a Reset ..................................................... 302
Interrupts .................................................................. 302
Operation.................................................................. 301
Operation During Sleep ............................................ 302
Outputs ..................................................................... 301
Reference ................................................................. 301
External Signal ................................................. 301
Internal Signal................................................... 301
Response Time......................................................... 301
Comparator Specifications................................................ 407
Comparator Voltage Reference........................................ 305
Accuracy and Error................................................... 306
Associated Registers................................................ 307
Configuring ............................................................... 305
Connection Considerations....................................... 306
Effects of a Reset ..................................................... 306
C
C Compilers
MPLAB C18 ..............................................................390
CALL .................................................................................354
CALLW..............................................................................383
Capture (CCP Module)......................................................176
CCP Pin Configuration..............................................176
CCPR2H:CCPR2L Registers....................................176
Software Interrupt .....................................................176
Timer1/Timer3 Mode Selection.................................176
Capture/Compare/PWM (CCP).........................................173
Capture Mode. See Capture.
CCP Mode and Timer Resources.............................174
CCPRxH Register.....................................................174
CCPRxL Register......................................................174
Compare Mode. See Compare.
Configuration.............................................................174
Interaction of CCP1 and CCP2 for
Timer Resources...............................................175
Interconnect Configurations ......................................174
Charge Time Measurement Unit (CTMU) .........................309
Associated Registers ................................................323
Calibrating the Module ..............................................311
Creating a Delay .......................................................320
Effects of a Reset......................................................320
DS39933D-page 436
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PIC18F87J90 FAMILY
Operation During Sleep ............................................ 306
Compare (CCP Module) ................................................... 177
Capture, Compare, Timer1, Timers Associated
E
Effect on Standard PIC18 Instructions.............................. 386
Effects of Power-Managed Modes on Various
Registers........................................................... 178
Clock Sources ............................................................ 43
Electrical Characteristics .................................................. 393
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
ENVREG Pin .................................................................... 333
Equations
CCP Pin Configuration.............................................. 177
CCPR2 Register ....................................................... 177
Software Interrupt ..................................................... 177
Special Event Trigger................................ 153, 177, 296
Timer1/Timer3 Mode Selection................................. 177
Computed GOTO................................................................ 69
Configuration Bits.............................................................. 325
Configuration Mismatch (CM) ............................................. 55
Configuration Register Protection ..................................... 337
Core Features
16 x 16 Signed Multiplication Algorithm.................... 100
16 x 16 Unsigned Multiplication Algorithm................ 100
A/D Acquisition Time ................................................ 294
A/D Minimum Charging Time ................................... 294
Calculating the Minimum Required
Easy Migration .............................................................. 9
Extended Instruction Set............................................... 9
Memory Options............................................................ 9
nanoWatt Technology................................................... 9
Oscillator Options and Features ................................... 9
CPFSEQ ........................................................................... 356
CPFSGT ........................................................................... 357
CPFSLT ............................................................................ 357
Crystal Oscillator/Ceramic Resonator................................. 39
Customer Change Notification Service ............................. 445
Customer Notification Service........................................... 445
Customer Support............................................................. 445
Acquisition Time ............................................... 294
Converting Error, Clock Pulses ................................ 168
LCD Static and Dynamic Current ............................. 193
Errata.................................................................................... 8
EUSART
Asynchronous Mode................................................. 264
12-Bit Break Transmit and Receive.................. 269
Associated Registers, Receive......................... 267
Associated Registers, Transmit........................ 265
Auto-Wake-up on Sync Break Character ......... 268
Receiver ........................................................... 266
Setting up 9-Bit Mode with
Address Detect......................................... 266
Transmitter ....................................................... 264
Baud Rate Generator (BRG) .................................... 259
Associated Registers........................................ 259
Auto-Baud Rate Detect..................................... 262
Baud Rate Error, Calculating............................ 259
Baud Rates, Asynchronous Modes .................. 260
High Baud Rate Select (BRGH Bit) .................. 259
Operation in Power-Managed Modes............... 259
Sampling .......................................................... 259
Synchronous Master Mode....................................... 270
Associated Registers, Receive......................... 272
Associated Registers, Transmit........................ 271
Reception ......................................................... 272
Transmission .................................................... 270
Synchronous Slave Mode......................................... 273
Associated Registers, Receive......................... 274
Associated Registers, Transmit........................ 273
Reception ......................................................... 274
Transmission .................................................... 273
Extended Instruction Set
ADDFSR................................................................... 382
ADDULNK ................................................................ 382
CALLW ..................................................................... 383
MOVSF..................................................................... 383
MOVSS..................................................................... 384
PUSHL...................................................................... 384
SUBFSR................................................................... 385
SUBULNK................................................................. 385
External Oscillator Modes
D
Data Addressing Modes...................................................... 82
Comparing Addressing Modes with the
Extended Instruction Set Enabled ...................... 86
Direct........................................................................... 82
Indexed Literal Offset.................................................. 85
BSR .................................................................... 87
Instructions Affected ........................................... 85
Mapping Access Bank ........................................ 87
Indirect ........................................................................ 82
Inherent and Literal..................................................... 82
Data Memory ...................................................................... 72
Access Bank ............................................................... 74
Bank Select Register (BSR)........................................ 72
Extended Instruction Set............................................. 85
General Purpose Registers......................................... 74
Memory Maps
PIC18FX6J90/X7J90 Devices ............................ 73
Special Function Registers ................................. 75
Special Function Registers ......................................... 75
DAW.................................................................................. 358
DC Characteristics ............................................................ 404
Power-Down and Supply Current ............................. 396
Supply Voltage.......................................................... 395
DCFSNZ ........................................................................... 359
DECF ................................................................................ 358
DECFSZ............................................................................ 359
Default System Clock.......................................................... 38
Details on Individual Family Members ................................ 10
Development Support ....................................................... 389
Device Overview ................................................................... 9
Features (64-Pin Devices) .......................................... 11
Features (80-Pin Devices) .......................................... 11
Direct Addressing................................................................ 83
Clock Input (EC Modes) ............................................. 40
HS............................................................................... 39
2010 Microchip Technology Inc.
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PIC18F87J90 FAMILY
Master Mode............................................................. 239
Baud Rate Generator ....................................... 241
Operation.......................................................... 240
Reception ......................................................... 245
Repeated Start Condition Timing ..................... 244
Start Condition Timing...................................... 243
Transmission .................................................... 245
Multi-Master Communication, Bus Collision
F
Fail-Safe Clock Monitor............................................. 325, 335
Exiting Fail-Safe Operation .......................................336
Interrupts in Power-Managed Modes........................336
POR or Wake-up From Sleep ...................................336
WDT During Oscillator Failure ..................................335
Fast Register Stack.............................................................69
Firmware Instructions........................................................339
Flash Configuration Words................................................325
Flash Program Memory.......................................................89
Associated Registers ..................................................98
Control Registers ........................................................90
EECON1 and EECON2 ......................................90
TABLAT (Table Latch) Register..........................92
TBLPTR (Table Pointer) Register.......................92
Erase Sequence .........................................................94
Erasing........................................................................94
Operation During Code-Protect ..................................98
Reading.......................................................................93
Table Pointer
Boundaries Based on Operation.........................92
Table Pointer Boundaries ...........................................92
Table Reads and Table Writes ...................................89
Write Sequence ..........................................................95
Write Sequence (Word Programming)........................97
Writing.........................................................................95
Unexpected Termination.....................................98
Write Verify .........................................................98
FSCM. See Fail-Safe Clock Monitor.
and Arbitration .................................................. 249
Multi-Master Mode.................................................... 249
Operation.................................................................. 225
Read/Write Bit Information (R/W Bit)................ 225, 227
Registers .................................................................. 220
Serial Clock (SCK/SCL)............................................ 227
Slave Mode............................................................... 225
Address Masking.............................................. 226
Addressing........................................................ 225
Reception ......................................................... 227
Transmission .................................................... 227
Sleep Operation........................................................ 249
Stop Condition Timing .............................................. 248
INCF ................................................................................. 360
INCFSZ............................................................................. 361
In-Circuit Debugger........................................................... 337
In-Circuit Serial Programming (ICSP)....................... 325, 337
Indexed Literal Offset Addressing
and Standard PIC18 Instructions.............................. 386
Indexed Literal Offset Mode.............................................. 386
Indirect Addressing............................................................. 83
INFSNZ............................................................................. 361
Initialization Conditions for all Registers....................... 59–64
Instruction Cycle ................................................................. 70
Clocking Scheme........................................................ 70
Flow/Pipelining............................................................ 70
Instruction Set................................................................... 339
ADDLW..................................................................... 345
ADDWF..................................................................... 345
ADDWF (Indexed Literal Offset Mode)..................... 387
ADDWFC.................................................................. 346
ANDLW..................................................................... 346
ANDWF..................................................................... 347
BC............................................................................. 347
BCF .......................................................................... 348
BN............................................................................. 348
BNC .......................................................................... 349
BNN .......................................................................... 349
BNOV ....................................................................... 350
BNZ .......................................................................... 350
BOV .......................................................................... 353
BRA .......................................................................... 351
BSF........................................................................... 351
BSF (Indexed Literal Offset Mode) ........................... 387
BTFSC...................................................................... 352
BTFSS ...................................................................... 352
BTG .......................................................................... 353
BZ ............................................................................. 354
CALL......................................................................... 354
CLRF ........................................................................ 355
CLRWDT .................................................................. 355
COMF ....................................................................... 356
CPFSEQ................................................................... 356
CPFSGT ................................................................... 357
CPFSLT.................................................................... 357
G
GOTO................................................................................360
H
Hardware Multiplier .............................................................99
8 x 8 Multiplication Algorithms ....................................99
Operation ....................................................................99
Performance Comparison (table)................................99
I
I/O Ports............................................................................117
Input Voltage Considerations....................................117
Open-Drain Outputs..................................................118
Output Pin Drive........................................................117
Pin Capabilities .........................................................117
Pull-up Configuration ................................................118
2
I C Mode (MSSP) .............................................................220
Acknowledge Sequence Timing................................248
Associated Registers ................................................254
Baud Rate Generator................................................241
Bus Collision
During a Repeated Start Condition...................252
During a Stop Condition....................................253
Clock Arbitration........................................................242
Clock Stretching........................................................234
10-Bit Slave Receive Mode (SEN = 1)..............234
10-Bit Slave Transmit Mode..............................234
7-Bit Slave Receive Mode (SEN = 1)................234
7-Bit Slave Transmit Mode................................234
Clock Synchronization and the CKP Bit....................235
Effects of a Reset......................................................249
General Call Address Support ..................................238
2
I C Clock Rate w/BRG..............................................241
DS39933D-page 438
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
DAW.......................................................................... 358
DCFSNZ ................................................................... 359
DECF ........................................................................ 358
DECFSZ.................................................................... 359
Extended Instructions ............................................... 381
Considerations when Enabling ......................... 386
Syntax............................................................... 381
Use with MPLAB IDE Tools .............................. 388
General Format......................................................... 341
GOTO ....................................................................... 360
INCF.......................................................................... 360
INCFSZ..................................................................... 361
INFSNZ..................................................................... 361
IORLW ...................................................................... 362
IORWF...................................................................... 362
LFSR......................................................................... 363
MOVF........................................................................ 363
MOVFF ..................................................................... 364
MOVLB ..................................................................... 364
MOVLW .................................................................... 365
MOVWF .................................................................... 365
MULLW..................................................................... 366
MULWF..................................................................... 366
NEGF........................................................................ 367
NOP .......................................................................... 367
Opcode Field Descriptions........................................ 340
POP .......................................................................... 368
PUSH........................................................................ 368
RCALL ...................................................................... 369
RESET...................................................................... 369
RETFIE ..................................................................... 370
RETLW ..................................................................... 370
RETURN................................................................... 371
RLCF......................................................................... 371
RLNCF...................................................................... 372
RRCF........................................................................ 372
RRNCF ..................................................................... 373
SETF......................................................................... 373
SETF (Indexed Literal Offset Mode) ......................... 387
SLEEP ...................................................................... 374
Standard Instructions................................................ 339
SUBFWB................................................................... 374
SUBLW ..................................................................... 375
SUBWF..................................................................... 375
SUBWFB................................................................... 376
SWAPF ..................................................................... 376
TBLRD ...................................................................... 377
TBLWT...................................................................... 378
TSTFSZ .................................................................... 379
XORLW..................................................................... 379
XORWF..................................................................... 380
Interrupt Sources .............................................................. 325
A/D Conversion Complete........................................ 293
Capture Complete (CCP) ......................................... 176
Compare Complete (CCP) ....................................... 177
Interrupt-on-Change (RB7:RB4)............................... 120
TMR0 Overflow......................................................... 141
TMR1 Overflow......................................................... 143
TMR2 to PR2 Match (PWM)..................................... 179
TMR3 Overflow................................................. 151, 153
Interrupts .......................................................................... 101
During, Context Saving............................................. 116
INTx Pin.................................................................... 116
PORTB, Interrupt-on-Change................................... 116
TMR0........................................................................ 116
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit).......................................................... 120
INTOSC, INTRC. See Internal Oscillator Block.
IORLW.............................................................................. 362
IORWF.............................................................................. 362
L
LCD
Associated Registers................................................ 209
Bias Generation........................................................ 189
Bias Configurations .......................................... 190
M0 and M1 ............................................... 190
M2 ............................................................ 191
M3 ............................................................ 192
Bias Types........................................................ 189
Voltage Regulator............................................. 189
Charge Pump ................................................... 190, 193
Clock Source Selection ............................................ 188
Configuring the Module ............................................ 208
Frame Frequency ..................................................... 194
Interrupts .................................................................. 206
LCDCON Register.................................................... 184
LCDDATA Registers................................................. 184
LCDPS Register ....................................................... 184
LCDREG Register .................................................... 184
LCDSE Registers ..................................................... 184
Multiplex Types......................................................... 193
Operation During Sleep............................................ 207
Pixel Control ............................................................. 193
Segment Enables ..................................................... 193
Waveform Generation .............................................. 194
LCD Driver.......................................................................... 10
LCDCON Register............................................................ 184
LCDDATA Registers......................................................... 184
LCDPS Register ............................................................... 184
LCDREG Register ............................................................ 184
LCDSE Registers.............................................................. 184
LFSR ................................................................................ 363
Liquid Crystal Display (LCD) Driver.................................. 183
Low-Voltage Detection...................................................... 333
INTCON Register
RBIF Bit..................................................................... 120
2
Inter-Integrated Circuit. See I C Mode.
Internal LCD Voltage Regulator Specifications................. 407
Internal Oscillator Block ...................................................... 41
Adjustment.................................................................. 42
INTIO Modes............................................................... 41
INTOSC Frequency Drift............................................. 42
INTOSC Output Frequency......................................... 42
INTPLL Modes............................................................ 41
Internal RC Oscillator
M
Master Clear (MCLR).......................................................... 55
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ......................................................... 65
Data Memory.............................................................. 72
Program Memory........................................................ 65
Memory Programming Requirements............................... 406
Microchip Internet Web Site.............................................. 445
Migration From PIC18F85J90 to PIC18F87J90................ 433
Use with WDT........................................................... 331
Internal Voltage Regulator Specifications......................... 407
Internet Address................................................................ 445
2010 Microchip Technology Inc.
DS39933D-page 439
PIC18F87J90 FAMILY
MOVF................................................................................363
MOVFF..............................................................................364
MOVLB..............................................................................364
MOVLW.............................................................................365
MOVSF .............................................................................383
MOVSS .............................................................................384
MOVWF ............................................................................365
MPLAB ASM30 Assembler, Linker, Librarian ...................390
MPLAB Integrated Development
Environment Software...............................................389
MPLAB PM3 Device Programmer.....................................392
MPLAB REAL ICE In-Circuit Emulator System.................391
MPLINK Object Linker/MPLIB Object Librarian ................390
MSSP
ACK Pulse......................................................... 225, 227
Control Registers (general).......................................211
Module Overview ......................................................211
SSPBUF Register .....................................................216
SSPSR Register .......................................................216
MULLW .............................................................................366
MULWF.............................................................................366
RB0/INT0/SEG30 ................................................. 15, 22
RB1/INT1/SEG8 ................................................... 15, 22
RB2/INT2/SEG9/CTED1....................................... 15, 22
RB3/INT3/SEG10/CTED2..................................... 15, 22
RB4/KBI0/SEG11 ................................................. 15, 22
RB5/KBI1/SEG29 ................................................. 15, 22
RB6/KBI2/PGC ..................................................... 15, 22
RB7/KBI3/PGD ..................................................... 15, 22
RC0/T1OSO/T13CKI ............................................ 16, 23
RC1/T1OSI/CCP2/SEG32.................................... 16, 23
RC2/CCP1/SEG13 ............................................... 16, 23
RC3/SCK/SCL/SEG17.......................................... 16, 23
RC4/SDI/SDA/SEG16........................................... 16, 23
RC5/SDO/SEG12 ................................................. 16, 23
RC6/TX1/CK1/SEG27 .......................................... 16, 23
RC7/RX1/DT1/SEG28 .......................................... 16, 23
RD0/SEG0/CTPLS ............................................... 17, 24
RD1/SEG1............................................................ 17, 24
RD2/SEG2............................................................ 17, 24
RD3/SEG3............................................................ 17, 24
RD4/SEG4............................................................ 17, 24
RD5/SEG5............................................................ 17, 24
RD6/SEG6............................................................ 17, 24
RD7/SEG7............................................................ 17, 24
RE0/LCDBIAS1 .................................................... 18, 25
RE1/LCDBIAS2 .................................................... 18, 25
RE3/COM0 ........................................................... 18, 25
RE4/COM1 ........................................................... 18, 25
RE5/COM2 ........................................................... 18, 25
RE6/COM3 ........................................................... 18, 25
RE7/CCP2/SEG31................................................ 18, 25
RF1/AN6/C2OUT/SEG19 ..................................... 19, 26
RF2/AN7/C1OUT/SEG20 ..................................... 19, 26
RF3/AN8/SEG21/C2INB....................................... 19, 26
RF4/AN9/SEG22/C2INA....................................... 19, 26
RF5/AN10/CVREF/SEG23/C1INB......................... 19, 26
RF6/AN11/SEG24/C1INA..................................... 19, 26
RF7/AN5/SS/SEG25............................................. 19, 26
RG0/LCDBIAS0.................................................... 20, 27
RG1/TX2/CK2....................................................... 20, 27
RG2/RX2/DT2/VLCAP1.......................................... 20, 27
RG3/VLCAP2 ......................................................... 20, 27
RG4/SEG26/RTCC............................................... 20, 27
RH0/SEG47................................................................ 28
RH1/SEG46................................................................ 28
RH2/SEG45................................................................ 28
RH3/SEG44................................................................ 28
RH4/SEG40................................................................ 28
RH5/SEG41................................................................ 28
RH6/SEG42................................................................ 28
RH7/SEG43................................................................ 28
RJ0 ............................................................................. 29
RJ1/SEG33................................................................. 29
RJ2/SEG34................................................................. 29
RJ3/SEG35................................................................. 29
RJ4/SEG39................................................................. 29
RJ5/SEG38................................................................. 29
RJ6/SEG37................................................................. 29
RJ7/SEG36................................................................. 29
VDD ............................................................................. 20
VDD ............................................................................. 29
VDDCORE/VCAP...................................................... 20, 29
VSS ............................................................................. 20
VSS ............................................................................. 29
N
NEGF ................................................................................367
NOP ..................................................................................367
Notable Differences Between
PIC18F87J90 and PIC18F85J90 Families................433
O
Oscillator Configuration.......................................................35
EC ...............................................................................35
ECPLL.........................................................................35
HS...............................................................................35
HSPLL.........................................................................35
Internal Oscillator Block ..............................................41
INTIO1 ........................................................................35
INTIO2 ........................................................................35
INTPLL1......................................................................35
INTPLL2......................................................................35
Oscillator Selection ...........................................................325
Oscillator Start-up Timer (OST) ..........................................43
Oscillator Switching.............................................................37
Oscillator Transitions...........................................................38
Oscillator, Timer1...................................................... 143, 153
Oscillator, Timer3..............................................................151
P
Packaging .........................................................................427
Details.......................................................................428
Marking .....................................................................427
Pin Functions
AVDD ...........................................................................20
AVDD ...........................................................................29
AVSS ...........................................................................29
AVSS ...........................................................................20
ENVREG............................................................... 20, 29
LCDBIAS3............................................................. 18, 25
MCLR....................................................................14, 21
OSC1/CLKI/RA7 ................................................... 14, 21
OSC2/CLKO/RA6 ................................................. 14, 21
RA0/AN0 ............................................................... 14, 21
RA1/AN1/SEG18 .................................................. 14, 21
RA2/AN2/VREF-..................................................... 14, 21
RA3/AN3/VREF+.................................................... 14, 21
RA4/T0CKI/SEG14 ...............................................14, 21
RA5/AN4/SEG15 .................................................. 14, 21
DS39933D-page 440
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
Pinout I/O Descriptions
Exiting Idle and Sleep Modes..................................... 51
By Interrupt......................................................... 51
By Reset............................................................. 51
By WDT Time-out............................................... 51
Without an Oscillator Start-up Delay .................. 51
Idle Modes.................................................................. 49
PRI_IDLE ........................................................... 50
RC_IDLE ............................................................ 51
SEC_IDLE.......................................................... 50
Multiple Sleep Commands.......................................... 46
Run Modes ................................................................. 46
PRI_RUN............................................................ 46
RC_RUN............................................................. 48
SEC_RUN .......................................................... 46
Selecting..................................................................... 45
Sleep Mode ................................................................ 49
OSC1 and OSC2 Pin States............................... 43
Summary (table)......................................................... 45
Power-on Reset (POR)....................................................... 55
Power-up Delays ................................................................ 43
Power-up Timer (PWRT) .............................................. 43, 56
Time-out Sequence .................................................... 56
Prescaler, Capture............................................................ 176
Prescaler, Timer0 ............................................................. 141
Prescaler, Timer2 ............................................................. 180
PRI_IDLE Mode.................................................................. 50
PRI_RUN Mode.................................................................. 46
Program Counter................................................................ 67
PCL, PCH and PCU Registers ................................... 67
PCLATH and PCLATU Registers............................... 67
Program Memory
Extended Instruction Set ............................................ 84
Flash Configuration Words......................................... 66
Hard Memory Vectors................................................. 66
Instructions ................................................................. 71
Two-Word........................................................... 71
Interrupt Vector........................................................... 66
Look-up Tables........................................................... 69
Memory Maps............................................................. 65
Hard Vectors and Configuration Words.............. 66
Reset Vector............................................................... 66
Program Verification and Code Protection ....................... 337
Programming, Device Instructions.................................... 339
Pulse-Width Modulation. See PWM (CCP Module).
PUSH................................................................................ 368
PUSH and POP Instructions............................................... 68
PUSHL.............................................................................. 384
PWM (CCP Module)
PIC18F6XJ90.............................................................. 14
PIC18F8XJ90.............................................................. 21
PLL...................................................................................... 40
HSPLL and ECPLL Oscillator Modes ......................... 40
Use with INTOSC........................................................ 40
POP .................................................................................. 368
POR. See Power-on Reset.
PORTA
Associated Registers ................................................ 119
LATA Register........................................................... 118
PORTA Register ....................................................... 118
TRISA Register......................................................... 118
PORTB
Associated Registers ................................................ 122
LATB Register........................................................... 120
PORTB Register ....................................................... 120
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit).......................................................... 120
TRISB Register......................................................... 120
PORTC
Associated Registers ................................................ 125
LATC Register .......................................................... 123
PORTC Register....................................................... 123
RC3/SCK/SCL/SEG17 Pin........................................ 227
TRISC Register......................................................... 123
PORTD
Associated Registers ................................................ 127
LATD Register .......................................................... 126
PORTD Register....................................................... 126
TRISD Register......................................................... 126
PORTE
Associated Registers ................................................ 129
LATE Register........................................................... 128
PORTE Register ....................................................... 128
TRISE Register......................................................... 128
PORTF
Associated Registers ................................................ 132
LATF Register........................................................... 130
PORTF Register ....................................................... 130
TRISF Register ......................................................... 130
PORTG
Associated Registers ................................................ 134
LATG Register .......................................................... 133
PORTG Register....................................................... 133
TRISG Register......................................................... 133
PORTH
Associated Registers ................................................ 136
LATH Register .......................................................... 135
PORTH Register....................................................... 135
TRISH Register......................................................... 135
PORTJ
Associated Registers ................................................ 138
LATJ Register ........................................................... 137
PORTJ Register........................................................ 137
TRISJ Register.......................................................... 137
Power-Managed Modes...................................................... 45
and SPI Operation .................................................... 219
Clock Sources............................................................. 45
Clock Transitions and Status Indicators...................... 46
Entering....................................................................... 45
Associated Registers................................................ 181
Duty Cycle ................................................................ 180
Example Frequencies/Resolutions........................... 180
Period ....................................................................... 179
Setup for Operation .................................................. 181
TMR2 to PR2 Match................................................. 179
Q
Q Clock............................................................................. 180
2010 Microchip Technology Inc.
DS39933D-page 441
PIC18F87J90 FAMILY
PIR2 (Peripheral Interrupt Request (Flag) 2)............ 107
PIR3 (Peripheral Interrupt Request (Flag) 3)............ 108
RCON (Reset Control)........................................ 54, 115
RCSTA1 (EUSART Receive Status
and Control)...................................................... 257
RCSTA2 (AUSART Receive Status
R
RAM. See Data Memory.
RC_IDLE Mode...................................................................51
RC_RUN Mode ...................................................................48
RCALL...............................................................................369
RCON Register
Bit Status During Initialization .....................................58
Reader Response .............................................................446
Real-Time Clock and Calendar
Operation ..................................................................165
Registers...................................................................156
Real-Time Clock and Calendar (RTCC)............................155
Register File........................................................................74
Register File Summary.................................................. 76–80
Registers
and Control)...................................................... 277
Reserved .................................................................. 160
RTCCAL (RTCC Calibration).................................... 158
RTCCFG (RTCC Configuration)............................... 157
SECOND (Second Value)......................................... 162
2
SSPCON1 (MSSP Control 1, I C Mode) .................. 222
SSPCON1 (MSSP Control 1, SPI Mode).................. 213
2
SSPCON2 (MSSP Control 2, I C Master Mode) ...... 223
2
SSPCON2 (MSSP Control 2, I C Slave Mode) ........ 224
2
SSPSTAT (MSSP Status, I C Mode) ....................... 221
ADCON0 (A/D Control 0)..........................................289
ADCON1 (A/D Control 1)..........................................290
ADCON2 (A/D Control 2)..........................................291
ALRMCFG (Alarm Configuration) .............................159
ALRMDAY (Alarm Day Value) ..................................163
ALRMHR (Alarm Hours Value) .................................164
ALRMMIN (Alarm Minutes Value).............................164
ALRMMNTH (Alarm Month Value)............................163
ALRMRPT (Alarm Calibration)..................................160
ALRMSEC (Alarm Seconds Value)...........................164
ALRMWD (Alarm Weekday Value)...........................163
BAUDCON1 (Baud Rate Control) 1 ..........................258
CCPxCON (CCPx Control, CCP1 and CCP2) ..........173
CMCON (Comparator Control) .................................299
CONFIG1H (Configuration 1 High) ...........................327
CONFIG1L (Configuration 1 Low).............................327
CONFIG2H (Configuration 2 High) ...........................329
CONFIG2L (Configuration 2 Low).............................328
CONFIG3H (Configuration 3 High) ...........................330
CONFIG3L (Configuration 3 Low).............................329
CTMUCONH (CTMU Control High) ..........................321
CTMUCONL (CTMU Control Low)............................322
CTMUICON (CTMU Current Control) .......................323
CVRCON (Comparator Voltage
Reference Control)............................................305
DAY (Day Value).......................................................161
DEVID1 (Device ID 1)...............................................330
DEVID2 (Device ID 2)...............................................330
EECON1 (EEPROM Control 1)...................................91
HOUR (Hour Value)..................................................162
INTCON (Interrupt Control).......................................103
INTCON2 (Interrupt Control 2)..................................104
INTCON3 (Interrupt Control 3)..................................105
IPR1 (Peripheral Interrupt Priority 1).........................112
IPR2 (Peripheral Interrupt Priority 2).........................113
IPR3 (Peripheral Interrupt Priority 3).........................114
LCDCON (LCD Control)............................................184
LCDDATAx (LCD Data) ............................................187
LCDPS (LCD Phase) ................................................185
LCDREG (LCD Voltage Regulator Control)..............189
LCDSEx (LCD Segment Enable) ..............................186
MINUTE (Minute Value)............................................162
MONTH (Month Value) .............................................161
OSCCON (Oscillator Control) .....................................36
OSCTUNE (Oscillator Tuning)....................................37
PADCFG1 (Pad Configuration).................................158
PIE1 (Peripheral Interrupt Enable 1).........................109
PIE2 (Peripheral Interrupt Enable 2).........................110
PIE3 (Peripheral Interrupt Enable 3).........................111
PIR1 (Peripheral Interrupt Request (Flag) 1)............106
SSPSTAT (MSSP Status, SPI Mode)....................... 212
STATUS ..................................................................... 81
STKPTR (Stack Pointer)............................................. 68
T0CON (Timer0 Control) .......................................... 139
T1CON (Timer1 Control) .......................................... 143
T2CON (Timer2 Control) .......................................... 149
T3CON (Timer3 Control) .......................................... 151
TXSTA1 (EUSART Transmit Status
and Control)...................................................... 256
TXSTA2 (AUSART Transmit Status
and Control)...................................................... 276
WDTCON (Watchdog Timer Control) ....................... 332
WEEKDAY (Weekday Value) ................................... 161
YEAR (Year Value)................................................... 160
RESET.............................................................................. 369
Reset .................................................................................. 53
Brown-out Reset (BOR).............................................. 53
Configuration Mismatch (CM) Reset........................... 53
MCLR Reset, During Power-Managed Modes ........... 53
MCLR Reset, Normal Operation................................. 53
Power-on Reset (POR)............................................... 53
RESET Instruction ...................................................... 53
Stack Full Reset.......................................................... 53
Stack Underflow Reset ............................................... 53
Watchdog Timer (WDT) Reset ................................... 53
Resets............................................................................... 325
Brown-out Reset (BOR)............................................ 325
Oscillator Start-up Timer (OST)................................ 325
Power-on Reset (POR)............................................. 325
Power-up Timer (PWRT) .......................................... 325
RETFIE............................................................................. 370
RETLW ............................................................................. 370
RETURN........................................................................... 371
Return Address Stack......................................................... 67
Return Stack Pointer (STKPTR)......................................... 68
Revision History................................................................ 433
RLCF ................................................................................ 371
RLNCF.............................................................................. 372
RRCF................................................................................ 372
RRNCF ............................................................................. 373
RTCC
Alarm ........................................................................ 168
Configuring ....................................................... 168
Interrupt ............................................................ 169
Mask Settings................................................... 169
Alarm Value Registers (ALRMVAL).......................... 163
Control Registers...................................................... 157
DS39933D-page 442
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
Operation
Calibration......................................................... 168
T
Table Pointer Operations (table)......................................... 92
Table Reads/Table Writes.................................................. 69
TBLRD.............................................................................. 377
TBLWT ............................................................................. 378
Timer0 .............................................................................. 139
Associated Registers................................................ 141
Clock Source Select (T0CS Bit) ............................... 140
Operation.................................................................. 140
Overflow Interrupt..................................................... 141
Prescaler .................................................................. 141
Switching Assignment ...................................... 141
Prescaler Assignment (PSA Bit)............................... 141
Prescaler Select (T0PS2:T0PS0 Bits)...................... 141
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode............................. 140
Source Edge Select (T0SE Bit) ................................ 140
Timer1 .............................................................................. 143
16-Bit Read/Write Mode ........................................... 145
Associated Registers................................................ 147
Interrupt .................................................................... 146
Operation.................................................................. 144
Oscillator........................................................... 143, 145
Layout Considerations...................................... 146
Oscillator as Secondary Clock.................................... 37
Overflow Interrupt..................................................... 143
Resetting, Using the CCP Special
Event Trigger.................................................... 146
TMR1H Register....................................................... 143
TMR1L Register ....................................................... 143
Use as a Clock Source............................................. 145
Use as a Real-Time Clock........................................ 146
Timer2 .............................................................................. 149
Associated Registers................................................ 150
Interrupt .................................................................... 150
Operation.................................................................. 149
Output....................................................................... 150
PR2 Register ............................................................ 179
TMR2 to PR2 Match Interrupt................................... 179
Timer3 .............................................................................. 151
16-Bit Read/Write Mode ........................................... 153
Associated Registers................................................ 153
Operation.................................................................. 152
Oscillator........................................................... 151, 153
Overflow Interrupt............................................. 151, 153
Special Event Trigger (CCP) .................................... 153
TMR3H Register....................................................... 151
TMR3L Register ....................................................... 151
Timing Diagrams
Clock Source .................................................... 166
Digit Carry Rules............................................... 166
General Functionality........................................ 167
Leap Year ......................................................... 167
Register Mapping.............................................. 167
ALRMVAL................................................. 168
RTCVAL.................................................... 167
Safety Window for Register Reads
and Writes................................................. 167
Write Lock......................................................... 167
Register Interface...................................................... 165
Register Maps........................................................... 171
Reset......................................................................... 170
Device............................................................... 170
Power-on Reset (POR)..................................... 170
Sleep Mode............................................................... 170
Value Registers (RTCVAL)....................................... 160
RTCEN Bit Write ............................................................... 165
S
SCK................................................................................... 211
SDI.................................................................................... 211
SDO .................................................................................. 211
SEC_IDLE Mode................................................................. 50
SEC_RUN Mode................................................................. 46
Serial Clock, SCK ............................................................. 211
Serial Data In (SDI)........................................................... 211
Serial Data Out (SDO) ...................................................... 211
Serial Peripheral Interface. See SPI Mode.
SETF................................................................................. 373
Slave Select (SS).............................................................. 211
SLEEP .............................................................................. 374
Software Simulator (MPLAB SIM)..................................... 391
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ............................................ 325
SPI Mode (MSSP)
Associated Registers ................................................ 219
Bus Mode Compatibility ............................................ 219
Effects of a Reset...................................................... 219
Enabling SPI I/O ....................................................... 215
Master Mode............................................................. 216
Operation .................................................................. 214
Operation in Power-Managed Modes ....................... 219
Serial Clock............................................................... 211
Serial Data In ............................................................ 211
Serial Data Out ......................................................... 211
Slave Mode............................................................... 217
Slave Select.............................................................. 211
Slave Select Synchronization ................................... 217
SPI Clock .................................................................. 216
Typical Connection ................................................... 215
SS ..................................................................................... 211
SSPOV.............................................................................. 245
SSPOV Status Flag .......................................................... 245
SSPSTAT Register
A/D Conversion ........................................................ 426
Acknowledge Sequence........................................... 248
Asynchronous Reception.................................. 267, 283
Asynchronous Transmission ............................ 265, 281
Asynchronous Transmission
(Back to Back) .......................................... 265, 281
Automatic Baud Rate Calculation............................. 263
Auto-Wake-up Bit (WUE) During
R/W Bit.............................................................. 225, 227
Stack Full/Underflow Resets............................................... 69
SUBFSR ........................................................................... 385
SUBFWB........................................................................... 374
SUBLW ............................................................................. 375
SUBULNK......................................................................... 385
SUBWF............................................................................. 375
SUBWFB........................................................................... 376
SWAPF ............................................................................. 376
Normal Operation ............................................. 268
Auto-Wake-up Bit (WUE) During Sleep.................... 268
Baud Rate Generator with Clock Arbitration............. 242
BRG Overflow Sequence ......................................... 263
BRG Reset Due to SDA Arbitration During
Start Condition.................................................. 251
Bus Collision During a Repeated Start
Condition (Case 1)............................................ 252
2010 Microchip Technology Inc.
DS39933D-page 443
PIC18F87J90 FAMILY
Bus Collision During a Repeated Start
Condition (Case 2)............................................252
Bus Collision During a Start
Time-out Sequence on Power-up (MCLR Not
Tied to VDD), Case 1 .......................................... 56
Time-out Sequence on Power-up (MCLR Not
Condition (SCL = 0) ..........................................251
Bus Collision During a Stop
Tied to VDD), Case 2 .......................................... 57
Time-out Sequence on Power-up (MCLR
Condition (Case 1)............................................253
Bus Collision During a Stop Condition (Case 2) .......253
Bus Collision During Start
Condition (SDA Only)........................................250
Bus Collision for Transmit and Acknowledge............249
Capture/Compare/PWM............................................415
CLKO and I/O ...........................................................412
Clock Synchronization ..............................................235
Clock/Instruction Cycle ...............................................70
EUSART/AUSART Synchronous Receive
Tied to VDD, VDD Rise Tpwrt)............................. 56
Timer Pulse Generation............................................ 170
Timer0 and Timer1 External Clock ........................... 414
Transition for Entry to Idle Mode................................. 50
Transition for Entry to SEC_RUN Mode ..................... 47
Transition for Entry to Sleep Mode ............................. 49
Transition for Two-Speed Start-up
(INTRC to HSPLL)............................................ 334
Transition for Wake From Idle to Run Mode............... 50
Transition for Wake From Sleep (HSPLL) .................. 49
Transition From RC_RUN Mode to
(Master/Slave)...................................................424
EUSART/AUSART Synchronous Transmission
(Master/Slave)...................................................424
Example SPI Master Mode (CKE = 0) ......................416
Example SPI Master Mode (CKE = 1) ......................417
Example SPI Slave Mode (CKE = 0) ........................418
Example SPI Slave Mode (CKE = 1) ........................419
External Clock...........................................................410
Fail-Safe Clock Monitor.............................................336
First Start Bit Timing .................................................243
PRI_RUN Mode.................................................. 48
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL)................................... 47
Transition to RC_RUN Mode...................................... 48
Type-A in 1/2 MUX, 1/2 Bias Drive........................... 196
Type-A in 1/2 MUX, 1/3 Bias Drive........................... 198
Type-A in 1/3 MUX, 1/2 Bias Drive........................... 200
Type-A in 1/3 MUX, 1/3 Bias Drive........................... 202
Type-A in 1/4 MUX, 1/3 Bias Drive........................... 204
Type-A/Type-B in Static Drive .................................. 195
Type-B in 1/2 MUX, 1/2 Bias Drive........................... 197
Type-B in 1/2 MUX, 1/3 Bias Drive........................... 199
Type-B in 1/3 MUX, 1/2 Bias Drive........................... 201
Type-B in 1/3 MUX, 1/3 Bias Drive........................... 203
Type-B in 1/4 MUX, 1/3 Bias Drive........................... 205
Timing Diagrams and Specifications
2
I C Bus Data.............................................................421
2
I C Bus Start/Stop Bits..............................................420
2
I C Master Mode (7 or 10-Bit Transmission) ............246
2
I C Master Mode (7-Bit Reception)...........................247
2
I C Slave Mode (10-Bit Reception,
SEN = 0, ADMSK = 01001) ..............................232
I C Slave Mode (10-Bit Reception, SEN = 0) ...........231
I C Slave Mode (10-Bit Reception, SEN = 1) ...........237
I C Slave Mode (10-Bit Transmission)......................233
2
2
Capture/Compare/PWM Requirements.................... 415
CLKO and I/O Requirements.................................... 412
EUSART/AUSART Synchronous Receive
2
2
I C Slave Mode (7-Bit Reception,
SEN = 0, ADMSK = 01011) ..............................229
I C Slave Mode (7-Bit Reception, SEN = 0) .............228
I C Slave Mode (7-Bit Reception, SEN = 1) .............236
I C Slave Mode (7-Bit Transmission)........................230
I C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode).........238
I C Stop Condition Receive or Transmit Mode .........248
Requirements ................................................... 424
EUSART/AUSART Synchronous Transmission
Requirements ................................................... 424
Example SPI Mode Requirements (Master Mode,
CKE = 0)........................................................... 416
Example SPI Mode Requirements (Master Mode,
CKE = 1)........................................................... 417
Example SPI Mode Requirements (Slave Mode,
CKE = 0)........................................................... 418
Example SPI Slave Mode Requirements
2
2
2
2
2
LCD Interrupt in Quarter Duty Cycle Drive................206
LCD Sleep Entry/Exit When SLPEN = 1
or CS1:CS0 = 00...............................................207
2
MSSP I C Bus Data..................................................422
(CKE = 1).......................................................... 419
External Clock Requirements ................................... 410
2
MSSP I C Bus Start/Stop Bits ..................................422
2
PWM Output .............................................................179
Repeated Start Condition..........................................244
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ......413
Send Break Character Sequence .............................269
Slave Synchronization ..............................................217
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) .............................................57
SPI Mode (Master Mode)..........................................216
SPI Mode (Slave Mode, CKE = 0) ............................218
SPI Mode (Slave Mode, CKE = 1) ............................218
Synchronous Reception (Master Mode,
I C Bus Data Requirements (Slave Mode)............... 421
2
I C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 420
Internal RC Accuracy (INTOSC and INTRC)............ 411
2
MSSP I C Bus Data Requirements.......................... 423
2
MSSP I C Bus Start/Stop Bits Requirements........... 422
PLL Clock ................................................................. 411
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements......................................... 413
Timer0 and Timer1 External Clock
Requirements ................................................... 414
Top-of-Stack Access........................................................... 67
TSTFSZ ............................................................................ 379
Two-Speed Start-up.................................................. 325, 334
Two-Word Instructions
SREN)....................................................... 272, 286
Synchronous Transmission............................... 270, 284
Synchronous Transmission
(Through TXEN)........................................ 271, 285
Example Cases........................................................... 71
DS39933D-page 444
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
V
VDDCORE/VCAP Pin............................................................ 333
Voltage Reference Specifications..................................... 407
Voltage Regulator (On-Chip) ............................................ 333
Brown-out Reset (BOR)............................................ 334
Low-Voltage Detection (LVD) ................................... 333
Operation in Sleep Mode .......................................... 334
Power-up Requirements ........................................... 334
W
Watchdog Timer (WDT) ............................................ 325, 331
Associated Registers ................................................ 332
Control Register........................................................ 331
During Oscillator Failure ........................................... 335
Programming Considerations ................................... 331
WCOL ....................................................... 243, 244, 245, 248
WCOL Status Flag .................................... 243, 244, 245, 248
WWW Address.................................................................. 445
WWW, On-Line Support ....................................................... 8
X
XORLW............................................................................. 379
XORWF............................................................................. 380
2010 Microchip Technology Inc.
DS39933D-page 445
PIC18F87J90 FAMILY
NOTES:
DS39933D-page 446
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following informa-
tion:
Users of Microchip products can receive assistance
through several channels:
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Customers should contact their distributor, representa-
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Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
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• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
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Technical support is available through the web site
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• Business of Microchip – Product selector and
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CUSTOMER CHANGE NOTIFICATION
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Microchip’s customer notification service helps keep
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ified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change Notifi-
cation and follow the registration instructions.
2010 Microchip Technology Inc.
DS39933D-page 447
PIC18F87J90 FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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DS39933D
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PIC18F87J90 Family
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DS39933D-page 448
2010 Microchip Technology Inc.
PIC18F87J90 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
b)
PIC18F87J90-I/PT 301 = Industrial temperature,
TQFP package, QTP pattern #301.
PIC18F87J90T-I/PT = Tape and reel, Industrial
temperature, TQFP package.
Device(1,2)
PIC18F66J90, PIC18F66J90T
PIC18F67J90, PIC18F67J90T
PIC18F86J90, PIC18F86J90T
PIC18F87J90, PIC18F87J90T
Temperature Range I = -40C to +85C (Industrial)
Package
Pattern
PT =TQFP (Thin Quad Flatpack)
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Note 1:
2:
F
T
=
=
Standard Voltage Range
In tape and reel
2010 Microchip Technology Inc.
DS39933D-page 449
WORLDWIDE SALES AND SERVICE
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12/30/09
DS39933D-page 450
2010 Microchip Technology Inc.
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