PIC18F87J93T-I/PT [MICROCHIP]
64/80-Pin, High-Performance Microcontrollers with LCD Driver, 12-Bit A/D and nanoWatt Technology; 八十〇分之六十四引脚，高性能微控制器与LCD驱动器， 12位A / D和纳瓦技术
| 型号： | PIC18F87J93T-I/PT |
| 厂家： | 
MICROCHIP |
| 描述： | 64/80-Pin, High-Performance Microcontrollers with LCD Driver, 12-Bit A/D and nanoWatt Technology |
| 文件： | 总54页 (文件大小：756K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F87J93 Family
Data Sheet
64/80-Pin, High-Performance Microcontrollers
with LCD Driver, 12-Bit A/D
and nanoWatt Technology
© 2009 Microchip Technology Inc.
Preliminary
DS39948A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
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conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
Omniscient Code Generation, PICC, PICC-18, PICkit,
32
PICDEM, PICDEM.net, PICtail, PIC logo, REAL ICE, rfLAB,
Select Mode, Total Endurance, TSHARC, WiperLock and
ZENA are trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39948A-page ii
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
64/80-Pin, High-Performance Microcontrollers with
LCD Driver, 12-Bit A/D and nanoWatt Technology
LCD Driver and Keypad Interface
Features:
• Direct LCD Panel Drive Capability:
- Can drive LCD panel while in Sleep mode
• Up to 48 Segments and 192 Pixels, Software
Selectable
• Programmable LCD Timing module:
- Multiple LCD timing sources available
- Up to four commons: static, 1/2, 1/3 or
1/4 multiplex
Peripheral Highlights:
• High-Current Sink/Source 25 mA/25 mA
(PORTB and PORTC)
• Up to Four External Interrupts
• Four 8-Bit/16-Bit Timer/Counter modules
• Two Capture/Compare/PWM (CCP) modules
• Master Synchronous Serial Port (MSSP) module
with Two Modes of Operation:
- 3-Wire/4-Wire SPI (supports all four SPI modes)
- I2C™ Master and Slave mode
- Static, 1/2 or 1/3 bias configuration
• On-Chip LCD Boost Voltage Regulator for
Contrast Control
• One Addressable USART module
• One Enhanced Addressable USART module:
- LIN/J2602 support
• Charge Time Measurement Unit (CTMU) for
Capacitive Touch Sensing
- Auto-wake-up on Start bit and Break character
- Auto-Baud Detect (ABD)
• ADC for Resistive Touch Sensing
• 12-Bit, up to 12-Channel A/D Converter:
- Auto-acquisition
Low-Power Features:
• Power-Managed modes:
- Run: CPU On, Peripherals On
- Idle: CPU Off, Peripherals On
- Sleep: CPU Off, Peripherals Off
• Two-Speed Oscillator Start-up
- Conversion available during Sleep
• Two Analog Comparators
• Programmable Reference Voltage for Comparators
• Hardware Real-Time Clock and Calendar (RTCC)
with Clock, Calendar and Alarm Functions
• Charge Time Measurement Unit (CTMU):
- Capacitance measurement
Flexible Oscillator Structure:
- Time measurement with 1 ns typical resolution
• Two Crystal modes, 4-25 MHz
• Two External Clock modes, up to 48 MHz
• 4x Phase Lock Loop (PLL)
• Internal Oscillator Block with PLL:
- Eight user-selectable frequencies from
31.25 kHz to 8 MHz
• Secondary Oscillator using Timer1 at 32 kHz
• Fail-Safe Clock Monitor (FSCM):
- Allows for safe shutdown if peripheral clock fails
Note:
This document is supplemented by the
“PIC18F87J90 Family Data Sheet”
(DS39933). See Section 1.0 “Device
Overview”.
MSSP
Flash
Program
Memory Memory
(Bytes)
SRAM
Data
LCD
(Pixels)
Device
I/O
CCP
Master
SPI
2
I C™
(Bytes)
PIC18F66J93
PIC18F67J93
PIC18F86J93
PIC18F87J93
64K
128K
64K
3,923
3,923
3,923
3,923
51
51
67
67
132
132
192
192
1/3
1/3
1/3
1/3
2
2
2
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1/1
1/1
1/1
1/1
12
12
12
12
2
2
2
2
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
128K
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 1
PIC18F87J93 FAMILY
• In-Circuit Serial Programming™ (ICSP™) via
Two Pins
Special Microcontroller Features:
• 10,000 Erase/Write Cycle Flash Program
Memory, Typical
• In-Circuit Debug via Two Pins
• Operating Voltage Range: 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• Flash Retention 20 Years, Minimum
• Self-Programmable under Software Control
• Flash Program Memory has Word Write
Capability for Data EEPROM Emulators
• Selectable Open-Drain Configuration for Serial
Communication and CCP Pins for Driving Outputs
up to 5V
• Priority Levels for Interrupts
• On-Chip 2.5V Regulator
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
DS39948A-page 2
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
Pin Diagrams – PIC18F6XJ93
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51
50 49
RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9/CTED1
RB3/INT3/SEG10/CTED2
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
RE1/LCDBIAS2
1
RE0/LCDBIAS1
2
RG0/LCDBIAS0
3
RG1/TX2/CK2
4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RG2/RX2/DT2/VLCAP1
5
RG3/VLCAP2
6
MCLR
7
PIC18F66J93
PIC18F67J93
RG4/SEG26/RTCC
VSS
VSS
8
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
9
VDDCORE/VCAP
10
11
12
13
14
15
16
RF7/AN5/SS/SEG25
RF6/AN11/SEG24/C1INA
RF5/AN10/CVREF/SEG23/C1INB
RF4/AN9/SEG22/C2INA
RF3/AN8/SEG21/C2INB
RF2/AN7/C1OUT/SEG20
RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17
RC2/CCP1/SEG13
17 18 19 20 21 22 23 24 25 26 27 28
29 30 31 32
Note 1: The CCP2 pin placement depends on the CCP2MX Configuration bit setting.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 3
PIC18F87J93 FAMILY
Pin Diagrams – PIC18F8XJ93
80-Pin TQFP
80 79 78
77 76 75 74 73 72 71 70 69 68 67 66 65
64 63 62 61
RH2/SEG45
RH3/SEG44
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RJ2/SEG34
2
RJ3/SEG35
3
RE1/LCDBIAS2
RE0/LCDBIAS1
RG0/LCDBIAS0
RG1/TX2/CK2
RG2/RX2/DT2/VLCAP1
RG3/VLCAP2
RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9/CTED1
RB3/INT3/SEG10/CTED2
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
VSS
4
5
6
7
8
MCLR
9
PIC18F86J93
PIC18F87J93
RG4/SEG26/RTCC
VSS
10
11
12
13
14
15
16
17
18
19
20
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
VDDCORE/VCAP
RF7/AN5/SS/SEG25
RF6/AN11/SEG24/C1INA
RF5/AN10/CVREF/SEG23/C1INB
RF4/AN9/SEG22/C2INA
RF3/AN8/SEG21/C2INB
RF2/AN7/C1OUT/SEG20
RH7/SEG43
RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17
RC2/CCP1/SEG13
RJ7/SEG36
RJ6/SEG37
RH6/SEG42
40
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Note 1: The CCP2 pin placement depends on the CCP2MX Configuration bit setting.
DS39948A-page 4
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 27
3.0 Special Features of the CPU...................................................................................................................................................... 37
4.0 Electrical Characteristics............................................................................................................................................................ 39
5.0 Packaging Information................................................................................................................................................................ 43
Appendix A: Revision History............................................................................................................................................................... 45
Appendix B: Device Differences .......................................................................................................................................................... 45
Appendix C: Conversion Considerations ............................................................................................................................................. 46
Appendix D: Migration From Baseline to Enhanced Devices .............................................................................................................. 46
Index .................................................................................................................................................................................................... 47
The Microchip Web Site....................................................................................................................................................................... 49
Customer Change Notification Service ................................................................................................................................................ 49
Customer Support................................................................................................................................................................................ 49
Reader Response................................................................................................................................................................................ 50
Product Identification System .............................................................................................................................................................. 51
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 5
PIC18F87J93 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS39948A-page 6
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
1.2
Details on Individual Family
Members
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
Devices in the PIC18F87J93 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
• PIC18F66J93
• PIC18F86J93
• PIC18F67J93
• PIC18F87J93
The devices are differentiated from each other in the
following ways:
Note: This data sheet documents only the devices’
features and specifications that are in addition
to the features and specifications of the
PIC18F87J90 family devices. For information
on the features and specifications shared by
the PIC18F87J93 family and PIC18F87J90
family devices, see the “PIC18F87J90 Family
Data Sheet” (DS39933).
• Flash Program Memory (64 Kbytes for
PIC18FX6J93 devices and 128 Kbytes for
PIC18FX7J93).
• LCD Pixels:
- 64-pin devices – 132 pixels
(33 SEGs x 4 COMs)
- 80-pin devices – 192 pixels
(48 SEGs x 4 COMs)
The PIC18F87J93 family of devices offers the
advantages of all PIC18 microcontrollers – high compu-
tational performance, a rich feature set and economical
price – with the addition of a versatile, on-chip LCD
driver. These features make the PIC18F87J93 family a
logical choice for many high-performance applications
where price is a primary consideration.
• I/O Ports (seven bidirectional ports on
PIC18F6XJ93 devices and nine bidirectional ports
on PIC18F8XJ93 devices).
All other features for devices in this family are identical
and are summarized in Table 1-1 and Table 1-2.
The devices’ block diagrams are given in Figure 1-1
and Figure 1-2.
1.1
Special Features
The pinouts for all devices are listed in Table 1-3 and
Table 1-4.
• 12-Bit A/D Converter: The PIC18F87J93 family
implements a 12-bit A/D converter. A/D converters
in both families incorporate programmable acquisi-
tion time. This allows for a channel to be selected
and a conversion to be initiated, without waiting for
a sampling period and thus, reducing code
overhead.
• Data RAM: The PIC18F87J93 family devices have
3,923 bytes of RAM.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 7
PIC18F87J93 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F6XJ93 (64-PIN DEVICES)
Features
PIC18F66J93
PIC18F67J93
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC – 48 MHz
64K
32,768
3,923
128K
65,536
3,923
29
I/O Ports
Ports A, B, C, D, E, F, G
LCD Driver (available pixels to drive)
Timers
132 (33 SEGs x 4 COMs)
4
Comparators
2
CTMU
Yes
RTCC
Yes
Capture/Compare/PWM Modules
Serial Communications
12-Bit Analog-to-Digital Module
Resets (and Delays)
2
MSSP, Addressable USART, Enhanced USART
12 Input Channels
POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set
Packages
75 Instructions, 83 with Extended Instruction Set Enabled
64-Pin TQFP
TABLE 1-2:
DEVICE FEATURES FOR THE PIC18F8XJ93 (80-PIN DEVICES)
Features
PIC18F86J93
PIC18F87J93
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC – 48 MHz
64K
32,768
3,923
128K
65,536
3,923
29
I/O Ports
Ports A, B, C, D, E, F, G, H, J
LCD Driver (available pixels to drive)
Timers
192 (48 SEGs x 4 COMs)
4
Comparators
2
CTMU
Yes
RTCC
Yes
Capture/Compare/PWM Modules
Serial Communications
12-Bit Analog-to-Digital Module
Resets (and Delays)
2
MSSP, Addressable USART, Enhanced USART
12 Input Channels
POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set
Packages
75 Instructions, 83 with Extended Instruction Set Enabled
80-Pin TQFP
DS39948A-page 8
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
FIGURE 1-1:
PIC18F6XJ93 (64-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
inc/dec logic
21
PORTA
Data Latch
8
RA0:RA7(1,2)
8
Data Memory
(2.0, 3.9
PCLATU PCLATH
Kbytes)
Address Latch
20
PCU PCH PCL
Program Counter
12
PORTB
Data Address<12>
RB0:RB7(1)
31-Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(96 Kbytes)
12
Data Latch
PORTC
RC0:RC7(1)
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
IR
Instruction Bus <16>
PORTD
RD0:RD7(1)
8
State Machine
Control Signals
Instruction
Decode and
Control
PORTE
RE0:RE1,
RE3:RE7(1)
PRODH PRODL
8 x 8 Multiply
3
Timing
Generation
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
BITOP
8
W
INTRC
Oscillator
8
Oscillator
Start-up Timer
8
8 MHz
Oscillator
PORTF
8
Power-on
Reset
8
RF1:RF7(1)
Precision
Band Gap
Reference
ALU<8>
8
Watchdog
Timer
ENVREG
BOR and
LVD(3)
Voltage
Regulator
PORTG
RG0:RG4(1)
VDDCORE/VCAP
VDD,VSS
MCLR
ADC
12-Bit
Timer0
CCP1
Timer1
Timer2
Timer3
CTMU
RTCC
Comparators
LCD
Driver
CCP2
MSSP
AUSART
EUSART
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/Os in select oscillator modes.
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 9
PIC18F87J93 FAMILY
FIGURE 1-2:
PIC18F8XJ93 (80-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
inc/dec logic
21
PORTA
Data Latch
8
8
RA0:RA7(1,2)
Data Memory
(2.0, 3.9
PCLATU PCLATH
Kbytes)
Address Latch
20
PORTB
PCU PCH PCL
Program Counter
RB0:RB7(1)
12
Data Address<12>
31-Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
PORTC
Access
Bank
Program Memory
(96 Kbytes)
RC0:RC7(1)
12
Data Latch
inc/dec
logic
8
PORTD
Table Latch
RD0:RD7(1)
Address
Decode
ROM Latch
IR
Instruction Bus <16>
PORTE
RE0:RE1,
RE3:RE7(1)
8
State Machine
Control Signals
Instruction
Decode and
Control
PORTF
PRODH PRODL
8 x 8 Multiply
RF1:RF7(1)
3
Timing
Generation
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
BITOP
8
W
PORTG
INTRC
Oscillator
8
Oscillator
Start-up Timer
8
RG0:RG4(1)
8 MHz
Oscillator
8
Power-on
Reset
8
Precision
Band Gap
Reference
ALU<8>
8
PORTH
Watchdog
Timer
RH0:RH7(1)
ENVREG
BOR and
LVD(3)
Voltage
Regulator
PORTJ
RJ0:RJ7(1)
VDDCORE/VCAP
VDD,VSS
MCLR
ADC
12-Bit
Timer0
CCP1
Timer1
Timer2
Timer3
CTMU
RTCC
Comparators
LCD
Driver
CCP2
MSSP
AUSART
EUSART
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/Os in select oscillator modes.
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
DS39948A-page 10
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
MCLR
7
I
ST
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
OSC1/CLKI/RA7
OSC1
39
40
Oscillator crystal or external clock input.
Oscillator crystal input.
I
I
CMOS
CMOS
CLKI
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
RA7
I/O
TTL
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
RA6
I/O
TTL
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
24
23
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
AN0
RA1/AN1/SEG18
RA1
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 1.
SEG18 output for LCD.
AN1
SEG18
RA2/AN2/VREF-
RA2
22
21
28
27
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
AN2
VREF-
RA3/AN3/VREF+
RA3
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA4/T0CKI/SEG14
RA4
I/O
I
O
ST
ST
Analog
Digital I/O.
Timer0 external clock input.
SEG14 output for LCD.
T0CKI
SEG14
RA5/AN4/SEG15
RA5
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 4.
SEG15 output for LCD.
AN4
SEG15
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 11
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/SEG30
RB0
48
47
46
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 0.
SEG30 output for LCD.
INT0
SEG30
RB1/INT1/SEG8
RB1
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 1.
SEG8 output for LCD.
INT1
SEG8
RB2/INT2/SEG9/CTED1
RB2
INT2
SEG9
CTED1
I/O
TTL
ST
Analog
ST
Digital I/O.
I
O
I
External Interrupt 2.
SEG9 output for LCD.
CTMU Edge 1 input.
RB3/INT3/SEG10/CTED2
45
RB3
INT3
SEG10
CTED2
I/O
TTL
ST
Analog
ST
Digital I/O.
I
O
I
External Interrupt 3.
SEG10 output for LCD.
CTMU Edge 2 input.
RB4/KBI0/SEG11
RB4
44
43
42
37
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
KBI0
SEG11
RB5/KBI1/SEG29
RB5
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.
KBI1
SEG29
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 12
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
30
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2/SEG32
29
RC1
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.
T1OSI
CCP2(1)
SEG32
Analog
RC2/CCP1/SEG13
RC2
33
34
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP1
SEG13
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
RC3/SCK/SCL/SEG17
RC3
SCK
SCL
SEG17
I/O
I/O
I/O
O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
SEG17 output for LCD.
Analog
RC4/SDI/SDA/SEG16
35
RC4
SDI
SDA
SEG16
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
Analog
SEG16 output for LCD.
RC5/SDO/SEG12
RC5
36
31
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
SDO
SEG12
RC6/TX1/CK1/SEG27
RC6
TX1
CK1
SEG27
I/O
O
I/O
O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.
Analog
RC7/RX1/DT1/SEG28
32
RC7
RX1
DT1
SEG28
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.
Analog
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 13
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTD is a bidirectional I/O port.
RD0/SEG0/CTPLS
RD0
58
I/O
O
O
ST
Analog
—
Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.
SEG0
CTPLS
RD1/SEG1
RD1
55
54
53
52
51
50
49
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
SEG1
RD2/SEG2
RD2
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
SEG2
RD3/SEG3
RD3
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
SEG3
RD4/SEG4
RD4
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
SEG4
RD5/SEG5
RD5
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
SEG5
RD6/SEG6
RD6
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
SEG6
RD7/SEG7
RD7
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
SEG7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 14
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTE is a bidirectional I/O port.
RE0/LCDBIAS1
RE0
2
I/O
I
ST
Analog
Digital I/O.
BIAS1 input for LCD.
LCDBIAS1
RE1/LCDBIAS2
RE1
1
I/O
I
ST
Analog
Digital I/O.
BIAS2 input for LCD.
LCDBIAS2
LCDBIAS3
64
63
I
Analog
BIAS3 input for LCD.
RE3/COM0
RE3
I/O
O
ST
Analog
Digital I/O.
COM0 output for LCD.
COM0
RE4/COM1
RE4
62
61
60
59
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
COM1
RE5/COM2
RE5
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
COM2
RE6/COM3
RE6
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
COM3
RE7/CCP2/SEG31
RE7
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP2(2)
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
SEG31
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 15
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT/SEG19
17
16
15
14
13
RF1
AN6
C2OUT
SEG19
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
SEG19 output for LCD.
Analog
RF2/AN7/C1OUT/SEG20
RF2
AN7
C1OUT
SEG20
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog Input 7.
Comparator 1 output.
SEG20 output for LCD.
Analog
RF3/AN8/SEG21/C2INB
RF3
AN8
SEG21
C2INB
I/O
ST
Digital I/O.
I
O
I
Analog
Analog
Analog
Analog Input 8.
SEG21 output for LCD.
Comparator 2 input B.
RF4/AN9/SEG22/C2INA
RF4
AN9
SEG22
C2INA
I/O
ST
Digital I/O.
I
O
I
Analog
Analog
Analog
Analog Input 9.
SEG22 output for LCD
Comparator 2 input A.
RF5/AN10/CVREF/
SEG23/C1INB
RF5
I/O
I
O
O
I
ST
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
SEG23 output for LCD.
Comparator 1 input B.
AN10
CVREF
SEG23
C1INB
Analog
Analog
Analog
Analog
RF6/AN11/SEG24/C1INA
12
11
RF6
I/O
ST
Digital I/O.
AN11
SEG24
C1INA
I
O
I
Analog
Analog
Analog
Analog Input 11.
SEG24 output for LCD
Comparator 1 input A.
RF7/AN5/SS/SEG25
RF7
AN5
SS
I/O
O
I
ST
Analog
TTL
Digital I/O.
Analog Input 5.
SPI slave select input.
SEG25 output for LCD.
SEG25
O
Analog
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 16
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTG is a bidirectional I/O port.
RG0/LCDBIAS0
RG0
3
I/O
I
ST
Analog
Digital I/O.
BIAS0 input for LCD.
LCDBIAS0
RG1/TX2/CK2
RG1
4
5
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
RG2/RX2/DT2/VLCAP1
RG2
RX2
DT2
VLCAP1
I/O
ST
ST
ST
Digital I/O.
I
I/O
I
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
LCD charge pump capacitor input.
Analog
RG3/VLCAP2
RG3
6
8
I/O
I
ST
Analog
Digital I/O.
LCD charge pump capacitor input.
VLCAP2
RG4/SEG26/RTCC
RG4
I/O
O
O
ST
Analog
—
Digital I/O.
SEG26 output for LCD.
RTCC output
SEG26
RTCC
VSS
9, 25, 41, 56
P
P
P
P
I
—
—
—
—
ST
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
Enable for on-chip voltage regulator.
VDD
26, 38, 57
AVSS
AVDD
ENVREG
20
19
18
10
VDDCORE/VCAP
VDDCORE
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
P
P
—
—
VCAP
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 17
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
MCLR
9
I
ST
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
OSC1/CLKI/RA7
OSC1
49
50
Oscillator crystal or external clock input.
Oscillator crystal input.
I
I
CMOS
CMOS
CLKI
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
RA7
I/O
TTL
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
RA6
I/O
TTL
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
30
29
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
AN0
RA1/AN1/SEG18
RA1
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 1.
SEG18 output for LCD.
AN1
SEG18
RA2/AN2/VREF-
RA2
28
27
34
33
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
AN2
VREF-
RA3/AN3/VREF+
RA3
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA4/T0CKI/SEG14
RA4
I/O
I
O
ST
ST
Analog
Digital I/O.
Timer0 external clock input.
SEG14 output for LCD.
T0CKI
SEG14
RA5/AN4/SEG15
RA5
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 4.
SEG15 output for LCD.
AN4
SEG15
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 18
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/SEG30
RB0
58
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 0.
SEG30 output for LCD.
INT0
SEG30
RB1/INT1/SEG8
RB1
57
56
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 1.
SEG8 output for LCD.
INT1
SEG8
RB2/INT2/SEG9/CTED1
RB2
INT2
SEG9
CTED1
I/O
TTL
ST
Analog
ST
Digital I/O.
I
O
I
External Interrupt 2.
SEG9 output for LCD.
CTMU Edge 1 input.
RB3/INT3/SEG10/
CTED2
55
RB3
INT3
SEG10
CTED2
I/O
TTL
ST
Analog
ST
Digital I/O.
I
O
I
External Interrupt 3.
SEG10 output for LCD.
CTMU Edge 2 input.
RB4/KBI0/SEG11
RB4
54
53
52
47
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
KBI0
SEG11
RB5/KBI1/SEG29
RB5
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.
KBI1
SEG29
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 19
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
36
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2/SEG32
RC1
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.
T1OSI
CCP2(1)
SEG32
Analog
RC2/CCP1/SEG13
RC2
43
44
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP1
SEG13
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
RC3/SCK/SCL/SEG17
RC3
SCK
SCL
SEG17
I/O
I/O
I/O
O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
SEG17 output for LCD.
Analog
RC4/SDI/SDA/SEG16
45
RC4
SDI
SDA
SEG16
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
Analog
SEG16 output for LCD.
RC5/SDO/SEG12
RC5
46
37
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
SDO
SEG12
RC6/TX1/CK1/SEG27
RC6
TX1
CK1
SEG27
I/O
O
I/O
O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.
Analog
RC7/RX1/DT1/SEG28
38
RC7
RX1
DT1
SEG28
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.
Analog
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 20
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTD is a bidirectional I/O port.
RD0/SEG0/CTPLS
RD0
72
I/O
O
O
ST
Analog
ST
Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.
SEG0
CTPLS
RD1/SEG1
RD1
69
68
67
66
65
64
63
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
SEG1
RD2/SEG2
RD2
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
SEG2
RD3/SEG3
RD3
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
SEG3
RD4/SEG4
RD4
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
SEG4
RD5/SEG5
RD5
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
SEG5
RD6/SEG6
RD6
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
SEG6
RD7/SEG7
RD7
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
SEG7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 21
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTE is a bidirectional I/O port.
RE0/LCDBIAS1
RE0
4
3
I/O
I
ST
Analog
Digital I/O.
BIAS1 input for LCD.
LCDBIAS1
RE1/LCDBIAS2
RE1
I/O
I
ST
Analog
Digital I/O.
BIAS2 input for LCD.
LCDBIAS2
LCDBIAS3
78
77
I
Analog
BIAS3 input for LCD.
RE3/COM0
RE3
I/O
O
ST
Analog
Digital I/O.
COM0 output for LCD.
COM0
RE4/COM1
RE4
76
75
74
73
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
COM1
RE5/COM2
RE5
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
COM2
RE6/COM3
RE6
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
COM3
RE7/CCP2/SEG31
RE7
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP2(2)
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
SEG31
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 22
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT/SEG19
23
18
17
16
15
RF1
AN6
C2OUT
SEG19
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
SEG19 output for LCD.
Analog
RF2/AN7/C1OUT/SEG20
RF2
AN7
C1OUT
SEG20
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog Input 7.
Comparator 1 output.
SEG20 output for LCD.
Analog
RF3/AN8/SEG21/C2INB
RF3
AN8
SEG21
C2INB
I/O
ST
Digital I/O.
I
O
I
Analog
Analog
Analog
Analog Input 8.
SEG21 output for LCD.
Comparator 2 input B.
RF4/AN9/SEG22/C2INA
RF4
AN9
SEG22
C2INA
I/O
ST
Digital I/O.
I
O
I
Analog
Analog
Analog
Analog Input 9.
SEG22 output for LCD.
Comparator 2 input A.
RF5/AN10/CVREF/
SEG23/C1INB
RF5
I/O
I
O
O
I
ST
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
SEG23 output for LCD.
Comparator 1 input B.
AN10
CVREF
SEG23
C1INB
Analog
Analog
Analog
Analog
RF6/AN11/SEG24/C1INA
14
13
RF6
I/O
ST
Digital I/O.
AN11
SEG24
C1INA
I
O
I
Analog
Analog
Analog
Analog Input 11.
SEG24 output for LCD.
Comparator 1 input A.
RF7/AN5/SS/SEG25
RF7
AN5
SS
I/O
O
I
ST
Analog
TTL
Digital I/O.
Analog Input 5.
SPI slave select input.
SEG25 output for LCD.
SEG25
O
Analog
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 23
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTG is a bidirectional I/O port.
RG0/LCDBIAS0
RG0
5
6
I/O
I
ST
Analog
Digital I/O.
BIAS0 input for LCD.
LCDBIAS0
RG1/TX2/CK2
RG1
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
RG2/RX2/DT2/VLCAP1
7
RG2
RX2
DT2
VLCAP1
I/O
ST
ST
ST
Digital I/O.
I
I/O
I
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
LCD charge pump capacitor input.
Analog
RG3/VLCAP2
RG3
8
I/O
I
ST
Analog
Digital I/O.
LCD charge pump capacitor input.
VLCAP2
RG4/SEG26/RTCC
RG4
10
I/O
O
O
ST
Analog
—
Digital I/O.
SEG26 output for LCD.
RTCC output.
SEG26
RTCC
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 24
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTH is a bidirectional I/O port.
79
RH0/SEG47
RH0
I/O
O
ST
Analog
Digital I/O.
SEG47 output for LCD.
SEG47
RH1/SEG46
RH1
80
1
I/O
O
ST
Analog
Digital I/O.
SEG46 output for LCD.
SEG46
RH2/SEG45
RH2
I/O
O
ST
Analog
Digital I/O.
SEG45 output for LCD.
SEG45
RH3/SEG44
RH3
2
I/O
O
ST
Analog
Digital I/O.
SEG44 output for LCD.
SEG44
RH4/SEG40
RH4
22
21
20
19
I/O
O
ST
Analog
Digital I/O.
SEG40 output for LCD.
SEG40
RH5/SEG41
RH5
I/O
O
ST
Analog
Digital I/O.
SEG41 output for LCD.
SEG41
RH6/SEG42
RH6
I/O
O
ST
Analog
Digital I/O.
SEG42 output for LCD.
SEG42
RH7/SEG43
RH7
I/O
O
ST
Analog
Digital I/O.
SEG43 output for LCD.
SEG43
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 25
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTJ is a bidirectional I/O port.
Digital I/O.
RJ0
62
61
I/O
ST
RJ1/SEG33
RJ1
I/O
O
ST
Analog
Digital I/O.
SEG33 output for LCD.
SEG33
RJ2/SEG34
RJ2
60
59
39
40
41
42
I/O
O
ST
Analog
Digital I/O.
SEG34 output for LCD.
SEG34
RJ3/SEG35
RJ3
I/O
O
ST
Analog
Digital I/O.
SEG35 output for LCD.
SEG35
RJ4/SEG39
RJ4
I/O
O
ST
Analog
Digital I/O.
SEG39 output for LCD.
SEG39
RJ5/SEG38
RJ5
I/O
O
ST
Analog
Digital I/O
SEG38 output for LCD.
SEG38
RJ6/SEG37
RJ6
I/O
O
ST
Analog
Digital I/O.
SEG37 output for LCD.
SEG37
RJ7/SEG36
RJ7
I/O
O
ST
Analog
Digital I/O.
SEG36 output for LCD.
SEG36
VSS
11, 31, 51, 70
P
P
P
P
I
—
—
—
—
ST
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
Enable for on-chip voltage regulator.
VDD
32, 48, 71
AVSS
AVDD
ENVREG
26
25
24
12
VDDCORE/VCAP
VDDCORE
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
P
P
—
—
VCAP
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 26
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
2.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has
12 inputs for all PIC18F87J93 family devices. This
module allows conversion of an analog input signal to
a corresponding 12-bit digital number.
The module has these registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
REGISTER 2-1:
ADCON0: A/D CONTROL REGISTER 0
R/W-0
ADCAL
bit 7
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADCAL: A/D Calibration bit
1= Calibration is performed on next A/D conversion
0= Normal A/D converter operation (no calibration is performed)
bit 6
Unimplemented: Read as ‘0’
bit 5-2
CHS<3:0>: Analog Channel Select bits
0000= Channel 00 (AN0)
0001= Channel 01 (AN1)
0010= Channel 02 (AN2)
0011= Channel 03 (AN3)
0100= Channel 04 (AN4)
0101= Channel 05 (AN5)
0110= Channel 06 (AN6)
0111= Channel 07 (AN7)
1000= Channel 08 (AN8)
1001= Channel 09 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
11xx= Unused
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D converter module is enabled
0= A/D converter module is disabled
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 27
PIC18F87J93 FAMILY
REGISTER 2-2:
ADCON1: A/D CONTROL REGISTER 1
R/W-0
TRIGSEL
bit 7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
TRIGSEL: Special Trigger Select bit
1= Selects the special trigger from the CTMU
0= Selects the special trigger from the CCP2
bit 6
bit 5
Unimplemented: Read as ‘0’
VCFG1: Voltage Reference Configuration bit (VREF- source)
1= VREF- (AN2)
0= AVSS
bit 4
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1= VREF+ (AN3)
0= AVDD
bit 3-0
PCFG<3:0>: A/D Port Configuration Control bits:
PCFG<3:0> AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
DS39948A-page 28
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
REGISTER 2-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
bit 7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT<2:0>: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS<2:0>: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEPinstruction to be executed before starting a conversion.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 29
PIC18F87J93 FAMILY
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS) or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF- pins.
A/D conversion. When the A/D conversion is complete,
the result is loaded into the ADRESH:ADRESL register
pair, the GO/DONE bit (ADCON0<1>) is cleared and the
A/D Interrupt Flag bit, ADIF, is set.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
The block diagram of the A/D module is shown in
Figure 2-1.
Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of the
FIGURE 2-1:
A/D BLOCK DIAGRAM(1,2)
CHS<3:0>
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
0011
(Input Voltage)
12-Bit
A/D
Converter
AN3
0010
AN2
0001
VCFG<1:0>
AN1
0000
AN0
AVDD
VREF+
VREF-
Reference
Voltage
AVSS
Note 1: Channels AN15 through AN12 are not available on PIC18F6XJ93 devices.
2: I/O pins have diode protection to VDD and VSS.
DS39948A-page 30
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0<1>)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
The following steps should be followed to do an A/D
conversion:
OR
• Waiting for the A/D interrupt
1. Configure the A/D module:
6. Read A/D Result registers (ADRESH:ADRESL);
clear ADIF bit, if required.
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
FIGURE 2-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CPIN
VAIN
ILEAKAGE
±100 nA
CHOLD = 25 pF
VT = 0.6V
5 pF
VSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to
various junctions
VDD
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
RSS
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
1
2
3
4
Sampling Switch (kΩ)
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 31
PIC18F87J93 FAMILY
To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (1,024 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
2.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is
2.5 kΩ. After the analog input channel is selected
(changed), the channel must be sampled for at least
Equation 2-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 2 kΩ
85°C (system max.)
the minimum acquisition time before starting
conversion.
a
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 2-1:
ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 2-2:
A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
)
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 2-3:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
0.2 μs
(Temp – 25°C)(0.02 μs/°C)
(85°C – 25°C)(0.02 μs/°C)
1.2 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048) μs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs
1.05 μs
TACQ
=
0.2 μs + 1 μs + 1.2 μs
2.4 μs
DS39948A-page 32
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 2-1:
TAD vs. DEVICE OPERATING
FREQUENCIES
2.2
Selecting and Configuring
Automatic Acquisition Time
AD Clock Source (TAD)
Maximum
Device
Frequency
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Operation
ADCS<2:0>
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(2)
000
100
001
101
010
110
x11
2.86 MHz
5.71 MHz
11.43 MHz
22.86 MHz
40.0 MHz
40.0 MHz
1.00 MHz(1)
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT<2:0> bits
(ADCON2<5:3>) remain in their Reset state (‘000’) and
is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module continues
to sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisition
time is programmed, there may be no need to wait for an
acquisition time between selecting a channel and setting
the GO/DONE bit.
Note 1: The RC source has a typical TAD time of
4 μs.
2: For device frequencies above 1 MHz, the
device must be in Sleep mode for the entire
conversion or the A/D accuracy may be out
of specification.
2.4
Configuring Analog Port Pins
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
2.3
Selecting the A/D Conversion
Clock
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable.
There are seven possible options for TAD:
• 2 TOSC
• 4 TOSC
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD.
Table 2-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 33
PIC18F87J93 FAMILY
2.5
A/D Conversions
2.6
Use of the CCP2 Trigger
Figure 2-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time is selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
Figure 2-4 shows the operation of the A/D converter
after the GO/DONE bit has been set; the ACQT<2:0>
bits are set to ‘010’ and a 4 TAD acquisition time is
selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 2-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD
TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7
b4
b1
b0
b9
b8
b7
b6
b5
b3
b2
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 2-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
7
8
9
10
b1
11
b0
1
2
3
4
1
2
3
4
5
6
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
DS39948A-page 34
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
If the A/D is expected to operate while the device is in
2.7
A/D Converter Calibration
a
power-managed mode, the ACQT<2:0> and
The A/D converter in the PIC18F87J93 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (which means it is reading none of
the input channels) and store the resulting value
internally to compensate for offset. Thus, subsequent
offsets will be compensated.
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been
completed. If desired, the device may be placed into
the corresponding power-managed Idle mode during
the conversion.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits, ACQT<2:0>, are set to ‘000’ and a
conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCSx bits in the OSCCON register must have already
been cleared prior to starting the conversion.
2.8
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
TABLE 2-2:
Name
SUMMARY OF A/D REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
—
—
—
—
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
—
—
—
TMR2IF
TMR1IF
PIE1
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
ADIP
PIR3
LCDIF
LCDIE
LCDIP
CTMUIF CCP2IF
CTMUIE CCP2IE
CTMUIP CCP2IP
CCP1IF
CCP1IE
CCP1IP
RTCCIF
RTCCIE
RTCCIP
PIE3
IPR3
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCP2CON
PORTA
TRISA
A/D Result Register High Byte
A/D Result Register Low Byte
ADCAL
TRIGSEL
ADFM
—
—
—
CHS3
VCFG1
ACQT2
DC2B1
RA5
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0 GO/DONE ADON
PCFG2
ADCS2
PCFG1
ADCS1
PCFG0
ADCS0
—
—
RA6(1)
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
RA7(1)
RA4
TRISA4
RF4
RA3
TRISA3
RF3
RA2
TRISA2
RF2
RA1
TRISA1
RF1
RA0
TRISA0
—
TRISA7(1) TRISA6(1) TRISA5
PORTF
TRISF
RF7
RF6
RF5
TRISF5
TRISF4
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
2: For these Reset values, see Section 4.0 “Reset” of the “PIC18F87J90 Family Data Sheet” (DS39933).
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 35
PIC18F87J93 FAMILY
NOTES:
DS39948A-page 36
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
3.1
Device ID Registers
3.0
SPECIAL FEATURES OF THE
CPU
The Device ID registers are “read-only” registers. They
identify the device type and revision for device
programmers and can be read by firmware using table
reads.
Note 1: This section documents only the CPU
features that are different from, or in addi-
tion to, the features of the PIC18F87J90
family devices.
2: For additional details on the Configuration
bits, refer to Section 24.1 “Configuration
Bits” in the “PIC18F87J90 Family Data
Sheet” (DS39933).
TABLE 3-1:
DEVICE ID REGISTERS
Default/
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unprogrammed
(1)
Value
(2)
3FFFFEh DEVID1
3FFFFFh DEVID2
DEV2
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
(2)
DEV10
0000 10x1
Legend:
x= unknown, —= unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset
states, the configuration bytes maintain their previously programmed states.
2: See Register 3-1 and Register 3-2 for DEVID values. These registers are read-only and cannot be programmed by
the user.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 37
PIC18F87J93 FAMILY
REGISTER 3-1:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F87J93 FAMILY DEVICES
R
DEV2
bit 7
R
R
R
R
R
R
R
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 0
Legend:
R = Read-only bit
bit 7-5
DEV<2:0>: Device ID bits
111= PIC18F87J93
110= PIC18F86J93
011= PIC18F67J93
010= PIC18F66J93
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 3-2:
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F87J93 FAMILY DEVICES
R
DEV10(1)
bit 7
R
R
R
R
R
R
R
DEV9(1)
DEV8(1)
DEV7(1)
DEV6(1)
DEV5(1)
DEV4(1)
DEV3(1)
bit 0
Legend:
R = Read-only bit
bit 7-0
DEV<10:3>: Device ID bits(1)
These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
0101 0000= PIC18F87J93 family devices
Note 1: The values for DEV<10:3> may be shared with other device families. The specific device is always
identified by using the entire DEV<10:0> bit sequence.
DS39948A-page 38
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
4.0
ELECTRICAL CHARACTERISTICS
Note: Other than some basic data, this section documents only the PIC18F87J93 family devices’ specifications that
differ from those of the PIC18F87J90 family devices. For detailed information on the electrical specifications
shared by the PIC18F87J93 family and PIC18F87J90 family devices, see the “PIC18F87J90 Family Data
Sheet” (DS39933).
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ........................................... -0.3V to 6.0V
Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)...... -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 3.6V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin..............................................................................................................................250 mA
Maximum output current sunk by PORTA<7:6> and any PORTB and PORTC I/O pins.........................................25 mA
Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins ..........................................................8 mA
Maximum output current sunk by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins ............................2 mA
Maximum output current sourced by PORTA<7:6> and any PORTB and PORTC I/O pins ...................................25 mA
Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins.....................................................8 mA
Maximum output current sourced by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins .......................2 mA
Maximum current sunk by all ports combined.......................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 39
PIC18F87J93 FAMILY
FIGURE 4-1:
VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL)(1)
4.0V
3.5V
3.0V
2.5V
2.0V
3.6V
PIC18LF87J93 Family
2.35V
0
8 MHz
48 MHz
Frequency
Note 1: When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset
before VDD reaches a level at which full-speed operation is not possible.
FIGURE 4-2:
VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL)(1)
3.00V
2.75V
2.50V
2.7V
PIC18LF87J93 Family
2.35V
2.25V
2.00V
48 MHz
8 MHz
Frequency
Note 1: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCORE ≤ VDD ≤ 3.6V.
DS39948A-page 40
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 4-1:
A/D CONVERTER CHARACTERISTICS: PIC18F87J93 FAMILY (INDUSTRIAL)
Param
Sym
No.
Characteristic
Min
Typ
Max
Units
Conditions
A01
A03
A04
A06
A07
A10
A20
NR
Resolution
—
—
—
—
—
—
<±1
12
±2.0
±1.5
±5
bit
ΔVREF ≥ 3.0V
EIL
EDL
Integral Linearity Error
LSB ΔVREF ≥ 3.0V
LSB ΔVREF ≥ 3.0V
LSB ΔVREF ≥ 3.0V
LSB ΔVREF ≥ 3.0V
Differential Linearity Error
<±1
EOFF Offset Error
<±1
EGN
—
Gain Error
<±1
±3
(1)
Monotonicity
Guaranteed
—
—
V
VSS ≤ VAIN ≤ VREF
For 12-bit resolution
ΔVREF Reference Voltage Range
3
VDD – VSS
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VREFL Reference Voltage Low
VSS + 3.0V
VSS – 0.3V
VREFL
—
—
—
—
VDD + 0.3V
VDD – 3.0V
VREFH
V
V
For 12-bit resolution
For 12-bit resolution
Note 2
VAIN
ZAIN
Analog Input Voltage
V
Recommended
—
2.5
kΩ
Impedance of Analog
Voltage Source
(2)
A50
IREF
VREF Input Current
—
—
—
—
5
150
μA During VAIN acquisition.
μA During A/D conversion cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from
the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 41
PIC18F87J93 FAMILY
FIGURE 4-3:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
A/D CLK(1)
132
. . .
. . .
11
10
9
3
2
1
0
A/D DATA
NEW_DATA
TCY
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 4-2:
A/D CONVERSION REQUIREMENTS
Characteristic
Param
No.
Symbol
Min
Max
Units
Conditions
130
131
TAD
A/D Clock Period
0.8
13
12.5(1)
14
μs TOSC based, VREF ≥ 3.0V
TCNV
Conversion Time
TAD
(not including acquisition time)(2)
132
135
137
TACQ
TSWC
TDIS
Acquisition Time(3)
1.4
—
—
(Note 4)
—
μs
Switching Time from Convert → Sample
Discharge Time
0.2
μs
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
DS39948A-page 42
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
5.0
PACKAGING INFORMATION
For packaging information, see the “PIC18F87J93
Family Data Sheet” (DS39933).
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 43
PIC18F87J93 FAMILY
NOTES:
DS39948A-page 44
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Revision A (June 2009)
The differences between the devices listed in this data
sheet are shown in Table B-1.
Original data sheet for PIC18F87J93 family devices.
TABLE B-1:
PIC18F87J93 FAMILY DEVICE DIFFERENCES
Features
PIC18F66J93
PIC18F67J93
PIC18F86J93
PIC18F87J93
Program Memory (Bytes)
Program Memory (Instructions)
Interrupt Sources
64K
32768
28
128K
65536
28
64K
32768
29
128K
65536
29
I/O Ports
Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E,
F, G
F, G
F, G, H, J
F, G, H, J
Capture/Compare/PWM Modules
2
2
2
3
2
3
Enhanced
3
3
Capture/Compare/PWM Modules
Packages
64-Pin TQFP
64-Pin TQFP
80-Pin TQFP
80-Pin TQFP
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 45
PIC18F87J93 FAMILY
APPENDIX C: CONVERSION
CONSIDERATIONS
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
This section discusses how to migrate from a Baseline
device (such as the PIC16C5X) to an Enhanced MCU
device (such as the PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available
DS39948A-page 46
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
INDEX
A
E
A/D
Electrical Characteristics .................................................... 39
Equations
A/D Converter Interrupt, Configuring ..........................31
Acquisition Requirements ...........................................32
ADCAL Bit...................................................................35
ADCON0 Register.......................................................27
ADCON1 Register.......................................................27
ADCON2 Register.......................................................27
ADRESH Register................................................. 27, 30
ADRESL Register .......................................................27
Analog Port Pins, Configuring.....................................33
Associated Registers ..................................................35
Configuring the Module...............................................31
Conversion Clock (TAD) ..............................................33
Conversion Status (GO/DONE Bit).............................30
Conversions................................................................34
Converter Calibration ..................................................35
Converter Characteristics ...........................................41
Operation in Power-Managed Modes .........................35
Overview .....................................................................27
Selecting and Configuring Automatic
A/D Acquisition Time .................................................. 32
A/D Minimum Charging Time...................................... 32
Calculating the Minimum Required
Acquisition Time ................................................. 32
Errata.................................................................................... 6
F
Features Summary
Device Overview........................................................... 1
Flexible Oscillator Structure.......................................... 1
LCD Driver and Keypad Interface................................. 1
Low Power.................................................................... 1
Peripheral Highlights..................................................... 1
Special Microcontroller Attributes ................................. 2
I
Internet Address ................................................................. 49
Interrupt Sources
A/D Conversion Complete .......................................... 31
Acquisition Time..................................................33
Special Event Trigger (CCP).......................................34
Use of the CCP2 Trigger.............................................34
Absolute Maximum Ratings ................................................39
ADCAL Bit...........................................................................35
ADCON0 Register...............................................................27
GO/DONE Bit..............................................................30
ADCON1 Register...............................................................27
ADCON2 Register...............................................................27
ADRESH Register...............................................................27
ADRESL Register ......................................................... 27, 30
Analog-to-Digital Converter. See A/D.
M
Microchip Internet Web Site................................................ 49
Migration From Baseline to Enhanced Devices.................. 46
P
Packaging Information........................................................ 43
Pin Diagrams
PIC18F66J93/67J93..................................................... 3
PIC18F86J93/87J93..................................................... 4
Pin Functions
AVDD........................................................................... 17
AVDD........................................................................... 26
AVSS ........................................................................... 17
AVSS ........................................................................... 26
ENVREG .............................................................. 17, 26
LCDBIAS3 ............................................................ 15, 22
MCLR ................................................................... 11, 18
OSC1/CLKI/RA7................................................... 11, 18
OSC2/CLKO/RA6 ................................................. 11, 18
RA0/AN0............................................................... 11, 18
RA1/AN1/SEG18 .................................................. 11, 18
RA2/AN2/VREF- .................................................... 11, 18
RA3/AN3/VREF+ ................................................... 11, 18
RA4/T0CKI/SEG14............................................... 11, 18
RA5/AN4/SEG15 .................................................. 11, 18
RB0/INT0/SEG30 ................................................. 12, 19
RB1/INT1/SEG8 ................................................... 12, 19
RB2/INT2/SEG9/CTED1....................................... 12, 19
RB3/INT3/SEG10/CTED2..................................... 12, 19
RB4/KBI0/SEG11 ................................................. 12, 19
RB5/KBI1/SEG29 ................................................. 12, 19
RB6/KBI2/PGC ..................................................... 12, 19
RB7/KBI3/PGD ..................................................... 12, 19
RC0/T1OSO/T13CKI ............................................ 13, 20
B
Block Diagrams
A/D..............................................................................30
Analog Input Model .....................................................31
PIC18F66J93/67J93 .....................................................9
PIC18F86J93/87J93 ...................................................10
C
Compare (CCP Module)
Special Event Trigger..................................................34
Conversion Considerations.................................................46
Customer Change Notification Service ...............................49
Customer Notification Service.............................................49
Customer Support...............................................................49
D
Device Differences..............................................................45
Device Overview
Detailed Features..........................................................7
Features (64-Pin Devices) ............................................8
Features (80-Pin Devices) ............................................8
Special Features...........................................................7
DS39948A-page 47
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
RC1/T1OSI/CCP2/SEG32 .................................... 13, 20
RC2/CCP1/SEG13................................................ 13, 20
RC3/SCK/SCL/SEG17.......................................... 13, 20
RC4/SDI/SDA/SEG16...........................................13, 20
RC5/SDO/SEG12 ................................................. 13, 20
RC6/TX1/CK1/SEG27...........................................13, 20
RC7/RX1/DT1/SEG28 .......................................... 13, 20
RD0/SEG0/CTPLS................................................ 14, 21
RD0/SEG1 ..................................................................14
RD1/SEG1 ..................................................................21
RD2/SEG2 ............................................................ 14, 21
RD3/SEG3 ............................................................ 14, 21
RD4/SEG4 ............................................................ 14, 21
RD5/SEG5 ............................................................ 14, 21
RD6/SEG6 ............................................................ 14, 21
RD7/SEG7 ............................................................ 14, 21
RE0/LCDBIAS1..................................................... 15, 22
RE1/LCDBIAS2..................................................... 15, 22
RE3/COM0............................................................ 15, 22
RE4/COM1............................................................ 15, 22
RE5/COM2............................................................ 15, 22
RE6/COM3............................................................ 15, 22
RE7/CCP2/SEG31................................................ 15, 22
RF1/AN6/C2OUT/SEG19 ..................................... 16, 23
RF2/AN7/C1OUT/SEG20 ..................................... 16, 23
RF3/AN8/SEG21/C2INB ....................................... 16, 23
RF4/AN9/SEG22/C2INA ....................................... 16, 23
RF5/AN10/CVREF/SEG23/C1INB ......................... 16, 23
RF6/AN11/SEG24/C1INA ..................................... 16, 23
RF7/AN5/SS/SEG25.............................................16, 23
RG0/LCDBIAS0 .................................................... 17, 24
RG1/TX2/CK2....................................................... 17, 24
RG2/RX2/DT2/VLCAP1.......................................... 17, 24
RG3/VLCAP2.......................................................... 17, 24
RG4/SEG26/RTCC ...............................................17, 24
RH0/SEG47 ................................................................25
RH1/SEG46 ................................................................25
RH2/SEG45 ................................................................25
RH3/SEG44 ................................................................25
RH4/SEG40 ................................................................25
RH5/SEG41 ................................................................25
RH6/SEG42 ................................................................25
RH7/SEG43 ................................................................25
RJ0..............................................................................26
RJ1/SEG33.................................................................26
RJ2/SEG34.................................................................26
RJ3/SEG35.................................................................26
RJ4/SEG39.................................................................26
RJ5/SEG38.................................................................26
RJ6/SEG37.................................................................26
RJ7/SEG36.................................................................26
VDD .............................................................................17
VDD .............................................................................26
VDDCORE/VCAP...................................................... 17, 26
VSS..............................................................................17
VSS..............................................................................26
Pinout I/O Descriptions
PIC18F6XJ93 ............................................................. 11
PIC18F8XJ93 ............................................................. 18
Product Identification System ............................................. 51
R
Reader Response............................................................... 50
Registers
ADCON0 (A/D Control 0)............................................ 27
ADCON1 (A/D Control 1)............................................ 28
ADCON2 (A/D Control 2)............................................ 29
DEVID1 (Device ID 1)................................................. 38
DEVID2 (Device ID 2)................................................. 38
Revision History.................................................................. 45
S
Special Features of the CPU .............................................. 37
T
Timing Diagrams
A/D Conversion........................................................... 42
Timing Diagrams and Specifications
A/D Conversion Requirements ................................... 42
V
Voltage-Frequency Graphs
Regulator Disabled, Industrial..................................... 40
Regulator Enabled, Industrial ..................................... 40
W
Worldwide Sales and Service Offices................................. 52
WWW Address ................................................................... 49
WWW, On-Line Support ....................................................... 6
DS39948A-page 48
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 49
PIC18F87J93 FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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RE:
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
PIC18F87J93 Family
DS39948A
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39948A-page 50
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain purchasing information such as pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
b)
PIC18F87J93-I/PT 301 = Industrial temperature,
TQFP package, QTP pattern #301.
PIC18F87J93T-I/PT = Tape and reel, Industrial
temperature, TQFP package.
Device(1,2)
PIC18F66J93, PIC18F66J93T
PIC18F67J93, PIC18F67J93T
PIC18F86J93, PIC18F86J93T
PIC18F87J93, PIC18F87J93T
Temperature Range I = -40°C to +85°C (Industrial)
Package
Pattern
PT =TQFP (Thin Quad Flatpack)
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Note 1:
2:
F
T
=
=
Standard Voltage Range
In Tape and Reel
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 51
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
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Tel: 33-1-69-53-63-20
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Tel: 91-20-2566-1512
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Tel: 61-2-9868-6733
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Duluth, GA
Tel: 678-957-9614
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Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
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Tel: 81-45-471- 6166
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Tel: 86-10-8528-2100
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Tel: 39-0331-742611
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Fax: 82-2-558-5932 or
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Tel: 65-6334-8870
Fax: 65-6334-8850
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
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Tel: 86-755-8203-2660
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Tel: 886-3-6578-300
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Kokomo
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Tel: 765-864-8360
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Tel: 949-462-9523
Fax: 949-462-9608
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Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
03/26/09
DS39948A-page 52
Preliminary
© 2009 Microchip Technology Inc.
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