MT9042CP1_技术文档

MT9042C

Multitrunk System Synchronizer

Data Sheet

November 2005

Features

•

Meets jitter requirements for: AT&T TR62411

Ordering Information

Stratum 3, 4 and Stratum 4 Enhanced for DS1

interfaces; and for ETSI ETS 300 011, TBR 4,

TBR 12 and TBR 13 for E1 interfaces

MT9042CP

MT9042CPR 28 Pin PLCC

MT9042CP1

28 Pin PLCC

Tubes

Tape & Reel

28 Pin PLCC* Tubes

•

Provides C1.5, C3, C2, C4, C8 and C16 output

clock signals

MT9042CPR1 28 Pin PLCC* Tape & Reel

*Pb Free Matte Tin

•

Provides 8 kHz ST-BUS framing signals

-40°C to +85°C

Selectable 1.544 MHz, 2.048 MHz or 8 kHz

input reference signals

Description

•

Accepts reference inputs from two independent

sources

The MT9042C Multitrunk System Synchronizer

contains a digital phase-locked loop (DPLL), which

provides timing and synchronization signals for

multitrunk T1 and E1 primary rate transmission links.

Provides bit error free reference switching -

meets phase slope and MTIE requirements

Operates in either Normal, Holdover and

Freerun modes

The MT9042C generates ST-BUS clock and framing

signals that are phase locked to either a 2.048 MHz,

1.544 MHz, or 8 kHz input reference.

Applications

The MT9042C is compliant with AT&T TR62411

Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300 011.

It will meet the jitter tolerance, jitter transfer, intrinsic

jitter, frequency accuracy, holdover accuracy, capture

range, phase slope and MTIE requirements for these

specifications.

•

Synchronization and timing control for

multitrunk T1 and E1 systems

•

ST-BUS clock and frame pulse sources

Primary Trunk Rate Converters

TRST

VDD

VSS

Virtual

Refer-

ence

C1.5o

C3o

C2o

C4o

C8o

C16o

F0o

OSCi

TIE

Master

Clock

Corrector

Circuit

DPLL

OSCo

Output

Interface

Circuit

Selected

Refer-

ence

State

Select

PRI

Reference

Select

F8o

F16o

SEC

MUX

Input

Impairment

Monitor

TIE

Correcto

r Enable

Reference

State

Select

Feedback

RSEL

LOS1

LOS2

Frequency

Select

MUX

Automatic/Manual

Control State Machine

Guard Time

Circuit

FS1

FS2

MS1

MS2

RST

GTo

GTi

Figure 1 - Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

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Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT9042C

Data Sheet

Change Summary

Changes from November 2004 Issue to November 2005 Issue. Page, section, figure and table numbers refer to this

issue.

Page

Item

Change

4

Pin Description - Pin 28 RST

The sentence "While the RST pin is low, all

frame and clock outputs are at logic high." is

changed to "While the RST pin is low, all

frame and all clock outputs except C16o are at

logic high; C16o is at logic low."

Changes from July 2004 Issue to November 2004 Issue. Page, section, figure and table numbers refer to this issue.

Page

Item

Guard Time Calculation

Change

18

Example time increases from to 0.9 to1.45

seconds.

24

Table "DC Electrical Characteristics"

line item 7

Changed Minimum Schmitt high level input

voltage V_SIHfrom 2.3 volts to 3.4 volts.

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

27

4

5

3 2

1

28

26

25

VDD

OSCo

OSCi

F16o

F0o

RSEL

MS1

MS2

LOS1

LOS2

24

23

22

21

6

7

8

9

10

11

20

19

GTo

GTi

F8o

C1.5o

12 13 14 15 16 17 18

Figure 2 - Pin Connections

Description (see notes 1 to 5)

Pin Description

Pin #

Name

1,15

2

V_SS

Ground. 0 Volts.

TRST

TIE Circuit Reset (TTL Input). A logic low at this input resets the Time Interval Error (TIE)

correction circuit resulting in a re-alignment of input phase with output phase as shown in

Figure 19. The TRST pin should be held low for a minimum of 300 ns.

3

SEC

Secondary Reference (TTL Input). This is one of two (PRI & SEC) input reference sources

(falling edge) used for synchronization. One of three possible frequencies (8 kHz, 1.544 MHz,

or 2.048 MHz) may be used. The selection of the input reference is based upon the MS1,

MS2, LOS1, LOS2, RSEL, and GTi control inputs (Automatic or Manual).

4

5,18

6

PRI

V_DD

Primary Reference (TTL Input). See pin description for SEC.

Positive Supply Voltage. +5V_DCnominal.

OSCo Oscillator Master Clock (CMOS Output). For crystal operation, a 20 MHz crystal is

connected from this pin to OSCi, see Figure 10. For clock oscillator operation, this pin is left

unconnected, see Figure 9.

7

8

OSCi

F16o

F0o

Oscillator Master Clock (CMOS Input). For crystal operation, a 20 MHz crystal is

connected from this pin to OSCo, see Figure 10. For clock oscillator operation, this pin is

connected to a clock source, see Figure 9.

Frame Pulse ST-BUS 16.384 Mb/s (CMOS Output). This is an 8 kHz 61 ns active low

framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-

BUS operation at 16.384 Mb/s. See Figure 20.

9

Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output). This is an 8 kHz 244 ns active low

framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-

BUS operation at 2.048 Mb/s and 4.096 Mb/s. See Figure 20.

10

F8o

Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8 kHz 122 ns active high

framing pulse, which marks the beginning of an ST-BUS frame. This is used for ST-BUS

operation at 8.192 Mb/s. See Figure 20.

11

12

13

C1.5o

C3o

Clock 1.544 MHz (CMOS Output). This output is used in T1 applications.

Clock 3.088 MHz (CMOS Output). This output is used in T1 applications.

Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s.

C2o

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MT9042C

Data Sheet

Pin Description

Pin #

Name

Description (see notes 1 to 5)

14

C4o

Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s

and 4.096 Mb/s.

16

17

C8o

Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at 8.192 Mb/s.

C16o

Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation at

16.384 Mb/s.

19

GTi

Guard Time (Schmitt Input). This input is used by the MT9042B state machine in both

Manual and Automatic modes. The signal at this pin affects the state changes between

Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and

Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o.

See Tables 4 and 5.

20

21

GTo

Guard Time (CMOS Output). The LOS1 input is gated by the rising edge of F8o, buffered

and output on GTo. This pin is typically used to drive the GTi input through an RC circuit.

LOS2

Secondary Reference Loss (TTL Input). This input is normally connected to the loss of

signal (LOS) output signal of a Line Interface Unit (LIU). When high, the SEC reference signal

is lost or invalid. LOS2, along with the LOS1 and GTi inputs control the MT9042B state

machine when operating in Automatic Control. The logic level at this input is gated in by the

rising edge of F8o.

22

23

LOS1

MS2

Primary Reference Loss (TTL Input). Typically, external equipment applies a logic high to

this input when the PRI reference signal is lost or invalid. The logic level at this input is gated

in by the rising edge of F8o. See LOS2 description.

Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1, determines the

device’s mode (Automatic or Manual) and state (Normal, Holdover or Freerun) of operation.

The logic level at this input is gated in by the rising edge of F8o. See Table 3.

24

25

MS1

Mode/Control Select 1 (TTL Input). The logic level at this input is gated in by the rising

edge of F8o. See pin description for MS1.

RSEL

Reference Source Select (TTL Input). In Manual Control, a logic low selects the PRI

(primary) reference source as the input reference signal and a logic high selects the SEC

(secondary) input. In Automatic Control, this pin must be at logic low. The logic level at this

input is gated in by the rising edge of F8o. See Table 2.

26

FS2

Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects which of three

possible frequencies (8 kHz, 1.544 MHz, or 2.048 MHz) may be input to the PRI and SEC

inputs. See Table 1.

27

28

FS1

RST

Frequency Select 1 (TTL Input). See pin description for FS2.

Reset (Schmitt Input). A logic low at this input resets the MT9042C. To ensure proper

operation, the device must be reset after changes to the method of control, reference signal

frequency changes and power-up. The RST pin should be held low for a minimum of 300 ns.

While the RST pin is low, all frame and all clock outputs except C16o are at logic high; C16o is

at logic low. Following a reset, the input reference source and output clocks and frame pulses

are phase aligned as shown in Figure 19.

Notes:

1. All inputs are CMOS with either TTL compatible logic levels, CMOS compatible logic levels or Schmitt trigger compatible logic levels

as indicated in the Pin Description.

2. All outputs are CMOS with CMOS compatible logic levels.

3. See DC Electrical Characteristics for static logic threshold values.

4. See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for dynamic logic threshold values.

5. Unless otherwise stated, all unused inputs should be connected to logic high or logic low and all unused outputs should be left open

circuit.

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

Functional Description

The MT9042C is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to

interface circuits for T1 and E1 Primary Rate Digital Transmission links.

Figure 1 is a functional block diagram which is described in the following sections.

Reference Select MUX Circuit

The MT9042C accepts two simultaneous reference input signals and operates on their falling edges. Either the

primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE

Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Tables

1, 4 and 5.

Frequency Select MUX Circuit

The MT9042C operates with one of three possible input reference frequencies (8 kHz, 1.544 MHz or 2.048 MHz).

The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference

inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be

performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and

must not be used. See Table 1.

FS2

FS1

Input Frequency

0

1

0

1

0

1

Reserved

8kHz

1.544MHz

2.048MHz

Table 1 - Input Frequency Selection

Time Interval Error (TIE) Corrector Circuit

The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or

SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.

During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary

reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL will

lead to unacceptable phase changes in the output signal.

As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the

signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is

input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.

During a switch, from one reference to the other, the State Machine first changes the mode of the device from

Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an

accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between

the current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to

the Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase

position as the previous reference signal would have been if the reference switch not taken place. The State

Machine then returns the device to Normal Mode.

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

TRST

Resets Delay

Control

Circuit

Control Signal

Delay Value

Programmable

Delay Circuit

Virtual

Reference

to DPLL

PRI or SEC

from

Reference

Select Mux

Compare

Circuit

TIE Corrector

Enable

Feedback

Signal from

Frequency

Select MUX

from

State Machine

Figure 3 - TIE Corrector Circuit

The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL,

no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change

at the input of the DPLL, or at the output of the DPLL.

Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual

reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.

This phase error is a function of the difference in phase between the two input reference signals during reference

rearrangements. Each time a reference switch is made, the delay between input signal and output signal will

change. The value of this delay is the accumulation of the error measured during each reference switch.

The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TRST) pin. A

minimum reset pulse width is 300 ns. This results in a phase alignment between the input reference signal and the

output signal as shown in Figure 20. The speed of the phase alignment correction is limited to 5 ns per 125 us, and

convergence is in the direction of least phase travel.

The state diagrams of Figure 7 and 8 indicate under which state changes the TIE Corrector Circuit is activated.

Digital Phase Lock Loop (DPLL)

As shown in Figure 4, the DPLL of the MT9042C consists of a Phase Detector, Limiter, Loop Filter, Digitally

Controlled Oscillator, and a Control Circuit.

Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the

feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase

difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the

proper feedback signal to be externally selected (e.g., 8 kHz, 1.544 MHz or 2.048 MHz).

Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all

input transient conditions with a maximum output phase slope of 5 ns per 125 us. This is well within the maximum

phase slope of 7.6 ns per 125 us or 81 ns per 1.326 ms specified by AT&T TR62411.

Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all three

reference frequency selections (8 kHz, 1.544 MHz or 2.048 MHz). This filter ensures that the jitter transfer

requirements in ETS 300 011 and AT&T TR62411 are met.

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

Virtual Reference

from

TIE Corrector

DPLL Reference

Phase

Detector

Digitally

Controlled

Oscillator

to

Limiter

Loop Filter

Output Interface Circuit

State Select

from

Input Impairment Monitor

Control

Circuit

Feedback Signal

from

Frequency Select MUX

State Select

from

State Machine

Figure 4 - DPLL Block Diagram

Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input

Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.

Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop FIlter, and

based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is

dependent on the state of the MT9042C.

In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input

reference signal.

In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30 ms to 60 ms) frequency the

DCO was generating while in Normal Mode.

In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.

Output Interface Circuit

The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure

5. The Output Interface Circuit uses two Tapped Delay Lines followed by a T1 Divider Circuit and an E1 Divider

Circuit to generate the required output signals.

C1.5o

T1 Divider

C3o

12MHz

Tapped

Delay

Line

From

DPLL

C2o

C4o

C8o

C16o

F0o

F8o

Tapped

Delay

Line

E1 Divider

16MHz

F16o

Figure 5 - Output Interface Circuit Block Diagram

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MT9042C

Data Sheet

Two tapped delay lines are used to generate a 16.384 MHz signal and a 12.352 MHz signal.

The E1 Divider Circuit uses the 16.384 MHz signal to generate four clock outputs and three frame pulse outputs.

The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.

These outputs have a nominal 50% duty cycle.

The T1 Divider Circuit uses the 12.384 MHz signal to generate two clock outputs. C1.5o and C3o are generated by

dividing the internal C12 clock by four and eight respectively. These outputs have a nominal 50% duty cycle.

The frame pulse outputs (F0o, F8o, F16o) are generated directly from the C16 clock.

The T1 and E1 signals are generated from a common DPLL signal. Consequently, the clock outputs C1.5o, C3o,

C2o, C4o, C8o, C16o, F0o and F16o are locked to one another for all operating states, and are also locked to the

selected input reference in Normal Mode. See Figures 20 & 21.

All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high

capacitance (e.g., 30 pF) loads.

Input Impairment Monitor

This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover)

when the frequency of the incoming signal is outside the auto-holdover capture range (See AC Electrical

Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the

incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output

signal locked to the input signal. The holdover output signal is based on the incoming signal 30 ms minimum to

60 ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the

Holdover Mode is very accurate (e.g., ±0.05 ppm). The the Auto-Holdover circuit does not use TIE correction.

Consequently, the phase delay between the input and output after switching back to Normal Mode is preserved (is

the same as just prior to the switch to Auto-Holdover).

Automatic/Manual Control State Machine

The Automatic/Manual Control State Machine allows the MT9042C to be controlled automatically (i.e., LOS1, LOS2

and GTi signals) or controlled manually (i.e., MS1, MS2, GTi and RSEL signals). With manual control a single mode

of operation (i.e., Normal, Holdover and Freerun) is selected. Under automatic control the state of the LOS1, LOS2

and GTi signals determines the sequence of modes that the MT9042C will follow.

As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit, the

DPLL and the Guard Time Circuit. Control is based on the logic levels at the control inputs LOS1, LOS2, RSEL,

MS1, MS2 and GTi of the Guard Time Circuit (See Figure 6).

To

To TIE

Corrector

Enable

To DPLL

State

Select

Reference

Select MUX

To

RSEL

LOS1

LOS2

Automatic/Manual Control

State Machine

and From

Guard Time

Circuit

MS1

MS2

Figure 6 - Automatic/Manual Control State Machine Block Diagram

All state machine changes occur synchronously on the rising edge of F8o. See the Controls and Modes of

Operation section for full details on Automatic Control and Manual Control.

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MT9042C

Data Sheet

Guard Time Circuit

The GTi pin is used by the Automatic/Manual Control State Machine in the MT9042C under either Manual or

Automatic control. The logic level at the GTi pin performs two functions, it enables and disables the TIE

Corrector Circuit (Manual and Automatic), and it selects which mode change takes place (Automatic only). See

the Applications - Guard Time section.

For both Manual and Automatic control, when switching from Primary Holdover to Primary Normal, the TIE

Corrector Circuit is enabled when GTi=1, and disabled when GTi=0.

Under Automatic control and in Primary Normal Mode, two state changes are possible (not counting Auto-

Holdover). These are state changes to Primary Holdover or to Secondary Normal. The logic level at the GTi pin

determines which state change occurs. When GTi=0, the state change is to Primary Holdover. When GTi=1, the

state change is to Secondary Normal.

Master Clock

The MT9042C can use either a clock or crystal as the master timing source. For recommended master timing

circuits, see the Applications - Master Clock section.

Control and Modes of Operation

The MT9042C can operate either in Manual or Automatic Control. Each control method has three possible modes

of operation, Normal, Holdover and Freerun.

As shown in Table 3, Mode/Control Select pins MS2 and MS1 select the mode and method of control.

Control

RSEL

Input Reference

MANUAL

0

1

0

1

PRI

SEC

AUTO

State Machine Control

Reserved

Table 2 - Input Reference Selection

MS2 MS1

Control

Mode

0

1

0

1

0

1

MANUAL

AUTO

NORMAL

HOLDOVER

FREERUN

State Machine Control

Table 3 - Operating Modes and States

Manual Control

Manual Control should be used when either very simple MT9042C control is required, or when complex control is

required which is not accommodated by Automatic Control. For example, very simple control could include

operation in a system which only requires Normal Mode with reference switching using only a single input stimulus

(RSEL). Very simple control would require no external circuitry. Complex control could include a system which

requires state changes between Normal, Holdover and Freerun Modes based on numerous input stimuli. Complex

control would require external circuitry, typically a microcontroller.

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

Under Manual Control, one of the three modes is selected by mode/control select pins MS2 and MS1. The active

reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and Figure 7 for

details of the state change sequences.

Automatic Control

Automatic Control should be used when simple MT9042C control is required, which is more complex than the very

simple control provide by Manual Control with no external circuitry, but not as complex as Manual Control with a

microcontroller. For example, simple control could include operation in a system which can be accommodated by

the Automatic Control State Diagram shown in Figure 8.

Automatic Control is also selected by mode/control pins MS2 and MS1. However, the mode and active reference

source is selected automatically by the internal Automatic State Machine (See Figure 6). The mode and reference

changes are based on the logic levels on the LOS1, LOS2 and GTi control pins. Refer to Table 5 and Figure 8 for

details of the state change sequences.

Normal Mode

Normal Mode is typically used when a slave clock source, synchronized to the network is required.

In Normal Mode, the MT9042C provides timing (C1.5o, C2o, C3o, C4o, C8o and C16o) and frame synchronization

(F0o, F8o, F16o) signals, which are synchronized to one of two reference inputs (PRI or SEC). The input reference

signal may have a nominal frequency of 8 kHz, 1.544 MHz or 2.048 MHz.

From a reset condition, the MT9042C will take up to 25 seconds for the output signal to be phase locked to the

selected reference.

The selection of input references is control dependent as shown in state tables 4 and 5. The reference frequencies

are selected by the frequency control pins FS2 and FS1 as shown in Table 1.

Holdover Mode

Holdover Mode is typically used for short durations (e.g., 2 seconds) while network synchronization is temporarily

disrupted.

In Holdover Mode, the MT9042C provides timing and synchronization signals, which are not locked to an external

reference signal, but are based on storage techniques. The storage value is determined while the device is in

Normal Mode and locked to an external reference signal.

When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the MT9042C

output frequency is stored alternately in two memory locations every 30 ms. When the device is switched into

Holdover Mode, the value in memory from between 30 ms and 60 ms is used to set the output frequency of the

device.

The frequency accuracy of Holdover Mode is ±0.05 ppm, which translates to a worst case 35 frame (125 us) slips in

24 hours. This exceeds the AT&T TR62411 Stratum 3 requirement of ±0.37 ppm (255 frame slips per 24 hours).

Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock while in Holdover Mode, drift on

the Master Clock directly affects the Holdover Mode accuracy. Note that the absolute Master Clock (OSCi)

accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a

±32 ppm master clock may have a temperature coefficient of ±0.1 ppm per degree C. So a 10 degree change in

temperature, while the MT9042C is in Holdover Mode may result in an additional offset (over the ±0.05 ppm) in

frequency accuracy of ±1 ppm. Which is much greater than the ±0.05 ppm of the MT9042C.

The other factor affecting accuracy is large jitter on the reference input prior (30 ms to 60 ms) to the mode switch.

For instance, jitter of 7.5 UI at 700 Hz may reduce the Holdover Mode accuracy from 0.05 ppm to 0.10 ppm.

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MT9042C

Data Sheet

Freerun Mode

Freerun Mode is typically used when a master clock source is required, or immediately following system power-up

before network synchronization is achieved.

In Freerun Mode, the MT9042C provides timing and synchronization signals which are based on the master clock

frequency (OSCi) only, and are not synchronized to the reference signals (PRI and SEC).

The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32 ppm output clock

is required, the master clock must also be ±32 ppm. See Applications - Crystal and Clock Oscillator sections.

Description

State

Normal

(PRI)

Normal

(SEC)

Holdover

(PRI)

Holdover

(SEC)

Input Controls

Freerun

S0

MS2

MS1

RSEL

GTi

S1

S2

S1H

S2H

0

1

0

1

0

1

0

1

X

0

1

S1

S2

/

-

S1 MTIE

S1

S1 MTIE

X

S2 MTIE

S1H

S2H

S0

-

/

S2 MTIE

-

/

-

/

S2H

S0

-

S0

Legend:

-

No Change

Not Valid

/

MTIE

State change occurs with TIE Corrector Circuit

Refer to Manual Control State Diagram for state changes to and from Auto-Holdover State

Table 4 - Manual Control State Table

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

S0

Freerun

(10X)

S1

S1A

Auto-Holdover

Primary

S2A

Auto-Holdover

Secondary

(001)

S2

{A}

Normal

Primary

(000)

Normal

Secondary

(001)

(000)

(GTi=0)

(GTi=1)

S1H

Holdover

Primary

(010)

S2H

Holdover

Secondary

(011)

NOTES:

(XXX)

{A}

MS2 MS1 RSEL

Invalid Reference Signal

Phase Re-Alignment

Phase Continuity Maintained (without TIE Corrector Circuit)

Phase Continuity Maintained (with TIE Corrector Circuit)

Movement to Normal State from any

state requires a valid input signal

Figure 7 - Manual Control State Diagram

State

Description

Normal

(PRI)

Normal

(SEC)

Holdover

(SEC)

Input Controls

Freerun

S0

(PRI)

LOS2

LOS1

GTi

RST

S1

S2

S1H

S2H

1

X

0

1

0

1

X

0

1

0

1

X

0 to 1

-

S0

1

S1

S2

-

S1 MTIE

S1

S1 MTIE

S2 MTIE

-

S1 MTIE

S1H

S2 MTIE

S1H

-

S2 MTIE

-

S2H

Legend:

-

No Change

MTIE

State change occurs with TIE Corrector Circuit

Refer to Automatic Control State Diagram for state changes to and from Auto-Holdover State

Table 5 - Automatic Control (MS1=MS2=1, RSEL=0) State Table

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

(11X)

(11X) RST=1

(X0X)

Reset

S0

Freerun

(01X)

(X0X)

(01X)

(X0X)

(01X)

(X0X)

(01X)

{A}

S1

Normal

Primary

S1A

Auto-Holdover

Primary

S2A

Auto-Holdover

Secondary

S2

{A}

Normal

Secondary

(X0X)

(011)

(11X)

(010 or 11X)

(X0X)

(011)

(01X)

(X00)

S1H

Holdover

Primary

S2H

Holdover

Secondary

(X01)

(010 or 11X)

(11X)

NOTES:

(XXX)

{A}

LOS2 LOS1 GTi

Invalid Reference Signal

Phase Re-Alignment

Phase Continuity Maintained (without TIE Corrector Circuit)

Phase Continuity Maintained (with TIE Corrector Circuit)

Movement to Normal State from any

state requires a valid input signal

Figure 8 - Automatic Control State Diagram

MT9042C Measures of Performance

The following are some synchronizer performance indicators and their corresponding definitions.

Intrinsic Jitter

Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by

applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may

also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring

the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters depending on the

applicable standards.

Jitter Tolerance

Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the

presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied

jitter magnitude and jitter frequency depends on the applicable standards.

13

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter

at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured

with various filters depending on the applicable standards.

For the MT9042C, two internal elements determine the jitter attenuation. This includes the internal 1.9 Hz low pass

loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5 ns/125 us.

Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the

maximum output phase slope will be limited (i.e., attenuated) to 5 ns/125 us.

The MT9042C has eight outputs with three possible input frequencies for a total of 24 possible jitter transfer

functions. However, the data sheet section on AC Electrical Characteristics - Jitter Transfer specifies transfer

values for only three cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz and 2.048 MHz to 2.048 MHz. Since all

outputs are derived from the same signal, these transfer values apply to all outputs.

It should be noted that 1 UI at 1.544 MHz is 644 ns, which is not equal to 1 UI at 2.048 MHz, which is 488 ns.

Consequently, a transfer value using different input and output frequencies must be calculated in common units

(e.g., seconds) as shown in the following example.

What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is

18 dB?

–A







------



20

OutputT1 = InputT1×10

–18







--------



20

OutputT1 = 20×10

= 2.5UI(T1)

(1UIT1)

(1UIE1)

---------------------

OutputE1 = OutputT1 ×

(644ns)

(488ns)

-------------------

OutputE1 = OutputT1 ×

= 3.3UI(T1)

Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on

the three jitter transfer functions provided.

Note that the resulting jitter transfer functions for all combinations of inputs (8 kHz, 1.544 MHz, 2.048 MHz) and

outputs (8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz) for a given input signal (jitter

frequency and jitter amplitude) are the same.

Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for

large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter

signals (e.g., 75% of the specified maximum jitter tolerance).

Frequency Accuracy

Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an

external reference, but is operating in a free running mode. For the MT9042C, the Freerun accuracy is equal to the

Master Clock (OSCi) accuracy.

14

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

Holdover Accuracy

Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external

reference signal, but is operating using storage techniques. For the MT9042C, the storage value is determined

while the device is in Normal Mode and locked to an external reference signal.

The absolute Master Clock (OSCi) accuracy of the MT9042C does not affect Holdover accuracy, but the change in

OSCi accuracy while in Holdover Mode does.

Capture Range

Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to

pull into synchronization. The MT9042C capture range is equal to ±230 ppm minus the accuracy of the master

clock (OSCi). For example, a ±32 ppm master clock results in a capture range of ±198 ppm.

Lock Range

This is the input frequency range over which the synchronizer must be able to maintain synchronization. The

lock range is equal to the capture range for the MT9042C.

Phase Slope

Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect

to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is

nominally equal to the value of the final output signal or final input signal.

Time Interval Error (TIE)

TIE is the time delay between a given timing signal and an ideal timing signal.

Maximum Time Interval Error (MTIE)

MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a

particular observation period.

MTIE(S)= TIEmax(t) – TIEmin(t)

Phase Continuity

Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a

particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.

Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a

mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has

settled to a steady state.

In the case of the MT9042C, the output signal phase continuity is maintained to within ±5 ns at the instance (over

one frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or type

of mode change, may accumulate up to ±200 ns over many frames. The rate of change of the ±200 ns phase shift

is limited to a maximum phase slope of approximately 5 ns/125 us. This meets the AT&T TR62411 maximum phase

slope requirement of 7.6 ns/125 us (81 ns/1.326 ms).

Phase Lock Time

This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal

and output signal are not changing in phase with respect to each other (not including jitter).

15

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

Lock time is very difficult to determine because it is affected by many factors which include:

i) initial input to output phase difference

ii) initial input to output frequency difference

iii) synchronizer loop filter

iv) synchronizer limiter

Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.

For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock

time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9042C loop filter

and limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently,

phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical

Characteristics - Performance for maximum phase lock time.

MT9042C and Network Specifications

The MT9042C fully meets all applicable PLL requirements (intrinsic jitter, jitter tolerance, jitter transfer, frequency

accuracy, holdover accuracy, capture range, phase change slope and MTIE during reference rearrangement) for

the following specifications.

1. AT&T TR62411 (DS1) December 1990 for Stratum 3, Stratum 4 Enhanced and Stratum 4

2. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4

3. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access

4. TBR 4 November 1995

5. TBR 12 December 1993

6. TBR 13 January 1996

7. TU-T I.431 March 1993

Applications

This section contains MT9042C application specific details for clock and crystal operation, guard time usage, reset

operation, power supply decoupling, Manual Control operation and Automatic Control operation.

Master Clock

The MT9042C can use either a clock or crystal as the master timing source.

In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source

at the OSCi pin. For applications not requiring an accurate Freerun Mode, tolerance of the master timing source

may be ±100 ppm. For applications requiring an accurate Freerun Mode, such as AT&T TR62411, the tolerance of

the master timing source must Be no greater than ±32 ppm.

Another consideration in determining the accuracy of the master timing source is the desired capture range. The

sum of the accuracy of the master timing source and the capture range of the MT9042C will always equal

±230 ppm. For example, if the master timing source is ±100 ppm, then the capture range will be ±130 ppm.

Clock Oscillator - when selecting a Clock Oscillator, numerous parameters must be considered. This includes

absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.

See AC Electrical Characteristics.

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

MT9042C

+5V

OSCi

+5V

20MHz OUT

GND

0.1uF

OSCo

No Connection

Figure 9 - Clock Oscillator Circuit

For applications requiring ±32 ppm clock accuracy, the following clock oscillator module may be used.

CTS CXO-65-HG-5-C-20.0 MHz

Frequency:

20 MHz

Tolerance:

25 ppm 0C to 70C

8 ns (0.5 V 4.5 V 50 pF)

45% to 55%

Rise & Fall Time:

Duty Cycle:

The output clock should be connected directly (not AC coupled) to the OSCi input of the MT9042C, and the OSCo

output should be left open as shown in Figure 9.

Crystal Oscillator - Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a

crystal, resistor and capacitors is shown in Figure 10.

MT9042C

OSCi

20 MHz

1 MΩ

56 pF

39 pF

3-50 pF

OSCo

100 Ω

1 uH

1 uH inductor: may improve stability and is optional

Figure 10 - Crystal Oscillator Circuit

The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance.

Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance

contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances, and stray

capacitances have a major effect on the accuracy of the oscillator frequency.

The trimmer capacitor shown in Figure 10 may be used to compensate for capacitive effects. If accuracy is not a

concern, then the trimmer may be removed, the 39 pF capacitor may be increased to 56 pF, and a wider tolerance

crystal may be substituted.

17

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a

simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses.

The crystal specification is as follows.

Frequency:

20 MHz

As required

Fundamental

Parallel

32 pF

Tolerance:

Oscillation Mode:

Resonance Mode:

Load Capacitance:

Maximum Series Resistance:

Approximate Drive Level:

e.g., CTS R1027-2BB-20.0 MHZ

35 Ω

1 mW

(±20 ppm absolute, ±6 ppm 0C to 50C, 32 pF, 25 Ω)

Guard Time Adjustment

AT&T TR62411 recommends that excessive switching of the timing reference should be minimized. And that

switching between references only be performed when the primary signal is degraded (e.g., error bursts of 2.5

seconds).

Minimizing switching (from PRI to SEC) in the MT9042C can be realized by first entering Holdover Mode for a

predetermined maximum time (i.e., guard time). If the degraded signal returns to normal before the expiry of the

guard time (e.g., 2.5 seconds), then the MT9042C is returned to its Normal Mode (with no reference switch taking

place). Otherwise, the reference input may be changed from Primary to Secondary.

MT9042C

GTo

R

+

150 kΩ

C

10 uF

GTi

R_P

1 kΩ

Figure 11 - Symmetrical Guard Time Circuit

A simple way to control the guard time (using Automatic Control) is with an RC circuit as shown in Figure 11.

Resistor R_Pis for protection only and limits the current flowing into the GTi pin during power down conditions. The

guard time can be calculated as follows.

V













DD

----------------------------------------

DD

guard

= RC × ln

time

V

– V

SIHtyp

≈ RC × 0.97

example

guard

≈ 150k × 10u × 0.97= 1.45s

time

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

•

V_SIHis the logic high going threshold level for the GTi Schmitt Trigger input, see DC Electrical Characteristics

SEC

SIGNAL

STATUS

GOOD

LOS2

PRI

SIGNAL

STATUS

GOOD

BAD

T_D

GOOD

BAD

T_D

LOS1

GTo

GTi

V_SIH

MT9042C

STATE

PRI

NORMAL

PRI

HOLDOVER

PRI

NORMAL

PRI

HOLDOVER

SEC

NORMAL

PRI

NORMAL

NOTES:

1. T_Drepresents the time delay from when the reference goes

bad to when the MT9042C is provided with a LOS indication.

Figure 12 - Automatic Control, Unsymmetrical Guard Time Circuit Timing Example

In cases where fast toggling might be expected of the LOS1 input, then an unsymmetrical Guard Time Circuit is

recommended. This ensures that reference switching doesn’t occur until the full guard time value has expired. An

unsymmetrical Guard Time Circuit is shown in Figure 12.

MT9042C

GTo

+

R_C

150 kΩ

R_D

1 kΩ

C

10 uF

GTi

R_P

1 kΩ

Figure 13 - Unsymmetrical Guard Time Circuit

Figure 13 shows a typical timing example of an unsymmetrical Guard Time Circuit with the MT9042C in Automatic

Control.

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

TIE Correction (using GTi)

When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will

prevent unwanted accumulated phase change between the input and output. This is mainly applicable to Manual

Control, since Automatic Control together with the Guard Time Circuit inherently operate in this manner.

For instance, 10 Normal to Holdover to Normal mode change sequences occur, and in each case Holdover was

entered for 2s. Each mode change sequence could account for a phase change as large as 350 ns. Thus, the

accumulated phase change could be as large as 3.5 us, and, the overall MTIE could be as large as 3.5 us.

Phase

= 0.05ppm × 2s = 100ns

= 50ns + 200ns= 250ns

hold

state

= 10 × (250ns + 100ns) = 3.5us

10

•

0.05 ppm is the accuracy of Holdover Mode

50 ns is the maximum phase continuity of the MT9042C from Normal Mode to Holdover Mode

200 ns is the maximum phase continuity of the MT9042C from Holdover Mode to Normal Mode (with or without TIE

Corrector Circuit)

20

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

MT9074

To Line 1

DSTo

TTIP

DSTi

To

TX Line

XFMR

TRING

F0i

C4i

RTIP

To

RX Line

XFMR

RRING

MT9042C

F0o

E1.5o

LOS

PRI

C4o

C2o

SEC

LOS1

LOS2

+ 5 V

FS1

FS2

MS1

150 kΩ

1 kΩ

MS2

RSEL

MT9074

To Line 2

GTo

GTi

DSTo

DSTi

TTIP

TRST

RST

TRING

To

TX Line

XFMR

1 kΩ

OSCi

+

F0i

C4i

RTIP

+ 5 V

10 kΩ

10 uF

RRING

To

RX Line

XFMR

10 nF

E1.5o

LOS

CLOCK

Out

20 MHz ±32 ppm

MT8985

STo0

STi0

STo1

STi1

F0i

C4i

Figure 14 - Dual T1 Reference Sources with MT9042C in 1.544 MHz Automatic Control

When 10 Normal to Holdover to Normal mode change sequences occur without MTIE enabled, and in each case

holdover was entered for 2s, each mode change sequence could still account for a phase change as large as

350 ns. However, there would be no accumulated phase change, since the input to output phase is re-aligned after

every Holdover to Normal state change. The overall MTIE would only be 350 ns.

Reset Circuit

A simple power up reset circuit with about a 50 us reset low time is shown in Figure 15. Resistor R_Pis for protection

only and limits current into the RST pin during power down conditions. The reset low time is not critical but should

be greater than 300 ns.

21

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

MT9042C

+5V

R

10 kΩ

RST

R_P

1 kΩ

C

10 nF

Figure 15 - Power-Up Reset Circuit

To Line 1

MT9075

DSTo

DSTi

TTIP

To

TX Line

XFMR

TRING

F0i

C4i

RTIP

To

RX Line

XFMR

RRING

MT9042C

F0o

RxFP

LOS

PRI

C4o

SEC

C1.5o

LOS1

LOS2

+ 5 V

FS1

FS2

MS1

MS2

RSEL

MT9075

To Line 2

DSTo

DSTi

TTIP

GTi

TRST

RST

To

TX Line

XFMR

CLOCK

Out

20 MHz ±32 ppm

TRING

OSCi

F0i

C4i

RTIP

RRING

To

RX Line

XFMR

RxFP

LOS

External Stimulus

CONTROLLER

MT8985

STo0

STi0

STo1

STi1

F0i

C4i

Figure 16 - Dual E1 Reference Sources with MT9042C in 8 kHz Manual Control

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Zarlink Semiconductor Inc.

MT9042C

Data Sheet

Power Supply Decoupling

The MT9042C has two VDD (+5V) pins and two VSS (GND) pins. Power and decoupling capacitors should be

included as shown in Figure 17.

C1

0.1 uF

18

15

MT9042C

5

1

C2

0.1 uF

Figure 17 - Power Supply Decoupling

Dual T1 Reference Sources with MT9042C in Automatic Control

For systems requiring simple state machine control, the application circuit shown in Figure 14 using Automatic

Control may be used.

In this circuit, the MT9042C is operating Automatically, is using a Guard Time Circuit, and the LOS1 and LOS2

inputs to determine all mode changes. Since the Guard Time Circuit is set to about 1s, all line interruptions

(LOS1=1) less than 1s will cause the MT9042C to go from Primary Normal Mode to Holdover Mode and not switch

references. For line interruptions greater than 1s, the MT9042C will switch Modes from Holdover to Secondary

Normal, providing the secondary signal is valid (LOS2=0). After receiving a good primary signal (LOS1=0), the

MT9042C will switch back to Primary Normal Mode.

For complete Automatic Control state machine details, refer to Table 5 for the State Table, and Figure 8 for the State

Diagram.

Dual E1 Reference Sources with MT9042B in Manual Control

For systems requiring complex state machine control, the application circuit shown in Figure 16 using Manual

Control may be used.

In this circuit, the MT9042C is operating Manually and is using a controller for all mode changes. The controller sets

the MT9042C modes (Normal, Holdover or Freerun) by controlling the MT9042C mode/control select pins (MS2

and MS1). The input (Primary or Secondary) is selected with the reference select pin (RSEL). TIE correction from

Primary Holdover Mode to Primary Normal Mode is enabled and disabled with the guard time input pin (GTi). The

input to output phase alignment is re-aligned with the TIE circuit reset pin (TRST), and a complete device reset is

done with the RST pin.

The controller uses two stimulus inputs (LOS) directly from the MT9075 E1 interfaces, as well as an external

stimulus input. The external input may come from a device that monitors the status registers of the E1 interfaces,

and outputs a logic one in the event of an unacceptable status condition.

For complete Manual Control state machine details, refer to Table 4 for the State Table, and Figure 7 for the State

Diagram.

23

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

Absolute Maximum Ratings* - Voltages are with respect to ground (VSS) unless otherwise stated

Parameter

Symbol

Min.

Max.

Units

1

2

3

4

5

Supply voltage

V_DD

V_PIN

I_PIN

T_ST

-0.3

7.0

V

Voltage on any pin

Current on any pin

Storage temperature

V_DD+0.3

20

V

mA

°C

-55

125

PLCC package power dissipation

P_PD

900

mW

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions* - * Voltages are with respect to ground (V_SS) unless otherwise stated

Characteristics

Sym.

Min.

Max.

Units

1

2

Supply voltage

Operating temperature

V_DD

T_A

4.5

-40

5.5

85

V

°C

DC Electrical Characteristics* - * Voltages are with respect to ground (V_SS) unless otherwise stated

Characteristics

Supply current with: OSCi = 0V

OSCi = Clock

Sym.

Min.

Max.

Units

Conditions/Notes

1

2

3

4

5

6

7

I_DDS

I_DD

10

60

mA

V

Outputs unloaded

TTL high-level input voltage

TTL low-level input voltage

CMOS high-level input voltage

CMOS low-level input voltage

Schmitt high-level input voltage

V_IH

2.0

0.7V_DD

3.4

V_IL

0.8

V

V_CIH

V_CIL

V_SIH

V

OSCi

0.3V_DD

V

GTi, RST

Note the typical value is

3.1 volts at V_DD= 5.0

volts

8

9

Schmitt low-level input voltage

Schmitt hysteresis voltage

V_SIL

V_HYS

I_IL

0.8

+10

0.4V

V

GTi, RST

0.4

-10

GTi, RST

10 Input leakage current

11 High-level output voltage

12 Low-level output voltage

uµA

V

V_I=V_DDor 0 V

I_OH=10 mA

I_OL=10 mA

V_OH

V_OL

2.4V

V

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

24

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

AC Electrical Characteristics - Performance

Characteristics

Sym.

Min.

Max.

Units Conditions/Notes†

1

2

3

4

5

6

7

8

9

Freerun Mode accuracy with OSCi at:

Holdover Mode accuracy with OSCi at:

Capture range with OSCi at:

±0ppm

±32ppm

±100ppm

±0ppm

-0

+0

ppm

s

5-8

-32

+32

5-8

-100

+100

5-8

-0.05 +0.05

1,2,4,6-8,40

1-3,6-8

1-3,6-14

±32ppm

±100ppm

±0ppm

-230

-198

-130

+230

+198

+130

30

±32ppm

±100ppm

10 Phase lock time

11 Output phase continuity with:

switch

reference

200

ns

12

13

14

mode switch to Normal

mode switch to Freerun

mode switch to Holdover

200

50

ns

1-2,4-14

1-,4,6-14

1-3,6-14

1-14,27

ns

15 MTIE (maximum time interval error)

16 Output phase slope

600

45

ns

us/s

ppm

1-14,27

17 Reference input for Auto-Holdover with:

8kHz

-18k

-36k

+18k

+36k

1-3,6,9-11

1-3,7,9-11

1-3,8-11

18

19

1.544MHz

2.048MHz

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - Voltages are with respect to ground

(VSS) unless otherwise stated.

Characteristics

Threshold Voltage

Sym.

Schmitt

TTL

CMOS

Units

1

2

3

V_T

1.5

2.3

0.8

1.5

2.0

0.8

0.5V_DD

0.7V_DD

0.3V_DD

V

Rise and Fall Threshold Voltage High

Rise and Fall Threshold Voltage Low

V_HM

V_LM

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

* Timing for input and output signals is based on the worst case result of the combination of TTL and CMOS thresholds.

* See Figure 18.

25

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

Timing Reference Points

V_HM

V_T

V_LM

ALL SIGNALS

t

_IRF,t_ORF

t_IRF,t_ORF

Figure 18 - Timing Parameter Measurement Voltage Levels

AC Electrical Characteristics - Input/Output Timing

Characteristics

Sym.

Min.

Max.

Units

1

Reference input pulse width high or low

Reference input rise or fall time

8kHz reference input to F8o delay

1.544MHz reference input to F8o delay

2.048MHz reference input to F8o delay

F8o to F0o delay

t_RW

t_IRF

100

ns

2

10

6

3

t_R8D

t_R15D

t_R2D

-21

337

222

110

11

4

363

238

134

35

5

6

t_F0D

7

F16o setup to C16o falling

F16o hold from C16o rising

F8o to C1.5o delay

t_F16S

t_F16H

t_C15D

t_C3D

t_C2D

t_C4D

t_C8D

t_C16D

t_C15W

t_C3W

t_C2W

t_C4W

t_C8W

t_C16WL

t_F0WL

t_F8WH

t_F16WL

t_ORF

t_S

8

0

20

-37

2

9

-51

-13

309

149

230

111

52

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

F8o to C3o delay

F8o to C2o delay

F8o to C4o delay

2

F8o to C8o delay

2

F8o to C16o delay

2

C1.5o pulse width high or low

C3o pulse width high or low

C2o pulse width high or low

C4o pulse width high or low

C8o pulse width high or low

C16o pulse width high or low

F0o pulse width low

339

175

258

133

70

24

35

230

111

52

258

133

70

F8o pulse width high

F16o pulse width low

Output clock and frame pulse rise or fall time

Input Controls Setup Time

Input Controls Hold Time

9

100

t_H

† See "Notes" following AC Electrical Characteristics tables.

26

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

t

R8D

PRI/SEC

8kHz

t

RW

V

T

t

R15D

PRI/SEC

RW

1.544MHz

V

T

t

R2D

t

PRI/SEC

RW

2.048MHz

V

T

V

T

F8o

NOTES:

1. Input to output delay values

are valid after a TRST or RST

with no further state changes

Figure 19 - Input to Output Timing (Normal Mode)

t

F8WH

V

T

F8o

F0D

t

F0WL

F0o

t

F16WL

F16o

t

F16H

F16S

t

t_C16D

C16WL

V

T

C16o

C8o

t

C8W

t

C8D

C4D

C2D

t

C4W

t

C4o

C2o

t

C2W

t

C3W

t

C3W

C3D

V

T

C3o

t

C15W

C15D

V

T

C1.5o

Figure 20 - Output Timing 1

27

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

V

T

F8o

MS1,2

t

H

S

V

T

LOS1,2

RSEL, GTi

Figure 21 - Input Controls Setup and Hold Timing

AC Electrical Characteristics - Intrinsic Jitter Unfiltered

Characteristics

Sym.

Min.

Max.

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Intrinsic jitter at F8o (8 kHz)

0.0002

0.030

0.040

0.060

0.080

0.160

0.320

UIpp

1-14,21-24,28

1-14,21-24,29

1-14,21-24,30

1-14,21-24,31

1-14,21-24,32

1-14,21-24,33

1-14,21-24,34

Intrinsic jitter at F0o (8 kHz)

Intrinsic jitter at F16o (8 kHz)

Intrinsic jitter at C1.5o (1.544 MHz)

Intrinsic jitter at C2o (2.048 MHz)

Intrinsic jitter at C3o (3.088 MHz)

Intrinsic jitter at C4o (4.096 MHz)

Intrinsic jitter at C8o (8.192 MHz)

Intrinsic jitter at C16o (16.384 MHz)

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - C1.5o (1.544 MHz) Intrinsic Jitter Filtered

Characteristics

Sym.

Min.

Max.

Units

Conditions/Notes†

1

2

3

4

Intrinsic jitter (4 Hz to 100 kHz filter)

Intrinsic jitter (10 Hz to 40 kHz filter)

Intrinsic jitter (8 kHz to 40 kHz filter)

Intrinsic jitter (10 Hz to 8 kHz filter)

0.015

0.010

0.005

UIpp

1-14,21-24,29

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - C2o (2.048 MHz) Intrinsic Jitter Filtered

Characteristics

Sym.

Min.

Max.

Units

Conditions/Notes†

1

2

3

4

Intrinsic jitter (4 Hz to 100 kHz filter)

Intrinsic jitter (10 Hz to 40 kHz filter)

Intrinsic jitter (8 kHz to 40 kHz filter)

Intrinsic jitter (10 Hz to 8 kHz filter)

0.015

0.010

0.005

UIpp

1-14,21-24,30

† See "Notes" following AC Electrical Characteristics tables

28

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

AC Electrical Characteristics - 8 kHz Input to 8 kHz Output Jitter Transfer

Characteristics

Sym. Min. Max. Units

Conditions/Notes†

1

2

3

4

5

6

Jitter attenuation for 1 Hz@0.01 UIpp input

Jitter attenuation for 1 Hz@0.54 UIpp input

Jitter attenuation for 10 Hz@0.10 UIpp input

Jitter attenuation for 60 Hz@0.10 UIpp input

Jitter attenuation for 300 Hz@0.10 UIpp input

Jitter attenuation for 3600 Hz@0.005 UIpp input

0

6

dB

1-3,6,9-14,21-22,24,28,35

6

16

22

38

12

28

42

45

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - 1.544 MHz Input to 1.544 MHz Output Jitter Transfer

Characteristics

Sym. Min. Max. Units

Conditions/Notes†

1

2

3

4

5

6

7

Jitter attenuation for 1 Hz@20 UIpp input

Jitter attenuation for 1 Hz@104 UIpp input

Jitter attenuation for 10 Hz@20 UIpp input

Jitter attenuation for 60 Hz@20 UIpp input

Jitter attenuation for 300 Hz@20 UIpp input

Jitter attenuation for 10 kHz@0.3 UIpp input

Jitter attenuation for 100 kHz@0.3 UIpp input

0

6

dB

1-3,7,9-14,21-22,24,29,35

6

16

22

38

12

28

42

45

† See "Notes" following AC Electrical Characteristics tables.

29

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

AC Electrical Characteristics - 2.048 MHz Input to 2.048 MHz Output Jitter Transfer

Characteristics

Sym. Min. Max. Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Jitter at output for 1 Hz@3.00 UIpp input

with 40 Hz to 100 kHz filter

2.9

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

UIpp 1-3,8,9-14,21-22,24,30,35

UIpp 1-3,8,9-14,21-22,24,30,36

0.09

1.3

Jitter at output for 3 Hz@2.33 UIpp input

with 40 Hz to 100 kHz filter

0.10

0.80

0.10

0.40

0.10

0.06

0.05

0.04

0.03

0.04

0.02

Jitter at output for 5 Hz@2.07 UIpp input

with 40 Hz to 100 kHz filter

Jitter at output for 10 Hz@1.76 UIpp input

with 40 Hz to 100 kHz filter

Jitter at output for 100 Hz@1.50 UIpp input

10 with 40 Hz to 100 kHz filter

11 Jitter at output for 2400 Hz@1.50 UIpp input

12 with 40 Hz to 100 kHz filter

13 Jitter at output for 100 kHz@0.20 UIpp input

14 with 40 Hz to 100 kHz filter

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - 8 kHz Input Jitter Tolerance

Characteristics

Sym.

Min.

Max.

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

Jitter tolerance for 1 Hz input

Jitter tolerance for 5 Hz input

Jitter tolerance for 20 Hz input

Jitter tolerance for 300 Hz input

Jitter tolerance for 400 Hz input

Jitter tolerance for 700 Hz input

Jitter tolerance for 2400 Hz input

Jitter tolerance for 3600 Hz input

0.80

0.70

0.60

0.20

0.15

0.08

0.02

0.01

UIpp

1-3,6,9-14,21-22,24-26,28

† See "Notes" following AC Electrical Characteristics tables.

30

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

AC Electrical Characteristics - 1.544 MHz Input Jitter Tolerance

Characteristics

Sym.

Min. Max.

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Jitter tolerance for 1 Hz input

Jitter tolerance for 5 Hz input

Jitter tolerance for 20 Hz input

Jitter tolerance for 300 Hz input

Jitter tolerance for 400 Hz input

Jitter tolerance for 700 Hz input

Jitter tolerance for 2400 Hz input

Jitter tolerance for 10 kHz input

Jitter tolerance for 100 kHz input

150

140

130

35

25

15

4

UIpp

1-3,7,9-14,21-22,24-26,29

1

0.5

† See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - 2.048 MHz Input Jitter Tolerance

Characteristics

Sym.

Min.

Max.

Units

Conditions/Notes†

1

2

3

4

5

6

7

8

9

Jitter tolerance for 1 Hz input

Jitter tolerance for 5 Hz input

Jitter tolerance for 20 Hz input

Jitter tolerance for 300 Hz input

Jitter tolerance for 400 Hz input

Jitter tolerance for 700 Hz input

Jitter tolerance for 2400 Hz input

Jitter tolerance for 10 kHz input

Jitter tolerance for 100 kHz input

150

140

130

50

40

20

5

UIpp

1-3,8,9-14,21-22,24-26,30

1

† See "Notes" following AC Electrical Characteristics tables.

31

Zarlink Semiconductor Inc.

MT9042C

Data Sheet

AC Electrical Characteristics - OSCi 20 MHz Master Clock Input

Characteristics

Sym.

Min.

Max.

Units

Conditions/Notes†

1

2

3

4

5

6

Frequency accuracy

-0

-32

-100

40

+0

+32

+100

60

ppm

%

15,18

16,19

17,20

(20 MHz nominal)

Duty cycle

Rise time

Fall time

10

ns

10

ns

† See "Notes" following AC Electrical Characteristics tables.

† Notes:

Voltages are with respect to ground (V_SS) unless otherwise stated.

Supply voltage and operating temperature are as per Recommended Operating Conditions.

Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels

1. PRI reference input selected.

2. SEC reference input selected.

3. Normal Mode selected.

4. Holdover Mode selected.

5. Freerun Mode selected.

6. 8 kHz Frequency Mode selected.

7. 1.544 MHz Frequency Mode selected.

8. 2.048 MHz Frequency Mode selected.

9. Master clock input OSCi at 20 MHz ±0 ppm.

10. Master clock input OSCi at 20 MHz ±32 ppm.

11. Master clock input OSCi at 20 MHz ±100 ppm.

12. Selected reference input at ±0 ppm.

13. Selected reference input at ±32 ppm.

14. Selected reference input at ±100 ppm.

15. For Freerun Mode of ±0 ppm.

16. For Freerun Mode of ±32 ppm.

17. For Freerun Mode of ±100 ppm.

18. For capture range of ±230 ppm.

19. For capture range of ±198 ppm.

20. For capture range of ±130 ppm.

21. 25 pF capacitive load.

22. OSCi Master Clock jitter is less than 2 nspp., or 0.04 UIpp where1 UIpp=1/20 MHz.

23. Jitter on reference input is less than 7 nspp.

24. Applied jitter is sinusoidal.

25. Minimum applied input jitter magnitude to regain synchronization.

26. Loss of synchronization is obtained at slightly higher input jitter amplitudes.

27. Within 10ms of the state, reference or input change.

28. 1 UIpp = 125 us for 8 kHz signals.

29. 1 UIpp = 648 ns for 1.544 MHz signals.

30. 1 UIpp = 488 ns for 2.048 MHz signals.

31. 1 UIpp = 323 ns for 3.088 MHz signals.

32. 1 UIpp = 244 ns for 4.096 MHz signals.

33. 1 UIpp = 122 ns for 8.192 MHz signals.

34. 1 UIpp = 61 ns for 16.384 MHz signals.

35. No filter.

36. 40 Hz to 100 kHz bandpass filter.

37. With respect to reference input signal frequency.

38. After a RST or TRST.

39. Master clock duty cycle 40% to 60%.

40. Prior to Holdover Mode, device was in Normal Mode and phase locked.

32

Zarlink Semiconductor Inc.


型号：	MT9042CP1
厂家：	MICROCHIP
描述：	Telecom Circuit, 1-Func, PQCC28 电信电信集成电路
文件：	总34页 (文件大小：401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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