MCRF355/WF [MICROCHIP]
SPECIALTY TELECOM CIRCUIT, UUC6, 0.008 INCH, BACKGRIND DIE-6;
| 型号： | MCRF355/WF |
| 厂家： | 
MICROCHIP |
| 描述： | SPECIALTY TELECOM CIRCUIT, UUC6, 0.008 INCH, BACKGRIND DIE-6 电信 电信集成电路 |
| 文件： | 总12页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCRF355/360
13.56 MHz Passive RFID Device with Anticollision
The device needs two external antenna coils (L1 and
FEATURES
L2) to pick up the RF magnetic fields and also to send
back encoded (modulated) data to the reader. The two
antenna coils are connected in series. The first coil (L1)
is connected between Antenna Pad A and Antenna
Pad B. The second coil (L2) is connected between
Antenna Pad B and VSS. The MCRF355 requires an
external capacitor to form a resonant circuit along with
the antenna coils.
• Frequency of operation: 13.56 MHz
• Built-in anticollision algorithm for reading up to 50
tags in the same RF field
• “Cloaking” feature minimizes the detuning effects
of adjacent tags
• Manchester coding protocol
• Data modulation frequency: 70 kHz
• 154 bits of user-programmable memory
• Contact programming or factory-programmed
options
The MCRF360 has 100 pF of internal resonance
capacitor between the Antenna Pad A and VSS (across
the coils). This capacitance can be utilized to form a
tuned LC circuit along with the external antenna coils.
See Section 2.2 for external resonant circuits.
• Very low power CMOS design
• Die, wafer, PDIP or SOIC package options
• On-chip 100 pF resonance capacitor (MCRF360)
• Read-only device after programming
The device includes a modulation transistor that is
located between Antenna Pad B and VSS. This
modulation gate is used to send data to the reader. The
modulation transistor is designed to result in approxi-
mately 2Ω of resistance between Drain, which is con-
nected to Antenna Pad B, and Source, which is
connected to VSS, when it is turned-on.
APPLICATION
RF
Signal
L1
MCRF355
Interrogator
The LC circuit is tuned to the operating frequency
(13.56 MHz) of the reader when the modulation
transistor is in a turned-off condition. This condition is
called uncloaking.
Data
L2
PACKAGE TYPE
PDIP/SOIC
As the modulation transistor turns on, there will be a
shorting effect across L2 due to the 2Ω resistance
across it. This results in a change of the inductance of
the antenna coil, and, therefore, the circuit no longer
resonates at 13.56 MHz. This condition is called cloak-
ing.
VPRG
VDD
1
8
CLK
NC
2
7
6
5
Ant. A
Ant. B
VSS
3
The occurrence of the cloaking and uncloaking of the
device is controlled by the modulation signal that turns
the modulation transistor on and off, resulting in com-
munication from the device to the reader.
NC
4
DESCRIPTION
The data stream consists of 154 bits of Manchester-
encoded data. The code waveforms are shown in
Figure 2-3. The data is sent to the reader by modulating
(AM) the carrier signal (13.56 MHz). After completion of
the data transmission, the device goes into sleep mode
for 100 ms ± 40%. The device repeats the transmitting
and sleep cycles as long as it is energized.
The MCRF355 and MCRF360 are Microchip’s newest
additions to the microID™ family of RFID tagging
devices. They are uniquely designed read-only passive
Radio Frequency Identification (RFID) devices with an
advanced anticollision feature, operating at 13.56 Mhz.
The device is powered remotely by rectifying RF mag-
netic fields that are transmitted from an interrogator
(reader).
Sleep time is determined by a built-in low-current timer.
The variation of sleep time is approximately ± 20%.
The variation of sleep time between each device results
in a randomness of the time slot. Each device wakes up
and transmits its data in a different time slot with
The device has a total of six pads (see Die Layout).
Three are used to connect the external resonant circuit
elements. The additional three pads are used for
programming and testing of the device.
1999 Microchip Technology Inc.
Preliminary
DS21287B-page 1
MCRF355/360
respect to each other. Based on this scenario, the
reader is able to read many tags that are in the same
RF field.
DIE LAYOUT
Ant. Pad A
CLK
The device has a total of 154 bits of contact
reprogrammable memory. All bits are reprogrammable
by a contact programmer. A contact programmer (part
number PG103003) is available from Microchip
Technology Inc. Factory programming prior to
shipment, known as SQTP (Serialized Quick Turn
Programming), is also available. The device is available
in die form or packaged in SOIC or PDIP.
Vss
VPRG
VDD
L1
L2
Ant. Pad B
Note: Information provided herein is preliminary
L1: Antenna Coil A
L2: Antenna Coil B
and subject to change without notice.
PAD COORDINATES (MICRONS)
Passivation Openings
Lower Lower Upper
LeftX Left Y Right X Right Y
Upper
Pad
Pad
Pad Name
Center X Center Y
Pad Width
89
Pad Height
89
Ant. Pad A -610.0 489.2
Ant. Pad B -605.0 -579.8
-521.0
-516.0
-516.0
552.4
552.4
552.4
578.2
-490.8
30.8
-565.5
-560.5
-560.5
507.9
507.9
507.9
533.7
-535.3
-13.7
89
89
89
89
89
89
89
89
89
89
VSS
VDD
-605.0 -58.2
463.4 -181.4
463.4 496.8
463.4 157.6
-92.4
585.8
246.6
-136.9
541.3
202.1
CLK
VPRG
Note 1: All coordinates are referenced from the center of the die. The minimum distance between pads (edge to
edge) is 10 mil.
2: Die Size = 1.417 mm x 1.513 mm
DS21287B-page 2
Preliminary
1999 Microchip Technology Inc.
MCRF355/360
TABLE 1-1:
Name
PAD FUNCTION TABLE
Function
1.0
ELECTRICAL
CHARACTERISTICS
Storage temperature ....................................- 65°C to +150°C
Ambient temp. with power applied ................-40°C to +125°C
Maximum current into coil pads ....................................50 mA
Ant. A
Ant. B
Vss
Connected to antenna coil L1
Connected to antenna coils L1 and L2
Connected to antenna coil L2.
Device ground during test mode.
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
VDD
DC voltage supply for programming
Main clock pulse for device
CLD
VPRG
Input/Output for programming and read
test.
TABLE 1-2:
DC CHARACTERISTICS
All parameters apply across Commercial (C): Tamb = -20oC to 50oC
the specified operating
ranges, unless otherwise
noted.
Parameters
Reading voltage
Symbol
Min
Typ
Max
Units
Conditions
VDD voltage for reading
VDDR
VHYST
IDDR
2.4
—
—
TBD
7
—
—
10
V
Hysteresis voltage
Operating current
TBD
µA
—
VDD = 2.4V during reading at
25°C
Testing voltage
VDDT
—
4
—
V
Programming voltage:
High level input voltage
Low level input voltage
High voltage
—
0.7*VDDT
—
—
—
—
20
—
—
—
V
V
External DC voltage for program-
ming and testing
VIH
VIL
VHH
0.3 * VDDT
—
—
V
Current leakage during
sleep time
IDD_OFF
—
10
—
nA
Note
Modulation resistance
RM
—
2
4
Ω
DC resistance between Drain and
Source gates of the modulation
transistor (when it is turned on)
Pull-Down resistor
RPDW
CRES
5
8
—
KΩ
CLK and VPRG internal pull-down
resistor
Internal resonant capacitor
(MCRF360)
90
100
110
pF
Internal resonant capacitor
between Antenna Pad A and VSS
(at 13.56 MHz)
Resonant frequency
(MCRF360)
FR
12.93
13.56
14.30
MHz with L = 1.377 µH
Note: This parameter is not tested in production.
1999 Microchip Technology Inc.
Preliminary
DS21287B-page 3
MCRF355/360
TABLE 1-3:
AC CHARACTERISTICS
All parameters apply across
the specified operating
ranges, unless otherwise
noted.
Commercial (C): Tamb = -20oC to 50oC
Parameters
Symbol
Min
Typ
Max
Units
Conditions
Operating frequency
Fc
FM
13.5598 13.56 13.5602 MHz Carrier frequency
Modulation frequency
Coil voltage during reading
58
4
70
82
kHz Manchester
VPP_AC
—
—
VPP Peak-to-Peak AC voltage across the
coil during reading
Coil clamp voltage
Test mode clock frequency
Sleep time
VCLMP_AC
Fclk
—
32
—
VPP
Peak -to-Peak coil clamp voltage
115
100
500
140
kHz 25°C
TOFF
60
ms Off time for anticollision feature, at
25°C
Write/Erase pulse width
Clock high time
TWC
THIGH
—
—
—
—
—
—
—
2
10
—
—
—
—
—
—
ms Time to program bit, at 25°C
µS 25°C
4.4
Clock low time
TLOW
4.4
µS 25°C
Stop condition pulse width
Stop condition setup time
Setup time for high voltage
High voltage delay time
TPW:STO
TSU:STO
TSU:HH
TDL:HH
1000
200
800
800
nS 25°C
nS 25°C
nS 25°C
nS Delay time before the next clock, at
25°C
Data input setup time
Data input hold time
Output valid from clock
Data retention
TSU:DAT
THD:DAT
TAA
—
—
200
800
200
—
—
—
—
nS 25°C
nS 25°C
—
nS 25°C
—
200
Years For T < 120°C
TABLE 1-4:
ABSOLUTE MAXIMUM/MINIMUM RATINGS
Parameters
Symbol
Min
Max
Units
Conditions
Coil current
IPP_AC
PMPD
—
—
40
1
mA
W
Peak-to-Peak coil current
Maximum Power Dissipation
Assembly temperature
Storage temperature
TASM
—
300
150
°C
°C
< 10 sec
TSTORE
-65
DS21287B-page 4
Preliminary
1999 Microchip Technology Inc.
MCRF355/360
2.1.3
DATA MODULATION
2.0
FUNCTIONAL DESCRIPTION
The device contains three major sections. The first one
is the RF Front-End section, second is the Controller
Logic, and third is the Memory section. Figure 2-1
shows the block diagram of the device.
The data modulation circuit consists of a modulation
transistor (MOSFET) and a 1-turn antenna coil (L2).
The two are connected in parallel. The transistor is
designed to result in less than two ohms (RM) between
Antenna Pad B and VSS. As the transistor turns on, the
transistor shorts L2 and, therefore, the external LC cir-
cuit is detuned (cloaking).
2.1
RF Front-End Section
The RF Front-End section includes power supply,
power-on-reset, and data modulation circuits.
Cloaking and uncloaking occur by driving the transistor
on and off, respectively. Therefore, since the data is
encoded by a Manchester format, data bit ‘1’ will be
sent by uncloaking and cloaking the transistor for 7 µs,
each. Similarly, data bit ‘0’ will be sent by cloaking and
uncloaking the transistor for 7 µs, each.
2.1.1
POWER SUPPLY
The power supply circuit generates DC voltage (VDD)
by rectifying induced AC coil voltage. The power supply
circuit includes high voltage clamping diodes to prevent
excessive voltage development across the antenna
coil.
2.1.2
POWER ON RESET (POR)
This circuit generates a power-on-reset when the tag
first enters the reader field. The reset releases when
sufficient power has developed on the VDD regulator to
allow for correct operation.
FIGURE 2-1: BLOCK DIAGRAM
CONTROLLER LOGIC
RF FRONT-END
MEMORY
Address
CLK Pulse
Column and Row Decoders
Column Drivers
(High Voltage Circuit)
VDD
Power Supply
Power on Reset
Modulation
Clock Generator
Modulation Logic
POR
Data
154-Bit
Modulation
Pulse
Wake-up Signal
Set/Clear
Sleep Timer
(anticollision)
Memory Array
Read/Write Logic
Test Logic
VPRG and CLK
1999 Microchip Technology Inc.
Preliminary
DS21287B-page 5
MCRF355/360
Figure 2-2(a) shows a configuration of an external
circuit for the MCRF355. Two external antenna coils
(L1 and L2) in series and a capacitor that is connected
across the two inductors form a parallel resonant circuit
to pick up incoming RF signals and also send back
modulated signals to the reader. The first coil (L1) is
connected between Antenna Pad A and Antenna Pad
B. The second coil (L2) is connected between Antenna
Pad B and VSS. The capacitor is connected between
Antenna Pad A and VSS.
2.2
Antenna
The MCRF360 requires an external inductor of
1.377 µH for 13.56 MHz resonance frequency. About
one-fourth of the turns of the inductor should be
connected between Antenna Pad B and VSS; remain-
ing turns should be connected between Antenna Pad A
and Antenna Pad B. The MCRF355 requires this induc-
tor plus 100 pF of external capacitance in order to res-
onate at 13.56 MHz.
Figure 2-2 (b) shows another configuration of an
external circuit for the MCRF355. In this case, the res-
onant circuit is formed by two capacitors (C1 and C2)
and one inductor.
Figure 2-2(c) shows a configuration of an external
circuit for MCRF360.
FIGURE 2-2: CONFIGURATION OF EXTERNAL RESONANT CIRCUITS
Antenna Pad A
L1
Interrogator
C
MCRF355
Antenna Pad B
Vss
L2
L1 > L2
1
f0= ---------------------------------------
2π (L1 + L2)C
(a)
Antenna Pad A
C1
Interrogator
MCRF355
Antenna Pad B
C2
Vss
C1 > C2
1
f0 = -----------------------------------------
C1C2
2π L --------------------
C1 + C2
(b)
Antenna Pad A
Antenna Pad B
L1
L2
100 pF
Interrogator
MCRF360
Vss
L1 > L2
1
f0 = ----------------------------------------------------
(c)
2π (L)(100 × 10–12
)
DS21287B-page 6
Preliminary
1999 Microchip Technology Inc.
MCRF355/360
2.3.3
SLEEP TIMER
2.3
Controller Logic
This circuit generates a sleep time (100 ms ± 40%) for
the anticollision feature. During this sleep time (TOFF),
the modulation transistor remains in a turned-on condi-
tion (cloaked) which detunes the LC resonant circuit
away from the operating frequency (13.56 MHz).
2.3.1
CLOCK PULSE GENERATOR
This circuit generates a clock pulse (CLK). The clock
pulse is generated by an on-board time base oscillator.
The clock pulse is used for baud rate timing, data
modulation rate, etc.
2.3.4
READ/WRITE LOGIC
2.3.2
MODULATION LOGIC
This logic controls the reading and programming of the
memory array.
This logic acts upon the serial data (154 bits) being
read from the memory array. The data is then con-
verted to Manchester code. The code waveforms are
shown in Figure 2-3. The encoded data is then fed to
the modulation gate in the RF Front-End section.
FIGURE 2-3: CODE WAVEFORMS
DESCRIPTION
WAVEFORM
SIGNAL
Data
Digital Data
1
0
1
1
0
0
0
1
1
0
1
0
Internal Clock Signal
CLK
Non-Return to Zero - Level
NRZ - L
“1” is represented by logic high level.
“0” is represented by logic low level.
(Reference only)
Biphase - Level (Split Phase)
A level change occurs at middle of
every bit clock period.
BIPHASE - L
(Manchester)
“1” is represented by a high to low
level change at midclock.
“0” is represented by a low to high
level change at midclock.
Note: The CLK and NRZ-L signals are shown for reference only. The NRZ-L is not an output of the device
1999 Microchip Technology Inc.
Preliminary
DS21287B-page 7
MCRF355/360
3.2
Pin Timing
3.0
DEVICE PROGRAMMING
MCRF355/360 is a contact programmable device. The
device has 154 bits of programmable memory. It can be
programmed in the following procedure. (A program-
mer, part number PG103003, is also available from
Microchip.)
1. Apply VDDT voltage to VDD. Leave VSS, CLK,
and VPRG at ground.
2. Load mode code into the VPRG pad. The VPRG
is sampled at CLK low to high edge.
3. The above mode function (3.2.2) will be
executed when the last bit of code is entered.
3.0.1
PROGRAMMING LOGIC
4. Power the device off (VDD = VSS) to exit
programming mode.
Programming logic is enabled by applying power to the
device and clocking the device via the CLK pad while
loading the mode code via the VPRG pad (See
Examples 3-1 through 3-4 for test definitions). Both the
CLK and the VPRG pads have internal pull-down
resistors.
5. An alternative method to exit the programming
mode is to bring CLK logic “High” before VPRG
to VHH (high voltage).
6. Any programming mode can be entered after
exiting the current function.
3.1
Pin Configuration
3.3
Programming Mode
Connect antenna pads A, B, and VSS to ground.
1. Erase EE Code:
2. Program EE Code:
3. Read EE Code:
0111010100
0111010010
0111010110
Note: ‘0’ means logic “Low” (VIL) and ‘1’ means
logic “High” (VIH).
3.4
Signal Timing
Examples 3-1 through 3-4 show the timing sequence
for programming and reading of the device.
EXAMPLE 3-1: PROGRAMMING MODE 1: ERASE EE
CLK Number:
CLK
1
2
3
4
5
6
7
8
9
10
11
VHH
VIL
VIH
TWC
VPRG:
Note: Erases entire array to a ‘1’ state between CLK and Number 11 and 12.
DS21287B-page 8
Preliminary
1999 Microchip Technology Inc.
MCRF355/360
EXAMPLE 3-2: PROGRAMMING MODE 2: PROGRAM EE
CLK Number:
1
2
5
6
7
8
9
10
11
…
165
…
CLK:
Pulse high to program bit to “0”
Leave low to leave bit at “1”
VHH…
VIH
TWC
TWC
VIL
VPRG:
Program bit #0 … Program bit #153
Note: Pulsing VPRG to VHH for the bit programming time while holding the CLK low programs the bit to a ‘0’.
EXAMPLE 3-3: PROGRAMMING MODE 3: READ EE
CLK Number:
CLK:
1
2
5
6
7
8
9
10
11
12
165
VIH…
VPRG:
VIL
...
bit #0
bit #1
data
bit #153
data
data
Turn off programmer drive during
CLK high so MCRF355 can drive
VPRG.
EXAMPLE 3-4: TIMING DATA
THIGH
TLOW
CLK:
Vprg:
TPW:STO
THD:DAT
VHH
VIH
VIL
TAA
TSU:STO
TSU:DAT
TWC
VHH
TDL:HH
TSU:HH
VIH…
VIL
1999 Microchip Technology Inc.
Preliminary
DS21287B-page 9
MCRF355/360
MCRF355/360 GUIDE PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, please refer to the factory or the listed sales office.
MCRF355 – /WF
WF = Sawed wafer on frame (11 mil backgrind)
W = Wafer (11 mil backgrind)
S = Dice in waffle pack
SN = 150 mil SOIC
P = PDIP
Package:
Temperature
Range:
= -20°C to +50°C
Part
Number:
MCRF355 = 13.56 MHz Anticollision device
MCRF360 = 13.56 MHz Anticollision device with 100 pF of
on-chip resonance capacitance
DS21287B-page 10
Preliminary
1999 Microchip Technology Inc.
MCRF355/360
NOTES:
1999 Microchip Technology Inc.
Preliminary
DS21287B-page 11
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DS21287B-page 12
1999 Microchip Technology Inc.
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