MCP6234T [MICROCHIP]
20 μA, 300 kHz Rail-to-Rail Op Amp; 20 μA ， 300 kHz的轨至轨运算放大器
| 型号： | MCP6234T |
| 厂家： | 
MICROCHIP |
| 描述： | 20 μA, 300 kHz Rail-to-Rail Op Amp |
| 文件： | 总40页 (文件大小：821K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6231/1R/1U/2/4
20 µA, 300 kHz Rail-to-Rail Op Amp
Description
Features
The Microchip Technology Inc. MCP6231/1R/1U/2/4
operational amplifiers (op amps) provide wide
bandwidth for the quiescent current. The MCP6231/1R/
1U/2/4 family has a 300 kHz gain bandwidth product
and 65°C (typical) phase margin. This family operates
from a single supply voltage as low as 1.8V, while
drawing 20 µA (typical) quiescent current. In addition,
the MCP6231/1R/1U/2/4 family supports rail-to-rail
input and output swing, with a common mode input
voltage range of VDD + 300 mV to VSS – 300 mV.
These op amps are designed in one of Microchip’s
advanced CMOS processes.
• Gain Bandwidth Product: 300 kHz (typical)
• Supply Current: IQ = 20 µA (typical)
• Supply Voltage: 1.8V to 6.0V
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in 5-Pin SC70 and SOT-23 packages
Applications
• Automotive
• Portable Equipment
• Transimpedance amplifiers
• Analog Filters
Package Types
MCP6231
MCP6231
• Notebooks and PDAs
• Battery-Powered Systems
MSOP, PDIP, SOIC
SOT-23-5
1
2
3
4
8
7
6
5
NC
NC
V
V
V
1
2
3
5
4
DD
OUT
V
–
+
–
+
DD
IN
V
Design Aids
SS
+
–
V
V
OUT
IN
V
V
–
IN
IN
• SPICE Macro Models
• FilterLab® Software
V
NC
SS
MCP6232
MSOP, PDIP, SOIC
MCP6231R
• Mindi™ Circuit Designer & Simulator
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
SOT-23-5
VOUTA
V
V
VDD
8
7
6
5
1
2
1
5
4
SS
OUT
_
V
VINA
2
3
-
VOUTB
DD
+
+
–
_
V
V –
IN
VINA+ 3
+
-
IN
VINB
Typical Application
VSS
4
VINB
+
RG2
MCP6232
MCP6231U
SC70-5, SOT-23-5
VIN2
VIN1
2x3 TDFN *
RG1
VDD
VOUTA
1
2
8
7
V
V
+
1
2
3
5
DD
IN
+
RF
_
VINA
VOUTB
EP
9
V
SS
–
_
VDD
VINA+
VINB
3
4
6
5
V
–
V
OUT
4
IN
–
VSS
VINB+
RX
RY
VOUT
MCP6231
+
MCP6231
DFN *
MCP6234
PDIP, SOIC, TSSOP
RZ
NC
1
2
8
NC
VOUTA
14 VOUTD
1
2
3
4
VINA
–
+
- + + 13 VIND
-
–
+
V
–
V
7
EP
9
IN
DD
VINA
12 VIND
V
+
V
3
4
6
5
IN
OUT
VDD
VSS
11
VSS
NC
Summing Amplifier Circuit
VINB
+
–
10 VINC
-
9 VINC
+
–
5
6
7
-
+ +
VINB
VOUTB
8 VOUTC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
© 2009 Microchip Technology Inc.
DS21881E-page 1
MCP6231/1R/1U/2/4
NOTES:
DS21881E-page 2
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Analog Input Pins (VIN+, VIN–).....................±2 mA
Analog Inputs (VIN+, VIN–) ††........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Difference Input Voltage ...................................... |VDD – VSS
|
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ...................................–65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD Protection On All Pins (HBM; MM) .............. ≥ 4 kV; 300V
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2,
RL = 100 kΩ to VDD/2 and VOUT ≈ VDD/2.
Sym
Min
Typ
Max
Units Conditions
Parameters
Input Offset
Input Offset Voltage
VOS
VOS
-5.0
-7.0
—
—
+5.0
+7.0
mV
mV
VCM = VSS
Extended Temperature
TA = -40°C to +125°C,
V
CM = VSS (Note 1)
µV/°C TA= -40°C to +125°C,
CM = VSS
Input Offset Drift with Temperature
ΔVOS/ΔTA
—
—
±3.0
83
—
—
V
Power Supply Rejection Ratio
Input Bias Current and Impedance
Input Bias Current:
PSRR
dB
VCM = VSS
IB
IB
—
—
—
—
—
—
±1.0
20
—
—
—
—
—
—
pA
pA
At Temperature
TA = +85°C
At Temperature
IB
1100
±1.0
1013||6
1013||3
pA
TA = +125°C
Input Offset Current
IOS
ZCM
ZDIFF
pA
Common Mode Input Impedance
Differential Input Impedance
Common Mode
Ω||pF
Ω||pF
Common Mode Input Range
Common Mode Rejection Ratio
VCMR
VSS – 0.3
61
—
VDD + 0.3
—
V
CMRR
75
dB
VCM = -0.3V to 5.3V,
V
DD = 5V
Open-Loop Gain
DC Open-Loop Gain (large signal)
AOL
90
110
—
—
dB
VOUT = 0.3V to VDD – 0.3V,
CM = VSS
V
Output
Maximum Output Voltage Swing
VOL, VOH
VSS + 35
VDD – 35
mV
RL =10 kΩ, 0.5V Input
Overdrive
Output Short-Circuit Current
ISC
ISC
—
—
±6
—
—
mA
mA
VDD = 1.8V
VDD = 5.5V
±23
Power Supply
Supply Voltage
VDD
IQ
1.8
10
—
6.0
30
V
Quiescent Current per Amplifier
20
µA
IO = 0, VCM = VDD – 0.5V
Note 1: The SC70 package is only tested at +25°C.
2: All parts with date codes February 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the
other minimum and maximum specifications are measured at 1.8V and 5.5V
© 2009 Microchip Technology Inc.
DS21881E-page 3
MCP6231/1R/1U/2/4
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
300
65
—
—
—
kHz
°
G = +1 V/V
Slew Rate
SR
0.15
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Eni
eni
ini
—
—
—
6.0
52
—
—
—
µVP-P f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 kHz
0.6
fA/√Hz f = 1 kHz
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Extended Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SC70
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-DFN
Thermal Resistance, 8L-MSOP
Thermal Resistance, 8L-TDFN
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
Note
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
θJA
θJA
θJA
θJA
θJA
θJA
θJA
θJA
θJA
θJA
331
256
84.5
206
41
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
85
163
70
120
100
Note:
The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
1.1
Test Circuits
VDD
1 µF
The test circuits used for the DC and AC tests are
shown in Figure 1-1 and Figure 1-1. The bypass
capacitors are laid out according to the rules discussed
in Section 4.6 “PCB Surface Leakage”.
0.1 µF
VDD/2
VOUT
RL
RN
RG
MCP623X
CL
VDD
RF
1 µF
VIN
0.1 µF
VIN
VL
VOUT
RL
RN
MCP623X
FIGURE 1-2:
Most Inverting Gain Conditions.
AC and DC Test Circuit for
CL
RG
RF
VDD/2
VL
FIGURE 1-1:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
DS21881E-page 4
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
90
85
80
75
70
20%
18%
16%
14%
12%
10%
8%
630 Samples
CM = VSS
V
PSRR (VCM = VSS
)
6%
CMRR (VCM = -0.3V to +5.3V,
VDD = 5.0V)
4%
2%
0%
-50
-25
0
25
50
75
100
125
Input Offset Voltage (mV)
Ambient Temperature (°C)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
CMRR, PSRR vs. Ambient
Temperature.
100
90
80
70
60
50
40
30
120
100
80
0
RL = 10 kΩ
PSRR-
-30
VCM = VDD/2
Gain
-60
CMRR
60
-90
Phase
PSRR+
40
20
0
-120
-150
-180
-210
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
20
-20
10
100
1k
10k
100k
0.1
1
10 100 1k 10k 100k 1M 10M
1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+
01 00 01 Fr0e2que0n3cy (0H4z) 05 06 07
Frequency (Hz)
FIGURE 2-2:
PSRR, CMRR vs.
FIGURE 2-5:
Open-Loop Gain, Phase vs.
Frequency.
Frequency.
20%
30%
632 Samples
CM = VDD/2
TA = +125°C
630 Samples
CM = VDD/2
TA = +85°C
18%
16%
14%
12%
10%
8%
V
V
25%
20%
15%
10%
5%
6%
4%
2%
0%
0%
Input Bias Current (pA)
Input Bias Current (nA)
FIGURE 2-3:
Input Bias Current at +85°C.
FIGURE 2-6:
Input Bias Current at
+125°C.
© 2009 Microchip Technology Inc.
DS21881E-page 5
MCP6231/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
1,000
20%
628 Samples
18%
VCM = VSS
16%
14%
12%
10%
8%
TA = -40°C to +125°C
100
10
6%
4%
2%
0%
0.1
1
10
100
1k
10k 100k
1.E-01 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0
0
1Freque2ncy (Hz3)
4
5
Input Offset Voltage Drift (µV/°C)
FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
Input Offset Voltage Drift.
vs. Frequency.
100
50
550
VCM = VSS
VDD = 1.8V
TA = -40°C
A = +25°C
TA = +85°C
A = +125°C
T
450
350
250
150
0
-50
-100
-150
-200
T
VDD = 5.5V
VDD = 1.8V
-250
-300
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-11:
Input Offset Voltage vs.
FIGURE 2-8:
Input Offset Voltage vs.
Output Voltage.
Common Mode Input Voltage at V = 1.8V.
DD
30
25
20
15
10
5
200
+ISC
VDD = 5.5 V
150
TA = +125°C
100
TA = +85°C
A = +25°C
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
50
T
0
-5
0
-50
TA = -40°C
-10
-15
-20
-25
-30
-100
-150
-200
-ISC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-12:
Output Short-Circuit Current
FIGURE 2-9:
Input Offset Voltage vs.
vs. Ambient Temperature.
Common Mode Input Voltage at V = 5.5V.
DD
DS21881E-page 6
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
0.30
0.25
0.20
0.15
0.10
0.05
G = +1 V/V
RL = 10 kΩ
VDD = 5.5V
Falling Edge
VDD = 1.8V
50
Rising Edge
-50 -25
0
25
75
100
125
Time (2 µs/div)
Ambient Temperature (°C)
FIGURE 2-13:
Slew Rate vs. Ambient
FIGURE 2-16:
Small-Signal, Non-Inverting
Temperature.
Pulse Response.
1,000
100
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.0V
G = +1 V/V
VDD – VOH
VOL – VSS
1
10µ
100µ
11
1m
1.0
10m
11
12
Output Current Magnitude (A)
Time (20 µs/div)
FIGURE 2-14:
Output Voltage Headroom
FIGURE 2-17:
Large-Signal, Non-Inverting
vs. Output Current Magnitude.
Pulse Response.
30
10
VCM = 0.9VDD
25
20
15
10
5
VDD = 5.5V
VDD = 1.8V
1
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
1k
10k
1.E+04
100k
1.E+05
1M
1.E+06
1.E+03
Frequency (Hz)
FIGURE 2-15:
Maximum Output Voltage
FIGURE 2-18:
Quiescent Current vs.
Swing vs. Frequency.
Power Supply Voltage.
© 2009 Microchip Technology Inc.
DS21881E-page 7
MCP6231/1R/1U/2/4
1.E-02
10m
1.E-03
1m
1.E- 4
100µ
1.E1-05µ
1.E-016µ
100n
1.E- 7
10n
1.E- 8
1n
1.E-09
100p
1.E-10
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-1.0
VDD = 5.0V
G = +2 V/V
VOUT
VIN
+125°C
+85°C
+25°C
-40°C
10p
1.E-11
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Time (1 ms/div)
FIGURE 2-19:
Measured Input Current vs.
FIGURE 2-20:
The MCP6231/1R/1U/2/4
Input Voltage (below V ).
Show No Phase Reversal.
SS
DS21881E-page 8
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6231
MCP6231R
MCP6231U
Symbol
Description
DFN, MSOP,
PDIP, SOIC
SOT-23-5
SC70
SOT-23-5
SOT-23-5
6
1
4
1
4
4
3
VOUT
VIN–
VIN+
VDD
VSS
NC
Analog Output
2
Inverting Input
3
3
3
1
Non-inverting Input
7
5
2
5
Positive Power Supply
Negative Power Supply
No Internal Connection
Exposed Thermal Pad (EP); must be
4
1, 5, 8
9
2
5
2
—
—
—
—
—
—
EP
connected to VSS
.
TABLE 3-2:
MCP6232
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6234
Symbol
Description
MSOP, PDIP,
SOIC, TDFN
PDIP, SOIC, TSSOP
1
2
1
2
VOUTA
Analog Output (op amp A)
VINA
–
+
Inverting Input (op amp A)
3
3
VINA
Non-inverting Input (op amp A)
Positive Power Supply
8
4
VDD
5
5
VINB
+
Non-inverting Input (op amp B)
Inverting Input (op amp B)
6
6
VINB
–
7
7
VOUTB
VOUTC
Analog Output (op amp B)
—
—
—
4
8
Analog Output (op amp C)
9
VINC
–
+
Inverting Input (op amp C)
10
11
12
13
14
—
VINC
Non-inverting Input (op amp C)
Negative Power Supply
VSS
—
—
—
9
VIND
+
Non-inverting Input (op amp D)
Inverting Input (op amp D)
VIND
–
VOUTD
—
Analog Output (op amp D)
Exposed Thermal Pad (EP); must be connected to VSS
.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.1
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
3.4
Exposed Thermal Pad (EP)
The non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
3.3
Power Supply (VSS and VDD)
The positive power supply (VDD) is 1.8V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
© 2009 Microchip Technology Inc.
DS21881E-page 9
MCP6231/1R/1U/2/4
NOTES:
DS21881E-page 10
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
4.0
APPLICATION INFORMATION
Bond
VDD
The MCP6231/1R/1U/2/4 family of op amps is
manufactured using Microchip’s state-of-the-art CMOS
process and is specifically designed for low-cost,
low-power and general-purpose applications. The low
supply voltage, low quiescent current and wide
bandwidth makes the MCP6231/1R/1U/2/4 ideal for
battery-powered applications.
Pad
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
4.1
Rail-to-Rail Inputs
Bond
Pad
VSS
4.1.1
PHASE REVERSAL
The MCP6231/1R/1U/2/4 op amp is designed to
prevent phase reversal when the input pins exceed the
supply voltages. Figure 4-1 shows the input voltage
exceeding the supply voltage without any phase
reversal.
FIGURE 4-2:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
6.0
VDD = 5.0V
VOUT
5.0
4.0
3.0
2.0
1.0
0.0
-1.0
G = +2 V/V
VIN
Time (1 ms/div)
VDD
FIGURE 4-1:
The MCP6231/1R/1U/2/4
Show No Phase Reversal.
D1 D2
4.1.2 INPUT VOLTAGE AND CURRENT
V1
LIMITS
R1
MCP623X
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
V2
R2
R3
VSS – (minimum expected V1)
R1 >
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
FIGURE 4-3:
Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
© 2009 Microchip Technology Inc.
DS21881E-page 11
MCP6231/1R/1U/2/4
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-19. Applications that are
high impedance may need to limit the usable voltage
range.
10,01000k
1k
1,000
4.1.3
NORMAL OPERATION
GN = 1 V/V
GN = 2 V/V
GN ≥ 4 V/V
The input stage of the MCP6231/1R/1U/2/4 op amps
use two differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM),
while the other operates at high VCM. WIth this
topology, the device operates with VCM up to 0.3V
100
100
10p
100p
100
1n
10n
10
1000
10000
Normalized Load Capacitance; CL/GN (F)
above VDD and 0.3V below VSS
.
FIGURE 4-5:
for Capacitive Loads.
Recommended R
Values
ISO
4.2
Rail-to-Rail Output
The output voltage range of the MCP6231/1R/1U/2/4
op amps is VDD – 35 mV (maximum) and VSS + 35 mV
(minimum) when RL = 10 kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to Figure 2-14 for more information.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6231/1R/1U/2/4 SPICE
macro model are very helpful. Modify RISO’s value until
the response is reasonable.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, but all gains show the
same general behavior.
4.4
Supply Bypass
With this op amp, the power supply pin (VDD for
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good
high-frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can
be shared with other nearby analog parts.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
4.5
Unused Op Amps
An unused op amp in a quad package (MCP6234)
should be configured as shown in Figure 4-6. Both
circuits prevent the output from toggling and causing
crosstalk. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage
and minimizes the supply current draw of the unused
op amp. Circuit
B
minimizes the number of
components, but may draw a little more supply current
for the unused op amp.
–
RISO
VOUT
MCP623X
+
VIN
CL
¼ MCP6234 (A)
VDD
¼ MCP6234 (B)
VDD
VDD
FIGURE 4-4:
stabilizes large capacitive loads.
Output resistor, R
ISO
R1
R2
VREF
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
signal gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., –1 V/V gives GN = +2 V/V).
R
2
--------------------
V
= V
⋅
REF
DD
R + R
1
2
FIGURE 4-6:
Unused Op Amps.
DS21881E-page 12
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
4.6
PCB Surface Leakage
4.7
Application Circuits
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6231/1R/1U/2/4 family’s bias current at +25°C
(1 pA, typical).
4.7.1
MATCHING THE IMPEDANCE AT
THE INPUTS
To minimize the effect of input bias current in an ampli-
fier circuit (this is important for very high source-
impedance applications, such as pH meters and
transimpedance amplifiers), the impedances at the
inverting and non-inverting inputs need to be
matched. This is done by choosing the circuit resistor
values so that the total resistance at each input is the
same. Figure 4-8 shows a summing amplifier circuit.
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
RG2
VIN2
VIN1
RG1
RF
VIN–
VIN+
VSS
VDD
–
RX
RY
VOUT
MCP623X
+
RZ
Guard Ring
Example Guard Ring Layout
FIGURE 4-8:
Summing Amplifier Circuit.
FIGURE 4-7:
for Inverting Gain.
To match the inputs, set all voltage sources to ground
and calculate the total resistance at the input nodes. In
this summing amplifier circuit, the resistance at the
inverting input is calculated by setting VIN1, VIN2 and
VOUT to ground. In this case, RG1, RG2 and RF are in
parallel. The total resistance at the inverting input is:
1. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
EQUATION 4-1:
1
1
RVIN – = ----------------------------------------------
1
1
⎛
⎝
⎞
⎠
2. Inverting Gain and Transimpedance Amplifiers
(convert current to voltage, such as photo
detectors):
--------- + --------- + ------
RG1 RG2 RF
Where:
RVIN
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
–
=
total resistance at the inverting
input
At the non-inverting input, VDD is the only voltage
source. When VDD is set to ground, both Rx and Ry are
in parallel. The total resistance at the non-inverting
input is:
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
EQUATION 4-2:
1
RVIN = ------------------------- + RZ
+
1
1
⎛
⎝
⎞
⎠
------ + -----
RX RY
Where:
RVIN
+
=
total resistance at the inverting
input
© 2009 Microchip Technology Inc.
DS21881E-page 13
MCP6231/1R/1U/2/4
To minimize output offset voltage and increase circuit
accuracy, the resistor values need to meet the
conditions:
EQUATION 4-3:
RVIN = RVIN
–
+
4.7.2
COMPENSATING FOR THE
PARASITIC CAPACITANCE
In analog circuit design, the PCB parasitic capacitance
can compromise the circuit behavior; Figure 4-9 shows
a typical scenario. If the input of an amplifier sees
parasitic capacitance of several picofarad (CPARA
,
which includes the common mode capacitance of 6 pF,
typical), and large RF and RG, the frequency response
of the circuit will include a zero. This parasitic zero
introduces gain-peaking and can cause circuit
instability.
VAC
+
VOUT
MCP623X
–
RG
RF
VDC
CPARA
CF
RG
------
RF
CF = CPARA
•
FIGURE 4-9:
Effect of Parasitic
Capacitance at the Input.
One solution is to use smaller resistor values to push
the zero to a higher frequency. Another solution is to
compensate by introducing a pole at the point at which
the zero occurs. This can be done by adding CF in
parallel with the feedback resistor (RF). CF needs to be
selected so that the ratio CPARA:CF is equal to the ratio
of RF:RG.
DS21881E-page 14
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
5.5
Analog Demonstration and
Evaluation Boards
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6231/1R/1U/2/4 family of op amps.
Microchip offers
a
broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
5.1
SPICE Macro Model
a
complete listing of these boards and their
The latest SPICE macro model for the MCP6231/1R/
1U/2/4 op amps is available on the Microchip web site
at www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
corresponding user’s guides and technical information,
visit the Microchip web site at:
www.microchip.com/analogtools
Two of our boards that are especially useful are:
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
Evaluation Board
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP
Evaluation Board
5.6
Application Notes
FilterLab® Software
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
5.2
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
5.3
Mindi™ Circuit Designer &
Simulator
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
These application notes and others are listed in the
design guide:
• “Signal Chain Design Guide”, DS21825
5.4
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data sheets,
Purchase, and Sampling of Microchip parts.
© 2009 Microchip Technology Inc.
DS21881E-page 15
MCP6231/1R/1U/2/4
NOTES:
DS21881E-page 16
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SC70 (MCP6231U Only)
Example:
AS25
XXNN
Example:
5-Lead SOT-23
5
4
3
5
4
3
Device
MCP6231
Code
BJNN
BKNN
BLNN
BJ25
XXNN
MCP6231R
MCP6231U
1
2
1
2
Note:
Applies to 5-Lead SOT-23.
Example:
8-Lead DFN (2 x 3) (MCP6231)
XXX
YWW
NNN
AER
929
256
Example:
8-Lead TDFN (2 x 3) (MCP6232)
AAE
929
256
XXX
YWW
NNN
Example:
8-Lead MSOP
XXXXXX
YWWNNN
6232E
929256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS21881E-page 17
MCP6231/1R/1U/2/4
Package Marking Information (Continued)
8-Lead PDIP (300 mil)
Example:
MCP6232
XXXXXXXX
XXXXXNNN
MCP6232
e
3
E/P256
0929
E/P 256
0929
OR
YYWW
8-Lead SOIC (150 mil)
Example:
MCP6232E
XXXXXXXX
XXXXYYWW
MCP6232
E/SN0929
OR
e
3
SN 0929
256
NNN
256
14-Lead PDIP (300 mil) (MCP6234)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP6234
e
3
E/P^^
YYWWNNN
0929256
14-Lead SOIC (150 mil) (MCP6234)
Example:
MCP6234
E/SL^
XXXXXXXXXX
XXXXXXXXXX
e
3
YYWWNNN
0929256
Example:
14-Lead TSSOP (MCP6234)
6234E
0929
XXXXXXXX
YYWW
256
NNN
DS21881E-page 18
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
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DS21881E-page 19
MCP6231/1R/1U/2/4
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© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
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ꢑꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢜꢐꢝꢀ)
© 2009 Microchip Technology Inc.
DS21881E-page 21
MCP6231/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ$ꢈꢄꢊ%ꢆꢜꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ&ꢄ'ꢃꢆꢕ(ꢘꢖꢆMꢆ *!*ꢚ+,ꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗ#$ꢜꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
e
D
b
N
N
L
K
E2
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EXPOSED PAD
NOTE 1
NOTE 1
2
1
1
2
D2
BOTTOM VIEW
TOP VIEW
A
NOTE 2
A3
A1
3ꢆꢃ#
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ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#
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;
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)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢚ".+ ꢚꢅ%ꢅꢍꢅꢆꢊꢅꢈꢂꢃꢄꢅꢆ ꢃꢇꢆ0ꢈ$ $ꢉꢋꢋꢘꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ0ꢈ%ꢇꢍꢈꢃꢆ%ꢇꢍꢄꢉ#ꢃꢇꢆꢈꢎ$ꢍꢎꢇ ꢅ ꢈꢇꢆꢋꢘꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢜꢀꢑꢛ*
DS21881E-page 22
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ$ꢈꢄꢊ%ꢆꢜꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ&ꢄ'ꢃꢆꢕ(ꢘꢖꢆMꢆ *!*ꢚ+,ꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗ#$ꢜꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
© 2009 Microchip Technology Inc.
DS21881E-page 23
MCP6231/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ$ꢈꢄꢊ%ꢆꢜꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ&ꢄ'ꢃꢆꢕ(ꢜꢖꢆMꢆ *!*ꢚ+ꢙꢀꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗꢒ#$ꢜꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
DS21881E-page 24
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ$ꢈꢄꢊ%ꢆꢜꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ&ꢄ'ꢃꢆꢕ(ꢜꢖꢆMꢆ *!*ꢚ+ꢙꢀꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗꢒ#$ꢜꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
© 2009 Microchip Technology Inc.
DS21881E-page 25
MCP6231/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ(ꢋꢌꢓꢔꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢇꢄꢌ&ꢄ'ꢃꢆꢕ(ꢍꢖꢆꢗ(ꢍꢏꢇꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
D
N
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E1
NOTE 1
2
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φ
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ꢛꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢚ".+ ꢚꢅ%ꢅꢍꢅꢆꢊꢅꢈꢂꢃꢄꢅꢆ ꢃꢇꢆ0ꢈ$ $ꢉꢋꢋꢘꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ0ꢈ%ꢇꢍꢈꢃꢆ%ꢇꢍꢄꢉ#ꢃꢇꢆꢈꢎ$ꢍꢎꢇ ꢅ ꢈꢇꢆꢋꢘꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢜꢀꢀꢀ)
DS21881E-page 26
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009 Microchip Technology Inc.
DS21881E-page 27
MCP6231/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ/ꢑꢁꢂꢋꢑꢃꢆꢕꢇꢖꢆMꢆ!ꢚꢚꢆꢎꢋꢈꢆ-ꢔꢅ.ꢆꢗꢇ#/ꢇꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
A1
c
e
eB
b1
b
3ꢆꢃ#
ꢙ5*:"ꢕ
ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#
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;
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M
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M
ꢏꢔ7
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1ꢃ#ꢊꢌ
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)ꢉ ꢅꢈ#ꢇꢈꢕꢅꢉ#ꢃꢆꢓꢈ1ꢋꢉꢆꢅ
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6,ꢅꢍꢉꢋꢋꢈ4ꢅꢆꢓ#ꢌ
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8
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ꢁꢐꢐ;
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M
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4ꢇ-ꢅꢍꢈ4ꢅꢉ!ꢈ=ꢃ!#ꢌ
6,ꢅꢍꢉꢋꢋꢈꢚꢇ-ꢈꢕꢎꢉꢊꢃꢆꢓꢈꢈꢟ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ 1ꢃꢆꢈꢀꢈ,ꢃ $ꢉꢋꢈꢃꢆ!ꢅ&ꢈ%ꢅꢉ#$ꢍꢅꢈꢄꢉꢘꢈ,ꢉꢍꢘ0ꢈ8$#ꢈꢄ$ #ꢈ8ꢅꢈꢋꢇꢊꢉ#ꢅ!ꢈ-ꢃ#ꢌꢈ#ꢌꢅꢈꢌꢉ#ꢊꢌꢅ!ꢈꢉꢍꢅꢉꢁ
ꢑꢁ ꢟꢈꢕꢃꢓꢆꢃ%ꢃꢊꢉꢆ#ꢈ*ꢌꢉꢍꢉꢊ#ꢅꢍꢃ #ꢃꢊꢁ
ꢛꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢁꢐꢀꢐAꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ
ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ꢈ)ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢜꢐꢀ;)
DS21881E-page 28
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢜꢖꢆMꢆꢜꢄꢓꢓꢔ0%ꢆ!+,ꢚꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗꢍꢏ/ꢘꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
D
e
N
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NOTE 1
1
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3
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h
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L1
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;
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ꢔ
M
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M
M
M
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*ꢌꢉꢄ%ꢅꢍꢈBꢇꢎ#ꢃꢇꢆꢉꢋC
.ꢇꢇ#ꢈ4ꢅꢆꢓ#ꢌ
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4ꢅꢉ!ꢈꢗꢌꢃꢊ/ꢆꢅ
4ꢅꢉ!ꢈ=ꢃ!#ꢌ
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ꢏꢇꢋ!ꢈꢂꢍꢉ%#ꢈꢔꢆꢓꢋꢅꢈ)ꢇ##ꢇꢄ
4ꢀ
ꢀ
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ꢐꢞ
ꢐꢁꢀꢒ
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M
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;ꢞ
ꢊ
8
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ꢐꢁꢑ(
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ꢀꢁ 1ꢃꢆꢈꢀꢈ,ꢃ $ꢉꢋꢈꢃꢆ!ꢅ&ꢈ%ꢅꢉ#$ꢍꢅꢈꢄꢉꢘꢈ,ꢉꢍꢘ0ꢈ8$#ꢈꢄ$ #ꢈ8ꢅꢈꢋꢇꢊꢉ#ꢅ!ꢈ-ꢃ#ꢌꢃꢆꢈ#ꢌꢅꢈꢌꢉ#ꢊꢌꢅ!ꢈꢉꢍꢅꢉꢁ
ꢑꢁ ꢟꢈꢕꢃꢓꢆꢃ%ꢃꢊꢉꢆ#ꢈ*ꢌꢉꢍꢉꢊ#ꢅꢍꢃ #ꢃꢊꢁ
ꢛꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀ(ꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ
ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢚ".+ ꢚꢅ%ꢅꢍꢅꢆꢊꢅꢈꢂꢃꢄꢅꢆ ꢃꢇꢆ0ꢈ$ $ꢉꢋꢋꢘꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ0ꢈ%ꢇꢍꢈꢃꢆ%ꢇꢍꢄꢉ#ꢃꢇꢆꢈꢎ$ꢍꢎꢇ ꢅ ꢈꢇꢆꢋꢘꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢜꢐ(ꢒ)
© 2009 Microchip Technology Inc.
DS21881E-page 29
MCP6231/1R/1U/2/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢜꢖꢆMꢆꢜꢄꢓꢓꢔ0%ꢆ!+,ꢚꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗꢍꢏ/ꢘꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
DS21881E-page 30
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
12ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ/ꢑꢁꢂꢋꢑꢃꢆꢕꢇꢖꢆMꢆ!ꢚꢚꢆꢎꢋꢈꢆ-ꢔꢅ.ꢆꢗꢇ#/ꢇꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
c
A1
b1
b
e
eB
3ꢆꢃ#
ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#
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56ꢏ
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M
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ꢁꢑꢖꢐ
ꢁꢒꢛ(
ꢁꢀꢀ(
ꢁꢐꢐ;
ꢁꢐꢖ(
ꢁꢐꢀꢖ
M
ꢁꢀꢛꢐ
M
ꢁꢛꢀꢐ
ꢁꢑ(ꢐ
ꢁꢒ(ꢐ
ꢁꢀꢛꢐ
ꢁꢐꢀꢐ
ꢁꢐ9ꢐ
ꢁꢐꢀ;
M
ꢁꢛꢑ(
ꢁꢑ;ꢐ
ꢁꢒꢒ(
ꢁꢀ(ꢐ
ꢁꢐꢀ(
ꢁꢐꢒꢐ
ꢁꢐꢑꢑ
ꢁꢖꢛꢐ
4ꢇ-ꢅꢍꢈ4ꢅꢉ!ꢈ=ꢃ!#ꢌ
6,ꢅꢍꢉꢋꢋꢈꢚꢇ-ꢈꢕꢎꢉꢊꢃꢆꢓꢈꢈꢟ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ 1ꢃꢆꢈꢀꢈ,ꢃ $ꢉꢋꢈꢃꢆ!ꢅ&ꢈ%ꢅꢉ#$ꢍꢅꢈꢄꢉꢘꢈ,ꢉꢍꢘ0ꢈ8$#ꢈꢄ$ #ꢈ8ꢅꢈꢋꢇꢊꢉ#ꢅ!ꢈ-ꢃ#ꢌꢈ#ꢌꢅꢈꢌꢉ#ꢊꢌꢅ!ꢈꢉꢍꢅꢉꢁ
ꢑꢁ ꢟꢈꢕꢃꢓꢆꢃ%ꢃꢊꢉꢆ#ꢈ*ꢌꢉꢍꢉꢊ#ꢅꢍꢃ #ꢃꢊꢁ
ꢛꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢁꢐꢀꢐAꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ
ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ꢈ)ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢜꢐꢐ()
© 2009 Microchip Technology Inc.
DS21881E-page 31
MCP6231/1R/1U/2/4
12ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢂꢖꢆMꢆꢜꢄꢓꢓꢔ0%ꢆ!+,ꢚꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗꢍꢏ/ꢘꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
D
N
E
E1
NOTE 1
1
2
3
e
h
b
α
h
c
φ
A2
A
L
A1
β
L1
3ꢆꢃ#
ꢏꢙ44ꢙꢏ"ꢗ"ꢚꢕ
ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#
ꢏꢙ5
56ꢏ
ꢏꢔ7
5$ꢄ8ꢅꢍꢈꢇ%ꢈ1ꢃꢆ
1ꢃ#ꢊꢌ
5
ꢅ
ꢀꢖ
ꢀꢁꢑꢒꢈ)ꢕ*
6,ꢅꢍꢉꢋꢋꢈ:ꢅꢃꢓꢌ#
ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈꢗꢌꢃꢊ/ꢆꢅ
ꢕ#ꢉꢆ!ꢇ%%ꢈꢈꢟ
ꢔ
M
ꢀꢁꢑ(
ꢐꢁꢀꢐ
M
M
M
ꢀꢁꢒ(
M
ꢐꢁꢑ(
ꢔꢑ
ꢔꢀ
"
6,ꢅꢍꢉꢋꢋꢈ=ꢃ!#ꢌ
9ꢁꢐꢐꢈ)ꢕ*
ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈ=ꢃ!#ꢌ
6,ꢅꢍꢉꢋꢋꢈ4ꢅꢆꢓ#ꢌ
*ꢌꢉꢄ%ꢅꢍꢈBꢇꢎ#ꢃꢇꢆꢉꢋC
.ꢇꢇ#ꢈ4ꢅꢆꢓ#ꢌ
"ꢀ
ꢂ
ꢌ
ꢛꢁꢝꢐꢈ)ꢕ*
;ꢁ9(ꢈ)ꢕ*
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ꢐꢁꢖꢐ
M
M
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ꢀꢁꢑꢒ
4
.ꢇꢇ#ꢎꢍꢃꢆ#
.ꢇꢇ#ꢈꢔꢆꢓꢋꢅ
4ꢅꢉ!ꢈꢗꢌꢃꢊ/ꢆꢅ
4ꢅꢉ!ꢈ=ꢃ!#ꢌ
ꢏꢇꢋ!ꢈꢂꢍꢉ%#ꢈꢔꢆꢓꢋꢅꢈꢗꢇꢎ
ꢏꢇꢋ!ꢈꢂꢍꢉ%#ꢈꢔꢆꢓꢋꢅꢈ)ꢇ##ꢇꢄ
4ꢀ
ꢀ
ꢀꢁꢐꢖꢈꢚ".
ꢐꢞ
ꢐꢁꢀꢒ
ꢐꢁꢛꢀ
(ꢞ
M
M
M
M
M
;ꢞ
ꢊ
8
ꢁ
ꢐꢁꢑ(
ꢐꢁ(ꢀ
ꢀ(ꢞ
ꢂ
(ꢞ
ꢀ(ꢞ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ 1ꢃꢆꢈꢀꢈ,ꢃ $ꢉꢋꢈꢃꢆ!ꢅ&ꢈ%ꢅꢉ#$ꢍꢅꢈꢄꢉꢘꢈ,ꢉꢍꢘ0ꢈ8$#ꢈꢄ$ #ꢈ8ꢅꢈꢋꢇꢊꢉ#ꢅ!ꢈ-ꢃ#ꢌꢃꢆꢈ#ꢌꢅꢈꢌꢉ#ꢊꢌꢅ!ꢈꢉꢍꢅꢉꢁ
ꢑꢁ ꢟꢈꢕꢃꢓꢆꢃ%ꢃꢊꢉꢆ#ꢈ*ꢌꢉꢍꢉꢊ#ꢅꢍꢃ #ꢃꢊꢁ
ꢛꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀ(ꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ
ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢚ".+ ꢚꢅ%ꢅꢍꢅꢆꢊꢅꢈꢂꢃꢄꢅꢆ ꢃꢇꢆ0ꢈ$ $ꢉꢋꢋꢘꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ0ꢈ%ꢇꢍꢈꢃꢆ%ꢇꢍꢄꢉ#ꢃꢇꢆꢈꢎ$ꢍꢎꢇ ꢅ ꢈꢇꢆꢋꢘꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢜꢐ9()
DS21881E-page 32
© 2009 Microchip Technology Inc.
MCP6231/1R/1U/2/4
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
© 2009 Microchip Technology Inc.
DS21881E-page 33
MCP6231/1R/1U/2/4
12ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢒ3ꢋꢑꢆꢍ3ꢓꢋꢑ&ꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢒꢖꢆMꢆ2+2ꢆꢎꢎꢆ-ꢔꢅ.ꢆꢗꢒꢍꢍꢏꢇꢛ
ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
D
N
E
E1
NOTE 1
1
2
e
b
c
φ
A2
A
A1
L
L1
3ꢆꢃ#
ꢏꢙ44ꢙꢏ"ꢗ"ꢚꢕ
ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#
ꢏꢙ5
56ꢏ
ꢏꢔ7
5$ꢄ8ꢅꢍꢈꢇ%ꢈ1ꢃꢆ
1ꢃ#ꢊꢌ
5
ꢅ
ꢀꢖ
ꢐꢁ9(ꢈ)ꢕ*
6,ꢅꢍꢉꢋꢋꢈ:ꢅꢃꢓꢌ#
ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈꢗꢌꢃꢊ/ꢆꢅ
ꢕ#ꢉꢆ!ꢇ%%ꢈ
6,ꢅꢍꢉꢋꢋꢈ=ꢃ!#ꢌ
ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈ=ꢃ!#ꢌ
ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈ4ꢅꢆꢓ#ꢌ
.ꢇꢇ#ꢈ4ꢅꢆꢓ#ꢌ
ꢔ
M
ꢐꢁ;ꢐ
ꢐꢁꢐ(
M
ꢀꢁꢐꢐ
M
9ꢁꢖꢐꢈ)ꢕ*
ꢖꢁꢖꢐ
(ꢁꢐꢐ
ꢐꢁ9ꢐ
ꢀꢁꢑꢐ
ꢀꢁꢐ(
ꢐꢁꢀ(
ꢔꢑ
ꢔꢀ
"
"ꢀ
ꢂ
ꢖꢁꢛꢐ
ꢖꢁꢝꢐ
ꢐꢁꢖ(
ꢖꢁ(ꢐ
(ꢁꢀꢐ
ꢐꢁꢒ(
4
.ꢇꢇ#ꢎꢍꢃꢆ#
.ꢇꢇ#ꢈꢔꢆꢓꢋꢅ
4ꢅꢉ!ꢈꢗꢌꢃꢊ/ꢆꢅ
4ꢅꢉ!ꢈ=ꢃ!#ꢌ
4ꢀ
ꢀ
ꢀꢁꢐꢐꢈꢚ".
ꢐꢞ
ꢐꢁꢐꢝ
ꢐꢁꢀꢝ
M
M
M
;ꢞ
ꢊ
8
ꢐꢁꢑꢐ
ꢐꢁꢛꢐ
ꢜꢔꢊꢃꢉꢝ
ꢀꢁ 1ꢃꢆꢈꢀꢈ,ꢃ $ꢉꢋꢈꢃꢆ!ꢅ&ꢈ%ꢅꢉ#$ꢍꢅꢈꢄꢉꢘꢈ,ꢉꢍꢘ0ꢈ8$#ꢈꢄ$ #ꢈ8ꢅꢈꢋꢇꢊꢉ#ꢅ!ꢈ-ꢃ#ꢌꢃꢆꢈ#ꢌꢅꢈꢌꢉ#ꢊꢌꢅ!ꢈꢉꢍꢅꢉꢁ
ꢑꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀ(ꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ
ꢛꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢚ".+ ꢚꢅ%ꢅꢍꢅꢆꢊꢅꢈꢂꢃꢄꢅꢆ ꢃꢇꢆ0ꢈ$ $ꢉꢋꢋꢘꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ0ꢈ%ꢇꢍꢈꢃꢆ%ꢇꢍꢄꢉ#ꢃꢇꢆꢈꢎ$ꢍꢎꢇ ꢅ ꢈꢇꢆꢋꢘꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢜꢐ;ꢒ)
DS21881E-page 34
© 2009 Microchip Technology Inc.
MCP6231/2/4
Revision C (March 2005)
APPENDIX A: REVISION HISTORY
Revision E (August 2009)
The following is the list of modifications:
1. Added the MCP6234 quad op amp.
The following is the list of modifications:
2. Corrected plots in Section 2.0 “Typical
Performance Curves”.
1. Added the 2x3 TDFN package for MCP6232.
3. Added Section 3.0 “Pin Descriptions”.
2. Updated the 2x3 DFN package information for
MCP6231.
4. Added new SC-70 package markings. Added
PDIP-14, SOIC-14, and TSSOP-14 packages
and corrected package marking information
(Section 6.0 “Packaging Information”).
3. Updated the “Temperature Characteristics”
table.
4. Updated Section 3.0 “Pin Descriptions”.
5. Added Appendix A: “Revision History”.
5. Updated the Package Outline Drawings in
Section 6.0 “Packaging Information”.
Revision B (August 2004)
6. Updated the Product Identification Systems
section.
• Undocumented changes.
Revision D (May 2008)
Revision A (March 2004)
The following is the list of modifications:
• Original Release of this Document.
1. Changed Heading “Available Tools” to “Design
Aids”.
2. Design Aids: Name change for Mindi Simulator
Tool.
3. Package Types: Added DFN to MCP6231
Device.
4. Absolute Maximum Ratings: Numerous
changes in this section.
5. Updated notes to Section 1.0 “Electrical
Characteristics”.
6. Added Test Circuits to Section 1.0 “Electrical
Characteristics”.
7. Corrected Figure 2-7.
8. Added Figure 2-19.
9. Numerous changes to Section 3.0 “Pin
Descriptions”.
10. Added Section 4.1.1 “Phase Reversal”,
Section 4.1.2 “Input Voltage and Current
Limits”,
and
Section 4.1.3
“Normal
Operation”.
11. Replaced Section 5.0 “Design Aids” with
additional information.
12. Updated
Section 6.0
“Packaging
Information” with updated Package Outline
Drawings.
© 2009 Microchip Technology Inc.
DS21881E-page 35
MCP6231/2/4
NOTES:
DS21881E-page 36
© 2009 Microchip Technology Inc.
MCP6231/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
-X
/XX
a) MCP6231-E/MC:
Extended Temperature
8LD DFN package.
Tape and Reel
and/or
Alternate Pinout
Temperature Package
Range
b) MCP6231-E/MS:
Extended Temperature
8LD MSOP package.
c) MCP6231UT-E/LT: Tape and Reel,
Extended Temperature
Device:
MCP6231:
MCP6231T:
Single Op Amp (MSOP, PDIP, SOIC)
Single Op Amp (Tape and Reel)
(MSOP, SOIC, SOT-23)
Single Op Amp (Tape and Reel)
(SOT-23)
5LD SC70 package.
Extended Temperature
8LD PDIP package.
MCP6231RT:
d) MCP6231-E/P:
MCP6231UT: Single Op Amp (Tape and Reel)
(SC70, SOT-23, TDFN)
MCP6232:
e) MCP6231RT-E/OT: Tape and Reel,
Extended Temperature
5LD SOT-23 package
f) MCP6231UT-E/OT: Tape and Reel,
Dual Op Amp
Dual Op Amp (Tape and Reel)
(MSOP, SOIC)
MCP6232T:
MCP6234:
Quad Op Amp
MCP6234T:
Quad Op Amp (Tape and Reel)
(TSSOP, SOIC)
Extended Temperature
5LD SOT-23.
g) MCP6231-E/SN:
Extended Temperature
8LD SOIC package.
Temperature Range:
Package:
E
=
-40° C to +125° C
a) MCP6232-E/SN:
b) MCP6232-E/MS:
c) MCP6232-E/P:
Extended Temperature
8LD SOIC package.
Extended Temperature
8LD MSOP package.
Extended Temperature
8LD PDIP package.
LT
MC
=
=
Plastic Package (SC70), 5-lead (MCP6231U only)
Plastic Dual Flat No-Lead (DFN) 2x3, 8-lead
(MCP6231 only)
MNY= Plastic Dual Flat No-Lead (TDFN) 2x3, 8-lead
(MCP6232 only)
MS
P
=
=
=
Plastic Micro Small Outline (MSOP), 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6231, MCP6231R, MCP6231U)
Plastic SOIC (150 mil Body), 8-lead
OT
d) MCP6232T-E/SN: Tape and Reel,
Extended Temperature
8LD SOIC package.
e) MCP6232T-E/MNY: Tape and Reel,
Extended Temperature
SN
SL
ST
=
=
=
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP (4.4 mil Body), 14-lead
8LD TDFN package.
a) MCP6234-E/P:
b) MCP6234-E/SL:
c) MCP6234-E/ST:
Extended Temperature
14LD PDIP package.
Extended Temperature
14LD SOIC package.
Extended Temperature,
14LD TSSOP package
d) MCP6234T-E/SL: Tape and Reel,
Extended Temperature
14LD SOIC package.
e) MCP6234T-E/ST: Tape and Reel,
Extended Temperature
14LD TSSOP package.
© 2009 Microchip Technology Inc.
DS21881E-page 37
MCP6231/2/4
NOTES:
DS21881E-page 38
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS21881E-page 39
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
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Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
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China - Chengdu
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China - Hong Kong SAR
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Fax: 852-2401-3431
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
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Tel: 630-285-0071
Fax: 630-285-0075
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Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
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Fax: 86-25-8473-2470
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Cleveland
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Fax: 216-447-0643
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Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
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Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
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Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
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Fax: 63-2-634-9069
Detroit
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Fax: 86-24-2334-2393
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Fax: 65-6334-8850
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
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Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
03/26/09
DS21881E-page 40
© 2009 Microchip Technology Inc.
相关型号：
MCP624-E/SL
QUAD OP-AMP, 200 uV OFFSET-MAX, 20 MHz BAND WIDTH, PDSO14, 3.90 MM, LEAD FREE, PLASTIC, SOIC-14
MICROCHIP
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