MCP6024T_技术文档

MCP6021/1R/2/3/4

Rail-to-Rail Input/Output, 10 MHz Op Amps

Description

Features

• Rail-to-Rail Input/Output

The MCP6021, MCP6021R, MCP6022, MCP6023 and

MCP6024 from Microchip Technology Inc. are rail-to-

rail input and output op amps with high performance.

Key specifications include: wide bandwidth (10 MHz),

low noise (8.7 nV/√Hz), low input offset voltage and low

distortion (0.00053% THD+N). The MCP6023 also

offers a Chip Select pin (CS) that gives power savings

when the part is not in use.

• Wide Bandwidth: 10 MHz (typical)

• Low Noise: 8.7 nV/√Hz, at 10 kHz (typical)

• Low Offset Voltage:

- Industrial Temperature: ±500 µV (maximum)

- Extended Temperature: ±250 µV (maximum)

• Mid-Supply V_REF: MCP6021 and MCP6023

• Low Supply Current: 1 mA (typical)

• Total Harmonic Distortion:

The single MCP6021 and MCP6021R are available in

SOT-23-5. The single MCP6021, single MCP6023 and

dual MCP6022 are available in 8-lead PDIP, SOIC and

TSSOP. The Extended Temperature single MCP6021

is available in 8-lead MSOP. The quad MCP6024 is

offered in 14-lead PDIP, SOIC and TSSOP packages.

-

0.00053% (typical, G = 1 V/V)

• Unity Gain Stable

• Power Supply Range: 2.5V to 5.5V

• Temperature Range:

The MCP6021/1R/2/3/4 family is available in Industrial

and Extended temperature ranges. It has a power

supply range of 2.5V to 5.5V.

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Applications

Package Types

• Automotive

MCP6021

SOT-23-5

MCP6022

PDIP SOIC, TSSOP

• Multi-Pole Active Filters

• Audio Processing

• DAC Buffer

V_OUTA

V_DD

V_OUT

V_SS

1

2

3

4

8

7

6

5

1

5

4

V_INA

V_SS

–

V_OUTB

2

3

• Test Equipment

• Medical Instrumentation

+

V_INB

–

+

V_IN

+

V_IN–

MCP6021R

SOT-23-5

Design Aids

MCP6023

PDIP SOIC, TSSOP

• SPICE Macro Models

• FilterLab^®Software

V_OUT

V_DD

1

2

3

V_SS

5

4

NC

1

2

3

4

8 CS

• Mindi™ Circuit Designer & Simulator

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

V_IN

–

+

V_DD

V_IN

+

7

6

5

V_IN–

V_IN

V_OUT

V_REF

MCP6021

PDIP SOIC,

MSOP, TSSOP

V_SS

MCP6024

PDIP SOIC, TSSOP

Typical Application

5.6 pF

Photo

Detector

NC

1

2

3

4

8

7

6

5

V_OUTA

V

1

2

3

4

5

6

7

14

13

12

11

10

9

OUTD

V_DD

V_IN

–

+

V_INA

–

+

–

100 kΩ

IND

V_OUT

V_REF

V_IN

V_INA

+

IND

V_SS

100 pF

V_DD

V_SS

V_INB

+

–

V

+

–

INC

MCP6021

V_DD/2

V_INB

V_INC

V_OUTB

V_OUTC

8

Transimpedance Amplifier

DS21685D-page 1

MCP6021/1R/2/3/4

NOTES:

DS21685D-page 2

MCP6021/1R/2/3/4

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational listings of this specification is not

implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

V_DD– V_SS........................................................................7.0V

Current at Analog Input Pins (V_IN+, V_IN–).....................±2 mA

Analog Inputs (V_IN+, V_IN–) ††........ V_SS– 1.0V to V_DD+ 1.0V

All Other Inputs and Outputs ......... V_SS– 0.3V to V_DD+ 0.3V

†† See Section 4.1.2 “ Input Voltage and Current Limits”.

Difference Input Voltage ...................................... |V_DD– V_SS

|

Output Short Circuit Current ................................Continuous

Current at Output and Supply Pins ............................±30 mA

Storage Temperature .................................–65° C to +150° C

Maximum Junction Temperature (T_J).........................+150° C

ESD Protection On All Pins (HBM; MM) .............. ≥ 2 kV; 200V

DC ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2,

V_OUT≈ V_DD/2 and R_L= 10 kΩ to V_DD/2.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Input Offset

Input Offset Voltage:

Industrial Temperature Parts

Extended Temperature Parts

V_OS

-500

-250

-2.5

—

+500

+250

+2.5

µV

V_CM= 0V

V_CM= 0V, V_DD= 5.0V

mV

V_CM= 0V, V_DD= 5.0V

T_A= -40°C to +125°C

Input Offset Voltage Temperature Drift ΔV_OS/ΔT_A

—

±3.5

90

—

µV/°C T_A= -40°C to +125°C

Power Supply Rejection Ratio

Input Current and Impedance

Input Bias Current

PSRR

74

dB

V_CM= 0V

I_B

—

1

30

—

150

5,000

—

pA

Industrial Temperature Parts

Extended Temperature Parts

Input Offset Current

T_A= +85°C

I_B

640

pA

T_A= +125°C

I_OS

Z_CM

Z_DIFF

±1

pA

Common-Mode Input Impedance

Differential Input Impedance

Common-Mode

10¹³||6

10¹³||3

—

Ω||pF

—

Common-Mode Input Range

Common-Mode Rejection Ratio

V_CMR

CMRR

V_SS-0.3

74

—

90

85

90

V_DD+0.3

V

—

dB

V_DD= 5V, V_CM= -0.3V to 5.3V

V_DD= 5V, V_CM= 3.0V to 5.3V

V_DD= 5V, V_CM= -0.3V to 3.0V

70

74

Voltage Reference (MCP6021 and MCP6023 only)

V_REFAccuracy (V_REF– V_DD/2)

V_REFTemperature Drift

V_{REF_ACC}

ΔV_REF/ΔT

A

-50

—

+50

—

mV

±100

µV/°C T_A= -40°C to +125°C

Open-Loop Gain

DC Open-Loop Gain (Large Signal)

A_OL

90

110

—

dB

V_CM= 0V,

_OUT= V_SS+0.3V to V_DD-0.3V

V

Output

Maximum Output Voltage Swing

Output Short Circuit Current

V_OL, V_OH

I_SC

V_SS+15

—

V_DD-20

—

mV

mA

0.5V input overdrive

V_DD= 2.5V

±30

±22

I_SC

—

V_DD= 5.5V

DS21685D-page 3

MCP6021/1R/2/3/4

AC ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2,

V_OUT≈ V_DD/2, R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

Parameters

Power Supply

Sym

Min

Typ

Max

Units

Conditions

Supply Voltage

V_DD

I_Q

2.5

0.5

—

5.5

V

Quiescent Current per Amplifier

AC Response

1.0

1.35

mA

I_O= 0

Gain Bandwidth Product

Phase Margin

GBWP

PM

—

10

65

—

MHz

°

G = +1 V/V

Settling Time, 0.2%

Slew Rate

t_SETTLE

SR

250

7.0

ns

G = +1 V/V, V_OUT= 100 mV_p-p

V/µs

Total Harmonic Distortion Plus Noise

f = 1 kHz, G = +1 V/V

THD+N

—

0.00053

0.00064

—

%

V_OUT= 0.25V to 3.25V (1.75V ± 1.50V_PK),

V

_DD= 5.0V, BW = 22 kHz

V_OUT= 0.25V to 3.25V (1.75V ± 1.50V_PK),

_DD= 5.0V, BW = 22 kHz

f = 1 kHz, G = +1 V/V, R_L= 600Ω

THD+N

V

f = 1 kHz, G = +1 V/V

f = 1 kHz, G = +10 V/V

f = 1 kHz, G = +100 V/V

Noise

THD+N

—

0.0014

0.0009

0.005

—

%

V_OUT= 4V_P-P, V_DD= 5.0V, BW = 22 kHz

Input Noise Voltage

Input Noise Voltage Density

Input Noise Current Density

E_ni

e_ni

i_ni

—

2.9

8.7

3

—

µVp-p f = 0.1 Hz to 10 Hz

nV/√Hz f = 10 kHz

fA/√Hz f = 1 kHz

MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2,

V_OUT≈ V_DD/2, R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

Parameters

CS Low Specifications

Sym

Min

Typ

Max

Units

Conditions

CS Logic Threshold, Low

CS Input Current, Low

V_IL

V_SS

-1.0

—

0.2 V_DD

—

V

I_CSL

0.01

µA CS = V_SS

CS High Specifications

CS Logic Threshold, High

CS Input Current, High

V_IH

I_CSH

0.8 V_DD

—

V_DD

2.0

—

V

—

-2

—

0.01

-0.05

0.01

µA CS = V_DD

GND Current

I_SS

Amplifier Output Leakage

CS Dynamic Specifications

CS Low to Amplifier Output Turn-on Time

I_O(LEAK)

—

t_ON

t_OFF

—

2

10

—

µs

G = +1, V_IN= V_SS

CS = 0.2V_DDto V_OUT= 0.45V_DDtime

,

CS High to Amplifier Output High-Z Time

Hysteresis

0.01

0.6

µs

V

G = +1, V_IN= V_SS,

CS = 0.8V_DDto V_OUT= 0.05V_DDtime

V_HYST

V_DD= 5.0V, Internal Switch

DS21685D-page 4

MCP6021/1R/2/3/4

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.5V to +5.5V and V_SS= GND.

Parameters

Temperature Ranges

Sym

Min

Typ

Max

Units

Conditions

Industrial Temperature Range

Extended Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 5L-SOT-23

Thermal Resistance, 8L-PDIP

Thermal Resistance, 8L-SOIC

Thermal Resistance, 8L-MSOP

Thermal Resistance, 8L-TSSOP

Thermal Resistance, 14L-PDIP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 14L-TSSOP

T_A

-40

-65

—

+85

°C

+125

+150

Note 1

θ_JA

—

256

85

—

°C/W

163

206

124

70

120

100

Note 1: The industrial temperature devices operate over this extended temperature range, but with reduced performance. In any

case, the internal junction temperature (T_J) must not exceed the absolute maximum specification of 150°C.

1.1

Test Circuits

CS

The test circuits used for the DC and AC tests are

shown in Figure 1-2 and Figure 1-3. The bypass

capacitors are laid out according to the rules discussed

in Section 4.7 “Supply Bypass”.

t_ON

t_OFF

High-Z

Amplifier On

High-Z

V_OUT

-1 mA

(typical)

V_DD

1 µF

0.1 µF

C_B1C_B2

R_N

I_SS

I_CS

-50 nA

(typical)

-50 nA

(typical)

V_IN

V_OUT

1 kΩ

MCP6021

10 nA

(typical)

C_L

60 pF

R_L

10 kΩ

(typical)

R_G

R_F

V_DD/2

FIGURE 1-1:

pin on the MCP6023.

Timing diagram for the CS

V_L

2 kΩ

FIGURE 1-2:

AC and DC Test Circuit for

Most Non-Inverting Gain Conditions.

V_DD

1 µF

0.1 µF

C_B1C_B2

R_N

V_DD/2

V_OUT

1 kΩ

MCP6021

C_L

60 pF

R_L

10 kΩ

R_G

R_F

V_IN

V_L

2 kΩ

FIGURE 1-3:

AC and DC Test Circuit for

Most Inverting Gain Conditions.

DS21685D-page 5

MCP6021/1R/2/3/4

NOTES:

DS21685D-page 6

MCP6021/1R/2/3/4

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

16%

14%

12%

10%

8%

24%

22%

20%

18%

16%

14%

12%

10%

8%

I-Temp

Parts

1192 Samples

_CM= 0V

T_A= +25°C

I-Temp

Parts

1192 Samples

_CM= 0V

_A= -40°C to +85°C

V

T

6%

4%

6%

4%

2%

0%

Input Offset Voltage (µV)

Input Offset Voltage Drift (µV/°C)

FIGURE 2-1:

Input Offset Voltage,

FIGURE 2-4:

Input Offset Voltage Drift,

(Industrial Temperature Parts).

24%

E-Temp

22%

438 Samples

E-Temp

Parts

438 Samples

V_CM= 0V

T_A= -40°C to +125°C

22%

20%

18%

16%

14%

12%

10%

8%

6%

4%

2%

0%

Parts

V_DD= 5.0V

20%

V_CM= 0V

18%

16%

14%

12%

10%

8%

6%

4%

2%

0%

T_A= +25°C

Input Offset Voltage (µV)

Input Offset Voltage Drift (µV/°C)

FIGURE 2-2:

Input Offset Voltage,

FIGURE 2-5:

Input Offset Voltage Drift,

(Extended Temperature Parts).

500

-40°C

V_DD= 5.5V

V_DD= 2.5V

400

+25°C

+85°C

+125°C

-40°C

300

200

100

0

300

200

100

0

+25°C

+85°C

+125°C

-100

-200

-300

-400

-500

-100

-200

-300

-400

-500

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Common Mode Input Voltage (V)

FIGURE 2-3:

Input Offset Voltage vs.

FIGURE 2-6:

Input Offset Voltage vs.

Common Mode Input Voltage with V = 2.5V.

Common Mode Input Voltage with V = 5.5V.

DD

DS21685D-page 7

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

100

50

200

150

100

50

V_CM= V_DD/2

0

V_DD= 5.5V

-50

0

-100

-150

-200

-250

-300

V_DD= 2.5V

-50

-100

-150

-200

V_DD= 5.0V

V_CM= 0V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 2-7:

Input Offset Voltage vs.

FIGURE 2-10:

Input Offset Voltage vs.

Temperature.

Output Voltage.

1,000

100

10

24

V_DD= 5.0V

22

20

18

16

14

12

10

8

f = 1 kHz

f = 10 kHz

6

4

2

0

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1

0.1

1

10

100

1k

10k 100k 1M

Frequency (Hz)

Common Mode Input Voltage (V)

FIGURE 2-8:

Input Noise Voltage Density

FIGURE 2-11:

Input Noise Voltage Density

vs. Frequency.

vs. Common Mode Input Voltage.

100

90

80

70

60

50

40

30

110

105

PSRR+

PSRR-

CMRR

100

95

90

85

80

75

70

PSRR (V_CM= 0V)

CMRR

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

20

100

1k

10k

100k

1M

-50

-25

0

25

50

75

100

125

Frequency (Hz)

Ambient Temperature (°C)

FIGURE 2-9:

CMRR, PSRR vs.

FIGURE 2-12:

CMRR, PSRR vs.

Frequency.

Temperature.

DS21685D-page 8

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

10,000

I_B, T_A= +125°C

V_DD= 5.5V

V_CM= V_DD

V_DD= 5.5V

1,000

100

10

1,000

100

10

I_OS, T_A= +125°C

I_B, T_A= +85°C

I_B

I_OS

I_OS, T_A= +85°C

1

25 35 45 55 65 75 85 95 105 115 125

Ambient Temperature (°C)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

FIGURE 2-16:

Input Bias, Offset Currents

FIGURE 2-13:

Input Bias, Offset Currents

vs. Temperature.

vs. Common Mode Input Voltage.

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

1.2

1.1

V_DD= 5.5V

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V_DD= 2.5V

+125°C

+85°C

+25°C

-40°C

V_CM= V_DD- 0.5V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

-50

-25

0

25

50

75

100 125

Ambient Temperature (°C)

FIGURE 2-17:

Temperature.

Quiescent Current vs.

FIGURE 2-14:

Supply Voltage.

Quiescent Current vs.

35

30

25

20

15

10

5

120

110

100

90

80

70

60

50

40

30

20

10

0

-15

-30

-45

-60

-75

-90

Phase

-105

-120

-135

-150

-165

-180

-195

-210

+125°C

+85°C

+25°C

-40°C

Gain

-10

-20

0

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1

10 100 1k 10k 100k 1M 10M 100M

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Supply Voltage (V)

Frequency (Hz)

FIGURE 2-18:

Frequency.

Open-Loop Gain, Phase vs.

FIGURE 2-15:

vs. Supply Voltage.

Output Short-Circuit Current

DS21685D-page 9

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

130

120

110

100

90

120

115

110

105

100

95

V_DD= 5.5V

V_DD= 2.5V

90

1.E+02

1.E+03

1.E+04

1.E+05

80

-50

-25

0

25

50

75

100

125

100

1k

10k

100k

Load Resistance (Ω)

Ambient Temperature (°C)

FIGURE 2-19:

DC Open-Loop Gain vs.

FIGURE 2-22:

DC Open-Loop Gain vs.

Load Resistance.

Temperature.

120

14

105

90

V_CM= V_DD/2

110

Gain Bandwidth Product

12

10

8

V_DD= 5.5V

75

100

90

60

Phase Margin, G = +1

45

6

V_DD= 2.5V

80

4

30

15

0

2

70

V_DD= 5.0V

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Common Mode Input Voltage (V)

Output Voltage Headroom (V);

V_DD- V_OHor V_OL- V_SS

FIGURE 2-20:

Small Signal DC Open-Loop

FIGURE 2-23:

Gain Bandwidth Product,

Gain vs. Output Voltage Headroom.

Phase Margin vs. Common Mode Input Voltage.

10

9

100

90

80

70

60

50

40

30

20

10

0

14

12

10

8

105

90

75

60

45

30

15

0

Gain Bandwidth Product

8

7

6

Phase Margin, G = +1

5

4

3

2

1

0

GBWP, V_DD= 5.5V

GBWP, V_DD= 2.5V

6

PM,

V

_DD= 2.5V

4

V_DD= 5.5V

V_DD= 5.0V

_CM= V_DD/2

2

V

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Output Voltage (V)

-50 -25

0

25

50

75 100 125

Ambient Temperature (°C)

FIGURE 2-21:

Gain Bandwidth Product,

FIGURE 2-24:

Gain Bandwidth Product,

Phase Margin vs. Temperature.

Phase Margin vs. Output Voltage.

DS21685D-page 10

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

10

11

10

9

Falling, V_DD= 5.5V

Rising, V_DD= 5.5V

V_DD= 5.5V

V_DD= 2.5V

8

7

6

5

4

3

1

Falling, V_DD= 2.5V

Rising, V_DD= 2.5V

2

1

0

1.E+04

1.E+05

1.E+06

1.E+07

0.1

-50

-25

0

25

50

75

100

125

10k

100k

Frequency (Hz)

1M

10M

Ambient Temperature (°C)

FIGURE 2-25:

Slew Rate vs. Temperature.

FIGURE 2-28:

Maximum Output Voltage

Swing vs. Frequency.

0.1000%

0.0100%

0.1000%

f = 1 kHz

BW_Meas= 22 kHz

V_DD= 5.0V

G = +100 V/V

G = +10 V/V

G = +1 V/V

G = +100 V/V

0.0100%

0.0010%

0.0001%

G = +10 V/V

0.0010%

0.0001%

f = 20 kHz

BW_Meas= 80 kHz

V_DD= 5.0V

G = +1 V/V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Output Voltage (V_P-P

)

FIGURE 2-26:

Total Harmonic Distortion

FIGURE 2-29:

Total Harmonic Distortion

plus Noise vs. Output Voltage with f = 1 kHz.

plus Noise vs. Output Voltage with f = 20 kHz.

135

130

125

120

115

6

V_DD= 5.0V

G = +2 V/V

5

V_OUT

4

V_IN

3

2

1

0

110

G = +1 V/V

-1

1.E+03

1.E+04

1.E+05

1.E+06

105

0

10 20 30 40 50 60 70 80 90 100

Time (10 µs/div)

1k

10k

100k

1M

Frequency (Hz)

FIGURE 2-27:

The MCP6021/1R/2/3/4

FIGURE 2-30:

Channel-to-Channel

family shows no phase reversal under overdrive.

Separation vs. Frequency (MCP6022 and

MCP6024 only).

DS21685D-page 11

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

1,000

100

10

9

8

7

6

5

4

3

2

1

0

V_OL- V_SS

V_DD- V_OH

V_OL- V_SS

V_DD- V_OH

1

-50

-25

0

25

50

75

100 125

0.01

0.1

1

10

Output Current Magnitude (mA)

Ambient Temperature (°C)

FIGURE 2-31:

Output Voltage Headroom

FIGURE 2-34:

Output Voltage Headroom

vs. Output Current.

vs. Temperature.

6.E-02

5.E-02

4.E-02

3.E-02

2.E-02

1.E-02

0.E+00

-1.E-02

-2.E-02

-3.E-02

-4.E-02

-5.E-02

-6.E-02

6.E-02

5.E-02

4.E-02

3.E-02

2.E-02

1.E-02

0.E+00

-1.E-02

-2.E-02

-3.E-02

-4.E-02

-5.E-02

-6.E-02

G = -1 V/V

R_F= 1 kΩ

G = +1 V/V

0.E+00

2.E-07

4.E-07

6.E-07

8.E-07

1.E-06

2.E-06

0.E+00

2.E-07

4.E-07

6.E-07

8.E-07

1.E-06

2.E-06

Time (200 ns/div)

FIGURE 2-32:

Small-Signal Non-inverting

FIGURE 2-35:

Small-Signal Inverting Pulse

Pulse Response.

Response.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

G = +1 V/V

G = -1 V/V

R_F= 1 kΩ

0.E+00

5.E-07

1.E-06

2.E-06

3.E-06

4.E-06

5.E-06

0.E+00

5.E-07

1.E-06

2.E-06

3.E-06

4.E-06

5.E-06

0.0

Time (500 ns/div)

FIGURE 2-33:

Large-Signal Non-inverting

FIGURE 2-36:

Large-Signal Inverting Pulse

Pulse Response.

Response.

DS21685D-page 12

MCP6021/1R/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

50

40

50

40

Representative Part

30

20

V_DD= 5.5V

V_DD= 2.5V

10

0

-10

-20

-30

-40

-50

-10

-20

-30

-40

-50

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

-50

-25

0

25

50

75

100 125

Ambient Temperature (°C)

FIGURE 2-37:

V

Accuracy vs. Supply

FIGURE 2-40:

V

Accuracy vs.

REF

Voltage (MCP6021 and MCP6023 only).

Temperature (MCP6021 and MCP6023 only).

1.6

Op Amp

turns on here

Op Amp

shuts off here

Op Amp

turns on here

Op Amp

shuts off here

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Hysteresis

CS swept

high to low

CS swept

high to low

Hysteresis

CS swept

low to high

CS swept

low to high

V_DD= 5.5V

G = +1 V/V

V_IN= 2.75V

V_DD= 2.5V

G = +1 V/V

V_IN= 1.25V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Chip Select Voltage (V)

0.0

0.5

1.0

1.5

2.0

2.5

Chip Select Voltage (V)

FIGURE 2-38:

Chip Select (CS) Hysteresis

FIGURE 2-41:

Chip Select (CS) Hysteresis

(MCP6023 only) with V = 2.5V.

(MCP6023 only) with V = 5.5V.

DD

5.5

5.0

4.5

4.0

3.5

1.E-02

10m

1.E-03

1m

1.E- 4

100µ

1.E1-05µ

V_DD= 5.0V

G = +1 V/V

V_IN= V_SS

CS Voltage

1.E-06

1µ

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

V_OUT

100n

1.E- 7

10n

1.E- 8

1n

1.E-09

100p

1.E-10

10p

1.E-11

1p

1.E-12

+125°C

+85°C

+25°C

-40°C

Output

on

Output

on

Output High-Z

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

0.0E+00

5.0E-06

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

3.5E-05

Time (5 µs/div)

FIGURE 2-39:

Chip Select (CS) to

FIGURE 2-42:

Measured Input Current vs.

Amplifier Output Response Time (MCP6023

only).

Input Voltage (below V ).

SS

DS21685D-page 13

MCP6021/1R/2/3/4

NOTES:

DS21685D-page 14

MCP6021/1R/2/3/4

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

MCP6021

PIN FUNCTION TABLE

MCP6021R MCP6022 MCP6023 MCP6024

Symbol

Description

PDIP,

SOIC,

SOT-23-5

(Note 2)

PDIP,

SOIC,

PDIP,

SOIC,

PDIP,

SOIC,

MSOP,

TSSOP

(Note 1)

TSSOP

6

2

1

2

6

2

1

2

V_OUT, V_OUTAAnalog Output (op amp A)

4

V_IN–, V_INA

V_IN+, V_INA

V_DD

–

Inverting Input (op amp A)

Non-inverting Input (op amp A)

Positive Power Supply

3

+

7

5

2

8

7

4

—

4

—

2

—

5

—

4

5

V_INB

+

–

Non-inverting Input (op amp B)

Inverting Input (op amp B)

Analog Output (op amp B)

Analog Output (op amp C)

Inverting Input (op amp C)

Non-inverting Input (op amp C)

Negative Power Supply

6

V_INB

7

V_OUTB

V_OUTC

—

4

8

9

V_INC

–

+

10

11

12

13

14

—

V_INC

V_SS

—

5

—

5

V_IND

+

Non-inverting Input (op amp D)

Inverting Input (op amp D)

Analog Output (op amp D)

Reference Voltage

V_IND

–

V_OUTD

V_REF

—

1, 8

—

8

1

—

CS

NC

Chip Select

No Internal Connection

Note 1:

The MCP6021 in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts.

2: The MCP6021R is only available in the 5-pin SOT-23 package, and for E-temp (Extended Temperature) parts.

3.1

Analog Outputs

3.4

Chip Select Digital Input (CS)

The op amp output pins are low-impedance voltage

sources.

This is a CMOS, Schmitt-triggered input that places the

part into a low power mode of operation.

3.2

Analog Inputs

3.5

Power Supply (V_SSand V_DD)

The op amp non-inverting and inverting inputs are high-

impedance CMOS inputs with low bias currents.

The positive power supply pin (V_DD) is 2.5V to 6.0V

higher than the negative power supply pin (V_SS). For

normal operation, the other pins are at voltages

between V_SSand V_DD

.

3.3

Reference Voltage (V_REF,

MCP6021 and MCP6023

)

Typically, these parts are used in a single (positive)

supply configuration. In this case, V_SSis connected to

ground and V_DDis connected to the supply. V_DDwill

need a bypass capacitor.

Mid-supply reference voltage provided by the single op

amps (except in SOT-23-5 package). This is an

unbuffered, resistor voltage divider internal to the part.

DS21685D-page 15

MCP6021/1R/2/3/4

NOTES:

DS21685D-page 16

MCP6021/1R/2/3/4

4.0

APPLICATIONS INFORMATION

V_DD

The MCP6021/1R/2/3/4 family of operational amplifiers

are fabricated on Microchip’s state-of-the-art CMOS

process. They are unity-gain stable and suitable for a

wide range of general-purpose applications.

D₁D₂

V₁

R₁

R₂

MCP602X

4.1

Rail-to-Rail Input

V₂

4.1.1

PHASE REVERSAL

The MCP6021/1R/2/3/4 op amp is designed to prevent

phase reversal when the input pins exceed the supply

voltages. Figure 2-42 shows the input voltage exceed-

ing the supply voltage without any phase reversal.

R₃

V_SS– (minimum expected V₁)

R₁>

R₂>

2 mA

V_SS– (minimum expected V₂)

2 mA

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

The ESD protection on the inputs can be depicted as

shown in Figure 4-1. This structure was chosen to

protect the input transistors, and to minimize input bias

current (I_B). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

V_SS. They also clamp any voltages that go too far

above V_DD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass

quick ESD events within the specified limits.

FIGURE 4-2:

Inputs.

Protecting the Analog

It is also possible to connect the diodes to the left of

resistors R₁and R₂. In this case, current through the

diodes D₁and D₂needs to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (V_IN+ and

V_IN–) should be very small.

A significant amount of current can flow out of the

inputs when the common mode voltage (V_CM) is below

ground (V_SS); see Figure 2-42. Applications that are

high impedance may need to limit the useable voltage

range.

Bond

V_DD

Pad

Bond

Pad

Bond

Pad

Input

Stage

4.1.3

NORMAL OPERATION

V_IN+

V_IN–

The input stage of the MCP6021/1R/2/3/4 op amps use

two differential CMOS input stages in parallel. One

operates at low common mode input voltage (V_CM),

while the other operates at high V_CM. WIth this topol-

ogy, the device operates with Vcm up to 0.3V above

Bond

Pad

V_SS

V_DDand 0.3V below V_SS

.

FIGURE 4-1:

Simplified Analog Input ESD

Structures.

4.2

Rail-to-Rail Output

In order to prevent damage and/or improper operation

of these op amps, the circuit they are in must limit the

currents and voltages at the V_IN+ and V_IN– pins (see

Absolute Maximum Ratings † at the beginning of

Section 1.0 “Electrical Characteristics”). Figure 4-2

shows the recommended approach to protecting these

inputs. The internal ESD diodes prevent the input pins

(V_IN+ and V_IN–) from going too far below ground, and

the resistors R₁and R₂limit the possible current drawn

out of the input pins. Diodes D₁and D₂prevent the

input pins (V_IN+ and V_IN–) from going too far above

V_DD, and dump any currents onto V_DD. When

implemented as shown, resistors R₁and R₂also limit

the current through D₁and D₂.

The Maximum Output Voltage Swing is the maximum

swing possible under particular output load.

According to the specification table, the output can

reach within 20 mV of either supply rail when

R_L= 10 kΩ. See Figure 2-31 and Figure 2-34 for more

information concerning typical performance.

a

4.3

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases, and the closed loop bandwidth is

reduced. This produces gain-peaking in the frequency

response, with overshoot and ringing in the step

response.

DS21685D-page 17

MCP6021/1R/2/3/4

When driving large capacitive loads with these op

amps (e.g., > 60 pF when G = +1), a small series

resistor at the output (R_ISOin Figure 4-3) improves the

feedback loop’s phase margin (stability) by making the

load resistive at higher frequencies. The bandwidth will

be generally lower than the bandwidth with no

capacitive load.

1 V/V (unity gain). C_Galso reduces the phase margin

of the feedback loop for both non-inverting and

inverting gains.

V_IN

V_OUT

V_IN

R_ISO

R_F

C_G

R_G

V_OUT

C_L

MCP602X

FIGURE 4-5:

Non-inverting Gain Circuit

with Parasitic Capacitance.

FIGURE 4-3:

Output Resistor R

ISO

Stabilizes Large Capacitive Loads.

The largest value of R_Fin Figure 4-5 that should be

used is a function of noise gain (see G_Nin Section 4.3

“Capacitive Loads”) and C_G. Figure 4-6 shows results

for various conditions. Other compensation techniques

may be used, but they tend to be more complicated to

the design.

Figure 4-4 gives recommended R_ISOvalues for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (C_L/G_N), where G_Nis the

circuit’s noise gain. For non-inverting gains, G_Nand the

Signal Gain are equal. For inverting gains, G_Nis

1+|Signal Gain| (e.g., -1 V/V gives G_N= +2 V/V).

1.E+05

100k

G_N> +1 V/V

1,000

G_N≥ +1

C_G= 7 pF

C_G= 20 pF

1.E1+00k4

100

10

1k

1.E+03

C_G= 50 pF

_G= 100 pF

C

100

1.E+02

1

10

Noise Gain; G_N(V/V)

10

100

1,000

10,000

Normalized Capacitance; C_L/G_N(pF)

FIGURE 4-6:

Non-inverting gain circuit

with parasitic capacitance.

FIGURE 4-4:

Recommended R

values

ISO

for capacitive loads.

4.5

MCP6023 Chip Select (CS)

After selecting R_ISOfor your circuit, double-check the

resulting frequency response peaking and step

response overshoot. Modify R_ISO’s value until the

response is reasonable. Evaluation on the bench and

simulations with the MCP6021/1R/2/3/4 Spice macro

model are helpful.

The MCP6023 is a single amplifier with chip select

(CS). When CS is pulled high, the supply current drops

to 10 nA (typical) and flows through the CS pin to V_SS

When this happens, the amplifier output is put into a

high-impedance state. By pulling CS low, the amplifier

is enabled. The CS pin has an internal 5 MΩ (typical)

pulldown resistor connected to V_SS, so it will go low if

the CS pin is left floating. Figure 1-1 and Figure 2-39

show the output voltage and supply current response to

a CS pulse.

.

4.4

Gain Peaking

Figure 2-35 and Figure 2-36 use R_F= 1 kΩ to avoid

(frequency response) gain peaking and (step

response) overshoot. The capacitance to ground at the

inverting input (C_G) is the op amp’s common mode

input capacitance plus board parasitic capacitance. C_G

is in parallel with R_G, which causes an increase in gain

at high frequencies for non-inverting gains greater than

DS21685D-page 18

MCP6021/1R/2/3/4

4.6

MCP6021 and MCP6023 Reference

Voltage

R_G

R_F

V_IN

V_OUT

The single op amps (MCP6021 and MCP6023), not in

the SOT-23-5 package, have an internal mid-supply

reference voltage connected to the V_REFpin (see

Figure 4-7). The MCP6021 has CS internally tied to

V_SS, which always keeps the op amp on and always

provides a mid-supply reference. With the MCP6023,

taking the CS pin high conserves power by shutting

down both the op amp and the V_REFcircuitry. Taking

the CS pin low turns on the op amp and V_REFcircuitry.

V_REF

C_B

FIGURE 4-9:

Inverting gain circuit using

V

(MCP6021 and MCP6023 only).

V_DD

REF

If you don’t need the mid-supply reference, leave the

V_REFpin open.

50 kΩ

4.7

Supply Bypass

V_REF

With this family of operational amplifiers, the power

supply pin (V_DDfor single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good, high-frequency performance. It also needs a

bulk capacitor (i.e., 1 µF or larger) within 100 mm to

provide large, slow currents. This bulk capacitor can be

shared with nearby analog parts.

50 kΩ

CS

5 MΩ

4.8

Unused Op Amps

V_SS

An unused op amp in a quad package (MCP6024)

should be configured as shown in Figure 4-10. These

circuits prevent the output from toggling and causing

crosstalk. Circuits A sets the op amp at its minimum

noise gain. The resistor divider produces any desired

reference voltage within the output voltage range of the

op amp; the op amp buffers that reference voltage.

Circuit B uses the minimum number of components

and operates as a comparator, but it may draw more

current.

(CS tied internally to V_SSfor MCP6021)

FIGURE 4-7:

Simplified internal V

REF

circuit (MCP6021 and MCP6023 only).

See Figure 4-8 for a non-inverting gain circuit using the

internal mid-supply reference. The DC-blocking

capacitor (C_B) also reduces noise by coupling the op

amp input to the source.

R_G

R_F

¼ MCP6024 (A)

V_DD

¼ MCP6024 (B)

V_DD

V_OUT

V_DD

R₁

R₂

C_B

V_REF

V_IN

V_REF

FIGURE 4-8:

Non-inverting gain circuit

using V

(MCP6021 and MCP6023 only).

REF

To use the internal mid-supply reference for an

inverting gain circuit, connect the V_REFpin to the

non-inverting input, as shown in Figure 4-9. The

capacitor C_Bhelps reduce power supply noise on the

output.

R₂

------------------

×

V_REF= V_DD

R₁+ R₂

FIGURE 4-10:

Unused Op Amps.

DS21685D-page 19

MCP6021/1R/2/3/4

Separate digital from analog, low speed from high

speed and low power from high power. This will reduce

interference.

4.9

PCB Surface Leakage

In applications where low input bias current is critical,

PCB (printed circuit board) surface-leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 10¹²Ω. A 5V difference would

cause 5 pA of current to flow, which is greater than the

MCP6021/1R/2/3/4 family’s bias current at +25°C

(1 pA, typical).

Keep sensitive traces short and straight. Separating

them from interfering components and traces. This is

especially important for high-frequency (low rise-time)

signals.

Sometimes it helps to place guard traces next to victim

traces. They should be on both sides of the victim

trace, and as close as possible. Connect the guard

trace to ground plane at both ends, and in the middle

for long traces.

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

Figure 4-11 shows an example of this type of layout.

Use coax cables (or low inductance wiring) to route

signal and power to and from the PCB.

4.11 Typical Applications

Guard Ring

V_IN– V_IN+

4.11.1

A/D CONVERTER DRIVER AND

ANTI-ALIASING FILTER

Figure 4-12 shows a third-order Butterworth filter that

can be used as an A/D converter driver. It has a band-

width of 20 kHz and a reasonable step response. It will

work well for conversion rates of 80 ksps and greater (it

has 29 dB attenuation at 60 kHz).

FIGURE 4-11:

Layout.

Example Guard Ring

1. Non-inverting Gain and Unity-Gain Buffer.

a) Connect the guard ring to the inverting input

pin (V_IN–); this biases the guard ring to the

common mode input voltage.

1.0 nF

MCP602X

14.7 kΩ 33.2 kΩ

8.45 kΩ

b) Connect the non-inverting pin (V_IN+) to the

input with a wire that does not touch the

PCB surface.

100 pF

1.2 nF

2. Inverting (Figure 4-11) and Transimpedance

Gain Amplifiers (convert current to voltage, such

as photo detectors).

FIGURE 4-12:

Anti-aliasing Filter with a 20 kHz Cutoff

Frequency.

A/D Converter Driver and

a) Connect the guard ring to the non-inverting

input pin (V_IN+). This biases the guard ring

to the same reference voltage as the op

amp’s input (e.g., V_DD/2 or ground).

This filter can easily be adjusted to another bandwidth

by multiplying all capacitors by the same factor.

Alternatively, the resistors can all be scaled by another

common factor to adjust the bandwidth.

b) Connect the inverting pin (V_IN–) to the input

with a wire that does not touch the PCB

surface.

4.10 High Speed PCB Layout

Due to their speed capabilities, a little extra care in the

PCB (Printed Circuit Board) layout can make a

significant difference in the performance of these op

amps. Good PC board layout techniques will help you

achieve the performance shown in Section 1.0 “Elec-

trical Characteristics” and Section 2.0 “Typical Per-

formance Curves”, while also helping you minimize

EMC (Electro-Magnetic Compatibility) issues.

Use a solid ground plane and connect the bypass local

capacitor(s) to this plane with minimal length traces.

This cuts down inductive and capacitive crosstalk.

DS21685D-page 20

MCP6021/1R/2/3/4

4.11.2

OPTICAL DETECTOR AMPLIFIER

Figure 4-13 shows the MCP6021 op amp used as a

transimpedance amplifier in a photo detector circuit.

The photo detector looks like a capacitive current

source, so the 100 kΩ resistor gains the input signal to

a reasonable level. The 5.6 pF capacitor stabilizes this

circuit and produces a flat frequency response with a

bandwidth of 370 kHz.

5.6 pF

Photo

Detector

100 kΩ

100 pF

MCP6021

V_DD/2

FIGURE 4-13:

Transimpedance Amplifier

for an Optical Detector.

DS21685D-page 21

MCP6021/1R/2/3/4

NOTES:

DS21685D-page 22

MCP6021/1R/2/3/4

5.5

Analog Demonstration and

Evaluation Boards

5.0

DESIGN AIDS

Microchip provides the basic design tools needed for

the MCP6021/1R/2/3/4 family of op amps.

Microchip offers a broad spectrum of Analog Demon-

stration and Evaluation Boards that are designed to

help you achieve faster time to market. For a complete

listing of these boards and their corresponding user’s

guides and technical information, visit the Microchip

web site at www.microchip.com/analogtools.

5.1

SPICE Macro Model

The latest SPICE macro model available for the

MCP6021/1R/2/3/4 op amps is on Microchip’s web site

at www.microchip.com. This model is intended as an

initial design tool that works well in the op amp’s linear

region of operation at room temperature. Within the

macro model file is information on its capabilities.

Some boards that are especially useful are:

• MCP6XXX Amplifier Evaluation Board 1

• MCP6XXX Amplifier Evaluation Board 2

• MCP6XXX Amplifier Evaluation Board 3

• MCP6XXX Amplifier Evaluation Board 4

• Active Filter Demo Board Kit

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristic curves.

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,

P/N: SOIC8EV

• 14-Pin SOIC/TSSOP/DIP Evaluation Board,

P/N: SOIC14EV

5.2

FilterLab^®Software

Microchip’s FilterLab^®software is an innovative

software tool that simplifies analog active filter (using

op amps) design. Available at no cost from the

Microchip web site at www.microchip.com/filterlab, the

FilterLab design tool provides full schematic diagrams

of the filter circuit with component values. It also

outputs the filter circuit in SPICE format, which can be

used with the macro model to simulate actual filter

performance.

5.6

Application Notes

The following Microchip Application Notes are avail-

able on the Microchip web site at www.microchip. com/

appnotes and are recommended as supplemental ref-

erence resources.

• ADN003: “Select the Right Operational Amplifier

for your Filtering Circuits”, DS21821

• AN722: “Operational Amplifier Topologies and DC

Specifications”, DS00722

5.3

Mindi™ Circuit Designer &

Simulator

• AN723: “Operational Amplifier AC Specifications

and Applications”, DS00723

Microchip’s Mindi™ Circuit Designer & Simulator aids

in the design of various circuits useful for active filter,

amplifier and power-management applications. It is a

free online circuit designer & simulator available from

the Microchip web site at www.microchip.com/mindi.

This interactive circuit designer & simulator enables

designers to quickly generate circuit diagrams,

simulate circuits. Circuits developed using the Mindi

Circuit Designer & Simulator can be downloaded to a

personal computer or workstation.

• AN884: “Driving Capacitive Loads With Op

Amps”, DS00884

• AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

• AN1177: “Op Amp Precision Design: DC Errors”,

DS01177

• AN1228: “Op Amp Precision Design: Random

Noise”, DS01228

These application notes and others are listed in the

design guide:

5.4

Microchip Advanced Part Selector

(MAPS)

“Signal Chain Design Guide”, DS21825

MAPS is a software tool that helps semiconductor

professionals efficiently identify Microchip devices that

fit a particular design requirement. Available at no cost

from the Microchip web site at www.microchip.com/

maps, the MAPS is an overall selection tool for

Microchip’s product portfolio that includes Analog,

Memory, MCUs and DSCs. Using this tool you can

define a filter to sort features for a parametric search of

devices and export side-by-side technical comparison

reports. Helpful links are also provided for Data sheets,

Purchase, and Sampling of Microchip parts.

DS21685D-page 23

MCP6021/1R/2/3/4

NOTES:

DS21685D-page 24

MCP6021/1R/2/3/4

6.0

6.1

PACKAGING INFORMATION

Package Marking Information

Example: (E-temp)

5-Lead SOT-23 (MCP6021/MCP6021R)

Device

E-Temp Code

MCP6021

XXNN

EYNN

EZNN

EY25

MCP6021R

Note: Applies to 5-Lead SOT-23

8-Lead PDIP (300 mil)

Example:

XXXXXXXX

XXXXXNNN

MCP6021

E/P^^256

0903

e

3

I/P256

OR

YYWW

0903

8-Lead SOIC (150 mil)

Example:

XXXXXXXX

XXXXYYWW

MCP6021

I/SN0903

MCP6021E

SN^^

e

3

0903

OR

NNN

256

Example:

8-Lead MSOP

6021E

903256

XXXXXX

YWWNNN

Example:

8-Lead TSSOP

6021

XXXX

YYWW

NNN

E903

256

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21685D-page 25

MCP6021/1R/2/3/4

Package Marking Information (Continued)

14-Lead PDIP (300 mil) (MCP6024)

Example:

MCP6024-I/P

XXXXXXXXXXXXXX

YYWWNNN

0903256

MCP6024

E/P^^

3

e

OR

0903256

14-Lead SOIC (150 mil) (MCP6024)

Example:

MCP6024ISL

XXXXXXXXXX

YYWWNNN

0903256

MCP6024

e

3

E/SL^^

OR

0903256

Example:

14-Lead TSSOP (MCP6024)

XXXXXX

YYWW

6024E

0903

NNN

256

DS21685D-page 26

MCP6021/1R/2/3/4

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DS21685D-page 27

MCP6021/1R/2/3/4

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DS21685D-page 28

MCP6021/1R/2/3/4

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DS21685D-page 29

MCP6021/1R/2/3/4

ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢛꢖꢆMꢆꢛꢄꢓꢓꢔ&'ꢆꢙ()#ꢆꢎꢎꢆ$ꢔꢅ%ꢆꢗꢍꢏ!*ꢚ

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DS21685D-page 30

MCP6021/1R/2/3/4

ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ+ꢋꢌꢓꢔꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢇꢄꢌ,ꢄ-ꢃꢆꢕ+ꢍꢖꢆꢗ+ꢍꢏꢇꢚ

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D

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DS21685D-page 31

MCP6021/1R/2/3/4

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ꢑꢁ ꢟꢈꢕꢃꢓꢆꢃ%ꢃꢊꢉꢆ#ꢈ*ꢌꢉꢍꢉꢊ#ꢅꢍꢃ #ꢃꢊꢁ

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ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ

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DS21685D-page 32

MCP6021/1R/2/3/4

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DS21685D-page 33

MCP6021/1R/2/3/4

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DS21685D-page 34

MCP6021/1R/2/3/4

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DS21685D-page 35

MCP6021/1R/2/3/4

NOTES:

DS21685D-page 36

MCP6021/1R/2/3/4

Revision B (November 2003)

APPENDIX A: REVISION HISTORY

• Second Release of this Document

Revision D (February 2009)

Revision A (November 2001)

The following is the list of modifications:

1. Changed all references to 6.0V back to 5.5V

throughout document.

• Original Release of this Document.

2. Design Aids: Name change for Mindi Simula-

tion Tool.

3. Section 1.0 “Electrical Characteristics”, DC

Electrical Specifications: Corrected “Maxi-

mum Output Voltage Swing” condition from 0.9V

Input Overdrive to 0.5V Input Overdrive.

4. Section 1.0 “Electrical Characteristics”, AC

Electrical Specifications: Changed Phase

Margin condition from G = +1 to G= +1 V/V.

5. Section 1.0 “Electrical Characteristics”, AC

Electrical Specifications: Changed Settling

Time, 0.2% condition from G = +1 to G = +1 V/V.

6. Section 1.0 “Electrical Characteristics”:

Added Section 1.1 Test Circuits.

7. Section 5.0 “Design AIDS”: Name change for

Mindi Simulation Tool. Added new boards to

Section 5.5 “Analog Demonstration and

Evaluation Boards” and new application notes

to Section 5.6 “Application Notes”.

8. Updates Appendix A: “Revision History”

Revision C (March 2006)

The following is the list of modifications:

1. Added SOT-23-5 package option for single op

amps MCP6021 and MCP6021R (E-temp only).

2. Added MSOP-8 package option for E-temp

single op amp (MCP6021).

3. Corrected package drawing on front page for

dual op amp (MCP6022).

4. Clarified spec conditions (I_SC, PM and THD+N)

in

Section 2.0

“Typical

Performance

Curves”.

5. Added Section 3.0 “Pin Descriptions”.

6. Updated Section 4.0 “Applications informa-

tion” for THD+N, unused op amps, and gain

peaking discussions.

7. Corrected and updated package marking infor-

mation in Section 6.0 “Packaging Informa-

tion”.

8. Added Appendix A: “Revision History”.

DS21685D-page 37

MCP6021/1R/2/3/4

NOTES:

DS21685D-page 38

MCP6021/1R/2/3/4

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

a)

MCP6021T-E/OT: Tape and Reel,

Extended temperature,

Temperature

Range

Package

5LD SOT-23.

Extended temperature,

8LD PDIP.

b)

c)

MCP6021-E/P:

MCP6021-E/SN: Extended temperature,

8LD SOIC.

Device:

MCP6021

Single Op Amp

MCP6021T Single Op Amp

(Tape and Reel for SOT-23, SOIC, TSSOP,

a)

MCP6021RT-E/OT:Tape and Reel,

Extended temperature,

5LD SOT-23.

MSOP)

MCP6021R Single Op Amp

MCP6021RT Single Op Amp

(Tape and Reel for SOT-23)

Dual Op Amp

MCP6022T Dual Op Amp

(Tape and Reel for SOIC and TSSOP)

Single Op Amp w/ CS

MCP6023T Single Op Amp w/ CS

(Tape and Reel for SOIC and TSSOP)

Quad Op Amp

MCP6024T Quad Op Amp

(Tape and Reel for SOIC and TSSOP)

a)

b)

c)

MCP6022-I/P:

MCP6022-E/P:

Industrial temperature,

8LD PDIP.

Extended temperature,

8LD PDIP.

MCP6022

MCP6023

MCP6022T-E/ST: Tape and Reel,

Extended temperature,

8LD TSSOP.

MCP6024

a)

b)

c)

MCP6023-I/P:

MCP6023-E/P:

Industrial temperature,

8LD PDIP.

Extended temperature,

8LD PDIP.

Temperature Range:

Package:

I

=

-40°C to +85°C

MCP6023-E/SN: Extended temperature,

8LD SOIC.

E

-40°C to +125°C

a)

b)

c)

MCP6024-I/SL: Industrial temperature,

14LD SOIC.

MCP6024-E/SL: Extended temperature,

14LD SOIC.

MCP6024T-E/ST: Tape and Reel,

Extended temperature,

OT

MS

=

Plastic Small Outline Transistor (SOT-23), 5-lead

(MCP6021, E-Temp; MCP6021R, E-Temp)

Plastic MSOP, 8-lead

(MCP6021, E-Temp)

P

=

Plastic DIP (300 mil Body), 8-lead, 14-lead

Plastic SOIC (150mil Body), 8-lead

Plastic SOIC (150 mil Body), 14-lead

Plastic TSSOP, 8-lead

SN

SL

ST

14LD TSSOP.

(MCP6021,I-Temp; MCP6022, I-Temp, E-Temp;

MCP6023, I-Temp, E-Temp;)

ST

=

Plastic TSSOP, 14-lead

DS21685D-page 39

MCP6021/1R/2/3/4

NOTES:

DS21685D-page 40

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

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Endurance, WiperLock and ZENA are trademarks of

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SQTP is a service mark of Microchip Technology Incorporated

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All other trademarks mentioned herein are property of their

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Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS21685D-page 41

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

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Austria - Wels

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Technical Support:

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Web Address:

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Germany - Munich

Tel: 49-89-627-144-0

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China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

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Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

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Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

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Fax: 630-285-0075

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Tel: 34-91-708-08-90

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Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

02/04/09

DS21685D-page 42


型号：	MCP6024T
厂家：	MICROCHIP
描述：	Rail-to-Rail Input/Output, 10 MHz Op Amps 轨至轨输入/输出， 10 MHz的运算放大器运算放大器
文件：	总42页 (文件大小：635K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP6024T [MICROCHIP]

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MCP6024T-E/SLVAO

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MCP6024T-E/ST

MCP6024T-E/STVAO

MCP6024T-I/MS

MCP6024T-I/OT

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MCP6024T-I/SL