MCP6024T-E/OT [MICROCHIP]
Rail-to-Rail Input/Output, 10 MHz Op Amps; 轨至轨输入/输出， 10 MHz的运算放大器
| 型号： | MCP6024T-E/OT |
| 厂家： | 
MICROCHIP |
| 描述： | Rail-to-Rail Input/Output, 10 MHz Op Amps |
| 文件： | 总34页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6021/1R/2/3/4
Rail-to-Rail Input/Output, 10 MHz Op Amps
Features
Description
• Rail-to-Rail Input/Output
The MCP6021, MCP6021R, MCP6022, MCP6023 and
MCP6024 from Microchip Technology Inc. are rail-to-
rail input and output op amps with high performance.
Key specifications include: wide bandwidth (10 MHz),
low noise (8.7 nV/√Hz), low input offset voltage and low
distortion (0.00053% THD+N). The MCP6023 also
offers a Chip Select pin (CS) that gives power savings
when the part is not in use.
• Wide Bandwidth: 10 MHz (typ.)
• Low Noise: 8.7 nV/√Hz, at 10 kHz (typ.)
• Low Offset Voltage:
- Industrial Temperature: ±500 µV (max.)
- Extended Temperature: ±250 µV (max.)
• Mid-Supply VREF: MCP6021 and MCP6023
• Low Supply Current: 1 mA (typ.)
• Total Harmonic Distortion: 0.00053% (typ., G = 1)
• Unity Gain Stable
The single MCP6021 and MCP6021R are available in
SOT-23-5. The single MCP6021, single MCP6023 and
dual MCP6022 are available in 8-lead PDIP, SOIC and
TSSOP. The Extended Temperature single MCP6021
is available in 8-lead MSOP. The quad MCP6024 is
offered in 14-lead PDIP, SOIC and TSSOP packages.
• Power Supply Range: 2.5V to 5.5V
• Temperature Range:
- Industrial: -40°C to +85°C
The MCP6021/1R/2/3/4 family is available in Industrial
and Extended temperature ranges. It has a power
supply range of 2.5V to 5.5V.
- Extended: -40°C to +125°C
Typical Applications
Package Types
• Automotive
• Driving A/D Converters
• Multi-Pole Active Filters
• Barcode Scanners
• Audio Processing
• Communications
• DAC Buffer
MCP6021
SOT-23-5
MCP6022
PDIP SOIC, TSSOP
VOUTA
VDD
VDD
VOUT
VSS
1
1
2
3
4
8
7
6
5
5
VINA
–
+
VOUTB
2
3
VINA
VINB
–
+
VIN+
4 VIN–
VSS
VINB
MCP6021R
• Test Equipment
SOT-23-5
MCP6023
PDIP SOIC, TSSOP
• Medical Instrumentation
VOUT
VDD
1
2
3
VSS
5
Available Tools
NC
VIN–
VIN+
VSS
1
2
3
4
8 CS
VDD
• SPICE Macro Model (at www.microchip.com)
• FilterLab® software (at www.microchip.com)
VIN+
7
6
5
4 VIN–
VOUT
VREF
MCP6021
PDIP SOIC,
MSOP, TSSOP
Typical Application
MCP6024
PDIP SOIC, TSSOP
5.6 pF
Photo
Detector
NC
NC
1
2
3
4
8
7
6
5
VOUTA
V
V
V
V
V
1
2
3
4
5
6
7
14
13
12
11
10
9
OUTD
VDD
VIN–
VIN+
VSS
100 kΩ
VINA
–
+
–
IND
VOUT
VREF
VINA
+
IND
100 pF
VDD
SS
VINB
+
–
+
MCP6021
INC
VINB
VINC
–
VDD/2
VOUTB
VOUTC
8
Transimpedance Amplifier
© 2006 Microchip Technology Inc.
DS21685C-page 1
MCP6021/1R/2/3/4
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
– V ........................................................................7.0V
SS
DD
All Inputs and Outputs.................... V – 0.3V to V + 0.3V
SS
DD
Difference Input Voltage ...................................... |V – V
|
DD
SS
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature.....................................-65°C to +150°C
Junction Temperature..................................................+150°C
ESD Protection on all pins (HBM; MM)................ ≥ 2 kV; 200V
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2, V
≈ V /2
OUT DD
A
DD
SS
CM
DD
and R = 10 kΩ to V /2.
L
DD
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset
Input Offset Voltage:
Industrial Temperature Parts
Extended Temperature Parts
Extended Temperature Parts
V
V
V
-500
-250
-2.5
—
—
—
+500
+250
+2.5
µV
µV
V
V
V
= 0V
OS
OS
OS
CM
CM
CM
= 0V, V = 5.0V
DD
mV
= 0V, V = 5.0V
DD
T = -40°C to +125°C
A
Input Offset Voltage Temperature Drift ΔV /ΔT
—
±3.5
90
—
—
µV/°C T = -40°C to +125°C
A
OS
A
Power Supply Rejection Ratio
Input Current and Impedance
Input Bias Current
PSRR
74
dB
V
= 0V
CM
I
I
I
—
—
—
—
—
—
1
—
150
5,000
—
pA
pA
B
B
B
Industrial Temperature Parts
Extended Temperature Parts
Input Offset Current
30
T = +85°C
A
640
±1
pA
T = +125°C
A
I
pA
OS
13
Common-Mode Input Impedance
Differential Input Impedance
Common-Mode
Z
10 ||6
—
Ω||pF
Ω||pF
CM
13
Z
10 ||3
—
DIFF
Common-Mode Input Range
Common-Mode Rejection Ratio
V
V
-0.3
—
90
85
90
V
+0.3
DD
V
CMR
SS
CMRR
CMRR
CMRR
74
—
dB
dB
dB
V
V
V
= 5V, V
= 5V, V
= 5V, V
= -0.3V to 5.3V
DD
DD
DD
CM
CM
CM
70
74
—
—
= 3.0V to 5.3V
= -0.3V to 3.0V
Voltage Reference (MCP6021 and MCP6023 only)
V
V
Accuracy (V
– V /2)
V
REF_ACC
-50
—
—
+50
—
mV
REF
REF
REF
DD
Temperature Drift
ΔV
/ΔT
±100
µV/°C T = -40°C to +125°C
A
REF
A
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
A
90
110
—
dB
V
V
= 0V,
CM
OL
= V +0.3V to V -0.3V
OUT
SS
DD
Output
Maximum Output Voltage Swing
Output Short Circuit Current
V
, V
V
+15
—
V -20
DD
mV
mA
mA
0.5V output overdrive
OL
OH
SS
I
I
—
—
±30
±22
—
V
V
= 2.5V
= 5.5V
SC
SC
DD
DD
—
Power Supply
Supply Voltage
V
2.5
0.5
—
5.5
V
S
Quiescent Current per Amplifier
I
1.0
1.35
mA
I = 0
O
Q
DS21685C-page 2
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2,
DD
A
DD
SS
CM
V
≈ V /2, R = 10 kΩ to V /2 and C = 60 pF.
DD L DD L
OUT
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin at Unity-Gain
Settling Time, 0.2%
Slew Rate
GBWP
PM
—
—
—
—
10
65
—
—
—
—
MHz
°
G = +1
G = +1, V
t
250
7.0
ns
= 100 mV
OUT p-p
SETTLE
SR
V/µs
Total Harmonic Distortion Plus Noise
f = 1 kHz, G = +1 V/V
THD+N
—
—
0.00053
0.00064
—
—
%
%
V
V
= 0.25V to 3.25V (1.75V ± 1.50V ),
OUT PK
= 5.0V, BW = 22 kHz
DD
f = 1 kHz, G = +1 V/V, R = 600Ω
THD+N
V
V
= 0.25V to 3.25V (1.75V ± 1.50V ),
L
OUT
PK
= 5.0V, BW = 22 kHz
DD
f = 1 kHz, G = +1 V/V
f = 1 kHz, G = +10 V/V
f = 1 kHz, G = +100 V/V
Noise
THD+N
THD+N
THD+N
—
—
—
0.0014
0.0009
0.005
—
—
—
%
%
%
V
V
V
= 4V , V = 5.0V, BW = 22 kHz
P-P DD
OUT
OUT
OUT
= 4V , V = 5.0V, BW = 22 kHz
P-P DD
= 4V , V = 5.0V, BW = 22 kHz
P-P DD
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
E
e
—
—
—
2.9
8.7
3
—
—
—
µVp-p f = 0.1 Hz to 10 Hz
nV/√Hz f = 10 kHz
ni
ni
i
fA/√Hz f = 1 kHz
ni
MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2,
DD
A
DD
SS
CM
V
≈ V /2, R = 10 kΩ to V /2 and C = 60 pF.
OUT
DD
L
DD
L
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
CS Input Current, Low
CS High Specifications
CS Logic Threshold, High
CS Input Current, High
GND Current
V
V
—
0.2 V
DD
V
IL
SS
I
-1.0
0.01
—
µA CS = V
CSL
SS
V
0.8 V
—
—
V
DD
V
IH
DD
I
0.01
-0.05
0.01
2.0
—
µA CS = V
µA CS = V
µA CS = V
CSH
DD
DD
DD
I
-2
SS
O(LEAK)
Amplifier Output Leakage
CS Dynamic Specifications
I
—
—
CS Low to Amplifier Output Turn-on Time
CS High to Amplifier Output High-Z Time
Hysteresis
t
—
—
—
2
10
—
—
µs
µs
V
G = +1, V = V
SS
,
ON
IN
CS = 0.2V to V
= 0.45V time
DD
DD
OUT
t
0.01
0.6
G = +1, V = V
SS
,
OFF
IN
CS = 0.8V to V
= 0.05V time
DD
DD
OUT
V
V
= 5.0V, Internal Switch
HYST
DD
© 2006 Microchip Technology Inc.
DS21685C-page 3
MCP6021/1R/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, V = +2.5V to +5.5V and V = GND.
DD
SS
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Industrial Temperature Range
Extended Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 8L-TSSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
T
-40
-40
-40
-65
—
—
—
—
+85
°C
°C
°C
°C
A
T
+125
+125
+150
A
T
Note 1
A
T
A
θ
θ
θ
θ
θ
θ
θ
θ
—
—
—
—
—
—
—
—
256
85
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JA
JA
JA
JA
JA
163
206
124
70
120
100
Note 1: The industrial temperature devices operate over this extended temperature range, but with reduced performance. In any
case, the internal junction temperature (T ) must not exceed the absolute maximum specification of 150°C.
J
CS
tON
tOFF
High-Z
Amplifier On
-1 mA (typ.)
10 nA (typ.)
High-Z
VOUT
ISS
-50 nA (typ.)
10 nA (typ.)
-50 nA (typ.)
10 nA (typ.)
ICS
FIGURE 1-1:
Timing diagram for the CS
pin on the MCP6023.
DS21685C-page 4
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
16%
14%
12%
10%
8%
24%
22%
20%
18%
16%
14%
12%
10%
8%
I-Temp
Parts
1192 Samples
VCM = 0V
I-Temp
Parts
1192 Samples
VCM = 0V
TA = +25°C
T
A = -40°C to +85°C
6%
4%
6%
4%
2%
2%
0%
0%
Input Offset Voltage (µV)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-1:
Input Offset Voltage,
FIGURE 2-4:
Input Offset Voltage Drift,
(Industrial Temperature Parts).
(Industrial Temperature Parts).
24%
24%
E-Temp
22%
438 Samples
DD = 5.0V
VCM = 0V
A = +25°C
E-Temp
Parts
438 Samples
CM = 0V
A = -40°C to +125°C
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
Parts
V
V
T
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
T
Input Offset Voltage (µV)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-2:
Input Offset Voltage,
FIGURE 2-5:
Input Offset Voltage Drift,
(Extended Temperature Parts).
(Extended Temperature Parts).
500
500
-40°C
VDD = 5.5V
VDD = 2.5V
400
400
+25°C
+85°C
+125°C
-40°C
300
200
100
0
300
200
100
0
+25°C
+85°C
+125°C
-100
-200
-300
-400
-500
-100
-200
-300
-400
-500
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 2.5V.
Common Mode Input Voltage with VDD = 5.5V.
© 2006 Microchip Technology Inc.
DS21685C-page 5
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
100
50
200
150
100
50
VCM = VDD/2
0
VDD = 5.5V
-50
0
-100
-150
-200
-250
-300
VDD = 2.5V
-50
-100
-150
-200
VDD = 5.0V
V
CM = 0V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
Input Offset Voltage vs.
Temperature.
Output Voltage.
1,000
100
10
24
VDD = 5.0V
22
20
18
16
14
12
10
8
f = 1 kHz
f = 10 kHz
6
4
2
0
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1
0.1
1
10
100
1k
10k 100k 1M
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-8:
Input Noise Voltage Density
FIGURE 2-11:
Input Noise Voltage Density
vs. Frequency.
vs. Common Mode Input Voltage.
100
90
80
70
60
50
40
30
110
105
PSRR+
PSRR-
CMRR
100
95
90
85
80
75
70
PSRR (VCM = 0V)
CMRR
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
20
100
1k
10k
100k
1M
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
CMRR, PSRR vs.
Frequency.
Temperature.
DS21685C-page 6
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
10,000
1,000
100
10
10,000
1,000
100
10
VCM = VDD
VDD = 5.5V
IB, TA = +125°C
VDD = 5.5V
IOS, TA = +125°C
IB, TA = +85°C
IB
IOS
IOS, TA = +85°C
1
1
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Bias, Offset Currents
FIGURE 2-16:
Input Bias, Offset Currents
vs. Common Mode Input Voltage.
vs. Temperature.
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.2
1.1
VDD = 5.5V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VDD = 2.5V
+125°C
+85°C
+25°C
-40°C
VCM = VDD - 0.5V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
FIGURE 2-14:
Quiescent Current vs.
FIGURE 2-17:
Quiescent Current vs.
Supply Voltage.
Temperature.
35
30
25
20
15
10
5
120
110
100
90
80
70
60
50
40
30
20
10
0
0
-15
-30
-45
-60
-75
-90
Phase
-105
-120
-135
-150
-165
-180
-195
-210
+125°C
+85°C
+25°C
-40°C
Gain
-10
-20
0
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1
10 100 1k 10k 100k 1M 10M 100M
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
Frequency (Hz)
FIGURE 2-15:
vs. Supply Voltage.
Output Short-Circuit Current
FIGURE 2-18:
Frequency.
Open-Loop Gain, Phase vs.
© 2006 Microchip Technology Inc.
DS21685C-page 7
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
130
120
110
100
90
120
115
110
105
100
95
VDD = 5.5V
VDD = 5.5V
VDD = 2.5V
VDD = 2.5V
90
1.E+02
1.E+03
1.E+04
1.E+05
80
-50
-25
0
25
50
75
100
125
100
1k
10k
100k
Load Resistance (Ω)
Ambient Temperature (°C)
FIGURE 2-19:
DC Open-Loop Gain vs.
FIGURE 2-22:
DC Open-Loop Gain vs.
Load Resistance.
Temperature.
120
14
105
90
VCM = VDD/2
110
Gain Bandwidth Product
12
10
8
VDD = 5.5V
75
100
90
60
Phase Margin, G = +1
45
6
VDD = 2.5V
80
4
30
15
0
2
70
VDD = 5.0V
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
Output Voltage Headroom (V);
VDD - VOH or VOL - VSS
FIGURE 2-20:
Small Signal DC Open-Loop
FIGURE 2-23:
Gain Bandwidth Product,
Gain vs. Output Voltage Headroom.
Phase Margin vs. Common Mode Input Voltage.
10
9
100
90
80
70
60
50
40
30
20
10
0
14
12
10
8
105
90
75
60
45
30
15
0
Gain Bandwidth Product
8
7
6
Phase Margin, G = +1
5
4
3
2
1
0
GBWP, VDD = 5.5V
GBWP, VDD = 2.5V
6
PM,
PM,
V
DD = 2.5V
4
VDD = 5.5V
VDD = 5.0V
VCM = VDD/2
2
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (V)
-50 -25
0
25
50
75 100 125
Ambient Temperature (°C)
FIGURE 2-21:
Gain Bandwidth Product,
FIGURE 2-24:
Gain Bandwidth Product,
Phase Margin vs. Temperature.
Phase Margin vs. Output Voltage.
DS21685C-page 8
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
10
11
10
9
Falling, VDD = 5.5V
Rising, VDD = 5.5V
VDD = 5.5V
VDD = 2.5V
8
7
6
5
4
3
1
Falling, VDD = 2.5V
Rising, VDD = 2.5V
2
1
0
0.1 1.E+04
1.E+05
1.E+06
1.E+07
-50
-25
0
25
50
75
100
125
10k
100k
Frequency (Hz)
1M
10M
Ambient Temperature (°C)
FIGURE 2-25:
Slew Rate vs. Temperature.
FIGURE 2-28:
Maximum Output Voltage
Swing vs. Frequency.
0.1000%
0.0100%
0.1000%
f = 1 kHz
BWMeas = 22 kHz
G = +100 V/V
VDD = 5.0V
G = +10 V/V
G = +1 V/V
G = +100 V/V
0.0100%
0.0010%
0.0001%
G = +10 V/V
G = +1 V/V
0.0010%
0.0001%
f = 20 kHz
BWMeas = 80 kHz
V
DD = 5.0V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (VP-P
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (VP-P
)
)
FIGURE 2-26:
Total Harmonic Distortion
FIGURE 2-29:
Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 1 kHz.
plus Noise vs. Output Voltage with f = 20 kHz.
135
130
125
120
115
6
VDD = 5.0V
G = +2 V/V
5
VOUT
4
VIN
3
2
1
0
110
G = +1 V/V
-1
1.E+03
1.E+04
1.E+05
1.E+06
105
0
10 20 30 40 50 60 70 80 90 100
Time (10 µs/div)
1k
10k
100k
1M
Frequency (Hz)
FIGURE 2-27:
The MCP6021/1R/2/3/4
FIGURE 2-30:
Channel-to-Channel
family shows no phase reversal under overdrive.
Separation vs. Frequency (MCP6022 and
MCP6024 only).
© 2006 Microchip Technology Inc.
DS21685C-page 9
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
1,000
100
10
10
9
8
7
6
5
4
3
2
1
0
VOL - VSS
VDD - VOH
VOL - VSS
VDD - VOH
1
-50
-25
0
25
50
75
100 125
0.01
0.1
1
10
Output Current Magnitude (mA)
Ambient Temperature (°C)
FIGURE 2-31:
Output Voltage Headroom
FIGURE 2-34:
Output Voltage Headroom
vs. Output Current.
vs. Temperature.
6.E-02
5.E-02
4.E-02
3.E-02
2.E-02
1.E-02
0.E+00
-1.E-02
-2.E-02
-3.E-02
-4.E-02
-5.E-02
-6.E-02
6.E-02
5.E-02
4.E-02
3.E-02
2.E-02
1.E-02
0.E+00
-1.E-02
-2.E-02
-3.E-02
-4.E-02
-5.E-02
-6.E-02
G = -1 V/V
RF = 1 kΩ
G = +1 V/V
0.E+00
2.E-07
4.E-07
6.E-07
8.E-07
1.E-06
1.E-06
1.E-06
2.E-06
2.E-06
2.E-06
0.E+00
2.E-07
4.E-07
6.E-07
8.E-07
1.E-06
1.E-06
1.E-06
2.E-06
2.E-06
2.E-06
Time (200 ns/div)
Time (200 ns/div)
FIGURE 2-32:
Small-Signal Non-inverting
FIGURE 2-35:
Small-Signal Inverting Pulse
Pulse Response.
Response.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
G = +1 V/V
G = -1 V/V
RF = 1 kΩ
0.E+00
5.E-07
1.E-06
2.E-06
2.E-06
3.E-06
3.E-06
4.E-06
4.E-06
5.E-06
5.E-06
0.0
0.E+00
5.E-07
1.E-06
2.E-06
2.E-06
3.E-06
3.E-06
4.E-06
4.E-06
5.E-06
5.E-06
0.0
Time (500 ns/div)
Time (500 ns/div)
FIGURE 2-33:
Large-Signal Non-inverting
FIGURE 2-36:
Large-Signal Inverting Pulse
Pulse Response.
Response.
DS21685C-page 10
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
50
40
50
40
Representative Part
30
30
20
20
VDD = 5.5V
VDD = 2.5V
10
10
0
0
-10
-20
-30
-40
-50
-10
-20
-30
-40
-50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
FIGURE 2-37:
VREF Accuracy vs. Supply
FIGURE 2-40:
VREF Accuracy vs.
Voltage (MCP6021 and MCP6023 only).
Temperature (MCP6021 and MCP6023 only).
1.6
1.6
Op Amp
turns on here
Op Amp
shuts off here
Op Amp
turns on here
Op Amp
shuts off here
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Hysteresis
CS swept
high to low
CS swept
high to low
Hysteresis
CS swept
low to high
CS swept
low to high
VDD = 5.5V
G = +1 V/V
VDD = 2.5V
G = +1 V/V
IN = 1.25V
VIN = 2.75V
V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
Chip Select Voltage (V)
FIGURE 2-38:
Chip Select (CS) Hysteresis
FIGURE 2-41:
Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 2.5V.
(MCP6023 only) with VDD = 5.5V.
5.5
5.0
4.5
4.0
3.5
VDD = 5.0V
G = +1 V/V
CS Voltage
VIN = VSS
3.0
2.5
VOUT
2.0
1.5
1.0
0.5
Output
on
Output
on
Output High-Z
0.0
-0.5 0.0E+00
5.0E-06
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.0E-05
3.5E-05
Time (5 µs/div)
FIGURE 2-39:
Chip Select (CS) to
Amplifier Output Response Time (MCP6023
only).
© 2006 Microchip Technology Inc.
DS21685C-page 11
MCP6021/1R/2/3/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6021
(PDIP,
SOIC,
MSOP,
TSSOP)
(Note 1)
MCP6021 MCP6021R
(SOT-23-5) (SOT-23-5) MCP6022 MCP6023 MCP6024
Symbol
Description
(Note 1)
(Note 2)
6
2
1
1
1
2
6
2
1
2
V
, V
Analog Output (op amp A)
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Positive Power Supply
OUT OUTA
4
4
V
–, V
+, V
–
+
IN
IN
INA
INA
3
3
3
3
3
3
V
7
5
2
8
7
4
V
DD
—
—
—
—
—
—
4
—
—
—
—
—
—
2
—
—
—
—
—
—
5
5
—
—
—
—
—
—
4
5
V
+
–
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Analog Output (op amp B)
Analog Output (op amp C)
Inverting Input (op amp C)
Non-inverting Input (op amp C)
Negative Power Supply
INB
INB
6
6
V
7
7
V
V
OUTB
OUTC
—
—
—
4
8
9
V
V
–
+
INC
INC
10
11
12
13
14
—
V
SS
—
—
—
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
V
V
+
Non-inverting Input (op amp D)
Inverting Input (op amp D)
Analog Output (op amp D)
Reference Voltage
IND
IND
–
V
OUTD
V
REF
—
—
—
—
—
—
—
8
1
—
—
CS
Chip Select
1, 8
NC
No Internal Connection
Note 1: The MCP6021 in the 8-pin MSOP package is only available for E-temp (Extended Temperature) parts. The MCP6021
in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts.
2: The MCP6021R is only available in the 5-pin SOT-23 package, and for E-temp (Extended Temperature) parts.
3.1
Analog Outputs
3.5
Power Supply (V and V
)
DD
SS
The op amp output pins are low-impedance voltage
sources.
The positive power supply pin (VDD) is 2.5V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD
.
3.2
Analog Inputs
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts need
to use a bulk capacitor (typically 1 µF or larger) within
100 mm of the VDD pin; it can be shared with nearby
analog parts.
The op amp non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3
V
Output (MCP6021 and
REF
MCP6023)
Mid-supply reference voltage provided by the single op
amps (except in SOT-23-5 package). This is an
unbuffered, resistor voltage divider internal to the part.
3.4
CS Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
DS21685C-page 12
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
4.2
Rail-to-Rail Output
4.0
APPLICATIONS INFORMATION
The Maximum Output Voltage Swing is the maximum
swing possible under particular output load.
According to the specification table, the output can
reach within 20 mV of either supply rail when
RL = 10 kΩ. See Figure 2-31 and Figure 2-34 for more
information concerning typical performance.
The MCP6021/1R/2/3/4 family of operational amplifiers
are fabricated on Microchip’s state-of-the-art CMOS
process. They are unity-gain stable and suitable for a
wide range of general-purpose applications.
a
4.1
Rail-to-Rail Input
The MCP6021/1R/2/3/4 amplifier family is designed to
not exhibit phase inversion when the input pins exceed
the supply voltages. Figure 2-27 shows an input volt-
age exceeding both supplies with no resulting phase
inversion.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases, and the closed loop bandwidth is
reduced. This produces gain-peaking in the frequency
response, with overshoot and ringing in the step
response.
The input stage of the MCP6021/1R/2/3/4 family of
devices uses two differential input stages in parallel;
one operates at low common-mode input voltage
(VCM), while the other operates at high VCM. With this
topology, the device operates with VCM up to 0.3V past
either supply rail (VSS – 0.3V to VDD + 0.3V) at +25°C.
The amplifier input behaves linearly as long as VCM is
kept within the specified VCMR limits. The input offset
voltage is measured at both VCM = VSS – 0.3V and
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-2) improves the
feedback loop’s phase margin (stability) by making the
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
VDD + 0.3V to ensure proper operation.
Input voltages that exceed the input voltage range
(VCMR) can cause excessive current to flow in or out of
the input pins. Current beyond ±2 mA introduces
possible reliability problems. Thus, applications that
exceed this rating must externally limit the input current
with an input resistor (RIN), as shown in Figure 4-1.
VIN
RISO
VOUT
MCP602X
CL
FIGURE 4-2:
Output resistor RISO
stabilizes large capacitive loads.
MCP602X
VOUT
RIN
Figure 4-3 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
VIN
(Maximum expected VIN) - VDD
RIN
RIN
≥
≥
2 mA
VSS - (Minimum expected VIN)
2 mA
1,000
GN ≥ +1
FIGURE 4-1:
RIN limits the current flow
into an input pin.
Total Harmonic Distortion Plus Noise (THD+N) can be
affected by the common mode input voltage (VCM). As
shown in Figure 2-3 and Figure 2-6, the input offset
voltage (VOS) is affected by the change from the NMOS
to the PMOS input differential pairs. This change in VOS
will increase the distortion if the input voltage includes
this transition region. This transition occurs between
VDD – 1.0V and VDD – 2.0V, depending on VDD and
temperature.
100
10
10
100
1,000
10,000
Normalized Capacitance; CL/GN (pF)
FIGURE 4-3:
Recommended RISO values
for capacitive loads.
© 2006 Microchip Technology Inc.
DS21685C-page 13
MCP6021/1R/2/3/4
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Evaluation on the bench and
simulations with the MCP6021/1R/2/3/4 Spice macro
model are helpful.
4.5
MCP6023 Chip Select (CS)
The MCP6023 is a single amplifier with chip select
(CS). When CS is high, the supply current is less than
10 nA (typ) and travels from the CS pin to VSS, with the
amplifier output being put into a high-impedance state.
When CS is low, the amplifier is enabled. If CS is left
floating, the amplifier may not operate properly.
Figure 1-1 and Figure 2-39 show the output voltage
and supply current response to a CS pulse.
4.4
Gain Peaking
Figure 2-35 and Figure 2-36 use RF = 1 kΩ to avoid
(frequency response) gain peaking and (step
response) overshoot. The capacitance to ground at the
inverting input (CG) is the op amp’s common mode
input capacitance plus board parasitic capacitance. CG
is in parallel with RG, which causes an increase in gain
at high frequencies for non-inverting gains greater than
1 V/V (unity gain). CG also reduces the phase margin
of the feedback loop for both non-inverting and
inverting gains.
4.6
MCP6021 and MCP6023 Reference
Voltage
The single op amps (MCP6021 and MCP6023), not in
the SOT-23-5 package, have an internal mid-supply
reference voltage connected to the VREF pin (see
Figure 4-6). The MCP6021 has CS internally tied to
VSS, which always keeps the op amp on and always
provides a mid-supply reference. With the MCP6023,
taking the CS pin high conserves power by shutting
down both the op amp and the VREF circuitry. Taking
the CS pin low turns on the op amp and VREF circuitry.
VIN
VOUT
VDD
RF
CG
RG
50 kΩ
VREF
FIGURE 4-4:
with parasitic capacitance.
Non-inverting gain circuit
50 kΩ
The largest value of RF in Figure 4-4 that should be
used is a function of noise gain (see GN in Section 4.3
“Capacitive Loads”) and CG. Figure 4-5 shows results
for various conditions. Other compensation techniques
may be used, but they tend to be more complicated to
the design.
CS
VSS
(CS tied internally to VSS for MCP6021)
FIGURE 4-6:
circuit (MCP6021 and MCP6023 only).
Simplified internal VREF
1.E+05
100k
GN > +1 V/V
See Figure 4-7 for a non-inverting gain circuit using the
internal mid-supply reference. The DC-blocking
capacitor (CB) also reduces noise by coupling the op
amp input to the source.
CG = 7 pF
CG = 20 pF
1.E1+00k4
1k
1.E+03
RG
RF
CG = 50 pF
G = 100 pF
C
100
1.E+02
1
10
VOUT
Noise Gain; GN (V/V)
CB
VREF
FIGURE 4-5:
with parasitic capacitance.
Non-inverting gain circuit
VIN
FIGURE 4-7:
Non-inverting gain circuit
using VREF (MCP6021 and MCP6023 only).
DS21685C-page 14
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
To use the internal mid-supply reference for an
inverting gain circuit, connect the VREF pin to the
non-inverting input, as shown in Figure 4-8. The
capacitor CB helps reduce power supply noise on the
output.
4.9
PCB Surface Leakage
In applications where low input bias current is critical,
PCB (printed circuit board) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6021/1R/2/3/4 family’s bias current at +25°C
(1 pA, typ).
RG
RF
VIN
VOUT
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-10 shows an example of this type of layout.
VREF
CB
Guard Ring
VIN– VIN+
FIGURE 4-8:
Inverting gain circuit using
VREF (MCP6021 and MCP6023 only).
If you don’t need the mid-supply reference, leave the
VREF pin open.
4.7
Supply Bypass
FIGURE 4-10:
Layout.
Example Guard Ring
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
1. Non-inverting Gain and Unity-Gain Buffer.
a) Connect the guard ring to the inverting input
pin (VIN–); this biases the guard ring to the
common mode input voltage.
b) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
4.8
Unused Op Amps
2. Inverting (Figure 4-10) and Transimpedance
Gain Amplifiers (convert current to voltage, such
as photo detectors).
An unused op amp in a quad package (MCP6024)
should be configured as shown in Figure 4-9. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage,
and minimizes the supply current draw of the unused
op amp. Circuit B uses the minimum number of compo-
nents and operates as a comparator; it may draw more
current.
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp’s input (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
¼ MCP6144 (A)
VDD
¼ MCP6144 (B)
4.10 High Speed PCB Layout
VDD
Due to their speed capabilities, a little extra care in the
PCB (Printed Circuit Board) layout can make a
significant difference in the performance of these op
amps. Good PC board layout techniques will help you
achieve the performance shown in Section 1.0 “Elec-
trical Characteristics” and Section 2.0 “Typical Per-
formance Curves”, while also helping you minimize
EMC (Electro-Magnetic Compatibility) issues.
VDD
R
R
FIGURE 4-9:
Unused Op Amps.
Use a solid ground plane and connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
© 2006 Microchip Technology Inc.
DS21685C-page 15
MCP6021/1R/2/3/4
Separate digital from analog, low speed from high
speed and low power from high power. This will reduce
interference.
4.11.2
OPTICAL DETECTOR AMPLIFIER
Figure 4-12 shows the MCP6021 op amp used as a
transimpedance amplifier in a photo detector circuit.
The photo detector looks like a capacitive current
source, so the 100 kΩ resistor gains the input signal to
a reasonable level. The 5.6 pF capacitor stabilizes this
circuit and produces a flat frequency response with a
bandwidth of 370 kHz.
Keep sensitive traces short and straight. Separating
them from interfering components and traces. This is
especially important for high-frequency (low rise-time)
signals.
Sometimes it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect the guard
trace to ground plane at both ends, and in the middle
for long traces.
5.6 pF
Photo
Detector
100 kΩ
Use coax cables (or low inductance wiring) to route
signal and power to and from the PCB.
100 pF
4.11 Typical Applications
MCP6021
4.11.1
A/D CONVERTER DRIVER AND
ANTI-ALIASING FILTER
VDD/2
Figure 4-11 shows a third-order Butterworth filter that
can be used as an A/D converter driver. It has a band-
width of 20 kHz and a reasonable step response. It will
work well for conversion rates of 80 ksps and greater (it
has 29 dB attenuation at 60 kHz).
FIGURE 4-12:
for an Optical Detector.
Transimpedance Amplifier
1.0 nF
MCP602X
14.7 kΩ 33.2 kΩ
8.45 kΩ
100 pF
1.2 nF
FIGURE 4-11:
A/D converter driver and
anti-aliasing filter with a 20 kHz cutoff frequency.
This filter can easily be adjusted to another bandwidth
by multiplying all capacitors by the same factor.
Alternatively, the resistors can all be scaled by another
common factor to adjust the bandwidth.
DS21685C-page 16
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
®
5.2
FilterLab Software
5.0
DESIGN TOOLS
Microchip’s FilterLab® software is an innovative tool
that simplifies analog active filter (using op amps)
design. It is available free of charge from our web site
at www.microchip.com. The FilterLab software tool
provides full schematic diagrams of the filter circuit with
component values. It also outputs the filter circuit in
SPICE format, which can be used with the macro
model to simulate actual filter performance.
Microchip provides the basic design tools needed for
the MCP6021/1R/2/3/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model available for the
MCP6021/1R/2/3/4 op amps is on Microchip’s web site
at www.microchip.com. This model is intended as an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. Within the
macro model file is information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
© 2006 Microchip Technology Inc.
DS21685C-page 17
MCP6021/1R/2/3/4
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
Example: (E-temp)
5-Lead SOT-23 (MCP6021/MCP6021R)
Device
E-Temp Code
MCP6021
XXNN
EYNN
EZNN
EY25
MCP6021R
Note: Applies to 5-Lead SOT-23
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
MCP6021
I/P256
MCP6021
E/P^256
e
3
OR
YYWW
0331
0549
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
XXXXYYWW
MCP6021
I/SN0331
MCP6021E
SN^
e
3
0549
OR
NNN
256
256
Example:
8-Lead MSOP
6021E
549256
XXXXXX
YWWNNN
Example:
8-Lead TSSOP
6021
XXXX
YYWW
NNN
E549
256
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS21685C-page 18
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6024)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP6024-I/P
XXXXXXXXXXXXXX
YYWWNNN
0331256
MCP6024
E/P^
3
e
OR
0549256
14-Lead SOIC (150 mil) (MCP6024)
Example:
MCP6024ISL
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
0331256
MCP6024
e
3
E/SL^
OR
0549256
Example:
14-Lead TSSOP (MCP6024)
XXXXXX
YYWW
6024E
0331
NNN
256
© 2006 Microchip Technology Inc.
DS21685C-page 19
MCP6021/1R/2/3/4
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
E
E1
p
B
p1
D
n
1
α
c
A
A2
φ
L
A1
β
Units
INCHES
*
MILLIMETERS
NOM
5
Dimension Limits
MIN
NOM
MAX
MIN
MAX
n
p
Number of Pins
Pitch
5
.038
0.95
p1
Outside lead pitch (basic)
Overall Height
.075
.046
.043
.003
.110
.064
.116
.018
1.90
A
A2
A1
E
.035
.057
0.90
1.18
1.45
1.30
0.15
3.00
1.75
3.10
0.55
Molded Package Thickness
Standoff
.035
.000
.102
.059
.110
.014
.051
.006
.118
.069
.122
.022
10
0.90
0.00
2.60
1.50
2.80
0.35
1.10
0.08
Overall Width
2.80
Molded Package Width
Overall Length
E1
D
1.63
2.95
Foot Length
L
f
0.45
Foot Angle
0
5
0
5
10
c
Lead Thickness
Lead Width
.004
.014
.006
.017
.008
.020
10
0.09
0.35
0.15
0.43
0.20
0.50
B
a
b
Mold Draft Angle Top
Mold Draft Angle Bottom
0
0
5
5
0
5
5
10
10
10
0
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-091
DS21685C-page 20
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.100
.155
.130
2.54
3.94
3.30
Top to Seating Plane
A
.140
.170
3.56
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
2.92
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
3.68
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2006 Microchip Technology Inc.
DS21685C-page 21
MCP6021/1R/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21685C-page 22
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
A
α
c
β
A2
A1
φ
L
Units
INCHES
NOM
MILLIMETERS
NOM
*
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
8
8
.026
0.65
1.05
0.90
0.10
6.38
4.40
3.00
0.60
Overall Height
A
A2
A1
E
.039
.041
.035
.004
.251
.173
.118
.024
.043
.037
.006
.256
.177
.122
.028
1.00
1.10
Molded Package Thickness
Standoff
.033
.002
.246
.169
.114
.020
0.85
0.05
6.25
4.30
2.90
0.50
0.95
0.15
6.50
4.50
3.10
0.70
Overall Width
Molded Package Width
Molded Package Length
Foot Length
E1
D
L
φ
Foot Angle
0°
4°
8°
0°
4°
8°
c
Lead Thickness
.004
.007
.006
.010
.008
.012
0.09
0.19
0.15
0.25
0.20
0.30
Lead Width
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
Controlling Parameter
0°
0°
5°
5°
10°
10°
0°
0°
5°
5°
10°
10°
β
*
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
Revised 07-21-05
© 2006 Microchip Technology Inc.
DS21685C-page 23
MCP6021/1R/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
n
1
B
α
c
φ
A2
A
L
F
A1
β
Units
INCHES
NOM
MILLIMETERS
*
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.026 BSC
0.65 BSC
Overall Height
A
A2
A1
E
-
-
.043
-
-
1.10
0.95
0.15
Molded Package Thickness
Standoff
.030
.033
.037
.006
0.75
0.85
.000
-
0.00
-
Overall Width
.193 BSC
4.90 BSC
Molded Package Width
Overall Length
E1
D
.118 BSC
.118 BSC
3.00 BSC
3.00 BSC
Foot Length
L
.016
.024
.037 REF
.031
0.40
0.60
0.95 REF
0.80
Footprint (Reference)
Foot Angle
F
φ
0°
-
8°
0°
-
-
-
-
-
8°
c
Lead Thickness
Lead Width
.003
.009
.006
.012
.009
.016
0.08
0.22
0.23
0.40
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
5°
5°
-
15°
15°
5°
5°
15°
15°
β
-
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-187
Drawing No. C04-111
Revised 07-21-05
DS21685C-page 24
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
14
14
.100
.155
.130
2.54
3.94
3.30
Top to Seating Plane
A
.140
.170
3.56
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.145
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
3.68
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
© 2006 Microchip Technology Inc.
DS21685C-page 25
MCP6021/1R/2/3/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.150
.337
.010
.016
0
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
DS21685C-page 26
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
L
A1
A2
Units
INCHES
NOM
MILLIMETERS
NOM
14
*
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
14
.026 BSC
.041
0.65 BSC
1.05
Overall Height
A
A2
A1
E
.039
.033
.002
.246
.169
.193
.020
.043
1.00
1.10
Molded Package Thickness
Standoff
.035
.004
.251
.173
.197
.024
.037
.006
.256
.177
.201
.028
0.85
0.05
6.25
4.30
4.90
0.50
0.90
0.95
0.15
6.50
4.50
5.10
0.70
0.10
Overall Width
6.38
Molded Package Width
Molded Package Length
Foot Length
E1
D
4.40
5.00
L
0.60
φ
Foot Angle
0°
4°
8°
0°
4°
0.15
0.25
12° REF
12° REF
8°
c
Lead Thickness
.004
.007
.006
.010
.008
.012
0.09
0.19
0.20
0.30
Lead Width
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
12° REF
12° REF
β
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tole rance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
Revised: 08-17-05
© 2006 Microchip Technology Inc.
DS21685C-page 27
MCP6021/1R/2/3/4
NOTES:
DS21685C-page 28
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
APPENDIX A: REVISION HISTORY
Revision C (March 2006)
The following is the list of modifications:
1. Added SOT-23-5 package option for single op
amps MCP6021 and MCP6021R (E-temp only).
2. Added MSOP-8 package option for E-temp
single op amp (MCP6021).
3. Corrected package drawing on front page for
dual op amp (MCP6022).
4. Clarified spec conditions (ISC, PM and THD+N)
in
Section 2.0
“Typical
Performance
Curves”.
5. Added Section 3.0 “Pin Descriptions”.
6. Updated Section 4.0 “Applications informa-
tion” for THD+N, unused op amps, and gain
peaking discussions.
7. Corrected and updated package marking infor-
mation in Section 6.0 “Packaging Informa-
tion”.
8. Added Appendix A: “REVISION HISTORY”.
Revision B (November 2003)
• Second Release of this Document
Revision A (November 2001)
• Original Release of this Document
© 2006 Microchip Technology Inc.
DS21685C-page 29
MCP6021/1R/2/3/4
NOTES:
DS21685C-page 30
© 2006 Microchip Technology Inc.
MCP6021/1R/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
/XX
a)
MCP6021T-E/OT: Tape and Reel,
Extended temperature,
Temperature
Range
Package
5LD SOT-23.
Extended temperature,
8LD PDIP.
b)
c)
MCP6021-E/P:
MCP6021-E/SN: Extended temperature,
8LD SOIC.
Device:
MCP6021
Single Op Amp
MCP6021T Single Op Amp
(Tape and Reel for SOT-23, SOIC, TSSOP,
a)
MCP6021RT-E/OT:Tape and Reel,
Extended temperature,
5LD SOT-23.
MSOP)
MCP6021R Single Op Amp
MCP6021RT Single Op Amp
(Tape and Reel for SOT-23)
Dual Op Amp
MCP6022T Dual Op Amp
(Tape and Reel for SOIC and TSSOP)
Single Op Amp w/ CS
MCP6023T Single Op Amp w/ CS
(Tape and Reel for SOIC and TSSOP)
Quad Op Amp
MCP6024T Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
a)
b)
c)
MCP6022-I/P:
MCP6022-E/P:
Industrial temperature,
8LD PDIP.
Extended temperature,
8LD PDIP.
MCP6022
MCP6023
MCP6022T-E/ST: Tape and Reel,
Extended temperature,
8LD TSSOP.
MCP6024
a)
b)
c)
MCP6023-I/P:
MCP6023-E/P:
Industrial temperature,
8LD PDIP.
Extended temperature,
8LD PDIP.
Temperature Range:
Package:
I
=
=
-40°C to +85°C
E
-40°C to +125°C
MCP6023-E/SN: Extended temperature,
8LD SOIC.
a)
b)
c)
MCP6024-I/SL: Industrial temperature,
14LD SOIC.
MCP6024-E/SL: Extended temperature,
14LD SOIC.
MCP6024T-E/ST: Tape and Reel,
Extended temperature,
14LD TSSOP.
OT
MS
=
=
Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6021, E-Temp; MCP6021R, E-Temp)
Plastic MSOP, 8-lead
(MCP6021, E-Temp)
P
=
=
=
=
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (150mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP, 8-lead
SN
SL
ST
(MCP6021,I-Temp; MCP6022, I-Temp, E-Temp;
MCP6023, I-Temp, E-Temp;)
ST
=
Plastic TSSOP, 14-lead
© 2006 Microchip Technology Inc.
DS21685C-page 31
MCP6021/1R/2/3/4
NOTES:
DS21685C-page 32
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip devices in life support and/or safety
applications is entirely at the buyer’s risk, and the buyer agrees
to defend, indemnify and hold harmless Microchip from any and
all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under
any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21685C-page 33
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02/16/06
DS21685C-page 34
© 2006 Microchip Technology Inc.
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