MCP4728A1-E/UN_技术文档

MCP4728

12-Bit, Quad Digital-to-Analog Converter with EEPROM Memory

Features

Description

• 12-Bit Voltage Output DAC with Four Buffered

Outputs

The MCP4728 device is a quad, 12-bit voltage output

Digital-to-Analog Convertor (DAC) with nonvolatile

memory (EEPROM). Its on-board precision output

amplifier allows it to achieve rail-to-rail analog output

swing.

• On-Board Nonvolatile Memory (EEPROM) for

DAC Codes and I²C™ Address Bits

• Internal or External Voltage Reference Selection

• Output Voltage Range:

The DAC input codes, device configuration bits, and

I²C address bits are programmable to the nonvolatile

memory (EEPROM) by using I²C serial interface

commands. The nonvolatile memory feature enables

the DAC device to hold the DAC input codes during

power-off time, allowing the DAC outputs to be

available immediately after power-up with the saved

settings. This feature is very useful when the DAC

device is used as a supporting device for other devices

in the application’s network.

- Using Internal V_REF(2.048V):

0.000V to 2.048V with Gain Setting = 1

0.000V to 4.096V with Gain Setting = 2

- Using External V_REF(V_DD):

0.000V to V_DD

• ±0.2 Least Significant Bit (LSB) Differential

Nonlinearity (DNL) (typical)

• Fast Settling Time: 6 µs (typical)

• Normal or Power-Down Mode

• Low Power Consumption

• Single-Supply Operation: 2.7V to 5.5V

• I²C Interface:

The MCP4728 device has a high precision internal

voltage reference (V_REF= 2.048V). The user can select

the internal reference or external reference (V_DD) for

each channel individually.

Each channel can be operated in Normal mode or

Power-Down mode individually by setting the

configuration register bits. In Power-Down mode, most

of the internal circuits in the powered down channel are

turned off for power savings, and the output amplifier

can be configured to present a known low, medium, or

high resistance output load.

- Address bits: User Programmable to

EEPROM

- Standard (100 kbps), Fast (400 kbps) and

High Speed (HS) Mode (3.4 Mbps)

• 10-Lead MSOP Package

• Extended Temperature Range: -40°C to +125°C

The MCP4728 device includes a Power-on Reset

(POR) circuit to ensure reliable power-up and an

on-board charge pump for the EEPROM programming

voltage.

The MCP4728 has a two-wire I²C compatible serial

interface for standard (100 kHz), fast (400 kHz), or high

speed (3.4 MHz) mode.

Applications

• Set Point or Offset Adjustment

• Sensor Calibration

• Closed-Loop Servo Control

• Low Power Portable Instrumentation

• PC Peripherals

The MCP4728 DAC is an ideal device for applications

requiring design simplicity with high precision, and for

applications requiring the DAC device settings to be

saved during power-off time.

• Programmable Voltage and Current Source

• Industrial Process Control

• Instrumentation

The MCP4728 device is available in a 10-lead MSOP

package and operates from a single 2.7V to 5.5V

supply voltage.

• Bias Voltage Adjustment for Power Amplifiers

DS22187E-page 1

MCP4728

Package Type

MCP4728

MSOP

V_DD

SCL

SDA

10 V_SS

1

2

9

8

7

V_OUT

D

V

_OUTC

_OUTB

3

LDAC 4

V

RDY/BSY

5

6 V_OUTA

Functional Block Diagram

LDAC

EEPROM A

INPUT

Output

Logic

V_REF

A

UDAC

Gain

V_DD

Control

OP

AMP A

OUTPUT

REGISTER A

V_OUT

A

STRING DAC A

V_SS

REGISTER A

Power Down

Control

EEPROM B

V_REF

B

UDAC

Output

Logic

Gain

Control

OP

AMP B

OUTPUT

INPUT

V_OUT

B

C

D

STRING DAC B

REGISTER B

SDA

SCL

Power Down

Control

EEPROM C

V

_REFC

Gain

UDAC

Output

Logic

Control

OP

AMP C

INPUT

REGISTER C

OUTPUT

REGISTER C

STRING DAC C

EEPROM D

Power Down

Control

V

_REFD

UDAC

Output

Logic

Gain

Control

INPUT

REGISTER D

OP

AMP D

OUTPUT

REGISTER D

RDY/BSY

STRING DAC D

Internal V_REF

(2.048V)

Power Down

Control

V_REFSelector

V_REF

(V_REFA, V_REFB, V_REFC, V_REFD)

V_DD

DS22187E-page 2

MCP4728

† Notice: Stresses above those listed under “Maximum

ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the

operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect

device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings†

V

...................................................................................6.5V

DD

All inputs and outputs w.r.t V ................. -0.3V to V +0.3V

SS

DD

Current at Input Pins ....................................................±2 mA

Current at Supply Pins .............................................±110 mA

Current at Output Pins ...............................................±25 mA

Storage Temperature ...................................-65°C to +150°C

Ambient Temp. with Power Applied .............-55°C to +125°C

ESD protection on all pins ................ ≥ 4 kV HBM, ≥ 400V MM

Maximum Junction Temperature (T ) .........................+150°C

J

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at V_DD= +2.7V to 5.5V, V_SS= 0V,

R_L= 5 kΩ, C_L= 100 pF, G_X= 1, T_A= -40°C to +125°C. Typical values are at +25°C, V_IH= V_DD, V_IL= V_SS.

Parameter

Symbol

Min

Typical

Max

Units

Conditions

Power Requirements

Operating Voltage

V_DD

2.7

—

5.5

V

Supply Current with

External Reference

I_{DD_EXT}

800

600

400

200

40

1400

µA

V_REF= V_DD, V_DD= 5.5V

All 4 channels are in Normal mode.

(V_REF= V_DD

)

—

µA

nA

µA

3 channels are in Normal mode,

1 channel is powered down.

(Note 1)

2 channels are in Normal mode,

2 channel are powered down.

—

1 channel is in Normal mode,

3 channels are powered down.

Power-Down Current with

External Reference

I_{PD_EXT}

I_{DD_INT}

—

All 4 channels are powered down.

(V_REF= V_DD

V_REF= Internal Reference

_DD= 5.5V

)

Supply Current with

Internal Reference

(V_REF= Internal)

(Note 1)

800

1400

V

All 4 channels are in normal mode.

—

600

400

200

45

—

60

µA

3 channels are in Normal mode,

1 channel is powered down.

2 channels are in Normal mode,

2 channels are powered down.

1 channel is in Normal mode,

3 channels are powered down.

Power-Down Current with

Internal Reference

I_{PD_INT}

All 4 channels are powered down.

V_REF= Internal Reference

Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.

2: The power-up ramp rate measures the rise of V_DDover time.

3: This parameter is ensured by design and not 100% tested.

4: This parameter is ensured by characterization and not 100% tested.

5: Test code range: 100 - 4000 codes, V_REF= V_DD, V_DD= 5.5V.

6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.

7: This parameter is indirectly tested by Offset and Gain error testing.

8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.

9: This time delay is measured from the falling edge of ACK pulse in I²C command to the beginning of V_OUT

.

This time delay is not included in the output settling time specification.

DS22187E-page 3

MCP4728

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at V_DD= +2.7V to 5.5V, V_SS= 0V,

R_L= 5 kΩ, C_L= 100 pF, G_X= 1, T_A= -40°C to +125°C. Typical values are at +25°C, V_IH= V_DD, V_IL= V_SS.

Parameter

Symbol

Min

Typical

Max

Units

Conditions

Power-on Reset

Threshold Voltage

V_POR

—

2.2

—

V

All circuits, including EEPROM, are

ready to operate.

Power-Up Ramp Rate

DC Accuracy

V_RAMP

1

—

V/s

Note 2, Note 4

Resolution

n

12

—

Bits

Code Change: 000h to FFFh

Integral Nonlinearity (INL)

Error

INL

±2

±13

LSB

Note 5

DNL Error

DNL

V_OS

-0.75

—

±0.2

5

±0.75

20

LSB

mV

Note 5

Offset Error

Code = 000h

See Figure 2-24

Offset Error Drift

Gain Error

ΔV_OS/°C

—

±0.16

±0.44

0.4

—

ppm/°C -45°C to +25°C

ppm/°C +25°C to +125°C

G_E

-1.25

+1.25

% of Code = FFFh,

FSR Offset error is not included.

Typical value is at room

temperature

See Figure 2-25

Gain Error Drift

ΔG_E/°C

—

-3

—

ppm/°C

Internal Voltage Reference (V_REF), (Note 3)

Internal Voltage Reference

Temperature Coefficient

V_REF

2.007

—

2.048

125

0.25

45

2.089

—

V

ΔV_REF/°C

ppm/°C -40 to 0°C

LSB/°C

—

ppm/°C 0 to +125°C

LSB/°C

—

0.09

290

—

Reference Output Noise

Output Noise Density

E_NREF

e_NREF

—

µV_p-p

Code = FFFh,

0.1 – 10 Hz, G_x= 1

—

1.2

1.0

400

—

Code = FFFh, 1 kHz, G_x= 1

Code = FFFh, 10 kHz, G_x= 1

μV

HZ

1/f Corner Frequency

f_CORNER

Hz

Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.

2: The power-up ramp rate measures the rise of V_DDover time.

3: This parameter is ensured by design and not 100% tested.

4: This parameter is ensured by characterization and not 100% tested.

5: Test code range: 100 - 4000 codes, V_REF= V_DD, V_DD= 5.5V.

6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.

7: This parameter is indirectly tested by Offset and Gain error testing.

8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.

9: This time delay is measured from the falling edge of ACK pulse in I²C command to the beginning of V_OUT

.

This time delay is not included in the output settling time specification.

DS22187E-page 4

MCP4728

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at V_DD= +2.7V to 5.5V, V_SS= 0V,

R_L= 5 kΩ, C_L= 100 pF, G_X= 1, T_A= -40°C to +125°C. Typical values are at +25°C, V_IH= V_DD, V_IL= V_SS.

Parameter

Symbol

Min

Typical

Max

Units

Conditions

Analog Output (Output Amplifier)

Output Voltage Swing

V_OUT

FSR

—

FSR

V_DD

—

V

Note 7

Full Scale Range

V_REF= V_DD

(Note 7)

FSR = from 0.0V to V_DD

—

V_REF

2 * V_REF

6

—

V

V_REF= Internal, G_x= 1,

FSR = from 0.0 V to V_REF

V_REF= Internal, G_x= 2,

FSR = from 0.0V to 2 * V_REF

Output Voltage

Settling Time

T_SETTLING

Td_ExPD

Td_REF

µs

Note 8

Analog Output Time Delay

from Power-Down Mode

4.5

V_DD= 5V,

Note 4, Note 9

Time delay to settle to new

reference

(Note 4, Note 6)

26

From External to Internal

Reference

44

From Internal to External

Reference

Power Supply Rejection

Capacitive Load Stability

PSRR

C_L

—

-57

—

dB

pF

V_DD= 5V ±10%, V_REF= Internal

1000

R_L= 5 kΩ

No oscillation, Note 4

Slew Rate

SR

p_M

—

0.55

66

—

V/µs

Phase Margin

Degree C_L= 400 pF, R_L= ∞

(°)

Short Circuit Current

I_SC

—

15

24

—

mA

V_DD= 5V,

All V_OUTPins = Grounded.

Tested at room temperature.

Short Circuit Current

Duration

T_{SC_DUR}

R_OUT

Infinite

hours Note 4

DC Output Impedance

(Note 4)

—

1

—

Ω

Normal mode

kΩ

Power-Down mode 1

(PD1:PD0 = 0:1), V_OUTto V_SS

—

100

500

—

kΩ

Power-Down mode 2

(PD1:PD0 = 1:0), V_OUTto V_SS

Power-Down mode 3

(PD1:PD0 = 1:1), V_OUTto V_SS

Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.

2: The power-up ramp rate measures the rise of V_DDover time.

3: This parameter is ensured by design and not 100% tested.

4: This parameter is ensured by characterization and not 100% tested.

5: Test code range: 100 - 4000 codes, V_REF= V_DD, V_DD= 5.5V.

6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.

7: This parameter is indirectly tested by Offset and Gain error testing.

8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.

9: This time delay is measured from the falling edge of ACK pulse in I²C command to the beginning of V_OUT

.

This time delay is not included in the output settling time specification.

DS22187E-page 5

MCP4728

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at V_DD= +2.7V to 5.5V, V_SS= 0V,

R_L= 5 kΩ, C_L= 100 pF, G_X= 1, T_A= -40°C to +125°C. Typical values are at +25°C, V_IH= V_DD, V_IL= V_SS.

Parameter

Symbol

Min

Typical

Max

Units

Conditions

Dynamic Performance (Note 4)

Major Code Transition

Glitch

—

45

—

nV-s 1 LSB code change around major

carry (from 7FFh to 800h)

Digital Feedthrough

Analog Crosstalk

—

<10

—

nV-s

DAC-to-DAC Crosstalk

Digital Interface

Output Low Voltage

V_OL

V_IL

—

0.4

0.3V_DD

0.2V_DD

—

V

I_OL= 3 mA

SDA and RDY/BSY pins

Schmitt Trigger

Low Input

Threshold Voltage

V_DD> 2.7V.

SDA, SCL, LDAC pins

—

V_DD≤ 2.7V.

SDA, SCL, LDAC pins

Schmitt Trigger

High Input

V_IH

0.7V_DD

SDA, SCL, LDAC pins

Threshold Voltage

Input Leakage

I_LI

—

±1

3

µA

pF

SCL = SDA = LDAC = V_DD

SCL = SDA = LDAC = V_SS

,

Pin Capacitance

EEPROM

C_PIN

Note 4

EEPROM Write Time

Data Retention

TWRITE

—

25

50

—

ms

EEPROM write time

200

Years At +25°C, Note 3

LDAC Input

LDAC Low Time

T_LDAC

210

—

ns

Updates analog outputs (Note 3)

Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.

2: The power-up ramp rate measures the rise of V_DDover time.

3: This parameter is ensured by design and not 100% tested.

4: This parameter is ensured by characterization and not 100% tested.

5: Test code range: 100 - 4000 codes, V_REF= V_DD, V_DD= 5.5V.

6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.

7: This parameter is indirectly tested by Offset and Gain error testing.

8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.

9: This time delay is measured from the falling edge of ACK pulse in I²C command to the beginning of V_OUT

.

This time delay is not included in the output settling time specification.

DS22187E-page 6

MCP4728

T_RSCL

T_HIGH

T_FSCL

T_SU:STA

SCL

SDA

T_SU:STO

T_BUF

T_SU:DAT

T_LOW

T_HD:STA

T_HD:DAT

0.7V_DD

T_SP

0.3V_DD

T_AA

T_FSDA

T_RSDA

FIGURE 1-1:

I²C Bus Timing Data.

LDAC

T_LDAC

0.7V_DD

0.3V_DD

V_OUT(UDAC = 1)

Update

No Update

FIGURE 1-2:

LDAC Pin Timing vs. V_OUTUpdate.

DS22187E-page 7

MCP4728

2

I C SERIAL TIMING SPECIFICATIONS

Electrical Specifications: Unless otherwise specified, all limits are specified for T_A= -40 to +125°C, V_SS= 0V,

Standard and Fast Mode: V_DD= +2.7V to +5.5V

High Speed Mode: V_DD= +4.5V to +5.5V.

Parameters

Clock Frequency

Sym

Min

Typ

Max

Units

kHz Standard Mode

C_b= 400 pF, 2.7V – 5.5V

kHz Fast Mode

C_b= 400 pF, 2.7V – 5.5V

Conditions

f_SCL

0

—

100

0

—

400

1.7

MHz High Speed Mode 1.7

C_b= 400 pF, 4.5V – 5.5V

0

3.4

MHz High Speed Mode 3.4

C_b= 100 pF, 4.5V – 5.5V

Bus Capacitive Loading

Cb

—

400

100

pF

Standard Mode

2.7V – 5.5V

Fast Mode

2.7V – 5.5V

High Speed Mode 1.7

4.5V – 5.5V

High Speed Mode 3.4

4.5V – 5.5V

Start Condition Setup Time

(Start, Repeated Start)

T

4700

600

160

4000

600

160

4000

600

160

4000

600

120

60

—

ns

Standard Mode

SU:STA

HD:STA

SU:STO

—

Fast Mode

High Speed Mode 1.7

High Speed Mode 3.4

Standard Mode

Start Condition Hold Time

Stop Condition Setup Time

Clock High Time

—

Fast Mode

High Speed Mode 1.7

High Speed Mode 3.4

Standard Mode

T

—

Fast Mode

High Speed Mode 1.7

High Speed Mode 3.4

Standard Mode

T

HIGH

Fast Mode

High Speed Mode 1.7

High Speed Mode 3.4

Standard Mode

Clock Low Time

T

4700

1300

320

160

LOW

Fast Mode

High Speed Mode 1.7

High Speed Mode 3.4

Note 1: This parameter is ensured by characterization and is not 100% tested.

2: After a Repeated Start condition or an Acknowledge bit.

2

3: If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I C bus line. If

this parameter is too long, the Data Input Setup (T

) or Clock Low time (T

) can be affected.

LOW

SU:DAT

Data Input: This parameter must be longer than t

.

SP

Data Output: This parameter is characterized, and tested indirectly by testing T parameter.

AA

2

4: This specification is not a part of the I C specification. This specification is equivalent to the Data Hold Time (T

)

HD:DAT

plus SDA Fall (or rise) time: T = T

+ T

(OR T

).

RSDA

AA

HD:DAT

FSDA

5: Time between Start and Stop conditions.

DS22187E-page 8

MCP4728

2

I C SERIAL TIMING SPECIFICATIONS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all limits are specified for T_A= -40 to +125°C, V_SS= 0V,

Standard and Fast Mode: V_DD= +2.7V to +5.5V

High Speed Mode: V_DD= +4.5V to +5.5V.

Parameters

SCL Rise Time

Sym

Min

Typ

Max

Units

Conditions

Standard Mode

T

—

20 + 0.1Cb

20

—

1000

300

80

ns

RSCL

(Note 1)

Fast Mode

High Speed Mode 1.7

20

160

High Speed Mode 1.7

(Note 2)

10

—

40

80

ns

High Speed Mode 3.4

(Note 2)

SDA Rise Time

(Note 1)

T

—

1000

300

80

ns

Standard Mode

RSDA

20 + 0.1Cb

Fast Mode

20

High Speed Mode 1.7

High Speed Mode 3.4

Standard Mode

10

40

SCL Fall Time

(Note 1)

T

—

300

80

FSCL

FSDA

20 + 0.1Cb

Fast Mode

20

High Speed Mode 1.7

High Speed Mode 3.4

Standard Mode

10

40

SDA Fall Time

(Note 1)

T

—

300

160

80

20 + 0.1Cb

Fast Mode

20

10

250

100

10

0

High Speed Mode 1.7

High Speed Mode 3.4

Standard Mode

Data Input Setup Time

T

—

SU:DAT

—

Fast Mode

—

High Speed Mode 1.7

High Speed Mode 3.4

Standard Mode

—

Data Hold Time

(Input, Output)

(Note 3)

3450

900

150

70

HD:DAT

0

Fast Mode

0

High Speed Mode 1.7

High Speed Mode 3.4

Standard Mode

0

Output Valid from Clock

(Note 4)

T

0

3750

1200

310

150

AA

0

Fast Mode

0

High Speed Mode 1.7

High Speed Mode 3.4

0

Note 1: This parameter is ensured by characterization and is not 100% tested.

2: After a Repeated Start condition or an Acknowledge bit.

2

3: If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I C bus line. If

this parameter is too long, the Data Input Setup (T

) or Clock Low time (T

) can be affected.

LOW

SU:DAT

Data Input: This parameter must be longer than t

.

SP

Data Output: This parameter is characterized, and tested indirectly by testing T parameter.

AA

2

4: This specification is not a part of the I C specification. This specification is equivalent to the Data Hold Time (T

)

HD:DAT

plus SDA Fall (or rise) time: T = T

+ T

(OR T

).

RSDA

AA

HD:DAT

FSDA

5: Time between Start and Stop conditions.

DS22187E-page 9

MCP4728

2

I C SERIAL TIMING SPECIFICATIONS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all limits are specified for T_A= -40 to +125°C, V_SS= 0V,

Standard and Fast Mode: V_DD= +2.7V to +5.5V

High Speed Mode: V_DD= +4.5V to +5.5V.

Parameters

Bus Free Time

Sym

Min

Typ

Max

Units

Conditions

Standard Mode

T

4700

1300

—

ns

BUF

(Note 5)

Fast Mode

High Speed Mode 1.7

High Speed Mode 3.4

—

Input Filter

T

—

Standard Mode

(Not Applicable)

SP

Spike Suppression

(SDA and SCL)

(Not Tested)

—

50

10

—

ns

Fast Mode

High Speed Mode 1.7

High Speed Mode 3.4

Note 1: This parameter is ensured by characterization and is not 100% tested.

2: After a Repeated Start condition or an Acknowledge bit.

2

3: If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I C bus line. If

this parameter is too long, the Data Input Setup (T

) or Clock Low time (T

) can be affected.

LOW

SU:DAT

Data Input: This parameter must be longer than t

.

SP

Data Output: This parameter is characterized, and tested indirectly by testing T parameter.

AA

2

4: This specification is not a part of the I C specification. This specification is equivalent to the Data Hold Time (T

)

HD:DAT

plus SDA Fall (or rise) time: T = T

+ T

(OR T

).

RSDA

AA

HD:DAT

FSDA

5: Time between Start and Stop conditions.

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Symbol

Min

Typical Max

Units

Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 10L-MSOP

T_A

-40

-65

—

+125

+150

°C

θ_JA

—

202

—

°C/W

DS22187E-page 10

MCP4728

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

Note: Unless otherwise indicated, T_A= -40°C to +125°C, V_DD= +5.0V, V_SS= 0V, R_L= 5 kΩ, C_L= 100 pF.

6

0.3

V_DD= 5.5V, V_REF= Internal, Gain = x1

4

2

0.2

0.1

0

-2

-4

-6

-0.1

-0.2

0

1024

2048

Code

3072

4096

0

1024

2048

Code

3072

4096

FIGURE 2-1:

INL vs. Code (T_A= +25°C).

FIGURE 2-4:

DNL vs. Code (T_A= +25°C).

6

4

0.3

0.2

0.1

0

V_DD= 5.5V, V_REF= Internal, Gain = x2

2

0

-2

-4

-0.1

-0.2

0

-6

0

1024

2048

Code

3072

4096

2048

Code

3072

4096

FIGURE 2-2:

INL vs. Code (T_A= +25°C).

FIGURE 2-5:

DNL vs. Code (T_A= +25°C).

0.2

0.15

0.1

6

4

V_DD= 5.5V, V_REF= V_DD

2

0.05

0

-2

-4

-0.05

-6

0

-0.1

0

2048

Code

3072

4096

1024

2048

Code

3072

4096

FIGURE 2-3:

INL vs. Code (T_A= +25°C).

FIGURE 2-6:

DNL vs. Code (T_A= +25°C).

DS22187E-page 11

MCP4728

Note: Unless otherwise indicated, T_A= -40°C to +125°C, V_DD= +5.0V, V_SS= 0V, R_L= 5 kΩ, C_L= 100 pF.

6

4

0.4

0.3

0.2

0.1

0

V_DD= 2.7V, V_REF= Internal, Gain = x1

2

0

-2

-4

-6

-0.1

-0.2

0

1024

2048

3072

4096

0

1024

2048

3072

4096

Code

FIGURE 2-7:

INL vs. Code (T_A= +25°C).

FIGURE 2-10:

DNL vs. Code (T_A= +25°C).

6

4

0.4

0.3

0.2

0.1

0

V_DD= 2.7V, V_REF= V_DD

2

0

-2

-4

-0.1

-0.2

0

-6

0

1024

2048

Code

3072

4096

1024

2048

Code

3072

4096

FIGURE 2-8:

INL vs. Code (T_A= +25°C).

FIGURE 2-11:

DNL vs. Code (T_A= +25°C).

0.4

0.3

0.2

0.1

0

6

4

V_DD= 5.5V, V_REF= Internal, Gain = x1

+85°C

-40^oC

2

0

-2

-4

-6

-8

+25^oC

+125^oC

-0.1

+125^oC

- 40^oC to +85^oC

-10

0

-0.2

1024

2048

Code

3072

4096

0

1024

2048

Code

3072

4096

FIGURE 2-9:

INL vs. Code and

FIGURE 2-12:

DNL vs. Code and

Temperature.

DS22187E-page 12

MCP4728

Note: Unless otherwise indicated, T_A= -40°C to +125°C, V_DD= +5.0V, V_SS= 0V, R_L= 5 kΩ, C_L= 100 pF.

0.4

0.3

0.2

0.1

0

6

4

V_DD= 5.5V, V_REF= Internal, Gain = x2

+85^oC

- 40^oC

+25^oC

2

0

-2

-4

-6

-8

-10

-0.1

-0.2

-0.3

+125^oC

1024

+125^oC

- 40^oC to +85^oC

0

2048

Code

3072

4096

0

1024

2048

3072

4096

Code

FIGURE 2-13:

INL vs. Code and

FIGURE 2-16:

DNL vs. Code and

Temperature.

6

4

0.5

0.4

0.3

0.2

0.1

0

V_DD= 2.7V, V_REF= Internal, Gain = x1

2

0

-2

-4

-6

-8

- 40^oC

+25^oC

+85^oC

-0.1

-0.2

+125^oC

-0.3

- 40^oC to +85^oC

-10

0

1024

2048

3072

4096

0

1024

2048

3072

4096

Code

FIGURE 2-14:

INL vs. Code and

FIGURE 2-17:

DNL vs. Code and

Temperature.

0.4

0.3

0.2

0.1

0

6

4

V_DD= 5.5V, V_REF= V_DD

+85^oC

2

0

-2

-4

- 40^oC

-0.1

+25^oC

+125^oC

- 40^oC to +85^oC

+125^oC

-6

-0.2

0

1024

2048

Code

3072

4096

1024

2048

Code

3072

4096

FIGURE 2-15:

INL vs. Code and

FIGURE 2-18:

DNL vs. Code and

Temperature.

DS22187E-page 13

MCP4728

Note: Unless otherwise indicated, T_A= -40°C to +125°C, V_DD= +5.0V, V_SS= 0V, R_L= 5 kΩ, C_L= 100 pF.

0.5

0.4

6

4

V_DD= 2.7V, V_REF= V_DD

+85^oC

- 40^oC

0.3

2

0.2

0.1

0

-2

+125^oC

0

-0.1

-0.2

-0.3

-4

-6

-8

+25^oC

+125^oC

1024

- 40^oC to +85^oC

0

1024

2048

3072

4096

0

2048

Code

3072

4096

Code

FIGURE 2-19:

INL vs. Code and

FIGURE 2-22:

DNL vs. Code and

Temperature.

6

5

-10

-20

-30

-40

-50

V_DD= 2.7V, Gain = 1

V_DD= 5.5V, Gain = 2

V_DD= 5.5V, Gain = 1

V_DD= 2.7V, Gain = 1

4

3

2

1

0

V_DD= 5.5V, Gain = 1

V_DD= 5.5V, Gain = 2

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

FIGURE 2-20:

Full Scale Error vs.

FIGURE 2-23:

Zero Scale Error vs.

Temperature (Code = FFFh, V_REF= Internal).

Temperature (Code = 000h, V_REF= Internal).

4

50

V_DD= 5.5V, Gain = 1

V_DD= 5.5V

V_DD= 2.7V

3

2

1

0

40

30

V_DD= 2.7V, Gain = 1

20

10

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

FIGURE 2-21:

Full Scale Error vs.

FIGURE 2-24:

Offset Error (Zero Scale

Temperature (Code = FFFh, V_REF= V_DD).

Error).

DS22187E-page 14

MCP4728

Note: Unless otherwise indicated, T_A= -40°C to +125°C, V_DD= +5.0V, V_SS= 0V, R_L= 5 kΩ, C_L= 100 pF.

16

14

12

10

8

V_REF= Internal, Gain = x2

Temp = +25^oC

Ch. D

V_OUT(2V/Div)

Time (2 µs/Div)

Ch. A

Ch. B

6

Ch. C

4

LDAC

2

0

500 1000 1500 2000 2500 3000 3500

Codes

FIGURE 2-25:

Absolute DAC Output Error

FIGURE 2-28:

Full Scale Settling Time

(V_DD= 5.5V).

(V_REF= Internal, V_DD= 5V, UDAC = 1,

Gain = x1, Code Change: 000h to FFFh).

V_OUT(2V/Div)

Time (2 µs/Div)

LDAC

FIGURE 2-26:

Full Scale Settling Time

FIGURE 2-29:

Full Scale Settling Time

(V_REF= V_DD, V_DD= 5V, UDAC = 1,

Code Change: 000h to FFFh).

(V_REF= V_DD, V_DD= 5V, UDAC = 1,

Code Change: FFFh to 000h).

V_OUT(2V/Div)

Time (2 µs/Div)

LDAC

FIGURE 2-27:

Half Scale Settling Time

FIGURE 2-30:

Half Scale Settling Time

(V_REF= V_DD, V_DD= 5V, UDAC = 1,

Code Change: 000h to 7FFh).

(V_REF= V_DD, V_DD= 5V, UDAC = 1,

Code Change: 7FFh to 000h).

DS22187E-page 15

MCP4728

Note: Unless otherwise indicated, T_A= -40°C to +125°C, V_DD= +5.0V, V_SS= 0V, R_L= 5 kΩ, C_L= 100 pF.

Discharging Time due to

internal pull-down resistor (500 kΩ)

V_OUT(1V/Div)

V_OUT(2V/Div)

Time (2 µs/Div)

LDAC

Time (10 µs/Div)

Last ACK CLK pulse

CLK

FIGURE 2-31:

Full Scale Settling Time

FIGURE 2-34:

Entering Power Down Mode

(V_REF= Internal, V_DD= 5V, UDAC = 1,

Gain = x1, Code Change: FFFh to 000h).

(Code: FFFh, V_REF= Internal, V_DD= 5V,

Gain = x1, PD1= PD0 = 1, No External Load).

V_OUT(1V/Div)

Time (2 µs/Div)

LDAC

FIGURE 2-32:

(V_REF= Internal, V_DD= 5V, UDAC = 1,

Gain = x1, Code Change: 000h to 7FFh).

Half Scale Settling Time

FIGURE 2-35:

(V_REF= Internal, V_DD= 5V, UDAC = 1,

Gain = x1, Code Change: 7FFh to 000h).

Half Scale Settling Time

V_OUT(2V/Div)

V_OUT(1V/Div)

Td_ExPD

Time (5 µs/Div)

CLK

FIGURE 2-36:

(Code: FFFh, V_REF= V_DD, V_DD= 5V, for all

Channels).

Last ACK CLK pulse

FIGURE 2-33:

(Code: FFFh, V_REF= Internal, V_DD= 5V,

Gain = x1, for all Channels.).

Exiting Power Down Mode

DS22187E-page 16

MCP4728

Note: Unless otherwise indicated, T_A= -40°C to +125°C, V_DD= +5.0V, V_SS= 0V, R_L= 5 kΩ, C_L= 100 pF.

Discharging Time due to

internal pull-down resistor (500 kΩ)

V_OUTat Channel D

(5V/Div)

V_OUT(2V/Div)

LDAC

V_OUTat Channel A

(100 mV/Div)

Time (5 µs/Div)

Time (20 µs/Div)

Last ACK CLK pulse

CLK

FIGURE 2-37:

Entering Power Down Mode

FIGURE 2-40:

Channel Cross Talk

(Code: FFFh, V_REF= V_DD, V_DD= 5V,

PD1= PD0 = 1, No External Load).

(V_REF= V_DD, V_DD= 5V).

V_OUT(2V/Div)

V_OUT(50 mV/Div)

Time (2 µs/Div)

Time (10 µs/Div)

CLK

Last ACK CLK pulse

FIGURE 2-38:

V_OUTTime Delay when

FIGURE 2-41:

Code Change Glitch

V_REFchanges from Internal Reference to V_DD

.

(V_REF= External, V_DD= 5V, No External Load),

Code Change: 800h to 7FFh.

V_OUT(2V/Div)

V_OUT(50 mV/Div)

Time (2 µs/Div)

Time (10 µs/Div)

CLK

Last ACK CLK pulse

FIGURE 2-39:

V_OUTTime Delay when

FIGURE 2-42:

Code Change Glitch

V_REFchanges from V_DDto Internal Reference.

(V_REF= Internal, V_DD= 5V, Gain = 1, No External

Load), Code Change: 800h to 7FFh.

DS22187E-page 17

MCP4728

Note: Unless otherwise indicated, T_A= -40°C to +125°C, V_DD= +5.0V, V_SS= 0V, R_L= 5 kΩ, C_L= 100 pF.

900

800

700

600

500

6

5

4

3

2

1

0

All Channels On

V_DD= 5V

V_DD= 5.5V

V_DD= 5V

_REF= V_DD

Code = FFFh

V

V_DD= 4.5V

V_DD= 3.3V

V_DD= 2.7V

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

0

1

2

3

4

5

Load Resistance (kΩ)

FIGURE 2-43:

V_OUTvs. Resistive Load.

FIGURE 2-46:

I_DDvs. Temperature

(V_REF= V_DD, All channels are in Normal Mode,

Code = FFFh).

1000

V_DD= 5.0V

1000

All Channels On

3 Channels On

2 Channels On

800

V_DD= 5.0V

800

600

400

200

0

3 Channels On

600

2 Channels On

400

1 Channel On

200

1 Channel On

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

FIGURE 2-47:

(V_REF= Internal, V_REF= 5V, Code = FFFh).

I

_DDvs. Temperature

FIGURE 2-44:

(V_REF= VDD, V_DD= 5V, Code = FFFh).

I_DDvs. Temperature

1000

800

V_DD= 2.7V

All Channels On

800

All Channels On

600

400

200

0

3 Channels On

600

400

200

3 Channels On

2 Channels On

1 Channel On

2 Channels On

1 Channel On

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

FIGURE 2-48:

(V_REF= Internal, V_DD= 2.7V, Code = FFFh).

I_DDvs. Temperature

FIGURE 2-45:

(V_REF= V_DD, V_DD= 2.7V, Code = FFFh).

I_DDvs. Temperature

DS22187E-page 18

MCP4728

Note: Unless otherwise indicated, T_A= -40°C to +125°C, V_DD= +5.0V, V_SS= 0V, R_L= 5 kΩ, C_L= 100 pF.

6

5

4

3

2

1

0

900

800

700

600

500

V_DD= 5.5V

Code = FFFh

All Channels On

V_DD= 5V

V_DD= 4.5V

V_DD= 3.3V

V_DD= 2.7V

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

0

2

4

6

8

10

12

14

16

Current (mA)

FIGURE 2-49:

I_DDvs. Temperature

FIGURE 2-51:

S o u r c e C u r r e n t C a p a b i l i t y

(V_REF= Internal _,All Channels are in Normal

Mode, Code = FFFh).

(V_REF= V_DD, Code = FFFh).

6

5

4

3

2

1

0

60

Code = 000h

All Channels Off

V_DD= 5.5V

50

40

30

20

V_DD= 5V

V_DD= 4.5V

V_DD= 2.7V

V_DD= 3.3V

0

2

4

6

8

10

12

14

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (^oC)

Sink Current (mA)

FIGURE 2-52:

Sink Current Capability

FIGURE 2-50:

I_DDvs. Temperature

(V_REF= V_DD, Code = 000h).

(V_REF= Internal _,All Channels are in Powered

Down).

DS22187E-page 19

MCP4728

NOTES:

DS22187E-page 20

MCP4728

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Type

Pin No.

Name

Function

1

2

3

4

V_DD

SCL

P

Supply Voltage

I²C Serial Clock Input (Note 1)

OI

SDA

LDAC

OI/OO I²C Serial Data Input and Output (Note 1)

ST

This pin is used for two purposes:

(a) Synchronization Input. It is used to transfer the contents of the DAC input

registers to the output registers (V_OUT).

(b) Select the device for reading and writing I²C address bits. (Note 2)

5

6

RDY/BSY

OO

AO

P

This pin is a status indicator of EEPROM programming activity. An external pull-up

resistor (about 100 kΩ) is needed from RDY/BSY pin to V_DDline. (Note 1)

V

_OUTA

_OUTB

Buffered analog voltage output of channel A. The output amplifier has rail-to-rail

operation.

7

V

Buffered analog voltage output of channel B. The output amplifier has rail-to-rail

operation.

8

V_OUT

V_SS

C

D

Buffered analog voltage output of channel C. The output amplifier has rail-to-rail

operation.

9

Buffered analog voltage output of channel D. The output amplifier has rail-to-rail

operation.

10

Ground reference.

Legend: P = Power, OI = Open-Drain Input, OO = Open-Drain Output, ST = Schmitt Trigger Input Buffer,

AO = Analog Output

Note 1: This pin needs an external pull-up resistor from V_DDline. Leave this pin float if it is not used.

2: This pin can be driven by MCU.

3.1

Supply Voltage Pins (V , V

)

SS

3.2

Serial Clock Pin (SCL)

DD

V_DDis the power supply pin for the device. The voltage

at the V_DDpin is used as a power supply input as well

as a DAC external reference. The power supply at the

V_DDpin should be as clean as possible for a good DAC

performance.

SCL is the serial clock pin of the I²C interface. The

MCP4728 device acts only as a slave and the SCL pin

accepts only external input serial clocks. The input data

from the Master device is shifted into the SDA pin on

the rising edges of the SCL clock, and output from the

MCP4728 occurs at the falling edges of the SCL clock.

It is recommended to use an appropriate bypass

capacitor of about 0.1 µF (ceramic) to ground. An

additional 10 µF capacitor (tantalum) in parallel is also

recommended to further attenuate high-frequency

noise present in application boards. The supply voltage

(V_DD) must be maintained in the 2.7V to 5.5V range for

specified operation.

The SCL pin is an open-drain N-channel driver.

Therefore, it needs a pull-up resistor from the V_DDline

to the SCL pin.

Refer to Section 5.0 “I²C Serial Interface

Communications” for more details on I²C Serial

Interface communication.

V_SSis the ground pin and the current return path of the

device. The user must connect the V_SSpin to a ground

plane through a low-impedance connection. If an

analog ground path is available in the application

printed circuit board (PCB), it is highly recommended

that the V_SSpin be tied to the analog ground path, or

isolated within an analog ground plane of the circuit

board.

Typical range of the pull-up resistor value for SCL and

SDA is from 5 kΩ to 10 kΩ for Standard (100 kHz) and

Fast (400 kHz) modes, and less than 1 kΩ for High

Speed mode (3.4 MHz).

DS22187E-page 21

MCP4728

3.3

Serial Data Pin (SDA)

3.5

RDY/BSY Status Indicator Pin

SDA is the serial data pin of the I²C interface. The SDA

pin is used to write or read the DAC register and

EEPROM data. Except for Start and Stop conditions,

the data on the SDA pin must be stable during the high

duration of the clock pulse. The High or Low state of the

SDA pin can only change when the clock signal on the

SCL pin is Low.

This pin is a status indicator of EEPROM programming

activity. This pin is “High” when the EEPROM has no

programming activity, and “Low” when the EEPROM is

in programming mode. It goes “High” when the

EEPROM program is completed.

The RDY/BSY pin is an open-drain N-channel driver.

Therefore, it needs a pull-up resistor (about 100 kΩ)

from the V_DDline to the RDY/BSY pin. Let this pin float

if it is not used.

The SDA pin is an open-drain N-channel driver.

Therefore, it needs a pull-up resistor from the V_DDline

to the SDA pin.

Refer to Section 5.0 “I²C Serial Interface

Communications” for more details on the I²C Serial

Interface communication.

3.6

Analog Output Voltage Pins

(V A, V B, V C, V D)

OUT

The device has four analog voltage output (V_OUT) pins.

Each output is driven by its own output buffer with a

gain of 1 or 2, depending on the gain and V_REF

selection bit settings. In Normal mode, the DC

impedance of the output pin is about 1Ω. In

Power-Down mode, the output pin is internally

connected to 1 kΩ, 100 kΩ, or 500 kΩ, depending on

the Power-Down selection bit settings.

3.4

LDAC Pin

This pin can be driven by an external control device

such as an MCU I/O pin. This pin is used to:

a) transfer the contents of the input registers to

their corresponding DAC output registers and

b) select a device of interest when reading or writ-

ing I²C address bits.

For more details on reading and writing the I²C address

bits, see Section 5.4.4 “General Call Read Address

Bits” and Section 5.6.8 “Write Command: Write I2C

Address bits (C2=0, C1=1, C0=1)”.

The V_OUTpin can drive up to 1000 pF of capacitive

load. It is recommended to use a load with R_Lgreater

than 5 kΩ.

When the logic status of the LDAC pin changes from

“High” to “Low”, the contents of all input registers

(Channels A – D) are transferred to their corresponding

output registers, and all analog voltage outputs are

updated simultaneously.

If this pin is permanently tied to “Low”, the content of

the input register is transferred to its output register

(V_OUT) immediately at the last input data byte’s

acknowledge pulse.

The user can also use the UDAC bit instead. However,

the UDAC bit updates a selected channel only. See

Section 4.8 “Output Voltage Update” for more

information on the LDAC pin and UDAC bit functions.

DS22187E-page 22

MCP4728

4.2

Reset Conditions

4.0

THEORY OF DEVICE

OPERATION

The device can be reset by two independent events:

a) by Power-on Reset

The MCP4728 device is a 12-bit 4-channel buffered

voltage output DAC with nonvolatile memory

(EEPROM). The user can program the EEPROM with

I²C address bits, configuration and DAC input data of

each channel. The device has an internal charge pump

circuit to provide the programming voltage of the

EEPROM.

b) by I²C General Call Reset Command

Under the reset conditions, the device uploads the

EEPROM data into both of the DAC input and output

registers simultaneously. The analog output voltage of

each channel is available immediately, regardless of

the LDAC and UDAC bit conditions.

When the device is first powered-up, it automatically

loads the stored data in its EEPROM to the DAC input

and output registers, and provides analog outputs with

the saved settings immediately. This event does not

require an LDAC or UDAC bit condition. After the

device is powered-up, the user can update the input

registers using I²C write commands. The analog

outputs can be updated with new register values if the

LDAC pin or UDAC bit is low. The DAC output of each

channel is buffered with a low power and precision

output amplifier. This amplifier provides a rail-to-rail

output with low offset voltage and low noise.

The factory default settings for the EEPROM prior to

the device shipment are shown in Table 4-2.

4.3

Output Amplifier

The DAC output is buffered with a low power precision

amplifier. This amplifier provides low offset voltage and

low noise, as well as rail-to-rail output.

The output amplifier can drive the resistive and high

capacitive loads without oscillation. The amplifier can

provide a maximum load current of 24 mA, which is

enough for most of programmable voltage reference

applications. Refer to Section 1.0 “Electrical

Characteristics” for the specifications of the output

amplifier.

The device uses a resistor string architecture. The

resistor ladder DAC can be driven from V_DDor internal

V_REF, depending on the reference selection. The user

can select internal (2.048V) or external reference (V_DD

)

for each DAC channel individually by software control.

The V_DDis used as the external reference. Each

channel is controlled and operated independently.

4.3.1

PROGRAMMABLE GAIN BLOCK

The rail-to-rail output amplifier of each channel has

configurable gain option. When the internal voltage

reference is selected, the output amplifier gain has two

selection options: Gain of 1 or Gain of 2.

The device has a Power-Down mode feature. Most of

the circuit in each powered down channel are turned

off. Therefore, operating power can be saved

significantly by putting any unused channel to the

Power-Down mode.

When the external reference is selected (V_REF= V_DD),

the Gain of 2 option is disabled, and only the Gain of 1

is used by default.

4.1

Power-on Reset (POR)

4.3.1.1

Resistive and Capacitive Loads

The analog output (V_OUT) pin is capable of driving

capacitive loads up to 1000 pF in parallel with 5 kΩ

load resistance. Figure 2-43 shows the V_OUTvs.

Resistive Load.

The device contains an internal Power-on Reset (POR)

circuit that monitors power supply voltage (V_DD) during

operation. This circuit ensures correct device start-up

at system power-up and power-down events.

If the power supply voltage is less than the POR

threshold (V_POR= 2V, typical), all circuits are disabled

and there will be no analog output. When the V_DD

increases above the V_POR, the device takes a reset

state. During the reset period, each channel uploads all

configuration and DAC input codes from EEPROM,

and analog output (V_OUT) will be available accordingly.

This enables the device to return to the same state that

it was at the last write to the EEPROM, before it was

powered off. The POR status is monitored by the POR

status bit by using the I²C read command. See

Figure 5-15 for the details of the POR status bit.

DS22187E-page 23

MCP4728

4.4

DAC Input Registers and

Non-Volatile EEPROM Memory

Each channel has its own volatile DAC input register

and EEPROM. The details of the input registers and

EEPROM are shown in Table 4-1 and Table 4-2,

respectively.

TABLE 4-1:

INPUT REGISTER MAP (VOLATILE)

Configuration Bits

DAC Input Data (12 bits)

RDY A2 A1 A0 VREF DAC1 DAC0 PD1 PD0

/BSY

GX

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Bit

Name

Bit

I²C

Ref. DAC Channel Power-Down Gain

(Note 2)

Function

Address Bits Select

Select

(Note 1) (Note 2) (Note 2)

(Note 2)

CH. A

CH. B

CH. C

CH. D

Note 1: EEPROM write status indication bit (flag).

2: Loaded from EEPROM during power-up, or can be updated by the user.

TABLE 4-2:

EEPROM MEMORY MAP AND FACTORY DEFAULT SETTINGS

Configuration Bits

DAC Input Data (12 bits)

A2

A1

A0

VREF

PD1

PD0

GX

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Bit Name

Bit

Function

Ref.

Select

Power-Down

Select

Gain

Select

I²C Address Bits

(Note 1)

(Note 2)

(Note 3)

CH. A

CH. B

CH. C

CH. D

0

1

0

Note 1: Device I²C address bits. The user can also specify these bits during the device ordering process. The

factory default setting is “000”. These bits can be reprogrammed by the user using the I²C Address Write

command.

2: Voltage Reference Select: 0 = External V_REF(V_DD), 1 = Internal V_REF(2.048V).

3: Gain Select: 0 = Gain of 1, 1 = Gain of 2.

DS22187E-page 24

MCP4728

TABLE 4-3:

Bit Name

CONFIGURATION BITS

Functions

RDY/BSY

This is a status indicator (flag) of EEPROM programming activity:

1 = EEPROM is not in programming mode

0 = EEPROM is in programming mode

Note: RDY/BSY status can also be monitored at the RDY/BSY pin.

(A2, A1, A0)

V_REF

Device I²C address bits. See Section 5.3 “MCP4728 Device Addressing” for more details.

Voltage Reference Selection bit:

0 = V_DD

1 = Internal voltage reference (2.048V)

Note: Internal voltage reference circuit is turned off if all channels select external reference

(V_REF= V_DD)

.

DAC1, DAC0

PD1, PD0

DAC Channel Selection bits:

00 = Channel A

01 = Channel B

10 = Channel C

11 = Channel D

Power-Down selection bits:

00 = Normal Mode

01 = V_OUTis loaded with 1 kΩ resistor to ground. Most of the channel circuits are powered off.

10 = V_OUTis loaded with 100 kΩ resistor to ground. Most of the channel circuits are powered

off.

11 = V_OUTis loaded with 500 kΩ resistor to ground. Most of the channel circuits are powered

off.

Note: See Table 4-7 and Figure 4-1 for more details.

G_X

Gain selection bit:

0 = x1 (gain of 1)

1 = x2 (gain of 2)

Note: Applicable only when internal V_REFis selected. If V_REF= V_DD, the device uses a gain of 1

regardless of the gain selection bit setting.

UDAC

DAC latch bit. Upload the selected DAC input register to its output register (V_OUT):

0 = Upload. Output (V_OUT) is updated.

1 = Do not upload.

Note: UDAC bit affects the selected channel only.

DS22187E-page 25

MCP4728

• When the external reference (V_REF=V_DD) is

selected:

4.5

Voltage Reference

The device has a precision internal voltage reference

which provides a nominal voltage of 2.048V. The user

can select the internal voltage reference or V_DDas the

voltage reference source of each channel using the

V_REFconfiguration bit. The internal voltage reference

circuit is turned off when all channels select V_DDas

their references. However, it stays turned on if any one

of the channels selects the internal reference.

- V_OUT= 0.000V to V_DD

Note:

The gain selection bit is not applicable

for V_REF= V_DD. In this case, Gain of 1

is used regardless of the gain selection

bit setting.

EQUATION 4-1:

V_OUTFOR V_REF=

INTERNAL REFERENCE

4.6

LSB Size

(V_REFx D_n)

V_OUT

≤ V_DD

x

G

x

=

The LSB is defined as the ideal voltage difference

between two successive codes. LSB sizes of the

MCP4728 device are shown in Table 4-4.

4096

Where:

V_REF

D_n

=

2.048V for internal reference selection

DAC input code

TABLE 4-4:

V_REF

LSB SIZES (EXAMPLE)

G_x

Gain Setting

Gain (G_X)

Selection

LSB Size

Condition

Internal

V_REF

(2.048V)

x1

x2

0.5 mV

1 mV

2.048V/4096

4.096V/4096

EQUATION 4-2:

V_OUTFOR V_REF= V_DD

(V_DD× D_n)

V_OUT= ----------------------------

4096

Where:

V_DD

x1

V_DD/4096

(Note 1)

Note 1: LSB size varies with the V_DDrange.

When V_REF= V_DD, the device uses

G_X= 1 by default. G_X= 2 option is

ignored.

D_n

=

DAC input code

4.8

Output Voltage Update

The following events update the output registers

(V_OUT):

4.7

DAC Output Voltage

Each channel has an independent output associated

with its own configuration bit settings and DAC input

code. When the internal voltage reference is selected

(V_REF= internal), it supplies the internal V_REFvoltage

to the resistor string DAC of the channel. When the

external reference (V_REF=V_DD) is selected, V_DDis used

for the channel’s resistor string DAC.

a. LDAC pin to “Low”: Updates all DAC channels.

b. UDAC bit to “Low”: Updates a selected channel

only.

c. General Call Software Update Command:

Updates all DAC channels.

d. Power-on Reset or General Call Reset

command: Both input and output registers are

updated with EEPROM data. All channels are

affected.

The V_DDneeds to be as clean as possible for accurate

DAC performance. When the V_DDis selected as the

voltage reference, any variation or noises on the V_DD

line can directly affect on the DAC output.

4.8.1

LDAC PIN AND UDAC BIT

The analog output of each channel has

a

The user can use the LDAC pin or UDAC bit to upload

the input DAC register to output DAC register (V_OUT).

However, the UDAC affects only the selected channel

while the LDAC affects all channels. The UDAC bit is

not used in the Fast Mode Writing.

programmable gain block. The rail-to-rail output

amplifier has a configurable gain of 1 or 2. But the gain

of 2 is not applicable if V_DDis selected for the voltage

reference. The formula for the analog output voltage is

given in Equation 4-1 and Equation 4-2.

Table 4-5 shows the output update vs. LDAC pin and

UDAC bit conditions.

4.7.1

OUTPUT VOLTAGE RANGE

The DAC output voltage range varies depending on the

voltage reference selection.

• When the internal reference (V_REF=2.048V) is

selected:

- V_OUT= 0.000V to 2.048V * 4095/4096 for

Gain of 1

- V_OUT= 0.000V to 4.096V * 4095/4096 for

Gain of 2

DS22187E-page 26

MCP4728

4.9

DAC Input Code Vs. DAC Analog

Output

TABLE 4-5:

LDAC AND UDAC

CONDITIONS VS. OUTPUT

UPDATE

Table 4-6 shows an example of the DAC input data

code vs. analog output. The MSB of the input data is

always transmitted first and the format is unipolar

binary.

LDAC Pin UDAC Bit

DAC Output (V_OUT)

0

1

0

1

0

1

Update all DAC channel

outputs

Update all DAC channel

outputs

Update a selected DAC

channel output

No update

TABLE 4-6:

DAC INPUT CODE VS. ANALOG OUTPUT (V_OUT

V_REF= Internal (2.048 V)

)

V_REF= V_DD

DAC Input Code

Gain

Selection

Nominal Output Voltage (V)

(See Note 1)

Gain

Selection

Nominal Output Voltage (V)

111111111111

111111111110

000000000010

000000000001

000000000000

x1

x2

x1

x2

x1

x2

x1

x2

x1

x2

V_REF- 1 LSB

2*V_REF- 1 LSB

V_REF- 2 LSB

2*V_REF- 2 LSB

2 LSB

Ignored

V_DD- 1 LSB

V_DD- 2 LSB

2 LSB

1 LSB

0

2 LSB

1 LSB

0

Note 1: (a) LSB with gain of 1 = 0.5 mV, and (b) LSB with gain of 2 = 1 mV.

DS22187E-page 27

MCP4728

Exiting Power-Down Mode:

4.10 Normal and Power-Down Modes

The device exits Power-Down mode immediately by

the following commands:

Each channel has two modes of operation: (a) Normal

mode where analog voltage is available and (b)

Power-Down mode which turns off most of the internal

circuits for power savings.

• Any write command for normal mode. Only

selected channel is affected

•

I²C General Call Wake-Up Command. All

channels are affected

The user can select the operating mode of each

channel individually by setting the Power-Down

selection bits (PD1 and PD0). For example, the user

can select Normal mode for channel A while selecting

Power-Down mode for all other channels.

• I²C General Call Reset Command. This is a

conditional case. The device exits Power-Down

mode, depending on the Power-Down bit settings

in EEPROM as the configuration bits and DAC

input codes are uploaded from EEPROM. All

channels are affected

See Section 5.6 “Write Commands for DAC

Registers and EEPROM” for more details on the

writing the power-down bits.

When the DAC operation mode is changed from the

Power-Down to Normal mode, there will be a time

delay until the analog output is available. Typical time

delay for the output voltage is approximately 4.5 µs.

This time delay is measured from the acknowledge

pulse of the I²C serial communication command to the

beginning of the analog output (V_OUT). This time delay

is not included in the output settling time specification.

See Section 2.0 “Typical Performance Curves” for

more details.

Most of the internal circuit in the powered down

channel are turned off. However, the internal voltage

reference circuit is not affected by the Power-Down

mode. The internal voltage reference circuit is turned

off only if all channels select external reference (V_REF

= V_DD).

Device actions during Power-Down mode:

• The powered down channel stays in a

power-saving condition by turning off most of its

circuits

TABLE 4-7:

POWER-DOWN BITS

• No analog voltage output at the powered down

channel

PD1

PD0 Function

• The output (V_OUT) pin of the powered down

channel is switched to a known resistive load. The

value of the resistive load is determined by the

state of the Power-Down bits (PD1 and PD0).

Table 4-7 shows the outcome of the Power-Down

bit settings

0

1

0

1

0

Normal Mode

1 kΩ resistor to ground (Note 1)

100 kΩ resistor to ground

(Note 1)

1

500 kΩ resistor to ground

(Note 1)

• The contents of both the DAC registers and

EEPROM are not changed

Note 1: In Power-Down mode: V_OUTis off and

most of internal circuits in the selected

channel are disabled.

• Draws less than 40 nA (typical) when all four

channels are powered down and V_DDis selected

as the voltage reference

Circuits that are not affected during Power-Down

mode:

• The I²C serial interface circuits remain active in

order to receive any command from the Master

V

OUT

OP

Amp

Power-Down

Control Circuit

•

The internal voltage reference circuit stays

turned-on if it is selected as reference by at least

one channel

1 kΩ

100 kΩ 500 kΩ

Resistor String DAC

Resistive

Load

FIGURE 4-1:

Output Stage for

Power-Down Mode.

DS22187E-page 28

MCP4728

2

5.1.1

HIGH-SPEED (HS) MODE

5.0

I C SERIAL INTERFACE

COMMUNICATIONS

The I²C specification requires that a high-speed mode

device must be ‘activated’ to operate in High-Speed

(3.4 Mbit/s) mode. This is done by sending a special

address byte of 00001XXX following the START bit.

The XXX bits are unique to the high-speed mode

Master. This byte is referred to as the high-speed

Master Mode Code (HSMMC). The MCP4728 device

does not acknowledge this byte. However, upon

receiving this command, the device switches to HS

mode and can communicate at up to 3.4 Mbit/s on SDA

and SCL lines. The device will switch out of the HS

mode on the next STOP condition.

The MCP4728 device uses a two-wire I²C serial

interface. When the device is connected to the I²C bus

line, the device works as a slave device. The device

supports standard, fast and high speed modes.

The following sections describe how to communicate

with the MCP4728 device using the I²C serial interface

commands.

2

5.1

Overview of I C Serial Interface

Communications

For more information on the HS mode, or other I²C

An example of the hardware connection diagram is

shown in Figure 7-1. A device that sends data onto the

bus is defined as the transmitter, and a device receiving

data, as the receiver. The bus has to be controlled by a

master (MCU) device which generates the serial clock

(SCL), controls the bus access and generates the

START and STOP conditions. Both master (MCU) and

slave (MCP4728) can operate as transmitter or

receiver, but the master device determines which mode

is activated.

modes, please refer to the Philips I²C specification.

2

5.2

I C BUS CHARACTERISTICS

The specification of the I²C serial communication

defines the following bus protocol:

• Data transfer may be initiated only when the bus

is not busy

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition

Communication is initiated by the master (MCU) which

sends the START bit, followed by the slave (MCP4728)

address byte. The first byte transmitted is always the

slave (MCP4728) address byte, which contains the

device code (1100), the address bits (A2, A1, A0), and

the R/W bit. The device code for the MCP4728 device

is 1100, and the address bits are user-writable.

Accordingly, the following bus conditions have been

defined using Figure 5-1.

5.2.1

BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

When the MCP4728 device receives a Read command

(R/W = 1), it transmits the contents of the DAC input

registers and EEPROM sequentially. When writing to

the device (R/W = 0), the device will expect Write

command type bits in the following byte. The reading

and various writing commands are explained in the

following sections.

5.2.2

START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line, while the

clock (SCL) is HIGH, determines a START condition.

All commands must be preceded by a START

condition.

The MCP4728 device supports all three I²C serial

communication operating modes:

5.2.3

STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line, while the

clock (SCL) is HIGH, determines a STOP condition. All

operations must be ended with a STOP condition.

• Standard Mode: bit rates up to 100 kbit/s

• Fast Mode: bit rates up to 400 kbit/s

• High Speed Mode (HS mode): bit rates up to

3.4 Mbit/s

Refer to the Philips I²C document for more details of

the I²C specifications.

5.2.4

DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition.

DS22187E-page 29

MCP4728

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must send an end of

data to the slave by not generating an acknowledge bit

on the last byte that has been clocked out of the slave.

5.2.5

ACKNOWLEDGE

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse, which is associated with this acknowledge bit.

In this case, the slave (MCP4728) will leave the data

line HIGH to enable the master to generate the STOP

condition.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

(A)

(B)

(D)

(C) (A)

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS OR

ACKNOWLEDGE ALLOWED

VALID TO CHANGE

DATA

FIGURE 5-1:

5.3

Data Transfer Sequence On The Serial Bus.

5.3.1

PROGRAMMING OF I²C ADDRESS

BITS

MCP4728 Device Addressing

The address byte is the first byte received following the

START condition from the master device. The first part

of the address byte consists of a 4-bit device code,

which is set to 1100 for the MCP4728 device. The

device code is followed by three I²C address bits (A2,

A1, A0) which are programmable by the users.

Although the three address bits are programmable at

the user’s application PCB, the user can also specify

the address bits during the product ordering process. If

there is no user’s request, the factory default setting of

the three address bits is “000”, programmed into the

EEPROM. The three address bits allow eight unique

addresses.

When the customer first receives any new MCP4728

device, its default address bit setting is “000” if the

address bit programming was not requested. The

customer can reprogram the I²C address bits into the

EEPROM by using “Write Address Bit” command. This

write command needs current address bits. If the

address bits are unknown, the user can find them by

sending “General Call Read Address” Command. The

LDAC pin is also used to select the device of interest to

be programmed or to read the current address.

The following steps are needed for the I²C address

programming.

(a) Read the address bits using “General Call Read

Address” Command. (This is the case when the

address is unknown.)

Acknowledge bit

Start bit

Read/Write bit

(b) Write I²C address bits using “Write I²C Address

Bits” Command.

Slave Address

Address Byte

R/W ACK

The Write Address command will replace the current

address with a new address in both input registers and

EEPROM.

Slave Address for MCP4728

See Section 5.4.4 “General Call Read Address Bits”

for the details of reading the address bits, and

Section 5.6.8 “Write Command: Write I2C Address

bits (C2=0, C1=1, C0=1)” for writing the address bits.

Device Code

Address Bits

A2

1

0

A1

A0

0

Device Code: Programmed (hard-wired) at the

factory.

Address Bits: Reprogrammable into EEPROM by

the user.

FIGURE 5-2:

Device Addressing.

DS22187E-page 30

MCP4728

2

5.4.1

GENERAL CALL RESET

5.4

I C General Call Commands

The General Call Reset occurs if the second byte is

“00000110” (06h). At the acknowledgement of this

byte, the device will abort the current conversion and

perform the following tasks:

The device acknowledges the general call address

command (0x00 in the first byte). The meaning of the

general call address is always specified in the second

byte. The I²C specification does not allow the use of

“00000000” (00h) in the second byte. Refer to the

Philips I²C document for more details of the General

Call specifications.

• Internal Reset similar to a Power-on Reset (POR).

The contents of the EEPROM are loaded into

each DAC input and output registers immediately

The MCP4728 device supports the following I²C

General Calls:

•

V_OUTwill be available immediately regardless of

the LDAC pin condition

• General Call Reset

• General Call Wake-Up

• General Call Software Update

• General Call Read Address Bits

ACK (MCP4728)

Clock Pulse (CLK Line)

Start

Stop

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

2nd Byte

(Command Type = General Call Reset)

1st Byte

(General Call Command)

Note 1

Data (SDA Line)

Note 1: At this falling edge of the last ACK clock bit:

a. Startup Timer starts a reset sequence and

b. EEPROM data is loaded into the DAC Input and Output Registers immediately.

FIGURE 5-3:

5.4.2

General Call Reset.

GENERAL CALL WAKE-UP

If the second byte is “00001001” (09h), the device will

reset the Power-Down bits (PD1, PD0 = 0,0).

ACK (MCP4728)

Clock Pulse (CLK Line)

Start

Stop

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1st Byte

(General Call Command)

2nd Byte

(Command Type = General Call Wake-Up)

Note 1

Data (SDA Line)

Note 1: Resets Power-Down bits at this falling edge of the last ACK clock bit.

FIGURE 5-4:

General Call Wake-Up.

DS22187E-page 31

MCP4728

5.4.3

GENERAL CALL SOFTWARE

UPDATE

If the second byte is “00001000” (08h), the device

updates all DAC analog outputs (V_OUT) at the same

time.

ACK (MCP4728)

Clock Pulse (CLK Line)

Start

Stop

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

2nd Byte

(Command Type = General Call Software Update)

1st Byte

(General Call Command)

Note 1

Data (SDA Line)

Note 1: At this falling edge of the last ACK clock bit, V_OUTA, V_OUTB, V_OUTC, V_OUTD are updated.

FIGURE 5-5:

General Call Software Update.

DS22187E-page 32

MCP4728

select the device of interest to read on the I²C bus. The

LDAC pin needs a logic transition from “High” to “Low”

during the negative pulse of the 8th clock of the second

byte, and stays “Low” until the end of the 3rd byte. The

maximum clock rate for this command is 400 kHz.

5.4.4

GENERAL CALL READ ADDRESS

BITS

This command is used to read the I²C address bits of

the device. If the second byte is “00001100” (0Ch), the

device will output its address bits stored in EEPROM

and register. This command uses the LDAC pin to

ACK (MCP4728)

Restart

ACK (Master)

Start

Stop

4th Byte

S

0

A

0

1

0

A Sr 1

1

0

X X X

1

A A2 A1 A0 1 A2 A1 A0 0 A P

1st Byte

(General Call Address)

2nd Byte

3rd Byte

Restart Byte

Address Bits Address Bits

in

in Input

EEPROM

Register

Reading Address Bits

Note 3

LDAC Pin

(Notes 1, 2, 3)

Clock and LDAC Transition Details:

ACK Clock

Clock Pulse

Restart Clock

ACK Clock

(CLK Line)

6

7

8

9

Sr

1

2

3

4

5

6

7

8

9

1

2

3

2nd Byte

4th Byte

3rd Byte

Reading Address Bits

Note 2(b, c)

LDAC Pin

Note 3

Note 2(b)

Note 2 (a)

Stay “Low” until the end of the 3rd Byte

Note 1: Clock Pulse and LDAC Transition Details.

2: LDAC pin events at the 2nd and 3rd bytes.

a. Keep LDAC pin “High” until the end of the positive pulse of the 8th clock of the 2nd byte.

b. LDAC pin makes a transition from “High” to “Low” during the negative pulse of the 8th clock of the 2nd

byte (just before the rising edge of the 9th clock) and stays “Low” until the rising edge of clock 9 of the

3rd byte.

c. The MCP4728 device does not acknowledge the 3rd byte if the conditions (a) and (b) are not met.

3: LDAC pin resumes its normal function after “Stop” bit.

FIGURE 5-6:

General Call Read I²C Address.

DS22187E-page 33

MCP4728

5.5

Writing and Reading Registers

and EEPROM

5.6

Write Commands for DAC

Registers and EEPROM

The Master (MCU) can write or read the DAC input

registers or EEPROM using the I²C interface

command.

Table 5-1 summarizes the write command types and

their functions.The write command is defined by using

three write command type bits (C₂, C₁, C₀) and two

write function bits (W1, W0). The register selection bits

(DAC1, DAC0) are used to select the DAC channel.

The following sections describe the communication

examples to write and read the DAC registers and

EEPROM using the I²C interface.

TABLE 5-1:

WRITE COMMAND TYPES

Write

Function

Command Field

Command Name

Function

C2

C1

C0

W1

W0

Fast Mode Write

0

X

Not Used

Fast Write for DAC

Input Registers

This command writes to the DAC input registers sequentially with

limited configuration bits. The data is sent sequentially from channels A

to D. The input register is written at the acknowledge clock pulse of the

channel’s last input data byte. EEPROM is not affected. (Note 1)

Write DAC Input Register and EEPROM

0

1

0

Multi-Write for DAC This command writes to multiple DAC input registers, one DAC input

Input Registers

register at a time. The writing channel register is defined by the DAC

selection bits (DAC1, DAC0). EEPROM is not affected. (Note 2)

1

0

Sequential Write for

DAC Input Registers

and EEPROM

This command writes to both the DAC input registers and EEPROM

sequentially. The sequential writing is carried out from a starting

channel to channel D. The starting channel is defined by the DAC

selection bits (DAC1 and DAC0).

The input register is written at the acknowledge clock pulse of the last

input data byte of each register. However, the EEPROM data is written

altogether at the same time sequentially at the end of the last byte.

(Note 2),(Note 3)

1

Single Write for DAC This command writes to a single selected DAC input register and its

Input Register and

EEPROM

EEPROM. Both the input register and EEPROM are written at the

acknowledge clock pulse of the last input data byte. The writing

channel is defined by the DAC selection bits (DAC1 and DAC0).

(Note 2),(Note 3)

2

Write I C Address Bits (A2, A1, A0)

2

0

1

Not Used Write I C Address Bits This command writes new I C address bits (A2, A1, A0) to the DAC

input register and EEPROM.

Write V_REF, Gain, and Power-Down Select Bits (Note 4)

1

0

Not Used

Write Reference

(V ) selection bits

This command writes Reference (V

) selection bits of each channel.

REF

to Input Registers

1

0

1

Not Used

Write Gain selection This command writes Gain selection bits of each channel.

bits to Input Registers

Write Power-Down

This command writes Power-Down bits of each channel.

bits to Input Registers

Note 1: The analog output is updated when LDAC pin is (or changes to) “Low”. UDAC bit is not used for this command.

2: The DAC output is updated when LDAC pin or UDAC bit is “Low”.

3: The device starts writing to the EEPROM on the acknowledge clock pulse of the last channel. The device does not

execute any command until RDY/BSY bit comes back to “High”.

4: The input and output registers are updated at the acknowledge clock pulse of the last byte. The update does not require

LDAC pin or UDAC bit conditions. EEPROM is not affected.

DS22187E-page 34

MCP4728

5 . 6 . 1

F A S T W R I T E C O M M A N D

(C2=0, C1=0, C0=X, X = DON’T

CARE)

5.6.2

MULTI-WRITE COMMAND: WRITE

DAC INPUT REGISTERS

(C2=0, C1=1, C0=0; W1=0, W0=0)

The Fast Write command is used to update the input

DAC registers from channels A to D sequentially. The

EEPROM data is not affected by this command. This

command is called “Fast Write” because it updates the

input registers with only limited data bits. Only the

Power-Down mode selection bits (PD1 and PD0) and

12 bits of DAC input data are writable.

This command is used to write DAC input register, one

at a time. The EEPROM data is not affected by this

command.

The DAC selection bits (DAC1, DAC0) select the DAC

channel to write. Only a selected channel is affected.

Repeated bytes are used to write more multiple DAC

registers.

The input register is updated at the acknowledge pulse

of each channel’s last data byte. Figure 5-7 shows an

example of the Fast Write command.

The D11 - D0 bits in the third and fourth bytes are the

DAC input data of the selected DAC channel.

Bytes 2 - 4 can be repeated for the other channels.

Figure 5-8 shows an example of the Multi-Write

command.

Updating Analog Outputs:

a. When the LDAC pin is “High” before the last byte

of the channel D, all analog outputs are updated

simultaneously by bringing down the LDAC pin

to “Low” any time.

Updating Analog Outputs:

The analog outputs can be updated by one of the

following events after the falling edge of the

acknowledge clock pulse of the 4th byte.

b. If the command starts with the LDAC pin “Low”,

the channel’s analog output is updated at the

falling edge of the acknowledge clock pulse of

the channel’s last byte.

a. When the LDAC pin or UDAC bit is “Low”.

b. If UDAC bit is “High”, bringing down the LDAC

pin to “Low” any time.

c. Send the General Call Software Update

command: This command updates all channels

simultaneously.

c. By sending the General Call Software Update

command.

Note:

The UDAC bit can be used effectively to

upload the input register to the output

register, but it affects only a selected

channel only, while the LDAC pin and

General Call Software Update command

affect all channels.

Note:

The UDAC bit is not used in this

command.

DS22187E-page 35

MCP4728

5.6.3

SEQUENTIAL WRITE COMMAND:

5.6.4

SINGLE WRITE COMMAND: WRITE

A SINGLE DAC INPUT REGISTER

AND EEPROM

WRITE DAC INPUT REGISTERS

AND EEPROM SEQUENTIALLY

FROM STARTING CHANNEL TO

CHANNEL D

(C2=0, C1=1, C0=0; W1=1, W0=1)

When the device receives this command, it writes the

input data to a selected single DAC input register and

also to its EEPROM. The channel is selected by the

channel selection bits (DAC1 and DAC0). See

Table 5-2 for the channel selection bit function.

Figure 5-10 shows an example of the single write

command.

(C2=0, C1=1, C0=0; W1=1, W0=0)

When the device receives this command, it writes the

input data to the DAC input registers sequentially from

the starting channel to channel D, and also writes to

EEPROM sequentially. The starting channel is

determined by the DAC1 and DAC0 bits. Table 5-2

shows the functions of the channel selection bits for the

sequential write command.

Updating Analog Outputs:

When the device is writing EEPROM, the RDY/BSY bit

stays “Low” until the EEPROM write operation is

completed. The state of the RDY/BSY bit flag can be

monitored by a read command or at the RDY/BSY pin.

Any new command received during the EEPROM write

operation (RDY/BSY bit is “Low”) is ignored. Figure 5-9

shows an example of the sequential write command.

The analog outputs can be updated by one of the

following events after the falling edge of the

acknowledge clock pulse of the 4th byte.

a. When the LDAC pin or UDAC bit is “Low”.

b. If UDAC bit is “High”, bringing down the LDAC

pin to “Low” any time.

c. By sending the General Call Software Update

command.

Updating Analog Outputs:

The analog outputs can be updated by one of the

following events after the falling edge of the

acknowledge clock pulse of the 4th byte.

Note:

The UDAC bit can be used effectively to

upload the input register to the output

register, but it affects only a selected

channel only, while the LDAC pin and

General Call Software Update command

affect all channels.

a. When the LDAC pin or UDAC bit is “Low”.

b. If UDAC bit is “High”, bringing down the LDAC

pin to “Low” any time.

c. By sending the General Call Software Update

command.

Note:

The UDAC bit can be used effectively to

upload the input register to the output

register, but it affects only a selected

channel only, while the LDAC pin and

General Call Software Update command

affect all channels.

TABLE 5-2:

DAC CHANNEL SELECTION

BITS FOR SEQUENTIAL

WRITE COMMAND

DAC1

DAC0

Channels

0

1

0

1

0

1

Ch. A - Ch. D

Ch. B - Ch. D

Ch. C - Ch. D

Ch. D

DS22187E-page 36

MCP4728

5.6.5

WRITE COMMAND: SELECT VREF

BIT (C2=1, C1=0, C0=0)

5.6.8

WRITE COMMAND: WRITE I²C

ADDRESS BITS (C2=0, C1=1, C0=1)

When the device receives this command, it updates the

DAC voltage reference selection bit (V_REF) of each

channel. The EEPROM data is not affected by this

command. The affected channel’s analog output is

updated after the acknowledge pulse of the last byte.

Figure 5-12 shows an example of the write command

for Select V_REFbits.

This command writes new I²C address bits (A2, A1,

A0) to the DAC input registers and EEPROM. When

the device receives this command, it overwrites the

current address bits with the new address bits.

This command is valid only when the LDAC pin makes

a transition from “High” to “Low” at the low time of the

last bit (8th clock) of the second byte, and stays “Low”

until the end of the third byte. The update occurs after

“Stop” bit, if the conditions are met. The LDAC pin is

used to select a device of interest to write. The highest

clock rate of this command is 400 kHz. Figure 5-11

shows the details of the address write command.

5.6.6

WRITE COMMAND: SELECT

POWER-DOWN BITS (C2=1, C1=0,

C0=1)

When the device receives this command, it updates the

Power-Down selection bits (PD1, PD0) of each

channel. The EEPROM data is not affected by this

command. The affected channel is updated after the

acknowledge pulse of the last byte. Figure 5-13 shows

an example of the write command for the Select

Power-Down bits.

Note:

To write a new device address, the current

address of the device is also required. If

the current address is not known, it can be

read out by sending General Call Read

Address Bits command. See 5.4.4

“General Call Read Address Bits” for

more details of reading the I²C address

bits.

5.6.7

WRITE COMMAND: SELECT GAIN

BIT (C2=1, C1=1, C0=0)

When the device receives this command, it updates the

gain selection bits (G_X) of each channel. The EEPROM

data is not affected by this command. The analog

output is updated after the acknowledge pulse of the

last byte. Figure 5-14 shows an example of the write

command for select gain bits.

5.6.9

READ COMMAND

If the R/W bit is set to a logic “High” in the I²C serial

communications command, the device enters

reading mode and reads out the input registers and

EEPROM. Figure 5-15 shows the details of the read

command.

a

Note:

The device address bits are read by using

General Call Read Address Bits

command.

DS22187E-page 37

MCP4728

Command Type Bits:

C2=0

C1=0

C0=X

ACK (MCP4728)

Start

1st byte

A2 A1 A0

(C2 C1)

2nd Byte

PD1 PD0 D11 D10 D9 D8

3rd Byte

S

1

0

A

0

A

D7 D6 D5 D4 D3 D2 D1 D0 A

R/W

DAC Input Register of Channel A

Device Addressing

Fast Write

Command

Update Channel A DAC Input Register at this ACK pulse.

ACK (MCP4728)

3rd Byte

2nd Byte

X

PD1 PD0 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A

DAC Input Register of Channel B

Update Channel B DAC Input Register at this ACK pulse.

ACK (MCP4728)

3rd Byte

2nd Byte

PD1 PD0 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A

X

DAC Input Register of Channel C

Update Channel C DAC Input Register at this ACK pulse.

ACK (MCP4728)

3rd Byte

2nd Byte

X

PD1 PD0 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A

DAC Input Register of Channel D

Update Channel D DAC Input Register at this ACK pulse.

Repeat Bytes

P

Stop

Note 1: X is a don’t care bit. V

can be updated after the last byte’s ACK pulse is issued and by

bringing down the LDAC

OUT

pin to “Low”.

FIGURE 5-7:

Fast Write Command: Write DAC Input Registers Sequentially from Channel A to D.

DS22187E-page 38

MCP4728

Command Type Bits:

C2=0

C1=1

C0=0 W1=0 W0=0

ACK (MCP4728)

Start

1st byte

A2 A1 A0

S

1

0

A

R/W

Device Addressing

ACK (MCP4728)

(C2 C1 C0 W1 W2)

3rd Byte

4th Byte

2nd Byte

0

1

0

DAC1 DAC0 UDAC A V

PD1 PD0 Gx D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A

REF

Channel

Select

Multi-Write

Command

DAC Input Register of Selected Channel

Note 1

Repeat Bytes of the 2nd - 4th Bytes

ACK (MCP4728)

2nd byte

DAC1 DAC0 UDAC A V

3rd Byte

4th Byte

D7 D6 D5 D4 D3 D2 D1 D0 A

X

PD1 PD0 Gx D11 D10 D9 D8

A

REF

Channel

Select

Note 2

Note 3

DAC Input Register of Selected Channel

Note 1

Repeat Bytes of the 2nd - 4th Bytes

P

Stop

Note 1:

V

Update:

OUT

If UDAC = 0 or LDAC Pin = 0: V

is updated after the 4th byte’s ACK is issued.

OUT

2: The user can write to the other channels by sending repeated bytes with new channel selection bits (DAC1, DAC0).

3: X is don’t care bit.

FIGURE 5-8:

Multi-Write Command: Write Multiple DAC Input Registers.

DS22187E-page 39

MCP4728

Command Type Bits:

C2=0

C1=1

C0=0 W1=1 W0=0

ACK (MCP4728)

Start

1st byte

A2 A1 A0

S

1

0

A

R/W

Device Addressing

ACK (MCP4728)

2nd Byte

(C2 C1 C0 W1 W2)

3rd Byte

PD1 PD0 Gx D11 D10 D9 D8

4th Byte

0

1

0

1

0

DAC1 DAC0 UDAC A V

A

D7 D6 D5 D4 D3 D2 D1 D0

A

REF

Sequential Write

Starting Channel

Select

Sequential Write

Command

DAC Input Register of Starting Channel

Note 1

Repeat Bytes of the 3rd - 4th Bytes

for the Starting Channel + 1, ... until Channel D.

ACK (MCP4728)

Stop

P

3rd Byte

4th Byte

D7 D6 D5 D4 D3 D2 D1 D0 A

V

PD1 PD0 Gx D11 D10 D9 D8

A

REF

DAC Input Register of Channel D

(Last Channel)

Notes 1 and 2

Note 1:

V

Update:

OUT

If UDAC = 0 or LDAC Pin = 0: V

is updated after the 4th byte’s ACK is issued.

OUT

2: EEPROM Write:

The MCP4728 device starts writing EEPROM at the falling edge of the 4th byte’s ACK pulse.

FIGURE 5-9:

Sequential Write Command: Write DAC Input Registers and EEPROM Sequentially

from Starting Channel to Channel D. The sequential input register starts with the "Starting Channel" and

ends at Channel D. For example, if DAC1:DAC0 = 00, then it starts with channel A and ends at channel D.

If DAC1:DAC0 = 01, then it starts with channel B and ends at Channel D. Note that this command can

send up to 10 bytes including the device addressing and command bytes. Any byte after the 10th byte is

ignored.

DS22187E-page 40

MCP4728

Command Type Bits:

C2=0

C1=1

C0=0 W1=1 W0=1

ACK (MCP4728)

Start

1st byte

A2 A1 A0

S

1

0

A

R/W

Device Addressing

ACK (MCP4728)

Stop

C2 C1 C0 W1 W0

3rd Byte

PD1 PD0 Gx D11 D10 D9 D8

4th Byte

D7 D6 D5 D4 D3 D2 D1 D0

2nd Byte

0

1

0

1

DAC1 DAC0 UDAC A V

A

P

REF

Channel

Select

Single Write

Command

DAC Input Register of Selected Channel

Note 1 and Note 2

Note 1:

V

Update:

OUT

If UDAC = 0 or LDAC Pin = 0: V

is updated after the 4th byte’s ACK is issued.

OUT

2: EEPROM Write:

The MCP4728 device starts writing EEPROM at the falling edge of the 4th byte’s ACK pulse.

FIGURE 5-10:

Single Write Command: Write to a Single DAC Input Register and EEPROM.

DS22187E-page 41

MCP4728

Command Type Bits:

C2=0

C1=1

C0=1

Start

Stop

A P

1st Byte

2nd Byte

3rd Byte

4th Byte

(C2 C1 C0)

S

1

0

0 A2 A1 A0 0

A

0

1

1 A2 A1 A0 0

1

A

0

1

1 A2 A1 A0 1

0

A

0

1

A2 A1 A0 1 1

R/W

Device

Current

Command Current

Type Address Bits

Command

Type Address Bits

New

Command New Address Bits

Code Address Bits

(for confirmation)

Type

Note 4

LDAC Pin

(Notes 1, 2, 3)

Note 3

Clock and LDAC Transition Details:

ACK (MCP4728)

Clock Pulse

(CLK Line)

Stop

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

-----

9

P

4th Byte

2nd Byte

3rd Byte

Note 4

Note 2(b)

LDAC Pin

Note 2(b)

Note 3

Note 2 (a)

Stay “Low” during this 3rd byte

Note 1: Clock Pulse and LDAC Transition Details.

2: LDAC pin events at the 2nd and 3rd bytes:

a. Keep LDAC pin “High” until the end of the positive pulse of the 8th clock of the 2nd byte.

b. LDAC pin makes a transition from “High” to “Low” during the negative pulse of the 8th clock of the 2nd byte

(just before the rising edge of the 9th clock), and stays “Low” until the rising edge of the 9th clock of the 3rd

byte.

c.

The MCP4728 device does not acknowledge the 3rd byte if the conditions (a) and (b) are not met.

3: LDAC pin resumes its normal function after “Stop” bit.

4: EEPROM Write:

a. Charge Pump initiates the EEPROM write sequence at the falling edge of the 4th byte’s ACK pulse.

b. The RDY/BSY bit (pin) goes “Low” at the falling edge of this ACK clock and back to “High” immediately after

the EEPROM write is completed.

FIGURE 5-11:

Write Command: Write I²C Address Bits to the DAC Registers and EEPROM.

2

Note:

The I C address bits can also be programmed at the factory for customers. See the Product Identification System

on page 65 for details.

DS22187E-page 42

MCP4728

Command Type Bits:

Start

C2=1

C1=0

C0=0

ACK (MCP4728)

Stop

1st byte

(C2 C1 C0)

2nd Byte

S

1

0

A2 A1 A0

0

A

1

0

X

V

A

V

B V

C V D

REF

A

P

REF

R/W

Device Addressing

Write

Command

Note 1

Registers and V are updated

OUT

at this falling edge of ACK pulse.

Note 1:

V

= 0: V

REF DD

= 1: Internal Reference (2.048V)

A = Voltage reference of Channel A

B = Voltage reference of Channel B

C = Voltage reference of Channel C

D = Voltage reference of Channel D

V

REF

2: X is don’t care bit.

FIGURE 5-12:

Write Command: Write Voltage Reference Selection Bit (V_REF) to the DAC Input

Registers.

Command Type Bits:

C2=1

C1=0

C0=1

ACK (MCP4728)

Start

1st byte

A2 A1 A0

S

1

0

A

R/W

Device Addressing

Stop

ACK (MCP4728)

(C2 C1 C0)

3rd Byte

2nd Byte

PD1 A PD0 A PD1 B PD0 B

1

0

1

X

A

PD1 C PD0 C PD1 D PD0 D

X

A

P

Command Channel A

Channel B

Channel C

Channel D

Write

for Power-Down

Selection Bits

Registers and V

are updated

OUT

at this falling edge of ACK pulse.

Note 1: X is don’t care bit.

FIGURE 5-13:

Write Command: Write Power-Down Selection Bits (PD1, PD0) to the DAC Input

Registers. See Table 4-7 for the power-down bit setting.

DS22187E-page 43

MCP4728

Command Type Bits:

C2=1

C1=1

C0=0

ACK (MCP4728)

(C2 C1 C0)

Start

1st Byte

A2 A1 A0

2nd Byte

Stop

S

1

0

A

1

0

X

G

A

G

B

G

C

G D

X

A

P

X

R/W

Command

Write

for Gain Selection Bits

Device Addressing

Note 1

are updated

Registers and V

OUT

at this falling edge of ACK pulse.

Note 1: GX A = Gain Selection for Channel A

GX B = Gain Selection for Channel B

GX C = Gain Selection for Channel C

GX D = Gain Selection for Channel D

Ex: GX A = 0: Gain of 1 for Channel A

= 1: Gain of 2 for Channel A

2: X is don’t care bit.

FIGURE 5-14:

Write Command: Write Gain Selection Bit (G_X) to the DAC Input Registers.

DS22187E-page 44

MCP4728

Read Command

ACK (MCP4728)

Start

S

1

0

A2 A1 A0

1

A

R/W

Device Code Address Bits

2nd Byte

ACK (MASTER)

Stop

3rd Byte

V_REFPD1 PD0 G_XD11 D10 D9 D8

4th Byte

RDY/

BSY

POR DAC1 DAC 0

0

A2 A1 A0

A

D7 D6 D5 D4 D3 D2 D1 D0

A

P

Channel A DAC Input Register

6th Byte

Stop

5th Byte

7th Byte

RDY/

BSY

POR DAC1 DAC 0

0

A2 A1 A0

A

V_REFPD1 PD0 G_XD11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

A

P

Channel A DAC EEPROM

3rd Byte

Stop

2nd Byte

4th Byte

RDY/

BSY

POR DAC1 DAC 0

0

A2 A1 A0

A

V_REFPD1 PD0 G_XD11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

A

P

Channel B DAC Input Register

6th Byte

Stop

5th Byte

7th Byte

RDY/

BSY

POR DAC1 DAC 0

0

A2 A1 A0

A

V_REFPD1 PD0 G_XD11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

A

P

Channel B DAC EEPROM

3rd Byte

Stop

2nd Byte

4th Byte

RDY/

BSY

POR DAC1 DAC 0

0

A2 A1 A0

A

V_REFPD1 PD0 G_XD11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

A

P

Channel C DAC Input Register

6th Byte

Stop

5th Byte

7th Byte

RDY/

BSY

POR DAC1 DAC 0

0

A2 A1 A0

A

V_REFPD1 PD0 G_XD11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

A

P

Channel C DAC EEPROM

3rd Byte

Stop

2nd Byte

4th Byte

RDY/

BSY

POR DAC1 DAC 0

0

A2 A1 A0

A

V_REFPD1 PD0 G_XD11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

A

P

Channel D DAC Input Register

6th Byte

Stop

5th Byte

7th Byte

RDY/

BSY

POR DAC1 DAC 0

0

A2 A1 A0

A

V_REFPD1 PD0 G_XD11 D10 D9 D8

Channel D DAC EEPROM

D7 D6 D5 D4 D3 D2 D1 D0 A P

Repeat

Note 1: The 2nd - 4th bytes are the contents of the DAC Input Register and the 5th - 7th bytes are the EEPROM contents.

The device outputs sequentially from channel A to D.

POR Bit: 1 = Set (Device is powered on with V > V

), 0 = Powered off state.

POR

DD

FIGURE 5-15:

Read Command and Device Outputs.

DS22187E-page 45

MCP4728

NOTES:

DS22187E-page 46

MCP4728

6.0

6.1

TERMINOLOGY

Resolution

7

6

INL = < -1 LSB

The resolution is the number of DAC output states that

divide the full scale range. For the 12-bit DAC, the

resolution is 2¹², meaning the DAC code ranges from 0

to 4095.

INL = - 1 LSB

5

Analog 4

Output

INL = 0.5 LSB

3

2

1

0

(LSB)

6.2

Least Significant Bit (LSB)

The least significant bit is the ideal voltage difference

between two successive codes.

EQUATION 6-1:

000 001 010 011 100 101 110 111

DAC Input Code

V_REF

2ⁿ

LSB = ------------

Ideal Transfer Function

Actual Transfer Function

(V_{Full Scale}– V_{Zero Scale}

)

= ---------------------------------------------------------

2¹²– 1

FIGURE 6-1:

INL Accuracy.

(V_{Full Scale}– V_{Zero Scale}

)

= ---------------------------------------------------------

4095

6.4 Differential Nonlinearity (DNL)

Where:

V_REF

Differential nonlinearity (DNL) error (see Figure 6-2) is

the measure of step size between codes in actual

transfer function. The ideal step size between codes is

1 LSB. A DNL error of zero would imply that every code

is exactly 1 LSB wide. If the DNL error is less than

1 LSB, the DAC guarantees monotonic output and no

missing codes. The DNL error between any two

adjacent codes is calculated as follows:

=

V_DDIf external reference is

selected

2.048V If internal reference is

selected

n

The number of digital input bits,

n = 12 for MCP4728

6.3

Integral Nonlinearity (INL)

EQUATION 6-3:

DNL ERROR

Integral nonlinearity (INL) error is the maximum

deviation of an actual transfer function from an ideal

transfer function (straight line). In the MCP4728, INL is

calculated using two end-points (zero and full scale).

INL can be expressed as a percentage of full scale

range (FSR) or in fractions of an LSB. INL is also called

relative accuracy. Equation 6-2 shows how to calculate

the INL error in LSB and Figure 6-1 shows an example

of INL accuracy.

ΔV_OUT– LSB

DNL = ----------------------------------

LSB

Where:

DNL is expressed in LSB.

ΔV

=

The measured DAC output

voltage difference between two

adjacent input codes

OUT

EQUATION 6-2:

INL ERROR

(V_OUT– V_Ideal

)

INL = ---------------------------------------

LSB

Where:

INL is expressed in LSB

V_Ideal

=

Code*LSB

V

The output voltage measured at

the given input code

OUT

DS22187E-page 47

MCP4728

For the MCP4728 device, the gain error is not

calibrated at the factory and most of the gain error is

contributed by the output buffer (op amp) saturation

near the code range beyond 4000. For applications that

need the gain error specification less than 1%

maximum, a user may consider using the DAC code

range between 100 and 4000 instead of using full code

range (code 0 to 4095). The DAC output of the code

range between 100 and 4000 is much more linear than

full scale range (0 to 4095). The gain error can be

calibrated out by using applications’ software.

7

6

DNL = 0.5 LSB

5

DNL = 2 LSB

4

3

Analog

Output

(LSB)

2

1

0

6.7

Full Scale Error (FSE)

Full scale error (see Figure 6-4) is the sum of offset

error plus gain error. It is the difference between the

ideal and measured DAC output voltage with all bits set

to one (DAC input code = FFFh).

000

001

011

010

100

101 110

111

DAC Input Code

Ideal Transfer Function

Actual Transfer Function

EQUATION 6-4:

(V_OUT– V_Ideal

FSE = ---------------------------------------

LSB

)

FIGURE 6-2:

6.5

DNL Accuracy.

Where:

Offset Error

FSE is expressed in LSB.

Offset error (see Figure 6-3) is the deviation from zero

voltage output when the digital input code is zero (zero

scale voltage). This error affects all codes by the same

amount. For the MCP4728 device, the offset error is

not trimmed at the factory. However, it can be calibrated

by software in application circuits.

V_Ideal

V_REF

=

(V_REF) (1 - 2^-n) - Offset Voltage (V_OS

Voltage Reference

)

Full Scale

Error

Actual Transfer Function

Analog

Output

Gain Error

Analog

Output

Actual Transfer Function

Ideal Transfer Function

Offset

after Offset Error is removed

Error

Ideal Transfer Function

DAC Input Code

0

DAC Input Code

0

FIGURE 6-3:

Offset Error.

6.6 Gain Error

FIGURE 6-4:

Gain Error and Full Scale

Gain error (see Figure 6-4) is the difference between

the actual full scale output voltage from the ideal output

voltage of the DAC transfer curve. The gain error is

calculated after nullifying the offset error, or full scale

error minus the offset error.

Error.

6.8

Gain Error Drift

Gain error drift is the variation in gain error due to a

change in ambient temperature. The gain error drift is

typically expressed in ppm/°C.

The gain error indicates how well the slope of the actual

transfer function matches the slope of the ideal transfer

function. The gain error is usually expressed as percent

of full scale range (% of FSR) or in LSB.

DS22187E-page 48

MCP4728

6.9

Offset Error Drift

6.13 Analog Crosstalk

Offset error drift is the variation in offset error due to a

change in ambient temperature. The offset error drift is

typically expressed in ppm/^oC.

Analog crosstalk is a glitch that appears at the output of

one DAC due to a change in the output of the other

DAC. The area of the glitch is expressed in nV-Sec,

and measured by loading one of the input registers with

a full scale code change (all 0s to all 1s and vice versa)

while keeping both the UDAC bit and the LDAC pin

high. Then bring down the LDAC pin to low and mea-

sure the output of the DAC whose digital code was not

changed.

6.10 Settling Time

The Settling time is the time delay required for the DAC

output to settle to its new output value from the start of

code transition, within specified accuracy. In the

MCP4728 device, the settling time is a measure of the

time delay until the DAC output reaches its final value

within 0.5 LSB when the DAC code changes from 400h

to C00h.

6.14 DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch that appears at the

output of one DAC due to an input code change and

subsequent output change of the other DAC. This

includes both digital and analog crosstalks. The area of

the glitch is expressed in nV-Sec, and measured by

loading one of the input registers with a full scale code

change (all 0s to all 1s and vice versa) while keeping

UDAC bit or LDAC pin low.

6.11 Major-Code Transition Glitch

Major-code transition glitch is the impulse energy

injected into the DAC analog output when the code in

the DAC register changes state. It is normally specified

as the area of the glitch in nV-Sec. and is measured

when the digital code is changed by 1 LSB at the major

carry transition (Example: 011...111 to 100...

000, or 100... 000to 011... 111).

6.15 Power-Supply Rejection Ratio

(PSRR)

PSRR indicates how the output of the DAC is affected

by changes in the supply voltage. PSRR is the ratio of

the change in V_OUTto a change in V_DDfor full scale

output of the DAC. It is measured on one DAC that is

using an internal V_REFwhile the V_DDis varied ±10%,

and expressed in dB or µV/V.

6.12 Digital Feedthrough

Digital feedthrough is a glitch that appears at the

analog output caused by coupling from the digital input

pins of the device. The area of the glitch is expressed

in nV-Sec, and is measured with a full scale change

(Example: all 0s to all 1s and vice versa) on the digital

input pins. The digital feedthrough is measured when

the DAC is not being written to the output register. This

condition can be created by writing the input register

with both the UDAC bit and the LDAC pin high.

DS22187E-page 49

MCP4728

NOTES:

DS22187E-page 50

MCP4728

7.1

Connecting to I²C BUS Using

Pull-Up Resistors

7.0

TYPICAL APPLICATIONS

The MCP4728 device is a part of Microchip’s latest

DAC family with nonvolatile EEPROM memory. The

device is a general purpose resistor string DAC

intended to be used in applications where a precise

and low power DAC, with moderate bandwidth, is

required.

The SCL, SDA, and RDY/BSY pins of the MCP4728

device are open-drain configurations. These pins

require a pull-up resistor, as shown in Figure 7-1. The

LDAC pin has a Schmitt trigger input configuration and

it can be driven by an external MCU I/O pin.

Since the device includes nonvolatile EEPROM

memory, the user can use this device for applications

that require the output to return to the previous set-up

value on subsequent power-ups.

The pull-up resistor values (R₁and R₂) for SCL and

SDA pins depend on the operating speed (standard,

fast, and high speed) and loading capacitance of the

I²C bus line. Higher value of pull-up resistor consumes

less power, but increases the signal transition time

(higher RC time constant) on the bus line. Therefore, it

can limit the bus operating speed. A lower resistor

value, on the other hand, consumes higher power, but

allows for higher operating speed. If the bus line has

higher capacitance due to long metal traces or multiple

device connections to the bus line, a smaller pull-up

resistor is needed to compensate for the long RC time

constant. The pull-up resistor is typically chosen

between 1 kΩ and 10 kΩ range for standard and fast

modes, and less than 1 kΩ for high speed mode.

Applications generally suited for the MCP4728 device

family include:

• Set Point or Offset Trimming

• Sensor Calibration

• Portable Instrumentation (Battery Powered)

• Motor Speed Control

V

DD

C

2

1

R

1

R

2

V

SS

V

10

9

1

2

DD

D

C

B

A

SCL

SDA

OUT

R

3

OUT

8

7

MCP4728

3

Analog Outputs

LDAC 4

RDY/BSY

5

6

To MCU

2

R and R

Pull-up resistors for I C Serial Communications

=

1

2

= 5 kΩ - 10 kΩ for f_SCL= 100 kHz to 400 kHz

= ~700Ω for f_SCL= 3.4 MHz

(a) Pull-up resistor to monitor RDY/BSY bit = ~ 100 kΩ

R

=

3

(b) Let this pin float when not used

C

0.1 µF, Ceramic capacitor

10 µF, Tantalum capacitor

=

1

2

FIGURE 7-1:

Example of the MCP4728 Device Connection.

DS22187E-page 51

MCP4728

7.1.1

DEVICE CONNECTION TEST

7.3

Power Supply Considerations

The user can test the presence of the MCP4728 device

on the I²C bus line without performing a data

conversion. This test can be achieved by checking an

acknowledge response from the MCP4728 device after

sending a read or write command. Figure 7-2 shows an

example with a read command:

The power source should be as clean as possible. The

power supply to the device is used for both V_DDand

DAC voltage reference by selecting V_REF= V_DD.Any

noise induced on the V_DDline can affect DAC

performance. A typical application will require a bypass

capacitor in order to filter out high-frequency noise on

the V_DDline. The noise can be induced onto the power

supply’s traces or as a result of changes on the DAC

output. The bypass capacitor helps to minimize the

effect of these noise sources on signal integrity.

Figure 7-1 shows an example of using two bypass

capacitors (a 10 µF tantalum capacitor and a 0.1 µF

ceramic capacitor) in parallel on the V_DDline. These

capacitors should be placed as close to the V_DDpin as

possible (within 4 mm). If the application circuit has

separate digital and analog power supplies, the V_DD

and V_SSpins of the MCP4728 device should reside on

the analog plane.

a. Set the R/W bit “High” or “Low” in the address

byte.

b. Check the ACK pulse after sending the address

byte.

If the device acknowledges (ACK = 0) the

command, then the device is connected,

otherwise it is not connected.

c. Send Stop Bit.

Address Byte

SCL

SDA

1

2

1

3

0

4

5

6

7

8

1

9

7.4

Using Power Saving Feature

The device consumes very little power when it is in

Power-Down (shut-down) mode. During the

Power-Down mode, most circuits in the selected

channel are turned off. It is recommended to power

down any unused channel.

1 A2 A1 A0

Start

Bit

Stop

Bit

Address bits

Device Code

R/W

The device consumes the least amount of power if it

enters the Power-Down mode after the internal voltage

reference is disabled. This can be achieved by

selecting V_DDas the voltage reference for all 4

channels, and then issuing the Power-Down mode for

all channels.

MCP4728

Response

FIGURE 7-2:

I²C Bus Connection Test.

7.2 Layout Considerations

Inductively-coupled AC transients and digital switching

noise from other devices can affect DAC performance

and DAC output signal integrity. Careful board layout

will minimize these effects. Bench testing has shown

that a multi-layer board utilizing a low-inductance

ground plane, isolated inputs, isolated outputs and

proper decoupling are critical to achieving good DAC

performance.

7.5

Using Nonvolatile EEPROM

Memory

The user can store the I²C device address bits,

configuration bits and DAC input code of each channel

in the on-board nonvolatile EEPROM memory using

the I²C write command. The contents of EEPROM are

readable and writable using the I²C command.

Separate digital and analog ground planes are

recommended. In this case, the V_SSpin and the ground

pins of the V_DDcapacitors of the MCP4728 should be

terminated to the analog ground plane.

When the MCP4728 device is first powered-up or

receives General Call Reset Command, it uploads the

EEPROM contents to the DAC output registers

automatically and provides analog outputs immediately

with the saved settings in EEPROM. This feature is

very useful in applications where the MCP4728 device

is used to provide set points or calibration data for other

devices in the application systems. The MCP4728

device can save important system parameters when

the application system experiences power failure. See

Section 5.5 “Writing and Reading Registers and

EEPROM” for more details on using the nonvolatile

EEPROM memory.

DS22187E-page 52

MCP4728

7.6.1

DC SET POINT OR CALIBRATION

VOLTAGE SETTINGS

7.6

Application Examples

The MCP4728 device is a rail-to-rail output DAC

designed to operate with a V_DDrange of 2.7V to 5.5V.

Its output amplifier of each channel is robust enough to

drive common, small-signal loads directly, thus

eliminating the cost and size of external buffers for

most applications. Since each channel has its own

configuration bits for selecting the voltage reference,

gain, power-down, etc., the MCP4728 device offers

great simplicity and flexibility to use for various DAC

applications.

A common application for the MCP4728 device is a

digitally-controlled set point or a calibration of variable

parameters such as sensor offset or bias point.

Figure 7-3 shows an example of the set point settings.

Let us consider that the application requires different

trip voltages (Trip 1 - Trip 4). Assuming the DAC output

voltage requirements are given as shown in Table 7-1,

examples of sending the Sequential Write and Fast

Write commands are shown in Figure 7-4 and

Figure 7-5.

TABLE 7-1:

EXAMPLE: SETTING V_OUTOF

EACH CHANNEL

Voltage

Reference

DAC Output

(V_OUT

DAC Channel

)

V_DD

V_DD/2

V_DD- 1 LSB

2.048V

V

_OUTA

_OUTB

_OUTC

Internal

4.096V

V_OUT

D

DS22187E-page 53

MCP4728

V

DD

Light

Comparator 1

R

SENSE

R

1

V

1

TRIP

R

2

0.1 µF

V

DD

Light

Comparator 2

R

SENSE

V

DD

R

1

0.1 µF 10 µF

V

2

TRIP

R

1

R

2

0.1 µF

R

2

V

SS

V

10

9

1

2

DD

R

3

D

C

B

A

SCL

SDA

OUT

R

4

8

7

MCP4728

3

LDAC 4

RDY/BSY

V

DD

Light

5

6

Analog Outputs

Comparator 3

R

SENSE

R

1

V

3

TRIP

To MCU

R

2

0.1 µF

V

DD

Light

D_n= Input Code (0 to 4095)

D_n

Comparator 4

R

SENSE

V_OUT= V_REF× -----------G_x

4096

R

1

V

4

TRIP

R₂

⎛

⎞

V_TRIP= V_OUT------------------

⎝

⎠

R₁+ R₂

R

2

0.1 µF

FIGURE 7-3:

Using the MCP4728 for Set Point or Threshold Calibration.

DS22187E-page 54

MCP4728

ACK (MCP4728)

Start

R/W

V

G

UDAC

REF

X

S

1

0

A

0

1

0

1

0

A

0

1

0

A

0

A

11

1st Byte

Device Addressing

Sequential Write Selecting

Command Channel A as

Starting Channel

Dn = 2 = 2048

for Writing

Update DAC A Input Register at this ACK pulse.

ACK (MCP4728)

V

G

REF

X

0

1 1 1 1 A 1 1 1 1 1 1 1 1 A

Dn = 4095

Update DAC B Input Register at this ACK pulse.

ACK (MCP4728)

V

G

REF

X

1

0

1

1 0 0 0 A 0 0 0 0 0 0 0 0 A

Dn = 2048

Update DAC C Input Register at this ACK pulse.

ACK (MCP4728)

Stop

P

V

G

X

REF

1

0 0 1 1 1 1 1 A 1 1 1 1 1 1 1 1 A

Dn = 4095

Update DAC D Input Register at this ACK pulse.

Expected Output Voltage at Each Channel:

D_n

V_DD

2048

V_OUTA = V_DD× ----------- = V_DD× -----------

= ---------- (V)

4096

D_n

4096

4095

2

V_OUTB = V_DD× ----------- = V_DD× -----------

=

(V_DD– LSB) (V)

4096

D_n

4096

2048

4096

4095

V_OUTC = V_REF× ----------- G_x= 2.048 × ----------- × 2 = 2.048 (V)

4096

D_n

V_OUTD = V_REF× ----------- G_x= 2.048 × ----------- × 2 = 4.096 (V)

4096

FIGURE 7-4:

Sequential Write Command for Setting Test Points in Figure 7-3.

DS22187E-page 55

MCP4728

Start

Stop

1st Byte

0 A2 A1 A0 0

2nd Byte

3rd Byte

S

1

0

A

0

1

1 A2 A1 A0 0

1

A

0

1

1 A2 A1 A0 1

0

A

. . . . . . .

P

Address Byte

Fast Mode

Write Command

DAC A

Next DAC Channels

The following example shows the expected analog outputs with the corresponding DAC input codes:

DAC A Input Code = 001111-11111111

DAC B Input Code = 000111-11111111

DAC C Input Code = 000011-11111111

DAC D Input Code = 000001-11111111

(V

× D )

REF

n

V

= --------------------------------- G

OUT

x

4096

(A) Channel A Output:

Dn for Channel A = 0FFF (hex) = 4095 (decimal)

(V

× 4095)

DD

= ----------------------------------- = V

4096 – 1

1

⎞

⎛

⎞

⎛

V

A

-------------------- = V

1 – ----------- = V

– LSB

OUT

(B) Channel B Output:

Dn for Channel B = 07FF (hex) = 2047 (decimal)

DD⎝

⎠

DD⎝

⎠

4096

DD

4096

(V

× 2047)

V

DD

= ----------------------------------- = V

2048 – 1

DD

2

⎞

DD

2

⎛

⎞

⎛

V

B

-------------------- = ------------ 1 – ----------- = ------------ – LSB

OUT

DD⎝

⎠

⎝

⎠

4096

(C) Channel C Output:

Dn for Channel C = 03FF (hex) = 1023 (decimal)

V

× 1023

V

DD

= ---------------------------------- = V

1024 – 1

DD

4

⎞

DD

4

⎛

⎞

⎛

V

C

-------------------- = ------------ 1 – ----------- = ------------ – LSB

OUT

(D) Channel D Output:

Dn for Channel D = 01FF (hex) = 511 (decimal)

DD⎝

⎠

⎝

⎠

4096

V

× 511

V

DD

= ------------------------------- = V

512 – 1

DD

8

DD

8

⎛

⎞

⎛

⎞

V

D

----------------- = ------------ 1 – ----------- = ------------ – LSB

OUT

DD⎝

⎠

⎝

⎠

4096

FIGURE 7-5: Example of Writing Fast Write Command for Various V_OUT. V_REF= V_DDFor All Channels.

DS22187E-page 56

MCP4728

8.0

8.1

DEVELOPMENT SUPPORT

Evaluation & Demonstration

Boards

The MCP4728 Evaluation Board is available from

Microchip Technology Inc. This board works with

Microchip’s PICkit™ Serial Analyzer. The user can

easily program the DAC input registers and EEPROM

using the PICkit Serial Analyzer, and test out the DAC

analog output voltages.The PICkit Serial Analyzer uses

the PC Graphic User Interface software. Refer to

www.microchip.com for further information on this

product’s capabilities and availability.

FIGURE 8-2:

Setup for the MCP4728

Evaluation Board with PICkit™ Serial Analyzer.

FIGURE 8-1:

MCP4728 Evaluation

Board.

FIGURE 8-3:

Example of PICkit™ Serial User Interface.

DS22187E-page 57

MCP4728

NOTES:

DS22187E-page 58

MCP4728

9.0

9.1

PACKAGING INFORMATION

Package Marking Information

10-Lead MSOP

Example

Device

Code

XXXXXX

YWWNNN

4728UN

007256

MCP4728-E/UN

4728UN

4728A0

4728A1

4728A2

4728A3

4728A4

4728A5

4728A6

4728A7

MCP4728T-E/UN

MCP4728A0-E/UN

MCP4728A0T-E/UN

MCP4728A1-E/UN

MCP4728A1T-E/UN

MCP4728A2-E/UN

MCP4728A2T-E/UN

MCP4728A3-E/UN

MCP4728A3T-E/UN

MCP4728A4-E/UN

MCP4728A4T-E/UN

MCP4728A5-E/UN

MCP4728A5T-E/UN

MCP4728A6-E/UN

MCP4728A6T-E/UN

MCP4728A7-E/UN

MCP4728A7T-E/UN

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22187E-page 59

MCP4728

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DS22187E-page 60

MCP4728

10-Lead Plastic Micro Small Outline Package (UN) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22187E-page 61

MCP4728

NOTES:

DS22187E-page 62

MCP4728

APPENDIX A: REVISION HISTORY

Revision E (October 2010)

The following is the list of modifications:

1. Corrected values in I²C Serial Timing

Specifications table (SCL Fall Time, SDA Fall

Time, Data Hold Time, Output Valid from Clock).

2. Updated the Package Marking Information table

in the “Packaging Information” section.

3. Updated the information in the section

“Product Identification System”.

Revision D (October 2009)

The following is the list of modifications:

1. Front page - Applications: Added new item:

Bias Voltage Adjustment for Power Amplifiers.

2. Electrical Characteristics: Changed typical,

max values for Offset Error.

3. Electrical Characteristics: Changed Min, Max

values for Gain Error.

4. Section 2.0 Typical Performance Curves:

Added new Figure 2-25: Absolute Gain Error.

5. Page 45, Figure 5-15: Changed ACK

(MCP4728) to ACK (MASTER).

Revision C (September 2009)

The following is the list of modifications:

6. Updated Figure 5-11 and Figure 7-4.

Revision B (August 2009)

The following is the list of modifications:

7. Updated Figure 2-25 to Figure 2-41 in

Section 2.0 “Typical Performance Curves”.

8. Updated Figure 5-7, Figure 5-8 and Figure 5-11.

Revision A (June 2009)

• Original Release of this Document.

DS22187E-page 63

MCP4728

NOTES:

DS22187E-page 64

MCP4728

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

XX

X

-X

/XX

a)

MCP4728-E/UN:

Extended Temperature,

10LD MSOP package.

Address

Options

Tape and Temperature

Reel Range

Package

b)

MCP4728T-E/UN: Tape and Reel,

Extended Temperature,

10LD MSOP package.

MCP4728A0-E/UN: Address Option = A0

Extended Temperature,

10LD MSOP package.

MCP4728A0T-E/UN:Address Option = A0

Tape and Reel,

Extended Temperature,

10LD MSOP package.

MCP4728A1-E/UN: Address Option = A1

Extended Temperature,

10LD MSOP package.

MCP4728A1T-E/UN:Address Option = A1

Tape and Reel,

Extended Temperature,

10LD MSOP package.

MCP4728A2-E/UN: Address Option = A2

Extended Temperature,

10LD MSOP package.

MCP4728A2T-E/UN:Address Option = A2

Tape and Reel,

Device:

MCP4728: 12-bit, Quad Digital-to-Analog Convertor with

EEPROM memory

c)

d)

Address Options:

XX

A0 *

A1

A2

A3

A4

A5

A6

A7

A2

0

A1

0

A0

0

=

0

1

e)

f)

0

1

0

1

0

1

0

1

0

g)

h)

1

* Default option. Contact Microchip factory for other address

options

Extended Temperature,

10LD MSOP package.

Note:

These address bits are reprogrammable by the

user.

i)

j)

MCP4728A3-E/UN: Address Option = A3

Extended Temperature,

10LD MSOP package.

MCP4728A3T-E/UN:Address Option = A3

Tape and Reel,

Extended Temperature,

10LD MSOP package.

MCP4728A4-E/UN: Address Option = A4

Extended Temperature,

10LD MSOP package.

MCP4728A4T-E/UN:Address Option = A4

Tape and Reel,

Tape and Reel:

Temperature Range:

Package:

T

E

=

Tape and Reel

°

-40 C to +125 C

k)

l)

UN

=

Plastic Micro Small Outline Transistor, 10-lead

Extended Temperature,

10LD MSOP package.

m) MCP4728A5-E/UN: Address Option = A5

Extended Temperature,

10LD MSOP package.

n)

MCP4728A5T-E/UN:Address Option = A5

Tape and Reel,

Extended Temperature,

10LD MSOP package.

o)

p)

MCP4728A6-E/UN: Address Option = A6

Extended Temperature,

10LD MSOP package.

MCP4728A6T-E/UN:Address Option = A6

Tape and Reel,

Extended Temperature,

10LD MSOP package.

q)

r)

MCP4728A7-E/UN: Address Option = A7

Extended Temperature,

10LD MSOP package.

MCP4728A7T-E/UN:Address Option = A7

Tape and Reel,

Extended Temperature,

10LD MSOP package.

DS22187E-page 65

MCP4728

NOTES:

DS22187E-page 66

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-562-6

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22187E-page 67

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Fax: 886-7-330-9305

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

08/04/10

DS22187E-page 68


型号：	MCP4728A1-E/UN
厂家：	MICROCHIP
描述：	SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PDSO10, PLASTIC, MSOP-10 输入元件光电二极管转换器
文件：	总68页 (文件大小：2585K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP4728A1-E/UN [MICROCHIP]

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