MCP4728T-E/UN [MICROCHIP]
SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PDSO10, PLASTIC, MSOP-10;
| 型号： | MCP4728T-E/UN |
| 厂家： | 
MICROCHIP |
| 描述： | SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PDSO10, PLASTIC, MSOP-10 转换器 存储 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总66页 (文件大小：3185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP4728
12-Bit, Quad Digital-to-Analog Converter with EEPROM Memory
Features
Description
• 12-Bit Voltage Output DAC with 4 Buffered
Outputs
The MCP4728 device is a quad, 12-bit voltage output
Digital-to-Analog Convertor (DAC) with non-volatile
memory (EEPROM). Its on-board precision output
amplifier allows it to achieve rail-to-rail analog output
swing.
• On-Board Non-Volatile Memory (EEPROM) for
DAC Codes and I2CTM Address Bits
• Internal or External Voltage Reference Selection
• Output Voltage Range:
The DAC input codes, device configuration bits, and
I2C address bits are programmable to the non-volatile
memory (EEPROM) by using I2C serial interface
commands. The non-volatile memory feature enables
the DAC device to hold the DAC input codes during
power-off time, allowing the DAC outputs to be
available immediately after power-up with the saved
settings. This feature is very useful when the DAC
device is used as a supporting device for other devices
in applications network.
- Using Internal VREF (2.048V):
0.000V to 2.048V with Gain Setting = 1
0.000V to 4.096V with Gain Setting = 2
- Using External VREF (VDD): 0.000V to VDD
• ±0.2 LSB DNL (typical)
• Fast Settling Time: 6 µs (typical)
• Normal or Power-Down Mode
• Low Power Consumption
The MCP4728 device has a high precision internal
voltage reference (VREF = 2.048V). The user can select
the internal reference or external reference (VDD) for
each channel individually.
• Single-Supply Operation: 2.7V to 5.5V
• I2C Interface:
- Address bits: User Programmable to
EEPROM
Each channel can be operated in normal mode or
power-down mode individually by setting the
configuration register bits. In power-down mode, most
of the internal circuits in the powered down channel are
turned off for power-savings and the output amplifier
can be configured to present a known low, medium, or
high resistance output load.
- Standard (100 kbps), Fast (400 kbps) and
High Speed (3.4 Mbps) Modes
• 10-Lead MSOP Package
• Extended Temperature Range: -40°C to +125°C
Applications
The MCP4728 device includes a Power-On-Reset
(POR) circuit to ensure reliable power-up and an
on-board charge pump for the EEPROM programming
voltage.
The MCP4728 has a two-wire I2C compatible serial
interface for standard (100 kHz), fast (400 kHz), or high
speed (3.4 MHz) mode.
• Set Point or Offset Adjustment
• Sensor Calibration
• Closed-Loop Servo Control
• Low Power Portable Instrumentation
• PC Peripherals
• Programmable Voltage and Current Source
• Industrial Process Control
• Instrumentation
The MCP4728 DAC is an ideal device for applications
requiring design simplicity with high precision, and for
applications requiring the DAC device settings to be
saved during power-off time.
The MCP4728 device is available in a 10-lead MSOP
package and operates from a single 2.7V to 5.5V
supply voltage.
© 2009 Microchip Technology Inc.
DS22187C-page 1
MCP4728
Package Type
MSOP-10
MCP4728
VDD
SCL
SDA
10 VSS
1
2
9
VOUT
VOUT
D
C
8
7
3
LDAC 4
VOUT B
RDY/BSY
5
6 VOUT
A
Functional Block Diagram
LDAC
EEPROM A
Output
Logic
V
A
REF
UDAC
Gain
Control
V
DD
OP
AMP A
INPUT
REGISTER A
OUTPUT
REGISTER A
V
A
OUT
STRING DAC A
V
SS
Power Down
Control
EEPROM B
V
B
REF
UDAC
Output
Logic
Gain
Control
OP
AMP B
OUTPUT
REGISTER B
INPUT
REGISTER B
V
V
V
B
C
D
STRING DAC B
OUT
OUT
OUT
SDA
SCL
Power Down
Control
EEPROM C
V
C
UDAC
REF
Output
Logic
Gain
Control
OP
AMP C
INPUT
REGISTER C
OUTPUT
REGISTER C
STRING DAC C
EEPROM D
Power Down
Control
V
D
UDAC
REF
Output
Logic
Gain
Control
INPUT
REGISTER D
OP
AMP D
OUTPUT
REGISTER D
STRING DAC D
RDY/BSY
Internal V
(2.048V)
Power Down
Control
REF
V
Selector
V
REF
REF
(V
A, V
B, V
C, V
D)
REF
REF
REF
REF
V
DD
DS22187C-page 2
© 2009 Microchip Technology Inc.
MCP4728
† Notice: Stresses above those listed under “Maximum rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
VDD...................................................................................6.5V
All inputs and outputs w.r.t VSS .................–0.3V to VDD+0.3V
Current at Input Pins ....................................................±2 mA
Current at Supply Pins .............................................±110 mA
Current at Output Pins ...............................................±25 mA
Storage Temperature ...................................-65°C to +150°C
Ambient Temp. with Power Applied .............-55°C to +125°C
ESD protection on all pins ................ ≥ 4 kV HBM, ≥ 400V MM
Maximum Junction Temperature (TJ) .........................+150°C
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V,
RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS.
Parameter
Symbol
Min
Typical
Max
Units
Conditions
Power Requirements
Operating Voltage
VDD
2.7
—
5.5
V
Supply Current with
External Reference
IDD_EXT
800
600
400
200
40
1400
µA
VREF = VDD, VDD = 5.5V
All 4 channels are in normal mode.
(VREF = VDD
)
—
—
—
—
—
—
—
µA
µA
µA
nA
µA
3 channels are in normal mode,
1 channel is powered down.
(Note 1)
2 channels are in normal mode,
2 channel are powered down.
—
1 channel is in normal mode,
3 channels are powered down.
Power-Down Current with- IPD_EXT
External Reference
—
All 4 channels are powered down.
(VREF = VDD
)
Supply Current with
Internal Reference
(VREF = Internal)
(Note 1)
IDD_INT
800
1400
VREF = Internal Reference
VDD = 5.5V
All 4 channels are in normal mode.
—
—
—
—
600
400
200
45
—
—
—
60
µA
µA
µA
µA
3 channels are in normal mode,
1 channel is powered down.
2 channels are in normal mode,
2 channels are powered down.
1 channel is in normal mode,
3 channels are powered down.
Power-Down Current with
Internal Reference
IPD_INT
All 4 channels are powered down.
VREF = Internal Reference
Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0x000.
2: The power-up ramp rate measures the rise of VDD over time.
3: This parameter is ensured by design and not 100% tested.
4: This parameter is ensured by characterization and not 100% tested.
5: Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V.
6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.
7: This parameter is indirectly tested by Offset and Gain error testing.
8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
9: This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT
.
This time delay is not included in the output settling time specification.
© 2009 Microchip Technology Inc.
DS22187C-page 3
MCP4728
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V,
RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS.
Parameter
Symbol
Min
Typical
Max
Units
Conditions
Power-On-Reset
Threshold Voltage
VPOR
—
2.2
—
V
All circuits including EEPROM are
ready to operate.
Power-Up Ramp Rate
DC Accuracy
Resolution
VRAMP
1
—
—
V/s
Note 2, Note 4
n
12
—
—
—
Bits
LSB
LSB
Code Change: 000h to FFFh
(Note 5)
INL Error
INL
DNL
VOS
±2
±13
DNL Error
-0.75
—
±0.2
0.02
±0.75
0.75
(Note 5)
Offset Error
% of Code = 000h
FSR
Offset Error Drift
Gain Error
ΔVOS/°C
—
—
-3
±0.16
±0.44
-0.1
—
—
3
ppm/°C -45°C to 25°C
ppm/°C +25°C to +125°C
GE
% of VREF = Internal, Gain = x1
FSR Code = FFFh,
Offset error is not included.
-3
-2
—
-0.1
-0.1
3
2
% of VREF = Internal, Gain = x2
FSR Code = FFFh,
Offset error is not included.
% of VREF = VDD
FSR Code = FFFh,
Offset error is not included.
Gain Error Drift
ΔGE/°C
-3
—
ppm/°C
Internal Voltage Reference (VREF), (Note 3)
Internal Voltage Reference
Temperature Coefficient
VREF
2.007
2.048
2.089
V
ΔVREF/°C
—
—
125
0.25
—
—
ppm/°C -40 to 0°C
LSB/°C -40 to 0°C
—
—
45
0.09
—
—
ppm/°C 0 to +125°C
LSB/°C 0 to +125°C
Reference Output Noise
Output Noise Density
ENREF
eNREF
—
290
—
µVp-p
Code = FFFh,
0.1 - 10 Hz, Gx=1
—
—
—
1.2
1.0
400
—
—
—
Code = FFFh, 1 kHz, Gx=1
Code = FFFh, 10 kHz, Gx=1
μV
H
Z
1/f Corner Frequency
fCORNER
Hz
Analog Output (Output Amplifier)
Output Voltage Swing VOUT
—
FSR
—
V
(Note 7)
Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0x000.
2: The power-up ramp rate measures the rise of VDD over time.
3: This parameter is ensured by design and not 100% tested.
4: This parameter is ensured by characterization and not 100% tested.
5: Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V.
6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.
7: This parameter is indirectly tested by Offset and Gain error testing.
8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
9: This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT
.
This time delay is not included in the output settling time specification.
DS22187C-page 4
© 2009 Microchip Technology Inc.
MCP4728
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V,
RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS.
Parameter
Symbol
Min
Typical
Max
Units
Conditions
Full Scale Range
FSR
—
VDD
—
V
VREF = VDD
(Note 7)
FSR = from 0.0V to VDD
—
—
—
—
—
—
VREF
2 * VREF
6
—
—
—
—
—
—
V
V
VREF = Internal, Gx =1,
FSR = from 0.0 V to VREF
VREF = Internal, Gx =2,
FSR = from 0.0V to 2*VREF
Output Voltage Settling
Time
TSETTLING
TdExPD
TdREF
µs
µs
µs
µs
(Note 8)
Analog Output Time Delay
from Power-Down Mode
4.5
VDD = 5V, (Note 4), (Note 9)
Time delay to settle to new
reference
(Note 4)
26
From External to Internal
Reference
44
From Internal to External
Reference
Power Supply Rejection
Capacitive Load Stability
Slew Rate
PSRR
CL
—
—
—
—
-57
—
—
1000
—
dB
VDD = 5V± 10%, VREF = Internal
pF
RL = 5 kΩ, No Oscillation, (Note 4)
SR
0.55
66
V/µs
Phase Margin
pM
—
Degree CL = 400 pF, RL = ∞
(°)
Short Circuit Current
ISC
—
—
15
24
—
mA
VDD = 5V,
All VOUT Pins = Grounded.
Tested at room temperature.
Short Circuit Current
Duration
TSC_DUR
ROUT
Infinite
hours (Note 4)
DC Output Impedance
(Note 4)
—
—
1
1
—
—
Ω
Normal mode
kΩ
Power-Down Mode 1
(PD1:PD0 = 0:1), VOUT to VSS
—
—
100
500
—
—
kΩ
kΩ
Power-Down Mode 2
(PD1:PD0 = 1:0), VOUT to VSS
Power-Down Mode 3
(PD1:PD0 = 1:1), VOUT to VSS
Dynamic Performance (Note 4)
Major Code Transition
Glitch
—
45
—
nV-s 1 LSB code change around major
carry (from 7FFh to 800h)
Digital Feedthrough
Analog Crosstalk
—
—
<10
<10
—
—
nV-s
nV-s
Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0x000.
2: The power-up ramp rate measures the rise of VDD over time.
3: This parameter is ensured by design and not 100% tested.
4: This parameter is ensured by characterization and not 100% tested.
5: Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V.
6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.
7: This parameter is indirectly tested by Offset and Gain error testing.
8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
9: This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT
.
This time delay is not included in the output settling time specification.
© 2009 Microchip Technology Inc.
DS22187C-page 5
MCP4728
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V,
RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS.
Parameter
Symbol
Min
Typical
Max
Units
Conditions
DAC-to-DAC Crosstalk
Digital Interface
—
<10
—
nV-s
Output Low Voltage
VOL
VIL
—
—
—
—
—
—
0.4
0.3VDD
0.2VDD
—
V
V
V
V
IOL = 3 mA
SDA and RDY/BSY pins
Schmitt Trigger
Low Input
Threshold Voltage
VDD > 2.7V.
SDA, SCL, LDAC pins
—
VDD ≤ 2.7V.
SDA, SCL, LDAC pins
Schmitt Trigger
High Input
VIH
0.7VDD
SDA, SCL, LDAC pins
Threshold Voltage
Input Leakage
ILI
—
—
—
—
±1
3
µA
pF
SCL = SDA = LDAC = VDD
SCL = SDA = LDAC = VSS
,
Pin Capacitance
EEPROM
CPIN
(Note 4)
EEPROM Write Time
Data Retention
TWRITE
—
—
25
50
—
ms
EEPROM write time
200
Years At +25°C, (Note 3)
LDAC Input
LDAC Low Time
TLDAC
210
—
—
ns
Updates analog outputs (Note 3)
Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0x000.
2: The power-up ramp rate measures the rise of VDD over time.
3: This parameter is ensured by design and not 100% tested.
4: This parameter is ensured by characterization and not 100% tested.
5: Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V.
6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.
7: This parameter is indirectly tested by Offset and Gain error testing.
8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
9: This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT
.
This time delay is not included in the output settling time specification.
DS22187C-page 6
© 2009 Microchip Technology Inc.
MCP4728
TRSCL
THIGH
TFSCL
TSU:STA
SCL
SDA
TSU:STO
TBUF
TSU:DAT
TLOW
THD:STA
THD:DAT
0.7VDD
TSP
0.3VDD
TAA
TFSDA
TRSDA
2
FIGURE 1-1:
I C Bus Timing Data.
LDAC
TLDAC
0.7VDD
0.3VDD
VOUT (UDAC = 1)
Update
No Update
FIGURE 1-2:
LDAC Pin Timing vs. V
Update.
OUT
© 2009 Microchip Technology Inc.
DS22187C-page 7
MCP4728
2
I C SERIAL TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +125°C, VSS = 0V,
Standard and Fast Mode: VDD = +2.7V to +5.5V
High Speed Mode: VDD = +4.5V to +5.5V.
Parameters
Clock Frequency
Sym
Min
Typ
Max
Units
Conditions
Standard Mode
fSCL
0
—
100
kHz
Cb = 400 pF, 2.7V - 5.5V
0
0
—
—
—
—
—
—
—
400
1.7
kHz
MHz
MHz
pF
Fast Mode
Cb = 400 pF, 2.7V - 5.5V
High Speed Mode 1.7
Cb = 400 pF, 4.5V - 5.5V
0
3.4
High Speed Mode 3.4
Cb = 100 pF, 4.5V - 5.5V
Bus Capacitive Loading
Cb
—
—
—
—
400
400
400
100
Standard Mode
2.7V - 5.5V
pF
Fast Mode
2.7V - 5.5V
pF
High Speed Mode 1.7
4.5V - 5.5V
pF
High Speed Mode 3.4
4.5V - 5.5V
Start Condition Setup Time
(Start, Repeated Start)
T
T
4700
600
160
160
4000
600
160
160
4000
600
160
160
4000
600
120
60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Standard Mode
SU:STA
HD:STA
SU:STO
—
—
—
Fast Mode
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode
Start Condition Hold Time
Stop Condition Setup Time
Clock High Time
—
—
—
Fast Mode
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode
T
—
—
—
—
—
—
—
—
—
—
—
Fast Mode
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode
T
HIGH
Fast Mode
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode
Clock Low Time
T
4700
1300
320
160
LOW
Fast Mode
High Speed Mode 1.7
High Speed Mode 3.4
Note 1: This parameter is ensured by characterization and is not 100% tested.
2: After a Repeated Start condition or an Acknowledge bit.
3: If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If
this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected.
Data Input: This parameter must be longer than tSP
.
Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
4: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (T
plus SDA Fall (or rise) time: TAA = THD:DAT + TFSDA (OR TRSDA).
)
HD:DAT
5: Time between Start and Stop conditions.
DS22187C-page 8
© 2009 Microchip Technology Inc.
MCP4728
2
I C SERIAL TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +125°C, VSS = 0V,
Standard and Fast Mode: VDD = +2.7V to +5.5V
High Speed Mode: VDD = +4.5V to +5.5V.
Parameters
SCL Rise Time
Sym
Min
Typ
Max
Units
Conditions
Standard Mode
T
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
10
10
1000
300
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RSCL
(Note 1)
20 + 0.1Cb
Fast Mode
20
High Speed Mode 1.7
High Speed Mode 1.7 (Note 2)
High Speed Mode 3.4
High Speed Mode 3.4 (Note 2)
Standard Mode
20
160
40
10
10
80
SDA Rise Time
(Note 1)
T
—
1000
300
80
RSDA
20 + 0.1Cb
Fast Mode
20
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode
10
40
SCL Fall Time
(Note 1)
T
—
300
300
160
80
FSCL
FSDA
20 + 0.1Cb
Fast Mode
20
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode
10
SDA Fall Time
(Note 1)
T
—
300
300
160
80
20 + 0.1Cb
Fast Mode
20
10
250
100
10
10
0
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode
Data Input Setup Time
T
T
—
SU:DAT
HD:DAT
—
Fast Mode
—
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode
—
Data Hold Time
(Input, Output)
(Note 3)
3450
900
70
0
Fast Mode
0
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode
0
150
3750
1200
150
310
—
Output Valid from Clock
(Note 4)
T
0
AA
0
Fast Mode
0
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode
0
Bus Free Time
(Note 5)
T
4700
1300
—
—
—
—
—
—
BUF
—
Fast Mode
—
High Speed Mode 1.7
High Speed Mode 3.4
Standard Mode, (Not Applicable)
Fast Mode
—
Input Filter Spike Suppression
(SDA and SCL)
(Not Tested)
T
—
SP
—
—
High Speed Mode 1.7
High Speed Mode 3.4
—
Note 1: This parameter is ensured by characterization and is not 100% tested.
2: After a Repeated Start condition or an Acknowledge bit.
3: If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If
this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected.
Data Input: This parameter must be longer than tSP
.
Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
4: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (T
plus SDA Fall (or rise) time: TAA = THD:DAT + TFSDA (OR TRSDA).
)
HD:DAT
5: Time between Start and Stop conditions.
© 2009 Microchip Technology Inc.
DS22187C-page 9
MCP4728
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Symbol
Min
Typical Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 10L-MSOP
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
θJA
—
202
—
°C/W
DS22187C-page 10
© 2009 Microchip Technology Inc.
MCP4728
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF.
6
0.3
VDD = 5.5V, VREF = Internal, Gain = x1
VDD = 5.5V, VREF = Internal, Gain = x1
4
2
0.2
0.1
0
0
-2
-4
-6
-0.1
-0.2
0
1024
2048
Code
3072
4096
0
1024
1024
1024
2048
Code
3072
4096
FIGURE 2-1:
INL vs. Code (T = +25°C).
FIGURE 2-4:
DNL vs. Code (T = +25°C).
A
A
6
4
0.3
0.2
0.1
0
VDD = 5.5V, VREF = Internal, Gain = x2
VDD = 5.5V, VREF = Internal, Gain = x2
2
0
-2
-4
-0.1
-0.2
0
-6
0
1024
2048
Code
3072
4096
2048
Code
3072
4096
FIGURE 2-2:
INL vs. Code (T = +25°C).
FIGURE 2-5:
DNL vs. Code (T = +25°C).
A
A
0.2
0.15
0.1
6
4
VDD = 5.5V, VREF = VDD
VDD = 5.5V, VREF = VDD
2
0.05
0
0
-2
-4
-0.05
-6
0
-0.1
0
2048
Code
3072
4096
1024
2048
Code
3072
4096
FIGURE 2-3:
INL vs. Code (T = +25°C).
FIGURE 2-6:
DNL vs. Code (T = +25°C).
A
A
© 2009 Microchip Technology Inc.
DS22187C-page 11
MCP4728
Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF.
6
4
0.4
0.3
0.2
0.1
0
VDD = 2.7V, VREF = Internal, Gain = x1
VDD = 2.7V, VREF = Internal, Gain = x1
2
0
-2
-4
-6
-0.1
-0.2
0
1024
2048
Code
3072
4096
0
1024
2048
Code
3072
4096
FIGURE 2-7:
INL vs. Code (T = +25°C).
FIGURE 2-10:
DNL vs. Code (T = +25°C).
A
A
6
4
0.4
0.3
0.2
0.1
0
VDD = 2.7V, VREF = VDD
VDD = 2.7V, VREF = VDD
2
0
-2
-4
-0.1
-0.2
0
-6
0
1024
2048
Code
3072
4096
1024
2048
Code
3072
4096
FIGURE 2-8:
INL vs. Code (T = +25°C).
FIGURE 2-11:
DNL vs. Code (T = +25°C).
A
A
0.4
0.3
0.2
0.1
0
6
4
VDD = 5.5V, VREF = Internal, Gain = x1
VDD = 5.5V, VREF = Internal, Gain = x1
+85°C
-40oC
2
0
-2
-4
-6
-8
+25oC
+125oC
-0.1
+125oC
- 40oC to +85oC
-10
0
-0.2
1024
2048
Code
3072
4096
0
1024
2048
Code
3072
4096
FIGURE 2-9:
INL vs. Code and
FIGURE 2-12:
DNL vs. Code and
Temperature.
Temperature.
DS22187C-page 12
© 2009 Microchip Technology Inc.
MCP4728
Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF.
6
4
0.4
0.3
0.2
0.1
0
VDD = 5.5V, VREF = Internal, Gain = x2
85oC
VDD = 5.5V, VREF = Internal, Gain = x2
- 40oC
25oC
2
0
-2
-4
-6
-8
-10
-0.1
-0.2
-0.3
+125oC
- 40oC to +85oC
125oC
0
1024
2048
Code
3072
4096
0
1024
2048
Code
3072
4096
FIGURE 2-13:
INL vs. Code and
FIGURE 2-16:
DNL vs. Code and
Temperature.
Temperature.
6
4
0.5
0.4
0.3
0.2
0.1
0
VDD = 2.7V, VREF = Internal, Gain = x1
VDD = 2.7V, VREF = Internal, Gain = 1X
2
0
-2
-4
-6
-8
- 40oC
25oC
-0.1
85oC
-0.2
+125oC
-0.3
- 40oC to +85oC
125oC
-10
0
1024
2048
3072
4096
0
1024
2048
3072
4096
Code
Code
FIGURE 2-14:
INL vs. Code and
FIGURE 2-17:
DNL vs. Code and
Temperature.
Temperature.
6
4
0.4
0.3
0.2
0.1
0
VDD = 5.5V, VREF = VDD
VDD = 5.5V, VREF = VDD
85oC
2
0
-2
-4
- 40oC
-0.1
25oC
+125oC
- 40oC to +85oC
125oC
-0.2
0
-6
1024
2048
Code
3072
4096
0
1024
2048
Code
3072
4096
FIGURE 2-15:
INL vs. Code and
FIGURE 2-18:
DNL vs. Code and
Temperature.
Temperature.
© 2009 Microchip Technology Inc.
DS22187C-page 13
MCP4728
Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF.
6
4
0.5
0.4
0.3
0.2
0.1
0
VDD = 2.7V, VREF = VDD
VDD = 2.7V, VREF = VDD
85oC
- 40oC
2
0
-2
-4
-6
-8
125oC
-0.1
-0.2
-0.3
25oC
+125oC
1024
- 40oC to +85oC
0
1024
2048
3072
4096
0
2048
3072
4096
Code
Code
FIGURE 2-19:
INL vs. Code and
FIGURE 2-22:
DNL vs. Code and
Temperature.
Temperature.
6
5
-10
-20
-30
-40
VDD = 2.7V, Gain = 1
VDD = 5.5V, Gain = 2
VDD = 5.5V, Gain = 1
VDD = 2.7V, Gain = 1
4
3
2
1
0
VDD = 5.5V, Gain = 1
VDD = 5.5V, Gain = 2
-50
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
FIGURE 2-20:
Full Scale Error vs.
FIGURE 2-23:
Zero Scale Error vs.
Temperature (Code = FFFh, V
= Internal).
Temperature (Code = 000h, V
= Internal).
REF
REF
50
4
VDD = 5.5V, Gain = 1
VDD = 5.5V
VDD = 2.7V
3
2
1
0
40
30
20
10
VDD = 2.7V, Gain = 1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
FIGURE 2-21:
Full Scale Error vs.
FIGURE 2-24:
Zero Scale Error vs.
Temperature (Code = FFFh, V
= V ).
Temperature (Code = 000h, V
= V ).
REF
DD
REF DD
DS22187C-page 14
© 2009 Microchip Technology Inc.
MCP4728
Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF.
VOUT (2V/Div)
VOUT (2V/Div)
Time (2 µs/Div)
Time (2 µs/Div)
LDAC
LDAC
FIGURE 2-25:
Full Scale Settling Time
FIGURE 2-28:
Full Scale Settling Time
(V
= V , V = 5V, UDAC = 1,
(V
= V , V = 5V, UDAC = 1,
REF
DD
DD
REF DD DD
Code Change: 000h to FFFh).
Code Change: FFFh to 000h ).
V
OUT (2V/Div)
VOUT (2V/Div)
Time (2 µs/Div)
Time (2 µs/Div)
LDAC
LDAC
FIGURE 2-26:
Half Scale Settling Time
FIGURE 2-29:
Half Scale Settling Time
(V = V , V = 5V, UDAC = 1,
(V
= V , V = 5V, UDAC = 1,
REF
DD
DD
REF
DD DD
Code Change: 000h to 7FFh).
Code Change: 7FFh to 000h).
VOUT (2V/Div)
Time (2 µs/Div)
VOUT (2V/Div)
Time (2 µs/Div)
LDAC
LDAC
FIGURE 2-27:
Full Scale Settling Time
FIGURE 2-30:
Full Scale Settling Time
(V = Internal, V = 5V, UDAC = 1,
(V = Internal, V = 5V, UDAC = 1,
REF
DD
REF
DD
Gain = x1, Code Change: 000h to FFFh).
Gain = x1, Code Change: FFFh to 000h).
© 2009 Microchip Technology Inc.
DS22187C-page 15
MCP4728
Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF.
VOUT (1V/Div)
VOUT (1V/Div)
Time (2 µs/Div)
Time (2 µs/Div)
LDAC
LDAC
FIGURE 2-31:
Half Scale Settling Time
FIGURE 2-34:
Half Scale Settling Time
(V
= Internal, V = 5V, UDAC = 1,
(V
= Internal, V = 5V, UDAC = 1,
REF
DD
REF DD
Gain = x1, Code Change: 000h to 7FFh).
Gain = x1, Code Change: 7FFh to 000h).
VOUT (2V/Div)
VOUT (1V/Div)
TdExPD
TdExPD
Time (5 µs/Div)
Time (5 µs/Div)
CLK
CLK
FIGURE 2-35:
(Code : FFFh, V
Channels).
Last ACK CLK pulse
Last ACK CLK pulse
FIGURE 2-32:
(Code : FFFh, V
Gain = x1, for all Channels.).
Exiting Power Down Mode
Exiting Power Down Mode
= V , V = 5V, for all
= Internal, V = 5V,
REF
DD
REF
DD
DD
Discharging Time due to
internal pull-down resistor (500 kΩ)
Discharging Time due to
internal pull-down resistor (500 kΩ)
VOUT (1V/Div)
VOUT (2V/Div)
Time (10 µs/Div)
Time (20 µs/Div)
Last ACK CLK pulse
CLK
Last ACK CLK pulse
CLK
FIGURE 2-33:
(Code : FFFh, V
Gain = x1, PD1= PD0 = 1, No External Load).
Entering Power Down Mode
= Internal, V = 5V,
FIGURE 2-36:
(Code : FFFh, V
PD1= PD0 = 1, No External Load).
Entering Power Down Mode
= V , V = 5V,
REF
DD
REF
DD
DD
DS22187C-page 16
© 2009 Microchip Technology Inc.
MCP4728
Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF.
VOUT (2V/Div)
VOUT (50 mV/Div)
Time (2 µs/Div)
Time (10 µs/Div)
CLK
Last ACK CLK pulse
Time Delay when
FIGURE 2-37:
V
FIGURE 2-40:
Code Change Glitch
OUT
V
changes from Internal Reference to V
.
(V = External, V = 5V, No External Load),
REF
DD
REF
DD
Code Change: 800h to 7FFh.
VOUT (2V/Div)
VOUT (50 mV/Div)
Time (2 µs/Div)
Time (10 µs/Div)
CLK
Last ACK CLK pulse
FIGURE 2-38:
V
Time Delay when
FIGURE 2-41:
Code Change Glitch
OUT
V
changes from V to Internal Reference.
(V = Internal, V = 5V, Gain = 1, No External
REF
DD
REF
DD
Load), Code Change: 800h to 7FFh.
6
5
4
3
2
1
0
VOUT at Channel D
(5V/Div)
VDD = 5V
VREF = VDD
Code = FFFh
LDAC
VOUT at Channel A
(100 mV/Div)
Time (5 µs/Div)
0
1
2
3
4
5
Load Resistance (kΩ)
FIGURE 2-39:
Channel Cross Talk
FIGURE 2-42:
V
vs. Resistive Load.
OUT
(V
= V , V = 5V).
REF
DD DD
© 2009 Microchip Technology Inc.
DS22187C-page 17
MCP4728
Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF.
1000
1000
800
600
400
200
0
VDD = 5.0V
All Channels On
3 Channels On
All Channels On
3 Channels On
2 Channels On
VDD
= 5.0V
800
600
400
200
0
2 Channels On
1 Channel On
1 Channel On
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
FIGURE 2-43:
(V
IDD vs. Temperature
= VDD, V = 5V, Code = FFFh).
FIGURE 2-46:
(V = Internal, V
IDD vs. Temperature
= 5V, Code = FFFh).
REF
DD
REF
REF
800
1000
VDD = 2.7V
VDD = 2.7V
All Channels On
3 Channels On
2 Channels On
All Channels On
3 Channels On
2 Channels On
800
600
400
200
0
600
400
200
0
1 Channel On
1 Channel On
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
FIGURE 2-44:
(V
IDD vs. Temperature
= V , V = 2.7V, Code = FFFh).
FIGURE 2-47:
IDD vs. Temperature (V
=
REF
Internal, V = 2.7V, Code = FFFh).
REF
DD
DD
DD
900
900
VDD = 5.5V
All Channels On
VDD = 5V
VDD = 5.5V
All Channels On
VDD = 5V
800
700
600
500
800
700
600
500
VDD = 4.5V
VDD = 3.3V
VDD = 2.7V
VDD = 4.5V
VDD = 3.3V
VDD = 2.7V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
FIGURE 2-45:
(V
IDD vs. Temperature
= V , All channels are in Normal Mode,
FIGURE 2-48:
(V
IDD vs. Temperature
= Internal , All Channels are in Normal
REF
DD
REF
Code = FFFh).
Mode, Code = FFFh).
DS22187C-page 18
© 2009 Microchip Technology Inc.
MCP4728
Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF.
6
5
4
3
2
1
0
60
50
40
30
20
Code = 000h
All Channels Off
VDD = 5.5V
VDD = 5V
VDD = 4.5V
VDD = 2.7V
VDD = 3.3V
0
2
4
6
8
10
12
14
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
Sink Current (mA)
FIGURE 2-49:
(V
IDD vs. Temperature
= Internal , All Channels are in Powered
FIGURE 2-51:
Sink Current Capability
(V = V , Code = 000h).
REF
REF
DD
Down).
6
5
4
3
2
1
0
Code = FFFh
0
2
4
6
8
10
12
14
16
Current (mA)
FIGURE 2-50:
SourceCurrentCapability
(V = V , Code = FFFh).
REF
DD
© 2009 Microchip Technology Inc.
DS22187C-page 19
MCP4728
NOTES:
DS22187C-page 20
© 2009 Microchip Technology Inc.
MCP4728
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Type
Pin No.
Name
Function
1
2
3
4
VDD
SCL
P
Supply Voltage
I2C Serial Clock Input. (Note 1)
OI
SDA
LDAC
OI/OO I2C Serial Data Input and Output. (Note 1)
ST
This pin is used for two purposes:
(a) Synchronization Input. It is used to transfer the contents of the DAC input
registers to the output registers (VOUT).
(b) Select the device for reading and writing I2C address bits. (Note 2)
5
6
RDY/BSY
OO
AO
AO
AO
AO
P
This pin is a status indicator of EEPROM programming activity. An external pull-up
resistor (about 100 kΩ) is needed from RDY/BSY pin to VDD line. (Note 1)
V
OUT A
OUT B
Buffered analog voltage output of channel A. The output amplifier has rail-to-rail
operation.
7
V
Buffered analog voltage output of channel B. The output amplifier has rail-to-rail
operation.
8
VOUT
OUT D
VSS
C
Buffered analog voltage output of channel C. The output amplifier has rail-to-rail
operation.
9
V
Buffered analog voltage output of channel D. The output amplifier has rail-to-rail
operation.
10
Ground reference.
Legend: P = Power, OI = Open-Drain Input, OO = Open-Drain Output, ST = Schmitt Trigger Input Buffer,
AO = Analog Output
Note 1: This pin needs an external pull-up resistor from VDD line. Leave this pin float if it is not used.
2: This pin can be driven by MCU.
3.1
Analog Output Voltage Pins (VOUTA,
3.2
Supply Voltage Pins (VDD, VSS)
V
OUTB, VOUTC, VOUTD)
VDD is the power supply pin for the device. The voltage
at the VDD pin is used as the power supply input as well
as the DAC external reference. The power supply at
the VDD pin should be as clean as possible for a good
DAC performance.
The device has four analog voltage output (VOUT) pins.
Each output is driven by its own output buffer with a
gain of 1 or 2 depending on the gain and VREF selection
bit settings. In normal mode, the DC impedance of the
output pin is about 1Ω. In Power-Down mode, the
output pin is internally connected to 1 kΩ, 100 kΩ, or
500 kΩ, depending on the Power-Down selection bit
settings.
It is recommended to use an appropriate bypass
capacitor of about 0.1 µF (ceramic) to ground. An
additional 10 µF capacitor (tantalum) in parallel is also
recommended to further attenuate high frequency
noise present in application boards. The supply voltage
(VDD) must be maintained in the 2.7V to 5.5V range for
specified operation.
The VOUT pin can drive up to 1000 pF of capacitive
load. It is recommended to use a load with RL greater
than 5 kΩ.
VSS is the ground pin and the current return path of the
device. The user must connect the VSS pin to a ground
plane through a low impedance connection. If an
analog ground path is available in the application PCB
(printed circuit board), it is highly recommended that
the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board.
© 2009 Microchip Technology Inc.
DS22187C-page 21
MCP4728
3.3
Serial Data Pin (SDA)
3.5
LDAC Pin
SDA is the serial data pin of the I2C interface. The SDA
pin is used to write or read the DAC register and
EEPROM data. Except for start and stop conditions,
the data on the SDA pin must be stable during the high
duration of the clock pulse. The High or Low state of the
SDA pin can only change when the clock signal on the
SCL pin is Low.
This pin can be driven by an external control device
such as an MCU I/O pin. This pin is used (a) to transfer
the contents of the input registers to their
corresponding DAC output registers and (b) to select a
device of interest when reading or writing I2C address
bits. See Section 5.4.4 “General call Read Address
Bits” and Section 5.6.8 “Write Command: Write I2C
Address bits (C2=0, C1=1, C0=1)” for more details on
the reading and writing the device I2C address bits,
respectively.
The SDA pin is an open-drain N-channel driver.
Therefore, it needs a pull-up resistor from the VDD line
to the SDA pin.
Refer to Section 5.0 “I2C Serial Interface
Communications” for more details on the I2C Serial
Interface communication.
When the logic status of the LDAC pin changes from
“High” to “Low”, the contents of all input registers
(Channels A - D) are transferred to their corresponding
output registers and all analog voltage outputs are
updated simultaneously.
3.4
Serial Clock Pin (SCL)
If this pin is permanently tied to “Low”, the content of
the input register is transferred to its output register
(VOUT) immediately at the last input data byte’s
acknowledge pulse.
SCL is the serial clock pin of the I2C interface. The
MCP4728 device acts only as a slave and the SCL pin
accepts only external input serial clocks. The input data
from the Master device is shifted into the SDA pin on
the rising edges of the SCL clock and output from the
MCP4728 occurs at the falling edges of the SCL clock.
The user can also use the UDAC bit instead. However,
the UDAC bit updates a selected channel only. See
Section 4.8 “Output Voltage Update” for more
information on the LDAC pin and UDAC bit functions.
The SCL pin is an open-drain N-channel driver.
Therefore, it needs a pull-up resistor from the VDD line
to the SCL pin.
Refer to Section 5.0 “I2C Serial Interface
Communications” for more details on I2C Serial
Interface communication.
3.6
RDY/BSY Status Indicator Pin
This pin is a status indicator of EEPROM programming
activity. This pin is “High” when the EEPROM has no
programming activity and “Low” when the EEPROM is
in programming mode. It goes “High” when the
EEPROM program is completed.
Typical range of the pull-up resistor value for SCL and
SDA is from 5 kΩ to 10 kΩ for standard (100 kHz) and
fast (400 kHz) modes, and less than 1 kΩ for high
speed mode (3.4 MHz).
The RDY/BSY pin is an open-drain N-channel driver.
Therefore, it needs a pull-up resistor (about 100 kΩ)
from the VDD line to the RDY/BSY pin. Leave this pin
float if it is not used.
DS22187C-page 22
© 2009 Microchip Technology Inc.
MCP4728
4.2
Reset Conditions
4.0
THEORY OF DEVICE
OPERATION
The device can be reset by two independent events: (a)
by Power-On-Reset or (b) by I2C General Call Reset
Command. Under the reset conditions, the device
uploads the EEPROM data into both of the DAC input
and output registers simultaneously. The analog output
voltage of each channel is available immediately
regardless of the LDAC and UDAC bit conditions.
The MCP4728 device is a 12-bit 4-channel buffered
voltage output DAC with non-volatile memory
(EEPROM). The user can program the EEPROM with
I2C address bits, configuration and DAC input data of
each channel. The device has an internal charge pump
circuit to provide the programming voltage of the
EEPROM.
The factory default settings for the EEPROM prior to
the device shipment are shown in Table 4-2.
When the device is first powered-up, it automatically
loads the stored data in its EEPROM to the DAC input
and output registers, and provides analog outputs with
the saved settings immediately. This event does not
require an LDAC or UDAC bit condition. After the
device is powered-up, the user can update the input
registers using I2C write commands. The analog out-
puts can be updated with new register values if the
LDAC pin or UDAC bit is low. The DAC output of each
channel is buffered with a low power and precision out-
put amplifier. This amplifier provides a rail-to-rail output
with low offset voltage and low noise.
4.3
Output Amplifier
The DAC output is buffered with a low power precision
amplifier. This amplifier provides low offset voltage and
low noise, as well as rail-to-rail output.
The output amplifier can drive the resistive and high
capacitive loads without oscillation. The amplifier can
provide a maximum load current of 24 mA which is
enough for most of programmable voltage reference
applications. Refer to Section 1.0 “Electrical
Characteristics” for the specifications of the output
amplifier.
The device uses a resistor string architecture. The
resistor ladder DAC can be driven from VDD or internal
VREF depending on the reference selection. The user
4.3.1
PROGRAMMABLE GAIN BLOCK
can select internal (2.048V) or external reference (VDD
)
The rail-to-rail output amplifier of each channel has
configurable gain option. When the internal voltage
reference is selected, the output amplifier gain has two
selection options: gain of 1 or gain of 2.
for each DAC channel individually by software control.
The VDD is used as the external reference. Each
channel is controlled and operated independently.
The device has a Power-Down mode feature. Most of
the circuit in each powered down channel are turned
off. Therefore, operating power can be saved
significantly by putting any unused channel to the
Power-Down mode.
When the external reference is selected (VREF = VDD),
the gain of 2 option is disabled, and only the gain of 1
is used by default.
4.3.1.1
Resistive and Capacitive Loads
The analog output (VOUT) pin is capable of driving
capacitive loads up to 1000 pF in parallel with 5 kΩ
load resistance. Figure 2-42 shows the VOUT vs.
Resistive Load.
4.1
Power-On-Reset (POR)
The device contains an internal Power-On-Reset
(POR) circuit that monitors power supply voltage (VDD
)
during operation. This circuit ensures correct device
start-up at system power-up and power-down events.
If the power supply voltage is less than the POR
threshold (VPOR = 2V, typical), all circuits are disabled
and there will be no analog output. When the VDD
increases above the VPOR, the device takes a reset
state. During the reset period, each channel uploads all
configuration and DAC input codes from EEPROM,
and analog output (VOUT) will be available accordingly.
This enables the device to return to the same state that
it was at the last write to the EEPROM before it was
powered off. The POR status is monitored by the POR
status bit by using the I2C read command. See
Figure 5-15 for the details of the POR status bit.
© 2009 Microchip Technology Inc.
DS22187C-page 23
MCP4728
4.4
DAC Input Registers and
Non-Volatile EEPROM Memory
Each channel has its own volatile DAC input register
and EEPROM. The details of the input registers and
EEPROM are shown in Table 4-1 and Table 4-2,
respectively.
TABLE 4-1:
INPUT REGISTER MAP (VOLATILE)
Configuration Bits
DAC Input Data (12 bits)
RDY A2 A1 A0 VREF DAC1 DAC0 PD1 PD0
/BSY
GX
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Bit
Name
2
Bit
I C
Ref. DAC Channel Power-Down Gain
(Note 2)
Function
Address Bits Select
(Note 2)
Select
(Note 2) (Note 2)
Select
(Note 1)
(Note 2)
(Note 2)
CH. A
CH. B
CH. C
CH. D
Note 1: EEPROM write status indication bit (flag).
2: Loaded from EEPROM during power-up, or can be updated by the user.
TABLE 4-2:
EEPROM MEMORY MAP AND FACTORY DEFAULT SETTINGS
Configuration Bits
DAC Input Data (12 bits)
A2
A1
A0
VREF
PD1
PD0
GX
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Bit Name
Bit
Function
Ref.
Select
Power-Down
Select
Gain
Select
2
I C Address Bits
(Note 1)
(Note 2)
(Note 3)
CH. A
CH. B
CH. C
CH. D
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note 1: Device I2C address bits. The user can also specify these bits during the device ordering process. The
factory default setting is “000”. These bits can be reprogrammed by the user using the I2C Address Write
command.
2: Voltage Reference Select: 0 = External VREF (VDD), 1 = Internal VREF (2.048V).
3: Gain Select: 0 = Gain of 1, 1 = Gain of 2.
DS22187C-page 24
© 2009 Microchip Technology Inc.
MCP4728
TABLE 4-3:
Bit Name
CONFIGURATION BITS
Functions
RDY/BSY
This is a status indicator (flag) of EEPROM programming activity:
1 = EEPROM is not in programming mode
0 = EEPROM is in programming mode
Note: RDY/BSY status can also be monitored at the RDY/BSY pin.
(A2, A1, A0)
VREF
Device I2C address bits. See Section 5.3 “MCP4728 Device Addressing” for more details.
Voltage Reference Selection bit:
0 = VDD
1 = Internal voltage reference (2.048V)
Note: Internal voltage reference circuit is turned off if all channels select external reference
(VREF = VDD)
.
DAC1, DAC0
PD1, PD0
DAC Channel Selection bits:
00 = Channel A
01 = Channel B
10 = Channel C
11 = Channel D
Power-Down selection bits:
00 = Normal Mode
01 = VOUT is loaded with 1 kΩ resistor to ground. Most of the channel circuits are powered off.
10 = VOUT is loaded with 100 kΩ resistor to ground. Most of the channel circuits are powered
off.
11 = VOUT is loaded with 500 kΩ resistor to ground. Most of the channel circuits are powered
off.
Note: See Table 4-7 and Figure 4-1 for more details.
GX
Gain selection bit:
0 = x1 (gain of 1)
1 = x2 (gain of 2)
Note: Applicable only when internal VREF is selected. If VREF = VDD, the device uses a gain of
1 regardless of the gain selection bit setting.
UDAC
DAC latch bit. Upload the selected DAC input register to its output register (VOUT):
0 = Upload. Output (VOUT) is updated.
1 = Do not upload.
Note: UDAC bit affects the selected channel only.
© 2009 Microchip Technology Inc.
DS22187C-page 25
MCP4728
4.7.1
OUTPUT VOLTAGE RANGE
4.5
Voltage Reference
The DAC output voltage range varies depending on the
voltage reference selection.
The device has a precision internal voltage reference
which provides a nominal voltage of 2.048V. The user
can select the internal voltage reference or VDD as the
voltage reference source of each channel using the
VREF configuration bit. The internal voltage reference
circuit is turned off when all channels select VDD as
their references. However, it stays turned on if any one
of the channels selects the internal reference.
• When the internal reference (VREF=2.048V) is
selected:
- VOUT = 0.000V to 2.048V * 4095/4096 for
Gain of 1
- VOUT = 0.000V to 4.096V * 4095/4096 for
Gain of 2
• When the external reference (VREF=VDD) is
selected:
4.6
LSB Size
The LSB is defined as the ideal voltage difference
between two successive codes. LSB sizes of the
MCP4728 device are shown in Table 4-4.
- VOUT = 0.000V to VDD
Note that the gain selection bit is not applicable for
VREF = VDD. In this case, Gain of 1 is used regard-
less of the gain selection bit setting.
TABLE 4-4:
VREF
LSB SIZES (EXAMPLE)
Gain (GX)
LSB Size
Condition
EQUATION 4-1:
V
FOR V
=
REF
Selection
OUT
INTERNAL REFERENCE
Internal
VREF
(2.048V)
x1
x2
0.5 mV
1 mV
2.048V/4096
4.096V/4096
(VREF × Dn)
------------------------------
VOUT
=
Gx
≤ VDD
4096
Where:
VDD
x1
VDD/4096
(Note 1)
VREF
Dn
=
=
=
2.048V for internal reference selection
DAC input code
Note 1: LSB size varies with the VDD range.
When VREF = VDD, the device uses
GX = 1 by default. GX = 2 option is
ignored.
Gx
Gain Setting
4.7
DAC Output Voltage
EQUATION 4-2:
V
FOR V
= VDD
REF
OUT
(VDD × Dn)
----------------------------
4096
Each channel has an independent output associated
with its own configuration bit settings and DAC input
code. When the internal voltage reference is selected
(VREF = internal), it supplies the internal VREF voltage
to the resistor string DAC of the channel. When the
external reference (VREF=VDD) is selected, VDD is used
for the channel’s resistor string DAC.
VOUT
=
Where:
Dn
=
DAC input code
4.8
Output Voltage Update
The following events update the output registers
(VOUT):
The VDD needs to be as clean as possible for accurate
DAC performance. When the VDD is selected as the
voltage reference, any variation or noises on the VDD
line can directly affect on the DAC output.
a. LDAC pin to “Low”: Updates all DAC channels.
b. UDAC bit to “Low”: Updates a selected channel
only.
The analog output of each channel has
a
programmable gain block. The rail-to-rail output
amplifier has a configurable gain of 1 or 2. But the gain
of 2 is not applicable if VDD is selected for the voltage
reference. The formula for the analog output voltage is
given in Equation 4-1 and Equation 4-2.
c. General Call Software Update Command:
Updates all DAC channels.
d. Power-On-Reset or General Call Reset com-
mand: Both input and output registers are
updated with EEPROM data. All channels are
affected.
4.8.1
LDAC PIN AND UDAC BIT
The user can use the LDAC pin or UDAC bit to upload
the input DAC register to output DAC register (VOUT).
However, the UDAC affects only the selected channel
while the LDAC affects all channels. The UDAC bit is
not used in the Fast Mode Writing.
Table 4-5 shows the output update vs. LDAC pin and
UDAC bit conditions.
DS22187C-page 26
© 2009 Microchip Technology Inc.
MCP4728
TABLE 4-5:
LDAC AND UDAC
CONDITIONS VS. OUTPUT
UPDATE
LDAC Pin UDAC Bit
DAC Output (VOUT)
0
0
1
1
0
1
0
1
Update all DAC channel
outputs.
Update all DAC channel
outputs.
Update a selected DAC
channel output.
No update
4.9
Analog Output Vs. DAC Input
Code
Table 4-6 shows an example of the DAC input data
code vs. analog output. The MSB of the input data is
always transmitted first and the format is unipolar
binary.
TABLE 4-6:
DAC INPUT CODE VS. ANALOG OUTPUT (V
)
OUT
VREF = Internal (2.048 V)
VREF = VDD
DAC Input Code
Gain
Selection
Nominal Output Voltage (V)
Gain
Selection
Nominal Output Voltage (V)
(See Note 1)
111111111111
111111111110
000000000010
000000000001
000000000000
x1
x2
x1
x2
x1
x2
x1
x2
x1
x2
VREF - 1 LSB
Ignored
VDD - 1 LSB
2*VREF - 1 LSB
V
REF - 2 LSB
VDD - 2 LSB
2 LSB
1 LSB
0
2*VREF - 2 LSB
2 LSB
2 LSB
1 LSB
1 LSB
0
0
Note 1: (a) LSB with gain of 1 = 0.5 mV, and (b) LSB with gain of 2 = 1 mV.
© 2009 Microchip Technology Inc.
DS22187C-page 27
MCP4728
When the DAC operation mode is changed from the
Power-Down to normal mode, there will be a time delay
until the analog output is available. Typical time delay
for the output voltage is approximately 4.5 µs. This time
delay is measured from the acknowledge pulse of the
I2C serial communication command to the beginning of
the analog output (VOUT). This time delay is not
included in the output settling time specification. See
Section 2.0 “Typical Performance Curves” for more
details.
4.10 Normal and Power-Down Modes
Each channel has two modes of operation: (a) Normal
mode where analog voltage is available and (b)
Power-Down mode which turns off most of the internal
circuits for power savings.
The user can select the operating mode of each
channel individually by setting the Power-Down
selection bits (PD1 and PD0). For example, the user
can select normal mode for channel A while selecting
power-down mode for all other channels.
TABLE 4-7:
POWER-DOWN BITS
See Section 5.6 “Write Commands for DAC
Registers and EEPROM” for more details on the
writing the power-down bits.
PD1
PD0 Function
0
0
1
0
1
0
Normal Mode
1 kΩ resistor to ground (Note 1)
100 kΩ resistor to ground
Most of the internal circuit in the powered down chan-
nel are turned off. However, the internal voltage refer-
ence circuit is not affected by the Power-Down mode.
The internal voltage reference circuit is turned off only
if all channels select external reference (VREF = VDD).
(Note 1)
1
1
500 kΩ resistor to ground
(Note 1)
Device actions during Power-Down mode:
Note 1: In Power-Down mode: VOUT is off and
most of internal circuits in the selected
channel are disabled.
• The powered down channel stays in a power sav-
ing condition by turning off most of its circuits.
• No analog voltage output at the powered down
channel.
VOUT
OP
Amp
• The output (VOUT) pin of the powered down
channel is switched to a known resistive load. The
value of the resistive load is determined by the
state of the Power-Down bits (PD1 and PD0).
Table 4-7 shows the outcome of the Power-Down
bit settings.
Power-Down
Control Circuit
1 kΩ
100 kΩ 500 kΩ
Resistor String DAC
Resistive
Load
• The contents of both the DAC registers and
EEPROM are not changed.
• Draws less than 40 nA (typical) when all four
channels are powered down and VDD is selected
as the voltage reference.
FIGURE 4-1:
Output Stage for
Power-Down Mode.
Circuits that are not affected during Power-Down
Mode:
• The I2C serial interface circuits remain active in
order to receive any command from the Master.
•
The internal voltage reference circuit stays
turned-on if it is selected as reference by at least
one channel.
Exiting Power-Down Mode:
The device exits Power-Down mode immediately by
the following commands:
• Any write command for normal mode. Only
selected channel is affected.
•
I2C General Call Wake-Up Command. All
channels are affected.
• I2C General Call Reset Command. This is a
conditional case. The device exits Power-Down
mode depending on the Power-Down bit settings
in EEPROM as the configuration bits and DAC
input codes are uploaded from EEPROM. All
channels are affected.
DS22187C-page 28
© 2009 Microchip Technology Inc.
MCP4728
2
mode and can communicate at up to 3.4 Mbit/s on SDA
and SCL lines. The device will switch out of the HS
mode on the next STOP condition.
5.0
I C SERIAL INTERFACE
COMMUNICATIONS
The MCP4728 device uses a two-wire I2C serial
interface. When the device is connected to the I2C bus
line, the device works as a slave device. The device
supports standard, fast and high speed modes.
For more information on the HS mode, or other I2C
modes, please refer to the Philips I2C specification.
5.2
I2C BUS CHARACTERISTICS
The following sections describes how to communicate
the MCP4728 device using the I2C serial interface
commands.
The specification of the I2C serial communication
defines the following bus protocol:
• Data transfer may be initiated only when the bus
is not busy.
5.1
Overview of I2C Serial Interface
Communications
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
An example of hardware connection diagram is shown
in Figure 7-1. A device that sends data onto the bus is
defined as transmitter, and a device receiving data as
receiver. The bus has to be controlled by a master
(MCU) device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions. Both master (MCU) and slave
(MCP4728) can operate as transmitter or receiver, but
the master device determines which mode is activated.
Accordingly, the following bus conditions have been
defined using Figure 5-1.
5.2.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
5.2.2
START DATA TRANSFER (B)
Communication is initiated by the master (MCU) which
sends the START bit, followed by the slave (MCP4728)
address byte. The first byte transmitted is always the
slave (MCP4728) address byte, which contains the
device code (1100), the address bits (A2, A1, A0), and
the R/W bit. The device code for the MCP4728 device
is 1100, and the address bits are user-writable.
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START
condition.
5.2.3
STOP DATA TRANSFER (C)
When the MCP4728 device receives a read command
(R/W = 1), it transmits the contents of the DAC input
registers and EEPROM sequentially. When writing to
the device (R/W = 0), the device will expect write
command type bits in the following byte. The reading
and various writing commands are explained in the
following sections.
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
5.2.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The MCP4728 device supports all three I2C serial
communication operating modes:
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
• Standard Mode: bit rates up to 100 kbit/s
• Fast Mode: bit rates up to 400 kbit/s
• High Speed Mode (HS mode): bit rates up to
3.4 Mbit/s
Each data transfer is initiated with a START condition
and terminated with a STOP condition.
Refer to the Philips I2C document for more details of
the I2C specifications.
5.2.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
5.1.1
HIGH-SPEED (HS) MODE
The I2C specification requires that a high-speed mode
device must be ‘activated’ to operate in high-speed
(3.4 Mbit/s) mode. This is done by sending a special
address byte of 00001XXX following the START bit.
The XXXbits are unique to the high-speed (HS) mode
Master. This byte is referred to as the high-speed (HS)
Master Mode Code (HSMMC). The MCP4728 device
does not acknowledge this byte. However, upon
receiving this command, the device switches to HS
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must send an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
© 2009 Microchip Technology Inc.
DS22187C-page 29
MCP4728
In this case, the slave (MCP4728) will leave the data
line HIGH to enable the master to generate the STOP
condition.
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
START
STOP
ADDRESS OR
DATA
CONDITION
CONDITION
ACKNOWLEDGE ALLOWED
VALID TO CHANGE
FIGURE 5-1:
Data Transfer Sequence On The Serial Bus.
5.3.1
MCP4728 Device Addressing
2
PROGRAMMING OF I C ADDRESS
BITS
5.3
The address byte is the first byte received following the
START condition from the master device. The first part
of the address byte consists of a 4-bit device code
which is set to 1100 for the MCP4728 device. The
device code is followed by three I2C address bits (A2,
A1, A0) which are programmable by the users.
Although the three address bits are programmable at
the user’s application PCB, the user can also specify
the address bits during the product ordering process. If
there is no user’s request, the factory default setting of
the three address bits is “000” which is programmed
into the EEPROM. The three address bits allows eight
unique addresses.
When the customer first receives any new MCP4728
device, its default address bit setting is “000” if the
address bit programming was not requested. The
customer can reprogram the I2C address bits into the
EEPROM by using “Write Address Bit” command. This
write command needs current address bits. If the
address bits are unknown, the user can find them by
sending “General Call Read Address” Command. The
LDAC pin is also used to select the device of interest to
be programmed or to read the current address.
The following steps are needed for the I2C address
programming.
(a) Read the address bits using “General Call Read
Address” Command. (This is the case when the
address is unknown.)
(b) Write I2C address bits using “Write I2C Address
Bits” Command.
Acknowledge bit
Start bit
Read/Write bit
R/W ACK
Slave Address
Address Byte
The write address command will replace the current
address with a new address in both input registers and
EEPROM.
See Section 5.4.4 “General call Read Address Bits”
for the details of reading the address bits, and
Section 5.6.8 “Write Command: Write I2C Address
bits (C2=0, C1=1, C0=1)” for writing the address bits.
Slave Address for MCP4728
Device Code
Address Bits
A2
1
1
0
A1
A0
0
Note:
Device Code: Programmed (hard-wired) at the factory.
Address Bits: Reprogrammable into EEPROM by the user.
FIGURE 5-2:
Device Addressing.
DS22187C-page 30
© 2009 Microchip Technology Inc.
MCP4728
I2C General Call Commands
5.4.1
GENERAL CALL RESET
5.4
The General Call Reset occurs if the second byte is
“00000110” (06h). At the acknowledgement of this
byte, the device will abort the current conversion and
perform the following tasks:
The device acknowledges the general call address
command (0x00 in the first byte). The meaning of the
general call address is always specified in the second
byte. The I2C specification does not allow to use
“00000000” (00h) in the second byte. Please refer to
the Philips I2C document for more details of the
General Call specifications.
• Internal reset similar to a Power-On-Reset (POR).
The contents of the EEPROM are loaded into
each DAC input and output registers immediately.
The MCP4728 device supports the following I2C
General Calls:
•
VOUT will be available immediately regardless of
the LDAC pin condition.
• General Call Reset
• General Call Wake-Up
• General Call Software Update
• General Call Read Address Bits
ACK (MCP4728)
Clock Pulse (CLK Line)
Start
Stop
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
2nd Byte
(Command Type = General Call Reset)
1st Byte
(General Call Command)
Note 1
Data (SDA Line)
Note 1: At this falling edge of the last ACK clock bit:
a. Startup Timer starts a reset sequence and
b. EEPROM data is loaded into the DAC Input and Output Registers immediately.
FIGURE 5-3:
General Call Reset.
5.4.2
GENERAL CALL WAKE-UP
If the second byte is “00001001” (09h), the device will
reset the Power-Down bits (PD1,PD0 = 0,0).
ACK (MCP4728)
Clock Pulse (CLK Line)
Start
Stop
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1st Byte
(General Call Command)
2nd Byte
(Command Type = General Call Wake-Up)
Note 1
Data (SDA Line)
Note 1: Resets Power-Down bits at this falling edge of the last ACK clock bit.
FIGURE 5-4:
General Call Wake-Up.
© 2009 Microchip Technology Inc.
DS22187C-page 31
MCP4728
5.4.3
GENERAL CALL SOFTWARE
UPDATE
If the second byte is “00001000” (08h), the device
updates all DAC analog outputs (VOUT) at the same
time.
ACK (MCP4728)
Clock Pulse (CLK Line)
Start
Stop
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
2nd Byte
(Command Type = General Call Software Update)
1st Byte
(General Call Command)
Note 1
Data (SDA Line)
Note 1: At this falling edge of the last ACK clock bit, VOUT A, VOUT B, VOUT C, VOUT D are
updated.
FIGURE 5-5:
General Call Software Update.
DS22187C-page 32
© 2009 Microchip Technology Inc.
MCP4728
select the device of interest to read on the I2C bus. The
LDAC pin needs a logic transition from “High” to “Low”
during the negative pulse of the 8th clock of the second
byte, and stays “Low” until the end of the 3rd byte. The
maximum clock rate for this command is 400 kHz.
5.4.4
GENERAL CALL READ ADDRESS
BITS
This command is used to read the I2C address bits of
the device. If the second byte is “00001100” (0Ch), the
device will output its address bits stored in EEPROM
and register. This command uses the LDAC pin to
ACK (MCP4728)
Restart
ACK (Master)
Start
Stop
4th Byte
S
0
0
0
0
0
0
0
0
A
0
0
0
0
1
1
0
0
A Sr 1
1
0
0
X X X
1
A A2 A1 A0 1 A2 A1 A0 0 A P
1st Byte
(General Call Address)
2nd Byte
3rd Byte
Restart Byte
Address Bits Address Bits
in
in Input
EEPROM
Register
Reading Address Bits
Note 3
LDAC Pin
(Notes 1, 2, 3)
Clock and LDAC Transition Details:
ACK Clock
Clock Pulse
Restart Clock
ACK Clock
(CLK Line)
6
7
8
9
Sr
1
2
3
4
5
6
7
8
9
1
2
3
2nd Byte
4th Byte
3rd Byte
Reading Address Bits
Note 2(b, c)
LDAC Pin
Note 3
Note 2(b)
Note 2 (a)
Stay “Low” until the end of the 3rd Byte
Note 1: Clock Pulse and LDAC Transition Details.
2: LDAC pin events at the 2nd and 3rd bytes.
a. Keep LDAC pin “High” until the end of the positive pulse of the 8th clock of the
2nd byte.
b. LDAC pin makes a transition from “High” to “Low” during the negative pulse of
the 8th clock of the 2nd byte (just before the rising edge of the 9th clock) and
stays “Low” until the rising edge of clock 9 of the 3rd byte.
c. The MCP4728 device does not acknowledge the 3rd byte if the conditions (a)
and (b) are not met.
3: LDAC pin resumes its normal function after “Stop” bit.
2
FIGURE 5-6:
General Call Read I C Address.
© 2009 Microchip Technology Inc.
DS22187C-page 33
MCP4728
5.5
Writing and Reading Registers
and EEPROM
5.6
Write Commands for DAC
Registers and EEPROM
The Master (MCU) can write or read the DAC input
registers or EEPROM using the I2C interface
command.
Table 5-1 summarizes the write command types and
their functions.The write command is defined by using
three write command type bits (C2, C1, C0) and two
write function bits (W1, W0). The register selection bits
(DAC1, DAC0) are used to select the DAC channel.
The following sections describe the communication
examples to write and read the DAC registers and
EEPROM using the I2C interface.
TABLE 5-1:
WRITE COMMAND TYPES
Write
Function
Command Field
Command Name
Function
C2
C1
C0
W1
W0
Fast Mode Write
0
0
X
Not Used
Fast Write for DAC
Input Registers
This command writes to the DAC input registers sequentially with lim-
ited configuration bits. The data is sent sequentially from channels A to
D. The input register is written at the acknowledge clock pulse of the
channel’s last input data byte. EEPROM is not affected. (Note 1)
Write DAC Input Register and EEPROM
0
1
0
0
0
Multi-Write for DAC This command writes to multiple DAC input registers, one DAC input
Input Registers
register at a time. The writing channel register is defined by the DAC
selection bits (DAC1, DAC0). EEPROM is not affected. (Note 2)
1
0
Sequential Write for
DAC Input Registers
and EEPROM
This command writes to both the DAC input registers and EEPROM
sequentially. The sequential writing is carried out from a starting chan-
nel to channel D. The starting channel is defined by the DAC selection
bits (DAC1 and DAC0).
The input register is written at the acknowledge clock pulse of the last
input data byte of each register. However, the EEPROM data is written
altogether at the same time sequentially at the end of the last byte.
(Note 2),(Note 3)
1
1
Single Write for DAC This command writes to a single selected DAC input register and its
Input Register and
EEPROM
EEPROM. Both the input register and EEPROM are written at the
acknowledge clock pulse of the last input data byte. The writing chan-
nel is defined by the DAC selection bits (DAC1 and DAC0).
(Note 2),(Note 3)
Write I2C Address Bits (A2, A1, A0)
0
1
1
Not Used Write I2C Address Bits This command writes new I2C address bits (A2, A1, A0) to the DAC
input register and EEPROM.
Write VREF, Gain, and Power-Down Select Bits (Note 4)
1
0
0
Not Used
Write Reference
(VREF) selection bits
to Input Registers
This command writes Reference (VREF) selection bits of each channel.
1
1
1
0
0
1
Not Used
Not Used
Write Gain selection This command writes Gain selection bits of each channel.
bits to Input Registers
Write Power-Down
This command writes Power-Down bits of each channel.
bits to Input Registers
Note 1: The analog output is updated when LDAC pin is (or changes to) “Low”. UDAC bit is not used for this command.
2: The DAC output is updated when LDAC pin or UDAC bit is “Low”.
3: The device starts writing to the EEPROM on the acknowledge clock pulse of the last channel. The device does not
execute any command until RDY/BSY bit comes back to “High”.
4: The input and output registers are updated at the acknowledge clock pulse of the last byte. The update does not require
LDAC pin or UDAC bit conditions. EEPROM is not affected.
DS22187C-page 34
© 2009 Microchip Technology Inc.
MCP4728
5 . 6 . 1
F A S T W R I T E C O M M A N D
(C2=0, C1=0, C0=X, X = DON’T
CARE)
5.6.2
MULTI-WRITE COMMAND: WRITE
DAC INPUT REGISTERS
(C2=0, C1=1, C0=0; W1=0, W0=0)
The Fast Write command is used to update the input
DAC registers from channels A to D sequentially. The
EEPROM data is not affected by this command. This
command is called “Fast Write” because it updates the
input registers with only limited data bits. Only the
Power-Down mode selection bits (PD1 and PD0) and
12 bits of DAC input data are writable.
This command is used to write DAC input register, one
at a time. The EEPROM data is not affected by this
command.
The DAC selection bits (DAC1, DAC0) select the DAC
channel to write. Only a selected channel is affected.
Repeated bytes are used to write more multiple DAC
registers.
The input register is updated at the acknowledge pulse
of each channel’s last data byte. Figure 5-7 shows an
example of the Fast Write command.
The D11 - D0 bits in the third and fourth bytes are the
DAC input data of the selected DAC channel. Bytes 2 -
4 can be repeated for the other channels. Figure 5-8
shows an example of the Multi-Write command.
Updating Analog Outputs:
Updating Analog Outputs:
a. When the LDAC pin is “High” before the last byte
of the channel D, all analog outputs are updated
simultaneously by bringing down the LDAC pin
to “Low” any time.
The analog outputs can be updated by one of the
following events after the falling edge of the
acknowledge clock pulse of the 4th byte.
b. If the command starts with the LDAC pin “Low”,
the channel’s analog output is updated at the
falling edge of the acknowledge clock pulse of
the channel’s last byte.
a. When the LDAC pin or UDAC bit is “Low”.
b. If UDAC bit is “High”, bringing down the LDAC
pin to “Low” any time.
c. By sending the General Call Software Update
command.
c. Send the General Call Software Update
command: This command updates all channels
simultaneously.
Note 1: The UDAC bit can be used effectively to
upload the input register to the output
register, but it affects only a selected
channel only, while the LDAC pin and
General Call Software Update command
affect all channels.
Note 1: UDAC bit is not used in this command.
© 2009 Microchip Technology Inc.
DS22187C-page 35
MCP4728
5.6.3
SEQUENTIAL WRITE COMMAND:
5.6.4
SINGLE WRITE COMMAND: WRITE
A SINGLE DAC INPUT REGISTER
AND EEPROM
WRITE DAC INPUT REGISTERS
AND EEPROM SEQUENTIALLY
FROM STARTING CHANNEL TO
CHANNEL D
(C2=0, C1=1, C0=0; W1=1, W0=1)
When the device receives this command, it writes the
input data to a selected single DAC input register and
also to its EEPROM. The channel is selected by the
channel selection bits (DAC1 and DAC0). See Table
for the channel selection bit function. Figure 5-10
shows an example of the single write command.
(C2=0, C1=1, C0=0; W1=1, W0=0)
When the device receives this command, it writes the
input data to the DAC input registers sequentially from
the starting channel to channel D, and also writes to
EEPROM sequentially. The starting channel is
determined by the DAC1 and DAC0 bits. Table 5-2
shows the functions of the channel selection bits for the
sequential write command.
Updating Analog Outputs:
The analog outputs can be updated by one of the
following events after the falling edge of the
acknowledge clock pulse of the 4th byte.
When the device is writing EEPROM, the RDY/BSY bit
stays “Low” until the EEPROM write operation is
completed. The state of the RDY/BSY bit flag can be
monitored by a read command or at the RDY/BSY pin.
Any new command received during the EEPROM write
operation (RDY/BSY bit is “Low”) is ignored. Figure 5-9
shows an example of the sequential write command.
a. When the LDAC pin or UDAC bit is “Low”.
b. If UDAC bit is “High”, bringing down the LDAC
pin to “Low” any time.
c. By sending the General Call Software Update
command.
Updating Analog Outputs:
Note 1: The UDAC bit can be used effectively to
upload the input register to the output
register, but it affects only a selected
channel only, while the LDAC pin and
General Call Software Update command
affect all channels.
The analog outputs can be updated by one of the
following events after the falling edge of the
acknowledge clock pulse of the 4th byte.
a. When the LDAC pin or UDAC bit is “Low”.
b. If UDAC bit is “High”, bringing down the LDAC
pin to “Low” any time.
c. By sending the General Call Software Update
command.
Note 1: The UDAC bit can be used effectively to
upload the input register to the output
register, but it affects only a selected
channel only, while the LDAC pin and
General Call Software Update command
affect all channels.
TABLE 5-2:
DAC CHANNEL SELECTION
BITS FOR SEQUENTIAL
WRITE COMMAND
DAC1
DAC0
Channels
0
0
1
1
0
1
0
1
Ch. A - Ch. D
Ch. B - Ch. D
Ch. C - Ch. D
Ch. D
DS22187C-page 36
© 2009 Microchip Technology Inc.
MCP4728
2
5.6.5
WRITE COMMAND: SELECT VREF
BIT (C2=1, C1=0, C0=0)
5.6.8
WRITE COMMAND: WRITE I C
ADDRESS BITS (C2=0, C1=1, C0=1)
When the device receives this command, it updates the
DAC voltage reference selection bit (VREF) of each
channel. The EEPROM data is not affected by this
command. The affected channel’s analog output is
updated after the acknowledge pulse of the last byte.
Figure 5-12 shows an example of the write command
for Select VREF bits.
This command writes new I2C address bits (A2, A1,
A0) to the DAC input registers and EEPROM. When
the device receives this command, it overwrites the
current address bits with the new address bits.
This command is valid only when the LDAC pin makes
a transition from “High” to “Low” at the low time of the
last bit (8th clock) of the second byte, and stays “Low”
until the end of the 3rd byte. The update occurs after
“Stop” bit if the conditions are met. The LDAC pin is
used to select a device of interest to write. The highest
clock rate of this command is 400 kHz. Figure 5-11
shows the details of the address write command.
5.6.6
WRITE COMMAND: SELECT
POWER-DOWN BITS (C2=1, C1=0,
C0=1)
When the device receives this command, it updates the
Power-Down selection bits (PD1, PD0) of each
channel. The EEPROM data is not affected by this
command. The affected channel is updated after the
acknowledge pulse of the last byte. Figure 5-13 shows
an example of the write command for the Select
Power-Down bits.
Note 1: To write a new device address, the
current address of the device is also
required. If the current address is not
known, it can be read out by sending
General Call Read Address Bits com-
mand. See 5.4.4 “General call Read
Address Bits” for more details of reading
the I2C address bits.
5.6.7
WRITE COMMAND: SELECT GAIN
BIT (C2=1, C1=1, C0=0)
When the device receives this command, it updates the
gain selection bits (GX) of each channel. The EEPROM
data is not affected by this command. The analog out-
put is updated after the acknowledge pulse of the last
byte. Figure 5-14 shows an example of the write com-
mand for select gain bits.
5.6.9
If the R/W bit is set to a logic “High” in the I2C serial
communications command, the device enters
reading mode and reads out the input registers and
EEPROM. Figure 5-15 shows the details of the read
command.
READ COMMAND
a
Note 1: The device address bits are read by using
General Call Read Address Bits
command.
© 2009 Microchip Technology Inc.
DS22187C-page 37
MCP4728
Command Type Bits:
C2=0
C1=0
C0=X
ACK (MCP4728)
Start
1st byte
A2 A1 A0
R/W
(C2 C1)
2nd Byte
PD1 PD0 D11 D10 D9 D8
3rd Byte
S
1
1
0
0
0
A
0
0
A
D7 D6 D5 D4 D3 D2 D1 D0 A
Device Addressing
Fast Write
Command
DAC Input Register of Channel A
Update Channel A DAC Input Register at this ACK pulse.
ACK (MCP4728)
3rd Byte
2nd Byte
PD1 PD0 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A
X
X
DAC Input Register of Channel B
Update Channel B DAC Input Register at this ACK pulse.
ACK (MCP4728)
3rd Byte
2nd Byte
X
X
PD1 PD0 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A
DAC Input Register of Channel C
Update Channel C DAC Input Register at this ACK pulse.
ACK (MCP4728)
3rd Byte
2nd Byte
PD1 PD0 D11 D10 D9 D8
X
X
A
D7 D6 D5 D4 D3 D2 D1 D0
A
DAC Input Register of Channel D
Update Channel D DAC Input Register at this ACK pulse.
Repeat Bytes
P
Stop
Note 1: X is a don’t care bit. VOUT can be updated after the last byte’s ACK pulse is issued and
by
bringing down the LDAC pin to “Low”.
FIGURE 5-7:
Fast Write Command: Write DAC Input Registers Sequentially from Channel A to D.
DS22187C-page 38
© 2009 Microchip Technology Inc.
MCP4728
Command Type Bits:
C2=0
C1=1
C0=0 W1=0 W0=0
ACK (MCP4728)
Start
1st byte
A2 A1 A0
S
1
1
0
0
0
A
R/W
Device Addressing
ACK (MCP4728)
(C2 C1 C0 W1 W2)
3rd Byte
4th Byte
2nd Byte
0
1
0
0
0 DAC1 DAC0 UDAC A VREF PD1 PD0 Gx D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A
Channel
Select
Multi-Write
Command
DAC Input Register of Selected Channel
Note 1
Repeat Bytes of the 2nd - 4th Bytes
ACK (MCP4728)
2nd byte
3rd Byte
4th Byte
D7 D6 D5 D4 D3 D2 D1 D0 A
X
X
X
X
X
DAC1 DAC0 UDAC A VREF PD1 PD0 Gx D11 D10 D9 D8
A
Channel
Select
Note 3
DAC Input Register of Selected Channel
Note 1
Note 2
Repeat Bytes of the 2nd - 4th Bytes
P
Stop
Note 1: VOUT Update:
If UDAC = 0 or LDAC Pin = 0: VOUT is updated after the 4th byte’s ACK is issued.
2: The user can write to the other channels by sending repeated bytes with new channel
selection bits (DAC1, DAC0).
3: X is don’t care bit.
FIGURE 5-8:
Multi-Write Command: Write Multiple DAC Input Registers.
© 2009 Microchip Technology Inc.
DS22187C-page 39
MCP4728
Command Type Bits:
C2=0
C1=1
C0=0 W1=1 W0=0
ACK (MCP4728)
Start
1st byte
A2 A1 A0
S
1
1
0
0
0
A
R/W
Device Addressing
ACK (MCP4728)
2nd Byte
(C2 C1 C0 W1 W2)
3rd Byte
4th Byte
0
1
0
1
0
DAC1 DAC0 UDAC A VREF PD1 PD0 Gx D11 D10 D9 D8
A
D7 D6 D5 D4 D3 D2 D1 D0
A
Sequential Write
Starting Channel
Select
Sequential Write
Command
DAC Input Register of Starting Channel
Note 1
Repeat Bytes of the 3rd - 4th Bytes
for the Starting Channel + 1, ... until Channel D.
ACK (MCP4728)
Stop
P
3rd Byte
4th Byte
D7 D6 D5 D4 D3 D2 D1 D0 A
VREF PD1 PD0 Gx D11 D10 D9 D8
A
DAC Input Register of Channel D
(Last Channel)
Notes 1 and 2
Note 1: VOUT Update:
If UDAC = 0 or LDAC Pin = 0: VOUT is updated after the 4th byte’s ACK is issued.
2: EEPROM Write:
The MCP4728 device starts writing EEPROM at the falling edge of the 4th byte’s ACK
pulse.
FIGURE 5-9:
Sequential Write Command: Write DAC Input Registers and EEPROM Sequentially
from Starting Channel to Channel D. The sequential input register starts with the "Starting Channel" and
ends at Channel D. For example, if DAC1:DAC0 = 00, then it starts with channel A and ends at channel D.
If DAC1:DAC0 = 01, then it starts with channel B and ends at Channel D. Note that this command can
send up to 10 bytes including the device addressing and command bytes. Any byte after the 10th byte is
ignored.
DS22187C-page 40
© 2009 Microchip Technology Inc.
MCP4728
Command Type Bits:
C2=0
C1=1
C0=0 W1=1 W0=1
ACK (MCP4728)
Start
1st byte
A2 A1 A0
S
1
1
0
0
0
A
R/W
Device Addressing
ACK (MCP4728)
Stop
C2 C1 C0 W1 W0
3rd Byte
DAC1 DAC0 UDAC A VREF PD1 PD0 Gx D11 D10 D9 D8
4th Byte
D7 D6 D5 D4 D3 D2 D1 D0
2nd Byte
0
1
0
1
1
A
A
P
Channel
Select
Single Write
Command
DAC Input Register of Selected Channel
Note 1 and Note 2
Note 1: VOUT Update:
If UDAC = 0 or LDAC Pin = 0: VOUT is updated after the 4th byte’s ACK is issued.
2: EEPROM Write:
The MCP4728 device starts writing EEPROM at the falling edge of the 4th byte’s ACK
pulse.
FIGURE 5-10:
Single Write Command: Write to a Single DAC Input Register and EEPROM.
© 2009 Microchip Technology Inc.
DS22187C-page 41
MCP4728
Command Type Bits:
C2=0
C1=1
C0=1
Start
Stop
A P
1st Byte
2nd Byte
3rd Byte
4th Byte
(C2 C1 C0)
S
1
1
0
0 A2 A1 A0 0
A
0
1
1 A2 A1 A0 0
1
A
0
1
1 A2 A1 A0 1
0
A
0
1
1
A2 A1 A0 1 1
R/W
Device
Current
Command Current
Type Address Bits
Command
Type Address Bits
New
Command New Address Bits
Code Address Bits
(for confirmation)
Type
Note 4
LDAC Pin
(Notes 1, 2, 3)
Note 3
Clock and LDAC Transition Details:
ACK (MCP4728)
Clock Pulse
(CLK Line)
Stop
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
-----
9
P
4th Byte
2nd Byte
3rd Byte
Note 4
Note 2(b)
LDAC Pin
Note 2(b)
Note 3
Note 2 (a)
Stay “Low” during this 3rd byte
Note 1: Clock Pulse and LDAC Transition Details.
2: LDAC pin events at the 2nd and 3rd bytes:
a. Keep LDAC pin “High” until the end of the positive pulse of the 8th clock of the
2nd byte.
b. LDAC pin makes a transition from “High” to “Low” during the negative pulse of the
8th clock of the 2nd byte (just before the rising edge of the 9th clock), and stays
“Low” until the rising edge of the 9th clock of the 3rd byte.
c.
The MCP4728 device does not acknowledge the 3rd byte if the conditions (a) and
(b) are not met.
3: LDAC pin resumes its normal function after “Stop” bit.
4: EEPROM Write:
a. Charge Pump initiates the EEPROM write sequence at the falling edge of the 4th
byte’s ACK pulse.
b. The RDY/BSY bit (pin) goes “Low” at the falling edge of this ACK clock and back
to “High” immediately after the EEPROM write is completed.
2
FIGURE 5-11:
Write Command: Write I C Address Bits to the DAC Registers and EEPROM.
DS22187C-page 42
© 2009 Microchip Technology Inc.
MCP4728
Command Type Bits:
Start
C2=1
C1=0
C0=0
ACK (MCP4728)
Stop
1st byte
(C2 C1 C0)
2nd Byte
S
1
1
0
0
A2 A1 A0
0
A
1
0
0
X
VREF A VREF B VREF C VREF
D
A
P
R/W
Device Addressing
Write
Note 1
Command
Registers and VOUT are updated
at this falling edge of ACK pulse.
Note 1: VREF = 0: VDD
= 1: Internal Reference (2.048V)
REF A = Voltage reference of Channel A
REF B = Voltage reference of Channel B
REF C = Voltage reference of Channel C
REF D = Voltage reference of Channel D
V
V
V
V
2: X is don’t care bit.
FIGURE 5-12:
Write Command: Write Voltage Reference Selection Bit (V
) to the DAC Input
REF
Registers.
Command Type Bits:
C2=1
C1=0
C0=1
ACK (MCP4728)
Start
1st byte
A2 A1 A0
S
1
1
0
0
0
A
R/W
Device Addressing
Stop
ACK (MCP4728)
(C2 C1 C0)
3rd Byte
2nd Byte
PD1 A PD0 A PD1 B PD0 B
1
0
1
X
A
PD1 C PD0 C PD1 D PD0 D
X
X
X
X
A
P
Command Channel A
Channel B
Channel C
Channel D
Write
for Power-Down
Selection Bits
Registers and VOUT are updated
at this falling edge of ACK pulse.
Note 1: X is don’t care bit.
FIGURE 5-13:
Write Command: Write Power-Down Selection Bits (PD1, PD0) to the DAC Input
Registers. See Table 4-7 for the power-down bit setting.
© 2009 Microchip Technology Inc.
DS22187C-page 43
MCP4728
Command Type Bits:
C2=1
C1=1
C0=0
ACK (MCP4728)
(C2 C1 C0)
Start
1st Byte
A2 A1 A0
2nd Byte
GX GX
Stop
S
1
1
0
0
0
A
1
1
0
X
GX
A
B
C
GX
D
A
P
R/W
Command
Write
for Gain Selection Bits
Device Addressing
Note 1
Registers and VOUT are updated
at this falling edge of ACK pulse.
Note 1: GX A = Gain Selection for Channel A
GX B = Gain Selection for Channel B
GX C = Gain Selection for Channel C
GX D = Gain Selection for Channel D
Ex: GX A = 0: Gain of 1 for Channel A
= 1: Gain of 2 for Channel A
2: X is don’t care bit.
FIGURE 5-14:
Write Command: Write Gain Selection Bit (G ) to the DAC Input Registers.
X
DS22187C-page 44
© 2009 Microchip Technology Inc.
MCP4728
Read Command
ACK (MCP4728)
Start
S
1
1
0
0
A2 A1 A0
1
A
R/W
Device Code Address Bits
2nd Byte
ACK (MCP4728)
Stop
3rd Byte
4th Byte
RDY/
BSY
POR DAC1 DAC 0
0
A2 A1 A0
A
V
PD1 PD0
G
D11 D10 D9 D8
X
A
A
A
A
A
A
A
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
REF
Channel A DAC Input Register
6th Byte
Stop
5th Byte
7th Byte
RDY/
BSY
POR DAC1 DAC 0
0
A2 A1 A0
A
V
PD1 PD0
G
D11 D10 D9 D8
X
D7 D6 D5 D4 D3 D2 D1 D0
A
P
REF
Channel A DAC EEPROM
3rd Byte
Stop
2nd Byte
4th Byte
RDY/
BSY
POR DAC1 DAC 0
0
A2 A1 A0
A
V
PD1 PD0
G
D11 D10 D9 D8
X
D7 D6 D5 D4 D3 D2 D1 D0
A
P
REF
Channel B DAC Input Register
6th Byte
Stop
5th Byte
7th Byte
RDY/
BSY
POR DAC1 DAC 0
0
A2 A1 A0
A
V
PD1 PD0
G
D11 D10 D9 D8
X
D7 D6 D5 D4 D3 D2 D1 D0
A
P
REF
Channel B DAC EEPROM
3rd Byte
Stop
2nd Byte
4th Byte
RDY/
BSY
POR DAC1 DAC 0
0
A2 A1 A0
A
V
PD1 PD0
G
D11 D10 D9 D8
X
D7 D6 D5 D4 D3 D2 D1 D0
A
P
REF
Channel C DAC Input Register
6th Byte
Stop
5th Byte
7th Byte
RDY/
BSY
POR DAC1 DAC 0
0
A2 A1 A0
A
V
PD1 PD0
G
D11 D10 D9 D8
X
D7 D6 D5 D4 D3 D2 D1 D0
A
P
REF
Channel C DAC EEPROM
3rd Byte
Stop
2nd Byte
4th Byte
RDY/
BSY
POR DAC1 DAC 0
0
A2 A1 A0
A
V
PD1 PD0
G
D11 D10 D9 D8
X
D7 D6 D5 D4 D3 D2 D1 D0
A
P
REF
Channel D DAC Input Register
6th Byte
Stop
5th Byte
7th Byte
RDY/
BSY
POR DAC1 DAC 0
0
A2 A1 A0
A
V
PD1 PD0
G
D11 D10 D9 D8
X
D7 D6 D5 D4 D3 D2 D1 D0
A
P
REF
Repeat
Channel D DAC EEPROM
Note 1: The 2nd - 4th bytes are the contents of the DAC Input Register and the 5th - 7th bytes
are the EEPROM contents.
The device outputs sequentially from channel A to D.
POR Bit: 1 = Set (Device is powered on with VDD > VPOR), 0 = Powered off state.
FIGURE 5-15:
Read Command and Device Outputs.
© 2009 Microchip Technology Inc.
DS22187C-page 45
MCP4728
NOTES:
DS22187C-page 46
© 2009 Microchip Technology Inc.
MCP4728
6.0
6.1
TERMINOLOGY
Resolution
7
6
INL = < -1 LSB
The resolution is the number of DAC output states that
divide the full scale range. For the 12-bit DAC, the
resolution is 212, meaning the DAC code ranges from 0
to 4095.
INL = - 1 LSB
5
Analog 4
Output
INL = 0.5 LSB
3
2
1
0
(LSB)
6.2
LSB
The least significant bit or the ideal voltage difference
between two successive codes.
EQUATION 6-1:
000 001 010 011 100 101 110 111
DAC Input Code
VREF
2n
------------
LSB
=
Ideal Transfer Function
Actual Transfer Function
(VFull Scale – VZero Scale
)
= ---------------------------------------------------------
212 – 1
FIGURE 6-1:
INL Accuracy.
(VFull Scale – VZero Scale
= ---------------------------------------------------------
4095
)
6.4
Differential Nonlinearity (DNL)
Where
VREF
Differential nonlinearity (DNL) error (see Figure 6-2) is
the measure of step size between codes in actual
transfer function. The ideal step size between codes is
1 LSB. A DNL error of zero would imply that every code
is exactly 1 LSB wide. If the DNL error is less than
1 LSB, the DAC guarantees monotonic output and no
missing codes. The DNL error between any two
adjacent codes is calculated as follows:
=
VDD If external reference is
selected
=
=
2.048V If internal reference is
selected
n
The number of digital input bits,
n = 12 for MCP4728.
6.3
Integral Nonlinearity (INL)
EQUATION 6-3:
DNL ERROR
Integral nonlinearity (INL) error is the maximum
deviation of an actual transfer function from an ideal
transfer function (straight line). In the MCP4728, INL is
calculated using two end-points (zero and full scale).
INL can be expressed as a percentage of full scale
range (FSR) or in fraction of an LSB. INL is also called
relative accuracy. Equation 6-2 shows how to calculate
the INL error in LSB and Figure 6-1 shows an example
of INL accuracy.
ΔVOUT – LSB
DNL = ----------------------------------
LSB
Where:
DNL is expressed in LSB.
ΔV
=
The measured DAC output
voltage difference between two
adjacent input codes.
OUT
EQUATION 6-2:
INL ERROR
(VOUT – VIdeal
)
INL = ---------------------------------------
LSB
Where:
INL is expressed in LSB
VIdeal
VOUT
=
=
Code*LSB
The output voltage measured at
the given input code
© 2009 Microchip Technology Inc.
DS22187C-page 47
MCP4728
For the MCP4728 device, the gain error is not
calibrated at the factory and most of the gain error is
contributed by the output buffer (op amp) saturation
near the code range beyond 4000. For applications that
need the gain error specification less than 1%
maximum, a user may consider using the DAC code
range between 100 and 4000 instead of using full code
range (code 0 to 4095). The DAC output of the code
range between 100 and 4000 is much more linear than
full scale range (0 to 4095). The gain error can be
calibrated out by software in applications.
7
6
DNL = 0.5 LSB
5
DNL = 2 LSB
4
3
Analog
Output
(LSB)
2
1
0
6.7
Full Scale Error (FSE)
Full scale error (see Figure 6-4) is the sum of offset
error plus gain error. It is the difference between the
ideal and measured DAC output voltage with all bits set
to one (DAC input code = FFFh).
000
001
011
010
100
110
101
111
DAC Input Code
Ideal Transfer Function
Actual Transfer Function
EQUATION 6-4:
(VOUT – VIdeal
FSE = ---------------------------------------
LSB
)
FIGURE 6-2:
DNL Accuracy.
Where:
6.5
Offset Error
FSE is expressed in LSB.
Offset error (see Figure 6-3) is the deviation from zero
voltage output when the digital input code is zero (zero
scale voltage). This error affects all codes by the same
amount. For the MCP4728 device, the offset error is
not trimmed at the factory. However, it can be calibrated
by software in application circuits.
VIdeal
VREF
=
=
(VREF) (1 - 2-n) - Offset Voltage (VOS
Voltage Reference
)
Full Scale
Error
Actual Transfer Function
Actual Transfer Function
Analog
Output
Gain Error
Analog
Output
Actual Transfer Function
after Offset Error is removed
Ideal Transfer Function
Offset
Error
Ideal Transfer Function
0
DAC Input Code
FIGURE 6-3:
Offset Error.
0
DAC Input Code
FIGURE 6-4:
Error.
Gain Error and Full Scale
6.6
Gain Error
Gain error (see Figure 6-4) is the difference between
the actual full scale output voltage from the ideal output
voltage of the DAC transfer curve. The gain error is
calculated after nullifying the offset error, or full scale
error minus the offset error.
6.8
Gain Error Drift
Gain error drift is the variation in gain error due to a
change in ambient temperature. The gain error drift is
typically expressed in ppm/°C.
The gain error indicates how well the slope of the actual
transfer function matches the slope of the ideal transfer
function. The gain error is usually expressed as percent
of full scale range (% of FSR) or in LSB.
DS22187C-page 48
© 2009 Microchip Technology Inc.
MCP4728
6.9
Offset Error Drift
6.13 Analog Crosstalk
Offset error drift is the variation in offset error due to a
change in ambient temperature. The offset error drift is
typically expressed in ppm/oC.
Analog crosstalk is the glitch that appears at the output
of one DAC due to a change in the output of the other
DAC. The area of the glitch is expressed in nV-Sec,
and measured by loading one of the input registers with
a full scale code change (all 0s to all 1s and vice versa)
while keeping both UDAC bit and LDAC pin high. Then
bring down the LDAC pin to low and measure the
output of the DAC whose digital code was not changed.
6.10 Settling Time
The Settling time is the time delay required for the DAC
output to settle to its new output value from the start of
code transition, within specified accuracy. In the
MCP4728 device, the settling time is a measure of the
time delay until the DAC output reaches its final value
within 0.5 LSB when the DAC code changes from 400h
to C00h.
6.14 DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch that appears at the
output of one DAC due to an input code change and
subsequent output change of the other DAC. This
includes both digital and analog crosstalks. The area of
the glitch is expressed in nV-Sec, and measured by
loading one of the input registers with a full scale code
change (all 0s to all 1s and vice versa) while keeping
UDAC bit or LDAC pin low.
6.11 Major-Code Transition Glitch
Major-code transition glitch is the impulse energy
injected into the DAC analog output when the code in
the DAC register changes state. It is normally specified
as the area of the glitch in nV-Sec. and is measured
when the digital code is changed by 1 LSB at the major
carry transition (Example: 011...111 to 100...
000, or 100... 000to 011... 111).
6.15 Power-Supply Rejection Ratio
(PSRR)
PSRR indicates how the output of the DAC is affected
by changes in the supply voltage. PSRR is the ratio of
the change in VOUT to a change in VDD for full scale
output of the DAC. It is measured on one DAC that is
using an internal VREF while the VDD is varied +/- 10%,
and expressed in dB or µV/V.
6.12 Digital Feedthrough
Digital feedthrough is the glitch that appears at the
analog output caused by coupling from the digital input
pins of the device. The area of the glitch is expressed
in nV-Sec, and is measured with a full scale change
(Example: all 0s to all 1s and vice versa) on the digital
input pins. The digital feedthrough is measured when
the DAC is not being written to the output register. This
condition can be created by writing input register with
both UDAC bit and LDAC pin high.
© 2009 Microchip Technology Inc.
DS22187C-page 49
MCP4728
NOTES:
DS22187C-page 50
© 2009 Microchip Technology Inc.
MCP4728
7.1
Connecting to I2C BUS using
Pull-Up Resistors
7.0
TYPICAL APPLICATIONS
The MCP4728 device is a part of Microchip’s latest
DAC family with non-volatile EEPROM memory. The
device is a general purpose resistor string DAC
intended to be used in applications where a precision,
and low power DAC with moderate bandwidth is
required.
The SCL, SDA, and RDY/BSY pins of the MCP4728
device are open-drain configurations. These pins
require a pull-up resistor as shown in Figure 7-1. The
LDAC pin has a schmitt trigger input configuration and
it can be driven by an external MCU I/O pin.
Since the device includes non-volatile EEPROM
memory, the user can use this device for applications
that require the output to return to the previous set-up
value on subsequent power-ups.
The pull-up resistor values (R1 and R2) for SCL and
SDA pins depend on the operating speed (standard,
fast, and high speed) and loading capacitance of the
I2C bus line. Higher value of pull-up resistor consumes
less power, but increases the signal transition time
(higher RC time constant) on the bus line. Therefore, it
can limit the bus operating speed. A lower resistor
value, on the other hand, consumes higher power, but
allows for higher operating speed. If the bus line has
higher capacitance due to long metal traces or multiple
device connections to the bus line, a smaller pull-up
resistor is needed to compensate the long RC time
constant. The pull-up resistor is typically chosen
between 1 kΩ and 10 kΩ ranges for standard and fast
modes, and less than 1 kΩ for high speed mode.
Applications generally suited for the MCP4728 device
family include:
• Set Point or Offset Trimming
• Sensor Calibration
• Portable Instrumentation (Battery Powered)
• Motor Speed Control
VDD
C1
C2
R1
R2
VSS
VDD
1
10
9
VOUT
VOUT
D
C
SCL
2
R3
SDA
8
7
6
MCP4728
3
Analog Outputs
V
OUT B
OUT A
LDAC 4
V
RDY/BSY
5
To MCU
R1 - R3 are the pull-up resistors:
R1 and R2 (Pull-up resistors for
I2C Serial Communications):
5 kΩ - 10 kΩ for fSCL
~700Ω for fSCL
=
=
100 kHz to 400 kHz
3.4 MHz
R3 (Pull-Up resistor ( ~ 100 kΩ)
to monitor RDY/BSY bit. Leave
this pin float if it is not used.):
C1: 0.1 µF, Ceramic capacitor
C2: 10 µF, Tantalum capacitor
FIGURE 7-1:
Example of the MCP4728 Device Connection.
© 2009 Microchip Technology Inc.
DS22187C-page 51
MCP4728
7.1.1
DEVICE CONNECTION TEST
7.3
Power Supply Considerations
The user can test the presence of the MCP4728 device
on the I2C bus line without performing a data
conversion. This test can be achieved by checking an
acknowledge response from the MCP4728 device after
sending a read or write command. Figure 7-2 shows an
example with a read command:
The power source should be as clean as possible. The
power supply to the device is used for both VDD and
DAC voltage reference by selecting VREF = VDD. Any
noise induced on the VDD line can affect DAC
performance. A typical application will require a bypass
capacitor in order to filter out high frequency noise on
the VDD line. The noise can be induced onto the power
supply’s traces or as a result of changes on the DAC
output. The bypass capacitor helps to minimize the
effect of these noise sources on signal integrity.
Figure 7-1 shows an example of using two bypass
capacitors (a 10 µF tantalum capacitor and a 0.1 µF
ceramic capacitor) in parallel on the VDD line. These
capacitors should be placed as close to the VDD pin as
possible (within 4 mm). If the application circuit has
separate digital and analog power supplies, the VDD
and VSS pins of the MCP4728 device should reside on
the analog plane.
a. Set the R/W bit “High” or “Low” in the address
byte.
b. Check the ACK pulse after sending the address
byte.
If the device acknowledges (ACK = 0) the
command, then the device is connected,
otherwise it is not connected.
c. Send Stop bit.
Address Byte
SCL
SDA
1
1
2
1
3
0
4
5
6
7
8
1
9
7.4
Using Power Saving Feature
The device consumes very little power when it is in
Power-Down (shut-down) mode. During the
Power-Down mode, most circuits in the selected
channel are turned off. It is recommended to power
down any unused channel.
1 A2 A1 A0
Start
Bit
Stop
Bit
Address bits
Device Code
R/W
The device consumes the least amount of power if it
enters the Power-Down mode after the internal voltage
reference is disabled. This can be achieved by
selecting VDD as the voltage reference for all 4
channels and then issuing the Power-Down mode for
all channels.
MCP4728
Response
2
FIGURE 7-2:
I C Bus Connection Test.
7.2
Layout Considerations
Inductively-coupled AC transients and digital switching
noise from other devices can affect DAC performance
and DAC output signal integrity. Careful board layout
will minimize these effects. Bench testing has shown
that a multi-layer board utilizing a low-inductance
ground plane, isolated inputs, isolated outputs and
proper decoupling are critical to achieving good DAC
performance.
7.5
Using Non-Volatile EEPROM
Memory
The user can store the I2C device address bits,
configuration bits and DAC input code of each channel
in the on-board non-volatile EEPROM memory using
the I2C write command. The contents of EEPROM are
readable and writable using the I2C command.
Separate digital and analog ground planes are
recommended. In this case, the VSS pin and the ground
pins of the VDD capacitors of the MCP4728 should be
terminated to the analog ground plane.
When the MCP4728 device is first powered-up or
receives General Call Reset Command, it uploads the
EEPROM contents to the DAC output registers
automatically and provides analog outputs immediately
with the saved settings in EEPROM. This feature is
very useful in applications where the MCP4728 device
is used to provide set points or calibration data for other
devices in the application systems. The MCP4728
device can save important system parameters when
the application system experiences power failure. See
Section 5.5 “Writing and Reading Registers and
EEPROM” for more details on using the non-volatile
EEPROM memory.
DS22187C-page 52
© 2009 Microchip Technology Inc.
MCP4728
7.6.1
DC SET POINT OR CALIBRATION
VOLTAGE SETTINGS
7.6
Application Examples
The MCP4728 device is a rail-to-rail output DAC
designed to operate with a VDD range of 2.7V to 5.5V.
Its output amplifier of each channel is robust enough to
drive common, small-signal loads directly, thus
eliminating the cost and size of external buffers for
most applications. Since each channel has its own
configuration bits for selecting the voltage reference,
gain, power-down, etc., the MCP4728 device offers
great simplicity and flexibility to use for various DAC
applications.
A common application for the MCP4728 device is a
digitally-controlled set point or a calibration of variable
parameters such as sensor offset or bias point.
Figure 7-3 shows an example of the set point settings.
Let us consider that the application requires different
trip voltages (Trip 1 - Trip 4). Assuming the DAC output
voltage requirements are given as shown in Table 7-1,
examples of sending the Sequential Write and Fast
Write commands are shown in Figure 7-4 and
Figure 7-5.
TABLE 7-1:
EXAMPLE: SETTING V OF
OUT
EACH CHANNEL
Voltage
Reference
DAC Output
(VOUT
DAC Channel
)
VDD
VDD
VDD/2
VDD - 1 LSB
2.048V
VOUT
VOUT
VOUT
VOUT
A
B
C
D
Internal
Internal
4.096V
© 2009 Microchip Technology Inc.
DS22187C-page 53
MCP4728
VDD
Light
Comparator 1
RSENSE
R1
V
TRIP1
R2
0.1 µF
VDD
Light
Comparator 2
RSENSE
R1
VDD
0.1 µF 10 µF
V
TRIP2
R1
R2
0.1 µF
R2
VSS
10
VDD
SCL
1
2
R3
VOUT
9
D
C
R4
VOUT
SDA
8
7
6
MCP4728
3
V
V
OUT B
OUT A
LDAC 4
RDY/BSY
VDD
Light
5
Analog Outputs
Comparator 3
RSENSE
R1
V
TRIP3
To MCU
R2
0.1 µF
VDD
Light
Dn = Input Code (0 to 4095)
Dn
Comparator 4
RSENSE
R1
-----------
Gx
VOUT = VREF
×
4096
V
TRIP4
R2
⎛
⎞
⎠
------------------
R1 + R2
VTRIP = VOUT
⎝
R2
0.1 µF
FIGURE 7-3:
Using the MCP4728 for Set Point or Threshold Calibration.
DS22187C-page 54
© 2009 Microchip Technology Inc.
MCP4728
ACK (MCP4728)
Start
R/W
UDAC VREF
GX
S
1
1
0
0
0
0
0
0
A
0
1
0
1
0
0
0
0
A
0
0
0
0
1
0
0
0
A
0
0
0
0
0
0
0
0
A
1st Byte
Device Addressing
Sequential Write Selecting
Command Channel A as
Starting Channel
Dn = 211 = 2048
Update DAC A Input Register at this ACK pulse.
ACK (MCP4728)
VREF
GX
0
0
0
0
1 1 1 1 A 1 1 1 1 1 1 1 1 A
Dn = 4095
Update DAC B Input Register at this ACK pulse.
ACK (MCP4728)
VREF
GX
1
0
0
1
1 0 0 0 A 0 0 0 0 0 0 0 0 A
Dn = 2048
Update DAC C Input Register at this ACK pulse.
ACK (MCP4728)
Stop
P
VREF
GX
1
0
0
1
1 1 1 1 A 1 1 1 1 1 1 1 1 A
Dn = 4095
Update DAC D Input Register at this ACK pulse.
Expected Output Voltage at Each Channel:
Dn
VDD
2048
-----------
4096
-----------
4096
VOUT A = VDD
VOUT B = VDD
×
×
= VDD
= VDD
×
×
= ---------- (V)
2
Dn
4095
-----------
-----------
4096
=
(VDD – LSB) (V)
4096
Dn
2048
-----------
4096
-----------
4096
VOUT C = VREF
VOUT D = VREF
×
×
Gx = 2.048 ×
Gx = 2.048 ×
× 2 = 2.048 (V)
× 2 = 4.096 (V)
Dn
4095
-----------
-----------
4096
4096
FIGURE 7-4:
Sequential Write Command for Setting Test Points in Figure 7-3.
© 2009 Microchip Technology Inc.
DS22187C-page 55
MCP4728
Start
Stop
1st Byte
0 A2 A1 A0 0
2nd Byte
3rd Byte
S
1
1
0
A
0
1
1 A2 A1 A0 0
1
A
0
1
1 A2 A1 A0 1
0
A
. . . . . . .
P
Address Byte
Fast Mode
Write Command
DAC A
Next DAC Channels
The following example shows the expected analog outputs with the corresponding DAC input codes:
DAC A Input Code = 001111-11111111
DAC B Input Code = 000111-11111111
DAC C Input Code = 000011-11111111
DAC D Input Code = 000001-11111111
(V
× D )
REF
n
V
= --------------------------------- G
OUT
x
4096
(A) Channel A Output:
Dn for Channel A = 0FFF (hex) = 4095 (decimal)
(V
× 4095)
4096 – 1
4096
DD
= ----------------------------------- = V
1
⎞
⎛
⎞
⎠
⎛
--------------------
V
A
= V
1 – ----------- = V
– LSB
OUT
(B) Channel B Output:
Dn for Channel B = 07FF (hex) = 2047 (decimal)
DD⎝
DD⎝
⎠
4096
DD
DD
4096
(V
× 2047)
V
V
2048 – 1
4096
DD
= ----------------------------------- = V
DD
2
⎞
⎛
⎞
⎠
⎛
--------------------
V
B
= ------------ 1 – ----------- = ------------ – LSB
OUT
DD⎝
⎝
⎠
4096
4096
2
2
(C) Channel C Output:
Dn for Channel C = 03FF (hex) = 1023 (decimal)
V
× 1023
V
V
1024 – 1
4096
DD
= ---------------------------------- = V
DD
4
4
⎞
DD
4
⎛
⎞
⎠
⎛
--------------------
V
C
= ------------ 1 – ----------- = ------------ – LSB
OUT
(D) Channel D Output:
Dn for Channel D = 01FF (hex) = 511 (decimal)
DD⎝
⎝
⎠
4096
4096
V
× 511
V
V
512 – 1
4096
DD
= ------------------------------- = V
DD
8
8
⎞
DD
8
⎛
⎞
⎠
⎛
-----------------
V
D
= ------------ 1 – ----------- = ------------ – LSB
OUT
DD⎝
⎝
⎠
4096
4096
FIGURE 7-5:
Example of Writing Fast Write Command for Various V
. V
= V for all
OUT REF DD
Channels.
DS22187C-page 56
© 2009 Microchip Technology Inc.
MCP4728
8.0
8.1
DEVELOPMENT SUPPORT
Evaluation & Demonstration
Boards
The MCP4728 Evaluation Board is available from
Microchip Technology Inc. This board works with Micro-
chip’s PICkit™ Serial Analyzer. The user can easily
program the DAC input registers and EEPROM using
the PICkit Serial Analyzer, and test out the DAC analog
output voltages.The PICkit Serial Analyzer uses the PC
Graphic User Interface software. Refer to www.micro-
chip.com for further information on this product’s capa-
bilities and availability.
FIGURE 8-2:
Setup for the MCP4728
Evaluation Board with PICkit™ Serial Analyzer.
FIGURE 8-1:
MCP4728 Evaluation
Board.
FIGURE 8-3:
Example of PICkit™ Serial User Interface.
© 2009 Microchip Technology Inc.
DS22187C-page 57
MCP4728
NOTES:
DS22187C-page 58
© 2009 Microchip Technology Inc.
MCP4728
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
10-Lead MSOP
Example
XXXXXX
YWWNNN
4728
906256
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS22187C-page 59
MCP4728
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1
2
b
e
c
A
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,ꢁ ꢐꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢔꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢔꢅꢑꢉꢊꢅꢕꢖꢒ*ꢅ-ꢀꢗꢁ+ꢒꢁ
.ꢖ/0 .ꢇ ꢃꢍꢅꢐꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢘꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ
ꢙ*10 ꢙꢉ$ꢉꢊꢉꢄꢍꢉꢅꢐꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ
ꢒꢃꢍꢊꢌꢍꢎꢃꢑ ꢘꢉꢍꢎꢄꢌꢈꢌꢔꢋ ꢐꢊꢇ)ꢃꢄꢔ /ꢓꢗꢞꢓꢏꢀ.
DS22187C-page 60
© 2009 Microchip Technology Inc.
MCP4728
APPENDIX A: REVISION HISTORY
Revision C (September 2009)
The following is the list of modifications:
1. Updated Figure 5-11 and Figure 7-4.
Revision B (August 2009)
The following is the list of modifications:
2. Updated Figure 2-25 to Figure 2-41 in
Section 2.0 “Typical Performance Curves”.
3. Updated Figure 5-7, Figure 5-8 and Figure 5-11.
Revision A (June 2009)
• Original Release of this Document.
© 2009 Microchip Technology Inc.
DS22187C-page 61
MCP4728
NOTES:
DS22187C-page 62
© 2009 Microchip Technology Inc.
MCP4728
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
‚
PART NO.
Device
X
/XX
a)
MCP4728:
Tape and Reel,
Temperature
Range
Package
Extended Temperature,
10LD MSOP package.
Device:
MCP4728:
Single Comparator
° °
= -40 C to +125 C
Temperature Range:
Package:
E
UN = Plastic Micro Small Outline Transistor, 10-lead
© 2009 Microchip Technology Inc.
DS22187C-page 63
MCP4728
NOTES:
DS22187C-page 64
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS22187C-page 65
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Cleveland
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
03/26/09
DS22187C-page 66
© 2009 Microchip Technology Inc.
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