KSZ8041NL-AM_技术文档

KSZ8041NL/RNL

10BASE-T/100BASE-TX

Physical Layer Transceiver

Highlights

Key Benefits

• Single-Chip Ethernet Physical Layer Transceiver

(PHY)

• Single-Chip 10BASE-T/100BASE-TX Physical

Layer Solution

• HP Auto-MDIX Support

• Fully Compliant To IEEE 802.3u Standard

• Low Power CMOS Design, Power Consumption

of <180 mW

Target Applications

• HP Auto MDI/MDI-X For Reliable Detection and

Correction for Straight-Through and Crossover

Cables with Disable and Enable Option

• Printer

• LOM

• Game Console

• IPTV

• Robust Operation Over Standard Cables

• Power Down and Power Saving Modes

• MII Interface Support (KSZ8041NL Only)

• IP Phone

• IP Set-Top Box

• RMII Interface Support with External 50-MHz

System Clock (KSZ8041NL Only)

• RMII Interface Support with 25-MHz Crystal/Clock

Input and 50-MHz Reference Clock Output to

MAC (KSZ8041RNL Only)

• MIIM (MDC/MDIO) Management Bus to 6.25 MHz

for Rapid PHY Register Configuration

• Interrupt Pin Option

• Programmable LED Outputs for Link, Activity

and Speed

• ESD Rating (6 kV)

• Single Power Supply (3.3V)

• Built-in 1.8V Regulator for Core

• Available In 32-pin 5 mm × 5 mm QFN Package

DS00002245B-page 1

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-

rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the

revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are

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DS00002245B-page 2

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

Table of Contents

1.0 General Description ........................................................................................................................................................................ 4

2.0 Pin Description and Configuration .................................................................................................................................................. 6

3.0 Functional Description .................................................................................................................................................................. 17

4.0 Registers ....................................................................................................................................................................................... 29

5.0 Operational Characteristics ........................................................................................................................................................... 38

6.0 Electrical Characteristics ............................................................................................................................................................... 39

7.0 Timing Diagrams ........................................................................................................................................................................... 40

8.0 Selection of Isolation Transformer ................................................................................................................................................ 50

9.0 Selection of Reference Crystal ..................................................................................................................................................... 51

10.0 Package Outline & Recommended Land Pattern ....................................................................................................................... 52

Appendix A: Data Sheet Revision History ........................................................................................................................................... 53

The Microchip Web Site ...................................................................................................................................................................... 54

Customer Change Notification Service ............................................................................................................................................... 54

Customer Support ............................................................................................................................................................................... 54

Product Identification System ............................................................................................................................................................. 55

 2017 Microchip Technology Inc.

DS00002245B-page 3

KSZ8041NL/RNL

1.0

GENERAL DESCRIPTION

The KSZ8041NL is a single supply 10BASE-T/100BASE-TX physical layer transceiver, which provides

MII/RMII interfaces to transmit and receive data. A unique mixed-signal design extends signaling distance

while reducing power consumption.

HP Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between

crossover and straight-through cables.

The KSZ8041NL represents a new level of features and performance and is an ideal choice of physical layer

transceiver for 10BASE-T/100BASE-TX applications.

The KSZ8041RNL is an enhanced Reduced Media Independent Interface (RMII) version of the

KSZ8041NL that does not require a 50-MHz system clock. It uses a 25-MHz crystal for its input reference

clock and outputs a 50-MHz RMII reference clock to the media access control (MAC).

The KSZ8041NL and KSZ8041RNL are available in 32-pin, lead-free QFN packages (see Product Identifi-

cation System).

FIGURE 1-1:

KSZ8041NL FUNCTIONAL DIAGRAM

4B/5B Encoder

Scrambler

Parallel/Serial

NRZ/NRZI

MLT3 Encoder

MDC

MDIO

10/100

Pulse

Shaper

TX+

Transmitter

TXC

TX-

TXEN

TXD3

TXD2

TXD1

TXD0

Parallel/Serial

Manchester Encoder

REXT

MII/RMII

Registers

Adaptive EQ

Base Line

Wander Correction

MLT3 Decoder

NRZI/NRZ

RXC

4B/5B Decoder

Descrambler

Serial/Parallel

RX+

RX-

and

RXDV

RXD3

RXD2

Clock

Recovery

Controller

Interface

RXD1

RXD0

RXER

Auto

Negotiation

CRS

COL

10Base-T

Receiver

Manchester Decoder

Serial/Parallel

INTRP

RST#

Power Down

Power Saving

XI

LED0

LED1

LED

PLL

XO

Driver

DS0002245B-page 4

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

FIGURE 1-2:

KSZ8041RNL FUNCTIONAL DIAGRAM

4B/5B Encoder

Scrambler

Parallel/Serial

NRZ/NRZI

MLT3 Encoder

MDC

MDIO

10/100

Pulse

Shaper

TX+

TX-

Transmitter

TX_EN

TXD1

TXD0

Parallel/Serial

Manchester Encoder

REXT

CRS_DV

RXD1

RXD0

RMII

Adaptive EQ

Base Line

Wander Correction

MLT3 Decoder

NRZI/NRZ

4B/5B Decoder

Descrambler

Serial/Parallel

RX+

RX-

Clock

Recovery

RX_ER

REF_CLK

Auto

Negotiation

10Base-T

Receiver

Manchester Decoder

Serial/Parallel

INTRP

RST#

Power Down

Power Saving

XI

LED0

LED1

LED

PLL

XO

Driver

 2017 Microchip Technology Inc.

DS0002245B-page 5

KSZ8041NL/RNL

2.0

2.1

PIN DESCRIPTION AND CONFIGURATION

KSZ8041NL Pin Description and Configuration

FIGURE 2-1:

KSZ8041NL 32-QFN PIN ASSIGNMENT (TOP VIEW)

32 31 30 29 28 27 26 25

1

2

24

23

GND

VDDPLL_1.8

VDDA_3.3

RX-

TXD0/TXD[0]

TXEN/TX_EN

3

4

5

22 TXC

21

INTRP

RXER/RX_ER/ISO

RXC

RXDV/CRSDV/CONFIG2

VDDIO_3.3

Paddle Ground

on bottom of chip

20

RX+

TX-

TX+

XO

6

7

8

19

18

17

9

10 11 12 13 14 15 16

TABLE 2-1:

Pin Number

KSZ8041NL PIN DESCRIPTION

Buffer Type

Symbol

Description

(Note 2-1)

1

2

GND

Gnd

P

Ground

1.8V Analog V_DD

Decouple with 1.0-µF and 0.1-µF capacitors to ground.

VDDPLL_1.8

3

4

5

6

VDDA_3.3

RX-

P

3.3V Analog V_DD

I/O

Physical receive or transmit signal (- differential)

Physical receive or transmit signal (+ differential)

Physical transmit or receive signal (- differential)

RX+

TX-

DS00002245B-page 6

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

TABLE 2-1:

Pin Number

KSZ8041NL PIN DESCRIPTION (CONTINUED)

Buffer Type

Symbol

Description

(Note 2-1)

7

8

TX+

XO

I/O

Physical transmit or receive signal (+ differential)

Crystal Feedback.

This pin is used only in MII mode when a 25-MHz crystal is used.

This pin is a no connect if an oscillator or an external clock source is

used, or if RMII mode is selected.

O

Crystal/Oscillator/External Clock Input:

MII mode: 25 MHz ±50 ppm (crystal, oscillator, or external clock)

RMII mode: 50 MHz ±50 ppm (oscillator or external clock only)

XI /

REFCLK

9

I

Set physical transmit output current.

Connect a 6.49-K resistor in parallel with a 100-pF capacitor to

ground on this pin.

10

REXT

I/O

Management Interface (MII) Data I/O

This pin requires an external 4.7-K pull-up resistor.

11

12

MDIO

MDC

I/O

I

Management Interface (MII) Clock Input

This pin is synchronous to the MDIO data interface.

MII mode: Receive Data Output[3] (Note 2-2)

Config mode: The pull-up/pull-down value is latched as PHY-

ADDR[0] during power-up or reset. See “Strap-In option –

KSZ8041NL” for details.

RXD3 /

PHYAD0

13

14

Ipu/O

Ipd/O

MII mode: Receive Data Output[2] (Note 2-2)

Config mode: The pull-up/pull-down value is latched as PHY-

ADDR[1] during power-up or reset. See “Strap-In option –

KSZ8041NL” for details.

RXD2 /

PHYAD1

MII mode: Receive Data Output[1] (Note 2-2)

RMII mode: Receive Data Output[1] (Note 2-3)

Config mode: The pull-up/pull-down value is latched as PHY-

ADDR[2] during power-up or reset. See “Strap-In option –

KSZ8041NL” for details.

RXD1 /

RXD[1] /

PHYAD2

15

Ipd/O

MII mode: Receive Data Output[0] (Note 2-2).

RMII mode: Receive Data Output[0] (Note 2-3).

Config mode: Latched as DUPLEX (register 0h, bit 8) during power-

up or reset. See “Strap-In option – KSZ8041NL” for details.

RXD0 /

RXD[0] /

DUPLEX

16

17

Ipu/O

P

3.3V Digital V_DD

VDDIO_3.3

MII mode: Receive Data Valid Output

RXDV /

CRSDV /

CONFIG2

RMII mode: Carrier Sense/Receive Data Valid Output

Config mode: The pull-up/pull-down value is latched as CONFIG2

during power-up or reset. See “Strap-In option – KSZ8041NL”

18

19

20

Ipd/O

O

for details.

MII mode: Receive Clock Output

RXC

MII mode: Receive Error Output

RMII mode: Receive Error Output

Config mode: The pull-up/pull-down value is latched as ISOLATE

during power-up or reset. See “Strap-In option – KSZ8041NL” for

details.

RXER /

RX_ER /

ISO

Ipd/O

 2017 Microchip Technology Inc.

DS00002245B-page 7

KSZ8041NL/RNL

TABLE 2-1:

Pin Number

KSZ8041NL PIN DESCRIPTION (CONTINUED)

Buffer Type

(Note 2-1)

Symbol

Description

Interrupt Output: Programmable Interrupt Output

Register 1Bh is the Interrupt Control/Status Register for program-

ming the interrupt conditions and reading the interrupt status. Regis-

ter 1Fh bit 9 sets the interrupt output to active low (default) or active

high.

21

INTRP

TXC

Opu

MII mode: Transmit Clock Output

22

23

O

I

MII mode: Transmit Enable Input

RMII mode: Transmit Enable Input

TXEN /

TX_EN

MII mode: Transmit Data Input[0] (Note 2-4)

RMII mode: Transmit Data Input[0] (Note 2-5)

TXD0 /

TXD[0]

24

25

I

MII mode: Transmit Data Input[1] (Note 2-4)

RMII mode: Transmit Data Input[1] (Note 2-5)

TXD1 /

TXD[1]

MII mode: Transmit Data Input[2] (Note 2-4)

MII mode: Transmit Data Input[3] (Note 2-4)

26

27

TXD2

TXD3

I

MII mode: Collision Detect Output

Config mode: The pull-up/pull-down value is latched as CONFIG0

during power-up or reset. See “Strap-In option – KSZ8041NL” for

details.

28

29

COL/CONFIG0

CRS/CONFIG1

Ipd/O

MII mode: Collision Sense Output

Config mode: The pull-up/pull-down value is latched as CONFIG1

during power-up or reset. See “Strap-In option – KSZ8041NL” for

details.

DS00002245B-page 8

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

TABLE 2-1:

Pin Number

KSZ8041NL PIN DESCRIPTION (CONTINUED)

Buffer Type

Symbol

Description

(Note 2-1)

LED Output: Programmable LED0 Output

Config ode: Latched as Auto-Negotiation Enable (register 0h, bit 12)

during power-up or reset. See Strap-In option – KSZ8041NL for

details.

The LED0 pin is programmable via register 1Eh bits [15:14] and is

defined as follows:

LED Mode = [00]

Link/Activity

No Link

Link

Pin State

LED Definition

OFF

H

L

ON

Activity

Toggle

Blinking

30

LED0 / NWAYEN

Ipu/O

LED Mode = [01]

Link/Activity

No Link

Link

Pin State

LED Definition

H

L

OFF

ON

LED Mode = [10]

Reserved

LED Mode = [11]

Reserved

 2017 Microchip Technology Inc.

DS00002245B-page 9

KSZ8041NL/RNL

TABLE 2-1:

Pin Number

KSZ8041NL PIN DESCRIPTION (CONTINUED)

Buffer Type

(Note 2-1)

Symbol

Description

LED Output: Programmable LED1 Output

Config mode: Latched as SPEED (register 0h, bit 13) during power-

up or reset. See Strap-In option – KSZ8041NL for details.

The LED1 pin is programmable via register 1Eh bits [15:14] and is

defined as follows:

LED Mode = [00]

Speed

10BT

Pin State

LED Definition

H

L

OFF

ON

100BT

31

LED1 / SPEED

Ipu/O

LED Mode = [01]

Activity

No Activity

Activity

Pin State

H

LED Definition

OFF

Toggle

Blinking

LED Mode = [10]

Reserved

LED Mode = [11]

Reserved

32

RST#

GND

I

Chip Reset (active low)

Ground

PADDLE

Gnd

Note 2-1

P = Power supply

Gnd = Ground

I = Input

O = Output

I/O = Bi-directional

Ipd = Input with internal pull-down (40K ±30%)

Ipu = Input with internal pull-up (40K ±30%)

Opu = Output with internal pull-up (40K ±30%)

Ipu/O = Input with internal pull-up (40K ±30%) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise.

Note 2-2

Note 2-3

Note 2-4

MII Rx mode: The RXD[3:0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3:0]

presents a valid data to the MAC through the MII. RXD[3:0] is invalid when RXDV is deasserted.

RMII Rx mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which

CRS_DV is asserted, two bits of recovered data are sent from the PHY.

MII Tx mode: The TXD[3:0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3:0]

presents a valid data from the MAC through the MII. TXD[3..0] has no effect when TXEN is

deasserted.

Note 2-5

RMII Tx mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which

TX_EN is asserted, two bits of data are received by the PHY from the MAC.

DS00002245B-page 10

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

2.2

STRAP-IN OPTION – KSZ8041NL

Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during

power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this

case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap in to ISO-

LATE mode, or is not configured with an incorrect PHY Address.

TABLE 2-2:

STRAP-IN OPTION – KSZ8041NL

Type

Number

Pin Name

Pin Function

(Note 2-1)

15

14

PHYAD2

PHYAD1

Ipd/O

The PHY Address is latched at power-up or reset and is configurable to any

value from 1 to 7.

The default PHY Address is 00001.

13

PHYAD0

Ipu/O

PHY Address bits [4:3] are always set to ‘00’.

18

29

CONFIG2

CONFIG1

Ipd/O

The CONFIG[2:0] strap-in pins are latched at power-up or reset and are

defined as follows:

CONFIG[2:0]

000

Mode

MII (default)

001

RMII

010

Reserved - not used

MII 100 Mbps Preamble Restore

Reserved - not used

011

28

CONFIG0

Ipd/O

100

101

110

111

ISOLATE mode:

Pull-up = Enable

Pull-down (default) = Disable

During power-up or reset, this pin value is latched into register 0h bit 10.

20

31

ISO

Ipd/O

Ipu/O

SPEED mode:

Pull-up (default) = 100 Mbps

Pull-down = 10 Mbps

During power-up or reset, this pin value is latched into register 0h bit 13 as

the Speed Select, and also is latched into register 4h (Auto-Negotiation

Advertisement) as the Speed capability support.

SPEED

DUPLEX mode:

Pull-up (default) = Half Duplex

16

DUPLEX

NWAYEN

Ipu/O

Pull-down = Full Duplex

During power-up or reset, this pin value is latched into register 0h bit 8 as

the Duplex mode.

Nway Auto-Negotiation Enable:

Pull-up (default) = Enable Auto-Negotiation

Pull-down = Disable Auto-Negotiation

30

During power-up or reset, this pin value is latched into register 0h bit 12.

Note 2-1

Ipu/O = Input with internal pull-up (40K ±30%) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise.

 2017 Microchip Technology Inc.

DS00002245B-page 11

KSZ8041NL/RNL

2.3

KSZ8041RNL Pin Description and Configuration

FIGURE 2-2:

KSZ8041RNL 32-QFN PIN ASSIGNMENT (TOP VIEW)

32

31

30

29

28

27

26

25

GND

1

2

3

4

5

6

7

8

24 TXD0

23 TX_EN

22 NC

VDDPLL_1.8

VDDA_3.3

RX-

Paddle

21 INTRP

Ground

RX_ER /

ISO

RX+

20

(on bottom of chip)

TX-

19 REF_CLK

CRS_DV /

18

TX+

CONFIG2

XO

17 VDDIO_3.3

9

10

11

12

13

14

15

16

TABLE 2-3:

Pin Number

1

KSZ8041RNL PIN DESCRIPTION

Pin Name

Type (Note 2-1)

Pin Function

GND

Gnd

Ground

1.8V Analog V_DD

Decouple with 1.0-µF and 0.1-µF capacitors to ground.

2

VDDPLL_1.8

P

3

4

5

6

7

VDDA_3.3

RX-

P

3.3V Analog V_DD

I/O

Physical receive or transmit signal (- differential)

Physical receive or transmit signal (+ differential)

Physical transmit or receive signal (- differential)

Physical transmit or receive signal (+ differential)

RX+

TX-

TX+

Crystal Feedback for 25-MHz Crystal

This pin is a no connect if an oscillator or an external clock

source is used.

8

9

XO

XI

O

I

Crystal/Oscillator/External Clock Input

25 MHz ±50 ppm

Set physical transmit output current.

Connect a 6.49-k resistor in parallel with a 100-pF capaci-

tor to ground on this pin. See KSZ8041RNL reference

schematics.

10

REXT

I/O

DS00002245B-page 12

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

TABLE 2-3:

Pin Number

KSZ8041RNL PIN DESCRIPTION (CONTINUED)

Pin Name

Type (Note 2-1)

Pin Function

Management Interface (MII) Data I/O

This pin requires an external 4.7-k pull-up resistor.

11

12

MDIO

I/O

Management Interface (MII) Clock Input

This pin is synchronous to the MDIO data interface.

MDC

I

The pull-up/pull-down value is latched as PHYADDR[0]

during power-up or reset. See Strap-In option –

KSZ8041RNL for details.

13

14

PHYAD0

Ipu/O

The pull-up/pull-down value is latched as PHYADDR[1]

during power-up or reset. See Strap-In option –

KSZ8041RNL for details.

PHYAD1

Ipd/O

RMII mode: RMII Receive Data Output[1] (Note 2-2)

Config mode: The pull-up/pull-down value is latched as

PHYADDR[2] during power-up or reset. See Strap-In option

– KSZ8041RNL for details.

RXD1 /

PHYAD2

15

RMII mode: RMII Receive Data Output[0]] (Note 2-2)

Config mode: Latched as DUPLEX (register 0h, bit 8) during

power-up or reset. See Strap-In option – KSZ8041RNL for

details.

RXD0 /

DUPLEX

16

17

18

Ipu/O

P

VDDIO_3.3

3.3V Digital V_DD

RMII mode: Carrier Sense/Receive Data Valid Output

Config mode: The pull-up/pull-down value is latched as

CONFIG2 during power-up or reset. See Strap-In option –

KSZ8041RNL for details.

CRSDV /

CONFIG2

Ipd/O

50 MHz Clock Output

19

20

REF_CLK

O

This pin provides the 50-MHz RMII reference clock output to

the MAC.

RMII mode: Receive Error Output.

RXER /

RX_ER /

ISO

Config mode: The pull-up/pull-down value is latched as ISO-

LATE during power-up or reset. See Strap-In option –

KSZ8041RNL for details.

Ipd/O

Interrupt Output: Programmable Interrupt Output

Register 1Bh is the Interrupt Control/Status Register for pro-

gramming the interrupt conditions and reading the interrupt

status. Register 1Fh bit 9 sets the interrupt output to active

low (default) or active high.

21

INTRP

Opu

No Connect

22

23

24

25

26

27

NC

TX_EN

TXD0

TXD1

NC

O

I

RMII Transmit Enable Input

RMII Transmit Data Input[0] (Note 2-3)

RMII Transmit Data Input[1] (Note 2-3)

No Connect

I

No Connect

NC

I

The pull-up/pull-down value is latched as CONFIG0 during

power-up or reset. See Strap-In option – KSZ8041RNL for

details.

28

29

CONFIG0

CONFIG1

Ipd/O

The pull-up/pull-down value is latched as CONFIG1 during

power-up or reset. See Strap-In option – KSZ8041RNL for

details.

 2017 Microchip Technology Inc.

DS00002245B-page 13

KSZ8041NL/RNL

TABLE 2-3:

Pin Number

KSZ8041RNL PIN DESCRIPTION (CONTINUED)

Pin Name

Type (Note 2-1)

Pin Function

LED Output: Programmable LED0 Output

Config mode: Latched as Auto-Negotiation Enable (register

0h, bit 12) during power-up or reset. See Strap-In option –

KSZ8041RNL for details.

The LED0 pin is programmable via register 1Eh bits [15:14]

and is defined as follows:

LED Mode = [00]

Link/Activity

No Link

Link

Pin State

LED Definition

OFF

H

L

ON

LED0 /

NWAYEN

30

Ipu/O

Activity

Toggle

Blinking

LED Mode = [01]

Link

Pin State

LED Definition

No Link

Link

H

L

OFF

ON

LED Mode = [10], [11]

Reserved

LED Output: Programmable LED1 Output

Config mode: Latched as SPEED (register 0h, bit 13) during

power-up or reset. See Strap-In option – KSZ8041RNL for

details.

The LED1 pin is programmable via register 1Eh bits [15:14]

and is defined as follows:

LED Mode = [00]

Speed

10BT

Pin State

LED Definition

H

L

OFF

ON

LED1 /

SPEED

100BT

31

Ipu/O

LED Mode = [01]

Activity

No Activity

Activity

Pin State

H

LED Definition

OFF

Toggle

Blinking

LED Mode = [10], [11]

Reserved

32

RST#

GND

I

Chip Reset (active low)

Ground

PADDLE

Gnd

DS00002245B-page 14

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

Note 2-1

P = Power supply

Gnd = Ground

I = Input

O = Output

I/O = Bi-directional

Opu = Output with internal pull-up (40K ±30%)

Ipu/O = Input with internal pull-up (40K ±30%) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise.

Note 2-2

Note 2-3

RMII Rx mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which

CRS_DV is asserted, two bits of recovered data are sent from the PHY.

RMII Tx mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which

TX_EN is asserted, two bits of data are received by the PHY from the MAC.

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KSZ8041NL/RNL

2.4

STRAP-IN OPTION – KSZ8041RNL

Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during

power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched high. In this case,

it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap in to ISOLATE

mode, or is not configured with an incorrect PHY Address.

TABLE 2-4:

STRAP-IN OPTION – KSZ8041RNL

Type

Number

Pin Name

Pin Function

(Note 2-1)

15

14

PHYAD2

PHYAD1

Ipd/O

The PHY Address is latched at power-up or reset and is configurable to any

value from 1 to 7.

The default PHY Address is 00001.

13

PHYAD0

Ipu/O

PHY Address bits [4:3] are always set to ‘00’.

18

29

CONFIG2

CONFIG1

Ipd/O

The CONFIG[2:0] strap-in pins are latched at power-up or reset and are

defined as follows:

CONFIG[2:0]

000

Mode

Reserved - not used

RMII

001

010

Reserved - not used

011

28

CONFIG0

Ipd/O

100

101

110

111

ISOLATE mode:

Pull-up = Enable

Pull-down (default) = Disable

During power-up or reset, this pin value is latched into register 0h bit 10.

20

31

ISO

Ipd/O

Ipu/O

SPEED mode:

Pull-up (default) = 100 Mbps

Pull-down = 10 Mbps

During power-up or reset, this pin value is latched into register 0h bit 13 as

the Speed Select, and also is latched into register 4h (Auto-Negotiation

Advertisement) as the Speed capability support.

SPEED

DUPLEX mode:

Pull-up (default) = Half Duplex

16

DUPLEX

NWAYEN

Ipu/O

Pull-down = Full Duplex

During power-up or reset, this pin value is latched into register 0h bit 8 as

the Duplex mode.

Nway Auto-Negotiation Enable:

Pull-up (default) = Enable Auto-Negotiation

Pull-down = Disable Auto-Negotiation

30

During power-up or reset, this pin value is latched into register 0h bit 12.

Note 2-1

Ipu/O = Input with internal pull-up (40K ±30%) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise.

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KSZ8041NL/RNL

3.0

FUNCTIONAL DESCRIPTION

The KSZ8041NL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u

specification.

On the media side, the KSZ8041NL supports 10BASE-T and 100BASE-TX with HP auto MDI/MDI-X for reliable detec-

tion of and correction for straight-through and crossover cables.

The KSZ8041NL offers a choice of MII or RMII data interface connection with the MAC processor. The MII management

bus option gives the MAC processor complete access to the KSZ8041NL control and status registers. Additionally, an

interrupt pin eliminates the need for the processor to poll for PHY status change.

Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the

design more efficient and allow for lower power consumption and smaller chip die size.

The KSZ8041RNL is an enhanced RMII version of the KSZ8041NL that does not require a 50-MHz system clock. It uses

a 25-MHz crystal for its input reference clock and outputs a 50-MHz RMII reference clock to the MAC.

3.1

100BASE-TX Transmit

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI con-

version, and MLT3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125-MHz serial

bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized

data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output.

The output current is set by an external 6.49-kΩ 1% resistor for the 1:1 transformer ratio. It has typical rise or fall times

of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The

wave-shaped 10BASE-T output drivers are also incorporated into the 100BASE-TX drivers.

3.2

100BASE-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted

pair cable. Because the amplitude loss and phase distortion are functions of the cable length, the equalizer must adjust

its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on

comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimiza-

tion. This is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used

to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion

circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125-MHz clock from the edges of the NRZI signal. This recovered clock is then

used to convert the NRZI signal into the NRZ format. This signal is sent through the descrambler followed by the 4B/5B

decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.

3.3

PLL Clock Synthesizer

The KSZ8041NL/RNL generates 125-MHz, 25-MHz, and 20-MHz clocks for system timing. Internal clocks are gener-

ated from an external 25-MHz crystal or oscillator. For the KSZ8041NL in RMII mode, these internal clocks are gener-

ated from an external 50-MHz oscillator or system clock.

3.4

Scrambler/Descrambler (100BASE-TX only)

The purpose of the scrambler is to spread the power spectrum of the signal to reduce EMI and baseline wander.

3.5

10BASE-T Transmit

The 10BASE-T drivers are incorporated with the 100BASE-TX drivers to allow for transmission using the same mag-

netic. The drivers also perform internal wave-shaping and pre-emphasize, and output 10BASE-T signals with a typical

amplitude of 2.5V peak. The 10BASE-T signals have harmonic contents that are at least 27 dB below the fundamental

frequency when driven by an all-ones Manchester-encoded signal.

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KSZ8041NL/RNL

3.6

10BASE-T Receive

On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit

and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and

NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at

the RX+ and RX- inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks

onto the incoming signal and the KSZ8041NL/RNL decodes a data frame. The receive clock is kept active during idle

periods in between data reception.

3.7

SQE and Jabber Function (10BASE-T only)

In 10BASE-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required

as a test of the 10BASE-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the

10BASE-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the

10BASE-T transmitter is re-enabled and COL is deasserted (returns to low).

3.8

Auto-Negotiation

The KSZ8041NL/RNL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification.

Auto-negotiation is enabled by either hardware pin strapping (pin 30) or software (register 0h bit 12).

Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.

Link partners advertise their capabilities to each other, and then compare their own capabilities with those they received

from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the

mode of operation.

The following list shows the speed and duplex operation mode from highest to lowest:

• Priority 1: 100BASE-TX, full-duplex

• Priority 2: 100BASE-TX, half-duplex

• Priority 3: 10BASE-T, full-duplex

• Priority 4: 10BASE-T, half-duplex

If auto-negotiation is not supported or the KSZ8041NL/RNL link partner is forced to bypass auto-negotiation, the

KSZ8041NL/RNL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and

this allows the KSZ8041NL/RNL to establish a link by listening for a fixed signal protocol in the absence of auto-nego-

tiation advertisement protocol.

The auto-negotiation link-up process is shown in the flow chart illustrated as Figure 3-1.

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KSZ8041NL/RNL

FIGURE 3-1:

AUTO-NEGOTIATION FLOW CHART

Start Auto Negotiation

N

o

Parallel

Force Link Setting

Yes

Operation

Listen for 10BASE-T

Bypass Auto Negotiation

and Set Link Mode

Attempt Auto

Negotiation

Listen for 100BASE-TX

Idles

Link Pulses

No

Join

Flow

Link Mode Set ?

Yes

Link Mode Set

3.9

MII Management (MIIM) Interface

The KSZ8041NL/RNL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input

or Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the

KSZ8041NL/RNL. An external device with MIIM capability is used to read the PHY status or to configure the PHY set-

tings or both. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 specification.

The MIIM interface consists of the following:

• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).

• A specific protocol that operates across the aforementioned physical connection that allows an external controller

to communicate with one or more PHY devices. Each KSZ8041NL/RNL device is assigned a unique PHY address

between 1 and 7 by its PHYAD[2:0] strapping pins. Additionally, every KSZ8041NL/RNL device supports the

broadcast PHY address 0, as defined per the IEEE 802.3 specification, which can be used to read or write to a

single KSZ8041NL/RNL device, or write to multiple KSZ8041NL/RNL devices simultaneously.

• A set of 16-bit MDIO registers. Registers [0:6] are required, and their functions are defined per the IEEE 802.3

specification. The additional registers are provided for expanded functionality.

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KSZ8041NL/RNL

Table 3-1 shows the MII Management frame format for the KSZ8041NL/RNL.

TABLE 3-1:

MII MANAGEMENT FRAME FORMAT

Read/

Write

OP

PHY

REG

Start of

Frame

Address Address

Bits

Preamble

TA

Data Bits [15:0]

Idle

Bits

[4:0]

Code

Read

Write

32 1’s

01

10

01

00AAA RRRRR

Z0

10

DDDDDDDD_DDDDDDDD

Z

3.10 Interrupt (INTRP)

INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status

update to the KSZ8041NL/RNL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits and are used to

enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits,

and are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading

register 1Bh.

Bit 9 of register 1Fh sets the interrupt level to active high or active low.

3.11 MII Data Interface (KSZ8041NL only)

The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3 specification. It provides a common

interface between physical layer and MAC layer devices, and has the following key characteristics:

• Supports 10 Mbps and 100 Mbps data rates

• Uses a 25-MHz reference clock, sourced by the PHY

• Provides independent 4-bit wide (nibble) transmit and receive data paths

• Contains two distinct groups of signals: one for transmission and the other for reception

By default, the KSZ8041NL is configured to MII mode after it is powered up or reset with the following:

• A 25-MHz crystal connected to XI, XO (pins 9, 8), or an external 25-MHz clock source (oscillator) connected to XI

• CONFIG[2:0] (pins 18, 29, 28) set to ‘000’ (default setting)

3.12 MII Signal Definition (KSZ8041NL only)

Table 3-2 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 specification for detailed information.

TABLE 3-2:

MII SIGNAL DEFINITION

Direction (with

respect to PHY,

KSZ8041NL signal)

MII Signal

Name

Direction

(with respect to MAC)

Description

Transmit Clock

(2.5 MHz for 10 Mbps, 25 MHz for 100 Mbps)

TXC

Output

Input

TXEN

Input

Output

Transmit Enable

TXD[3:0]

Transmit Data [3:0]

Receive Clock

(2.5 MHz for 10 Mbps, 25 MHz for 100 Mbps)

RXC

Output

Input

RXDV

RXD[3:0]

RXER

CRS

Output

Input

Receive Data Valid

Receive Data [3:0]

Input, or (not required) Receive Error

Input

Carrier Sense

COL

Collision Detection

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KSZ8041NL/RNL

3.12.1

TRANSMIT CLOCK (TXC)

TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for Transmit Enable (TXEN) and

Transmit Data [3:0] (TXD[3:0]).

TXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.

3.12.2

TRANSMIT ENABLE (TXEN)

TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first

nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated

prior to the first TXC following the final nibble of a frame.

TXEN transitions synchronously with respect to TXC.

3.12.3

TRANSMIT DATA [3:0] (TXD[3:0])

TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmis-

sion by the PHY. TXD[3:0] is “00” to indicate idle when TXEN is deasserted. Values other than “00” on TXD[3:0] while

TXEN is deasserted are ignored by the PHY.

3.12.4

RECEIVE CLOCK (RXC)

RXC provides the timing reference for RXDV, RXD[3:0], and RXER.

• In 10 Mbps mode, RXC is recovered from the line while the carrier is active. RXC is derived from the PHY’s refer-

ence clock when the line is idle or the link is down.

• In 100 Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the

PHY’s reference clock.

RXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.

3.12.5

RECEIVE DATA VALID (RXDV)

RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].

• In 10 Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains

asserted until the end of the frame.

• In 100 Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.

RXDV transitions synchronously with respect to RXC.

3.12.6

RECEIVE DATA [3:0] (RXD[3:0])

RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]

transfers a nibble of recovered data from the PHY.

3.12.7

RECEIVE ERROR (RXER)

RXER is asserted for one or more RXC periods to indicate that a Symbol Error (for example, a coding error that a PHY

is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the

frame presently being transferred from the PHY.

RXER transitions synchronously with respect to RXC. While RXDV is deasserted, RXER has no effect on the MAC.

3.12.8

CARRIER SENSE (CRS)

CRS is asserted and deasserted as follows:

• In 10 Mbps mode, CRS assertion is based on the reception of valid preambles. CRS deassertion is based on the

reception of an end-of-frame (EOF) marker.

• In 100 Mbps mode, CRS is asserted when a start-of-stream delimiter, or /J/K symbol pair is detected. CRS is

deasserted when an end-of-stream delimiter, or /T/R symbol pair is detected. Additionally, the PMA layer

deasserts CRS if IDLE symbols are received without /T/R.

3.12.9

COLLISION (COL)

COL is asserted in half-duplex mode whenever the transmitter and the receiver are simultaneously active on the line.

This is used to inform the MAC that a collision has occurred during its transmission to the PHY.

COL transitions asynchronously with respect to TXC and RXC.

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KSZ8041NL/RNL

3.13 Reduced MII (RMII) Data Interface

The Reduced Media Independent Interface (RMII) specifies a low pin count MII. It provides a common interface between

physical layer and MAC layer devices, and has the following key characteristics:

• Supports 10 Mbps and 100 Mbps data rates

• Uses a 50-MHz reference clock

• Provides independent 2-bit wide (di-bit) transmit and receive data paths

• Contains two distinct groups of signals: one for transmission and the other for reception

The KSZ8041NL is configured in RMII mode after it is powered up or reset with the following:

• A 500MHz reference clock connected to REFCLK (pin 9)

• CONFIG[2:0] (pins 18, 29, 28) set to ‘001’

The KSZ8041RNL is configured in RMII mode and outputs the 50-MHz RMII reference clock to the MAC on REF_CLK

(pin 19) after it is powered up or reset with the following:

• A 25-MHz crystal connected to XI (pin 9) and XO (pin 8), or a 25-MHz reference clock connected to XI (pin 9)

• CONFIG[2:0] (pins 18, 29, 28) set to ‘001’

In RMII mode, unused MII signals, TXD[3:2] (pins 27, 26), are tied to ground.

3.14 RMII Signal Definition

Table 3-3 and Table 3-4 describe the RMII signals for KSZ8041NL and KSZ8041RNL. Refer to RMII specification for

detailed information.

TABLE 3-3:

RMII SIGNAL DESCRIPTION – KSZ8041NL

Direction (with

RMII Signal

Name

respect to PHY,

respect to MAC)

KSZ8041NL signal)

Description

Synchronous 50-MHz clock reference for receive,

transmit, and control interface

REF_CLK

Input

Input or Output

TX_EN

TXD[1:0]

CRS_DV

RXD[1:0]

Input

Output

Input

Transmit Enable

Transmit Data [1:0]

Output

Carrier Sense/Receive Data Valid

Receive Data [1:0]

Input

Input, or (not

required)

RX_ER

Output

Receive Error

TABLE 3-4:

RMII SIGNAL DESCRIPTION – KSZ8041RNL

Direction (with

RMII Signal

Name

respect to PHY,

KSZ8041RNL

signal)

Direction (with

respect to MAC)

Description

Synchronous 50-MHz clock reference for receive,

transmit, and control interface

REF_CLK

Output

Input

TX_EN

TXD[1:0]

CRS_DV

RXD[1:0]

Input

Output

Input

Transmit Enable

Transmit Data [1:0]

Output

Carrier Sense/Receive Data Valid

Receive Data [1:0]

Input

Input, or (not

required)

RX_ER

Output

Receive Error

3.14.1

REFERENCE CLOCK (REF_CLK)

REF_CLK is a continuous 50-MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0],

and RX_ER.

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KSZ8041NL/RNL

The KSZ8041NL inputs the 50-MHz REF_CLK from the MAC or system board.

The KSZ8041RNL generates the 50MHz RMII REF_CLK and outputs it to the MAC.

3.14.2

TRANSMIT ENABLE (TX_EN)

TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the

first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is

negated prior to the first REF_CLK following the final di-bit of a frame.

TX_EN transitions synchronously with respect to REF_CLK.

3.14.3

TRANSMIT DATA [1:0] (TXD[1:0])

TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] is accepted for trans-

mission by the PHY. TXD[1:0] is “00” to indicate idle when TX_EN is deasserted. Values other than “00” on TXD[1:0]

while TX_EN is deasserted are ignored by the PHY.

3.14.4

CARRIER SENSE/RECEIVE DATA VALID (CRS_DV)

CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of a

carrier. This is when a squelch is passed in 10 Mbps mode, and when two non-contiguous zeros in 10 bits are detected

in 100 Mbps mode. Loss of carrier results in the deassertion of CRS_DV.

As long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of

the frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The

data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchro-

nous relative to REF_CLK, the data on RXD[1:0] is “00” until proper receive signal decoding takes place.

3.14.5

RECEIVE DATA [1:0] (RXD[1:0])

RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] trans-

fers two bits of recovered data from the PHY. RXD[1:0] is “00” to indicate idle when CRS_DV is deasserted. Values other

than “00” on RXD[1:0] while CRS_DV is deasserted are ignored by the MAC.

3.14.6

RECEIVE ERROR (RX_ER)

RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (for example,. a coding error that

a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere

in the frame presently being transferred from the PHY.

RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is deasserted, RX_ER has no effect on the

MAC.

3.14.7

COLLISION DETECTION

The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.

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KSZ8041NL/RNL

3.15 RMII Signal Diagram

The KSZ8041NL RMII pin connections to the MAC are shown in Figure 3-2.

FIGURE 3-2:

KSZ8041NL RMII INTERFACE

KSZ8041NL

RMII MAC

CRS_DV

RXD[1:0]

CRS_DV

RXD[1:0]

RX_ER

TX_EN

TXD[1:0]

REF_CLK

REFCLK

50 MHz

OSC

FIGURE 3-3:

KSZ8041RNL RMII INTERFACE

KSZ8041RNL

RMII MAC

CRS_DV

RXD[1:0]

CRS_DV

RXD[1:0]

RX_ER

TX_EN

TXD[1:0]

REF_CLK

XO

XI

25 MHz

XTAL

22 pF

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KSZ8041NL/RNL

3.16 HP Auto MDI/MDI-X

HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable

between the KSZ8041NL/RNL and its link partner. This feature allows the KSZ8041NL/RNL to use either type of cable

to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive

pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041NL/RNL accordingly.

HP Auto MDI/MDI-X is enabled by default. Writing “1” to register 1F bit 13 disables HP Auto MDI/MDL-X. Register 1F

bit 14 selects MDI and MDI-X mode if HP Auto MDI/MDI-X is disabled.

An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.

The IEEE 802.3 Standard MDI and MDI-X is defined in Table 3-5.

TABLE 3-5:

MDI/MDI-X PIN DESCRIPTION

MDI

MDI-X

RJ-45 Pin

Signal

RJ-45 Pin

Signal

1

2

3

6

TD+

TD–

RD+

RD–

1

2

3

6

RD+

RD–

TD+

TD–

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KSZ8041NL/RNL

3.16.1

STRAIGHT CABLE

A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-4 depicts

a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).

FIGURE 3-4:

TYPICAL STRAIGHT CABLE CONNECTION

3.16.2

CROSSOVER CABLE

A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.

Table 3-4 depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices).

FIGURE 3-5:

TYPICAL CROSSOVER CABLE CONNECTION

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KSZ8041NL/RNL

3.17 Power Management

The KSZ8041NL/RNL offers the following two power management modes:

• Power Saving Mode

This mode is used to reduce power consumption when the cable is unplugged. It is in effect when the auto-negoti-

ation mode is enabled, the cable is disconnected, and register 1F bit 10 is set to 1. Under the power saving mode,

the KSZ8041NL/RNL shuts down all transceiver blocks, except for transmitter, energy detect, and PLL circuits.

Additionally, for the KSZ8041NL in MII mode, the RXC clock output is disabled. RXC clock is enabled after the

cable is connected and a link is established.

Power-saving mode is disabled by writing “0” to register 1F bit 10.

• Power-Down Mode

This mode is used to power down the entire KSZ8041NL/RNL device when it is not in use. Power down mode is

enabled by writing “1” to register 0 bit 11. In the power down state, the KSZ8041NL/RNL disables all internal func-

tions, except for the MII management interface.

3.18 Reference Clock Connection Options

A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041NL/RNL.

Figure 3-6 illustrates how to connect the 25-MHz crystal and oscillator reference clock.

FIGURE 3-6:

25-MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK

22pF

pF

XI

25MHz OSC

+/-50ppm

22pF

NC

XO

NC

25MHz XTAL

+/-50ppm

For the KSZ8041NL, Figure 3-7 illustrates how to connect the 50-MHz oscillator reference clock for RMII mode.

FIGURE 3-7:

50-MHZ OSCILLATOR REFERENCE CLOCK FOR KSZ8041NL RMII MODE

REFCLK

50MHz OSC

+/-50ppm

NC

XO

NC

3.19 Reference Circuit for Power and Ground Connections

The KSZ8041NL/RNL is a single 3.3V supply device with a built-in 1.8V low-noise regulator. The power and ground con-

nections are shown in Figure 3-8 and Table 3-6.

 2017 Microchip Technology Inc.

DS00002245B-page 27

KSZ8041NL/RNL

FIGURE 3-8:

KSZ8041NL/RNL POWER AND GROUND CONNECTIONS

Ferrite

Bead

`

2

1.0uF

0.1uF

V_IN

V_OUT

3

1.8V Low Noise

Regulator

(integrated)

`

VDDA_3.3

22uF

0.1uF

17

3.3V

VDDIO_3.3

`

22uF

0.1uF

GND

KSZ8041NL/RNL

1

Paddle

TABLE 3-6:

Power Pin

KSZ8041NL/RNL POWER PIN DESCRIPTION

Pin Number

Description

VDDPLL_1.8

VDDA_3.3

2

3

Decouple with 1.0 µF and 0.1 µF capacitors to ground.

Connect to the board’s 3.3V supply through ferrite bead.

Connect to the board’s 3.3V supply.

VDDIO_3.3

17

DS00002245B-page 28

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

4.0

4.1

REGISTERS

Register Map

Table 4-1 summarizes the register map.

TABLE 4-1:

Register Number (Hex)

0h

REGISTER MAP

Description

Basic Control

1h

Basic Status

2h

PHY Identifier 1

3h

PHY Identifier 2

4h

Auto-Negotiation Advertisement

Auto-Negotiation Link Partner Ability

Auto-Negotiation Expansion

Auto-Negotiation Next Page

Link Partner Next Page Ability

Reserved

5h

6h

7h

8h

9h – 13h

14h

MII Control

15h

RXER Counter

16h – 1Ah

1Bh

1Ch – 1Dh

1Eh

1Fh

Reserved

Interrupt Control/Status

Reserved

PHY Control 1

PHY Control 2

 2017 Microchip Technology Inc.

DS00002245B-page 29

KSZ8041NL/RNL

4.2

Register Descriptions

Table 4-2 provides a list of supported registers and their descriptions.

TABLE 4-2:

Address

REGISTER DESCRIPTIONS

Name

Mode

(Note 4-1)

Description

Default

Register 0h – Basic Control

1 = Software reset

0 = Normal operation

This bit is self-cleared after a ‘1’

is written to it.

0.15

0.14

Reset

RW/SC

RW

0

1 = Loop-back mode

0 = Normal operation

Loop-Back

1 = 100 Mbps

0 = 10 Mbps

This bit is ignored if auto-negotia-

tion is enabled (register 0.12 =

1).

Set by SPEED strapping

pin.

See Table 2-2 and

Table 2-4 for details.

0.13

0.12

Speed Select (LSB)

RW

1 = Enable auto-negotiation

process

0 = Disable auto-negotiation

process

If enabled, auto-negotiation

result overrides the settings in

register 0.13 and 0.8.

Set by NWAYEN strap-

ping pin.

See Table 2-2 and

Table 2-4 for details.

Auto-Negotiation Enable

1 = Power-down mode

0 = Normal operation

0.11

0.10

Power Down

Isolate

RW

0

1 = Electrical isolation of PHY

from MII and TX+/TX-

Set by ISO strapping pin.

See Table 2-2 and

0 = Normal operation

Table 2-4 for details.

1 = Restart auto-negotiation

process

0.9

0.8

Restart Auto-Negotiation

Duplex Mode

0 = Normal operation

This bit is self-cleared after a ‘1’

is written to it.

RW/SC

RW

0

Inverse of DUPLEX

strapping pin value.

See Table 2-2 and

Table 2-4 for details.

1 = Full-duplex

0 = Half-duplex

1 = Enable COL test

0 = Disable COL test

0.7

0.6:1

0.0

Collision Test

Reserved

RW

RO

RW

0

000_000

0

Disable

Transmitter

0 = Enable transmitter

1 = Disable transmitter

Register 1h – Basic Status

1 = T4 capable

0 = Not T4 capable

1.15

100BASE-T4

RO

0

1

1 = Capable of 100 Mbps full-

duplex

0 = Not capable of 100 Mbps full-

duplex

1.14

100BASE-TX Full Duplex

DS00002245B-page 30

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

TABLE 4-2:

Address

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Default

Name

Description

(Note 4-1)

1 = Capable of 100 Mbps half-

duplex

0 = Not capable of 100 Mbps

half-duplex

1.13

1.12

1.11

100BASE-TX Half Duplex

RO

1

1 = Capable of 10 Mbps full-

duplex

0 = Not capable of 10 Mbps full-

duplex

10BASE-T Full Duplex

10BASE-T Half Duplex

1 = Capable of 10 Mbps half-

duplex

0 = Not capable of 10 Mbps half-

duplex

1.10:7

1.6

Reserved

—

RO

0000

1

1 = Preamble suppression

0 = Normal preamble

No Preamble

1 = Auto-negotiation process

completed

0 = Auto-negotiation process not

completed

1.5

1.4

1.3

Auto-Negotiation Complete

Remote Fault

RO

RO/LH

RO

0

1

1 = Remote fault

0 = No remote fault

1 = Capable to perform auto-

negotiation

0 = Not capable to perform auto-

negotiation

Auto-Negotiation Ability

1 = Link is up

0 = Link is down

1.2

1.1

1.0

Link Status

RO/LL

RO/LH

RO

0

1

1 = Jabber detected

0 = Jabber not detected (default

is low)

Jabber Detect

1 = Supports extended capabili-

ties registers

Extended Capability

Register 2h – PHY Identifier 1

Assigned to the 3rd through 18th

bits of the Organizationally

Unique Identifier (OUI). Kendin

Communication’s OUI is 0010A1

(hex)

2.15.0

PHY ID Number

RO

0022h

Register 3h – PHY Identifier 2

Assigned to the 19th through

24th bits of the Organizationally

Unique Identifier (OUI). Kendin

Communication’s OUI is 0010A1

(hex)

3.15:10

PHY ID Number

0001_01

Six bit manufacturer’s model

number

3.9:4

3.3:0

Model Number

RO

01_0001

Four bit manufacturer’s

revision number

Revision Number

Indicates silicon revision

 2017 Microchip Technology Inc.

DS00002245B-page 31

KSZ8041NL/RNL

TABLE 4-2:

Address

REGISTER DESCRIPTIONS (CONTINUED)

Name Description

Mode

(Note 4-1)

Default

Register 4h – Auto-Negotiation Advertisement

1 = Next page capable

0 = No next page capability

4.15

4.14

4.13

4.12

RW

RO

RW

RO

0

—

1 = Remote fault supported

0 = No remote fault

Remote Fault

Reserved

—

[00] = No PAUSE

[10] = Asymmetric PAUSE

[01] = Symmetric PAUSE

[11] = Asymmetric & Symmetric

PAUSE

4.11:10

Pause

RW

00

1 = T4 capable

0 = No T4 capability

4.9

4.8

100BASE-T4

RO

RW

0

Set by SPEED strapping

pin.

See Table 2-2 and

Table 2-4 for details.

1 = 100 Mbps full-duplex capable

0 = No 100 Mbps full-duplex

capability

100BASE-TX Full-Duplex

1 = 100 Mbps half-duplex capa-

ble

0 = No 100 Mbps half-duplex

capability

Set by SPEED strapping

pin.

See Table 2-2 and

Table 2-4 for details.

4.7

4.6

100BASE-TX Half-Duplex

10BASE-T Full-Duplex

RW

1 = 10 Mbps full-duplex capable

0 = No 10 Mbps full-duplex capa-

bility

1

1 = 10 Mbps half-duplex

capable

0 = No 10 Mbps half-duplex

capability

4.5

10BASE-T Half-Duplex

Selector Field

RW

1

4.4:0

[00001] = IEEE 802.3

0_0001

Register 5h – Auto-Negotiation Link Partner Ability

1 = Next page capable

0 = No next page capability

5.15

5.14

RO

0

1 = Link code word received from

partner

0 = Link code word not yet

received

Acknowledge

1 = Remote fault detected

0 = No remote fault

5.13

5.12

Remote Fault

Reserved

RO

0

—

[00] = No PAUSE

[10] = Asymmetric PAUSE

[01] = Symmetric PAUSE

[11] = Asymmetric &

Symmetric PAUSE

5.11:10

Pause

RO

00

1 = T4 capable

0 = No T4 capability

5.9

5.8

100BASE-T4

RO

0

1 = 100 Mbps full-duplex capable

0 = No 100 Mbps full-duplex

capability

100BASE-TX Full-Duplex

DS00002245B-page 32

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

TABLE 4-2:

Address

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Default

Name

Description

(Note 4-1)

1 = 100 Mbps half-duplex

capable

0 = No 100 Mbps half-duplex

capability

5.7

5.6

100BASE-TX Half-Duplex

RO

0

1 = 10 Mbps full-duplex

capable

0 = No 10 Mbps full-duplex

capability

10BASE-T Full-Duplex

1 = 10 Mbps half-duplex

capable

0 = No 10 Mbps half-duplex

capability

5.5

10BASE-T Half-Duplex

Selector Field

RO

0

0_0001

5.4:0

[00001] = IEEE 802.3

Register 6h – Auto-Negotiation Expansion

6.15:5

Reserved

—

RO

0000_0000_000

0

1 = Fault detected by parallel

detection

0 = No fault detected by parallel

detection.

6.4

Parallel Detection Fault

RO/LH

1 = Link partner has next page

capability

0 = Link partner does not have

next page capability

6.3

Link Partner Next Page Able

RO

0

1 = Local device has next page

capability

0 = Local device does not have

next page capability

6.2

6.1

6.0

Next Page Able

Page Received

RO

RO/LH

RO

1

0

1 = New page received

0 = New page not received yet

1 = Link partner has auto-

negotiation capability

0 = Link partner does not have

auto-negotiation capability

Link Partner Auto-Negotia-

tion Able

Register 7h – Auto-Negotiation Next Page

1 = Additional next page(s) will

follow

7.15

0

0 = Last page

7.14

7.13

7.12

Reserved

—

RO

RW

0

1

0

1 = Message page

0 = Unformatted page

Message Page

Acknowledge2

1 = Will comply with message

0 = Cannot comply with message

1 = Previous value of the trans-

mitted link code word equaled

logic one

7.11

Toggle

RO

RW

0

0 = Logic zero

11-bit wide field to encode 2048

messages

7.10:0

Message Field

000_0000_0001

 2017 Microchip Technology Inc.

DS00002245B-page 33

KSZ8041NL/RNL

TABLE 4-2:

Address

REGISTER DESCRIPTIONS (CONTINUED)

Name Description

Mode

(Note 4-1)

Default

Register 8h – Link Partner Next Page Ability

1 = Additional Next Page(s) will

follow

0 = Last page

8.15

RO

0

1 = Successful receipt of link

word

0 = No successful receipt of link

word

8.14

Acknowledge

1 = Message page

0 = Unformatted page

8.13

8.12

Message Page

Acknowledge2

RO

0

1 = Able to act on the information

0 = Not able to act on the

information

1 = Previous value of transmitted

link code word equal to logic zero

0 = Previous value of transmitted

link code word equal to logic one

8.11

Toggle

RO

0

8.10:0

Message Field

—

RO

000_0000_0000

0000_0000

Register 14h – MII Control

14.15:8

Reserved

—

1 = Restore received preamble to

MII output (random latency)

0 = Consume 1-byte preamble

before sending frame to MII

output for fixed latency

0 or

100BASE-TX Preamble

Restore

1 (if CONFIG[2:0] = 100)

See Table 2-2 and

Table 2-4 for details.

14.7

RW

1 = Restore received preamble to

MII output

0 = Remove all 7-bytes of

preamble before sending frame

(starting with SFD) to MII output

10BASE-T Preamble

Restore

14.6

0

14.5:0

Reserved

—

RO

00_0001

000h

Register 15h – RXER Counter

15.15:0 RXER Counter

Register 1Bh – Interrupt Control/Status

Receive error counter for Symbol

Error frames

RO/SC

1 = Enable Jabber Interrupt

0 = Disable Jabber Interrupt

1b.15

Jabber Interrupt Enable

RW

0

1 = Enable Receive Error

Interrupt

0 = Disable Receive Error

Interrupt

Receive Error Interrupt

Enable

1b.14

1 = Enable Page Received

Interrupt

0 = Disable Page Received

Interrupt

Page Received Interrupt

Enable

1b.13

1b.12

RW

0

1 = Enable Parallel Detect Fault

Interrupt

0 = Disable Parallel Detect Fault

Interrupt

Parallel Detect Fault Inter-

rupt Enable

DS00002245B-page 34

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

TABLE 4-2:

Address

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Default

Name

Description

(Note 4-1)

1 = Enable Link Partner

Acknowledge Interrupt

0 = Disable Link Partner

Acknowledge Interrupt

Link Partner Acknowledge

Interrupt Enable

1b.11

1b.10

1b.9

RW

0

1= Enable Link Down Interrupt

0 = Disable Link Down Interrupt

Link Down Interrupt Enable

1 = Enable Remote Fault

Interrupt

0 = Disable Remote Fault

Interrupt

Remote Fault Interrupt

Enable

1 = Enable Link Up Interrupt

0 = Disable Link Up Interrupt

1b.8

1b.7

1b.6

1b.5

Link Up Interrupt Enable

Jabber Interrupt

RW

0

1 = Jabber occurred

0 = Jabber did not occur

RO/SC

1 = Receive Error occurred

0 = Receive Error did not occur

Receive Error Interrupt

Page Receive Interrupt

1 = Page Receive occurred

0 = Page Receive did not occur

1 = Parallel Detect Fault

occurred

0 = Parallel Detect Fault did not

occur

Parallel Detect Fault

Interrupt

1b.4

1b.3

RO/SC

0

1= Link Partner Acknowledge

occurred

0= Link Partner Acknowledge did

not occur

Link Partner Acknowledge

Interrupt

1= Link Down occurred

0= Link Down did not occur

1b.2

1b.1

1b.0

Link Down Interrupt

Remote Fault Interrupt

Link Up Interrupt

RO/SC

0

1= Remote Fault occurred

0= Remote Fault did not occur

1= Link Up occurred

0= Link Up did not occur

Register 1Eh – PHY Control 1

[00] = LED1 : Speed

LED0 : Link/Activity

1e:15:14 LED mode

[01] = LED1 : Activity

LED0 : Link

RW

00

[10], [11] = Reserved

0 = Polarity is not reversed

1 = Polarity is reversed

1e.13

1e.12

Polarity

RO

—

0

Reserved

—

0 = MDI

1 = MDI-X

1e.11

MDI/MDI-X State

Reserved

—

1e:10:8

—

0 = Normal mode

1e:7

Remote loopback

1 = Remote (analog) loop back is

enabled

RW

0

 2017 Microchip Technology Inc.

DS00002245B-page 35

KSZ8041NL/RNL

TABLE 4-2:

Address

1e:6:0

REGISTER DESCRIPTIONS (CONTINUED)

Name Description

Mode

(Note 4-1)

Default

Reserved

—

Register 1Fh – PHY Control 2

0 = Auto MDI/MDI-X mode

1 = HP Auto MDI/MDI-X mode

1f:15

HP_MDIX

RW

1

0

When Auto MDI/MDI-X is

disabled,

0 = MDI mode

Transmit on TX+/- (pins 7, 6) and

Receive on RX+/- (pins 5, 4)

1 = MDI-X mode

1f:14

MDI/MDI-X Select

RW

Transmit on RX+/- (pins 5,4) and

Receive on TX+/- (pins 7, 6)

1 = Disable auto MDI/MDI-X

0 = Enable auto MDI/MDI-X

1f:13

1f.12

Pair Swap Disable

Energy Detect

RW

RO

0

1 = Presence of signal on RX+/-

analog wire pair

0 = No signal detected on RX+/-

1 = Force link pass

0 = Normal link operation

This bit bypasses the control

logic and allows the transmitter

to send a pattern even if there is

no link.

1f.11

Force Link

RW

0

Register 1Fh – PHY Control 2 (Continued)

1 = Enable power saving

0 = Disable power saving

If power saving mode is enabled

and the cable is disconnected,

the RXC clock output (in MII

mode) is disabled. RXC clock is

enabled after the cable is con-

nected and a link is established.

1f.10

Power Saving

RW

0

1 = Interrupt pin active high

0 = Interrupt pin active low

1f.9

1f.8

Interrupt Level

Enable Jabber

RW

0

1

1 = Enable jabber counter

0 = Disable jabber counter

1 = Auto-negotiation process

completed

0 = Auto-negotiation process not

completed

1f.7

Auto-Negotiation Complete

RW

0

Enable Pause (Flow Con-

trol)

1 = Flow control capable

0 = No flow control capability

1f.6

1f.5

RO

0

1 = PHY in isolate mode

0 = PHY in normal operation

PHY Isolate

[000] = Still in auto-negotiation

[001] = 10 BASE-T half-duplex

[010] = 100 BASE-TX half-duplex

[011] = Reserved

1f.4:2

Operation Mode Indication

RO

000

[101] = 10 BASE-T full-duplex

[110] = 100 BASE-TX full-duplex

[111] = Reserved

DS00002245B-page 36

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

TABLE 4-2:

Address

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Default

Name

Description

(Note 4-1)

1 = Enable SQE test

0 = Disable SQE test

1f.1

Enable SQE test

RW

0

1 = Disable scrambler

0 = Enable scrambler

1f.0

Disable Data Scrambling

Note 4-1

RW = Read/Write

RO = Read only

SC = Self-cleared

LH = Latch high

LL = Latch low

 2017 Microchip Technology Inc.

DS00002245B-page 37

KSZ8041NL/RNL

5.0

5.1

OPERATIONAL CHARACTERISTICS

Absolute Maximum Ratings (Note 5-1)

Supply Voltage (V_{DDPLL_1.8})...................................................................................................................... –0.5V to +2.4V

Supply Voltage (V_{DDPLL_3.3}, V_{DDPLL_3.3}) .................................................................................................. –0.5V to +4.0V

Input Voltage (all inputs)............................................................................................................................ –0.5V to +4.0V

Output Voltage (all outputs)....................................................................................................................... –0.5V to +4.0V

Storage Temperature (T_S)......................................................................................................................–55°C to +150°C

ESD Performance Rating (Note 5-2)........................................................................................................................+6 kV

5.2

Operating Ratings (Note 5-3)

Supply Voltage (V_{DDIO_3.3}, V_{DDA_3.3})................................................................................................+3.135V to +3.465V

Ambient Temperature

(T_A, Commercial)...............................................................................................................................0°C to +70°C

(T_A, Industrial)................................................................................................................................–40°C to +85°C

(T_A, Automotive Qualified) .............................................................................................................–40°C to +85°C

Maximum Junction Temperature (T_Jmaximum)....................................................................................................+125°C

Thermal Resistance (_JA)......................................................................................................................................34°C/W

Thermal Resistance (_JC)........................................................................................................................................6°C/W

Note 5-1

Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute

maximum rating may cause permanent damage to the device. Operation of the device at these or

any other conditions above those specified in the operating sections of this specification is not

implied. Maximum conditions for extended periods may affect reliability.

Note 5-2

Note 5-3

Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kꢀ in

series with 100 pF.

The device is not guaranteed to function outside its operating rating.

DS00002245B-page 38

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

6.0

ELECTRICAL CHARACTERISTICS

TABLE 6-1:

Symbol

ELECTRICAL CHARACTERISTICS (Note 6-1, Note 6-2)

Parameter

Condition

Min.

Typ.

Max.

Units

Supply Current

Chip only (no transformer);

Full-duplex traffic @ 100%

utilization

I_DD1

100BASE-TX

—

53.0

38.0

—

mA

Chip only (no transformer);

Full-duplex traffic @ 100%

utilization

I_DD2

10BASE-T

Ethernet cable discon-

nected (reg. 1F.10 = 1)

I_DD3

I_DD4

Power-Saving Mode

Power-Down Mode

—

32.0

4.0

—

mA

Software power-down (reg.

0.11 = 1)

TTL Inputs

V_IH

Input High Voltage

Input Low Voltage

Input Current

—

2.0

—

0.8

10

V

V_IL

—

I_IN

V_IN= GND ~ VDDIO

—

–10

µA

TTL Outputs

V_OH

Output High Voltage

Output Low Voltage

I_OH= 4 mA

I_OL= 4 mA

—

2.4

—

0.4

10

V

V_OL

|I_oz|

Output Tri-State Leakage

—

µA

LED Outputs

Each LED pin (LED0,

LED1)

I_LED

Output Drive Current

—

8

—

mA

100BASE-TX Transmit (measured differentially after 1:1 transformer)

Peak Differential Output

Voltage

100 termination across

differential output

V_O

0.95

—

1.05

2

V

100 termination across

differential output

V_IMB

Output Voltage Imbalance

%

Rise/Fall Time

—

3

—

5

0.5

+0.25

5

ns

%

V

Rise/Fall Time Imbalance

Duty Cycle Distortion

Overshoot

—

0

t_r, t_f

—

V_SET

—

Reference Voltage of ISET

Output Jitter

—

0.65

0.7

—

Peak-to-peak

1.4

ns

10BASE-T Transmit (measured differentially after 1:1 transformer)

Peak Differential Output

Voltage

100 termination across

differential output

2.2

—

2.8

V

V_P

—

Jitter Added

Peak-to-peak

—

3.5

—

ns

t_r, t_f

Rise/Fall Time

25

10BASE-T Receive

Squelch Threshold

5 MHz square wave

—

400

—

mV

V_SQ

Note 6-1

Current consumption is for the single 3.3V supply KSZ8041NL/RNL device only, and includes the

1.8V supply voltage (VDDPLL_1.8) that is provided by the KSZ8041NL/RNL. The PHY port’s

transformer consumes an additional 45 mA @ 3.3V for 100BASE-TX and 70 mA @ 3.3V for

10BASE-T.

Note 6-2

T_A= 25°C. Specification for packaged product only.

 2017 Microchip Technology Inc.

DS00002245B-page 39

KSZ8041NL/RNL

7.0

7.1

TIMING DIAGRAMS

MII SQE Timing

FIGURE 7-1:

MII SQE TIMING (10BASE-T)

t_WL

TXC

t_WH

t_P

TXEN

COL

t_SQE

t_SQEP

TABLE 7-1:

MII SQE TIMING (10BASE-T) PARAMETERS

Description Min.

Timing

Parameter

Typ.

Max.

Unit

t_P

TXC Period

—

400

200

2.5

—

ns

us

t_WL

TXC Pulse Width Low

t_WH

t_SQE

t_SQEP

TXC Pulse Width High

COL (SQE) Delay After TXEN De-Asserted

COL (SQE) Pulse Duration

1.0

7.2

MII Transmit Timing (10BASE-T)

FIGURE 7-2:

MII TRANSMIT TIMING (10BASE-T)

t_P

t_WL

TXC

t_WH

TXEN

TXD[3:0]

CRS

t_SU2

t_HD2

t_SU1

t_HD1

t_CRS1

t_CRS2

DS00002245B-page 40

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

TABLE 7-2:

MII TRANSMIT TIMING (10BASE-T) PARAMETERS

Timing

Parameter

Description

Min.

Typ.

Max.

Units

t_P

TXC Period

—

400

200

—

ns

t_WL

TXC Pulse Width Low

t_WH

TXC Pulse Width High

t_SU1

t_SU2

t_HD1

t_HD2

t_CRS1

t_CRS2

TXD[3:0] Setup to Rising Edge of TXC

TXEN Setup to Rising Edge of TXC

TXD[3:0] Hold from Rising Edge of TXC

TXEN Hold from Rising Edge of TXC

TXEN High to CRS Asserted Latency

TXEN Low to CRS De-Asserted Latency

10

0

—

0

—

160

510

7.3

MII Receive Timing (10BASE-T)

FIGURE 7-3:

MII RECEIVE TIMING (10BASE-T)

CRS

t_RLAT

t_OD

RXDV

RXD[3:0]

RXER

t_P

t_WL

RXC

t_WH

TABLE 7-3:

MII RECEIVE TIMING (10BASE-T) PARAMETERS

Timing

Parameter

Description

Min.

Typ.

Max.

Unit

t_P

RXC Period

—

400

200

—

ns

t_WL

t_WH

RXC Pulse Width Low

RXC Pulse Width High

(RXD[3:0], RXER, RXDV) Output Delay

from Rising Edge of RXC

t_OD

182

—

225

—

ns

µs

t_RLAT

CRS to (RXD[3:0], RXER, RXDV) Latency

6.5

 2017 Microchip Technology Inc.

DS00002245B-page 41

KSZ8041NL/RNL

7.4

MII Transmit Timing (100BASE-TX)

FIGURE 7-4:

MII TRANSMIT TIMING (100BASE-TX)

t_WL

TXC

t_WH

t_HD2

t_SU2

t_P

TXEN

t_HD1

t_SU1

Data

In

TXD[3:0]

t_CRS2

t_CRS1

CRS

TABLE 7-4:

MII TRANSMIT TIMING (100BASE-TX) PARAMETERS

Timing

Parameter

Description

Min.

Typ.

Max.

Unit

t_P

TXC Period

—

40

20

—

ns

t_WL

TXC Pulse Width Low

t_WH

TXC Pulse Width High

t_SU1

t_SU2

t_HD1

t_HD2

t_CRS1

t_CRS2

TXD[3:0] Setup to Rising Edge of TXC

TXEN Setup to Rising Edge of TXC

TXD[3:0] Hold from Rising Edge of TXC

TXEN Hold from Rising Edge of TXC

TXEN High to CRS Asserted Latency

TXEN Low to CRS De-Asserted Latency

10

0

—

34

33

DS00002245B-page 42

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

7.5

MII Receive Timing (100BASE-TX)

FIGURE 7-5:

MII RECEIVE TIMING (100BASE-TX)

CRS

t_RLAT

RXDV

t_OD

RXD[3:0]

RXER

t_WL

RXC

t_WH

t_P

TABLE 7-5:

MII RECEIVE TIMING (100BASE-TX) PARAMETERS

Timing

Parameter

Description

Min.

Typ

Max.

Units

t_P

RXC Period

—

40

20

—

ns

t_WL

t_WH

RXC Pulse Width Low

RXC Pulse Width High

—

(RXD[3:0], RXER, RXDV) Output Delay

from Rising Edge of RXC

t_OD

19

—

25

ns

CRS to RXDV Latency

CRS to RXD[3:0] Latency

CRS to RXER Latency

—

140

52

—

ns

t_RLAT

60

 2017 Microchip Technology Inc.

DS00002245B-page 43

KSZ8041NL/RNL

7.6

RMII Timing

FIGURE 7-6:

RMII TIMING – DATA RECEIVED FROM RMII

FIGURE 7-7:

RMII TIMING – DATA INPUT TO RMII

Receive

Timing

tcyc

REFCLK

CRSDV

RXD[1:0]

tod

TABLE 7-6:

RMII TIMING PARAMETERS – KSZ8041NL

Timing

Parameter

Description

Min.

Typ

Max.

Units

t_cyc

t₁

Clock Cycle

Setup Time

Hold Time

—

4

20

—

9

ns

t₂

2

t_od

Output Delay

3

TABLE 7-7:

RMII TIMING PARAMETERS – KSZ8041RNL

Description Min.

Timing

Parameter

Typ

Max.

Units

t_cyc

t₁

Clock Cycle

Setup Time

Hold Time

—

4

20

—

11

—

13

ns

t₂

1

t_od

Output Delay

9

DS00002245B-page 44

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

7.7

Auto-Negotiation Timing

FIGURE 7-8:

Auto-Negotiation

Fast Link Pulse (FLP) Timing

AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING

FLP

Burst

FLP

Burst

TX+/TX-

t_FLPW

t_BTB

Clock

Pulse

Data

Pulse

Clock

Pulse

Data

Pulse

TX+/TX-

t_PW

t_CTD

t_CTC

TABLE 7-8:

AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS

Timing

Parameter

Description

FLP Burst to FLP Burst

Min.

Typ

Max.

Units

t_BTB

t_FLPW

t_PW

8

16

2

24

—

ms

ns

FLP Burst Width

—

Clock/Data Pulse Width

Clock Pulse to Data Pulse

Clock Pulse to Clock Pulse

—

100

64

—

t_CTD

t_CTC

55.5

111

69.5

139

µs

128

Number of Clock/Data Pulse per FLP

Burst

—

17

—

33

—

 2017 Microchip Technology Inc.

DS00002245B-page 45

KSZ8041NL/RNL

7.8

MDC/MDIO Timing

FIGURE 7-9:

MDC/MDIO TIMING

t_P

MDC

t_MD1

t_MD2

MDIO

(PHY input)

Valid

Data

Valid

Data

t_MD3

MDIO

(PHY output)

Valid

Data

TABLE 7-9:

MDC/MDIO TIMING PARAMETERS

Description

Timing

Parameter

Min.

—

Typ.

Max.

—

Unit

t_P

MDC Period

400

—

ns

MDIO (PHY Input) Setup to Rising Edge of

MDC

—

t_1MD1

10

MDIO (PHY Input) Hold from Rising Edge of

MDC

—

t_MD2

t_MD3

4

ns

MDIO (PHY Output) Delay from Rising

Edge of MDC

—

222

DS00002245B-page 46

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

7.9

Power-Up/Reset Timing

The KSZ8041NL/RNL reset timing requirement is summarized in Figure 7-10 and Figure 7-10.

FIGURE 7-10: POWER-UP/RESET TIMING

TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS

Parameters

Description

Min

Max

Units

Supply Voltage (V_DDIO_3.3, V_DDA_3.3) Rise

Time

t_VR

250

—

µs

t_sr

t_cs

t_ch

t_rc

Stable Supply Voltage to Reset High

Configuration Setup Time

10

5

—

ms

ns

Configuration Hold Time

5

Reset to Strap-In Pin Output

6

The supply voltage (V_DDIO_3.3 and V_DDA_3.3) power-up waveform should be monotonic. The 250 µs minimum rise time

is from 10% to 90%.

After the deassertion of reset, it is recommended to wait a minimum of 100 µs before starting programming on the MIIM

(MDC/MDIO) Interface.

 2017 Microchip Technology Inc.

DS00002245B-page 47

KSZ8041NL/RNL

7.10 Reset Circuit

The reset circuit in Figure 7-11 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power

supply.

FIGURE 7-11:

RECOMMENDED RESET CIRCUIT

3.3V

D1: 1N4148

D1

R

10k

KSZ8041NL

RST#

C

10µF

Figure 7-12 shows a reset circuit recommended for applications where reset is driven by another device (for example,

the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2

is required if using different VDDIO voltage between the switch and CPU/FPGA. Diode D2 should be selected to provide

maximum 0.3V V_F(Forward Voltage), for example, VISHAY BAT54, MSS1P2L. Alternatively, a level shifter device can

also be used. D2 is not required if PHY and CPU/FPGA use same V_DDIOvoltage.

FIGURE 7-12:

RECOMMENDED RESET CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET

OUTPUT

3.3V

R

10k

D1

KSZ8041NL

RST#

CPU/FPGA

RST_OUT_n

D2

C

10µF

D1, D2: 1N4148

DS00002245B-page 48

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

7.11 Reference Circuits for LED Strapping Pins

The Figure 7-13 shows the reference circuits for pull-up, float, and pull-down on the LED1 and LED0 strapping pins.

FIGURE 7-13:

REFERENCE CIRCUITS FOR LED STRAPPING PINS

3.3V

Pull-up

220Ω

4.7kΩ

KSZ8041NL/RNL

LED pin

3.3V

Float

220Ω

KSZ8041NL/RNL

LED pin

3.3V

Pull-down

220Ω

KSZ8041NL/RNL

LED pin

1kΩ

 2017 Microchip Technology Inc.

DS00002245B-page 49

KSZ8041NL/RNL

8.0

SELECTION OF ISOLATION TRANSFORMER

A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode

chokes is recommended for exceeding FCC requirements.

Table 8-1 gives the recommended transformer characteristics.

TABLE 8-1:

TRANSFORMER SELECTION CRITERIA

Parameter

Value

Test Condition

Turns Ratio

1 CT : 1 CT

350 H

0.4 H

—

Open-Circuit Inductance (minimum)

Leakage Inductance (maximum)

Inter-Winding Capacitance (typical)

DC Resistance (typical)

100 mV, 100 kHz, 8 mA

1 MHz (minimum)

12 pF

—

0.9

—

0 MHz – 65 MHz

—

Insertion Loss (maximum)

HIPOT (minimum)

1.0 dB

1500 V_RMS

TABLE 8-2:

QUALIFIED SINGLE PORT MAGNETICS

Magnetic Manufacturer

Part Number

Auto MDI-X

Number of Ports

Bel Fuse

S558-5999-U7

SI-46001

SI-50170

LF8505

Yes

1

Bel Fuse (Mag Jack)

Delta

LanKom

LF-H41S

H1102

Pulse

Pulse (low cost)

Transpower

TDK (Mag Jack)

H1260

HB726

TLA-6T718

DS00002245B-page 50

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

9.0

SELECTION OF REFERENCE CRYSTAL

TABLE 9-1:

TYPICAL REFERENCE CRYSTAL CHARACTERISTICS

Characteristics

Value

Units

Frequency

25

±50

20

MHz

ppm

pF

Frequency Tolerance (maximum)

Load Capacitance

40

ꢀ

Series Resistance

 2017 Microchip Technology Inc.

DS00002245B-page 51

KSZ8041NL/RNL

10.0 PACKAGE OUTLINE & RECOMMENDED LAND PATTERN

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

FIGURE 10-1:

32-LEAD QFN 5X5 PACKAGE

TITLE

32 LEAD QFN 5x5mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN

DRAWING #

UNIT

MM

QFN55-32LD-PL-1

DS00002245B-page 52

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

APPENDIX A: DATA SHEET REVISION HISTORY

TABLE A-1:

REVISION HISTORY

Section/Figure/Entry

Figure 10-1

Revision

Correction

Updated the 32-LEAD QFN 5X5 Package

illustration.

DS00002245B (11-17-17)

—

Minor text changes throughout.

DS00002245A (05-02-17)

ALL

KSZ8041NL/RNL Datasheet initial conversion to

Microchip DS00002245A.

 2017 Microchip Technology Inc.

DS00002245B-page 53

KSZ8041NL/RNL

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make

files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-

tains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s

guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion

groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-

nars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive

e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or

development tool of interest.

To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-

cation” and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales

offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-

ment.

Technical support is available through the web site at: http://microchip.com/support

DS00002245B-page 54

Advance Information

 2017 Microchip Technology Inc.

KSZ8041NL/RNL

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, for example, on pricing or delivery, refer to the factory or the listed sales office.

X

Examples:

PART NO.

Device

X

a)

b)

c)

KSZ8041NL – 10BASE-T/100BASE-TX Physi-

cal Layer Transceiver, MII/RMII, 32-pin QFN

Commercial temperature

KSZ8041NLI – 10BASE-T/100BASE-TX Phys-

ical Layer Transceiver, MII/RMII, 32-pin QFN,

Industrial Temperature

Temperature

Power

Option

Interface

Package

Device:

KSZ8041 – 10BASE-T/100BASE-TX Physical Layer

Transceiver

KSZ8041NL-AM

– 10BASE-T/100BASE-TX

Physical Layer Transceiver, MII/RMII, 32-pin

QFN

Industrial temperature, Automotive Grade 3

Interface:

Blank

R

=

MII/RMII

RMII

d)

e)

f)

KSZ8041RNLU

–

10BASE-T/100BASE-TX

Physical Layer Transceiver, RMII, 32-pin QFN

Automotive Grade 3

Package:

N

L

=

32-pin QFN

KSZ8041RNL

–

10BASE-T/100BASE-TX

Physical Layer Transceiver, RMII, 32-pin QFN,

Commercial temperature

Power Option:

Temperature:

Integrated LDO/LDO Controller/Regulator

KSZ8041RNLI

–

10BASE-T/100BASE-TX

Physical Layer Transceiver, RMII, 32-pin QFN,

Industrial temperature

Blank

I

U

=

Commercial (0°C to +70°C)

Industrial (–40°C to +85°C)

Automotive Grade 3 (–40°C to +85°C)

(RMII Versions Only)

AM

=

Automotive Grade 3 (–40°C to +85°C)

(MII/RMII Version Only)

 2017 Microchip Technology Inc.

DS00002245B-page 55

KSZ8041NL/RNL

NOTES:

DS00002245B-page 56

 2017 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be

superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO

REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of

Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implic-

itly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF,

dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR,

MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,

SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and

other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision

Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard,

CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,

EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench,

MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,

SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other

countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 978-1-5224-2384-3

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

CERTIFIEDꢀBYꢀDNVꢀ

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TSꢀ16949ꢀ==ꢀ

 2017 Microchip Technology Inc.

Advance Information

DS00002245B-page 57

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Australia - Sydney

Tel: 61-2-9868-6733

India - Bangalore

Tel: 91-80-3090-4444

Austria - Wels

Tel: 43-7242-2244-39

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Tel: 86-10-8569-7000

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Tel: 91-11-4160-8631

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

China - Chengdu

Tel: 86-28-8665-5511

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Tel: 91-20-4121-0141

Finland - Espoo

Tel: 358-9-4520-820

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Web Address:

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Tel: 678-957-9614

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China - Qingdao

Philippines - Manila

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Tel: 86-532-8502-7355

Tel: 63-2-634-9065

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

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Singapore

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Germany - Rosenheim

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Dallas

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Italy - Milan

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Fax: 39-0331-466781

China - Suzhou

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Taiwan - Taipei

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Detroit

Novi, MI

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Thailand - Bangkok

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Netherlands - Drunen

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Fax: 31-416-690340

Indianapolis

Noblesville, IN

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Fax: 317-773-5453

Tel: 317-536-2380

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Tel: 86-592-2388138

Norway - Trondheim

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Poland - Warsaw

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Los Angeles

Mission Viejo, CA

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Spain - Madrid

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Raleigh, NC

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Sweden - Gothenberg

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New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

DS00002245B-page 58

 2017 Microchip Technology Inc.

10/25/17


型号：	KSZ8041NL-AM
厂家：	MICROCHIP
描述：	IC TXRX PHY 10/100 AUTO 32-MLF 局域网（LAN）标准以太网：16GBASE-T 电信电信集成电路
文件：	总58页 (文件大小：1576K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KSZ8041NL-AM [MICROCHIP]

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