KSZ8041NLAM [MICREL]
10Base-T/100Base-TX Physical Layer Transceiver; 10BASE-T / 100BASE-TX物理层收发器
| 型号： | KSZ8041NLAM |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 10Base-T/100Base-TX Physical Layer Transceiver |
| 文件： | 总45页 (文件大小：585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KSZ8041NL
10Base-T/100Base-TX
Physical Layer Transceiver
Data Sheet Rev. 1.2
General Description
The KSZ8041NL is a single supply 10Base-T/100Base-TX
Physical Layer Transceiver, which provides MII/RMII
interfaces to transmit and receive data. An unique mixed
signal design extends signaling distance while reducing
power consumption.
The KSZ8041NL represents a new level of features and
performance and is an ideal choice of physical layer
transceiver for 10Base-T/100Base-TX applications.
The KSZ8041NL comes in a 32-pin, lead-free MLF® (QFN
per JDEC) package (See Ordering Information).
HP Auto MDI/MDI-X provides the most robust solution for
eliminating the need to differentiate between crossover
and straight-through cables.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Diagram
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
M9999-071808-1.2
July 2008
Micrel, Inc.
KSZ8041NL
Features
Applications
• Single-chip 10Base-T/100Base-TX physical layer
• Printer
• LOM
• Game Console
• IPTV
• IP Phone
• IP Set-top Box
solution
• Fully compliant to IEEE 802.3u Standard
• Low power CMOS design, power consumption of
<180mW
• HP auto MDI/MDI-X for reliable detection and
correction for straight-through and crossover cables
with disable and enable option
• Robust operation over standard cables
• Power down and power saving modes
• MII interface support
• RMII interface support with external 50MHz system
clock
• MIIM (MDC/MDIO) management bus to 6.25MHz for
rapid PHY register configuration
• Interrupt pin option
• Programmable LED outputs for link, activity and
speed
• ESD rating (6kV)
• Single power supply (3.3V)
• Built-in 1.8V regulator for core
• Available in 32-pin (5mm x 5mm) MLF® package
Ordering Information
Part Number
Temp. Range
0°C to 70°C
Package
Lead Finish
Pb-Free
Description
KSZ8041NL
KSZ8041NLI (1)
KSZ8041NL AM(1)
32-Pin MLF®
32-Pin MLF®
32-Pin MLF®
Commercial Temperature Device
Industrial Temperature Device
Automotive Qualified Device
-40°C to 85°C
-40°C to 85°C
Pb-Free
Pb-Free
Note:
1. Contact factory for lead time.
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KSZ8041NL
Revision History
Revision
1.0
Date
Summary of Changes
10/13/06
4/27/07
Data sheet created.
1.1
Added maximum MDC clock speed.
Added 40K +/-30% to note 1 of Pin Description and Strapping Options tables for internal pull-ups/pull-
downs.
Changed Model Number in Register 3h – PHY Identifier 2.
Changed polarity (swapped definition) of DUPLEX strapping pin.
Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6].
Set “Disable power saving” as the default for Register 1Fh bit [10].
Corrected LED1 (pin 31) definition for Activity in LED mode 01.
Added Symbol Error to MII/RMII Receive Error description and Register 15h – RXER Counter.
Added a 100pF capacitor on REXT (pin 10) in Pin Description table.
Added Automotive Qualified part number to Ordering Information.
Added maximum case temperature.
1.2
7/18/08
Added thermal resistance (θJC).
Added chip maximum current consumption.
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Contents
Pin Configuration ..................................................................................................................................................................8
Pin Description......................................................................................................................................................................9
Strapping Options...............................................................................................................................................................12
Functional Description .......................................................................................................................................................13
100Base-TX Transmit.......................................................................................................................................................13
100Base-TX Receive........................................................................................................................................................13
PLL Clock Synthesizer......................................................................................................................................................13
Scrambler/De-scrambler (100Base-TX only)....................................................................................................................13
10Base-T Transmit ...........................................................................................................................................................13
10Base-T Receive ............................................................................................................................................................13
SQE and Jabber Function (10Base-T only)......................................................................................................................14
Auto-Negotiation...............................................................................................................................................................14
MII Management (MIIM) Interface ....................................................................................................................................16
Interrupt (INTRP) ..............................................................................................................................................................16
MII Data Interface .............................................................................................................................................................16
MII Signal Definition..........................................................................................................................................................17
Transmit Clock (TXC)...................................................................................................................................................17
Transmit Enable (TXEN) ..............................................................................................................................................17
Transmit Data [3:0] (TXD[3:0]) .....................................................................................................................................17
Receive Clock (RXC)....................................................................................................................................................17
Receive Data Valid (RXDV)..........................................................................................................................................18
Receive Data [3:0] (RXD[3:0])......................................................................................................................................18
Receive Error (RXER) ..................................................................................................................................................18
Carrier Sense (CRS) ....................................................................................................................................................18
Collision (COL) .............................................................................................................................................................18
Reduced MII (RMII) Data Interface...................................................................................................................................18
RMII Signal Definition .......................................................................................................................................................19
Reference Clock (REF_CLK) .......................................................................................................................................19
Transmit Enable (TX_EN) ............................................................................................................................................19
Transmit Data [1:0] (TXD[1:0]) .....................................................................................................................................19
Carrier Sense/Receive Data Valid (CRS_DV)..............................................................................................................19
Receive Data [1:0] (RXD[1:0])......................................................................................................................................19
Receive Error (RX_ER) ................................................................................................................................................19
Collision Detection........................................................................................................................................................20
HP Auto MDI/MDI-X..........................................................................................................................................................20
Straight Cable...............................................................................................................................................................20
Crossover Cable...........................................................................................................................................................21
Power Management..........................................................................................................................................................22
Power Saving Mode .....................................................................................................................................................22
Power Down Mode .......................................................................................................................................................22
Reference Clock Connection Options ..............................................................................................................................22
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Reference Circuit for Power and Ground Connections ....................................................................................................23
Register Map........................................................................................................................................................................24
Register Description...........................................................................................................................................................24
Absolute Maximum Ratings(1) ............................................................................................................................................31
Operating Ratings(2) ............................................................................................................................................................31
Electrical Characteristics(4) ................................................................................................................................................31
Electrical Characteristics(6) ................................................................................................................................................32
Timing Diagrams .................................................................................................................................................................33
MII SQE Timing (10Base-T) .............................................................................................................................................33
MII Transmit Timing (10Base-T).......................................................................................................................................34
MII Receive Timing (10Base-T)........................................................................................................................................35
MII Transmit Timing (100Base-TX) ..................................................................................................................................36
MII Receive Timing (100Base-TX) ...................................................................................................................................37
RMII Timing.......................................................................................................................................................................38
Auto-Negotiation Timing ...................................................................................................................................................39
MDC/MDIO Timing ...........................................................................................................................................................40
Reset Timing.....................................................................................................................................................................41
Reset Circuit ........................................................................................................................................................................42
Reference Circuits for LED Strapping Pins......................................................................................................................43
Selection of Isolation Transformer....................................................................................................................................44
Selection of Reference Crystal ..........................................................................................................................................44
Package Information...........................................................................................................................................................45
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List of Figures
Figure 1. Auto-Negotiation Flow Chart.................................................................................................................................15
Figure 2. Typical Straight Cable Connection .......................................................................................................................20
Figure 3. Typical Crossover Cable Connection ...................................................................................................................21
Figure 4. 25MHz Crystal / Oscillator Reference Clock for MII Mode ...................................................................................22
Figure 5. 50MHz Oscillator Reference Clock for RMII Mode...............................................................................................22
Figure 6. KSZ8041NL Power and Ground Connections......................................................................................................23
Figure 7. MII SQE Timing (10Base-T) .................................................................................................................................33
Figure 8. MII Transmit Timing (10Base-T)...........................................................................................................................34
Figure 9. MII Receive Timing (10Base-T)............................................................................................................................35
Figure 10. MII Transmit Timing (100Base-TX).....................................................................................................................36
Figure 11. MII Receive Timing (100Base-TX)......................................................................................................................37
Figure 12. RMII Timing – Data Received from RMII............................................................................................................38
Figure 13. RMII Timing – Data Input to RMII .......................................................................................................................38
Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................39
Figure 15. MDC/MDIO Timing..............................................................................................................................................40
Figure 16. Reset Timing.......................................................................................................................................................41
Figure 17. Recommended Reset Circuit..............................................................................................................................42
Figure 18. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output......................................................42
Figure 19. Reference Circuits for LED Strapping Pins.........................................................................................................43
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List of Tables
Table 1. MII Management Frame Format ............................................................................................................................16
Table 2. MII Signal Definition ...............................................................................................................................................17
Table 3. RMII Signal Description..........................................................................................................................................19
Table 4. MDI/MDI-X Pin Definition .......................................................................................................................................20
Table 5. KSZ8041NL Power Pin Description.......................................................................................................................23
Table 6. MII SQE Timing (10Base-T) Parameters...............................................................................................................33
Table 7. MII Transmit Timing (10Base-T) Parameters.........................................................................................................34
Table 8. MII Receive Timing (10Base-T) Parameters..........................................................................................................35
Table 9. MII Transmit Timing (100Base-TX) Parameters....................................................................................................36
Table 10. MII Receive Timing (100Base-TX) Parameters...................................................................................................37
Table 11. RMII Timing Parameters......................................................................................................................................38
Table 12. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters...............................................................................39
Table 13. MDC/MDIO Timing Parameters...........................................................................................................................40
Table 14. Reset Timing Parameters ....................................................................................................................................41
Table 15. Transformer Selection Criteria.............................................................................................................................44
Table 16. Qualified Single Port Magnetics...........................................................................................................................44
Table 17. Typical Reference Crystal Characteristics...........................................................................................................44
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Pin Configuration
32-Pin (5mm x 5mm) MLF®
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Pin Description
Type(1)
Gnd
Pin Number
Pin Name
Pin Function
1
2
3
4
5
6
7
8
GND
Ground
VDDPLL_1.8
VDDA_3.3
RX-
P
1.8V analog VDD
P
3.3V analog VDD
I/O
I/O
I/O
I/O
O
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Physical transmit or receive signal (+ differential)
Crystal feedback
RX+
TX-
TX+
XO
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode is selected.
9
XI /
I
Crystal / Oscillator / External Clock Input
REFCLK
MII Mode:
25MHz +/-50ppm (crystal, oscillator, or external clock)
50MHz +/-50ppm (oscillator, or external clock only)
RMII Mode:
10
REXT
I/O
Set physical transmit output current
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041NL reference schematics.
11
12
13
MDIO
MDC
I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
Management Interface (MII) Clock Input
I
This pin is synchronous to the MDIO data interface.
MII Mode:
Receive Data Output[3](2)
/
RXD3 /
Ipu/O
PHYAD0
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
14
15
RXD2 /
Ipd/O
Ipd/O
MII Mode:
Receive Data Output[2](2)
/
PHYAD1
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
RXD1 /
MII Mode:
Receive Data Output[1](2)
Receive Data Output[1](3)
/
/
RXD[1] /
PHYAD2
RMII Mode:
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
16
RXD0 /
Ipu/O
MII Mode:
Receive Data Output[0](2)
Receive Data Output[0](3)
/
/
RXD[0] /
DUPLEX
RMII Mode:
Config Mode:
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
17
18
VDDIO_3.3
RXDV /
P
3.3V digital VDD
MII Mode:
Ipd/O
Receive Data Valid Output /
CRSDV /
CONFIG2
RMII Mode:
Config Mode:
Carrier Sense/Receive Data Valid Output /
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
19
RXC
O
MII Mode:
Receive Clock Output
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KSZ8041NL
Type(1)
Ipd/O
Pin Number
Pin Name
Pin Function
20
RXER /
RX_ER /
ISO
MII Mode:
Receive Error Output /
Receive Error Output /
RMII Mode:
Config Mode:
The pull-up/pull-down value is latched as ISOLATE during
power-up / reset. See “Strapping Options” section for details.
21
INTRP
Opu
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt
output to active low (default) or active high.
22
23
TXC
O
I
MII Mode:
MII Mode:
RMII Mode:
Transmit Clock Output
Transmit Enable Input /
Transmit Enable Input
TXEN /
TX_EN
TXD0 /
TXD[0]
MII Mode:
RMII Mode:
MII Mode:
RMII Mode:
MII Mode:
Transmit Data Input[0](4)
Transmit Data Input[0](5)
Transmit Data Input[1](4)
Transmit Data Input[1](5)
Transmit Data Input[2](4)
Transmit Data Input[3](4)
Collision Detect Output /
/
/
24
25
I
I
TXD1 /
TXD[1]
26
27
28
TXD2
TXD3
I
/
/
I
MII Mode:
COL /
Ipd/O
MII Mode:
CONFIG0
Config Mode:
The pull-up/pull-down value is latched as CONFIG0 during
power-up / reset. See “Strapping Options” section for details.
29
30
CRS /
Ipd/O
Ipu/O
MII Mode:
Carrier Sense Output /
CONFIG1
Config Mode:
The pull-up/pull-down value is latched as CONFIG1 during
power-up / reset. See “Strapping Options” section for details.
LED0 /
LED Output:
Config Mode:
Programmable LED0 Output /
NWAYEN
Latched as Auto-Negotiation Enable (register 0h, bit 12) during
power-up / reset. See “Strapping Options” section for details.
The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Link/Activity
No Link
Link
Pin State
LED Definition
OFF
H
L
ON
Activity
Toggle
Blinking
LED mode = [01]
Link
Pin State
LED Definition
No Link
Link
H
L
OFF
ON
LED mode = [10]
Reserved
LED mode = [11]
Reserved
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KSZ8041NL
Type(1)
Ipu/O
Pin Number
Pin Name
Pin Function
31
LED1 /
LED Output:
Config Mode:
Programmable LED1 Output /
SPEED
Latched as SPEED (register 0h, bit 13) during power-up / reset.
See “Strapping Options” section for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Speed
10BT
Pin State
LED Definition
H
L
OFF
ON
100BT
LED mode = [01]
Activity
Pin State
H
LED Definition
OFF
No Activity
Activity
Toggle
Blinking
LED mode = [10]
Reserved
LED mode = [11]
Reserved
32
RST#
GND
I
Chip Reset (active low)
Ground
PADDLE
Notes:
Gnd
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down (40K +/-30%).
Ipu = Input with internal pull-up (40K +/-30%).
Opu = Output with internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the MII.
RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered
data are sent from the PHY.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through
the MII. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are
received by the PHY from the MAC.
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Strapping Options
Type(1)
Ipd/O
Pin Number
Pin Name
Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
The PHY Address is latched at power-up / reset and is configurable to any value from
1 to 7.
Ipd/O
Ipu/O
The default PHY Address is 00001.
PHY Address bits [4:3] are always set to ‘00’.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as
follows:
CONFIG[2:0]
Mode
000
MII (default)
001
RMII
010
Reserved – not used
Reserved – not used
PCS Loopback
Reserved – not used
Reserved – not used
Reserved – not used
011
100
101
110
111
20
31
ISO
Ipd/O
Ipu/O
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
During power-up / reset, this pin value is latched into register 0h bit 10.
SPEED mode
SPEED
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
16
30
DUPLEX
NWAYEN
Ipu/O
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
Note:
1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this case,
it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE or
PCS Loopback mode, or is not configured with an incorrect PHY Address.
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KSZ8041NL
Functional Description
The KSZ8041NL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u Specification.
On the media side, the KSZ8041NL supports 10Base-T and 100Base-TX with HP auto MDI/MDI-X for reliable detection of
and correction for straight-through and crossover cables.
The KSZ8041NL offers a choice of MII or RMII data interface connection with the MAC processor. The MII management
bus option gives the MAC processor complete access to the KSZ8041NL control and status registers. Additionally, an
interrupt pin eliminates the need for the processor to poll for PHY status change.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the
design more efficient and allow for lower power consumption and smaller chip die size.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output.
The output current is set by an external 6.49kΩ 1% resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4
ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-
shaped 10Base-T output drivers are also incorporated into the 100Base-TX drivers.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8041NL generates 125MΗz, 25MΗz and 20MΗz clocks for system timing. Internal clocks are generated from an
external 25MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an external 50MHz oscillator
or system clock.
Scrambler/De-scrambler (100Base-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers also perform internal wave-shaping and pre-emphasize, and output 10Base-T signals with a typical amplitude
of 2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency
when driven by an all-ones Manchester-encoded signal.
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and
a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data.
A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RX+ and
RX- inputs from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming
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signal and the KSZ8041NL decodes a data frame. The receive clock is kept active during idle periods in between data
reception.
SQE and Jabber Function (10Base-T only)
In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required
as a test of the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the
10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the 10Base-
T transmitter is re-enabled and COL is de-asserted (returns to low).
Auto-Negotiation
The KSZ8041NL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification. Auto-
negotiation is enabled by either hardware pin strapping (pin 30) or software (register 0h bit 12).
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link
partners advertise their capabilities to each other, and then compare their own capabilities with those they received from
their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode
of operation.
The following list shows the speed and duplex operation mode from highest to lowest.
•
•
•
•
Priority 1: 100Base-TX, full-duplex
Priority 2: 100Base-TX, half-duplex
Priority 3: 10Base-T, full-duplex
Priority 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8041NL link partner is forced to bypass auto-negotiation, the KSZ8041NL
sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the
KSZ8041NL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement
protocol.
The auto-negotiation link up process is shown in the following flow chart.
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Start Auto Negotiation
N
o
Parallel
Operation
Force Link Setting
Yes
Listen for 10BASE-T
Link Pulses
Bypass Auto Negotiation
and Set Link Mode
Attempt Auto
Negotiation
Listen for 100BASE-TX
Idles
No
Join
Flow
Link Mode Set ?
Yes
Link Mode Set
Figure 1. Auto-Negotiation Flow Chart
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KSZ8041NL
MII Management (MIIM) Interface
The KSZ8041NL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output
(MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ8041NL. An
external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. Additional details
on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:
•
•
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with one or more KSZ8041NL devices. Each KSZ8041NL device is assigned a PHY address
between 1 and 7 by the PHYAD[2:0] strapping pins.
•
An internal addressable set of thirteen 16-bit MDIO registers. Register [0:6] are required, and their functions are
defined by the IEEE 802.3u Specification. The additional registers are provided for expanded functionality.
The KSZ8041NL supports MIIM in both MII mode and RMII mode.
The following table shows the MII Management frame format for the KSZ8041NL.
Preamble
Start of
Frame
Read/Write PHY
REG
TA
Data
Idle
OP Code
Address
Address
Bits [4:0]
RRRRR
RRRRR
Bits [15:0]
Bits [4:0]
00AAA
Read
Write
32 1’s
32 1’s
01
01
10
01
Z0
10
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
Z
Z
00AAA
Table 1. MII Management Frame Format
Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ8041NL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to enable
and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and are
used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh.
Bit 9 of register 1Fh sets the interrupt level to active high or active low.
MII Data Interface
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Specification. It provides a common
interface between physical layer and MAC layer devices, and has the following key characteristics:
•
•
•
•
Supports 10Mbps and 100Mbps data rates.
Uses a 25MHz reference clock, sourced by the PHY.
Provides independent 4-bit wide (nibble) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception.
By default, the KSZ8041NL is configured in MII mode after it is power-up or reset with the following:
•
•
A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
CONFIG[2:0] (pins 18, 29, 28) set to ‘000’ (default setting).
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MII Signal Definition
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3u Specification for detailed information.
Direction
(with respect to PHY,
KSZ8041NL signal)
MII
Direction
(with respect to MAC)
Description
Signal Name
TXC
Output
Input
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN
TXD[3:0]
RXC
Input
Output
Output
Input
Transmit Enable
Input
Transmit Data [3:0]
Receive Clock
Output
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
Receive Data Valid
Receive Data [3:0]
Receive Error
RXDV
RXD[3:0]
RXER
CRS
Output
Output
Output
Output
Output
Input
Input
Input, or (not required)
Input
Input
Carrier Sense
COL
Collision Detection
Table 2. MII Signal Definition
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission
by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN
is de-asserted are ignored by the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
•
In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle, or link is down.
•
In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
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Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
•
In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains
asserted until the end of the frame.
•
In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
Receive Data [3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable
of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame
presently being transferred from the PHY.
RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
•
In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
•
In 100Mbps mode, CRS is asserted when a start-of-stream delimiter, or /J/K symbol pair is detected. CRS is de-
asserted when an end-of-stream delimiter, or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts
CRS if IDLE symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This is
used to inform the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
Reduced MII (RMII) Data Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
•
•
•
•
Supports 10Mbps and 100Mbps data rates.
Uses a single 50MHz reference clock provided by the MAC or the system board.
Provides independent 2-bit wide (di-bit) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception.
The KSZ8041NL is configured in RMII mode after it is power-up or reset with the following:
•
•
A 50MHz reference clock connected to REFCLK (pin 9).
CONFIG[2:0] (pins 18, 29, 28) set to ‘001’.
In RMII mode, unused MII signals, TXD[3:2] (pins 27, 26), are tied to ground.
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RMII Signal Definition
The following table describes the RMII signals. Refer to RMII Specification for detailed information.
Direction
(with respect to PHY,
KSZ8041NL signal)
RMII
Signal Name
Direction
(with respect to MAC)
Description
REF_CLK
Input
Input, or Output
Synchronous 50 MHz clock reference for
receive, transmit and control interface
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
CRS_DV
RXD[1:0]
RX_ER
Input
Output
Transmit Data [1:0]
Carrier Sense/Receive Data Valid
Receive Data [1:0]
Receive Error
Output
Output
Output
Input
Input
Input, or (not required)
Table 3. RMII Signal Description
Reference Clock (REF_CLK)
REF_CLK is sourced by the MAC or system board. It is a continuous 50MHz clock that provides the timing reference for
TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER.
Transmit Enable (TX_EN)
TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final di-bit of a frame.
TX_EN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY. TXD[1:0] is ”00” to indicate idle when TX_EN is de-asserted. Values other than “00” on TXD[1:0]
while TX_EN is de-asserted are ignored by the PHY.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of the
frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place.
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers
two bits of recovered data from the PHY. RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other
than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC.
Receive Error (RX_ER)
RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is
capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY.
RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the
MAC.
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Collision Detection
The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable
between the KSZ8041NL and its link partner. This feature allows the KSZ8041NL to use either type of cable to connect
with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from
the link partner, and then assigns transmit and receive pairs of the KSZ8041NL accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 1F bit 13. MDI and MDI-X mode is
selected by register 1F bit 14 if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.
The IEEE 802.3u Standard defines MDI and MDI-X as follow:
MDI
MDI-X
RJ-45 Pin
Signal
TD+
TD-
RJ-45 Pin
Signal
RD+
RD-
1
2
3
6
1
2
3
6
RD+
RD-
TD+
TD-
Table 4. MDI/MDI-X Pin Definition
Straight Cable
A straight cable connects a MDI device to a MDI-X device, or a MDI-X device to a MDI device. The following diagram
depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
10/100 Ethernet
10/100 Ethernet
Media Dependent Interface
Media Dependent Interface
1
1
Transmit Pair
2
Receive Pair
2
Straight
Cable
3
3
4
4
Receive Pair
5
Transmit Pair
5
6
7
8
6
7
8
Modular Connector
(RJ-45)
Modular Connector
(RJ-45)
HUB
NIC
(Repeater or Switch)
Figure 2. Typical Straight Cable Connection
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KSZ8041NL
Crossover Cable
A crossover cable connects a MDI device to another MDI device, or a MDI-X device to another MDI-X device. The
following diagram depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices).
10/100 Ethernet
10/100 Ethernet
Media Dependent Interface
Media Dependent Interface
1
1
Crossover
Cable
Receive Pair
2
Receive Pair
2
3
3
4
4
Transmit Pair
5
Transmit Pair
5
6
7
8
6
7
8
Modular Connector (RJ-45)
HUB
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
(Repeater or Switch)
Figure 3. Typical Crossover Cable Connection
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KSZ8041NL
Power Management
The KSZ8041NL offers the following power management modes:
Power Saving Mode
This mode is used to reduce power consumption when the cable is unplugged. It is in effect when auto-negotiation mode
is enabled, cable is disconnected, and register 1F bit 10 is set to 1. Under power saving mode, the KSZ8041NL shuts
down all transceiver blocks, except for transmitter, energy detect and PLL circuits. Additionally, in MII mode, the RXC
clock output is disabled. RXC clock is enabled after the cable is connected and link is established.
Power saving mode is disabled by writing a zero to register 1F bit 10.
Power Down Mode
This mode is used to power down the entire KSZ8041NL device when it is not in use. Power down mode is enabled by
writing a one to register 0 bit 11. In the power down state, the KSZ8041NL disables all internal functions, except for the
MII management interface.
Reference Clock Connection Options
A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041NL. The reference
clock is 25MHz for MII mode and 50MHz for RMII mode. The following two figures illustrate how to connect the reference
clock to XI / REFCLK (pin 9) and XO (pin 8) of the KSZ8041NL.
Figure 4. 25MHz Crystal / Oscillator Reference Clock for MII Mode
Figure 5. 50MHz Oscillator Reference Clock for RMII Mode
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Reference Circuit for Power and Ground Connections
The KSZ8041NL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground
connections are shown in the following figure and table.
Figure 6. KSZ8041NL Power and Ground Connections
Power Pin
VDDPLL_1.8
VDDA_3.3
VDDIO_3.3
Pin Number Description
2
3
Decouple with 10uF and 0.1uF capacitors-to-ground.
Connect to board’s 3.3V supply through ferrite bead.
Connect to board’s 3.3V supply.
17
Table 5. KSZ8041NL Power Pin Description
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Register Map
Register Number (Hex)
Description
0h
Basic Control
1h
Basic Status
2h
PHY Identifier 1
3h
PHY Identifier 2
4h
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Auto-Negotiation Next Page
Link Partner Next Page Ability
Reserved
5h
6h
7h
8h
9h – 14h
15h
RXER Counter
16h – 1Ah
1Bh
Reserved
Interrupt Control/Status
Reserved
1Ch – 1Dh
1Eh
PHY Control 1
1Fh
PHY Control 2
Register Description
Mode(1)
Address
Name
Description
Default
Register 0h – Basic Control
0.15
Reset
1 = Software reset
RW/SC
0
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
1 = Loop-back mode
0 = Normal operation
1 = 100Mbps
0.14
0.13
Loop-back
RW
RW
0
Speed Select
(LSB)
Set by SPEED strapping pin.
0 = 10Mbps
See “Strapping Options” section
for details.
This bit is ignored if auto-negotiation is enabled
(register 0.12 = 1).
0.12
Auto-
Negotiation
Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
RW
Set by NWAYEN strapping pin.
See “Strapping Options” section
for details.
If enabled, auto-negotiation result overrides
settings in register 0.13 and 0.8.
0.11
0.10
Power Down
Isolate
1 = Power down mode
0 = Normal operation
RW
RW
0
1 = Electrical isolation of PHY from MII and
TX+/TX-
Set by ISO strapping pin.
See “Strapping Options” section
for details.
0 = Normal operation
0.9
Restart Auto-
Negotiation
1 = Restart auto-negotiation process
0 = Normal operation.
RW/SC
0
This bit is self-cleared after a ‘1’ is written to it.
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Mode(1)
Address
Name
Description
Default
0.8
Duplex Mode
1 = Full-duplex
0 = Half-duplex
RW
Set by DUPLEX strapping pin.
See “Strapping Options” section
for details.
0.7
Collision Test
1 = Enable COL test
0 = Disable COL test
RW
0
0.6:1
0.0
Reserved
Disable
RO
RW
000_000
0
0 = Enable transmitter
1 = Disable transmitter
Transmitter
Register 1h – Basic Status
1.15
1.14
1.13
1.12
1.11
100Base-T4
1 = T4 capable
RO
RO
RO
RO
RO
0
1
1
1
1
0 = Not T4 capable
100Base-TX
Full Duplex
1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps full-duplex
1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps half-duplex
100Base-TX
Half Duplex
10Base-T Full 1 = Capable of 10Mbps full-duplex
Duplex
0 = Not capable of 10Mbps full-duplex
10Base-T Half 1 = Capable of 10Mbps half-duplex
Duplex
0 = Not capable of 10Mbps half-duplex
1.10:7
1.6
Reserved
RO
RO
0000
1
No Preamble
1 = Preamble suppression
0 = Normal preamble
1.5
Auto-
Negotiation
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
RO
0
1.4
1.3
Remote Fault
1 = Remote fault
RO/LH
RO
0
1
0 = No remote fault
Auto-
Negotiation
Ability
1 = Capable to perform auto-negotiation
0 = Not capable to perform auto-negotiation
1.2
1.1
1.0
Link Status
1 = Link is up
RO/LL
RO/LH
RO
0
0
1
0 = Link is down
Jabber Detect
1 = Jabber detected
0 = Jabber not detected (default is low)
1 = Supports extended capabilities registers
Extended
Capability
Register 2h – PHY Identifier 1
2.15:0
PHY ID
Number
Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1 (hex)
RO
0022h
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Mode(1)
Address
Name
Description
Default
Register 3h – PHY Identifier 2
3.15:10
PHY ID
Number
Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1 (hex)
RO
0001_01
3.9:4
3.3:0
Model Number Six bit manufacturer’s model number
RO
RO
01_0001
0010
Revision
Number
Four bit manufacturer’s model number
Register 4h – Auto-Negotiation Advertisement
4.15
Next Page
1 = Next page capable
RW
0
0 = No next page capability.
4.14
4.13
Reserved
RO
RW
0
0
Remote Fault
1 = Remote fault supported
0 = No remote fault
4.12:11
4.10
Reserved
Pause
RO
RW
00
0
1 = PAUSE function supported
0 = No PAUSE function supported
1 = T4 capable
4.9
4.8
100Base-T4
RO
RW
0
0 = No T4 capability
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
Set by SPEED strapping pin.
See “Strapping Options” section
for details.
4.7
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
RW
Set by SPEED strapping pin.
0 = No 100Mbps half-duplex capability
See “Strapping Options” section
for details.
4.6
10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
[00001] = IEEE 802.3
RW
RW
RW
1
4.5
10Base-T
Half-Duplex
1
4.4:0
Selector Field
0_0001
Register 5h – Auto-Negotiation Link Partner Ability
5.15
5.14
5.13
Next Page
1 = Next page capable
RO
RO
RO
0
0
0
0 = No next page capability
1 = Link code word received from partner
0 = Link code word not yet received
1 = Remote fault detected
Acknowledge
Remote Fault
0 = No remote fault
5.12
Reserved
Pause
RO
RO
0
5.11:10
[00] = No PAUSE
00
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric PAUSE
1 = T4 capable
5.9
100Base-T4
RO
0
0 = No T4 capability
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Mode(1)
Address
Name
Description
Default
5.8
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
[00001] = IEEE 802.3
RO
0
5.7
100Base-TX
Half-Duplex
RO
RO
RO
RO
0
5.6
10Base-T
Full-Duplex
0
5.5
10Base-T
Half-Duplex
0
5.4:0
Selector Field
0_0001
Register 6h – Auto-Negotiation Expansion
6.15:5
6.4
Reserved
RO
0000_0000_000
0
Parallel
Detection Fault
1 = Fault detected by parallel detection
0 = No fault detected by parallel detection.
1 = Link partner has next page capability
RO/LH
6.3
6.2
Link Partner
Next Page
Able
RO
RO
0
1
0 = Link partner does not have next page
capability
Next Page
Able
1 = Local device has next page capability
0 = Local device does not have next page
capability
6.1
6.0
Page Received 1 = New page received
0 = New page not received yet
RO/LH
RO
0
0
Link Partner
Auto-
1 = Link partner has auto-negotiation capability
0 = Link partner does not have auto-negotiation
capability
Negotiation
Able
Register 7h – Auto-Negotiation Next Page
7.15
Next Page
1 = Additional next page(s) will follow
0 = Last page
RW
0
7.14
7.13
Reserved
RO
RW
0
1
Message Page 1 = Message page
0 = Unformatted page
7.12
7.11
Acknowledge2 1 = Will comply with message
0 = Cannot comply with message
RW
RO
0
0
Toggle
1 = Previous value of the transmitted link code
word equaled logic one
0 = Logic zero
Message Field 11-bit wide field to encode 2048 messages
7.10:0
RW
000_0000_0001
Register 8h – Link Partner Next Page Ability
8.15
8.14
8.13
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
RO
RO
RO
0
0
0
Acknowledge
1 = Successful receipt of link word
0 = No successful receipt of link word
Message Page 1 = Message page
0 = Unformatted page
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KSZ8041NL
Mode(1)
Address
Name
Description
Default
8.12
Acknowledge2 1 = Able to act on the information
0 = Not able to act on the information
RO
0
8.11
Toggle
1 = Previous value of transmitted link code
word equal to logic zero
RO
0
0 = Previous value of transmitted link code
word equal to logic one
8.10:0
Message Field
RO
000_0000_0000
Register 15h – RXER Counter
15.15:0 RXER Counter Receive error counter for Symbol Error frames
Register 1Bh – Interrupt Control/Status
RO/SC
RW
0000h
0
1b.15
1b.14
1b.13
1b.12
1b.11
Jabber
Interrupt
Enable
1 = Enable Jabber Interrupt
0 = Disable Jabber Interrupt
Receive Error
Interrupt
Enable
1 = Enable Receive Error Interrupt
0 = Disable Receive Error Interrupt
RW
RW
RW
RW
0
0
0
0
Page Received 1 = Enable Page Received Interrupt
Interrupt
Enable
0 = Disable Page Received Interrupt
Parallel Detect 1 = Enable Parallel Detect Fault Interrupt
Fault Interrupt
Enable
0 = Disable Parallel Detect Fault Interrupt
Link Partner
Acknowledge
Interrupt
1 = Enable Link Partner Acknowledge Interrupt
0 = Disable Link Partner Acknowledge
Interrupt
Enable
1b.10
1b.9
1b.8
Link Down
Interrupt
Enable
1= Enable Link Down Interrupt
0 = Disable Link Down Interrupt
RW
RW
RW
0
0
0
Remote Fault
Interrupt
Enable
1 = Enable Remote Fault Interrupt
0 = Disable Remote Fault Interrupt
Link Up
Interrupt
Enable
1 = Enable Link Up Interrupt
0 = Disable Link Up Interrupt
1b.7
1b.6
1b.5
1b.4
1b.3
Jabber
Interrupt
1 = Jabber occurred
RO/SC
RO/SC
RO/SC
RO/SC
RO/SC
0
0
0
0
0
0 = Jabber did not occurred
1 = Receive Error occurred
0 = Receive Error did not occurred
1 = Page Receive occurred
0 = Page Receive did not occurred
Receive Error
Interrupt
Page Receive
Interrupt
Parallel Detect 1 = Parallel Detect Fault occurred
Fault Interrupt
0 = Parallel Detect Fault did not occurred
Link Partner
Acknowledge
Interrupt
1= Link Partner Acknowledge occurred
0= Link Partner Acknowledge did not occurred
1b.2
Link Down
Interrupt
1= Link Down occurred
RO/SC
0
0= Link Down did not occurred
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KSZ8041NL
Mode(1)
Address
Name
Description
Default
1b.1
Remote Fault
Interrupt
1= Remote Fault occurred
0= Remote Fault did not occurred
1= Link Up occurred
RO/SC
0
1b.0
Link Up
Interrupt
RO/SC
RW
0
0= Link Up did not occurred
Register 1Eh – PHY Control 1
1e:15:14
LED mode
[00] =
00
LED1 : Speed
LED0 : Link/Activity
[01] =
LED1 : Activity
LED0 : Link
[10] =
Reserved
[11] =
Reserved
1e.13
Polarity
0 = Polarity is not reversed
1 = Polarity is reversed
RO
1e.12
1e.11
Reserved
RO
RO
0
0
MDI/MDI-X
State
0 = MDI
1 = MDI-X
1e:10:8
1e:7
Reserved
Remote
0 = Normal mode
RW
loopback
1 = Remote (analog) loop back is enable
1e:6:0
Reserved
Register 1Fh – PHY Control 2
1f:15
HP_MDIX
0 = Micrel Auto MDI/MDI-X mode
1 = HP Auto MDI/MDI-X mode
When Auto MDI/MDI-X is disabled,
0 = MDI Mode
RW
RW
1
0
1f:14
MDI/MDI-X
Select
Transmit on TX+/- (pins 7,6) and
Receive on RX+/- (pins 5,4)
1 = MDI-X Mode
Transmit on RX+/- (pins 5,4) and
Receive on TX+/- (pins 7,6)
1f:13
1f.12
Pairswap
Disable
1 = Disable auto MDI/MDI-X
0 = Enable auto MDI/MDI-X
RW
RO
0
0
Energy Detect
1 = Presence of signal on RX+/- analog wire
pair
0 = No signal detected on RX+/-
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KSZ8041NL
Mode(1)
Address
Name
Description
Default
1f.11
Force Link
1 = Force link pass
RW
0
0 = Normal link operation
This bit bypasses the control logic and allow
transmitter to send pattern even if there is no
link.
1f.10
Power Saving
1 = Enable power saving
0 = Disable power saving
RW
0
If power saving mode is enabled and the cable
is disconnected, the RXC clock output (in MII
mode) is disabled. RXC clock is enabled after
the cable is connected and link is established.
1f.9
1f.8
1f.7
Interrupt Level
Enable Jabber
1 = Interrupt pin active high
RW
RW
RW
0
1
0
0 = Interrupt pin active low
1 = Enable jabber counter
0 = Disable jabber counter
Auto-
Negotiation
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
1f.6
Enable Pause
(Flow Control)
1 = Flow control capable
0 = No flow control capability
1 = PHY in isolate mode
0 = PHY in normal operation
[000] = still in auto-negotiation
[001] = 10Base-T half-duplex
[010] = 100Base-TX half-duplex
[011] = reserved
RO
RO
RO
0
1f.5
PHY Isolate
0
1f.4:2
Operation
Mode
Indication
000
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = reserved
1f.1
1f.0
Enable SQE
test
1 = Enable SQE test
RW
RW
0
0
0 = Disable SQE test
Disable Data
Scrambling
1 = Disable scrambler
0 = Enable scrambler
Note:
1. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
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KSZ8041NL
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage
Supply Voltage
(VDDPLL_1.8)...............................................-0.5V to +2.4V
(VDDIO_3.3, VDDA_3.3) ...................................-0.5V to +4.0V
Input Voltage (all inputs) ...............................-0.5V to +4.0V
Output Voltage (all outputs) ..........................-0.5V to +4.0V
Lead Temperature (soldering, 10sec.)....................... 260°C
Storage Temperature (Ts) ..........................-55°C to +150°C
ESD Rating(3)..................................................................6kV
(VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V
Ambient Temperature (TA)..............................0°C to +70°C
Maximum Junction Temperature (TJ Max) ................. 125°C
Maximum Case Temperature (TC Max)...................... 150°C
Thermal Resistance (θJA) .........................................34°C/W
Thermal Resistance (θJC)...........................................6°C/W
Electrical Characteristics(4)
Symbol
Supply Current(5)
IDD1 100Base-TX
Parameter
Condition
Min
Typ
Max
Units
Chip only (no transformer);
53
38
58.3
41.8
mA
mA
Full-duplex traffic @ 100% utilization
Chip only (no transformer);
IDD2
10Base-T
Full-duplex traffic @ 100% utilization
Ethernet cable disconnected (reg. 1F.10 = 1)
Software power down (reg. 0.11 = 1)
IDD3
Power Saving Mode
Power Down Mode
32
4
35.2
4.4
mA
mA
IDD4
TTL Inputs
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
Input Current
2.0
2.4
V
V
0.8
10
VIN = GND ~ VDDIO
-10
µA
TTL Outputs
VOH
VOL
|Ioz|
Output High Voltage
IOH = -4mA
IOL = 4mA
V
V
Output Low Voltage
0.4
10
Output Tri-State Leakage
µA
100Base-TX Transmit (measured differentially after 1:1 transformer)
VO
Peak Differential Output Voltage
Output Voltage Imbalance
Rise/Fall Time
0.95
1.05
V
100Ω termination across differential output
100Ω termination across differential output
VIMB
tr, tf
2
5
%
3
0
ns
ns
ns
%
0.5
+ 0.25
5
Rise/Fall Time Imbalance
Duty Cycle Distortion
Overshoot
0.65
0.7
VSET
Reference Voltage of ISET
Output Jitter
V
1.4
Peak-to-peak
ns
Notes:
1. Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent
damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification
is not implied. Maximum conditions for extended periods may affect reliability.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
4. TA = 25°C. Specification for packaged product only.
5. Current consumption is for the single 3.3V supply KSZ8041NL device only, and includes the 1.8V supply voltage (VDDPLL_1.8) that is provided by the
KSZ8041NL. The PHY port’s transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for 10Base-T.
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KSZ8041NL
Electrical Characteristics(6)
10Base-T Transmit (measured differentially after 1:1 transformer)
VP
Peak Differential Output Voltage
Jitter Added
2.2
2.8
3.5
V
100Ω termination across differential output
Peak-to-peak
ns
ns
25
tr, tf
Rise/Fall Time
10Base-T Receive
VSQ
Squelch Threshold
5MHz square wave
400
mV
Notes:
6. TA = 25°C. Specification for packaged product only.
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KSZ8041NL
Timing Diagrams
MII SQE Timing (10Base-T)
Figure 7. MII SQE Timing (10Base-T)
Timing Parameter
Description
Min
Typ
400
200
200
2.5
Max
Unit
ns
tP
TXC period
tWL
TXC pulse width low
ns
tWH
tSQE
tSQEP
TXC pulse width high
ns
COL (SQE) delay after TXEN de-asserted
COL (SQE) pulse duration
us
1.0
us
Table 6. MII SQE Timing (10Base-T) Parameters
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KSZ8041NL
MII Transmit Timing (10Base-T)
Figure 8. MII Transmit Timing (10Base-T)
Timing Parameter
Description
Min
Typ
400
200
200
Max
Unit
ns
tP
TXC period
tWL
TXC pulse width low
ns
tWH
tSU1
tSU2
tHD1
tHD2
tCRS1
TXC pulse width high
ns
TXD[3:0] setup to rising edge of TXC
TXEN setup to rising edge of TXC
TXD[3:0] hold from rising edge of TXC
TXEN hold from rising edge of TXC
TXEN high to CRS asserted latency
10
10
0
ns
ns
ns
0
ns
4
8
Bit
Time
tCRS2
TXEN low to CRS de-asserted latency
Bit
Time
Table 7. MII Transmit Timing (10Base-T) Parameters
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KSZ8041NL
MII Receive Timing (10Base-T)
Figure 9. MII Receive Timing (10Base-T)
Timing Parameter
Description
Min
Typ
400
200
200
Max
Unit
ns
tP
RXC period
tWL
tWH
tOD
RXC pulse width low
RXC pulse width high
ns
ns
(RXD[3:0], RXER, RXDV) output
delay from rising edge of RXC
182
225
ns
tRLAT
CRS to (RXD[3:0], RXER, RXDV)
latency
6.5
us
Table 8. MII Receive Timing (10Base-T) Parameters
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KSZ8041NL
MII Transmit Timing (100Base-TX)
Figure 10. MII Transmit Timing (100Base-TX)
Timing Parameter
Description
Min
Typ
40
Max
Unit
ns
tP
TXC period
tWL
TXC pulse width low
20
ns
tWH
tSU1
tSU2
tHD1
tHD2
tCRS1
TXC pulse width high
20
ns
TXD[3:0] setup to rising edge of TXC
TXEN setup to rising edge of TXC
TXD[3:0] hold from rising edge of TXC
TXEN hold from rising edge of TXC
TXEN high to CRS asserted latency
10
10
0
ns
ns
ns
0
ns
4
4
Bit
Time
tCRS2
TXEN low to CRS de-asserted latency
Bit
Time
Table 9. MII Transmit Timing (100Base-TX) Parameters
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KSZ8041NL
MII Receive Timing (100Base-TX)
Figure 11. MII Receive Timing (100Base-TX)
Timing Parameter
Description
Min
Typ
40
Max
Unit
ns
tP
RXC period
tWL
tWH
tOD
RXC pulse width low
RXC pulse width high
20
ns
20
ns
(RXD[3:0], RXER, RXDV) output
delay from rising edge of RXC
19
1
25
3
ns
tRLAT
CRS to (RXD[3:0], RXER, RXDV)
latency
2
Bit
Time
Table 10. MII Receive Timing (100Base-TX) Parameters
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KSZ8041NL
RMII Timing
Figure 12. RMII Timing – Data Received from RMII
Figure 13. RMII Timing – Data Input to RMII
Timing Parameter
Description
Clock cycle
Setup time
Hold time
Min
Typ
Max
Unit
ns
tcyc
t1
20
4
2
ns
t2
ns
tod
Output delay
2.8
10
ns
Table 11. RMII Timing Parameters
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KSZ8041NL
Auto-Negotiation Timing
Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing
Timing Parameter
Description
Min
Typ
16
Max
Units
ms
ms
ns
tBTB
tFLPW
tPW
FLP Burst to FLP Burst
FLP Burst width
8
24
2
Clock/Data Pulse width
Clock Pulse to Data Pulse
Clock Pulse to Clock Pulse
100
64
tCTD
tCTC
55.5
111
17
69.5
139
33
µs
128
µs
Number of Clock/Data Pulse per
FLP Burst
Table 12. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
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KSZ8041NL
MDC/MDIO Timing
Figure 15. MDC/MDIO Timing
Timing Parameter
Description
Min
Typ
Max
Unit
tP
MDC period
400
ns
ns
ns
ns
t1MD1
tMD2
tMD3
MDIO (PHY input) setup to rising edge of MDC
MDIO (PHY input) hold from rising edge of MDC
MDIO (PHY output) delay from rising edge of MDC
10
10
222
Table 13. MDC/MDIO Timing Parameters
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Micrel, Inc.
KSZ8041NL
Reset Timing
The KSZ8041NL reset timing requirement is summarized in the following figure and table.
Figure 16. Reset Timing
Parameter
Description
Min
10
5
Max
Units
ms
ns
tsr
tcs
tch
trc
Stable supply voltage to reset high
Configuration setup time
Configuration hold time
Reset to strap-in pin output
5
ns
6
ns
Table 14. Reset Timing Parameters
After the de-assertion of reset, it is recommended to wait a minimum of 100 us before starting programming on the MIIM
(MDC/MDIO) Interface.
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KSZ8041NL
Reset Circuit
The following reset circuit is recommended for powering up the KSZ8041NL if reset is triggered by the power supply.
Figure 17. Recommended Reset Circuit
The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA).
At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041NL device. The RST_OUT_n
from CPU/FPGA provides the warm reset after power up.
Figure 18. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output.
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KSZ8041NL
Reference Circuits for LED Strapping Pins
The following figure shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins.
Figure 19. Reference Circuits for LED Strapping Pins
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KSZ8041NL
Selection of Isolation Transformer
A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes
is recommended for exceeding FCC requirements.
The following table gives recommended transformer characteristics.
Parameter
Value
Test Condition
Turns ratio
1 CT : 1 CT
350μH
0.4μH
Open-circuit inductance (min.)
Leakage inductance (max.)
Inter-winding capacitance (max.)
D.C. resistance (max.)
Insertion loss (max.)
HIPOT (min.)
100mV, 100kHz, 8mA
1MHz (min.)
12pF
0.9Ω
1.0dB
0MHz – 65MHz
1500Vrms
Table 15. Transformer Selection Criteria
Magnetic Manufacturer
Bel Fuse
Part Number
S558-5999-U7
SI-46001
SI-50170
LF8505
Auto MDI-X
Yes
Number of Port
1
1
1
1
1
1
1
1
1
Bel Fuse (Mag Jack)
Bel Fuse (Mag Jack)
Delta
Yes
Yes
Yes
LanKom
LF-H41S
H1102
Yes
Pulse
Yes
Pulse (low cost)
Transpower
H1260
Yes
HB726
Yes
TDK (Mag Jack)
TLA-6T718
Yes
Table 16. Qualified Single Port Magnetics
Selection of Reference Crystal
Characteristics
Value
Units
MHz
ppm
pF
Frequency
25
Frequency tolerance (max)
Load capacitance (max)
Series resistance
±50
20
40
Ω
Table 17. Typical Reference Crystal Characteristics
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KSZ8041NL
Package Information
32-Pin (5mm x 5mm) MLF® Package
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user.
A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to
fully indemnify Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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M9999-071808-1.2
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