HV5530PG-G [MICROCHIP]
EL DISPLAY DRIVER, PQFP44;
| 型号： | HV5530PG-G |
| 厂家： | 
MICROCHIP |
| 描述： | EL DISPLAY DRIVER, PQFP44 驱动 接口集成电路 |
| 文件： | 总18页 (文件大小：806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV5530
32-Channel Serial-to-Parallel Converter With Open Drain Outputs
Features
General Description
• 100 mA Minimum Sink Current
• 8 MHz Shift Register Speed
The HV5530 is
serial-to-parallel converter with open drain outputs.
This device is designed as driver for
AC-electroluminescent displays. It can also be used in
any application requiring multiple-output high-voltage
current-sinking capabilities such as driving inkjet and
electrostatic print heads, plasma panels, vacuum
fluorescent and large matrix LCD displays.
a
low-voltage to high-voltage
a
• Polarity and Blanking Inputs
• CMOS-compatible Inputs
• Forward and Reverse Shifting Options
• Diode to VPP allows Efficient Power Recovery
Applications
The device consists of a 32-bit Shift register, 32 latches
and control logic to perform the polarity select and
blanking of the outputs. Data is shifted through the Shift
register on the high-to-low transition of the clock. The
HV5530 shifts in a counter-clockwise direction when
viewed from the top of the package. A data output
buffer is provided for cascading devices. This output
reflects the current status of the last bit of the Shift
register. The operation of the Shift register is not
affected by the latch enable (LE), blanking (BL) and
polarity (POL) inputs. Transfer of data from the Shift
register to the latch occurs when the LE input is high.
The data in the latch is stored when LE is low.
• Display Driver
• Inkjet Driver
• Print Head Driver
• Microelectromechanical Systems Applications
Package Types
44-lead PLCC
44-lead PQFP
(Top view)
(Top view)
6
40
1 44
44
1
See Table 2-1 and Table 2-2 for pin information.
2017 Microchip Technology Inc.
DS20005851A-page 1
HV5530
Functional Block Diagram
POL
BL
LE
HVOUT1
DATA
IN
Latch
Latch
HVOUT
2
CLK
32-Bit
Shift
Register
(Outputs 3 to 30 not shown)
HVOUT31
Latch
Latch
HVOUT32
DATA
OUT
DS20005851A-page 2
2017 Microchip Technology Inc.
HV5530
Typical Application Circuit
High Voltage
Amplifier Driver
VDD
POL
BL
HVOUT1
LE
Data
In
CLK
HVOUT32
Data
Out
To Data Input for cascading
2017 Microchip Technology Inc.
DS20005851A-page 3
HV5530
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage, VDD (Note 1) .................................................................................................................. –0.5V to +15V
High-voltage Output Voltage, HVOUT (Note 1) ...................................................................................... –0.5V to +315V
Logic Input Levels (Note 1) .............................................................................................................. –0.5V to VDD+0.5V
Ground Current (Note 2) ......................................................................................................................................... 1.5A
Maximum Junction Temperature, TJ(MAX) ........................................................................................................... +125°C
Storage Temperature, TS .................................................................................................................... –65°C to +150°C
Continuous Total Power Dissipation:
44-lead PQFP (Note 3) ......................................................................................................................... 1200 mW
44-lead PLCC (Note 3) ......................................................................................................................... 1200 mW
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: All voltages are referenced to VSS
.
2: Duty cycle is limited by the total power dissipated in the package.
3: For operations above 25°C ambient, derate linearly to the maximum operating temperature at 20 mW/°C.
RECOMMENDED OPERATING CONDITIONS
Parameter
Logic Supply Voltage
Sym.
VDD
HVOUT
VIH
Min.
Typ.
—
Max.
Unit
V
Conditions
10.8
–0.3
VDD–2
0
13.2
+300
VDD
2
High-voltage Output Voltage
High-level Input Voltage
Low-level Input Voltage
Clock Frequency
—
V
—
V
VIL
—
V
fCLK
TA
—
MHz
°C
—
8
Operating Ambient Temperature
—
–40
+85
DS20005851A-page 4
2017 Microchip Technology Inc.
HV5530
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over recommended operating conditions unless otherwise stated
Parameter
DD Supply Current
Sym.
Min.
—
Typ.
—
Max.
Unit
Conditions
fCLK = 8 MHz,
DATA = 4 MHz
V
IDD
IDDQ
15
100
10
mA
f
—
—
Quiescent VDD Supply Current
Off State Output Current
µA All VIN = 0
All outputs high, all SWS
parallel
—
—
IO(OFF)
µA
—
—
—
—
—
—
—
—
High-level Logic Input Current
Low-level Logic Input Current
High-level Output Data Out
IIH
IIL
1
–1
—
µA
µA
V
V
IH = VDD
IL = 0V
V
VOH
VDD–1V
—
IDOUT = –100 µA
HVOUT = 100 mA
IDOUT = 100 µA
IOL = –100 mA
HVOUT
15
1
V
I
Low-level Output Voltage
HVOUT Clamp Voltage
VOL
VOC
—
V
Data Out
—
–1.5
V
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: For VDD = 12V and TA = 25°C.
Parameter
Clock Frequency
Sym.
Min.
Typ.
Max.
Unit
Conditions
fCLK
tWL, tWH
tSU
—
62
25
10
—
—
—
—
8
MHz
ns
Clock Width High or Low
—
—
—
Data Set-up Time before Clock Falls
Data Hold Time after Clock Falls
ns
tH
ns
RL = 2 kΩ
to VPP maximum
—
50
50
Turn-on Time, HVOUT from Enable
Latch Enable Pulse Width
tON
tWLE
tDLE
—
—
—
500
—
ns
ns
ns
Delay Time Clock to Latch Enable Low to
High
—
Latch Enable Set-up Time before Clock
Falls
50
tSLE
—
—
ns
Delay Time Clock to Data Low to High
Delay Time Clock to Data High to Low
tDLH
tDHL
—
—
—
—
100
100
ns CL = 15 pF
ns CL = 15 pF
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min. Typ.
Max.
Unit
Conditions
TEMPERATURE RANGE
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
TA
TJ(MAX)
TS
–40
—
—
—
—
+85
+125
+150
°C
°C
°C
–65
PACKAGE THERMAL RESISTANCE
44-lead PQFP
JA
JA
—
—
51
37
—
—
°C/W
°C/W
44-lead PLCC
2017 Microchip Technology Inc.
DS20005851A-page 5
HV5530
Timing Waveforms
VIH
VIL
VIH
VIL
DATA
IN
50%
Data Valid
50%
50%
tSU
tH
CLK
50%
50%
50%
tWH
tWL
VOH
VOL
50%
DATA
OUT
tDLH
VOH
VOL
50%
tDHL
VIH
VIL
50%
50%
LE
tWLE
tSLE
tDLE
VOH
VOL
HVOUT
w/ S/R HIGH
10%
tON
DS20005851A-page 6
2017 Microchip Technology Inc.
HV5530
2.0
PIN DESCRIPTION
The details on the pins of HV5530 44-lead PQFP and
44-lead PLCC are in Table 2-1 and Table 2-2,
respectively. Refer to Package Types for the location
of pins.
TABLE 2-1:
Pin Number
44-LEAD PQFP PIN FUNCTION TABLE
Pin Name
Description
1
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DATA OUTPUT Data output pin
NC
NC
No connection
No connection
No connection
NC
POL
CLK
VSS
VDD
Inverts the polarity of the HVOUT pins
Clock pin. Shift registers shift data on the falling edge of the input clock.
Reference voltage (usually ground)
Logic supply voltage
Latch enable pin. Data is shifted from the Shift register to the latches on logic
input high.
31
32
33
34
LE
DATA INPUT
BL
Data input pin
This blanking pin sets all HVOUT pins low or high depending upon the state of
polarity. See Table 3-2.
NC
No connection
2017 Microchip Technology Inc.
DS20005851A-page 7
HV5530
TABLE 2-1:
Pin Number
44-LEAD PQFP PIN FUNCTION TABLE (CONTINUED)
Pin Name
Description
35
36
37
38
39
40
41
42
43
44
HVOUT1
HVOUT2
HVOUT3
HVOUT4
HVOUT5
HVOUT6
HVOUT7
HVOUT8
HVOUT9
HVOUT10
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
TABLE 2-2:
Pin Number
44-LEAD PLCC PIN FUNCTION TABLE
Pin Name
Description
1
2
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DATA OUTPUT Data output pin
NC
NC
No connection
No connection
No connection
NC
POL
CLK
VSS
VDD
Inverts the polarity of the HVOUT pins
Clock pin. Shift registers shift data on the falling edge of the input clock.
Reference voltage (usually ground)
Logic supply voltage
Latch enable pin. Data is shifted from the Shift register to the latches on logic
input high.
26
LE
DS20005851A-page 8
2017 Microchip Technology Inc.
HV5530
TABLE 2-2:
Pin Number
27
44-LEAD PLCC PIN FUNCTION TABLE (CONTINUED)
Pin Name
Description
DATA INPUT
Data input pin
This blanking pin sets all HVOUT pins low or high depending upon the state of
polarity. See Table 3-2.
28
BL
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC
No connection
HVOUT1
HVOUT2
HVOUT3
HVOUT4
HVOUT5
HVOUT6
HVOUT7
HVOUT8
HVOUT9
HVOUT10
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
High-voltage output
2017 Microchip Technology Inc.
DS20005851A-page 9
HV5530
3.0
FUNCTIONAL DESCRIPTION
Follow the steps in Table 3-1 to power up and power
down the HV5530.
TABLE 3-1:
POWER-UP AND POWER-DOWN SEQUENCE
Power-up
Description
Power-down
Description
Remove all inputs.
Step
Step
1
2
3
Connect ground.
Apply VDD.
1
2
3
Remove VDD.
Set all inputs to a known state.
Disconnect ground.
TABLE 3-2:
Function
TRUTH FUNCTION TABLE
Inputs
Outputs
Shift Register
2...32
High-voltage Output
Data Out
Data CLK LE
BL POL
*
1
1
2...32
All On
X
X
X
X
L
L
L
L
H
L
*
*
*
*...*
*...*
*...*
On
Off
*
On...On
Off...Off
*...*
*
*
*
*
*
*
*
*
All Off
X
X
Invert Mode
Load S/R
X
X
H
H
H
H
H
H
H or L
↓
H or L
H or L
↓
L
H
H
L
H or L
*...*
*...*
*...*
*...*
*...*
*
*...*
X
X
L
↑
*
*
*
*...*
Load Latches
↑
*
*...*
H
H
H
H
L
H
Off
On
*...*
Transparent
Latch Mode
H
↓
*...*
Note:
H = High-logic level
L = Low-logic level
X = Irrelevant
↓ = High-to-low transition
↑ = Low-to-high transition
* = Dependent on the previous stage’s state before the last CLK ↓ or last LE high
VDD
VDD
HVOUT
DATA
DATA
IN
HVIN
OUT
VSS
VSS
VSS
High Voltage Outputs
Logic Data Output
Logic Inputs
FIGURE 3-1:
Input and Output Equivalent Circuits.
DS20005851A-page 10
2017 Microchip Technology Inc.
HV5530
4.0
4.1
PACKAGE MARKING INFORMATION
Packaging Information
44-lead PQFP
Example
XXXXXXXXX
HV5530PG
e3
e3
YYWWNNN
1729614
44-lead PLCC
Example
XXXXXXXXXX
HV5530PJ
e3
e3
1731985
YYWWNNN
Legend: XX...X Product Code or Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( )
e
3
*
e
3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2017 Microchip Technology Inc.
DS20005851A-page 11
HV5530
44-Lead PQFP Package Outline (PG)
10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch
D
D1
E
E1
Note 1
(Index Area
D1/4 x E1/4)
44
1
b
e
Top View
View B
Gauge
Plane
L2
A2
A1
A
Seating
Plane
L
Seating
Plane
θ
L1
Side View
View B
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Note:
1. $ꢁ3LQꢁꢃꢁLGHQWL¿HUꢁPXVWꢁEHꢁORFDWHGꢁLQꢁWKHꢁLQGH[ꢁDUHDꢁLQGLFDWHGꢂꢁ7KHꢁ3LQꢁꢃꢁLGHQWL¿HUꢁFDQꢁEHꢄꢁDꢁPROGHGꢁPDUNꢅLGHQWL¿HUꢆꢁDQꢁHPEHGGHGꢁPHWDOꢁPDUNHUꢆꢁRUꢁ
a printed indicator.
Symbol
A
A1
MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80*
NOM 2.00 13.90 10.00 13.90 10.00
MAX 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20*
A2
b
D
D1
E
E1
e
L
L1
L2
ș
0O
3.5O
7O
0.73
0.88
1.03
Dimension
(mm)
0.80
BSC
1.95 0.25
REF BSC
-
-
-
JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.
ꢀꢁ7KLVꢁGLPHQVLRQꢁLVꢁQRWꢁVSHFL¿HGꢁLQꢁWKHꢁ-('(&ꢁGUDZLQJꢂ
Drawings not to scale.
DS20005851A-page 12
2017 Microchip Technology Inc.
HV5530
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
.048/.042 x 45O
D
D1
1
O
.056/.042 x 45
6
44
40
.150 MAX
Note 1
(Index Area)
.075 MAX
E1
E
Note 2
.020max
(3 Places)
Top View
Vertical Side View
View B
b1
.020 MIN
Base
Plane
A
A2
Seating
Plane
e
A1
b
R
Horizontal Side View
View B
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Notes:
1. $ꢁ3LQꢁꢃꢁLGHQWL¿HUꢁPXVWꢁEHꢁORFDWHGꢁLQꢁWKHꢁLQGH[ꢁDUHDꢁLQGLFDWHGꢂꢁ7KHꢁ3LQꢁꢃꢁLGHQWL¿HUꢁFDQꢁEHꢄꢁDꢁPROGHGꢁPDUNꢅLGHQWL¿HUꢆꢁDQꢁHPEHGGHGꢁPHWDOꢁPDUNHUꢆꢁRU
a printed indicator.
2. $FWXDOꢁVKDSHꢁRIꢁWKLVꢁIHDWXUHꢁPD\ꢁYDU\ꢂ
Symbol
A
A1
A2
.062
-
b
.013
-
b1
.026
-
D
D1
E
E1
e
R
MIN
.165
.172
.180
.090
.105
.120
.685
.690
.695
.650
.653
.656
.685
.690
.695
.650
.653
.656
.025
.035
.045
Dimension
(inches)
.050
BSC
NOM
MAX
.083
.021
.036†
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
2017 Microchip Technology Inc.
DS20005851A-page 13
HV5530
NOTES:
DS20005851A-page 14
2017 Microchip Technology Inc.
HV5530
APPENDIX A: REVISION HISTORY
Revision A (October 2017)
• Converted Supertex Doc # DSFP-HV5530 to
Microchip DS20005851A
• Removed “Processed with HVCMOS® Technol-
ogy” in the Features section
• Changed the package marking format
• Removed the 44-lead PQFP PG M919 and
44-lead PLCC PJ M903 media types
• Made minor changes throughout the document
2017 Microchip Technology Inc.
DS20005851A-page 15
HV5530
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
XX
PART NO.
Device
-
X
-
X
Package
Options
Environmental
Media Type
a) HV5530PG-G:
32-Channel Serial-to-Parallel
Converter with Open Drain
Outputs, 44-lead PQFP,
96/Tray
Device:
HV5530
=
32-Channel Serial-to-Parallel Converter
with Open Drain Outputs
b) HV5530PJ-G:
32-Channel Serial-to-Parallel
Converter with Open Drain
Outputs, 44-lead PLCC,
27/Tube
Packages:
PG
PJ
=
=
44-lead PQFP
44-lead PLCC
Environmental:
Media Types:
G
=
Lead (Pb)-free/RoHS-compliant Package
(blank)
(blank)
=
=
96/Tray for a PG Package
27/Tube for a PJ Package
DS20005851A-page 16
2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
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Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
CERTIFIEDꢀBYꢀDNVꢀ
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2251-8
== ISO/TSꢀ16949ꢀ==ꢀ
2017 Microchip Technology Inc.
DS20005851A-page 17
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
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EUROPE
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Technical Support:
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Taiwan - Taipei
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Fax: 905-695-2078
DS20005851A-page 18
2017 Microchip Technology Inc.
10/10/17
相关型号：
HV5530PJ-G
EL Driver, 32-Segment, CMOS, PQCC44, 0.653 X 0.653 INCH, 0.180 INCH HEIGHT, 1.27 MM PITCH, GREEN, PLASTIC, LCC-44
SUPERTEX
HV56-040-000.08M
HCMOS Output Clock Oscillator, 0.08MHz Nom, HERMATIC SEALED, METAL, DIP-14/4
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