HV5530X [SUPERTEX]
32-Channel Serial To Parallel Converter With Open Drain Outputs; 32通道串行到并行转换器采用开漏输出
| 型号： | HV5530X |
| 厂家： | 
Supertex, Inc |
| 描述： | 32-Channel Serial To Parallel Converter With Open Drain Outputs |
| 文件： | 总6页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV5522/HV5530
HV5622/HV5630
32-Channel Serial To Parallel Converter
With Open Drain Outputs
Ordering Information
Package Options
Device
Recommended
Operating VPP max
44 J-Lead Quad
Ceramic Chip Carrier Plastic Chip Carrier
44 J-Lead Quad
44 Lead Quad
Plastic Gullwing
Die
HV5522
HV5530
HV5622
HV5630
220V
300V
220V
300V
HV5522DJ
HV5530DJ
HV5622DJ
HV5630DJ
HV5522PJ
HV5530PJ
HV5622PJ
HV5630PJ
HV5522PG
HV5530PG
HV5622PG
HV5630PG
HV5522X
HV5530X
HV5622X
HV5630X
Features
General Description
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Processed with HVCMOS® technology
The HV55 and HV56 are low-voltage serial to high-voltage
parallel converters with open drain outputs. These devices have
been designed for use as drivers for AC-electroluminescent
displays. They can also be used in any application requiring
multiple output high voltage current sinking capabilities such as
drivinginkjetandelectrostaticprintheads,plasmapanels,vacuum
fluorescent, or large matrix LCD displays.
Sink current minimum 100mA
Shift register speed 8MHz
Polarity and Blanking inputs
CMOS compatible inputs
Forward and reverse shifting options
Diode to VPP allows efficient power recovery
44-lead ceramic surface mount package
Hi-Rel processing available
These devices consist of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. Dataisshiftedthroughtheshiftregisteronthehightolow
transition of the clock. The HV55 shifts in the counterclockwise
direction when viewed from the top of the package, and the HV56
shifts in the clockwise direction. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register. Operation of the shift register is not
affected by the LE (latch enable), BL (blanking), or the POL
(polarity)inputs. Transferofdatafromtheshiftregistertothelatch
occurs when the LE (latch enable) input is high. The data in the
latch is stored when LE is low.
Absolute Maximum Ratings
Supply voltage, VDD
1
-0.5V to +15V
1
Output voltage, VPP
HV5530/HV5630
-0.5V to +315V
-0.5V to +230V
-0.5V to VDD + 0.5V
1.5A
HV5522/HV5622
Logic input levels1
Ground current2
Continuous total power dissipation3 Ceramic
Plastic
1500mW
1200mW
Operating temperature range
Ceramic -55°C to +125°C
Plastic -40°C to +85°C
Storage temperature range
-65°C to +150°C
260°C
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
Notes:
1. All voltages are referenced to VSS
.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20°C for plastic and at 15mW/°C for ceramic.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV5522/HV5530/HV5622/HV5630
Electrical Characteristics (over recommended operating conditions unless noted)
DC Characteristics
Symbol
Parameter
Min
Max
Units Conditions
IDD
VDD supply current
15
mA
fCLK = 8MHz
FDATA = 4MHz
IDDQ
Quiescent VDD supply current
Off state output current
100
10
µA
µA
VIN = 0V
IO(OFF)
All outputs high
All SWS parallel
IIH
High-level logic input current
Low-level logic input current
High-level output data out
1
µA
µA
V
VIH = VDD
IIL
-1
VIL = 0V
VOH
VDD - 1.0V
IDout = -100µA
IHVout = +100mA
IDout = +100µA
IOL = -100mA
HVOUT
15.0
1.0
V
VOL
Low-level output voltage
HVOUT clamp voltage
Data out
V
VOC
-1.5
V
AC Characteristics (VDD = 12V, TC = 25°C)
Symbol
fCLK
tW
Parameter
Min
Max
Units Conditions
Clock frequency
8
MHz
ns
Clock width high or low
62
25
10
tSU
Data set-up time before clock falls
Data hold time after clock falls
Turn on time, HVOUT from enable
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
Width of LE pulse
ns
tH
ns
tON
500
100
100
ns
ns
ns
ns
ns
ns
RL = 2KΩ to VPP MAX
tDHL
tDLH
tDLE
tWLE
tSLE
CL = 15pF
CL = 15pF
50
50
50
LE set-up time before clock falls
Recommended Operating Conditions
Symbol
Parameter
Min
Max
13.2
+300
+220
VDD
2.0
Units
V
VDD
Logic supply voltage
High voltage output
10.8
-0.3
HV5530 and HV5630
HV5522 and HV5622
V
HVOUT
-0.3
V
VIH
VIL
fCLK
TA
High-level input voltage
Low-level input voltage
Clock frequency
VDD - 2V
0
V
V
8
MHz
°C
°C
Operating free-air temperature
Plastic
-40
-55
+85
+125
Ceramic
Note:
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD
.
3. Set all inputs to a known state.
Power-down sequence should be the reverse of the above.
2
HV5522/HV5530/HV5622/HV5630
Input and Output Equivalent Circuits
V
V
DD
DD
HV
OUT
Data Out
Input
HV
IN
V
SS
V
V
SS
SS
Logic Data Output
Logic Inputs
High Voltage Outputs
Switching Waveforms
VIH
VIL
VIH
VIL
Data Input
50%
Data Valid
50%
tSU
tH
Clock
50%
50%
50%
50%
tWH
tWL
VOH
VOL
50%
50%
tDLH
Data Out
VOH
VOL
tDHL
VIH
VIL
50%
50%
Latch Enable
tWLE
tSLE
tDLE
VOH
VOL
HVOUT
w/ S/R HIGH
10%
tON
3
HV5522/HV5530/HV5622/HV5630
Functional Block Diagram
Polarity
Blanking
Latch Enable
HVOUT1
Data Input
Clock
Latch
Latch
HVOUT
2
32-Bit
Shift
Register
(Outputs 3 to 30
not shown)
HVOUT31
HVOUT32
Latch
Latch
Data Out
Function Table
Inputs
Outputs
HV Outputs
Function
Shift Reg
Data Out
Data
CLK
LE
BL
POL
1
2…32
*…*
1
2…32
*
All on
X
X
X
X
L
L
L
L
H
L
*
On
On…On
*
*
*
*
*
*
*
*
All off
X
X
*
*…*
Off Off…Off
Invert mode
Load S/R
X
X
H
H
H
H
H
H
*
*…*
*
*
*…*
*…*
*…*
*…*
*…*
*…*
H or L
↓
H or L
H or L
↓
L
H
H
L
H or L *…*
Load
Latches
X
X
L
↑
*
*
*…*
*…*
*…*
*…*
*
↑
*
Transparent
Latch mode
H
H
H
H
L
H
Off
On
H
↓
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion.
* = dependent on previous stage’s state before the last CLK ↓ or last LE high.
4
HV5522/HV5530/HV5622/HV5630
Pin Configurations
Package Outline
HV55
44 Pin J-Lead Package
Pin Function
Pin Function
39 38 37 36 35 34 33 32 31 30 29
1
2
3
4
5
6
7
8
HVOUT 16
HVOUT 17
HVOUT 18
HVOUT 19
HVOUT 20
HVOUT 21
HVOUT 22
HVOUT 23
HVOUT 24
HVOUT 25
HVOUT 26
HVOUT 27
HVOUT 28
HVOUT 29
HVOUT 30
HVOUT 31
HVOUT 32
Data Out
N/C
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Clock
VSS
VDD
28
27
26
25
24
23
22
21
20
19
18
40
41
42
43
44
1
Latch Enable
Data In
Blanking
N/C
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT 10
HVOUT 11
HVOUT 12
HVOUT 13
HVOUT 14
HVOUT 15
1
2
3
4
5
6
7
8
9
2
9
3
10
11
12
13
14
15
16
17
18
19
20
21
22
4
5
6
7
8
9
10 11 12 13 14 15 16 17
top view
44-pin J-Lead Package
N/C
N/C
Polarity
HV56
44 Pin J-Lead Package
Pin Function
Pin Function
1
2
3
4
5
6
7
8
HVOUT 17
HVOUT 16
HVOUT 15
HVOUT 14
HVOUT 13
HVOUT 12
HVOUT 11
HVOUT 10
HVOUT 9
HVOUT 8
HVOUT 7
HVOUT 6
HVOUT 5
HVOUT 4
HVOUT 3
HVOUT 2
HVOUT 1
Data Out
N/C
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Clock
VSS
VDD
Latch Enable
Data In
Blanking
N/C
HVOUT 32
HVOUT 31
HVOUT 30
HVOUT 29
HVOUT 28
HVOUT 27
HVOUT 26
HVOUT 25
HVOUT 24
HVOUT 23
HVOUT 22
HVOUT 21
HVOUT 20
HVOUT 19
HVOUT 18
9
10
11
12
13
14
15
16
17
18
19
20
21
22
N/C
N/C
Polarity
5
HV5522/HV5530/HV5622/HV5630
Pin Configurations
Package Outline
HV55
44-Pin Quad Plastic Gullwing Package
Pin Function
Pin Function
1
2
3
4
5
6
7
8
HVOUT 11
HVOUT 12
HVOUT 13
HVOUT 14
HVOUT 15
HVOUT 16
HVOUT 17
HVOUT 18
HVOUT 19
HVOUT 20
HVOUT 21
HVOUT 22
HVOUT 23
HVOUT 24
HVOUT 25
HVOUT 26
HVOUT 27
HVOUT 28
HVOUT 29
HVOUT 30
HVOUT 31
HVOUT 32
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Data Out
N/C
N/C
N/C
Polarity
Clock
VSS
VDD
Latch Enable
Data In
Blanking
N/C
HVOUT 1
HVOUT 2
HVOUT 3
HVOUT 4
HVOUT 5
HVOUT 6
HVOUT 7
HVOUT 8
HVOUT 9
HVOUT 10
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
9
7
10
11
12
13
14
15
16
17
18
19
20
21
22
8
9
10
11
12 13 14 15
17 18 19 20 21 22
16
top view
44-pin Quad Plastic Gullwing Package
HV56
44-Pin Quad Plastic Gullwing Package
Pin Function
Pin Function
1
2
3
4
5
6
7
8
HVOUT 22
HVOUT 21
HVOUT 20
HVOUT 19
HVOUT 18
HVOUT 17
HVOUT 16
HVOUT 15
HVOUT 14
HVOUT 13
HVOUT 12
HVOUT 11
HVOUT 10
HVOUT 9
HVOUT 8
HVOUT 7
HVOUT 6
HVOUT 5
HVOUT 4
HVOUT 3
HVOUT 2
HVOUT 1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Data Out
N/C
N/C
N/C
Polarity
Clock
VSS
VDD
Latch Enable
Data In
Blanking
N/C
HVOUT 32
HVOUT 31
HVOUT 30
HVOUT 29
HVOUT 28
HVOUT 27
HVOUT 26
HVOUT 25
HVOUT 24
HVOUT 23
9
10
11
12
13
14
15
16
17
18
19
20
21
22
12/13/010
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
6
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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