HV5408PG-B-G [MICROCHIP]
AC PLASMA DISPLAY DRIVER, PQFP44;
| 型号： | HV5408PG-B-G |
| 厂家： | 
MICROCHIP |
| 描述： | AC PLASMA DISPLAY DRIVER, PQFP44 驱动 接口集成电路 |
| 文件： | 总12页 (文件大小：869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
HV5408B
32-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
Features
General Description
► Processed with HVCMOS® technology
► Low power level shifting
The HV5408B is a low voltage serial to high voltage parallel
converter with push-pull outputs. This device has been designed
for use as a driver for AC-electroluminescent displays. It can also
be used in any application requiring multiple output high voltage
current sourcing and sinking capabilities, such as driving plasma
panels, vacuum fluorescent, or large matrix LCD displays.
► SOURCE/SINK current minimum 20mA
► Shift register speed 8.0MHz
► Latched data outputs
► CMOS compatible inputs
► Forward and reverse shifting options
► Diode to VPP allows efficient power recovery
The HV5408B consists of a 32-bit shift register, 32 latches, and
control logic to enable outputs. Q1 is connected to the first stage
of the shift register through the Output Enable logic. Data is shifted
through the shift register on the low to high transition of the clock.
When viewed from the top of the package, the HV5408B shifts in
the counter-clockwise direction. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register (32). Operation of the shift register
is not affected by the LE (latch enable) or the OE (output enable)
inputs. Transfer of data from the shift register to the latch occurs
when the LE input is high. The data in the latch is retained when
LE is low.
Typical Application Circuit
VPP
VDD
DATA
INPUT
HVOUT
1
Columns
CLK
High Voltage
Low Voltage
LE
Level
Translators
&
Micro
Processor
Shift Register
OE
Latches
Row
Push-Pull
Output
Buffers
Output Contr.
Driver
DATA
OUT
HVOUT32
Display
Panel
Supertex HV5408B
Data Input for cascading the next HV5408B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV5408B
Ordering Information
Package Options
44-Lead PQFP
10.00x10.00mm body
2.35mm height (max)
0.80mm pitch
44-Lead
44-Lead PLCC
Quad Cerpac
Device
.653x.653in body
.180in height (max)
.050in pitch
.650x.650in body
.190in height (max)
.050in pitch
HV5408B
HV5408DJ-B*
HV5408PG-B-G
HV5408PJ-B-G
-G indicates package is RoHS compliant (‘Green’).
Hi-Rel process flow available.
*
Pin Configurations
6
40
1 44
Absolute Maximum Ratings
Parameter
Value
-0.5V to +16V
-0.5V to +90V
-0.5V to VDD +0.5V
1.5A
Supply voltage, VDD
Supply voltage, VPP
Logic input levels
Ground current1
44-Lead Quad Cerpac (DJ)
(top view)
Continuous total power dissipation2
Plastic
Ceramic
1200mW
1500mW
Operating temperature range
Plastic
Ceramic
-40OC to +85OC
-55OC to +125OC
-65OC to +150OC
44
Storage temperature range
1
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
44-Lead PQFP (PG)
(top view)
6
40
1 44
Notes:
1. Duty cycle is limited by the total power dissipated in the package.
2. For operation above 25°C ambient derate linearly to maximum
operating temperature at 20mW/°C for plastic and at 15mW/°C for
ceramic.
44-Lead PLCC (PJ)
(top view)
Product Marking
Top Marking
Top Marking
Top Marking
YY = Year Sealed
YYWW
HV5408PG-B
LLLLLLLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
YYWW AAA
HV5408PJ-B
LLLLLLLLLL
YYWW
WW = Week Sealed
L = Lot Number
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
*May be part of top marking
HV5408DJ-B
LLLLLLLLLL
A = Assembler ID
C = Country of Origin*
Bottom Marking
Bottom Marking
C = Country of Origin*
A = Assembler ID*
Bottom Marking
= “Green” Packaging
CCCCCCCCCCC
AAA
CCCCCCCCCCC
CCCCCCCC
AAA
= “Green” Packaging
*May be part of top marking
*May be part of top marking
44-Lead PQFP
(PG)
44-Lead Quad Cerpac
(DJ)
44-Lead PLCC
(PJ)
Packages may or may not include the following marks: Si or
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
2
HV5408B
Recommended Operating Conditions (over -40°C to 85°C for plastic and -55°C to 125°C for ceramic)
Sym
VDD
VPP
VIH
Parameter
Min
10.8
8.0
Max
13.2
80
Units
Logic voltage supply
High voltage supply
Input high voltage
Input low voltage
Clock frequency
V
V
VDD - 2.0
0
VDD
2.0
V
VIL
V
fCLK
0
8.0
MHz
Power-Up Sequence
Power-up sequence should be the following:
1. Connect ground
2. Apply VDD
3. Set all inputs (Data, CLK, LE, etc.) to a known state
4. Apply VPP
5. The VPP should not fall below VDD or float during operation.
Power-down sequence should be the reverse of the above.
Electrical Characteristics (VPP = 60V, VDD = 12V, TA = 25°C)
DC Characteristics
Sym
Parameter
Min
Max Units Conditions
IPP
VPP supply current
-
0.5
100
15
-
mA HVOUTPUTS high to low
µA All inputs = VDD or GND
mA VDD = VDD max, fCLK = 8.0MHz
IDDQ
IDD
IDD supply current (quiescent)
IDD supply current (operating)
-
-
VOH (data) Shift register output voltage
VOL (data) Shift register output voltage
10.5
V
V
IO = -100µA
-
-
1.0
1.0
-1.0
-1.5
-
IO = 100µA
IIH
Current leakage, any input
Current leakage, any input
HV output clamp diode voltage
HV output when sourcing
HV output when sinking
HV output when sourcing
HV output when sinking
µA
µA
V
VIN = VDD
IIL
-
VIN = 0
VOC
VOH
VOL
VOH
VOL
-
IOL = -100mA
52
-
V
IOH = -20mA, -40 to 85°C
IOL = 20mA, -40 to 85°C
IOH = -15mA, -55 to 125°C
IOL = 15mA, -55 to 125°C
8.0
-
V
52
-
V
8.0
V
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
3
HV5408B
AC Characteristics
Sym
Parameter
Min
-
Max Units Conditions
fCLK
Clock frequency
8.0
MHz ---
tWL or tWH Clock width, HIGH or LOW
62
25
10
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
---
tSU
tH
Setup time before CLK rises
Hold time after CLK rises
-
-
---
---
tDLH (data) Data output delay after L to H CLK
tDHL (data) Data output delay after H to L CLK
110
110
-
CL = 15pF
-
CL = 15pF
tDLE
tWLE
tSLE
tON
LE delay after L to H CLK
Width of LE pulse
50
50
50
-
---
---
---
---
---
-
LE setup time before L to H CLK
Delay from LE to HVOUT, L to H
Delay from LE to HVOUT, H to L
-
500
500
tOFF
-
Switching Waveforms
VIH
VIL
DATA
50%
50%
Data Valid
50%
IN
tSU
tH
VIH
50%
50%
50%
CLK
VIL
tWL
tWH
VOH
VOL
50%
50%
tDLH
DATA
OUT
VOH
VOL
tDHL
VIH
VIL
50%
50%
LE
tWLE
tSLE
tDLE
VOH
VOL
90%
10%
HVOUT
w/ S/R LOW
tOFF
VOH
VOL
90%
HVOUT
w/ S/R HIGH
10%
tON
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
4
HV5408B
Input and Output Equivalent Circuits
VDD
VDD
VPP
DATA
INPUT
DATA OUT
HVOUT
GND
GND
GND
Logic Data Output
Logic Inputs
High Voltage Outputs
Functional Block Diagram
VPP
OE
LE
DATA
INPUT
HVOUT1
CLK
HVOUT
2
•
•
•
32 bit
32 bit
Latches
Static
28 Additional
Register
Outputs
•
•
•
HVOUT31
DATA
OUT
HVOUT32
Function Tables
DATA INPUT
LE
X
OE
HV OUT
DATA INPUT
CLK*
DATA OUT
H
L
H
L
X
X
H
L
L
H
H
H
All HVOUT = LOW
L
Previous latched data
X
No
No change
H
H
H
L
Note:
*
= LOW - to - HIGH transition
H = High
L = Low
X = Don’t Care
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
HV5408B
44-Lead PQFP Pin Assignment (PG)
Pin
Function
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
High voltage outputs.
High voltage push-pull outputs, which, depending on controlling low voltage data,
can drive loads either to GND, or to VPP rail levels.
Serial data output.
23
DATA OUT
Data output for cascading to the data input of the next device.
24
25
26
N/C
No connect.
Data shift register clock
27
CLK
Input are shifted into the shift register on the positive edge of the clock.
Logic and high voltage ground.
28
29
30
GND
VPP
VDD
High voltage power rail.
Low voltage logic power rail.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
6
HV5408B
44-Lead PQFP Pin Assignment (PG)
Pin
Function
Description
Latch enable input.
31
LE
When LE is HIGH, shift register data is transferred into a data latch. When LE is
LOW, data is latched, and new data can be clocked into the shift register.
Serial data input.
32
33
DATA IN
OE
Data needs to be present before each rising edge of the clock.
Output enable input.
When OE is LOW, all HV outputs are forced into a LOW state, regardless of data
in each channel. When OE is HIGH, all HV outputs reflect data latched.
34
35
36
37
38
39
40
41
42
43
44
N/C
No connect.
HVOUT1
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
2
3
4
5
6
7
8
9
High voltage outputs.
High voltage push-pull outputs, which, depending on controlling low voltage data,
can drive loads either to GND, or to VPP rail levels.
HVOUT10
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
7
HV5408B
44-Lead Quad Cerpac/PLCC Pin Assignment (DJ/PJ)
Pin
Function
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
Description
1
2
3
4
5
6
7
8
High voltage outputs.
9
High voltage push-pull outputs, which, depending on controlling low voltage data,
can drive loads either to GND, or to VPP rail levels.
10
11
12
13
14
15
16
17
Serial data output.
18
DATA OUT
Data output for cascading to the data input of the next device.
19
20
21
N/C
No connect.
Data shift register clock
22
CLK
Input are shifted into the shift register on the positive edge of the clock.
Logic and high voltage ground.
23
24
25
GND
VPP
VDD
High voltage power rail.
Low voltage logic power rail.
Latch enable input.
26
27
LE
When LE is HIGH, shift register data is transferred into a data latch. When LE is
LOW, data is latched, and new data can be clocked into the shift register.
Serial data input.
DATA IN
Data needs to be present before each rising edge of the clock.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
8
HV5408B
44-Lead Quad Cerpac/PLCC Pin Assignment (DJ/PJ)
Pin
Function
Description
Output enable input.
28
OE
When OE is LOW, all HV outputs are forced into a LOW state, regardless of data
in each channel. When OE is HIGH, all HV outputs reflect data latched.
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
N/C
No connect.
HVOUT1
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
2
3
4
5
6
7
8
9
High voltage outputs.
High voltage push-pull outputs, which, depending on controlling low voltage data,
can drive loads either to GND, or to VPP rail levels.
HVOUT10
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
9
HV5408B
44-Lead Quad Cerpac Package Outline (DJ)
.650x.650in body, .190in height (max), .050in pitch
D
D1
1
.040 x 45O
O
.035 x 45
6
44
40
.150 MAX
Note 1
(Index Area)
.075 MAX
E1
E
0.25 max
3 Places
Top View
Vertical Side View
View B
b1
.025 MIN
A
A2
Seating
Plane
e
A1
b
Horizontal Side View
View B
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
A
A1
A2
b
b1
D
D1
E
E1
e
MIN
NOM
MAX
.155
.172
.190
.090
.100
.120
.017
.019
.021
.026
.029
.032
.685
.690
.695
.630
.650
.665
.685
.690
.695
.630
.650
.665
Dimension
(inches)
.060
REF
.050
BSC
JEDEC Registration MO-087, Variation AB, Issue B, August, 1991.
Drawings not to scale.
Supertex Doc. #: DSPD-44CERPACDJ, Version D090808.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
10
HV5408B
44-Lead PQFP Package Outline (PG)
10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch
D
D1
E
E1
Note 1
(Index Area
D1/4 x E1/4)
44
1
b
e
Top View
View B
Gauge
L2
A2
A1
Plane
A
Seating
Plane
L
Seating
Plane
θ
L1
Side View
View B
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
A
A1
MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80*
NOM 2.00 13.90 10.00 13.90 10.00
MAX 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20*
A2
b
D
D1
E
E1
e
L
L1
L2
θ
0O
0.73
0.88
1.03
Dimension
(mm)
0.80
BSC
1.95 0.25
REF BSC
-
-
-
3.5O
7O
JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.
* This dimension is not specified in the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PQFPPG, Version C041309.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
11
HV5408B
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
.048/.042 x 45O
D
D1
1
O
.056/.042 x 45
6
44
40
.150 MAX
Note 1
(Index Area)
.075 MAX
E1
E
Note 2
.020max
(3 Places)
Top View
Vertical Side View
View B
b1
.020 MIN
Base
Plane
A
A2
Seating
Plane
e
A1
b
R
Horizontal Side View
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Actual shape of this feature may vary.
Symbol
A
A1
A2
.062
-
b
.013
-
b1
.026
-
D
D1
E
E1
e
R
MIN
.165
.172
.180
.090
.105
.120
.685
.690
.695
.650
.653
.656
.685
.690
.695
.650
.653
.656
.025
.035
.045
Dimension
(inches)
.050
BSC
NOM
MAX
.083
.021
.036†
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PLCCPJ, Version F031111.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.
supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2011 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-HV5408B
A042811
12
相关型号：
HV5408PJ-B-G
AC Plasma Driver, 32-Segment, CMOS, PQCC44, 0.653 X 0.653 INCH, 0.180 INCH HEIGHT, 0.050 INCH PITCH, GREEN, PLASTIC, MS-018AC, LCC-44
SUPERTEX
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