HV5408X [SUPERTEX]
32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs; 32通道串行到并行转换高压推挽输出
| 型号： | HV5408X |
| 厂家： | 
Supertex, Inc |
| 描述： | 32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs |
| 文件： | 总6页 (文件大小：461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV5308
HV5408
32-Channel Serial To Parallel Converter
With High Voltage Push-Pull Outputs
Ordering Information
Package Options
Device
44 J-Lead Quad
44 J-Lead Quad
44 Lead Quad
44 J-Lead Quad
Ceramic Chip Carrier
Plastic Chip Carrier
Plastic Gullwing
Die
Ceramic Chip Carrier
(MIL-STD-883 Processed*)
HV5308
HV5408
HV5308DJ
HV5408DJ
HV5308PJ
HV5408PJ
HV5308PG
HV5408PG
HV5308X
HV5408X
RBHV5308DJ
RBHV5408DJ
* For Hi-Rel process flows, please refer to perfer to page 5-3 in the Databook.
Features
General Description
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Processed with HVCMOS® technology
The HV53 and HV54 are low voltage serial to high voltage
parallel converters with push-pull outputs. These devices have
been designed for use as drivers for AC-electroluminescent
displays. They can also be used in any application requiring
multiple output high voltage current sourcing and sinking capa-
bilities such as driving plasma panels, vacuum fluorescent, or
large matrix LCD displays.
Low power level shifting
Source/sink current minimum 20mA
Shift register speed 8MHz
Latched data outputs
CMOS compatible inputs
These devices consist of a 32-bit shift register, 32 latches, and
control logic to enable outputs. Q1 is connected to the first stage
of the shift register through the Output Enable logic. Data is
shifted through the shift register on the low to high transition of
the clock. The HV54 shifts in the counterclockwise direction
when viewed from the top of the package and the HV53 shifts in
the clockwise direction. A data output buffer is provided for
cascading devices. This output reflects the current status of the
last bit of the shift register (32). Operation of the shift register is
not affected by the LE (latch enable) or the OE (output enable)
inputs. Transfer of data from the shift register to the latch occurs
when the LE input is high. The data in the latch is retained when
LE is low.
Forward and reverse shifting options
Diode to VPP allows efficient power recovery
Absolute Maximum Ratings1
Supply voltage, VDD
Supply voltage, VPP
Logic input levels2
Ground current3
2
-0.5V to +16V
-0.5V to +90V
-0.5 to VDD + 0.5V
1.5A
Continuous total power dissipation4 Plastic
Ceramic
1200mW
1500mW
Operating temperature range
Plastic -40°C to +85°C
Ceramic -55°C to 125°C
Storage temperature range
-65°C to +150°C
260°C
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
Notes:
1. Device will survive (but operation may not be specified or guaranteed) at
these extremes.
2. All voltages are referenced to GND.
3. Duty cycle is limited by the total power dissipated in the package.
4. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C for plastic and at 15mW/°C for ceramic.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV5308/HV5408
Electrical Characteristics (VPP = 60V, VDD = 12V, TA =25°C)
DC Characteristics
Symbol
Parameter
Min
Max
0.5
100
15
Units
mA
Conditions
IPP
VPP Supply Current
HVoutputs HIGH to LOW
All inputs = VDD or GND
IDDQ
IDD
IDD Supply Current (Quiescent)
IDD Supply Current (Operating)
µA
mA
VDD = VDD max,
fCLK = 8 MHz
V
OH (Data)
OL (Data)
Shift Register Output Voltage
Shift Register Output Voltage
Current Leakage, any input
Current Leakage, any input
HV Output Clamp Diode Voltage
HV Output when Sourcing
HV Output when Sinking
10.5
V
V
IO = 100µA
V
1
1
IO = 100µA
IIH
µA
µA
V
VIN = VDD
IIL
-1
VIN = 0
VOC
VOH
VOL
VOH
VOL
-1.5
IOL = -100mA
52
52
V
IOH = -20mA, -40 to 85°C
IOL = 20mA, -40 to 85°C
IOH = -15mA, -55 to 125°C
IOL = 15mA, -55 to 125°C
8
8
V
HV Output when Sourcing
HV Output when Sinking
V
V
AC Characteristics
Symbol
Parameter
Min
Max
Units
MHz
ns
Conditions
fCLK
Clock Frequency
8
t
WL or tWH
tSU
tH
DLH (Data)
Clock width, HIGH or LOW
Setup time before CLK rises
Hold time after CLK rises
Data Output Delay after L to H CLK
Data Output Delay after H to L CLK
LE Delay after L to H CLK
Width of LE Pulse
62
25
10
ns
ns
t
110
110
ns
CL = 15pF
CL = 15pF
tDHL (Data)
tDLE
ns
50
50
50
ns
tWLE
ns
tSLE
LE Setup Time before L to H CLK
Delay from LE to HVOUT, L to H
Delay from LE to HVOUT, H to L
ns
tON
500
500
ns
tOFF
ns
Recommended Operating Conditions
(over -40 to 85°C for plastic and -55°C to 125°C for ceramic)
Symbol
VDD
Parameter
Min
10.8
8.0
VDD-2
0
Max
13.2
80
Units
Logic Voltage Supply
High Voltage Supply
Input HIGH Voltage
Input LOW Voltage
Clock Frequency
V
V
VPP
VIH
VDD
2
V
VIL
V
fCLK
0
8
MHz
Note:
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD
3. Set all inputs (Data, CLK, LE, etc.) to a known state.
4. Apply VPP
.
.
5. The VPP should not fall below VDD or float during operation.
Power-down sequence should be the reverse of the above.
2
HV5308/HV5408
Input and Output Equivalent Circuits
V
DD
V
DD
V
PP
Data Out
HV
OUT
Input
GND
GND
GND
Logic Data Output
Logic Inputs
High Voltage Outputs
Switching Waveforms
VIH
VIL
VIH
VIL
Data Input
Clock
50%
Data Valid
tH
50%
tSU
50%
50%
50%
50%
tWL
tWH
VOH
VOL
50%
tDLH
Data Out
VOH
VOL
50%
tDHL
VIH
50%
50%
Latch Enable
VOL
tWLE
tSLE
tDLE
VOH
VOL
90%
10%
Q
w/ S/R LOW
tOFF
VOH
VOL
Q
90%
10%
tON
w/ S/R HIGH
3
HV5308/HV5408
Functional Block Diagram
VPP
Output Enable
Latch Enable
Data Input
Clock
HVOUT
1
2
HVOUT
•
•
•
32 Bit
Shift
Register
32
Latches
32 Outputs Total
•
•
•
HVOUT31
Data Out
HVOUT32
Function Tables
Data Input
CLK*
Data Output
H
L
H
L
X
No
No Change
*
= LOW-to-HIGH level transition
Data Input
LE
X
OE
L
HV Output
X
X
H
L
All HVOUT = LOW
L
H
Previous Latched Data
H
H
H
H
L
H
4
HV5308/HV5408
Pin Configuration
Package Outline
HV53
44 Pin J-Lead Package
39 38 37 36 35 34 33 32 31 30 29
28
27
26
25
24
23
22
21
20
19
18
Pin Function
Pin Function
40
41
42
43
44
1
1
2
3
4
5
6
7
8
HVOUT 17
HVOUT 16
HVOUT 15
HVOUT 14
HVOUT 13
HVOUT 12
HVOUT 11
HVOUT 10
HVOUT 9
HVOUT 8
HVOUT 7
HVOUT 6
HVOUT 5
HVOUT 4
HVOUT 3
HVOUT 2
HVOUT 1
Data Out
N/C
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
GND
VPP
VDD
Latch Enable
Data In
Output Enable
N/C
2
3
HVOUT 32
HVOUT 31
HVOUT 30
HVOUT 29
HVOUT 28
HVOUT 27
HVOUT 26
HVOUT 25
HVOUT 24
HVOUT 23
HVOUT 22
HVOUT 21
HVOUT 20
HVOUT 19
HVOUT 18
4
9
5
10
11
12
13
14
15
16
17
18
19
20
21
22
6
7
8
9
10 11 12 13 14 15 16 17
top view
44-pin J-Lead Package
N/C
N/C
Clock
HV54
44 Pin J-Lead Package
Pin Function
Pin Function
1
2
3
4
5
6
7
8
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
Data Out
N/C
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
GND
VPP
VDD
Latch Enable
Data In
Output Enable
N/C
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT10
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
1
2
3
4
5
6
7
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
N/C
N/C
Clock
5
HV5308/HV5408
Pin Configuration
Package Outline
HV53
44 Pin Quad Plastic Gullwing Package
Pin Function
Pin Function
1
2
3
4
5
6
7
8
HVOUT 22
HVOUT 21
HVOUT 20
HVOUT 19
HVOUT 18
HVOUT 17
HVOUT 16
HVOUT 15
HVOUT 14
HVOUT 13
HVOUT 12
HVOUT 11
HVOUT 10
HVOUT 9
HVOUT 8
HVOUT 7
HVOUT 6
HVOUT 5
HVOUT 4
HVOUT 3
HVOUT 2
HVOUT 1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Data Out
N/C
N/C
N/C
Clock
GND
VPP
VDD
Latch Enable
Data In
Output Enable
N/C
HVOUT 32
HVOUT 31
HVOUT 30
HVOUT 29
HVOUT 28
HVOUT 27
HVOUT 26
HVOUT 25
HVOUT 24
HVOUT 23
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
9
7
10
11
12
13
14
15
16
17
18
19
20
21
22
8
9
10
11
12 13 14 15
17 18 19 20 21 22
16
top view
44-pin Quad Plastic Gullwing Package
HV54
44 Pin Quad Plastic Gullwing Package
Pin Function Pin Function
1
2
3
4
5
6
7
8
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Data Out
N/C
N/C
N/C
Clock
GND
VPP
VDD
Latch Enable
Data In
Output Enable
N/C
9
10
11
12
13
14
15
16
17
18
19
20
21
22
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
1
2
3
4
5
6
7
8
9
HVOUT10
12/13/010
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
6
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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