ATXMEGA32D3-MN_技术文档

8/16-bit Atmel AVR XMEGA D3 Microcontroller

ATxmega32D3 / ATxmega64D3 / ATxmega128D3 /

ATxmega192D3 / ATxmega256D3 / ATxmega384D3

Features



High-performance, low-power Atmel^®AVR^®XMEGA^®8/16-bit Microcontroller

Nonvolatile program and data memories

 32K - 384KBytes of in-system self-programmable flash

 4K - 8KBytes boot section

 1K - 4KBytes EEPROM

 4K - 32KBytes internal SRAM



Peripheral features

 Four-channel event system

 Five 16-bit timer/counters



Four timer/counters with four output compare or input capture channels

One timer/counter with two output compare or input capture channels

High resolution extension on two timer/counters

Advanced waveform extension (AWeX) on one timer/counter

 Three USARTs with IrDA support for one USART

 Two two-wire interfaces with dual address match (I²C and SMBus compatible)

 Two serial peripheral interfaces (SPIs)

 CRC-16 (CRC-CCITT) and CRC-32 (IEEE^®802.3) generator

 16-bit real time counter (RTC) with separate oscillator

 One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter

 Two Analog Comparators with window compare function, and current sources

 External interrupts on all general purpose I/O pins

 Programmable watchdog timer with separate on-chip ultra low power oscillator

 Atmel QTouch^®library support



Capacitive touch buttons, sliders and wheels



Special microcontroller features

 Power-on reset and programmable brown-out detection

 Internal and external clock options with PLL and prescaler

 Programmable multilevel interrupt controller

 Five sleep modes

 Programming and debug interface



PDI (program and debug interface)

I/O and packages

 50 programmable I/O pins

 64-lead TQFP

 64-pad QFN



Operating voltage

 1.6 – 3.6V

Operating frequency

 0 – 12MHz from 1.6V

 0 – 32MHz from 2.7V

Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

1.

Ordering Information

EEPROM

[bytes]

SRAM

[bytes]

Power

supply

Package

(1)(2)(3)

Ordering code

ATxmega32D3-AU

Flash [bytes]

32K + 4K

Speed [MHz]

Temp.

1K

2K

4K

1K

2K

4K

ATxmega32D3-AUR ⁽⁴⁾

ATxmega64D3-AU

32K + 4K

64K + 4K

4K

ATxmega64D3-AUR ⁽⁴⁾

ATxmega128D3-AU

64K + 4K

4K

128K + 8K

192K + 8K

256K + 8K

384K + 8K

32K + 4K

8K

ATxmega128D3-AUR ⁽⁴⁾

ATxmega192D3-AU

8K

64A

16K

32K

4K

ATxmega192D3-AUR ⁽⁴⁾

ATxmega256D3-AU

ATxmega256D3-AUR ⁽⁴⁾

ATxmega384D3-AU

ATxmega384D3-AUR ⁽⁴⁾

ATxmega32D3-MH

32

1.6 - 3.6V

-40C - 85C

ATxmega32D3-MHR ⁽⁴⁾

ATxmega64D3-MH

32K + 4K

4K

64K + 4K

4K

ATxmega64D3-MHR ⁽⁴⁾

ATxmega128D3-MH

ATxmega128D3-MHR ⁽⁴⁾

ATxmega192D3-MH

ATxmega192D3-MHR ⁽⁴⁾

ATxmega256D3-MH

ATxmega256D3-MHR ⁽⁴⁾

ATxmega384D3-MH

ATxmega384D3-MHR ⁽⁴⁾

64K + 4K

4K

128K + 8K

192K + 8K

256K + 8K

384K + 8K

8K

64M

16K

32K

XMEGA D3 [DATASHEET]

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2

EEPROM

[bytes]

SRAM

[bytes]

Power

supply

Package

(1)(2)(3)

Ordering code

Flash [bytes]

32K + 4K

Speed [MHz]

Temp.

ATxmega32D3-AN

1K

2K

4K

1K

2K

4K

ATxmega32D3-ANR ⁽⁴⁾

ATxmega64D3-AN

32K + 4K

64K + 4K

4K

ATxmega64D3-ANR ⁽⁴⁾

ATxmega128D3-AN

ATxmega128D3-ANR ⁽⁴⁾

ATxmega192D3-AN

ATxmega192D3-ANR ⁽⁴⁾

ATxmega256D3-AN

ATxmega256D3-ANR ⁽⁴⁾

ATxmega384D3-AN

ATxmega384D3-ANR ⁽⁴⁾

ATxmega32D3-MN

64K + 4K

4K

128K + 8K

192K + 8K

256K + 8K

384K + 8K

32K + 4K

8K

64A

16K

32K

4K

32

1.6 - 3.6V

-40C - 105C

ATxmega32D3-MNR ⁽⁴⁾

ATxmega64D3-MN

32K + 4K

4K

64K + 4K

4K

ATxmega64D3-MNR ⁽⁴⁾

ATxmega128D3-MN

ATxmega128D3-MNR ⁽⁴⁾

ATxmega192D3-MN

ATxmega192D3-MNR ⁽⁴⁾

ATxmega256D3-MN

ATxmega256D3-MNR ⁽⁴⁾

ATxmega384D3-MN

ATxmega384D3-MNR ⁽⁴⁾

64K + 4K

4K

128K + 8K

192K + 8K

256K + 8K

384K + 8K

8K

64M

16K

32K

Notes:

1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

3. For packaging information, see “Packaging Information” on page 61.

4. Tape and Reel.

XMEGA D3 [DATASHEET]

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Package type

64-lead, 14 * 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)

64-pad, 9 * 9 * 1.0mm body, lead pitch 0.50mm, 7.65mm exposed pad, quad flat no-lead package (QFN)

64A

64M

Typical applications

Industrial control

Climate control

RF and ZigBee^®

Motor control

Sensor control

Optical

Low power battery applications

Power tools

Factory automation

Building control

HVAC

Board control

Utility metering

White goods

Medical applications

XMEGA D3 [DATASHEET]

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2.

Pinout/block Diagram

Figure 2-1. Block Diagram and Pinout

Power

Programming, debug, test

Ground

Digital function

Analog function/Oscillators

External clock/Crystal pins

General Purpose I /O

Port R

XOSC

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

GND

VCC

PC0

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PF2

PF1

PF0

VCC

GND

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

VCC

GND

PD7

DATA BUS

3

OSC/CLK

Control

Internal

oscillators

Watchdog

oscillator

Power

Supervision

4

AREF

Sleep

Controller

Real Time

Counter

Watchdog

Timer

Reset

Controller

ADC

5

AC0:1

Event System

Controller

Prog/Debug

Interface

6

CRC

OCD

7

Interrupt

Controller

BUS

matrix

8

AREF

Internal

references

CPU

9

SRAM

10

11

12

13

14

15

16

FLASH

EEPROM

DATA BUS

EVENT ROUTING NETWORK

Port C

Port D

Port E

Port F

Notes: 1. For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 50.

2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good

mechanical stability.

XMEGA D3 [DATASHEET]

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3.

Overview

The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based

on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices

achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system

designer to optimize power consumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly

connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,

executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times

faster than conventional single-accumulator or CISC based microcontrollers.

The XMEGA D3 devices provide the following features: in-system programmable flash with read-while-write capabilities;

internal EEPROM and SRAM; four-channel event system and programmable multilevel interrupt controller, 50 general

purpose I/O lines, 16-bit real-time counter (RTC); five, 16-bit timer/counters with compare and PWM channels; three

USARTs; two two-wire serial interfaces (TWIs); two serial peripheral interfaces (SPIs); one sixteen-channel, 12-bit ADC

with programmable gain; two analog comparators (ACs) with window mode; programmable watchdog timer with separate

internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection.

The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.

The AVR XMEGA devices have five software selectable power saving modes. The idle mode stops the CPU while

allowing the SRAM, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode

saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, or pin-

change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the

application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal

oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal,

combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer

continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be

stopped in active mode and idle sleep mode.

Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR

microcontrollers.

The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can

be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to download the

application program to the flash memory. The boot loader software in the boot flash section will continue to run while the

application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with

in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible

and cost effective solution for many embedded applications.

All AVR XMEGA devices are supported with a full suite of program and system development tools, including: C

compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.

XMEGA D3 [DATASHEET]

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3.1

Block Diagram

Figure 3-1. XMEGA D3 Block Diagram

PR[0..1]

XTAL1

Power

Ground

Digital function

Analog function/Oscillators

Programming, debug,

External clock/Crystal pins

General Purpose I /O

XTAL2

Oscillator

Circuits/

Clock

Real Time

Counter

Watchdog

Oscillator

PORT R (2)

Generation

DATA BUS

Watchdog

Timer

ACA

Event System

Controller

Oscillator

Control

Sleep

Controller

VCC

GND

Power

Supervision

POR/BOD &

RESET

PA[0..7]

PORT A (8)

ADCA

SRAM

BUS Matrix

AREFA

VCC/10

Int. Refs.

Tempref

AREFB

RESET/

Interrupt

Prog/Debug

Controller

PDI_CLK

PDI

Controller

PDI_DATA

CPU

CRC

OCD

NVM Controller

PB[0..7]

PORT B (8)

TCF0

PF[0..7]

Flash

EEPROM

DATA BUS

EVENT ROUTING NETWORK

To Clock

Generator

PORT C (8)

PORT D (8)

PORT E (8)

TOSC1

TOSC2

PC[0..7]

PD[0..7]

PE[0..7]

XMEGA D3 [DATASHEET]

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4.

Resources

A comprehensive set of development tools, application notes and datasheets are available for download on

www.atmel.com/avr.

4.1

Recommended Reading



Atmel AVR XMEGA D manual



XMEGA application notes

This device data sheet only contains part specific information with a short description of each peripheral and module. The

XMEGA D manual describes the modules and peripherals in depth. The XMEGA application notes contain example code

and show applied use of the modules and peripherals.

All documentation are available from www.atmel.com/avr.

5.

Capacitive Touch Sensing

The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR

microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced

reporting of touch keys and includes Adjacent Key Suppression^™(AKS^™) technology for unambiguous detection of key

events. The QTouch library includes support for the QTouch and Atmel QMatrix acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR

microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the

touch sensing API’s to retrieve the channel information and determine the touch sensor states.

The QTouch library is FREE and downloadable from the Atmel website at the following location:

http://www.atmel.com/tools/qtouchlibrary.aspx. For implementation details and other information, refer to the QTouch

library user guide - also available for download from the Atmel website.

XMEGA D3 [DATASHEET]

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6.

AVR CPU

6.1

Features

 8/16-bit, high-performance Atmel AVR RISC CPU

 137 instructions

 Hardware multiplier

 32x8-bit registers directly connected to the ALU

 Stack in RAM

 Stack pointer accessible in I/O memory space

 Direct addressing of up to 16MB of program memory and 16MB of data memory

 True 16/24-bit access to 16/24-bit I/O registers

 Efficient support for 8-, 16-, and 32-bit arithmetic

 Configuration change protection of system-critical features

6.2

6.3

Overview

All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and

perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the

program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable

Multilevel Interrupt Controller” on page 28.

Architectural Overview

In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories

and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one

instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to

be executed on every clock cycle. For details of all AVR instructions, refer to www.atmel.com/avr.

XMEGA D3 [DATASHEET]

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Figure 6-1. Block Diagram of the AVR CPU Architecture

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a

register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is

updated to reflect information about the result of the operation.

The ALU is directly connected to the fast-access register file. The 32 * 8-bit general purpose working registers all have

single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a

register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data

space addressing, enabling efficient address calculations.

The memory spaces are linear. The data memory space and the program memory space are two different memory

spaces.

The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be

memory mapped in the data memory.

All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O

memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.

The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as

data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.

The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different

addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.

Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.

The program memory is divided in two sections, the application program section and the boot program section. Both

sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-

programming of the application flash memory must reside in the boot program section. The application section contains

an application table section with separate lock bits for write and read/write protection. The application table section can

be used for safe storing of nonvolatile data in the program memory.

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6.4

ALU - Arithmetic Logic Unit

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a

register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general

purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register

and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the

status register is updated to reflect information about the result of the operation.

ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit

arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware

multiplier supports signed and unsigned multiplication and fractional format.

6.4.1 Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different

variations of signed and unsigned integer and fractional numbers:



Multiplication of unsigned integers

Multiplication of signed integers

Multiplication of a signed integer with an unsigned integer

Multiplication of unsigned fractional numbers

Multiplication of signed fractional numbers

Multiplication of a signed fractional number with an unsigned one

A multiplication takes two CPU clock cycles.

6.5

Program Flow

After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program

counter (PC) addresses the next instruction to be fetched.

Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole

address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general

data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After

reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the

I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be

accessed through the five different addressing modes supported in the AVR CPU.

6.6

Status Register

The status register (SREG) contains information about the result of the most recently executed arithmetic or logic

instruction. This information can be used for altering program flow in order to perform conditional operations. Note that

the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many

cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine nor restored when returning from an

interrupt. This must be handled by software.

The status register is accessible in the I/O memory space.

6.7

Stack and Stack Pointer

The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing

temporary data. The Stack Pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit

registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and

POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing

data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded

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after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point

above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.

During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be

two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program

memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices

with more than 128KB of program memory, the return address is three bytes, and hence the SP is

decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the

RETI instruction, and from subroutine calls using the RET instruction.

The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one

when data is popped off the stack using the POP instruction.

To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts

for up to four instructions or until the next I/O memory write.

After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 16.

6.8

Register File

The register file consists of 32 * 8-bit general purpose working registers with single clock cycle access time. The register

file supports the following input/output schemes:



One 8-bit output operand and one 8-bit result input

Two 8-bit output operands and one 8-bit result input

Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input

Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient

address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash

program memory.

XMEGA D3 [DATASHEET]

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7.

Memories

7.1

Features

 Flash program memory

 One linear address space

 In-system programmable

 Self-programming and boot loader support

 Application section for application code

 Application table section for application code or data storage

 Boot section for application code or boot loader code

 Separate read/write protection lock bits for all sections

 Built in fast CRC check of a selectable flash program memory section

 Data memory

 One linear address space

 Single-cycle access from CPU

 SRAM

 EEPROM



Byte and page accessible



Optional memory mapping for direct load and store

 I/O memory



Configuration and status registers for all peripherals and modules

Four bit-accessible general purpose registers for global variables or flags



 Production signature row memory for factory programmed data

 ID for each microcontroller device type

 Serial number for each device

 Calibration bytes for factory calibrated peripherals

 User signature row

 One flash page in size

 Can be read and written from software

 Content is kept after chip erase

7.2

Overview

The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code

can reside only in the program memory, while data can be stored in the program memory and the data memory. The data

memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and

require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write

operations. This prevents unrestricted access to the application software.

A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can

only be written by an external programmer.

The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a

Flash memory signature row for calibration data, device identification, serial number etc.

7.3

Flash Program Memory

The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The

flash memory can be accessed for read and write from an external programmer through the PDI or from application

software running in the device.

All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized

in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but

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device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store

program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate

when executed from the boot loader section.

The application section contains an application table section with separate lock settings. This enables safe storage of

nonvolatile data in the program memory.

Figure 7-1. Flash Program Memory (hexadecimal address)

Word address

ATxmega

32D3

64D3

128D3

192D3

256D3

384D3

0

Application section

(32K/64K/128K/192K/256K/384K)

...

37FF

3800

3FFF

4000

47FF

77FF

7800

7FFF

8000

87FF

EFFF

F000

16FFF

17000

17FFF

18000

18FFF

1EFFF

1F000

1FFFF

20000

20FFF

2EFFF

2F000

2FFFF

30000

30FFF

Application table section

(4K/4K/8K/8K/8K/8K)

FFFF

10000

10FFF

Boot section (4K/4K/8K/8K/8K/8K)

7.3.1 Application Section

The application section is the section of the flash that is used for storing the executable application code. The protection

level for the application section can be selected by the boot lock bits for this section. The application section can not store

any boot loader code since the SPM instruction cannot be executed from the application section.

7.3.2 Application Table Section

The application table section is a part of the application section of the flash memory that can be used for storing data.

The size is identical to the boot loader section. The protection level for the application table section can be selected by

the boot lock bits for this section. The possibilities for different protection levels on the application section and the

application table section enable safe parameter storage in the program memory. If this section is not used for data,

application code can reside here.

7.3.3 Boot Loader Section

While the application section is used for storing the application code, the boot loader software must be located in the boot

loader section because the SPM instruction can only initiate programming when executing from this section. The SPM

instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader

section can be selected by the boot loader lock bits. If this section is not used for boot loader software, the application

code can be stored here.

7.3.4 Production Signature Row

The production signature row is a separate memory section for factory programmed data. It contains calibration data for

functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the

corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to

the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical

Characteristics” on page 63.

The production signature row also contains an ID that identifies each microcontroller device type and a serial number for

each manufactured device. The serial number consists of the production lot number, wafer number, and wafer

coordinates for the device. The device ID for the available devices is shown in Table 7-1 on page 15.

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The production signature row cannot be written or erased, but it can be read from application software and external

programmers.

Table 7-1. Device ID Bytes

Device

Device ID bytes

Byte 1

Byte 2

4A

Byte 0

1E

ATxmega32D3

ATxmega64D3

ATxmega128D3

ATxmega192D3

ATxmega256D3

ATxmega384D3

95

96

97

98

4A

1E

48

1E

49

1E

44

1E

47

1E

7.3.5 User Signature Row

The user signature row is a separate memory section that is fully accessible (read and write) from application software

and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration

data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase

commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during

multiple program/erase operations and on-chip debug sessions.

7.4

Fuses and Lock Bits

The fuses are used to configure important system functions, and can only be written from an external programmer. The

application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and

watchdog, and startup configuration.

The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be

blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.

Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the

lock bits are erased after the rest of the flash memory has been erased.

An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.

Both fuses and lock bits are reprogrammable like the flash program memory.

7.5

Data Memory

The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory

if available. The data memory is organized as one continuous memory section, see Figure 7-2 on page 16. To simplify

development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA

devices.

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Figure 7-2. Data Memory Map (hexadecimal address)

Byte address

ATxmega32D3

Byte address

ATxmega64D3

0

FFF

0

FFF

I/O registers (4K)

1000

17FF

1000

17FF

EEPROM (1K)

RESERVED

EEPROM (2K)

RESERVED

2000

2FFF

2000

2FFF

Internal SRAM (4K)

Byte address

ATxmega128D3

Byte address

ATxmega192D3

0

FFF

0

FFF

I/O registers (4K)

1000

17FF

1000

17FF

EEPROM (2K)

RESERVED

EEPROM (2K)

RESERVED

2000

3FFF

2000

5FFF

Internal SRAM (8K)

Internal SRAM (16K)

Byte address

ATxmega256D3

Byte address

ATxmega384D3

0

FFF

0

FFF

I/O registers (4K)

1000

EEPROM (4K)

1FFF

2000

5FFF

1FFF

2000

9FFF

Internal SRAM (16K)

Internal SRAM (32K)

7.6

EEPROM

All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or

memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory

mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is

accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address

0x1000.

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7.7

I/O Memory

The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O

memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,

which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT

instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,

single-cycle instructions for manipulation and checking of individual bits are available.

The I/O memory address for all peripherals and modules is shown in the “Peripheral Module Address Map” on page 55.

7.7.1 General Purpose I/O Registers

The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for

storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

7.8

7.9

Memory Timing

Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from

SRAM takes two cycles. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst

read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and

instruction timing.

Device ID and Revision

Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A

separate register contains the revision number of the device.

7.10 I/O Memory Protection

Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the

I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is

enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers

themselves are protected by the configuration change protection mechanism.

7.11 Flash and EEPROM Page Size

The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the

flash and byte accessible for the EEPROM.

Table 7-2 on page 18 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and

erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash

access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page

number and the least significant address bits (FWORD) give the word in the page.

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Table 7-2. Number of Words and Pages in the Flash

Devices

PC size

Flash size

Page size

FWORD

FPAGE

Application

Boot

No. of

pages

No. of

pages

[bits]

[bytes]

[words]

Size

ATxmega32D3

ATxmega64D3

ATxmega128D3

ATxmega192D3

ATxmega256D3

ATxmega384D3

15

16

17

18

32K + 4K

64K + 4K

128

256

Z[7:1]

Z[8:1]

Z[15:7]

Z[16:9]

Z[17:9]

Z[18:9]

Z[19:9]

32K

64K

128

4K

8K

16

256

128K + 8K

192K + 8K

256K + 8K

384K + 8K

128K

192K

256K

384K

256

384

512

768

Table 7-3 shows EEPROM memory organization. EEEPROM write and erase operations can be performed one page or

one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address

register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number

and the least significant address bits (E2BYTE) give the byte in the page.

Table 7-3. Number of Bytes and Pages in the EEPROM

Devices

EEPROM

size

1K

Page size

E2BYTE

E2PAGE

No. of pages

[bytes]

32

ATxmega32D3

ATxmega64D3

ATxmega128D3

ATxmega192D3

ATxmega256D3

ATxmega384D3

ADDR[4:0]

ADDR[10:5]

ADDR[11:5]

64

2K

32

2K

32

64

2K

32

64

4K

32

128

4K

32

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8.

Event System

8.1

Features

 System for direct peripheral-to-peripheral communication and signaling

 Peripherals can directly send, receive, and react to peripheral events

 CPU independent operation

 100% predictable signal timing

 Short and guaranteed response time

 Four event channels for up to four different and parallel signal routing configurations

 Events can be sent and/or used by most peripherals, clock system, and software

 Additional functions include

 Quadrature decoders

 Digital filtering of I/O pin state

 Works in active mode and idle sleep mode

8.2

Overview

The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one

peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for

short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction

without the use of interrupts or CPU resources, and is thus a powerful tool for reducing the complexity, size and

execution time of application code. It also allows for synchronized timing of actions in several peripheral modules.

A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt

conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing

network. How events are routed and used by the peripherals is configured in software.

Figure 8-1 shows a basic diagram of all connected peripherals. The event system can directly connect together analog to

digital converter, analog comparators, I/O port pins, the real-time counter, timer/counters, and IR communication module

(IRCOM). Events can also be generated from software and the peripheral clock.

Figure 8-1. Event System Overview and Connected Peripherals

CPU /

Software

Event Routing Network

clk_PER

Prescaler

ADC

Event

Real Time

System

Counter

Controller

AC

Timer /

Counters

Port pins

IRCOM

The event routing network consists of four software-configurable multiplexers that control how events are routed and

used. These are called event channels, and allow for up to four parallel event routing configurations. The maximum

routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.

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9.

System Clock and Clock Options

9.1

Features

 Fast start-up time

 Safe run-time clock switching

 Internal oscillators:

 32MHz run-time calibrated and tuneable oscillator

 2MHz run-time calibrated oscillator

 32.768kHz calibrated oscillator

 32kHz ultra low power (ULP) oscillator with 1kHz output

 External clock options

 0.4MHz - 16MHz crystal oscillator

 32.768kHz crystal oscillator

 External clock

 PLL with 20MHz - 128MHz output frequency

 Internal and external clock options and 1× to 31× multiplication

 Lock detector

 Clock prescalers with 1× to 2048× division

 Fast peripheral clocks running at two and four times the CPU clock

 Automatic run-time calibration of internal oscillators

 External oscillator and PLL lock failure detection with optional non-maskable interrupt

9.2

Overview

Atmel AVR XMEGA D3 devices have a flexible clock system supporting a large number of clock sources. It incorporates

both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked

loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL)

is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over

voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the

internal oscillator if the external oscillator or PLL fails.

When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device

will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and

prescalers can be changed from software at any time.

Figure 9-1 on page 21 presents the principal clock system. Not all of the clocks need to be active at a given time. The

clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in

“Power Management and Sleep Modes” on page 23.

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Figure 9-1. The Clock System, Clock Sources, and Clock Distribution

Real Time

Peripherals

Counter

Non-Volatile

Memory

RAM

AVR CPU

clk_PER

clk_PER2

clk_CPU

clk_PER4

System Clock Prescalers

clk_SYS

Brown-out

Detector

Watchdog

Timer

clk_RTC

System Clock Multiplexer

(SCLKSEL)

RTCSRC

PLL

PLLSRC

XOSCSEL

32kHz

Int. ULP

32.768kHz

Int. OSC

32.768kHz

TOSC

0.4 – 16MHz

XTAL

32MHz

Int. Osc

2MHz

Int. Osc

9.3

Clock Sources

The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock

sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,

depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other

clock sources, DFLLs and PLL, are turned off by default.

The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the

internal oscillators, refer to the device datasheet.

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9.3.1 32kHz Ultra Low Power Internal Oscillator

This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low

power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a

1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.

This oscillator can be selected as the clock source for the RTC.

9.3.2 32.768kHz Calibrated Internal Oscillator

This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency

close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the

oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz

output.

9.3.3 32.768kHz Crystal Oscillator

A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low

frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator

can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.

9.3.4 0.4 - 16MHz Crystal Oscillator

This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.

9.3.5 2MHz Run-time Calibrated Internal Oscillator

The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during

production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time

calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.

9.3.6 32MHz Run-time Calibrated Internal Oscillator

The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to

provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for

automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator

accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz.

9.3.7 External Clock Sources

The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.

XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a

32.768kHz crystal oscillator.

9.3.8 PLL with 1x-31x Multiplication Factor

The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-

selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output

frequencies from all clock sources.

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10. Power Management and Sleep Modes

10.1 Features

 Power management for adjusting power consumption and functions

 Five sleep modes

 Idle

 Power down

 Power save

 Standby

 Extended standby

 Power reduction register to disable clock and turn off unused peripherals in active and idle modes

10.2 Overview

Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.

This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.

All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application

code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the

device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals

and all enabled reset sources can restore the microcontroller from sleep to active mode.

In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When

this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This

reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power

management than sleep modes alone.

10.3 Sleep Modes

Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA

microcontrollers have five different sleep modes tuned to match the typical functional stages during application

execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the

device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an

enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal

program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending

when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt

service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution

starts.

The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will

reset, start up, and execute from the reset vector.

10.3.1 Idle Mode

In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but

all peripherals, including the interrupt controller and event system are kept running. Any enabled interrupt will wake the

device.

10.3.2 Power-down Mode

In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of

asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-

wire interface address match interrupt and asynchronous port interrupts.

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10.3.3 Power-save Mode

Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep

running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.

10.3.4 Standby Mode

Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running

while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.

10.3.5 Extended Standby Mode

Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are

kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.

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11. System Control and Reset

11.1 Features

 Reset the microcontroller and set it to initial state when a reset source goes active

 Multiple reset sources that cover different situations

 Power-on reset

 External reset

 Watchdog reset

 Brownout reset

 PDI reset

 Software reset

 Asynchronous operation

 No running system clock in the device is required for reset

 Reset status register for reading the reset source from the application code

11.2 Overview

The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where

operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset

source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins

are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their

initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of

the accessed location can not be guaranteed.

After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts

running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to

move the reset vector to the lowest address in the boot section.

The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software

reset feature makes it possible to issue a controlled system reset from the user software.

The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows

which sources have issued a reset since the last power-on.

11.3 Reset Sequence

A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is

active. When all reset requests are released, the device will go through three stages before the device starts running

again:



Reset counter delay

Oscillator startup

Oscillator calibration

If another reset requests occurs during this process, the reset sequence will start over again.

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11.4 Reset Sources

11.4.1 Power-on Reset

A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the V_CCrises and

reaches the POR threshold voltage (V_POT), and this will start the reset sequence.

The POR is also activated to power down the device properly when the V_CCfalls and drops below the V_POTlevel.

The V_POTlevel is higher for falling V_CCthan for rising V_CC. Consult the datasheet for POR characteristics data.

11.4.2 Brownout Detection

The on-chip brownout detection (BOD) circuit monitors the V_CClevel during operation by comparing it to a fixed,

programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip

erase and when the PDI is enabled.

11.4.3 External Reset

The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is

driven below the RESET pin threshold voltage, V_RST, for longer than the minimum pulse period, t_EXT. The reset will be

held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.

11.4.4 Watchdog Reset

The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from

the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one

to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 27.

11.4.5 Software Reset

The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset

control register. The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any

instruction from when a software reset is requested until it is issued.

11.4.6 Program and Debug Interface Reset

The program and debug interface reset contains a separate reset source that is used to reset the device during external

programming and debugging. This reset source is accessible only from external debuggers and programmers.

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12. WDT – Watchdog Timer

12.1 Features

 Issues a device reset if the timer is not reset before its timeout period

 Asynchronous operation from dedicated oscillator

 1kHz output of the 32kHz ultra low power oscillator

 11 selectable timeout periods, from 8ms to 8s

 Two operation modes:

 Normal mode

 Window mode

 Configuration lock to prevent unwanted changes

12.2 Overview

The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover

from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout

period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a

microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application

code.

The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT

must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.

Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.

The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock

source, and will continue to operate to issue a system reset even if the main clocks fail.

The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For

increased safety, a fuse for locking the WDT settings is also available.

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13. Interrupts and Programmable Multilevel Interrupt Controller

13.1 Features

 Short and predictable interrupt response time

 Separate interrupt configuration and vector address for each interrupt

 Programmable multilevel interrupt controller

 Interrupt prioritizing according to level and vector address

 Three selectable interrupt levels for all interrupts: low, medium, and high

 Selectable, round-robin priority scheme within low-level interrupts

 Non-maskable interrupts for critical functions

 Interrupt vectors optionally placed in the application section or the boot loader section

13.2 Overview

Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have

one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it

will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt

controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged

by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.

All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are

prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level

interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the

interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest

interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are

serviced within a certain amount of time.

Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.

13.3 Interrupt Vectors

The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in

each peripheral. The base addresses for the Atmel AVR XMEGA D3 devices are shown in Table 13-1 on page 29. Offset

addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA D manual. For

peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 13-1 on page 29. The program

address is the word address.

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Table 13-1. Reset and Interrupt Vectors

Program address

(base address)

0x000

0x002

0x004

0x008

0x014

0x018

0x01C

0x028

0x030

0x032

0x040

0x044

0x056

0x05A

0x05E

0x074

0x080

0x084

0x088

0x08E

0x09A

0x0AE

0x0B0

0x0B6

0x0D0

0x0D8

Source

Interrupt description

RESET

OSCF_INT_vect

PORTC_INT_base

PORTR_INT_base

RTC_INT_base

Crystal oscillator failure interrupt vector (NMI)

Port C interrupt base

Port R interrupt base

Real Time Counter Interrupt base

Two-Wire Interface on Port C Interrupt base

Timer/Counter 0 on port C Interrupt base

Timer/Counter 1 on port C Interrupt base

SPI on port C Interrupt vector

TWIC_INT_base

TCC0_INT_base

TCC1_INT_base

SPIC_INT_vect

USARTC0_INT_base

NVM_INT_base

PORTB_INT_base

PORTE_INT_base

TWIE_INT_base

TCE0_INT_base

USARTE0_INT_base

PORTD_INT_base

PORTA_INT_base

ACA_INT_base

ADCA_INT_base

TCD0_INT_base

SPID_INT_vector

USARTD0_INT_base

USARTD1_INT_base

PORTF_INT_base

TCF0_INT_base

USART 0 on port C Interrupt base

Non-Volatile Memory Interrupt base

Port B Interrupt base

Port E INT base

Two-Wire Interface on Port E Interrupt base

Timer/Counter 0 on port E Interrupt base

USART 0 on port E Interrupt base

Port D Interrupt base

Port A Interrupt base

Analog Comparator on Port A Interrupt base

Analog to Digital Converter on Port A Interrupt base

Timer/Counter 0 on port D Interrupt base

SPI D Interrupt vector

USART 0 on port D Interrupt base

USART 1 on port D Interrupt base

Port F Interrupt base

Timer/Counter 0 on port F Interrupt base

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14. I/O Ports

14.1 Features

 50 general purpose input and output pins with individual configuration

 Output driver with configurable driver and pull settings:

 Totem-pole

 Wired-AND

 Wired-OR

 Bus-keeper

 Inverted I/O

 Input with synchronous and/or asynchronous sensing with interrupts and events

 Sense both edges

 Sense rising edges

 Sense falling edges

 Sense low level

 Optional pull-up and pull-down resistor on input and Wired-OR/AND configuration

 Asynchronous pin change sensing that can wake the device from all sleep modes

 Two port interrupts with pin masking per I/O port

 Efficient and safe access to port pins

 Hardware read-modify-write through dedicated toggle/clear/set registers

 Configuration of multiple pins in a single operation

 Mapping of port registers into bit-accessible I/O memory space

 Peripheral clocks output on port pin

 Real-time counter clock output to port pin

 Event channels can be output on port pin

 Remapping of digital peripheral pin functions

 Selectable USART, SPI, and timer/counter input/output pin locations

14.2 Overview

One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable

driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for

selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from

all sleep modes, included the modes where no clocks are running.

All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins

have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor

configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other

pin.

The port pin configuration also controls input and output selection of other device functions. It is possible to have both the

peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events

from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as

USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus

application needs.

The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF, and PORTR.

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14.3 Output Driver

All port pins (Pn) have programmable output configuration.

14.3.1 Push-pull

Figure 14-1. I/O Configuration - Totem-pole

DIRn

OUTn

INn

Pn

14.3.2 Pull-down

Figure 14-2. I/O Configuration - Totem-pole with Pull-down (on input)

DIRn

OUTn

INn

Pn

14.3.3 Pull-up

Figure 14-3. I/O Configuration - Totem-pole with Pull-up (on input)

DIRn

OUTn

INn

Pn

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14.3.4 Bus-keeper

The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level

was ‘1’, and pull-down if the last level was ‘0’.

Figure 14-4. I/O Configuration - Totem-pole with Bus-keeper

DIRn

OUTn

INn

Pn

14.3.5 Others

Figure 14-5. Output Configuration - Wired-OR with Optional Pull-down

OUTn

Pn

INn

Figure 14-6. I/O Configuration - Wired-AND with Optional Pull-up

INn

Pn

OUTn

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14.4 Input Sensing

Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is

shown in Figure 14-7.

Figure 14-7. Input Sensing System Overview

Asynchronous sensing

EDGE

DETECT

Interrupt

Control

IRQ

Synchronous sensing

Pxn

Synchronizer

INn

EDGE

DETECT

Synchronous

Events

D

Q

D

Q

R

INVERTED I/O

Asynchronous

Events

When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.

14.5 Alternate Port Functions

Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is

enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins

are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for

that peripheral. “Pinout and Pin Functions” on page 50 shows which modules on peripherals that enable alternate

functions on a pin, and which alternate functions that are available on a pin.

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15. TC0/1 – 16-bit Timer/Counter Type 0 and 1

15.1 Features

 Five 16-bit timer/counters

 Four timer/counters of type 0

 One timer/counter of type 1

 Split-mode enabling two 8-bit timer/counter from each timer/counter type 0

 32-bit timer/counter support by cascading two timer/counters

 Up to four compare or capture (CC) channels

 Four CC channels for timer/counters of type 0

 Two CC channels for timer/counters of type 1

 Double buffered timer period setting

 Double buffered capture or compare channels

 Waveform generation:

 Frequency generation

 Single-slope pulse width modulation

 Dual-slope pulse width modulation

 Input capture:

 Input capture with noise cancelling

 Frequency capture

 Pulse width capture

 32-bit input capture

 Timer overflow and error interrupts/events

 One compare match or input capture interrupt/event per CC channel

 Can be used with event system for:

 Quadrature decoding

 Count and direction control

 Capture

 High-resolution extension

 Increases frequency and waveform resolution by 4× (2-bit) or 8× (3-bit)

 Advanced waveform extension:

 Low- and high-side output with programmable dead-time insertion (DTI)

 Event controlled fault protection for safe disabling of drivers

15.2 Overview

Atmel AVR XMEGA D3 devices have a set of five flexible 16-bit timer/counters (TC). Their capabilities include accurate

program execution timing, frequency and waveform generation, and input capture with time and frequency measurement

of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.

A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be

used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC

channels can be used together with the base counter to do compare match control, frequency generation, and pulse

width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either

capture or compare functions, but cannot perform both at the same time.

A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.

The event system can also be used for direction control and capture trigger or to synchronize operations.

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There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and

timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.

Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels

each.

Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced

waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high-

side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can

also generate a synchronized bit pattern across the port pins.

The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter.

This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 37 for more details.

The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by

using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution

Extension” on page 38 for more details.

Figure 15-1. Overview of a Timer/Counter and Closely Related Peripherals

Timer/Counter

Base Counter

Prescaler

clk_PER

Timer Period

Counter

Control Logic

Event

System

clk_PER4

Compare/Capture Channel D

Compare/Capture Channel C

Compare/Capture Channel B

Compare/Capture Channel A

AWeX

Pattern

Generation

Fault

Dead-Time

Insertion

Capture

Comparator

Control

Protection

Waveform

Generation

Buffer

PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD, PORTE and PORTF each has one Timer/Counter

0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCE0, and TCF0, respectively.

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16. TC2 – Timer/Counter Type 2

16.1 Features

 Eight 8-bit timer/counters

 Four Low-byte timer/counter

 Four High-byte timer/counter

 Up to eight compare channels in each Timer/Counter 2

 Four compare channels for the low-byte timer/counter

 Four compare channels for the high-byte timer/counter

 Waveform generation

 Single slope pulse width modulation

 Timer underflow interrupts/events

 One compare match interrupt/event per compare channel for the low-byte timer/counter

 Can be used with the event system for count control

16.2 Overview

There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of

two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation

(PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of

PWM channels.

The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,

respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare

match interrupts and events. The two eight-bit timer/counters have a shared clock source and separate period and

compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event

system. The counters are always counting down.

PORTC, PORTD, PORTE, and PORTF each has one Timer/Counter 2. Notation of these are TCC2 (Timer/Counter C2),

TCD2, TCE2, and TCF2, respectively.

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17. AWeX – Advanced Waveform Extension

17.1 Features

 Waveform output with complementary output from each compare channel

 Four dead-time insertion (DTI) units

 8-bit resolution

 Separate high and low side dead-time setting

 Double buffered dead time

 Optionally halts timer during dead-time insertion

 Pattern generation unit creating synchronised bit pattern across the port pins

 Double buffered pattern generation

 Optional distribution of one compare channel output across the port pins

 Event controlled fault protection for instant and predictable fault triggering

17.2 Overview

The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)

modes. It is primarily intended for use with different types of motor control and other power control applications. It

enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external

drivers. It can also generate a synchronized bit pattern across the port pins.

Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any

AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non-

inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS

switching. The DTI output will override the normal port value according to the port override setting.

The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,

the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator

unit is enabled, the DTI unit is bypassed.

The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable

the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of

fault triggers.

The AWeX is available for TCC0. The notation of this is AWEXC.

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18. Hi-Res – High Resolution Extension

18.1 Features

 Increases waveform generator resolution up to 8× (three bits)

 Supports frequency, single-slope PWM, and dual-slope PWM generation

 Supports the AWeX when this is used for the same timer/counter

18.2 Overview

The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a

timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM

generation. It can also be used with the AWeX if this is used for the same timer/counter.

The hi-res extension uses the peripheral 4× clock (Clk_PER4). The system clock prescalers must be configured so the

peripheral 4× clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res

extension is enabled.

There is one hi-res extensions that can be enabled for timer/counters pair on PORTC. The notation of this is HIRESC.

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19. RTC – 16-bit Real-Time Counter

19.1 Features

 16-bit resolution

 Selectable clock source

 32.768kHz external crystal

 External clock

 32.768kHz internal oscillator

 32kHz internal ULP oscillator

 Programmable 10-bit clock prescaling

 One compare register

 One period register

 Clear counter on period overflow

 Optional interrupt/event on overflow and compare match

19.2 Overview

The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to

keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.

The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the

configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs

a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal

oscillator or the 32kHz internal ULP oscillator.

The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the

counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the

maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the

maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event

when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period

register value.

Figure 19-1. Real-time Counter Overview

External Clock

TOSC1

32.768kHz Crystal Osc

TOSC2

32.768kHz Int. Osc

32kHz int ULP (DIV32)

PER

RTCSRC

TOP/

clk_RTC

10-bit

=

Overflow

CNT

prescaler

”match”/

Compare

COMP

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20. TWI – Two-Wire Interface

20.1 Features

 Two Identical two-wire interface peripherals

 Bidirectional, two-wire communication interface

 Phillips I²C compatible

 System Management Bus (SMBus) compatible

 Bus master and slave operation supported

 Slave operation

 Single bus master operation

 Bus master in multi-master bus environment

 Multi-master arbitration

 Flexible slave address match functions

 7-bit and general call address recognition in hardware

 10-bit addressing supported

 Address mask register for dual address match or address range masking

 Optional software address recognition for unlimited number of addresses

 Slave can operate in all sleep modes, including power-down

 Slave address match can wake device from all sleep modes

 100kHz and 400kHz bus frequency support

 Slew-rate limited output drivers

 Input filter for bus noise and spike suppression

 Support arbitration between start/repeated start and data bit (SMBus)

 Slave arbitration allows support for address resolve protocol (ARP) (SMBus)

20.2 Overview

The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I²C and System Management Bus

(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.

A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a

slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or

several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to

transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.

The TWI module supports master and slave functionality. The master and slave functionality are separated from each

other, and can be enabled and configured separately. The master module supports multi-master bus operation and

arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command

and smart mode can be enabled to auto-trigger operations and reduce software complexity.

The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is

also supported. A dedicated address mask register can act as a second address match register or as a register for

address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables

the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address

matching to let this be handled in software instead.

The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,

and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave

modes.

It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external

TWI bus driver. This can be used for applications where the device operates from a different V_CCvoltage than used by

the TWI bus.

PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.

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21. SPI – Serial Peripheral Interface

21.1 Features

 Two identical SPI peripherals

 Full-duplex, three-wire synchronous data transfer

 Master or slave operation

 Lsb first or msb first data transfer

 Eight programmable bit rates

 Interrupt flag at the end of transmission

 Write collision flag to indicate data collision

 Wake up from idle sleep mode

 Double speed master mode

21.2 Overview

The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It

allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several

microcontrollers. The SPI supports full-duplex communication.

A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.

PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID, respectively.

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22. USART

22.1 Features

 Three identical USART peripherals

 Full-duplex operation

 Asynchronous or synchronous operation

 Synchronous clock rates up to 1/2 of the device clock frequency

 Asynchronous clock rates up to 1/8 of the device clock frequency

 Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits

 Fractional baud rate generator

 Can generate desired baud rate from any system clock frequency

 No need for external oscillator with certain frequencies

 Built-in error detection and correction schemes

 Odd or even parity generation and parity check

 Data overrun and framing error detection

 Noise filtering includes false start bit detection and digital low-pass filter

 Separate interrupts for

 Transmit complete

 Transmit data register empty

 Receive complete

 Multiprocessor communication mode

 Addressing scheme to address a specific devices on a multidevice bus

 Enable unaddressed devices to automatically ignore all frames

 Master SPI mode

 Double buffered operation

 Operation up to 1/2 of the peripheral clock frequency

 IRCOM module for IrDA compliant pulse modulation/demodulation

22.2 Overview

The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial

communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.

The USART can be configured to operate in SPI master mode and used for SPI communication.

Communication is frame based, and the frame format can be customized to support a wide range of standards. The

USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate

interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow

are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can

also be enabled.

The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates

from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency

to achieve a required baud rate. It also supports external clock input in synchronous slave operation.

When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive

buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.

The registers are used in both modes, but their functionality differs for some control settings.

An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and

demodulation for baud rates up to 115.2kbps.

PORTC, PORTD, and PORTE each has one USART. Notation of these peripherals are USARTC0, USARTD0, and

USARTE0, respectively.

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23. IRCOM – IR Communication Module

23.1 Features

 Pulse modulation/demodulation for infrared communication

 IrDA compatible for baud rates up to 115.2kbps

 Selectable pulse modulation scheme

 3/16 of the baud rate period

 Fixed pulse period, 8-bit programmable

 Pulse modulation disabled

 Built-in filtering

 Can be connected to and used by any USART

23.2 Overview

Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates

up to 115.2kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.

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24. CRC – Cyclic Redundancy Check generator

24.1 Features

 Cyclic redundancy check (CRC) generation and checking for

 Communication data

 Program or data in flash memory

 Data in SRAM and I/O memory space

 Integrated with flash memory and CPU

 Automatic CRC of the complete or a selectable range of the flash memory

 CPU can load data to the CRC generator through the I/O interface

 CRC polynomial software selectable to

 CRC-16 (CRC-CCITT)

 CRC-32 (IEEE 802.3)

 Zero remainder detection

24.2 Overview

A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and

it is commonly used to determine the correctness of a data transmission, and data present in the data and program

memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be

appended to the data and used as a checksum. When the same data are later received or read, the device or application

repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.

The application will then detect this and may take a corrective action, such as requesting the data to be sent again or

simply not using the incorrect data.

Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits

(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2^-nof all longer error

bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-

CCITT) and CRC-32 (IEEE 802.3).

CRC-16:

Polynominal: x¹⁶+x¹²+x⁵+1

Hex value:

0x1021

CRC-32:

Polynominal: x³²+x²⁶+x²³+x²²+x¹⁶+x¹²+x¹¹+x¹⁰+x⁸+x⁷+x⁵+x⁴+x²+x+1

Hex value: 0x04C11DB7

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25. ADC – 12-bit Analog to Digital Converter

25.1 Features

 One Analog to Digital Converter (ADC)

 12-bit resolution

 Up to 300 thousand samples per second

 Down to 2.3µs conversion time with 8-bit resolution

 Down to 3.35µs conversion time with 12-bit resolution

 Differential and single-ended input

 16 single-ended inputs

 16 * 4 differential inputs without gain

 8 * 4 differential input with gain

 Built-in differential gain stage

 1/2×, 1×, 2×, 4×, 8×, 16×, 32×, and 64× gain options

 Single, continuous and scan conversion options

 Three internal inputs

 Internal temperature sensor

 AV_CCvoltage divided by 10

 1.1V bandgap voltage

 Internal and external reference options

 Compare function for accurate monitoring of user defined thresholds

 Optional event triggered conversion for accurate timing

 Optional interrupt/event on compare result

25.2 Overview

The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 300

thousand samples per second (ksps). The input selection is flexible, and both single-ended and differential

measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic

range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.

The ADC measurements can either be started by application software or an incoming event from another peripheral in

the device. The ADC measurements can be started with predictable timing, and without software intervention.

Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the

ADC. The AV_CC/10 and the bandgap voltage can also be measured by the ADC.

The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention

required.

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Figure 25-1. ADC Overview

Compare

Register

ADC0

•

V_INP

<

>

ADC15

Threshold

(Int Req)

Internal

signals

CH0 Result

ADC

ADC0

•

V_INN

ADC7

Internal 1.00V

Internal AVCC/1.6V

l

Interna AVCC/2

Reference

Voltage

AREFA

AREFB

The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from

3.35µs for 12-bit to 2.3µs for 8-bit result.

ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when

the result is represented as a signed integer (signed 16-bit number).

PORTA has one ADC. Notation of this peripheral is ADCA.

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26. AC – Analog Comparator

26.1 Features

 Two analog comparators (AC)

 Selectable hysteresis

 No

 Small

 Large

 Analog comparator output available on pin

 Flexible input selection

 All pins on the port

 Bandgap reference voltage

 A 64-level programmable voltage scaler of the internal AV_CCvoltage

 Interrupt and event generation on:

 Rising edge

 Falling edge

 Toggle

 Window function interrupt and event generation on:

 Signal above window

 Signal inside window

 Signal below window

 Constant current source with configurable output pin selection

26.2 Overview

The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this

comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several

different combinations of input change.

The analog comparator hysteresis can be adjusted in order to achieve the optimal operation for each application.

The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The

analog comparator output state can also be output on a pin for use by external devices.

A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,

external resistors used to charge capacitors in capacitive touch sensing applications.

The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and

analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in

window mode to compare a signal to a voltage range instead of a voltage level.

PORTA has one AC pair. Notation is ACA.

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Figure 26-1. Analog Comparator Overview

Pin Input

+

AC0OUT

Pin Input

-

Hysteresis

Enable

Interrupt

Interrupts

Events

Interrupt

Mode

Sensititivity

Control

&

Voltage

Scaler

ACnMUXCTRL

ACnCTRL

WINCTRL

Window

Function

Enable

Bandgap

Hysteresis

+

-

Pin Input

AC1OUT

Pin Input

The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in

Figure 26-2.

Figure 26-2. Analog Comparator Window Function

+

AC0

Upper limit of window

-

Interrupts

Interrupt

Input signal

sensitivity

Events

control

+

AC1

Lower limit of window

-

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27. Programming and Debugging

27.1 Features

 Programming

 External programming through PDI interface



Minimal protocol overhead for fast operation



Built-in error detection and handling for reliable operation

 Boot loader support for programming through any communication interface

 Debugging

 Nonintrusive, real-time, on-chip debug system

 No software or hardware resources required from device except pin connection

 Program flow control



Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor

 Unlimited number of user program breakpoints

 Unlimited number of user data breakpoints, break on:



Data location read, write, or both read and write

Data location content equal or not equal to a value

Data location content is greater or smaller than a value

Data location content is within or outside a range

 No limitation on device clock frequency

 Program and Debug Interface (PDI)

 Two-pin interface for external programming and debugging

 Uses the Reset pin and a dedicated pin

 No I/O pins required during programming or debugging

27.2 Overview

The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip

debugging of a device.

The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user

signature row.

Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any

software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete

program flow control and support for an unlimited number of program and complex data breakpoints. Application debug

can be done from a C or other high-level language source code level, as well as from an assembler and disassembler

level.

Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset

pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external

programmer or on-chip debugger/emulator can be directly connected to this interface.

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28. Pinout and Pin Functions

The device pinout is shown in “Pinout/block Diagram” on page 5. In addition to general purpose I/O functionality, each pin

can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin.

Only one of the pin functions can be used at time.

28.1 Alternate Pin Function Description

The tables below show the notation for all pin functions available and describe its function.

28.1.1 Operation/power Supply

V_CC

Digital supply voltage

Analog supply voltage

Ground

AV_CC

GND

28.1.2 Port Interrupt Functions

SYNC

Port pin with full synchronous and limited asynchronous interrupt function

ASYNC

Port pin with full synchronous and full asynchronous interrupt function

28.1.3 Analog Functions

ACn

Analog comparator input pin n

Analog comparator n output

Analog to digital converter input pin n

Analog reference input pin

ACnOUT

ADCn

A_REF

28.1.4 Timer/counter and AWEX Functions

OCnxLS

OCnxHS

Output compare channel x low side for Timer/Counter n

Output compare channel x high side for Timer/Counter n

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28.1.5 Communication Functions

SCL

Serial Clock for TWI

SDA

Serial Data for TWI

SCLIN

SCLOUT

SDAIN

SDAOUT

XCKn

RXDn

TXDn

SS

Serial Clock In for TWI when external driver interface is enabled

Serial Clock Out for TWI when external driver interface is enabled

Serial Data In for TWI when external driver interface is enabled

Serial Data Out for TWI when external driver interface is enabled

Transfer Clock for USART n

Receiver Data for USART n

Transmitter Data for USART n

Slave Select for SPI

MOSI

MISO

SCK

Master Out Slave In for SPI

Master In Slave Out for SPI

Serial Clock for SPI

28.1.6 Oscillators, Clock, and Event

TOSCn

XTALn

Timer Oscillator pin n

Input/Output for Oscillator pin n

Peripheral Clock Output

Event Channel Output

CLKOUT

EVOUT

RTCOUT

RTC Clock Source Output

28.1.7 Debug/system Functions

RESET

Reset pin

PDI_CLK

PDI_DATA

Program and Debug Interface Clock pin

Program and Debug Interface Data pin

28.2 Alternate Pin Functions

The tables below show the primary/default function for each pin on a port in the first column, the pin number in the

second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that

enable and use the alternate pin functions.

For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the

first table where this apply.

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Table 28-1. Port A - Alternate Functions

ADCA POS/

ADCA

PORT A

GND

AVCC

PA0

PIN #

60

61

62

63

64

1

INTERRUPT

GAINPOS

ADCA NEG

GAINNEG

ACA POS

ACA NEG

ACA OUT

REFA

SYNC

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC0

ADC1

ADC2

ADC3

AC0

AC1

AC2

AC3

AC4

AC5

AC6

AC0

AC1

AREFA

PA1

PA2

SYNC/ASYNC

SYNC

PA3

AC3

AC5

AC7

PA4

2

SYNC

ADC4

ADC5

ADC6

ADC7

PA5

3

SYNC

PA6

4

SYNC

AC1OUT

AC0OUT

PA7

5

SYNC

Table 28-2. Port B - Alternate Functions

PORT B

PB0

PIN #

6

INTERRUPT

SYNC

ADCA POS

ADC8

REFB

AREFB

PB1

7

SYNC

ADC91

ADC10

ADC11

ADC12

ADC13

ADC14

ADC15

PB2

8

SYNC/ASYNC

SYNC

PB3

9

PB4

10

11

12

13

14

15

SYNC

PB5

SYNC

PB6

SYNC

PB7

SYNC

GND

VCC

Table 28-3. Port C - Alternate Functions

PORT C

PC0

PIN #

16

INTERRUPT

SYNC

TCC0 ⁽¹⁾⁽²⁾

OC0A

AWEXC

OC0ALS

OC0AHS

OC0BLS

OC0BHS

OC0CLS

OC0CHS

TCC1

USARTC0 ⁽³⁾

SPIC ⁽⁴⁾

TWIC

CLOCKOUT ⁽⁵⁾

EVENTOUT ⁽⁶⁾

SDA

SCL

PC1

17

SYNC

OC0B

XCK0

RXD0

TXD0

PC2

18

SYNC/ASYNC

SYNC

OC0C

PC3

19

OC0D

PC4

20

SYNC

OC1A

OC1B

SS

PC5

21

SYNC

MOSI

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PORT C

PC6

PIN #

22

INTERRUPT

SYNC

TCC0 ⁽¹⁾⁽²⁾

AWEXC

OC0DLS

OC0DHS

TCC1

USARTC0 ⁽³⁾

SPIC ⁽⁴⁾

MISO

SCK

TWIC

CLOCKOUT ⁽⁵⁾

RTCOUT

clk_PER

EVENTOUT ⁽⁶⁾

PC7

23

SYNC

EVOUT

GND

VCC

24

25

Notes:

1. Pin mapping of all TC0 can optionally be moved to high nibble of port.

2. If TC0 is configured as TC2 all eight pins can be used for PWM output.

3. Pin mapping of all USART0 can optionally be moved to high nibble of port.

4. Pins MOSI and SCK for all SPI can optionally be swapped.

5. CLKOUT can optionally be moved between port C, D, and E and between pin 4 and 7.

6. EVOUT can optionally be moved between port C, D, and E and between pin 4 and 7.

Table 28-4. Port D - Alternate Functions

PORT D

PD0

PIN #

26

INTERRUPT

SYNC

TCD0

OC0A

OC0B

OC0C

OC0D

USARTD0

SPID

CLOCKOUT

EVENTOUT

PD1

27

SYNC

XCK0

RXD0

TXD0

PD2

28

SYNC/ASYNC

SYNC

PD3

29

PD4

30

SYNC

SS

PD5

31

SYNC

MOSI

MISO

SCK

PD6

32

SYNC

PD7

33

SYNC

Clk_PER

EVOUT

GND

VCC

34

35

Table 28-5. Port E - Alternate Functions

PORT E

PE0

PIN #

36

INTERRUPT

SYNC

TCE0

USARTE0

TOSC

TWIE

CLOCKOUT

EVENTOUT

OC0A

OC0B

OC0C

OC0D

SDA

SCL

PE1

37

SYNC

XCK0

RXD0

TXD0

PE2

38

SYNC/ASYNC

SYNC

PE3

39

PE4

40

SYNC

PE5

41

SYNC

PE6

42

SYNC

TOSC2

TOSC1

PE7

43

SYNC

Clk_PER

EVOUT

GND

VCC

44

45

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Table 28-6. Port F - Alternate Functions

PORT F

PF0

PIN #

46

INTERRUPT

SYNC

TCF0

OC0A

OC0B

OC0C

OC0D

PF1

47

SYNC

PF2

48

SYNC/ASYNC

SYNC

PF3

49

PF4

50

SYNC

PF5

51

SYNC

PF6

54

SYNC

PF7

55

SYNC

GND

VCC

52

53

Table 28-7. Port R - Alternate Functions

PORT R

PDI

PIN #

56

INTERRUPT

PDI

XTAL

PDI_DATA

PDI_CLOCK

RESET

PRO

57

58

SYNC

XTAL2

XTAL1

PR1

59

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29. Peripheral Module Address Map

The address maps show the base address for each peripheral and module in Atmel AVR XMEGA D3. For complete

register description and summary for each peripheral module, refer to the XMEGA D manual.

Table 29-1. Peripheral Module Address Map

Base address

0x0000

0x0010

0x0014

0x0018

0x001C

0x0030

0x0040

0x0048

0x0050

0x0060

0x0068

0x0070

0x0078

0x0080

0x0090

0x00A0

0x00B0

0x0180

0x00D0

0x01C0

0x0200

0x0380

0x0400

0x0480

0x04A0

0x0600

0x0620

0x0640

Name

GPIO

Description

General Purpose IO Registers

Virtual Port 0

VPORT0

VPORT1

VPORT2

VPORT3

CPU

Virtual Port 1

Virtual Port 2

CPU

CLK

Clock Control

SLEEP

OSC

Sleep Controller

Oscillator Control

DFLLRC32M

DFLLRC2M

PR

DFLL for the 32MHz Internal Oscillator

DFLL for the 2MHz Internal Oscillator

Power Reduction

RST

Reset Controller

WDT

Watchdog Timer

MCU

MCU Control

PMIC

Programmable Multilevel Interrupt Controller

Port Configuration

PORTCFG

EVSYS

CRC

Event System

CRC Module

NVM

Non Volatile Memory (NVM) Controller

Analog to Digital Converter on port A

Analog Comparator pair on port A

Real-Time Counter

ADCA

ACA

RTC

TWIC

Two-Wire Interface on port C

Two-Wire Interface on port E

Port A

TWIE

PORTA

PORTB

PORTC

Port B

Port C

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Base address

0x0660

0x0680

0x06A0

0x07E0

0x0800

0x0840

0x0880

0x0890

0x08A0

0x08C0

0x08F8

0x0900

0x09A0

0x09C0

0x0A00

0x0A80

0x0AA0

0x0AC0

0x0B00

Name

PORTD

PORTE

PORTF

PORTR

TCC0

Description

Port D

Port E

Port F

Port R

Timer/Counter 0 on port C

Timer/Counter 1 on port C

Advanced Waveform Extension on port C

High Resolution Extension on port C

USART 0 on port C

TCC1

AWEXC

HIRESC

USARTC0

SPIC

Serial Peripheral Interface on port C

Infrared Communication Module

Timer/Counter 0 on port D

USART 0 on port D

IRCOM

TCD0

USARTD0

SPID

Serial Peripheral Interface on port D

Timer/Counter 0 on port E

Advanced Waveform Extension on port E

USART 0 on port E

TCE0

AWEXE

USARTE0

SPIE

Serial Peripheral Interface on port E

Timer/Counter 0 on port F

TCF0

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30. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

Arithmetic and logic instructions

ADD

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add without Carry

Rd



Rd + Rr

Z,C,N,V,S,H

Z,C,N,V,S

Z,C,N,V,S,H

Z,C,N,V,S

Z,N,V,S

Z,C,N,V,S

Z,C,N,V,S,H

Z,N,V,S

None

1

2

1

2

1

2

ADC

Add with Carry

Rd + Rr + C

Rd + 1:Rd + K

Rd - Rr

ADIW

SUB

Add Immediate to Word

Subtract without Carry

Subtract Immediate

Subtract with Carry

Subtract Immediate with Carry

Subtract Immediate from Word

Logical AND

SUBI

SBC

Rd - K

Rd - Rr - C

Rd - K - C

Rd + 1:Rd - K

Rd  Rr

SBCI

SBIW

AND

Rd + 1:Rd

Rd

ANDI

OR

Logical AND with Immediate

Logical OR

Rd

Rd  K

Rd

Rd v Rr

ORI

Logical OR with Immediate

Exclusive OR

Rd

Rd v K

EOR

COM

NEG

SBR

Rd

Rd  Rr

One’s Complement

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd

$FF - Rd

Rd

$00 - Rd

Rd, K

Rd

Rd v K

CBR

Rd

Rd  ($FFh - K)

Rd + 1

INC

Rd

DEC

Rd

Decrement

Rd

Rd - 1

TST

Rd

Test for Zero or Minus

Clear Register

Rd

Rd  Rd

CLR

Rd

Rd  Rd

SER

Rd

Set Register

Rd

$FF

MUL

Rd, Rr

Multiply Unsigned

R1:R0

Rd x Rr (UU)

Rd x Rr (SS)

Rd x Rr (SU)

Rd x Rr<<1 (UU)

Rd x Rr<<1 (SS)

Rd x Rr<<1 (SU)

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

Branch instructions

RJMP

IJMP

k

Relative Jump

PC



PC + k + 1

None

2

PC(15:0)

Z,

0



Indirect Jump to (Z)

PC(21:16)

PC(15:0)

Z,

EIND



EIJMP

Extended Indirect Jump to (Z)

None

2

PC(21:16)

JMP

k

Jump

PC



k

None

3

RCALL

Relative Call Subroutine

PC + k + 1

2 / 3 ⁽¹⁾

PC(15:0)

Z,

0

2 / 3 ⁽¹⁾



ICALL

Indirect Call to (Z)

None

PC(21:16)

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Mnemonics

Operands

Description

Operation

Flags

#Clocks

PC(15:0)

Z,

EIND

3 ⁽¹⁾



EICALL

Extended Indirect Call to (Z)

None

PC(21:16)

CALL

RET

k

call Subroutine

PC

k

None

I

3 / 4 ⁽¹⁾

4 / 5 ⁽¹⁾

1 / 2 / 3

1



Subroutine Return

PC

STACK

PC + 2 or 3

RETI

Interrupt Return

CPSE

CP

Rd, Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC

None

Z,C,N,V,S,H

None

Rd, Rr

Rd - Rr

CPC

Rd, Rr

Compare with Carry

Rd - Rr - C

1

CPI

Rd, K

Compare with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd - K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b) = 0) PC

if (Rr(b) = 1) PC

if (I/O(A,b) = 0) PC

If (I/O(A,b) =1) PC

if (SREG(s) = 1) then PC

if (SREG(s) = 0) then PC

if (Z = 1) then PC

if (Z = 0) then PC

if (C = 1) then PC

if (C = 0) then PC

if (C = 1) then PC

if (N = 1) then PC

if (N = 0) then PC

if (N  V= 0) then PC

if (N  V= 1) then PC

if (H = 1) then PC

if (H = 0) then PC

if (T = 1) then PC

if (T = 0) then PC

if (V = 1) then PC

if (V = 0) then PC

if (I = 1) then PC

if (I = 0) then PC



PC + 2 or 3

PC + k + 1

1 / 2 / 3

2 / 3 / 4

1 / 2

Rr, b

A, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

1 / 2

k

Branch if Not Equal

1 / 2

k

Branch if Carry Set

1 / 2

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

1 / 2

k

1 / 2

k

1 / 2

k

Branch if Minus

1 / 2

k

Branch if Plus

1 / 2

k

Branch if Greater or Equal, Signed

Branch if Less Than, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

Data transfer instructions

MOV

MOVW

LDI

Rd, Rr

Rd, K

Rd, k

Copy Register

Rd

Rd+1:Rd

Rd



Rr

None

1

Copy Register Pair

Load Immediate

Rr+1:Rr

K

1

LDS

LD

Load Direct from data space

Load Indirect

Rd

(k)

(X)

2 ⁽¹⁾⁽²⁾

1 ⁽¹⁾⁽²⁾

Rd, X

Rd

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Mnemonics

Operands

Description

Operation

Flags

#Clocks

Rd

(X)

X + 1

1 ⁽¹⁾⁽²⁾



LD

Rd, X+

Load Indirect and Post-Increment

None

X

X  X - 1,

Rd  (X)

X - 1

(X)

2 ⁽¹⁾⁽²⁾

1 ⁽¹⁾⁽²⁾



LD

Rd, -X

Rd, Y

Load Indirect and Pre-Decrement

Load Indirect

None

Rd  (Y)

(Y)



Rd

Y

(Y)

Y + 1



Rd, Y+

Load Indirect and Post-Increment

Y

Y - 1

(Y)

2 ⁽¹⁾⁽²⁾



LD

Rd, -Y

Load Indirect and Pre-Decrement

None

Rd

LDD

LD

Rd, Y+q

Rd, Z

Load Indirect with Displacement

Load Indirect

Rd



(Y + q)

(Z)

None

2 ⁽¹⁾⁽²⁾

1 ⁽¹⁾⁽²⁾

Rd

Z

(Z),

Z+1



LD

Rd, Z+

Rd, -Z

Load Indirect and Post-Increment

Load Indirect and Pre-Decrement

None

Z

Z - 1,

(Z)

2 ⁽¹⁾⁽²⁾

2 ⁽¹⁾



Rd

LDD

STS

ST

Rd, Z+q

k, Rr

Load Indirect with Displacement

Store Direct to Data Space

Store Indirect

Rd

(k)

(X)



(Z + q)

Rd

None

X, Rr

Rr

1 ⁽¹⁾

(X)

X

Rr,

X + 1

1 ⁽¹⁾



ST

X+, Rr

Store Indirect and Post-Increment

None

X

X - 1,

Rr

2 ⁽¹⁾

1 ⁽¹⁾



ST

-X, Rr

Y, Rr

Store Indirect and Pre-Decrement

Store Indirect

None

(X)

(Y)



Rr

(Y)

Y

Rr,

Y + 1



Y+, Rr

Store Indirect and Post-Increment

Y

Y - 1,

Rr

2 ⁽¹⁾



ST

-Y, Rr

Store Indirect and Pre-Decrement

None

(Y)

STD

ST

Y+q, Rr

Z, Rr

Store Indirect with Displacement

Store Indirect

(Y + q)

(Z)



Rr

None

2 ⁽¹⁾

1 ⁽¹⁾

(Z)

Z

Rr

Z + 1

1 ⁽¹⁾



ST

Z+, Rr

Store Indirect and Post-Increment

None

ST

-Z, Rr

Store Indirect and Pre-Decrement

Store Indirect with Displacement

Load Program Memory

Z

(Z + q)

R0



Z - 1

Rr

None

2 ⁽¹⁾

3

STD

LPM

Z+q, Rr

(Z)

Rd, Z

Load Program Memory

Rd

(Z)

3

Rd

Z

(Z),

Z + 1



LPM

Rd, Z+

Load Program Memory and Post-Increment

None

3

ELPM

Extended Load Program Memory

R0

Rd



(RAMPZ:Z)

None

3

Rd, Z

Extended Load Program Memory and Post-

Increment

Rd

Z

(RAMPZ:Z),

Z + 1



ELPM

SPM

Rd, Z+

None

3

-

Store Program Memory

(RAMPZ:Z)



R1:R0

(RAMPZ:Z)

Z

R1:R0,

Z + 2



Z+

Store Program Memory and Post-Increment by 2

-

IN

Rd, A

A, Rr

Rr

In From I/O Location

Out To I/O Location

Rd

I/O(A)

STACK

Rd



I/O(A)

Rr

None

1

OUT

PUSH

POP

1

Push Register on Stack

Pop Register from Stack

Rr

1 ⁽¹⁾

2 ⁽¹⁾

Rd

STACK

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Mnemonics

Operands

Description

Operation

Flags

#Clocks

Bit and bit-test instructions

Rd(n+1)

Rd(n),

0,



LSL

Rd

Logical Shift Left

Z,C,N,V,H

Z,C,N,V

1

Rd(0)

Rd(n)

Rd(7)

Rd(n+1),

0,



LSR

ROL

ROR

Logical Shift Right

Rd(0)

C,

Rd(n),



Rotate Left Through Carry

Rotate Right Through Carry

Z,C,N,V,H

Z,C,N,V

Rd(n+1)

Rd(7)

Rd(n)

C,

Rd(n+1),



ASR

SWAP

BSET

BCLR

SBI

Rd

Arithmetic Shift Right

Swap Nibbles

Rd(n)







Rd(n+1), n=0..6

Z,C,N,V

1

Rd

Rd(3..0)

Rd(7..4)

None

s

Flag Set

SREG(s)

1

SREG(s)

s

Flag Clear

SREG(s)

0

SREG(s)

A, b

Rr, b

Rd, b

Set Bit in I/O Register

Clear Bit in I/O Register

Bit Store from Register to T

Bit load from T to Register

Set Carry

I/O(A, b)

1

None

CBI

I/O(A, b)

0

None

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

T

Rr(b)

T

1

T

Rd(b)

C

N

Z

None

C

N

Z

Clear Carry

0

Set Negative Flag

1

Clear Negative Flag

Set Zero Flag

0

1

Clear Zero Flag

Z

0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I

1

I

CLI

I

0

I

SES

CLS

SEV

CLV

SET

CLT

S

1

S

V

T

S

0

V

1

V

0

T

1

Clear T in SREG

T

0

T

SEH

CLH

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H

1

H

0

MCU control instructions

BREAK

NOP

Break

(See specific descr. for BREAK)

None

1

No Operation

Sleep

SLEEP

WDR

(See specific descr. for Sleep)

(See specific descr. for WDR)

Watchdog Reset

Notes:

1. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.

2. One extra cycle must be added when accessing internal SRAM.

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31. Packaging Information

31.1 64A

PIN 1

e

B

PIN 1 IDENTIFIER

E1

E

D1

D

C

0°~7°

A2

A

A1

L

COMMON DIMENSIONS

(Unit of measure = mm)

MIN

–

MAX

1.20

NOM

–

NOTE

SYMBOL

A

A1

A2

D

0.05

0.95

15.75

13.90

15.75

13.90

–

0.15

1.00

16.00

14.00

16.00

14.00

0.45

–

1.05

16.25

14.10

16.25

14.10

D1

E

Note 2

Notes:

1.This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

E1

B

0.30–

protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10mm maximum.

C

0.09

0.45

0.20

0.75

L

–

e

0.80 TYP

2010-10-20

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

San Jose, CA 95131

64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,

0.8mm Lead Pitch, Thin Proﬁle Plastic Quad Flat Package (TQFP)

64A

C

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31.2 64M

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32. Electrical Characteristics

All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum

values are valid across operating temperature and voltage unless other conditions are given.

32.1 Atmel ATxmega32D3

32.1.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 32-1 may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

Table 32-1. Absolute Maximum Ratings

Symbol

V_CC

I_VCC

I_GND

V_PIN

I_PIN

Parameter

Condition

Min.

Typ.

Max.

4

Units

Power supply voltage

Current into a V_CCpin

Current out of a Gnd pin

Pin voltage with respect to Gnd and V_CC

I/O pin sink/source current

Storage temperature

-0.3

V

200

mA

200

-0.5

-25

-65

V_CC+ 0.5

25

V

mA

T_A

150

°C

T_j

Junction temperature

150

32.1.2 General Operating Ratings

The device must operate within the ratings listed in Table 32-31 on page 82 in order for all other electrical characteristics

and typical characteristics of the device to be valid.

Table 32-2. General Operating Conditions

Symbol

V_CC

Parameter

Condition

Min.

1.60

-40

Typ.

Max.

3.6

Units

Power supply voltage

Analog supply voltage

Temperature range

Junction temperature

V

AV_CC

T_A

3.6

85

°C

T_j

-40

105

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Table 32-3. Operating Voltage and Frequency

Symbol

Parameter

Condition

V_CC= 1.6V

V_CC= 1.8V

V_CC= 2.7V

V_CC= 3.6V

Min.

Typ.

Max.

12

Units

0

12

Clk_CPU

CPU clock frequency

MHz

32

The maximum CPU clock frequency depends on V_CC. As shown in Figure 32-8 on page 83 the frequency vs. V_CCcurve is

linear between 1.8V < V_CC< 2.7V.

Figure 32-1. Maximum Frequency vs. V_CC

MHz

32

Safe operating area

12

V

1.6

1.8

2.7

3.6

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32.1.3 Current Consumption

Table 32-4. Current Consumption for Active Mode and Sleep Modes

Symbol Parameter

Condition

Min.

Typ.

50

Max. Units

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

32kHz, Ext. Clk

130

215

475

445

0.95

7.8

2.8

3

µA

1MHz, Ext. Clk

Active power

consumption ⁽¹⁾

600

2MHz, Ext. Clk

32MHz, Ext. Clk

32kHz, Ext. Clk

1.5

mA

12.0

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

46

1MHz, Ext. Clk

2MHz, Ext. Clk

µA

Idle power

92

consumption ⁽¹⁾

93

225

350

184

2.9

0.07

1.3

4.0

1.3

2.6

5.0

1.7

1.8

0.5

0.7

0.9

1.2

120

V_CC= 3.0V

I_CC

32MHz, Ext. Clk

5.0

1.0

5.0

8.0

2.0

6.0

10

mA

T = 25°C

T = 85°C

V_CC= 3.0V

T = 105°C

Power-down power

consumption

WDT and sampled BOD enabled, T = 25°C

WDT and sampled BOD enabled, T = 85°C

WDT and sampled BOD enabled, T= 105°C

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

µA

RTC from ULP clock, WDT and sampled

BOD enabled, T = 25°C

2.0

3.0

Power-save power

consumption ⁽²⁾

RTC from 1.024kHz low power 32.768kHz

TOSC, T = 25°C

RTC from low power 32.768kHz TOSC,

T = 25°C

Reset power consumption Current through RESET pin substracted

Notes:

1. All Power Reduction Registers set.

2. Maximum limits are based on characterization, and not tested in production.

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Table 32-5. Current Consumption for Modules and Peripherals

Symbol Parameter

Condition ⁽¹⁾

Min.

Typ.

0.9

29

Max.

Units

ULP oscillator

32.768kHz int. oscillator

82

2MHz int. oscillator

32MHz int. oscillator

DFLL enabled with 32.768kHz int. osc. as reference

114

250

400

µA

20× multiplication factor,

32MHz int. osc. DIV4 as reference

PLL

300

Watchdog timer

1.0

140

1.4

Continuous mode

BOD

Sampled mode, includes ULP oscillator

I_CC

Internal 1.0V reference

Temperature sensor

180

175

1.23

1.1

CURRLIMIT = LOW

16ksps

V_REF= Ext. ref.

CURRLIMIT = MEDIUM

0.98

0.87

CURRLIMIT = HIGH

ADC

mA

75ksps

CURRLIMIT = LOW

V_REF= Ext. ref.

1.7

3.1

300ksps

V_REF= Ext. ref.

USART

Rx and Tx enabled, 9600 BAUD

9.7

5

µA

Flash memory and EEPROM programming

mA

Note:

1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V_CC= 3.0V, Clk_SYS= 1MHz external clock

without prescaling, T = 25°C unless other conditions are given.

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32.1.4 Wake-up Time from Sleep Modes

Table 32-6. Device Wake-up Time from Sleep Modes with Various System Clock Sources

Symbol Parameter

Condition

Min.

Typ. ⁽¹⁾

2.0

Max.

Units

External 2MHz clock

Wake-up time from idle,

standby, and extended standby

mode

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

External 2MHz clock

125

2.0

0.2

t_wakeup

µs

4.6

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

330

9.5

Wake-up time from power-save

and power-down mode

5.6

Note:

1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-2. All peripherals and modules start

execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 32-2. Wake-up Time Definition

Wakeup time

Wakeup request

Clock output

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32.1.5 I/O Pin Characteristics

The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low-level input and output

voltage limits reflect or exceed this specification.

Table 32-7. I/O Pin Characteristics

Symbol

Parameter

Condition

Min.

-15

Typ.

Max.

15

Units

I_OH⁽¹⁾/ I_OL

I/O pin source/sink current

mA

(2)

V_CC= 2.4 - 3.6V

0.7 * V_CC

0.8 * V_CC

-0.5

V_CC+ 0.5

0.3 * V_CC

0.2 * V_CC

V_IH

High level input voltage

Low level input voltage

V_CC= 1.6 - 2.4V

V_CC= 2.4 - 3.6V

V_CC= 1.6 - 2.4V

V_CC= 3.3V

V_IL

-0.5

I_OH= -4mA

I_OH= -3mA

I_OH= -1mA

I_OL= 8mA

I_OL= 5mA

I_OL= 3mA

2.6

2.9

2.6

V

V_OH

High level output voltage

Low level output voltage

V_CC= 3.0V

2.1

V_CC= 1.8V

1.4

1.6

V_CC= 3.3V

0.4

0.76

0.64

0.46

1

V_OL

V_CC= 3.0V

0.3

V_CC= 1.8V

0.2

I_IN

Input leakage current I/O pin

Pull/buss keeper resistor

T = 25°C

<0.01

25

µA

R_P

k

Notes:

1. The sum of all I_OHfor PORTA and PORTB must not exceed 100mA.

The sum of all I_OHfor PORTC, PORTD, and PORTE must for each port not exceed 200mA.

The sum of all I_OHfor pins PF[0-5] on PORTF must not exceed 200mA.

The sum of all I_OLfor pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.

2. The sum of all I_OLfor PORTA and PORTB must not exceed 100mA.

The sum of all I_OLfor PORTC, PORTD, and PORTE must for each port not exceed 200mA.

The sum of all I_OLfor pins PF[0-5] on PORTF must not exceed 200mA.

The sum of all I_OLfor pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.

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32.1.6 ADC Characteristics

Table 32-8. Power Supply, Reference, and Input Range

Symbol Parameter

Condition

Min.

V_CC- 0.3

1

Typ.

Max.

V_CC+ 0.3

AV_CC- 0.6

4.5

Units

AV_CC

V_REF

R_in

Analog supply voltage

V

Reference voltage

Input resistance

Switched

k

pF

C_in

Input capacitance

Reference input resistance

Reference input capacitance

Input range

Switched

5

R_AREF

C_AREF

V_in

(leakage only)

Static load

>10

7

M

pF

0

V_REF

Conversion range

Fixed offset voltage

Differential mode, Vinp - Vinn

-V_REF

-V

V

Single ended unsigned mode, Vinp

V_REF- V

V

200

lsb

Table 32-9. Clock and Timing

Symbol Parameter

Condition

Min.

100

16

Typ.

Max.

1800

125

300

250

150

50

Units

Maximum is 1/4 of peripheral clock frequency

Measuring internal signals

Clk_ADC

ADC clock frequency

Sample rate

kHz

f_ClkADC

Current limitation (CURRLIMIT) off

CURRLIMIT = LOW

16

ksps

µs

f_ADC

Sample rate

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

16

Configurable in steps of 1/2 Clk_ADCcycle up

to 32 Clk_ADCcycles

Sampling time

0.28

5.5

320

10

(RES+2)/2 + 1 + GAIN

RES (Resolution) = 8 or 12, GAIN = 0 to 3

Conversion time (latency)

Clk_ADC

cycles

Start-up time

ADC clock cycles

12

7

24

7

ADC settling time

After changing reference or input mode

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Table 32-10. Accuracy Characteristics

Symbol

Parameter

Condition ⁽²⁾

Differential

Min.

Typ.

12

Max.

12

11

12

1

Units

8

7

8

RES

Resolution

12-bit resolution

Differential mode

Single ended signed

Single ended unsigned

16ksps, V_REF= 3V

16ksps, all V_REF

300ksps, V_REF= 3V

300ksps, all V_REF

16ksps, V_REF= 3.0V

16ksps, all V_REF

16ksps, V_REF= 3V

16ksps, all V_REF

300ksps, V_REF= 3V

300ksps, all V_REF

16ksps, V_REF= 3V

16ksps, all V_REF

300ksps, V_REF= 3V

Temperature drift, V_REF= 3V

Operating voltage drift

External reference

AV_CC/1.6

11

Bits

12

0.5

0.8

0.6

1

2

1

INL ⁽¹⁾

Integral non-linearity

2

0.5

1.3

0.3

0.5

0.3

0.5

0.6

-7

1

Single ended

unsigned mode

2

lsb

1

Differential mode

1

DNL ⁽¹⁾

Differential non-linearity

1

Single ended

unsigned mode

1

mV

Offset error

Differential mode

0.01

0.16

-5

mV/K

mV/V

-5

mV

AV_CC/2.0

-6

Gain error

Differential mode

Bandgap

±10

0.02

2

Temperature drift

Operating voltage drift

External reference

AV_CC/1.6

mV/K

mV/V

-8

mV

AV_CC/2.0

-8

Single ended

unsigned mode

Gain error

Bandgap

±10

0.03

2

Temperature drift

Operating voltage drift

mV/K

mV/V

Notes:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.

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Table 32-11. Gain Stage Characteristics

Symbol

R_in

Parameter

Condition

Switched in normal mode

Gain stage output

Min.

Typ.

4.0

Max.

Units

Input resistance

Input capacitance

Signal range

k

C_sample

4.4

pF

0

AV_CC- 0.6

V

Propagation delay

Clock frequency

ADC conversion rate

Same as ADC

1/2

100

1

3

Clk_ADCcycles

kHz

1800

0.5× gain, normal mode

1× gain, normal mode

8× gain, normal mode

64× gain, normal mode

0.5× gain, normal mode

1× gain, normal mode

8× gain, normal mode

64× gain, normal mode

-1

Gain error

%

-1

5

10

5

Offset error, input

referred

mV

-20

-126

32.1.7 Analog Comparator Characteristics

Table 32-12. Analog Comparator Characteristics

Symbol

V_off

Parameter

Condition

Min.

Typ.

10

Max.

Units

mV

nA

Input offset voltage

Input leakage current

Input voltage range

AC startup time

I_lk

<10

50

-0.1

AV_CC

V

50

0

µs

V_hys1

V_hys2

V_hys3

Hysteresis, none

Hysteresis, small

Hysteresis, large

V_CC= 1.6V - 3.6V

V_CC= 3.0V, T = 85°C

V_CC= 3.0V

15

30

20

17

0.3

5

mV

40

0.5

6

t_delay

Propagation delay

ns

64-level voltage scaler

Integral non-linearity (INL)

lsb

%

Current source accuracy after calibration

Current source calibration range

Single mode

4

µA

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32.1.8 Bandgap and Internal 1.0V Reference Characteristics

Table 32-13. Bandgp and Internal 1.0V Reference Characteristics

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

As reference for ADC

As input voltage to ADC and AC

1 Clk_PER+ 2.5µs

Startup time

µs

1.5

1.1

1

Bandgap voltage

V

INT1V

Internal 1.00V reference

T = 85°C, after calibration

Calibrated at T = 85°C

0.99

1.01

Variation over voltage and temperature

1

%

32.1.9 Brownout Detection Characteristics

Table 32-14. Brownout Detection Characteristics ⁽¹⁾

Symbol Parameter (BOD level 0 at 85°C)

BOD level 0 falling V_CC

Condition

Min.

Typ.

1.60

1.8

Max.

Units

1.40

1.70

BOD level 1 falling V_CC

BOD level 2 falling V_CC

2.0

BOD level 3 falling V_CC

V_BOT

2.2

V

BOD level 4 falling V_CC

2.4

BOD level 5 falling V_CC

BOD level 6 falling V_CC

BOD level 7 falling V_CC

2.6

2.8

3.0

Continuous mode

Sampled mode

0.4

t_BOD

Detection time

Hysteresis

µs

%

1000

1.0

V_HYST

Note:

1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.

32.1.10 External Reset Characteristics

Table 32-15. External Reset Characteristics

Symbol Parameter

Condition

Min.

Typ.

90

Max.

Units

t_EXT

V_RST

R_RST

Minimum reset pulse width

Reset threshold voltage

Reset pin pull-up resistor

1000

ns

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 2.7V

0.45 * V_CC

0.42 * V_CC

25

V

k

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32.1.11 Power-on Reset Characteristics

Table 32-16. Power-on Reset Characteristics

Symbol Parameter

Condition

Min.

0.4

Typ.

1.0

Max.

Units

V_CCfalls faster than 1V/ms

V_CCfalls at 1V/ms or slower

(1)

V_POT-

POR threshold voltage falling V_CC

POR threshold voltage rising V_CC

0.8

1.3

V

V_POT+

1.3

1.59

Note:

1. V_POT-values are only valid when BOD is disabled. When BOD is enabled V_POT-= V_POT+

.

32.1.12 Flash and EEPROM Memory Characteristics

Table 32-17. Endurance and Data Retention

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

10K

2K

Write/Erase cycles

Cycle

Flash

100

25

Data retention

Year

Cycle

Year

10

100K

30K

100

25

Write/Erase cycles

Data retention

EEPROM

10

Table 32-18. Programming Time

Symbol Parameter

Chip erase ⁽²⁾

Condition

Min.

Typ. ⁽¹⁾

Max.

Units

32KB Flash, EEPROM

Section erase

Page erase

50

6

Application erase

4

Flash

Page write

4

ms

Atomic page erase and write

Page erase

8

4

EEPROM

Page write

4

Atomic page erase and write

8

Notes:

1. Programming is timed from the 2MHz internal oscillator.

2. EEPROM is not erased if the EESAVE fuse is programmed.

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32.1.13 Clock and Oscillator Characteristics

32.1.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics

Table 32-19. 32.768kHz Internal Oscillator Characteristics

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

Frequency

32.768

kHz

Factory calibration accuracy

User calibration accuracy

T = 85C, V_CC= 3.0V

-0.5

0.5

%

32.1.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics

Table 32-20. 2MHz Internal Oscillator Characteristics

Symbol Parameter

Frequency range

Condition

Min.

Typ.

2.0

Max.

Units

DFLL can tune to this frequency over

voltage and temperature

1.8

2.2

MHz

Factory calibrated frequency

Factory calibration accuracy

User calibration accuracy

DFLL calibration stepsize

2.0

T = 85C, V_CC= 3.0V

-1.5

-0.2

1.5

0.2

%

0.18

32.1.13.3 Calibrated 32MHz Internal Oscillator Characteristics

Table 32-21. 32MHz Internal Oscillator Characteristics

Symbol Parameter

Frequency range

Condition

Min.

Typ.

32

Max.

Units

DFLL can tune to this frequency over

voltage and temperature

30

55

MHz

Factory calibrated frequency

Factory calibration accuracy

User calibration accuracy

DFLL calibration step size

32

T = 85C, V_CC= 3.0V

-1.5

-0.2

1.5

0.2

%

0.19

32.1.13.4 32kHz Internal ULP Oscillator Characteristics

Table 32-22. 32kHz Internal ULP Oscillator Characteristics

Symbol Parameter

Factory calibrated frequency

Condition

Min.

Typ.

Max.

Units

32

kHz

Factory calibration accuracy

Accuracy

T = 85°C, V_CC= 3.0V

-12

-30

12

30

%

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32.1.13.5 Internal Phase Locked Loop (PLL) Characteristics

Table 32-23. Internal PLL Characteristics

Symbol Parameter

Condition

Min.

0.4

20

Typ.

Max.

64

Units

f_IN

Input frequency

Output frequency must be within f_OUT

V_CC= 1.6 - 1.8V

48

MHz

f_OUT

Output frequency ⁽¹⁾

V_CC= 2.7 - 3.6V

20

128

Start-up time

Re-lock time

25

µs

Note:

1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.

32.1.13.6 External Clock Characteristics

Figure 32-3. External Clock Drive Waveform

t_CH

t_CR

t_CF

V_IH1

V_IL1

t_CL

t_CK

Table 32-24. External Clock used as System Clock without Prescaling

Symbol

Parameter

Condition

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

Min.

0

Typ.

Max.

12

Units

1/t_CK

Clock Frequency ⁽¹⁾

MHz

0

32

83.3

31.5

30.0

12.5

30.0

12.5

t_CK

t_CH

t_CL

t_CR

Clock Period

Clock High Time

Clock Low Time

ns

10

3

Rise Time (for maximum frequency)

10

3

t_CF

Fall Time (for maximum frequency)

t_CK

Change in period from one clock cycle to the next

10

%

Note:

1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

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Table 32-25. External Clock with Prescaler ⁽¹⁾for System Clock

Symbol Parameter

Condition

Min.

0

Typ.

Max.

90

Units

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

1/t_CK

Clock Frequency ⁽²⁾

Clock Period

MHz

0

142

11

7

t_CK

4.5

2.4

4.5

2.4

t_CH

Clock High Time

t_CL

Clock Low Time

ns

1.5

1.0

1.5

1.0

10

t_CR

Rise Time (for maximum frequency)

t_CF

Fall Time (for maximum frequency)

t_CK

Change in period from one clock cycle to the next

%

Notes:

1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.

2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

32.1.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics

Table 32-26. External 16MHz Crystal Oscillator and XOSC Characteristics

Symbol Parameter

Condition

Min.

Typ.

0

Max.

Units

FRQRANGE=0

XOSCPWR=0

XOSCPWR=1

XOSCPWR=0

XOSCPWR=1

Cycle to cycle jitter

FRQRANGE=1, 2, or 3

0

ns

FRQRANGE=0

0

Long term jitter

Frequency error

FRQRANGE=1, 2, or 3

0

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

0.03

0.003

50

XOSCPWR=0

XOSCPWR=1

XOSCPWR=0

XOSCPWR=1

%

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

50

Duty cycle

50

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Symbol Parameter

Condition

Min.

Typ.

Max.

Units

0.4MHz resonator,

CL=100pF

44k

XOSCPWR=0,

FRQRANGE=0

1MHz crystal, CL=20pF

2MHz crystal, CL=20pF

2MHz crystal

67k

82k

XOSCPWR=0,

FRQRANGE=1,

CL=20pF

8MHz crystal

1500

2700

1000

3600

1300

590

9MHz crystal

8MHz crystal

XOSCPWR=0,

FRQRANGE=2,

CL=20pF

Negative impedance ⁽¹⁾

R_Q

9MHz crystal

12MHz crystal

9MHz crystal

XOSCPWR=0,

FRQRANGE=3,

CL=20pF

12MHz crystal

16MHz crystal

9MHz crystal



390

XOSCPWR=1,

FRQRANGE=0,

CL=20pF

12MHz crystal

16MHz crystal

9MHz crystal

50

10

1500

650

XOSCPWR=1,

FRQRANGE=1,

CL=20pF

12MHz crystal

16MHz crystal

12MHz crystal

270

Negative impedance ⁽¹⁾

XOSCPWR=1,

FRQRANGE=2,

CL=20pF

1000

R_Q

16MHz crystal

12MHz crystal

16MHz crystal

440

1300

590

XOSCPWR=1,

FRQRANGE=3,

CL=20pF

ESR

SF = safety factor

min(R_Q)/SF

k

XOSCPWR=0,

FRQRANGE=0

0.4MHz resonator,

CL=100pF

1.0

2.6

0.8

1.0

1.4

XOSCPWR=0,

FRQRANGE=1

2MHz crystal, CL=20pF

8MHz crystal, CL=20pF

12MHz crystal, CL=20pF

16MHz crystal, CL=20pF

XOSCPWR=0,

FRQRANGE=2

Start-up time

ms

XOSCPWR=0,

FRQRANGE=3

XOSCPWR=1,

FRQRANGE=3

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Symbol Parameter

Condition

Min.

Typ.

Max.

Units

Parasitic capacitance

XTAL1 pin

C_XTAL1

5.9

Parasitic capacitance

XTAL2 pin

pF

C_XTAL2

C_LOAD

8.3

3.5

Parasitic capacitance load

Note:

1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.

32.1.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics

Table 32-27. External 32.768kHz Crystal Oscillator and TOSC Characteristics

Symbol Parameter

Condition

Min.

Typ.

Max.

60

Units

Crystal load capacitance 6.5pF

Crystal load capacitance 9.0pF

Crystal load capacitance 12pF

Recommended crystal equivalent

ESR/R1

35

k

series resistance (ESR)

28

C_TOSC1

C_TOSC2

Parasitic capacitance TOSC1 pin

Parasitic capacitance TOSC2 pin

3.5

pF

Capacitance load matched to crystal

specification

Recommended safety factor

3

Note:

See Figure 32-11 on page 97 for definition.

Figure 32-4. TOSC Input Capacitance

C_L1

C_L2

Device internal

External

TOSC1

TOSC2

32.768 kHz crystal

The parasitic capacitance between the TOSC pins is C_L1+ C_L2in series as seen from the crystal when oscillating without

external capacitors.

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32.1.14 SPI Characteristics

Figure 32-5. SPI Timing Requirements in Master Mode

SS

t_MOS

t_SCKR

t_SCKF

SCK

(CPOL = 0)

t_SCKW

SCK

(CPOL = 1)

t_SCKW

t_MIS

t_MIH

MSB

t_SCK

MISO

(Data Input)

LSB

t_MOH

MOSI

(Data Output)

MSB

LSB

Figure 32-6. SPI Timing Requirements in Slave Mode

SS

t_SSS

t_SCKR

t_SCKF

t_SSH

SCK

(CPOL = 0)

t_SSCKW

SCK

(CPOL = 1)

t_SSCKW

t_SIS

t_SIH

MSB

t_SSCK

LSB

MOSI

(Data Input)

t_SOSSS

t_SOS

t_SOSSH

MISO

(Data Output)

MSB

LSB

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Table 32-28. SPI Timing Characteristics and Requirements

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

(See Table 20-3 in

XMEGA D manual)

t_SCK

SCK period

Master

t_SCKW

t_SCKR

t_SCKF

t_MIS

SCK high/low width

SCK rise time

Master

Slave

0.5 * SCK

2.7

SCK fall time

2.7

MISO setup to SCK

MISO hold after SCK

MOSI setup SCK

MOSI hold after SCK

Slave SCK Period

SCK high/low width

SCK rise time

10

t_MIH

10

0.5 * SCK

1

t_MOS

t_MOH

t_SSCK

t_SSCKW

t_SSCKR

t_SSCKF

t_SIS

4 * t Clk_PER

2 * t Clk_PER

ns

1600

SCK fall time

MOSI setup to SCK

MOSI hold after SCK

SS setup to SCK

SS hold after SCK

MISO setup SCK

MISO hold after SCK

MISO setup after SS low

MISO hold after SS high

3

t Clk_PER

21

t_SIH

t_SSS

t_SSH

20

t_SOS

8

13

11

8

t_SOH

t_SOSS

t_SOSH

32.1.15 Two-wire Interface Characteristics

Table 32-29 on page 81 describes the requirements for devices connected to the two-wire interface bus. The Atmel AVR

XMEGA two-wire interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to

Figure 32-7.

Figure 32-7. Two-wire Interface Bus Timing

t_of

t_HIGH

t_LOW

t_r

SCL

SDA

t_HD;DAT

t_SU;STA

t_SU;STO

t_SU;DAT

t_HD;STA

t_BUF

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Table 32-29. Two-wire Interface Characteristics

Symbol Parameter

Condition

Min.

0.7V_CC

-0.5

Typ.

Max.

V_CC+ 0.5

0.3V_CC

Units

V_IH

V_IL

V_hys

V_OL

t_r

Input high voltage

Input low voltage

V

(1)

Hysteresis of Schmitt trigger inputs

Output low voltage

0.05V_CC

0

3mA, sink current

0.4

300

250

50

(1)(2)

Rise time for both SDA and SCL

Output fall time from V_IHminto V_ILmax

Spikes suppressed by input filter

Input current for each I/O pin

Capacitance for each I/O pin

SCL clock frequency

20 + 0.1C_b

t_of

10pF < C_b< 400pF ⁽²⁾

0.1V_CC< V_I< 0.9V_CC

20 + 0.1C_b

ns

t_SP

I_I

0

-10

10

µA

pF

C_I

10

f_SCL

f_PER⁽³⁾> max(10f_SCL, 250kHz)

f_SCL 100kHz

0

400

kHz

100ns

--------------

C_b

V_CC– 0.4V

---------------------------

3mA

R_P

Value of pull-up resistor



300ns

f_SCL> 100kHz

--------------

C_b

f_SCL 100kHz

f_SCL> 100kHz

f_SCL 100kHz

f_SCL> 100kHz

f_SCL 100kHz

f_SCL> 100kHz

f_SCL 100kHz

f_SCL> 100kHz

f_SCL 100kHz

f_SCL> 100kHz

f_SCL 100kHz

f_SCL> 100kHz

f_SCL 100kHz

f_SCL> 100kHz

f_SCL 100kHz

f_SCL> 100kHz

4.0

0.6

4.7

1.3

4.0

0.6

4.7

0.6

0

t_HD;STA

Hold time (repeated) START condition

Low period of SCL clock

t_LOW

t_HIGH

High period of SCL clock

Set-up time for a repeated START

condition

t_SU;STA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

µs

3.45

0.9

Data hold time

0

250

100

4.0

0.6

4.7

1.3

Data setup time

Setup time for STOP condition

Bus free time between a STOP and

START condition

Notes:

1. Required only for f_SCL> 100kHz.

2. C_b= Capacitance of one bus line in pF.

3. f_PER= Peripheral clock frequency.

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32.2 Atmel ATxmega64D3

32.2.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 32-30 may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

Table 32-30. Absolute Maximum Ratings

Symbol

V_CC

I_VCC

I_GND

V_PIN

I_PIN

Parameter

Condition

Min.

Typ.

Max.

4

Units

Power supply voltage

Current into a V_CCpin

Current out of a Gnd pin

Pin voltage with respect to Gnd and V_CC

I/O pin sink/source current

Storage temperature

-0.3

V

200

mA

200

-0.5

-25

-65

V_CC+ 0.5

25

V

mA

T_A

150

°C

T_j

Junction temperature

150

32.2.2 General Operating Ratings

The device must operate within the ratings listed in Table 32-31 in order for all other electrical characteristics and typical

characteristics of the device to be valid.

Table 32-31. General Operating Conditions

Symbol

V_CC

Parameter

Condition

Min.

1.60

-40

Typ.

Max.

3.6

Units

Power supply voltage

Analog supply voltage

Temperature range

Junction temperature

V

AV_CC

T_A

3.6

85

°C

T_j

-40

105

Table 32-32. Operating Voltage and Frequency

Symbol

Parameter

Condition

V_CC= 1.6V

V_CC= 1.8V

V_CC= 2.7V

V_CC= 3.6V

Min.

Typ.

Max.

12

Units

0

12

Clk_CPU

CPU clock frequency

MHz

32

The maximum CPU clock frequency depends on V_CC. As shown in Figure 32-8 on page 83 the frequency vs. V_CCcurve is

linear between 1.8V < V_CC< 2.7V.

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Figure 32-8. Maximum Frequency vs. V_CC

MHz

32

Safe operating area

12

V

1.6

1.8

2.7

3.6

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32.2.3 Current Consumption

Table 32-33. Current Consumption for Active Mode and Sleep Modes

Symbol Parameter

Condition

Min.

Typ.

50

Max. Units

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

32kHz, Ext. Clk

130

215

475

445

0.95

7.8

2.8

3

µA

1MHz, Ext. Clk

Active power

consumption ⁽¹⁾

600

2MHz, Ext. Clk

32MHz, Ext. Clk

32kHz, Ext. Clk

1.5

mA

12.0

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

46

1MHz, Ext. Clk

2MHz, Ext. Clk

µA

Idle power

92

consumption ⁽¹⁾

93

225

350

184

2.9

0.07

1.3

4.0

1.3

2.6

5.0

1.7

1.8

0.5

0.7

0.9

1.2

120

V_CC= 3.0V

I_CC

32MHz, Ext. Clk

5.0

1.0

5.0

8.0

2.0

6.0

10

mA

T = 25°C

T = 85°C

V_CC= 3.0V

T = 105°C

Power-down power

consumption

WDT and sampled BOD enabled, T = 25°C

WDT and sampled BOD enabled, T = 85°C

WDT and sampled BOD enabled, T= 105°C

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

µA

RTC from ULP clock, WDT and sampled

BOD enabled, T = 25°C

2.0

3.0

Power-save power

consumption ⁽²⁾

RTC from 1.024kHz low power 32.768kHz

TOSC, T = 25°C

RTC from low power 32.768kHz TOSC,

T = 25°C

Reset power consumption Current through RESET pin substracted

Notes:

1. All Power Reduction Registers set.

2. Maximum limits are based on characterization, and not tested in production.

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Table 32-34. Current Consumption for Modules and Peripherals

Symbol Parameter

Condition ⁽¹⁾

Min.

Typ.

0.9

29

Max.

Units

ULP oscillator

32.768kHz int. oscillator

82

2MHz int. oscillator

32MHz int. oscillator

DFLL enabled with 32.768kHz int. osc. as reference

114

250

400

µA

20× multiplication factor,

32MHz int. osc. DIV4 as reference

PLL

300

Watchdog timer

1.0

140

1.4

Continuous mode

BOD

Sampled mode, includes ULP oscillator

I_CC

Internal 1.0V reference

Temperature sensor

180

175

1.23

1.1

CURRLIMIT = LOW

16ksps

V_REF= Ext. ref.

CURRLIMIT = MEDIUM

0.98

0.87

CURRLIMIT = HIGH

ADC

mA

75ksps

CURRLIMIT = LOW

V_REF= Ext. ref.

1.7

3.1

300ksps

V_REF= Ext. ref.

USART

Rx and Tx enabled, 9600 BAUD

9.7

5

µA

Flash memory and EEPROM programming

mA

Note:

1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V_CC= 3.0V, Clk_SYS= 1MHz external clock

without prescaling, T = 25°C unless other conditions are given.

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32.2.4 Wake-up Time from Sleep Modes

Table 32-35. Device Wake-up Time from Sleep Modes with Various System Clock Sources

Symbol Parameter

Condition

Min.

Typ. ⁽¹⁾

2.0

Max.

Units

External 2MHz clock

Wake-up time from idle,

standby, and extended standby

mode

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

External 2MHz clock

125

2.0

0.2

t_wakeup

µs

4.6

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

330

9.5

Wake-up time from power-save

and power-down mode

5.6

Note:

1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-9. All peripherals and modules start

execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 32-9. Wake-up Time Definition

Wakeup time

Wakeup request

Clock output

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32.2.5 I/O Pin Characteristics

The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output

voltage limits reflect or exceed this specification.

Table 32-36. I/O Pin Characteristics