ATXMEGA32D4-ANR [MICROCHIP]
IC MCU 8BIT 32KB FLASH 44TQFP;型号: | ATXMEGA32D4-ANR |
厂家: | MICROCHIP |
描述: | IC MCU 8BIT 32KB FLASH 44TQFP |
文件: | 总328页 (文件大小:23267K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
8/16-bit Atmel XMEGA D4 Microcontroller
ATxmega128D4 / ATxmega64D4 /
ATxmega32D4 / ATxmega16D4
Features
High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
16K - 128KBytes of in-system self-programmable flash
4K - 8KBytes boot section
1K - 2KBytes EEPROM
2K - 8KBytes internal SRAM
Peripheral Features
Four-channel event system
Four 16-bit timer/counters
Two timer/counters with 4 output compare or input capture channels
Two timer/counters with 2 output compare or input capture channels
High-resolution extensions on all timer/counters
Advanced waveform extension (AWeX) on one timer/counter
Two USARTs with IrDA support for one USART
Two two-wire interfaces with dual address match (I2C and SMBus compatible)
Two serial peripheral interfaces (SPIs)
CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) generator
16-bit real time counter (RTC) with separate oscillator
One twelve-channel, 12-bit, 200ksps Analog to Digital Converter
Two Analog Comparators with window compare function, and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interfaces
PDI (program and debug interface)
I/O and packages
34 Programmable I/O pins
44 - lead TQFP
44 - pad VQFN/QFN
49 - ball VFBGA
Operating voltage
1.6 – 3.6V
Operating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
1.
Ordering Information
Flash
EEPROM
(Bytes)
SRAM
(Bytes)
Speed
(MHz)
Power
Supply
Ordering Code
ATxmega128D4-AU
(Bytes)
128K + 8K
128K + 8K
64K + 4K
64K + 4K
32K + 4K
32K + 4K
16K + 4K
16K + 4K
128K + 8K
128K + 8K
64K + 4K
64K + 4K
32K + 4K
32K + 4K
16K + 4K
16K + 4K
128K + 8K
128K + 8K
64K + 4K
64K + 4K
32K + 4K
32K + 4K
16K + 4K
16K + 4K
Package(1)(2)(3)
Temp
2K
2K
2K
2K
1K
1K
1K
1K
2K
2K
2K
2K
1K
1K
1K
1K
2K
2K
2K
2K
1K
1K
1K
1K
8K
8K
4K
4K
4K
4K
2K
2K
8K
8K
4K
4K
4K
4K
2K
2K
8K
8K
4K
4K
4K
4K
2K
2K
ATxmega128D4-AUR(4)
ATxmega64D4-AU
ATxmega64D4-AUR(4)
ATxmega32D4-AU
44A
ATxmega32D4-AUR(4)
ATxmega16D4-AU
ATxmega16D4-AUR(4)
ATxmega128D4-MH
ATxmega128D4-MHR(4)
ATxmega64D4-MH
ATxmega64D4-MHR(4)
ATxmega32D4-MH
32
1.6 - 3.6V
44M1
-40C - 85C
ATxmega32D4-MHR(4)
ATxmega16D4-MH
ATxmega16D4-MHR(4)
ATxmega128D4-CU
ATxmega128D4-CUR(4)
ATxmega64D4-CU
ATxmega64D4-CUR(4)
ATxmega32D4-CU
49C2
ATxmega32D4-CUR(4)
ATxmega16D4-CU
ATxmega16D4-CUR(4)
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
2
Flash
(Bytes)
EEPROM
(Bytes)
SRAM
(Bytes)
Speed
(MHz)
Power
Supply
Ordering Code
ATxmega128D4-AN
ATxmega128D4-ANR(4)
ATxmega64D4-AN
Package(1)(2)(3)
Temp
128K + 8K
128K + 8K
64K + 4K
64K + 4K
32K + 4K
32K + 4K
16K + 4K
16K + 4K
128K + 8K
128K + 8K
64K + 4K
64K + 4K
32K + 4K
32K + 4K
16K + 4K
16K + 4K
2K
2K
2K
2K
1K
1K
1K
1K
2K
2K
2K
2K
1K
1K
1K
1K
8K
8K
4K
4K
4K
4K
2K
2K
8K
8K
4K
4K
4K
4K
2K
2K
ATxmega64D4-ANR(4)
ATxmega32D4-AN
44A
ATxmega32D4-ANR(4)
ATxmega16D4-AN
ATxmega16D4-ANR(4)
ATxmega128D4-M7
ATxmega128D4-M7R(4)
ATxmega64D4-M7
32
1.6 - 3.6V
-40C - 105C
ATxmega64D4-M7R(4)
ATxmega32D4-M7
44M1
ATxmega32D4-M7R(4)
ATxmega16D4-M7
ATxmega16D4-M7R(4)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information see ”Packaging information” on page 64.
4. Tape and Reel.
Package type
44-lead, 10*10mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
44-Pad, 7*7*1mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad no lead package (VQFN)
49-ball (7 * 7 Array), 0.65mm pitch, 5.0*5.0*1.0mm, very thin, fine-pitch ball grid array package (VFBGA)
44A
44M1
49C2
Typical Applications
Industrial control
Climate control
RF and ZigBee®
USB connectivity
Sensor control
Optical
Low power battery applications
Power tools
Factory automation
Building control
HVAC
Board control
Utility metering
White goods
Medical applications
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
3
2.
Pinout/Block diagram
Figure 2-1. Block Diagram and QFN/TQFP Pinout
Power
Programming, debug, test
Ground
Digital function
Analog function / Oscillators
External clock / Crystal pins
General Purpose I /O
Port R
XOSC
TOSC
PA5
PA6
PA7
PB0
PB1
PB2
PB3
GND
VCC
PC0
PC1
1
2
33
32
31
30
29
28
27
26
25
24
23
PE3
PE2
VCC
GND
PE1
PE0
PD7
PD6
PD5
PD4
PD3
DATA BUS
OSC/CLK
Control
Internal
oscillators
Power
Watchdog
Supervision
AREF
3
Sleep
Controller
Real Time
Counter
Watchdog
Timer
Reset
Controller
ADC
AC0:1
4
Event System
Controller
Prog/Debug
Interface
CRC
OCD
5
Interrupt
Controller
BUS
matrix
AREF
6
Internal
references
CPU
7
8
SRAM
FLASH
EEPROM
DATA BUS
9
EVENT ROUTING NETWORK
10
11
Port C
Port D
Port E
Note:
1. For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 49.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
4
Figure 2-2. VFBGA Pinout
Top view
1 2 3 4 5 6 7
Bottom view
7 6 5 4 3 2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
G
1
2
3
4
5
PR0
6
7
A
B
C
D
E
F
PA3
PA4
PA5
PB1
GND
VCC
PC1
AVCC
PA1
GND
PA0
PA6
PB3
PC3
PC4
PC5
PR1
GND
PA7
PB0
GND
PC6
PC7
PDI
PE3
VCC
GND
PE0
PD6
PD3
PD2
RESET/PDI_CLK
GND
PE2
PE1
PD7
PD5
PD1
VCC
PA2
PB2
GND
PC0
PC2
GND
PD4
PD0
G
GND
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
5
3.
Overview
The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based
on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA device
achieves throughputs CPU approaching one million instructions per second (MIPS) per megahertz, allowing the system
designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The AVR XMEGA D4 devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; four-channel event system and programmable multilevel interrupt controller,
34 general purpose I/O lines, 16-bit real-time counter (RTC); four flexible, 16-bit timer/counters with compare and PWM
channels; two USARTs; two two-wire serial interfaces (TWIs); two serial peripheral interfaces (SPIs); one twelve-
channel, 12-bit ADC with optional differential input with programmable gain; two analog comparators (ACs) with window
mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and
prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.
The XMEGA D4 devices have five software selectable power saving modes. The idle mode stops the CPU while allowing
the SRAM, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves
the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, or pin-change
interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to
maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps
running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low
power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To
further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active
mode and idle sleep mode.
Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI interface. A boot loader running in the device can use any interface to
download the application program to the flash memory. The boot loader software in the boot flash section will continue to
run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit
RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a
highly flexible and cost effective solution for many embedded applications.
All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
6
3.1
Block Diagram
Figure 3-1. XMEGA D4 Block Diagram
PR[0..1]
Digital function
Analog function
Programming, debug, test
Oscillator/Crystal/Clock
General Purpose I/O
XTAL/
TOSC1
XTAL2/
TOSC2
Oscillator
Circuits/
Clock
Real Time
Counter
Watchdog
Oscillator
PORT R (2)
Generation
DATA BUS
Watchdog
Timer
ACA
Event System
Controller
Oscillator
Control
Sleep
Controller
Power
Supervision
POR/BOD &
RESET
PA[0..7]
PORT A (8)
ADCA
VCC
GND
SRAM
BUS Matrix
AREFA
VCC/10
Int. Refs.
Tempref
AREFB
RESET/
Interrupt
Prog/Debug
Controller
PDI_CLK
PDI
Controller
PDI_DATA
CPU
CRC
OCD
NVM Controller
PB[0..3]
PORT B (4)
Flash
EEPROM
DATA BUS
EVENT ROUTING NETWORK
To Clock
Generator
PORT C (8)
PORT D (8)
PORT E (4)
TOSC1
TOSC2
PC[0..7]
PD[0..7]
PE[0..3]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
7
4.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
4.1
Recommended Reading
Atmel AVR XMEGA D manual
XMEGA application notes
This device data sheet only contains part specific information with a short description of each peripheral and module. The
XMEGA D manual describes the modules and peripherals in depth. The XMEGA application notes contain example code
and show applied use of the modules and peripherals.
All documentations are available from www.atmel.com/avr.
5.
Capacitive Touch Sensing
The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced
reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key
events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Atmel website at the following location:
http://www.atmel.com/tools/QTOUCHLIBRARY.aspx. For implementation details and other information, refer to the
QTouch library user guide - also available for download from the Atmel website.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
8
6.
AVR CPU
6.1
Features
8/16-bit, high-performance Atmel AVR RISC CPU
137 instructions
Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack pointer accessible in I/O memory space
Direct addressing of up to 16MB of program memory and 16MB of data memory
True 16/24-bit access to 16/24-bit I/O registers
Efficient support for 8-, 16-, and 32-bit arithmetic
Configuration change protection of system-critical features
6.2
6.3
Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable
Multilevel Interrupt Controller” on page 27.
Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 6-1. Block Diagram of the AVR CPU Architecture
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
9
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be
memory mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-
programming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for safe storing of nonvolatile data in the program memory.
6.4
ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the
status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
6.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
10
6.5
Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.6
Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 15.
6.8
Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
11
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
7.
Memories
7.1
Features
Flash program memory
One linear address space
In-system programmable
Self-programming and boot loader support
Application section for application code
Application table section for application code or data storage
Boot section for application code or boot loader code
Separate read/write protection lock bits for all sections
Built in fast CRC check of a selectable flash program memory section
Data memory
One linear address space
Single-cycle access from CPU
SRAM
EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
I/O memory
Configuration and status registers for all peripherals and modules
16 bit-accessible general purpose registers for global variables or flags
Production signature row memory for factory programmed data
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
User signature row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2
Overview
The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code
can reside only in the program memory, while data can be stored in the program memory and the data memory. The data
memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write
operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a
Flash memory signature row for calibration data, device identification, serial number etc.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
12
7.3
Flash Program Memory
The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The
flash memory can be accessed for read and write from an external programmer through the PDI or from application
software running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store
program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate
when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 7-1. Flash Program Memory (Hexadecimal Address)
Word address
ATxmega128D4
ATxmega64D4
ATxmega32D4
ATxmega16D4
0
0
0
0
Application section
(128K/64K/32K/16K)
...
EFFF
F000
/
/
/
/
/
77FF
7800
7FFF
8000
87FF
/
/
/
/
/
37FF
3800
3FFF
4000
47FF
/
/
/
/
/
17FF
1800
1FFF
2000
27FF
Application table section
(8K/4K/4K/4K)
FFFF
10000
10FFF
Boot section
(8K/4K/4K/4K)
7.3.1 Application Section
The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
7.3.2 Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
7.3.3 Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can only initiate programming when executing from this section. The SPM
instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader
section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code
can be stored here.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
13
7.3.4 Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical
Characteristics” on page 64.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device. The device ID for the available devices is shown in Table 7-1 on page 14.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 7-1. Device ID Bytes for Atmel AVR XMEGA D4 Devices
Device
Device ID bytes
Byte 1
Byte 2
42
Byte 0
1E
ATxmega16D4
ATxmega32D4
ATxmega64D4
ATxmega128D4
94
95
96
97
42
1E
47
1E
47
1E
7.3.5 User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
7.4
Fuses and Lock Bits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, startup configuration, JTAG enable, and JTAG user ID.
The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
7.5
Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory
if available. The data memory is organized as one continuous memory section, see Figure 7-2 on page 15. To simplify
development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA
devices.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
14
Figure 7-2. Data Memory Map (Hexadecimal Address)
Byte address
ATxmega64D4
Byte address
ATxmega32D4
Byte address
ATxmega16D4
0
0
0
I/O Registers (4K)
I/O Registers (4K)
I/O Registers (4K)
FFF
1000
17FF
FFF
1000
13FF
FFF
1000
13FF
EEPROM (2K)
RESERVED
EEPROM (1K)
RESERVED
EEPROM (1K)
RESERVED
2000
2FFF
2000
2FFF
2000
27FF
Internal SRAM (4K)
Internal SRAM (4K)
Internal SRAM (2K)
Byte address
ATxmega128D4
0
FFF
I/O Registers (4K)
1000
17FF
EEPROM (2K)
RESERVED
2000
3FFF
Internal SRAM (8K)
7.6
7.7
EEPROM
XMEGA D devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default)
or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory
mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is
accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address
0x1000.
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA D4 is shown in the “Peripheral Module Address Map”
on page 54.
7.7.1 General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
15
7.8
7.9
Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the bus masters (CPU, etc.) can access different
memory sections at the same time.
Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst
read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and
instruction timing.
7.10 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
7.11 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
7.12 Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-2 on page 16 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and
erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash
access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page
number and the least significant address bits (FWORD) give the word in the page.
Table 7-2. Number of Words and Pages in the Flash
Devices
PC size
bits
14
Flash size
bytes
Page Size
words
128
FWORD
FPAGE
Application
Boot
Size
16K
No of pages
Size
4K
No of pages
ATxmega16D4
ATxmega32D4
ATxmega64D4
ATxmega128D4
16K + 4K
32K + 4K
64K + 4K
128K + 8K
Z[7:1]
Z[7:1]
Z[7:1]
Z[9:1]
Z[13:8]
Z[14:8]
Z[15:8]
Z[16:8]
64
16
16
16
32
15
128
32K
128
256
512
4K
16
128
64K
4K
17
128
128K
8K
Table 7-3 on page 17 shows EEPROM memory organization for the Atmel AVR XMEGA D4 devices. EEEPROM write
and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at
a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in
the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
16
Table 7-3. Number of Bytes and Pages in the EEPROM
Devices
EEPROM
Size
1K
Page Size
E2BYTE
E2PAGE
No of Pages
bytes
32
ATxmega16D4
ATxmega32D4
ATxmega64D4
ATxmega128D4
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
32
32
64
64
1K
32
2K
32
2K
32
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
17
8.
Event System
8.1
Features
System for direct peripheral-to-peripheral communication and signaling
Peripherals can directly send, receive, and react to peripheral events
CPU independent operation
100% predictable signal timing
Short and guaranteed response time
Four event channels for up to four different and parallel signal routing configurations
Events can be sent and/or used by most peripherals, clock system, and software
Additional functions include
Quadrature decoders
Digital filtering of I/O pin state
Works in active mode and idle sleep mode
8.2
Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts, CPU, and is thus a powerful tool for reducing the complexity, size and execution time of
application code. It also allows for synchronized timing of actions in several peripheral modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure 8-1 shows a basic diagram of all connected peripherals. The event system can directly connect together analog to
digital converter, analog comparators, I/O port pins, the real-time counter, timer/counters, and IR communication module
(IRCOM). Events can also be generated from software and the peripheral clock.
Figure 8-1. Event System Overview and Connected Peripherals
CPU /
Software
Event Routing Network
clkPER
Prescaler
ADC
Event
Real Time
Counter
System
Controller
Timer /
Counters
AC
Port pins
IRCOM
The event routing network consists of four software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to four parallel event routing configurations. The maximum
routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
18
9.
System Clock and Clock Options
9.1
Features
Fast start-up time
Safe run-time clock switching
Internal oscillators:
32MHz run-time calibrated and tuneable oscillator
2MHz run-time calibrated oscillator
32.768kHz calibrated oscillator
32kHz ultra low power (ULP) oscillator with 1kHz output
External clock options
0.4MHz - 16MHz crystal oscillator
32.768kHz crystal oscillator
External clock
PLL with 20MHz - 128MHz output frequency
Internal and external clock options and 1x to 31x multiplication
Lock detector
Clock prescalers with 1x to 2048x division
Fast peripheral clocks running at two and four times the CPU clock
Automatic run-time calibration of internal oscillators
External oscillator and PLL lock failure detection with optional non-maskable interrupt
9.2
Overview
Atmel AVR XMEGA D4 devices have a flexible clock system supporting a large number of clock sources. It incorporates
both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked
loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL)
is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over
voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the
internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and
prescalers can be changed from software at any time.
Figure 9-1 on page 20 presents the principal clock system in the XMEGA D4 family of devices. Not all of the clocks need
to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power
reduction registers, as described in “Power Management and Sleep Modes” on page 22.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
19
Figure 9-1. The Clock System, Clock Sources and Clock Distribution
Real Time
Counter
Non-Volatile
Memory
Peripherals
RAM
AVR CPU
clkPER
clkPER2
clkPER4
clkCPU
System Clock Prescalers
clkSYS
Brown-out
Detector
Watchdog
Timer
clkRTC
System Clock Multiplexer
(SCLKSEL)
RTCSRC
PLL
PLLSRC
XOSCSEL
32 kHz
Int. ULP
32.768 kHz
Int. OSC
32.768 kHz
TOSC
0.4 – 16 MHz
XTAL
32 MHz
Int. Osc
2 MHz
Int. Osc
9.3
Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other
clock sources, DFLLs and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
9.3.1 32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
20
1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC.
9.3.2 32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
9.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator
can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.
9.3.4 0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.
9.3.5 2MHz Run-time Calibrated Internal Oscillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during
production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time
calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
9.3.6 32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz.
9.3.7 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a
32.768kHz crystal oscillator.
9.3.8 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-
selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output
frequencies from all clock sources.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
21
10. Power Management and Sleep Modes
10.1 Features
Power management for adjusting power consumption and functions
Five sleep modes
Idle
Power down
Power save
Standby
Extended standby
Power reduction register to disable clock and turn off unused peripherals in active and idle modes
10.2 Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
10.3 Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
10.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, and event system are kept running. Any enabled interrupt will wake the
device.
10.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-
wire interface address match interrupt, and asynchronous port interrupts.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
22
10.3.3 Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
10.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
10.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
23
11. System Control and Reset
11.1 Features
Reset the microcontroller and set it to initial state when a reset source goes active
Multiple reset sources that cover different situations
Power-on reset
External reset
Watchdog reset
Brownout reset
PDI reset
Software reset
Asynchronous operation
No running system clock in the device is required for reset
Reset status register for reading the reset source from the application code
11.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset
source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins
are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their
initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of
the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
11.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
Reset counter delay
Oscillator startup
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
24
11.4 Reset Sources
11.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
11.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
11.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
11.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one
to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 26.
11.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
11.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
25
12. WDT – Watchdog Timer
12.1 Features
Issues a device reset if the timer is not reset before its timeout period
Asynchronous operation from dedicated oscillator
1kHz output of the 32kHz ultra low power oscillator
11 selectable timeout periods, from 8ms to 8s
Two operation modes:
Normal mode
Window mode
Configuration lock to prevent unwanted changes
12.2 Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
26
13. Interrupts and Programmable Multilevel Interrupt Controller
13.1 Features
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium and high
Selectable, round-robin priority scheme within low-level interrupts
Non-maskable interrupts for critical functions
Interrupt vectors optionally placed in the application section or the boot loader section
13.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
13.3 Interrupt Vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the Atmel AVR XMEGA D4 devices are shown in Table 13-1 on page 28. Offset
addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA D manual. For
peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 13-1 on page 28. The program
address is the word address.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
27
Table 13-1. Reset and Interrupt Vectors
Program Address
(Base Address)
0x000
0x002
0x004
0x008
0x014
0x018
0x01C
0x028
0x030
0x032
0x040
0x044
0x056
0x05A
0x05E
0x080
0x084
0x088
0x08E
0x09A
0x0AE
0x0B0
Source
Interrupt Description
RESET
OSCF_INT_vect
PORTC_INT_base
PORTR_INT_base
RTC_INT_base
TWIC_INT_base
TCC0_INT_base
TCC1_INT_base
SPIC_INT_vect
USARTC0_INT_base
NVM_INT_base
PORTB_INT_base
PORTE_INT_base
TWIE_INT_base
TCE0_INT_base
PORTD_INT_base
PORTA_INT_base
ACA_INT_base
ADCA_INT_base
TCD0_INT_base
SPID_INT_vector
USARTD0_INT_base
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Port R Interrupt base
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
Timer/Counter 1 on port C Interrupt base
SPI on port C Interrupt vector
USART 0 on port C Interrupt base
Non-Volatile Memory Interrupt base
Port B Interrupt base
Port E Interrupt base
Two-Wire Interface on Port E Interrupt base
Timer/Counter 0 on port E Interrupt base
Port D Interrupt base
Port A Interrupt base
Analog Comparator on Port A Interrupt base
Analog to Digital Converter on Port A Interrupt base
Timer/Counter 0 on port D Interrupt base
SPI on port D Interrupt vector
USART 0 on port D Interrupt base
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
28
14. I/O Ports
14.1 Features
34 general purpose input and output pins with individual configuration
Output driver with configurable driver and pull settings:
Totem-pole
Wired-AND
Wired-OR
Bus-keeper
Inverted I/O
Input with synchronous and/or asynchronous sensing with interrupts and events
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
Asynchronous pin change sensing that can wake the device from all sleep modes
Two port interrupts with pin masking per I/O port
Efficient and safe access to port pins
Hardware read-modify-write through dedicated toggle/clear/set registers
Configuration of multiple pins in a single operation
Mapping of port registers into bit-accessible I/O memory space
Peripheral clocks output on port pin
Real-time counter clock output to port pin
Event channels can be output on port pin
Remapping of digital peripheral pin functions
Selectable USART, SPI, and timer/counter input/output pin locations
14.2 Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable
driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for
selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from
all sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus
application needs.
The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, and PORTR.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
29
14.3 Output Driver
All port pins (Pxn) have programmable output configuration.
14.3.1 Push-pull
Figure 14-1. I/O Configuration - Totem-pole
DIRxn
OUTxn
INxn
Pxn
14.3.2 Pull-down
Figure 14-2. I/O Configuration - Totem-pole with Pull-down (on Input)
DIRxn
OUTxn
INxn
Pxn
14.3.3 Pull-up
Figure 14-3. I/O Configuration - Totem-pole with Pull-up (on Input)
DIRxn
OUTxn
INxn
Pxn
14.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level
was ‘1’, and pull-down if the last level was ‘0’.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
30
Figure 14-4. I/O Configuration - Totem-pole with Bus-keeper
DIRxn
OUTxn
INxn
Pxn
14.3.5 Others
Figure 14-5. Output Configuration - Wired-OR with Optional Pull-down
OUTxn
Pxn
INxn
Figure 14-6. I/O Configuration - Wired-AND with Optional Pull-up
INxn
Pxn
OUTxn
14.4 Input Sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 14-7.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
31
Figure 14-7. Input Sensing System Overview
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IRQ
Synchronous sensing
Pxn
Synchronizer
INn
EDGE
DETECT
Synchronous
Events
D
Q
D
Q
R
R
INVERTED I/O
Asynchronous
Events
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
14.5 Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for
that peripheral. “Pinout and Pin Functions” on page 49 shows which modules on peripherals that enable alternate
functions on a pin, and which alternate functions that are available on a pin.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
32
15. TC0/1 – 16-bit Timer/Counter Type 0 and 1
15.1 Features
Four 16-bit timer/counters
Three timer/counters of type 0
One timer/counter of type 1
32-bit timer/counter support by cascading two timer/counters
Up to four compare or capture (CC) channels
Four CC channels for timer/counters of type 0
Two CC channels for timer/counters of type 1
Double buffered timer period setting
Double buffered capture or compare channels
Waveform generation:
Frequency generation
Single-slope pulse width modulation
Dual-slope pulse width modulation
Input capture:
Input capture with noise cancelling
Frequency capture
Pulse width capture
32-bit input capture
Timer overflow and error interrupts/events
One compare match or input capture interrupt/event per CC channel
Can be used with event system for:
Quadrature decoding
Count and direction control
Capture
High-resolution extension
Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
Advanced waveform extension:
Low- and high-side output with programmable dead-time insertion (DTI)
Event controlled fault protection for safe disabling of drivers
15.2 Overview
Atmel AVR XMEGA devices have a set of four flexible 16-bit Timer/Counters (TC). Their capabilities include accurate
program execution timing, frequency and waveform generation, and input capture with time and frequency measurement
of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either
capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels
each.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
33
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high-
side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can
also generate a synchronized bit pattern across the port pins.
The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter.
This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 36 for more details.
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by
using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution
Extension” on page 37 for more details.
Figure 15-1. Overview of a Timer/Counter and Closely Related Peripherals
Timer/Counter
Base Counter
Prescaler
clkPER
Timer Period
Counter
Control Logic
Event
System
clkPER4
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
AWeX
Pattern
Generation
Fault
Dead-Time
Insertion
Capture
Comparator
Control
Protection
Waveform
Generation
Buffer
PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD and PORTE each has one Timer/Conter0. Notation
of these are TCC0 (Time/Counter C0), TCC1, TCD0 and TCE0, respectively.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
34
16. TC2 Timer/Counter Type 2
16.1 Features
Six eight-bit timer/counters
Three Low-byte timer/counter
Three High-byte timer/counter
Up to eight compare channels in each Timer/Counter 2
Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
Waveform generation
Single slope pulse width modulation
Timer underflow interrupts/events
One compare match interrupt/event per compare channel for the low-byte timer/counter
Can be used with the event system for count control
16.2 Overview
There are three Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of
two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation
(PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of
PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts and events. The two eight-bit timer/counters have a shared clock source and separate period and
compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event
system. The counters are always counting down.
PORTC, PORTD and PORTE each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2), TCD2 and
TCE2, respectively.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
35
17. AWeX – Advanced Waveform Extension
17.1 Features
Waveform output with complementary output from each compare channel
Four dead-time insertion (DTI) units
8-bit resolution
Separate high and low side dead-time setting
Double buffered dead time
Optionally halts timer during dead-time insertion
Pattern generation unit creating synchronised bit pattern across the port pins
Double buffered pattern generation
Optional distribution of one compare channel output across the port pins
Event controlled fault protection for instant and predictable fault triggering
17.2 Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)
modes. It is primarily intended for use with different types of motor control and other power control applications. It
enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external
drivers. It can also generate a synchronized bit pattern across the port pins.
Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any
AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non-
inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS
switching. The DTI output will override the normal port value according to the port override setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,
the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator
unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable
the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of
fault triggers.
The AWeX is available for TCC0. The notation of this is AWEXC.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
36
18. Hi-Res – High Resolution Extension
18.1 Features
Increases waveform generator resolution up to 8x (three bits)
Supports frequency, single-slope PWM, and dual-slope PWM generation
Supports the AWeX when this is used for the same timer/counter
18.2 Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a
timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM
generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled.
There is one hi-res extension that can be enabled for each timer/counter on PORTC. The notation of this is HIRESC.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
37
19. RTC – 16-bit Real-Time Counter
19.1 Features
16-bit resolution
Selectable clock source
32.768kHz external crystal
External clock
32.768kHz internal oscillator
32kHz internal ULP oscillator
Programmable 10-bit clock prescaling
One compare register
One period register
Clear counter on period overflow
Optional interrupt/event on overflow and compare match
19.2 Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs
a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal
oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
Figure 19-1. Real-time Counter Overview
External Clock
TOSC1
32.768kHz Crystal Osc
TOSC2
32.768kHz Int. Osc
32kHz int ULP (DIV32)
PER
RTCSRC
TOP/
clkRTC
10-bit
=
=
Overflow
CNT
prescaler
”match”/
Compare
COMP
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
38
20. TWI – Two-Wire Interface
20.1 Features
Two identical two-wire interface peripherals
Bidirectional, two-wire communication interface
Phillips I2C compatible
System Management Bus (SMBus) compatible
Bus master and slave operation supported
Slave operation
Single bus master operation
Bus master in multi-master bus environment
Multi-master arbitration
Flexible slave address match functions
7-bit and general call address recognition in hardware
10-bit addressing supported
Address mask register for dual address match or address range masking
Optional software address recognition for unlimited number of addresses
Slave can operate in all sleep modes, including power-down
Slave address match can wake device from all sleep modes
100kHz and 400kHz bus frequency support
Slew-rate limited output drivers
Input filter for bus noise and spike suppression
Support arbitration between start/repeated start and data bit (SMBus)
Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
20.2 Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to
transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command
and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
39
21. SPI – Serial Peripheral Interface
21.1 Features
Two identical SPI peripherals
Full-duplex, three-wire synchronous data transfer
Master or slave operation
Lsb first or msb first data transfer
Eight programmable bit rates
Interrupt flag at the end of transmission
Write collision flag to indicate data collision
Wake up from idle sleep mode
Double speed master mode
21.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several
microcontrollers. The SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.
PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
40
22. USART
22.1 Features
Two identical USART peripherals
Full-duplex operation
Asynchronous or synchronous operation
Synchronous clock rates up to 1/2 of the device clock frequency
Asynchronous clock rates up to 1/8 of the device clock frequency
Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
Fractional baud rate generator
Can generate desired baud rate from any system clock frequency
No need for external oscillator with certain frequencies
Built-in error detection and correction schemes
Odd or even parity generation and parity check
Data overrun and framing error detection
Noise filtering includes false start bit detection and digital low-pass filter
Separate interrupts for
Transmit complete
Transmit data register empty
Receive complete
Multiprocessor communication mode
Addressing scheme to address a specific devices on a multidevice bus
Enable unaddressed devices to automatically ignore all frames
Master SPI mode
Double buffered operation
Operation up to 1/2 of the peripheral clock frequency
IRCOM module for IrDA compliant pulse modulation/demodulation
22.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.
The USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.
The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2kbps.
PORTC and PORTD each has one USART. Notation of these peripherals are USARTC0 and USARTD0 respectively.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
41
23. IRCOM – IR Communication Module
23.1 Features
Pulse modulation/demodulation for infrared communication
IrDA compatible for baud rates up to 115.2kbps
Selectable pulse modulation scheme
3/16 of the baud rate period
Fixed pulse period, 8-bit programmable
Pulse modulation disabled
Built-in filtering
Can be connected to and used by any USART
23.2 Overview
Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates
up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
42
24. CRC – Cyclic Redundancy Check Generator
24.1 Features
Cyclic redundancy check (CRC) generation and checking for
Communication data
Program or data in flash memory
Data in SRAM and I/O memory space
Integrated with flash memory and CPU
Automatic CRC of the complete or a selectable range of the flash memory
CPU can load data to the CRC generator through the I/O interface
CRC polynomial software selectable to
CRC-16 (CRC-CCITT)
CRC-32 (IEEE 802.3)
Zero remainder detection
24.2 Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and
it is commonly used to determine the correctness of a data transmission, and data present in the data and program
memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or
simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits
(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error
bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-
CCITT) and CRC-32 (IEEE 802.3).
CRC-16:
Polynomial: x16+x12+x5+1
Hex value: 0x1021
CRC-32:
Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Hex value: 0x04C11DB7
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
43
25. ADC – 12-bit Analog to Digital Converter
25.1 Features
One Analog to Digital Converters (ADC)
12-bit resolution
Up to 200 thousand samples per second
Down to 3.6µs conversion time with 8-bit resolution
Down to 5.0µs conversion time with 12-bit resolution
Differential and single-ended input
Up to 12 single-ended inputs
12x4 differential inputs without gain
12x4 differential input with gain
Built-in differential gain stage
1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
Single, continuous and scan conversion options
Three internal inputs
Internal temperature sensor
AVCC voltage divided by 10
1.1V bandgap voltage
Internal and external reference options
Compare function for accurate monitoring of user defined thresholds
Optional event triggered conversion for accurate timing
Optional interrupt/event on compare result
25.2 Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 200
thousand samples per second (ksps). The input selection is flexible, and both single-ended and differential
measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic
range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.
The ADC measurements can either be started by application software or an incoming event from another peripheral in
the device. The ADC measurements can be started with predictable timing, and without software intervention.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the
ADC. The AVCC/10 and the bandgap voltage can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention
required.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
44
Figure 25-1. ADC overview
Compare
Register
ADC0
•
•
•
VINP
<
>
ADC11
Threshold
(Int Req)
Internal
signals
CH0 Result
ADC0
•
•
•
VINN
ADC7
Internal 1.00V
Internal AVCC/1.6V
Internal AVCC/2
AREFA
Reference
Voltage
AREFB
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 5.0µs
for 12-bit to 3.6µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
Notation of this peripheral is ADCA. The PORTA has ADCA inputs 0..7 and PORTB has ADCA inputs 8..11.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
45
26. AC – Analog Comparator
26.1 Features
Two Analog Comparators (ACs)
Selectable hysteresis
No
Small
Large
Analog comparator output available on pin
Flexible input selection
All pins on the port
Bandgap reference voltage
A 64-level programmable voltage scaler of the internal AVCC voltage
Interrupt and event generation on:
Rising edge
Falling edge
Toggle
Window function interrupt and event generation on:
Signal above window
Signal inside window
Signal below window
Constant current source with configurable output pin selection
26.2 Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several
different combinations of input change.
The important property of the analog comparator’s dynamic behavior is the hysteresis. It can be adjusted in order to
achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The
analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
PORTA has one AC pair. Notation is ACA.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
46
Figure 26-1. Analog Comparator Overview
Pin Input
+
-
AC0OUT
Pin Input
Hysteresis
Enable
Interrupt
Interrupts
Events
Interrupt
Mode
Sensititivity
Control
&
Voltage
ACnMUXCTRL
Scaler
ACnCTRL
WINCTRL
Window
Function
Enable
Bandgap
Hysteresis
+
-
Pin Input
AC1OUT
Pin Input
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in
Figure 26-2.
Figure 26-2. Analog Comparator Window Function
+
AC0
Upper limit of window
-
Interrupts
Interrupt
Input signal
sensitivity
Events
control
+
AC1
Lower limit of window
-
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
47
27. Programming and Debugging
27.1 Features
Programming
External programming through PDI interface
Minimal protocol overhead for fast operation
Built-in error detection and handling for reliable operation
Boot loader support for programming through any communication interface
Debugging
Nonintrusive, real-time, on-chip debug system
No software or hardware resources required from device except pin connection
Program flow control
Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
Unlimited number of user program breakpoints
Unlimited number of user data breakpoints, break on:
Data location read, write, or both read and write
Data location content equal or not equal to a value
Data location content is greater or smaller than a value
Data location content is within or outside a range
No limitation on device clock frequency
Program and Debug Interface (PDI)
Two-pin interface for external programming and debugging
Uses the Reset pin and a dedicated pin
No I/O pins required during programming or debugging
27.2 Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user
signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassembler
level.
Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset
pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external
programmer or on-chip debugger/emulator can be directly connected to this interface.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
48
28. Pinout and Pin Functions
The device pinout is shown in ”Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each
pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin.
Only one of the pin functions can be used at time.
28.1 Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
28.1.1 Operation/Power Supply
VCC
Digital supply voltage
Analog supply voltage
Ground
AVCC
GND
28.1.2 Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
ASYNC
Port pin with full synchronous and full asynchronous interrupt function
28.1.3 Analog Functions
ACn
Analog Comparator input pin n
Analog Comparator n Output
Analog to Digital Converter input pin n
Analog reference input pin
ACnOUT
ADCn
AREF
28.1.4 Timer/Counter and AWEX Functions
OCnxLS
OCnxHS
Output Compare Channel x Low Side for Timer/Counter n
Output Compare Channel x High Side for Timer/Counter n
28.1.5 Communication Functions
SCL
Serial Clock for TWI
SDA
XCKn
RXDn
TXDn
SS
Serial Data for TWI
Transfer Clock for USART n
Receiver Data for USART n
Transmitter Data for USART n
Slave Select for SPI
MOSI
MISO
SCK
Master Out Slave In for SPI
Master In Slave Out for SPI
Serial Clock for SPI
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
49
28.1.6 Oscillators, Clock and Event
TOSCn
XTALn
Timer Oscillator pin n
Input/Output for Oscillator pin n
Peripheral Clock Output
Event Channel Output
CLKOUT
EVOUT
RTCOUT
RTC Clock Source Output
28.1.7 Debug/System Functions
RESET
Reset pin
PDI_CLK
PDI_DATA
Program and Debug Interface Clock pin
Program and Debug Interface Data pin
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
50
28.2 Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the
second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that
enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the
first table where this apply.
Table 28-1. Port A - Alternate Functions
ADCA
NEG
ADCA
POS/GAINPOS
ADCA
GAINNEG
PORT A
GND
AVCC
PA0
PIN#
38
39
40
41
42
43
44
1
INTERRUPT
ACAPOS
ACANEG
ACAOUT
REFA
SYNC
SYNC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
ADC2
ADC3
AC0
AC1
AC2
AC3
AC4
AC5
AC6
AC0
AC1
AREF
PA1
SYNC/ASYNC
SYNC
PA2
PA3
AC3
AC5
AC7
PA4
SYNC
ADC4
ADC5
ADC6
ADC7
PA5
SYNC
PA6
2
SYNC
PA7
3
SYNC
AC0OUT
Table 28-2. Port B - Alternate Functions
PORT B
PB0
PIN#
INTERRUPT
SYNC
ADCAPOS/GAINPOS
ADC8
REFB
4
5
6
7
AREF
PB1
SYNC
ADC9
SYNC/ASYNC
SYNC
PB2
ADC10
PB3
ADC11
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
51
Table 28-3. Port C - Alternate Functions
(5)
PORT C
GND
VCC
PC0
PIN#
8
INTERRUPT
TCC0(1)(2)
AWEXC
TCC1
USARTC0(3)
SPIC(4)
TWIC
CLOCKOUT
EVENTOUT(6)
9
10
11
12
13
14
15
16
17
SYNC
SYNC
OC0A
OC0B
OC0C
OC0D
OC0ALS
OC0AHS
OC0BLS
OC0BHS
OC0CLS
OC0CHS
OC0DLS
OC0DHS
SDA
SCL
PC1
XCK0
RXD0
TXD0
PC2
SYNC/ASYNC
SYNC
PC3
PC4
SYNC
OC1A
OC1B
SS
PC5
SYNC
MOSI
MISO
SCK
PC6
SYNC
clkRTC
clkPER
PC7
SYNC
EVOUT
Notes:
1. Pin mapping of all TC0 can optionally be moved to high nibble of port
2. If TC0 is configured as TC2 all eight pins can be used for PWM output.
3. Pin mapping of all USART0 can optionally be moved to high nibble of port.
4. Pins MOSI and SCK for all SPI can optionally be swapped.
5. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7.
6. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7.
Table 28-4. Port D - Alternate Functions
PORT D
GND
VCC
PD0
PIN #
18
INTERRUPT
TCD0
USARTD0
SPID
CLOCKOUT
EVENTOUT
19
20
SYNC
SYNC
OC0A
OC0B
OC0C
OC0D
PD1
21
XCK0
RXD0
TXD0
PD2
22
SYNC/ASYNC
SYNC
PD3
23
PD4
24
SYNC
SS
PD5
25
SYNC
MOSI
MISO
SCK
PD6
26
SYNC
PD7
27
SYNC
clkPER
EVOUT
Table 28-5. Port E - Alternate Functions
PORT E
PE0
PIN #
28
INTERRUPT
SYNC
TCE0
TWIE
OC0A
OC0B
SDA
SCL
PE1
29
SYNC
GND
30
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
52
PORT E
VCC
PIN #
31
INTERRUPT
TCE0
TWIE
PE2
32
SYNC/ASYNC
SYNC
OC0C
OC0D
PE3
33
Table 28-6. Port F - Alternate Functions
PORT R
PDI
PIN #
34
INTERRUPT
PDI
XTAL
TOSC(1)
PDI_DATA
PDI_CLOCK
RESET
PRO
35
36
SYNC
SYNC
XTAL2
XTAL1
TOSC2
TOSC1
PR1
37
Note:
1. TOSC pins can optionally be moved to PE2/PE3
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
53
29. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in Atmel AVR XMEGA D4. For complete
register description and summary for each peripheral module, refer to the XMEGA D manual.
Table 29-1. Peripheral Module Address Map
Base address
0x0000
0x0010
0x0014
0x0018
0x001C
0x0030
0x0040
0x0048
0x0050
0x0060
0x0068
0x0070
0x0078
0x0080
0x0090
0x00A0
0x00B0
0x0180
0x00D0
0x01C0
0x0200
0x0380
0x0400
0x0480
0x04A0
0x0600
0x0620
0x0640
0x0660
Name
GPIO
Description
General purpose IO registers
Virtual Port 0
VPORT0
VPORT1
VPORT2
VPORT3
CPU
Virtual Port 1
Virtual Port 2
Virtual Port 2
CPU
CLK
Clock control
SLEEP
OSC
Sleep controller
Oscillator control
DFLLRC32M
DFLLRC2M
PR
DFLL for the 32 MHz internal RC oscillator
DFLL for the 2 MHz RC oscillator
Power reduction
RST
Reset controller
WDT
Watch-dog timer
MCU
MCU control
PMIC
Programmable multilevel interrupt controller
Port configuration
PORTCFG
EVSYS
CRC
Event system
CRC module
NVM
Nonvolatile memory (NVM) controller
Analog to digital converter on port A
Analog comparator pair on port A
Real time counter
ADCA
ACA
RTC
TWIC
Two wire interface on port C
Two wire interface on port E
Port A
TWIE
PORTA
PORTB
PORTC
PORTD
Port B
Port C
Port D
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
54
Base address
0x0680
0x07E0
0x0800
0x0840
0x0880
0x0890
0x08A0
0x08C0
0x08F8
0x0900
0x09A0
0x09C0
0x0A00
Name
PORTE
PORTR
TCC0
Description
Port E
Port R
Timer/counter 0 on port C
Timer/counter 1 on port C
Advanced waveform extension on port C
High resolution extension on port C
USART 0 on port C
TCC1
AWEXC
HIRESC
USARTC0
SPIC
Serial peripheral interface on port C
Infrared communication module
Timer/counter 0 on port D
USART 0 on port D
IRCOM
TCD0
USARTD0
SPID
Serial peripheral interface on port D
Timer/counter 0 on port E
TCE0
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
55
30. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Arithmetic and Logic Instructions
Flags
#Clocks
ADD
Rd, Rr
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add without Carry
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd + Rr
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,C,N,V,S
Z,C,N,V,S,H
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
Add with Carry
Rd + Rr + C
Rd + 1:Rd + K
Rd - Rr
ADIW
SUB
Add Immediate to Word
Subtract without Carry
Subtract Immediate
Subtract with Carry
Subtract Immediate with Carry
Subtract Immediate from Word
Logical AND
SUBI
SBC
Rd - K
Rd - Rr - C
Rd - K - C
Rd + 1:Rd - K
Rd Rr
SBCI
SBIW
AND
Rd + 1:Rd
Rd
ANDI
OR
Logical AND with Immediate
Logical OR
Rd
Rd K
Rd
Rd v Rr
ORI
Logical OR with Immediate
Exclusive OR
Rd
Rd v K
EOR
COM
NEG
SBR
Rd
Rd Rr
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd
$FF - Rd
Rd
Rd
$00 - Rd
Rd,K
Rd,K
Rd
Rd
Rd v K
CBR
Rd
Rd ($FFh - K)
Rd + 1
INC
Rd
DEC
Rd
Decrement
Rd
Rd - 1
TST
Rd
Test for Zero or Minus
Clear Register
Rd
Rd Rd
CLR
Rd
Rd
Rd Rd
SER
Rd
Set Register
Rd
$FF
MUL
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Multiply Unsigned
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
Rd x Rr (UU)
Rd x Rr (SS)
Rd x Rr (SU)
Rd x Rr<<1 (UU)
Rd x Rr<<1 (SS)
Rd x Rr<<1 (SU)
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
Branch instructions
RJMP
IJMP
k
Relative Jump
PC
PC + k + 1
None
None
2
2
Indirect Jump to (Z)
PC(15:0)
PC(21:16)
Z,
0
EIJMP
Extended Indirect Jump to (Z)
PC(15:0)
PC(21:16)
Z,
EIND
None
2
JMP
k
k
Jump
PC
PC
k
None
None
3
RCALL
Relative Call Subroutine
PC + k + 1
2 / 3(1)
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
56
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ICALL
Indirect Call to (Z)
PC(15:0)
PC(21:16)
Z,
0
None
2 / 3(1)
EICALL
Extended Indirect Call to (Z)
PC(15:0)
PC(21:16)
Z,
EIND
None
3(1)
CALL
RET
k
call Subroutine
PC
PC
k
None
None
I
3 / 4(1)
4 / 5(1)
4 / 5(1)
1 / 2 / 3
1
Subroutine Return
STACK
STACK
PC + 2 or 3
RETI
Interrupt Return
PC
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC
None
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Rd,Rr
Rd - Rr
CPC
Rd,Rr
Compare with Carry
Rd - Rr - C
1
CPI
Rd,K
Compare with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd - K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b) = 0) PC
if (Rr(b) = 1) PC
if (I/O(A,b) = 0) PC
If (I/O(A,b) =1) PC
if (SREG(s) = 1) then PC
if (SREG(s) = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (N V= 0) then PC
if (N V= 1) then PC
if (H = 1) then PC
if (H = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
1 / 2 / 3
1 / 2 / 3
2 / 3 / 4
2 / 3 / 4
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
Rr, b
A, b
A, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
Data transfer instructions
MOV
MOVW
LDI
Rd, Rr
Rd, Rr
Rd, K
Copy Register
Rd
Rd+1:Rd
Rd
Rr
None
None
None
1
1
1
Copy Register Pair
Load Immediate
Rr+1:Rr
K
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
57
Mnemonics
Operands
Rd, k
Description
Operation
Flags
None
None
None
#Clocks
2(1)(2)
LDS
LD
Load Direct from data space
Load Indirect
Rd
Rd
(k)
Rd, X
(X)
1(1)(2)
LD
Rd, X+
Load Indirect and Post-Increment
Rd
X
(X)
X + 1
1(1)(2)
LD
Rd, -X
Load Indirect and Pre-Decrement
X X - 1,
Rd (X)
X - 1
(X)
None
2(1)(2)
LD
LD
Rd, Y
Load Indirect
Rd (Y)
(Y)
None
None
1(1)(2)
1(1)(2)
Rd, Y+
Load Indirect and Post-Increment
Rd
Y
(Y)
Y + 1
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd
Y - 1
(Y)
None
2(1)(2)
LDD
LD
Rd, Y+q
Rd, Z
Load Indirect with Displacement
Load Indirect
Rd
Rd
(Y + q)
(Z)
None
None
None
2(1)(2)
1(1)(2)
1(1)(2)
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z
(Z),
Z+1
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd
Z - 1,
(Z)
None
2(1)(2)
LDD
STS
ST
Rd, Z+q
k, Rr
Load Indirect with Displacement
Store Direct to Data Space
Store Indirect
Rd
(k)
(X)
(Z + q)
Rd
None
None
None
None
2(1)(2)
2(1)
X, Rr
Rr
1(1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X
Rr,
X + 1
1(1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)
X - 1,
Rr
None
2(1)
ST
ST
Y, Rr
Store Indirect
(Y)
Rr
None
None
1(1)
1(1)
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y
Rr,
Y + 1
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)
Y - 1,
Rr
None
2(1)
STD
ST
Y+q, Rr
Z, Rr
Store Indirect with Displacement
Store Indirect
(Y + q)
(Z)
Rr
Rr
None
None
None
2(1)
1(1)
1(1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z
Rr
Z + 1
ST
-Z, Rr
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Load Program Memory
Z
(Z + q)
R0
Z - 1
Rr
None
None
None
None
None
2(1)
2(1)
3
STD
LPM
LPM
LPM
Z+q,Rr
(Z)
Rd, Z
Load Program Memory
Rd
(Z)
3
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z
(Z),
Z + 1
3
ELPM
ELPM
ELPM
Extended Load Program Memory
Extended Load Program Memory
R0
Rd
(RAMPZ:Z)
(RAMPZ:Z)
None
None
None
3
3
3
Rd, Z
Rd, Z+
Extended Load Program Memory and Post-
Increment
Rd
Z
(RAMPZ:Z),
Z + 1
SPM
Store Program Memory
(RAMPZ:Z)
R1:R0
None
-
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
58
Mnemonics
Operands
Description
Operation
Flags
#Clocks
SPM
Z+
Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
R1:R0,
Z + 2
None
-
Z
IN
Rd, A
A, Rr
Rr
In From I/O Location
Out To I/O Location
Rd
I/O(A)
Rr
None
None
None
None
None
1
1
OUT
PUSH
POP
XCH
I/O(A)
STACK
Rd
Push Register on Stack
Pop Register from Stack
Exchange RAM location
Rr
1(1)
2(1)
2
Rd
STACK
Z, Rd
Temp
Rd
(Z)
Rd,
(Z),
Temp
LAS
LAC
LAT
Z, Rd
Z, Rd
Z, Rd
Load and Set RAM location
Load and Clear RAM location
Load and Toggle RAM location
Temp
Rd
(Z)
Rd,
(Z),
Temp v (Z)
None
None
None
2
2
2
Temp
Rd
(Z)
Rd,
(Z),
($FFh – Rd) (Z)
Temp
Rd
(Z)
Rd,
(Z),
Temp (Z)
Bit and bit-test instructions
LSL
Rd
Rd
Rd
Rd
Logical Shift Left
Rd(n+1)
Rd(0)
C
Rd(n),
0,
Rd(7)
Z,C,N,V,H
Z,C,N,V
1
1
1
1
LSR
ROL
ROR
Logical Shift Right
Rd(n)
Rd(7)
C
Rd(n+1),
0,
Rd(0)
Rotate Left Through Carry
Rotate Right Through Carry
Rd(0)
Rd(n+1)
C
C,
Rd(n),
Rd(7)
Z,C,N,V,H
Z,C,N,V
Rd(7)
Rd(n)
C
C,
Rd(n+1),
Rd(0)
ASR
SWAP
BSET
BCLR
SBI
Rd
Arithmetic Shift Right
Swap Nibbles
Rd(n)
Rd(n+1), n=0..6
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd
Rd(3..0)
Rd(7..4)
None
s
Flag Set
SREG(s)
1
SREG(s)
s
Flag Clear
SREG(s)
0
SREG(s)
A, b
A, b
Rr, b
Rd, b
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
I/O(A, b)
1
None
CBI
I/O(A, b)
0
None
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
T
Rr(b)
T
T
Rd(b)
None
C
C
N
N
Z
Z
I
1
C
C
N
N
Z
Z
I
Clear Carry
0
Set Negative Flag
Clear Negative Flag
Set Zero Flag
1
0
1
Clear Zero Flag
0
Global Interrupt Enable
Global Interrupt Disable
1
CLI
I
0
I
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
59
Mnemonics
SES
Operands
Description
Operation
Flags
#Clocks
Set Signed Test Flag
S
S
V
V
T
1
0
1
0
1
0
1
0
S
S
V
V
T
T
H
H
1
1
1
1
1
1
1
1
CLS
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
SEV
CLV
SET
CLT
Clear T in SREG
T
SEH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H
H
CLH
MCU control instructions
BREAK
NOP
Break
(See specific descr. for BREAK)
None
None
None
None
1
1
1
1
No Operation
Sleep
SLEEP
WDR
(see specific descr. for Sleep)
(see specific descr. for WDR)
Watchdog Reset
Notes:
1. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing internal SRAM.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
60
31. Packaging information
31.1 44A
PIN 1 IDENTIFIER
PIN 1
B
e
E1
E
D1
D
C
0°~7°
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
–
0.15
1.00
1.05
12.00
10.00
12.00
10.00
0.37
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
(0.17)
0.60
0.20
3. Lead coplanarity is 0.10mm maximum.
L
0.75
e
0.80 TYP
06/02/2014
44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness,
0.8 mm lead pitch, thin profile plastic quad flat package (TQFP)
44A
C
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
61
31.2 44M1
D
Marked Pin# 1 I D
E
SE ATING PLAN
E
A1
A3
TOP VIE
W
A
K
L
Pin #1 Co rner
SIDE VIEW
D2
Pin #1
Triangle
Option A
COMMON DIMENSIONS
(Unit of Measure = mm)
1
2
3
MIN
0.80
–
MAX
1.00
0.05
NOM
0.90
NOTE
SYMBOL
A
E2
Option B
Option C
A1
A3
b
0.02
Pin #1
Cham fer
(C 0.30)
0.20 REF
0.23
0.18
6.90
5.00
6.90
0.30
7.10
5.40
7.10
D
7.00
D2
E
5.20
K
Pin #1
Notch
(0.20 R)
e
b
7.00
E2
e
5.00
5.20
0.50 BSC
0.64
5.40
B OTTOM VIE W
L
0.59
0.20
0.69
0.41
Note: JEDEC Standard MO-220, Fig
. 1 (S AW Singulation) VKKD-3 .
K
0.26
02/13/2014
GPC
ZWS
DRAWING NO.
TITLE
REV.
44M1, 44-pad, 7 x 7 x 1.0mm body, lead
pitch 0.50mm, 5.20mm exposed pad, thermally
enhanced plastic very thin quad flat no
lead package (VQFN)
Package Drawing Contact:
packagedrawings@atmel.com
44M1
H
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
62
31.3 49C2
E
A1 BALL ID
0.10
D
A1
A2
TOP VIEW
A
SIDE VIEW
E1
G
F
e
E
D
C
B
A
D1
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.00
–
NOM
–
NOTE
SYMBOL
A
1
2
3
4
5
6
7
A1
A2
D
0.20
0.65
4.90
–
A1 BALL CORNER
49 - Ø0.35 0.05
b
e
–
–
5.00
5.10
BOTTOM VIEW
D1
E4.90
E1
b
3.90 BSC
5.10
5.00
0.30
3.90 BSC
0.35
0.40
e
0.65 BSC
3/14/08
GPC
CBD
DRAWING NO.
TITLE
REV.
49C2, 49-ball (7 x 7 array), 0.65mm pitch,
5.0 x 5.0 x 1.0mm, very thin, fine-pitch
ball grid array package (VFBGA)
Package Drawing Contact:
packagedrawings@atmel.com
49C2
A
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
63
32. Electrical Characteristics
All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum
values are valid across operating temperature and voltage unless other conditions are given.
32.1 ATxmega16D4
32.1.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 32-1 under may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 32-1. Absolute Maximum Ratings
Symbol
VCC
IVCC
IGND
VPIN
IPIN
Parameter
Condition
Min.
Typ.
Max.
4
Units
Power supply voltage
Current into a VCC pin
Current out of a Gnd pin
Pin voltage with respect to Gnd and VCC
I/O pin sink/source current
Storage temperature
-0.3
V
200
mA
200
-0.5
-25
-65
VCC+0.5
25
V
mA
TA
150
°C
Tj
Junction temperature
150
32.1.2 General Operating Ratings
The device must operate within the ratings listed in Table 32-2 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 32-2. General Operating Conditions
Symbol
VCC
Parameter
Condition
Min.
1.60
1.60
-40
Typ.
Max.
3.6
Units
Power supply voltage
Analog supply voltage
Temperature range
Junction temperature
V
AVCC
TA
3.6
85
°C
Tj
-40
105
Table 32-3. Operating Voltage and Frequency
Symbol
Parameter
Condition
VCC = 1.6V
VCC = 1.8V
VCC = 2.7V
VCC = 3.6V
Min.
Typ.
Max.
12
Units
0
0
0
0
12
ClkCPU
CPU clock frequency
MHz
32
32
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
64
The maximum CPU clock frequency depends on VCC. As shown in Figure 32-15 the Frequency vs. VCC curve is linear
between 1.8V < VCC < 2.7V.
Figure 32-1. Maximum Frequency vs. VCC
MHz
32
Safe Operating Area
12
V
1.6
1.8
2.7
3.6
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
65
32.1.3 Current Consumption
Table 32-4. Current Consumption for Active Mode and Sleep Modes
Symbol Parameter
Condition
Min.
Typ.
40
Max.
Units
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
32kHz, Ext. Clk
80
200
410
350
0.75
7.5
2.0
2.8
42
µA
1MHz, Ext. Clk
Active power
consumption(1)
600
1.4
12
2MHz, Ext. Clk
32MHz, Ext. Clk
32kHz, Ext. Clk
VCC = 3.0V
mA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
1MHz, Ext. Clk
2MHz, Ext. Clk
µA
Idle power
85
consumption(1)
85
225
350
5.5
1.0
4.5
7.0
170
2.7
0.1
2.0
0.1
VCC = 3.0V
32MHz, Ext. Clk
T = 25°C
mA
ICC
T = 85°C
VCC = 3.0V
T = 105°C
WDT and sampled BOD enabled,
T = 25°C
Power-down power
consumption
1.4
3.0
1.4
3.0
6.0
10
WDT and sampled BOD enabled,
T = 85°C
VCC = 3.0V
WDT and sampled BOD enabled,
T = 105°C
µA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
1.5
1.5
0.6
0.7
0.8
1.0
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
2.0
2.0
3.0
3.0
Power-save power
consumption(2)
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
RTC from low power 32.768kHz
TOSC, T = 25°C
Current through RESET pin
substracted
Reset power consumption
VCC = 3.0V
300
Notes:
1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
66
Table 32-5. Current Consumption for Modules and Peripherals
Symbol Parameter
Condition(1)
Min.
Typ.
0.8
29
Max.
Units
ULP oscillator
32.768kHz int. oscillator
85
2MHz int. oscillator
32MHz int. oscillator
DFLL enabled with 32.768kHz int. osc. as reference
DFLL enabled with 32.768kHz int. osc. as reference
115
245
410
µA
20x multiplication factor,
32MHz int. osc. DIV4 as reference
PLL
290
Watchdog timer
1.0
138
1.2
175
170
1.2
1.0
0.9
0.8
Continuous mode
BOD
Sampled mode, includes ULP oscillator
ICC
Internal 1.0V reference
Temperature sensor
CURRLIMIT = LOW
16ksps
VREF = Ext ref
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
ADC
mA
75ksps
CURRLIMIT = LOW
VREF = Ext ref
1.7
3.1
200ksps
VREF = Ext ref
USART
Rx and Tx enabled, 9600 BAUD
11
4
µA
Flash memory and EEPROM programming
mA
Note:
1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
67
32.1.4 Wake-up Time from Sleep Modes
Table 32-6. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Symbol Parameter
Condition
External 2MHz clock
Min.
Typ.(1)
2.0
Max.
Units
Wake-up time from idle,
standby, and extended standby
mode
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
120
2.0
0.2
twakeup
µs
5.0
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
320
9.0
Wake-up time from power-save
and power-down mode
5.0
Note:
1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-2. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 32-2. Wake-up Time Definition
Wakeup time
Wakeup request
Clock output
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
68
32.1.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 32-7. I/O Pin Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
(1)
IOH
IOL
/
I/O pin source/sink current
High level input voltage
-20
20
mA
(2)
VCC = 2.4 - 3.6V
0.7*Vcc
0.8*VCC
-0.5
VCC+0.5
VCC+0.5
0.3*VCC
0.2*VCC
VIH
VCC = 1.6 - 2.4V
VCC = 2.4- 3.6V
VCC = 1.6 - 2.4V
VCC = 3.3V
VIL
Low level input voltage
High level output voltage
-0.5
IOH = -4mA
IOH = -3mA
IOH = -1mA
IOL = 8mA
IOL = 5mA
IOL = 3mA
2.6
2.9
2.7
V
VOH
VCC = 3.0V
2.1
VCC = 1.8V
1.4
1.6
VCC = 3.3V
0.4
0.76
0.64
0.46
1
VOL
Low level output voltage
VCC = 3.0V
0.3
VCC = 1.8V
0.2
IIN
Input leakage current I/O pin
Pull/buss keeper resistor
T = 25°C
<0.01
25
µA
RP
k
Notes:
1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
69
32.1.6 ADC Characteristics
Table 32-8. Power Supply, Reference and Input Range
Symbol
AVCC
VREF
Rin
Parameter
Condition
Min.
VCC- 0.3
1
Typ.
Max.
VCC+ 0.3
AVCC- 0.6
4.5
Units
Analog supply voltage
Reference voltage
Input resistance
V
Switched
k
pF
Cin
Input capacitance
Reference input resistance
Switched
5
RAREF
CAREF
(leakage only)
>10
7
M
pF
Reference input capacitance Static load
Input range
0
VREF
VREF
Vin
Conversion range
Conversion range
Fixed offset voltage
Differential mode, Vinp - Vinn
-VREF
-V
V
Single ended unsigned mode, Vinp
VREF-V
∆V
200
LSB
Table 32-9. Clock and Timing
Symbol
ClkADC
fClkADC
Parameter
Condition
Min.
Typ.
Max.
Units
Maximum is 1/4 of peripheral clock
frequency
100
1800
ADC clock frequency
Sample rate
kHz
Measuring internal signals
125
300
300
250
150
50
Current limitation (CURRLIMIT) off
CURRLIMIT = LOW
16
ksps
µs
fADC
Sample rate
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
Configurable in steps of 1/2 ClkADC cycles
up to 32 ClkADC cycles
Sampling time
0.28
4.5
320
10
(RES+1)/2 + GAIN
RES (Resolution) = 8 or 12, GAIN=0 to 3
Conversion time (latency)
ClkADC
cycles
Start-up time
ADC clock cycles
12
7
24
7
ADC settling time
After changing reference or input mode
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
70
Table 32-10. Accuracy Characteristics
Symbol
Parameter
Condition(2)
Differential
Min.
Typ.
12
Max.
12
11
12
1
Units
8
7
8
RES
Resolution
12-bit resolution
Single ended signed
Single ended unsigned
16ksps, VREF = 3V
16ksps, all VREF
11
Bits
12
0.5
0.8
0.6
1
2
Differential mode
200ksps, VREF = 3V
200ksps, all VREF
16ksps, VREF = 3.0V
16ksps, all VREF
1
INL(1)
Integral non-linearity
2
0.5
1.3
0.3
0.5
0.35
0.5
0.6
0.6
8
1
Single ended
unsigned mode
2
lsb
16ksps, VREF = 3V
16ksps, all VREF
1
1
Differential mode
200ksps, VREF = 3V
200ksps, all VREF
16ksps, VREF = 3.0V
16ksps, all VREF
1
DNL(1)
Differential non-linearity
1
1
Single ended
unsigned mode
1
mV
Offset Error
Differential mode
Temperature drift
Operating voltage drift
External reference
AVCC/1.6
0.01
0.25
-5
mV/K
mV/V
-5
mV
AVCC/2.0
-6
Differential mode
Bandgap
±10
0.02
2
Temperature drift
Operating voltage drift
External reference
AVCC/1.6
mV/K
mV/V
Gain Error
-8
-8
mV
AVCC/2.0
-8
Single ended
unsigned mode
Bandgap
±10
0.03
2
Temperature drift
Operating voltage drift
mV/K
mV/V
Notes:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
71
Table 32-11. Gain Stage Characteristics
Rin
Input resistance
Input capacitance
Signal range
Switched in normal mode
Switched in normal mode
Gain stage output
4.0
4.4
k
pF
V
Csample
0
AVCC- 0.6
3
ClkADC
cycles
Propagation delay
Clock frequency
ADC conversion rate
1/2
100
1
Same as ADC
1800
kHz
0.5x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
0.5x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
-1
-1
Gain Error
%
-1
10
10
5
Offset Error,
output referred
mV
-20
-150
32.1.7 Analog Comparator Characteristics
Table 32-12. Analog Comparator Characteristics
Symbol
Voff
Parameter
Condition
VCC=1.6V - 3.6V
Min.
Typ.
<±10
<1
Max.
Units
mV
nA
Input offset voltage
Input leakage current
Input voltage range
AC startup time
Hysteresis, none
Hysteresis, small
Hysteresis, large
Ilk
VCC=1.6V - 3.6V
-0.1
AVCC
V
100
0
µs
Vhys1
Vhys2
Vhys3
VCC=1.6V - 3.6V
VCC=1.6V - 3.6V
11
26
16
16
0.3
mV
VCC=1.6V - 3.6V
VCC = 3.0V, T= 85°C
VCC=1.6V - 3.6V
90
tdelay
Propagation delay
ns
64-level voltage scaler
Integral non-linearity (INL)
0.5
lsb
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
72
32.1.8 Bandgap and Internal 1.0V Reference Characteristics
Table 32-13. Bandgap and Internal 1.0V Reference Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
As reference for ADC
1 ClkPER + 2.5µs
Startup time
µs
As input voltage to ADC and AC
1.5
1.1
1
Bandgap voltage
V
INT1V
Internal 1.00V reference
T= 85°C, after calibration
0.98
1.02
Variation over voltage and temperature
Calibrated at T= 85°C, VCC = 3.0V
±1.0
%
32.1.9 Brownout Detection Characteristics
Table 32-14. Brownout Detection Characteristics(1)
Symbol Parameter
BOD level 0 falling VCC
BOD level 1 falling VCC
BOD level 2 falling VCC
Condition
Min.
Typ.
1.62
1.8
Max.
Units
1.50
1.75
2.0
BOD level 3 falling VCC
VBOT
2.2
V
BOD level 4 falling VCC
2.4
BOD level 5 falling VCC
BOD level 6 falling VCC
BOD level 7 falling VCC
2.6
2.8
3.0
Continuous mode
Sampled mode
0.4
tBOD
Detection time
Hysteresis
µs
%
1000
1.2
VHYST
Note:
1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
32.1.10 External Reset Characteristics
Table 32-15. External Reset Characteristics
Symbol Parameter
Condition
Min.
1000
Typ.
Max.
Units
tEXT
Minimum reset pulse width
90
ns
VCC = 2.7 - 3.6V
0.6*VCC
0.6*VCC
Reset threshold voltage (VIH)
VCC = 1.6 - 2.7V
VCC = 2.7 - 3.6V
VCC = 1.6 - 2.7V
VRST
V
0.5*VCC
0.4*VCC
Reset threshold voltage (VIL)
Reset pin pull-up resistor
RRST
25
k
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
73
32.1.11 Power-on Reset Characteristics
Table 32-16. Power-on Reset Characteristics
Symbol Parameter
Condition
VCC falls faster than 1V/ms
VCC falls at 1V/ms or slower
Min.
0.4
Typ.
1.0
Max.
Units
(1)
VPOT-
POR threshold voltage falling VCC
POR threshold voltage rising VCC
0.8
1.0
V
VPOT+
1.3
1.59
Note:
1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+
.
32.1.12 Flash and EEPROM Memory Characteristics
Table 32-17. Endurance and Data Retention
Symbol Parameter
Condition
Min.
10K
10K
2K
Typ.
Max.
Units
25°C
85°C
105°C
25°C
85°C
105°C
25°C
85°C
105°C
25°C
85°C
105°C
Write/Erase cycles
Cycle
Flash
100
25
Data retention
Year
Cycle
Year
10
100K
100K
30K
100
25
Write/Erase cycles
Data retention
EEPROM
10
Table 32-18. Programming Time
Symbol Parameter
Condition
Min.
Typ.(1)
Max.
Units
Chip erase(2)
16KB Flash, EEPROM
Page erase
45
4
Flash
Page write
4
Atomic page erase and write
Page erase
8
ms
4
EEPROM
Page write
4
Atomic page erase and write
8
Notes:
1. Programming is timed from the 2MHz internal oscillator.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
74
2. EEPROM is not erased if the EESAVE fuse is programmed.
32.1.13 Clock and Oscillator Characteristics
32.1.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 32-19. 32.768kHz Internal Oscillator Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Frequency
32.768
kHz
Factory calibration accuracy
User calibration accuracy
T = 85C, VCC = 3.0V
-0.5
-0.5
0.5
0.5
%
32.1.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 32-20. 2MHz Internal Oscillator Characteristics
Symbol Parameter
Frequency range
Condition
Min.
Typ.
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
1.8
2.2
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration stepsize
2.0
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.18
32.1.13.3 Calibrated and Tunable 32MHz Internal Oscillator Characteristics
Table 32-21. 32MHz Internal Oscillator Characteristics
Symbol Parameter
Frequency range
Condition
Min.
Typ.
32
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
30
55
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration step size
32
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.19
32.1.13.4 32kHz Internal ULP Oscillator Characteristics
Table 32-22. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Factory calibrated frequency
32
kHz
Factory calibration accuracy
Accuracy
T = 85C, VCC= 3.0V
-12
-30
12
30
%
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
75
32.1.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 32-23. Internal PLL Characteristics.
Symbol Parameter
Condition
Min.
0.4
20
Typ.
Max.
64
Units
fIN
Input frequency
Output frequency must be within fOUT
VCC= 1.6 - 1.8V
48
MHz
fOUT
Output frequency (1)
VCC= 2.7 - 3.6V
20
128
Start-up time
Re-lock time
25
25
µs
Note:
1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
32.1.13.6 External Clock Characteristics
Figure 32-3. External Clock Drive Waveform
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 32-24. External Clock(1)
Symbol Parameter
Condition
VCC = 1.6 - 1.8V
Min.
Typ.
Max.
90
Units
0
1/tCK
Clock frequency(2)
Clock period
MHz
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
0
142
11
7.0
4.5
2.4
tCK
ns
tCH/CL
Clock high/low time
VIL/IH
Low/high level input voltage
See Table 32-7 on page 69
10
V
Reduction in period time from one
clock cycle to the next
tCK
%
Notes:
1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
76
32.1.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 32-25. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter
.
Condition
Min.
Typ.
0
Max.
Units
FRQRANGE=0
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
Cycle to cycle jitter
FRQRANGE=1, 2, or 3
0
0
ns
FRQRANGE=0
0
Long term jitter
Frequency error
FRQRANGE=1, 2, or 3
0
0
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
0.03
0.03
0.03
0.003
50
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
%
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
50
Duty cycle
50
50
0.4MHz resonator,
CL=100pF
44k
XOSCPWR=0,
FRQRANGE=0
1MHz crystal, CL=20pF
2MHz crystal, CL=20pF
2MHz crystal
67k
67k
82k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
8MHz crystal
1500
1500
2700
2700
1000
3600
1300
590
9MHz crystal
8MHz crystal
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
RQ
Negative impedance
9MHz crystal
12MHz crystal
9MHz crystal
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
390
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
12MHz crystal
16MHz crystal
50
10
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
77
Symbol Parameter
Condition
Min.
Typ.
1500
650
Max.
Units
9MHz crystal
12MHz crystal
16MHz crystal
12MHz crystal
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
270
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
1000
RQ
Negative impedance
16MHz crystal
12MHz crystal
16MHz crystal
440
1300
590
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
ESR
SF = safety factor
min(RQ)/SF
k
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF
1.0
2.6
0.8
1.0
1.4
5.9
XOSCPWR=0,
FRQRANGE=1
2MHz crystal, CL=20pF
8MHz crystal, CL=20pF
12MHz crystal, CL=20pF
16MHz crystal, CL=20pF
XOSCPWR=0,
FRQRANGE=2
Start-up time
ms
XOSCPWR=0,
FRQRANGE=3
XOSCPWR=1,
FRQRANGE=3
Parasitic capacitance
XTAL1 pin
CXTAL1
Parasitic capacitance
XTAL2 pin
pF
CXTAL2
CLOAD
8.3
3.5
Parasitic capacitance load
32.1.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 32-26. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Symbol
Parameter
Condition
Min.
Typ.
Max.
60
Units
Crystal load capacitance 6.5pF
Crystal load capacitance 9.0pF
Crystal load capacitance 12pF
k
Recommended crystal equivalent
series resistance (ESR)
ESR/R1
35
28
CTOSC1
CTOSC2
Parasitic capacitance TOSC1 pin
Parasitic capacitance TOSC2 pin
3.5
3.5
pF
capacitance load matched to
crystal specification
Recommended safety factor
3
Note:
See Figure 32-4 for definition.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
78
Figure 32-4. TOSC Input Capacitance
CL1
CL2
Device internal
External
TOSC1
TOSC2
32.768KHz crystal
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
32.1.14 SPI Characteristics
Figure 32-5. SPI Timing Requirements in Master Mode
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
tMIH
MSB
tSCK
MISO
(Data Input)
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
79
Figure 32-6. SPI Timing Requirements in Slave Mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
tSIH
MSB
tSSCK
LSB
MOSI
(Data Input)
tSOSSS
tSOS
tSOSSH
MISO
(Data Output)
MSB
LSB
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
80
Table 32-27. SPI Timing Characteristics and Requirements
Symbol Parameter Condition
Min.
Typ.
Max.
Units
(See Table 20-3 in
XMEGA C Manual)
tSCK
SCK period
Master
tSCKW
tSCKR
tSCKF
tMIS
SCK high/low width
SCK rise time
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
0.5*SCK
2.7
2.7
SCK fall time
MISO setup to SCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Slave SCK Period
SCK high/low width
SCK rise time
10
tMIH
10
tMOS
tMOH
tSSCK
tSSCKW
tSSCKR
tSSCKF
tSIS
0.5*SCK
1
4*t ClkPER
2*t ClkPER
ns
1600
1600
SCK fall time
MOSI setup to SCK
MOSI hold after SCK
SS setup to SCK
SS hold after SCK
MISO setup SCK
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
3
t ClkPER
21
tSIH
tSSS
tSSH
20
tSOS
8
13
11
8
tSOH
tSOSS
tSOSH
32.1.15 Two-Wire Interface Characteristics
Table 32-28 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA
Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-
21.
Figure 32-7. Two-wire Interface Bus Timing
tof
tHIGH
tLOW
tr
SCL
SDA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
tHD;STA
tBUF
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
81
Table 32-28. Two-wire Interface Characteristics
Symbol Parameter
Condition
Min.
0.7VCC
-0.5
Typ.
Max.
VCC+0.5
0.3VCC
Units
VIH
VIL
Input high voltage
Input low voltage
V
(1)
Vhys
Hysteresis of Schmitt trigger inputs
Output low voltage
0.05VCC
0
VOL
3mA, sink current
0.4
300
250
50
(1)(2)
(1)(2)
tr
tof
Rise time for both SDA and SCL
Output fall time from VIHmin to VILmax
Spikes suppressed by input filter
Input current for each I/O Pin
Capacitance for each I/O Pin
SCL clock frequency
20+0.1Cb
20+0.1Cb
0
10pF < Cb < 400pF (2)
0.1VCC < VI < 0.9VCC
ns
tSP
II
-10
10
µA
pF
CI
10
fSCL
fPER (3)>max(10fSCL, 250kHz)
fSCL 100kHz
0
400
kHz
100ns
--------------
Cb
VCC – 0.4V
---------------------------
3mA
RP
Value of pull-up resistor
300ns
fSCL > 100kHz
--------------
Cb
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
0
tHD;STA
Hold time (repeated) START condition
Low period of SCL clock
tLOW
µs
tHIGH
High period of SCL clock
Set-up time for a repeated START
condition
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
3.45
0.9
Data hold time
µs
ns
µs
µs
0
250
100
4.0
0.6
4.7
1.3
Data setup time
Setup time for STOP condition
Bus free time between a STOP and
START condition
Notes:
1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3.
fPER = Peripheral clock frequency.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
82
32.2 ATxmega32D4
32.2.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 32-29 under may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 32-29. Absolute Maximum Ratings
Symbol
VCC
Parameter
Condition
Min.
Typ.
Max.
4
Units
Power supply voltage
Current into a VCC pin
Current out of a Gnd pin
-0.3
V
IVCC
200
200
mA
IGND
Pin voltage with respect to Gnd
and VCC
VPIN
-0.5
VCC+0.5
V
IPIN
TA
Tj
I/O pin sink/source current
Storage temperature
-25
-65
25
mA
150
150
°C
Junction temperature
32.2.2 General Operating Ratings
The device must operate within the ratings listed in Table 32-30 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 32-30. General Operating Conditions
Symbol
VCC
Parameter
Condition
Min.
1.60
1.60
-40
Typ.
Max.
3.6
Units
Power supply voltage
Analog supply voltage
Temperature range
Junction temperature
V
AVCC
TA
3.6
85
°C
Tj
-40
105
Table 32-31. Operating Voltage and Frequency
Symbol
Parameter
Condition
VCC = 1.6V
VCC = 1.8V
VCC = 2.7V
VCC = 3.6V
Min.
Typ.
Max.
12
Units
0
0
0
0
12
ClkCPU
CPU clock frequency
MHz
32
32
The maximum CPU clock frequency depends on VCC. As shown in Figure 32-8 the Frequency vs. VCC curve is linear
between 1.8V < VCC < 2.7V.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
83
Figure 32-8. Maximum Frequency vs. VCC
MHz
32
Safe Operating Area
12
V
1.6
1.8
2.7
3.6
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
84
32.2.3 Current Consumption
Table 32-32. Current Consumption for Active Mode and Sleep Modes
Symbol Parameter
Condition
Min.
Typ.
40
Max.
Units
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
32kHz, Ext. Clk
80
200
410
350
0.75
7.5
2.0
2.8
42
µA
1MHz, Ext. Clk
Active power
consumption(1)
600
1.4
12
2MHz, Ext. Clk
32MHz, Ext. Clk
32kHz, Ext. Clk
VCC = 3.0V
mA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
1MHz, Ext. Clk
2MHz, Ext. Clk
µA
Idle power
85
consumption(1)
85
225
350
5.5
1.0
4.5
7.0
170
2.7
0.1
2.0
0.1
VCC = 3.0V
32MHz, Ext. Clk
T = 25°C
mA
ICC
T = 85°C
VCC = 3.0V
T = 105°C
WDT and sampled BOD enabled,
T = 25°C
Power-down power
consumption
1.4
3.0
1.4
3.0
6.0
10
WDT and sampled BOD enabled,
T = 85°C
VCC = 3.0V
WDT and sampled BOD enabled,
T = 105°C
µA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
1.5
1.5
0.6
0.7
0.8
1.0
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
2.0
2.0
3.0
3.0
Power-save power
consumption(2)
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
RTC from low power 32.768kHz
TOSC, T = 25°C
Current through RESET pin
substracted
Reset power consumption
VCC = 3.0V
300
Notes:
1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
85
Table 32-33. Current Consumption for Modules and Peripherals
Symbol Parameter
Condition(1)
Min.
Typ.
0.8
29
Max.
Units
ULP oscillator
32.768kHz int. oscillator
85
2MHz int. oscillator
32MHz int. oscillator
DFLL enabled with 32.768kHz int. osc. as reference
DFLL enabled with 32.768kHz int. osc. as reference
115
245
410
µA
20x multiplication factor,
32MHz int. osc. DIV4 as reference
PLL
290
Watchdog timer
1.0
138
1.2
175
170
1.2
1.0
0.9
0.8
Continuous mode
BOD
Sampled mode, includes ULP oscillator
ICC
Internal 1.0V reference
Temperature sensor
CURRLIMIT = LOW
16ksps
VREF = Ext ref
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
ADC
mA
75ksps
CURRLIMIT = LOW
VREF = Ext ref
1.7
3.1
200ksps
VREF = Ext ref
USART
Rx and Tx enabled, 9600 BAUD
11
4
µA
Flash memory and EEPROM programming
mA
Note:
1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
86
32.2.4 Wake-up Time from Sleep Modes
Table 32-34. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Symbol Parameter
Condition
External 2MHz clock
Min.
Typ. (1)
2.0
Max.
Units
Wake-up time from idle,
standby, and extended standby
mode
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
120
2.0
0.2
twakeup
µs
5.0
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
320
9.0
Wake-up time from power-save
and power-down mode
5.0
Note:
1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-9. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 32-9. Wake-up Time Definition
Wakeup time
Wakeup request
Clock output
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
87
32.2.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 32-35. I/O Pin Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
(1)
IOH
IOL
/
I/O pin source/sink current
High level input voltage
-20
20
mA
(2)
VCC = 2.4 - 3.6V
0.7*Vcc
0.8*VCC
-0.5
VCC+0.5
VCC+0.5
0.3*VCC
0.2*VCC
VIH
VCC = 1.6 - 2.4V
VCC = 2.4- 3.6V
VCC = 1.6 - 2.4V
VCC = 3.3V
VIL
Low level input voltage
High level output voltage
-0.5
IOH = -4mA
IOH = -3mA
IOH = -1mA
IOL = 8mA
IOL = 5mA
IOL = 3mA
2.6
2.9
2.7
V
VOH
VCC = 3.0V
2.1
VCC = 1.8V
1.4
1.6
VCC = 3.3V
0.4
0.76
0.64
0.46
1
VOL
Low level output voltage
VCC = 3.0V
0.3
VCC = 1.8V
0.2
IIN
Input leakage current I/O pin
Pull/buss keeper resistor
T = 25°C
<0.01
25
µA
RP
k
Notes:
1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
88
32.2.6 ADC Characteristics
Table 32-36. Power Supply, Reference and Input Range
Symbol
AVCC
VREF
Rin
Parameter
Condition
Min.
VCC- 0.3
1
Typ.
Max.
VCC+ 0.3
AVCC- 0.6
4.5
Units
Analog supply voltage
Reference voltage
Input resistance
V
Switched
k
pF
Cin
Input capacitance
Reference input resistance
Switched
5
RAREF
CAREF
Vin
(leakage only)
>10
7
M
pF
Reference input capacitance Static load
Input range
0
VREF
VREF
Conversion range
Conversion range
Fixed offset voltage
Differential mode, Vinp - Vinn
-VREF
-V
V
Single ended unsigned mode, Vinp
VREF-V
∆V
200
LSB
Table 32-37. Clock and Timing
Symbol
ClkADC
fClkADC
Parameter
Condition
Min.
Typ.
Max.
Units
Maximum is 1/4 of peripheral clock
frequency
100
1800
ADC clock frequency
Sample rate
kHz
Measuring internal signals
125
300
300
250
150
50
Current limitation (CURRLIMIT) off
CURRLIMIT = LOW
16
ksps
µs
fADC
Sample rate
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
Configurable in steps of 1/2 ClkADC cycles
up to 32 ClkADC cycles
Sampling time
0.28
4.5
320
10
(RES+1)/2 + GAIN
RES (Resolution) = 8 or 12, GAIN=0 to 3
Conversion time (latency)
ClkADC
cycles
Start-up time
ADC clock cycles
12
7
24
7
ADC settling time
After changing reference or input mode
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
89
Table 32-38. Accuracy Characteristics
Symbol
Parameter
Condition(2)
Differential
Min.
Typ.
12
Max.
12
11
12
1
Units
8
7
8
RES
Resolution
12-bit resolution
Single ended signed
Single ended unsigned
16ksps, VREF = 3V
16ksps, all VREF
11
Bits
12
0.5
0.8
0.6
1
2
Differential mode
200ksps, VREF = 3V
200ksps, all VREF
16ksps, VREF = 3.0V
16ksps, all VREF
1
INL(1)
Integral non-linearity
2
0.5
1.3
0.3
0.5
0.35
0.5
0.6
0.6
8
1
Single ended
unsigned mode
2
lsb
16ksps, VREF = 3V
16ksps, all VREF
1
1
Differential mode
200ksps, VREF = 3V
200ksps, all VREF
16ksps, VREF = 3.0V
16ksps, all VREF
1
DNL(1)
Differential non-linearity
1
1
Single ended
unsigned mode
1
mV
Offset Error
Differential mode
Temperature drift
Operating voltage drift
External reference
AVCC/1.6
0.01
0.25
-5
mV/K
mV/V
-5
mV
AVCC/2.0
-6
Gain Error
Differential mode
Bandgap
±10
0.02
2
Temperature drift
Operating voltage drift
External reference
AVCC/1.6
mV/K
mV/V
-8
-8
mV
AVCC/2.0
-8
Single ended
unsigned mode
Gain Error
Bandgap
±10
0.03
2
Temperature drift
Operating voltage drift
mV/K
mV/V
Notes:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
90
Table 32-39. Gain Stage Characteristics
Rin
Input resistance
Input capacitance
Signal range
Switched in normal mode
Switched in normal mode
Gain stage output
4.0
4.4
k
pF
V
Csample
0
AVCC- 0.6
3
ClkADC
cycles
Propagation delay
Clock rate
ADC conversion rate
1/2
100
1
Same as ADC
1800
kHz
0.5x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
0.5x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
-1
-1
Gain error
%
-1
10
10
5
Offset error,
output referred
mV
-20
-150
32.2.7 Analog Comparator Characteristics
Table 32-40. Analog Comparator Characteristics
Symbol
Voff
Parameter
Condition
VCC=1.6V - 3.6V
Min.
Typ.
<±10
<1
Max.
Units
mV
nA
Input offset voltage
Input leakage current
Input voltage range
AC startup time
Hysteresis, none
Hysteresis, small
Hysteresis, large
Ilk
VCC=1.6V - 3.6V
-0.1
AVCC
V
100
0
µs
Vhys1
Vhys2
Vhys3
VCC=1.6V - 3.6V
VCC=1.6V - 3.6V
11
26
16
16
0.3
mV
VCC=1.6V - 3.6V
VCC = 3.0V, T= 85°C
VCC=1.6V - 3.6V
90
tdelay
Propagation delay
ns
64-level voltage scaler
Integral non-linearity (INL)
0.5
lsb
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
91
32.2.8 Bandgap and Internal 1.0V Reference Characteristics
Table 32-41. Bandgap and Internal 1.0V Reference Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
As reference for ADC
1 ClkPER + 2.5µs
Startup time
µs
As input voltage to ADC and AC
1.5
1.1
1
Bandgap voltage
V
INT1V
Internal 1.00V reference
T= 85°C, after calibration
0.98
1.02
Variation over voltage and temperature
Calibrated at T= 85°C, VCC = 3.0V
±1.0
%
32.2.9 Brownout Detection Characteristics
Table 32-42. Brownout Detection Characteristics(1)
Symbol Parameter
BOD level 0 falling VCC
BOD level 1 falling VCC
BOD level 2 falling VCC
Condition
Min.
Typ.
1.62
1.8
Max.
Units
1.50
1.75
2.0
BOD level 3 falling VCC
VBOT
2.2
V
BOD level 4 falling VCC
2.4
BOD level 5 falling VCC
BOD level 6 falling VCC
BOD level 7 falling VCC
2.6
2.8
3.0
Continuous mode
Sampled mode
0.4
tBOD
Detection time
Hysteresis
µs
%
1000
1.2
VHYST
Note:
1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
32.2.10 External Reset Characteristics
Table 32-43. External Reset Characteristics
Symbol Parameter
Condition
Min.
1000
Typ.
Max.
Units
tEXT
Minimum reset pulse width
90
ns
VCC = 2.7 - 3.6V
0.6*VCC
0.6*VCC
Reset threshold voltage (VIH)
VCC = 1.6 - 2.7V
VCC = 2.7 - 3.6V
VCC = 1.6 - 2.7V
VRST
V
0.5*VCC
0.4*VCC
Reset threshold voltage (VIL)
Reset pin pull-up resistor
RRST
25
k
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
92
32.2.11 Power-on Reset Characteristics
Table 32-44. Power-on Reset Characteristics
Symbol Parameter
Condition
VCC falls faster than 1V/ms
VCC falls at 1V/ms or slower
Min.
0.4
Typ.
1.0
Max.
Units
(1)
VPOT-
POR threshold voltage falling VCC
POR threshold voltage rising VCC
0.8
1.0
V
VPOT+
1.3
1.59
Note:
1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+
.
32.2.12 Flash and EEPROM Memory Characteristics
Table 32-45. Endurance and Data Retention
Symbol Parameter
Condition
Min.
10K
10K
2K
Typ.
Max.
Units
25°C
85°C
105°C
25°C
85°C
105°C
25°C
85°C
105°C
25°C
85°C
105°C
Write/Erase cycles
Cycle
Flash
100
25
Data retention
Year
Cycle
Year
10
100K
100K
30K
100
25
Write/Erase cycles
Data retention
EEPROM
10
Table 32-46. Programming Time
Symbol Parameter
Condition
Min.
Typ.(1)
Max.
Units
Chip erase(2)
32KB Flash, EEPROM
Page erase
50
4
Flash
Page write
4
Atomic page erase and write
Page erase
8
ms
4
EEPROM
Page write
4
Atomic page erase and write
8
Notes:
1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
93
32.2.13 Clock and Oscillator Characteristics
32.2.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 32-47. 32.768kHz Internal Oscillator Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Frequency
32.768
kHz
Factory calibration accuracy
User calibration accuracy
T = 85C, VCC = 3.0V
-0.5
-0.5
0.5
0.5
%
32.2.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 32-48. 2MHz Internal Oscillator Characteristics
Symbol Parameter
Frequency range
Condition
Min.
Typ.
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
1.8
2.2
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration stepsize
2.0
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.18
32.2.13.3 Calibrated and Tunable 32MHz Internal Oscillator Characteristics
Table 32-49. 32MHz Internal Oscillator Characteristics
Symbol Parameter
Frequency range
Condition
Min.
Typ.
32
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
30
55
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration step size
32
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.19
32.2.13.4 32kHz Internal ULP Oscillator Characteristics
Table 32-50. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Factory calibrated frequency
32
kHz
Factory calibration accuracy
Accuracy
T = 85C, VCC= 3.0V
-12
-30
12
30
%
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
94
32.2.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 32-51. Internal PLL Characteristics
Symbol Parameter
Condition
Min.
0.4
20
Typ.
Max.
64
Units
fIN
Input frequency
Output frequency must be within fOUT
VCC= 1.6 - 1.8V
48
MHz
fOUT
Output frequency(1)
VCC= 2.7 - 3.6V
20
128
Start-up time
Re-lock time
25
25
µs
Note:
1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
32.2.13.6External Clock Characteristics
Figure 32-10.External Clock Drive Waveform
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 32-52. External Clock(1)
Symbol Parameter
Condition
VCC = 1.6 - 1.8V
Min.
0
Typ.
Max.
90
Units
1/tCK
Clock frequency(2)
Clock period
MHz
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
0
142
11
tCK
7.0
4.5
2.4
ns
tCH/CL
Clock high/low time
VIL/IH
Low/high level input voltage
See Table 32-7 on page 69
10
V
Reduction in period time from one
clock cycle to the next
tCK
%
Notes:
1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
95
32.2.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 32-53. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter
.
Condition
Min.
Typ.
0
Max.
Units
FRQRANGE=0
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
Cycle to cycle jitter
FRQRANGE=1, 2, or 3
0
0
ns
FRQRANGE=0
0
Long term jitter
Frequency error
FRQRANGE=1, 2, or 3
0
0
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
0.03
0.03
0.03
0.003
50
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
%
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
50
Duty cycle
50
50
0.4MHz resonator,
CL=100pF
44k
XOSCPWR=0,
FRQRANGE=0
1MHz crystal, CL=20pF
2MHz crystal, CL=20pF
2MHz crystal
67k
67k
82k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
8MHz crystal
1500
1500
2700
2700
1000
3600
1300
590
9MHz crystal
RQ
Negative impedance
8MHz crystal
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
9MHz crystal
12MHz crystal
9MHz crystal
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
12MHz crystal
16MHz crystal
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
96
Symbol Parameter
Condition
Min.
Typ.
390
50
Max.
Units
9MHz crystal
12MHz crystal
16MHz crystal
9MHz crystal
12MHz crystal
16MHz crystal
12MHz crystal
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
10
1500
650
270
1000
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
RQ
Negative impedance
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
16MHz crystal
12MHz crystal
16MHz crystal
440
1300
590
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
ESR
SF = safety factor
min(RQ)/SF
k
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF
1.0
2.6
0.8
1.0
1.4
5.9
XOSCPWR=0,
FRQRANGE=1
2MHz crystal, CL=20pF
8MHz crystal, CL=20pF
12MHz crystal, CL=20pF
16MHz crystal, CL=20pF
XOSCPWR=0,
FRQRANGE=2
Start-up time
ms
XOSCPWR=0,
FRQRANGE=3
XOSCPWR=1,
FRQRANGE=3
Parasitic capacitance
XTAL1 pin
CXTAL1
Parasitic capacitance
XTAL2 pin
pF
CXTAL2
CLOAD
8.3
3.5
Parasitic capacitance load
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
97
32.2.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 32-54. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Symbol
Parameter
Condition
Min.
Typ.
Max.
60
Units
Crystal load capacitance 6.5pF
Crystal load capacitance 9.0pF
Crystal load capacitance 12pF
k
Recommended crystal equivalent
series resistance (ESR)
ESR/R1
35
28
CTOSC1
CTOSC2
Parasitic capacitance TOSC1 pin
Parasitic capacitance TOSC2 pin
3.5
3.5
pF
capacitance load matched to
crystal specification
Recommended safety factor
3
Note:
See Figure 32-11 for definition.
Figure 32-11.TOSC Input Capacitance
CL1
CL2
Device internal
External
TOSC1
TOSC2
32.768KHz crystal
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
98
32.2.14 SPI Characteristics
Figure 32-12.SPI Timing Requirements in Master Mode
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
tMIH
MSB
tSCK
MISO
(Data Input)
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Figure 32-13.SPI Timing Requirements in Slave Mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
tSIH
MSB
tSSCK
LSB
MOSI
(Data Input)
tSOSSS
tSOS
tSOSSH
MISO
(Data Output)
MSB
LSB
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
99
Table 32-55. SPI Timing Characteristics and Requirements
Symbol Parameter Condition
Min.
Typ.
Max.
Units
(See Table 20-3 in
XMEGA C Manual)
tSCK
SCK period
Master
tSCKW
tSCKR
tSCKF
tMIS
SCK high/low width
SCK rise time
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
0.5*SCK
2.7
2.7
SCK fall time
MISO setup to SCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Slave SCK Period
SCK high/low width
SCK rise time
10
tMIH
10
tMOS
tMOH
tSSCK
tSSCKW
tSSCKR
tSSCKF
tSIS
0.5*SCK
1
4*t ClkPER
2*t ClkPER
ns
1600
1600
SCK fall time
MOSI setup to SCK
MOSI hold after SCK
SS setup to SCK
SS hold after SCK
MISO setup SCK
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
3
t ClkPER
21
tSIH
tSSS
tSSH
20
tSOS
8
13
11
8
tSOH
tSOSS
tSOSH
32.2.15 Two-Wire Interface Characteristics
Table 32-56 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA
Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-
14.
Figure 32-14.Two-wire Interface Bus Timing
tof
tHIGH
tLOW
tr
SCL
SDA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
tHD;STA
tBUF
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
100
Table 32-56. Two-wire Interface Characteristics
Symbol Parameter
Condition
Min.
0.7VCC
-0.5
Typ.
Max.
VCC+0.5
0.3VCC
Units
VIH
VIL
Input high voltage
Input low voltage
V
(1)
Vhys
Hysteresis of Schmitt trigger inputs
Output low voltage
0.05VCC
0
VOL
3mA, sink current
0.4
300
250
50
(1)(2)
(1)(2)
tr
tof
Rise time for both SDA and SCL
Output fall time from VIHmin to VILmax
Spikes suppressed by input filter
Input current for each I/O Pin
Capacitance for each I/O Pin
SCL clock frequency
20+0.1Cb
20+0.1Cb
0
10pF < Cb < 400pF (2)
0.1VCC < VI < 0.9VCC
ns
tSP
II
-10
10
µA
pF
CI
10
fSCL
fPER (3)>max(10fSCL, 250kHz)
fSCL 100kHz
0
400
kHz
100ns
--------------
Cb
VCC – 0.4V
---------------------------
3mA
RP
Value of pull-up resistor
300ns
fSCL > 100kHz
--------------
Cb
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
0
tHD;STA
Hold time (repeated) START condition
Low period of SCL clock
tLOW
µs
tHIGH
High period of SCL clock
Set-up time for a repeated START
condition
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
3.45
0.9
Data hold time
Data setup time
µs
ns
µs
µs
0
250
100
4.0
0.6
4.7
1.3
Setup time for STOP condition
Bus free time between a STOP and
START condition
Notes:
1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3.
fPER = Peripheral clock frequency.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
101
32.3 ATxmega64D4
32.3.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 32-57 under may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 32-57. Absolute Maximum Ratings
Symbol
VCC
Parameter
Condition
Min.
Typ.
Max.
4
Units
Power supply voltage
Current into a VCC pin
Current out of a Gnd pin
-0.3
V
IVCC
200
200
mA
IGND
Pin voltage with respect to Gnd
and VCC
VPIN
-0.5
VCC+0.5
V
IPIN
TA
Tj
I/O pin sink/source current
Storage temperature
-25
-65
25
mA
150
150
°C
Junction temperature
32.3.2 General Operating Ratings
The device must operate within the ratings listed in Table 32-58 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 32-58. General Operating Conditions
Symbol
VCC
Parameter
Condition
Min.
1.60
1.60
-40
Typ.
Max.
3.6
Units
Power supply voltage
Analog supply voltage
Temperature range
Junction temperature
V
AVCC
TA
3.6
85
°C
Tj
-40
105
Table 32-59. Operating Voltage and Frequency
Symbol
Parameter
Condition
VCC = 1.6V
Min.
Typ.
Max.
12
Units
0
0
0
0
VCC = 1.8V
VCC = 2.7V
VCC = 3.6V
12
ClkCPU
CPU clock frequency
MHz
32
32
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
102
The maximum CPU clock frequency depends on VCC. As shown in Figure 32-15 the Frequency vs. VCC curve is linear
between 1.8V < VCC < 2.7V.
Figure 32-15.Maximum Frequency vs. VCC
MHz
32
Safe Operating Area
12
V
1.6
1.8
2.7
3.6
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
103
32.3.3 Current Consumption
Table 32-60. Current Consumption for Active Mode and Sleep Modes
Symbol Parameter
Condition
Min.
Typ.
68
Max.
Units
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
32kHz, Ext. Clk
145
260
540
460
0.96
9.8
2.4
3.9
62
µA
1MHz, Ext. Clk
Active power
consumption(1)
600
1.4
12
2MHz, Ext. Clk
32MHz, Ext. Clk
32kHz, Ext. Clk
VCC = 3.0V
mA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
1MHz, Ext. Clk
2MHz, Ext. Clk
µA
Idle power
118
125
240
3.8
0.1
1.2
0.1
consumption(1)
225
350
5.5
1.0
4.5
6.0
VCC = 3.0V
32MHz, Ext. Clk
T = 25°C
mA
ICC
T = 85°C
VCC = 3.0V
T = 105°C
WDT and sampled BOD enabled,
T = 25°C
Power-down power
consumption
1.3
2.4
1.3
3.0
6.0
8.0
WDT and sampled BOD enabled,
T = 85°C
VCC = 3.0V
WDT and sampled BOD enabled,
T = 105°C
µA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
1.2
1.3
0.6
0.7
0.8
1.0
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
2
2
3
3
Power-save power
consumption(2)
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
RTC from low power 32.768kHz
TOSC, T = 25°C
Current through RESET pin
substracted
Reset power consumption
VCC = 3.0V
320
Notes:
1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
104
Table 32-61. Current Consumption for Modules and Peripherals
Symbol Parameter
Condition(1)
Min.
Typ.
1.0
27
Max.
Units
ULP oscillator
32.768kHz int. oscillator
85
2MHz int. oscillator
32MHz int. oscillator
DFLL enabled with 32.768kHz int. osc. as reference
DFLL enabled with 32.768kHz int. osc. as reference
115
270
460
µA
20x multiplication factor,
32MHz int. osc. DIV4 as reference
PLL
220
Watchdog Timer
1.0
138
1.2
100
95
Continuous mode
BOD
Sampled mode, includes ULP oscillator
ICC
Internal 1.0V reference
Temperature sensor
3.0
2.6
2.1
1.6
330
16
CURRLIMIT = LOW
150ksps
ADC
mA
VREF = Ext ref
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
High Speed Mode
AC
Timer/Counter
USART
µA
Rx and Tx enabled, 9600 BAUD
2.5
4
Flash memory and EEPROM programming
8
mA
Note:
1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
105
32.3.4 Wake-up Time from Sleep Modes
Table 32-62. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Symbol Parameter
Condition
External 2MHz clock
Min.
Typ.(1)
2.0
Max.
Units
Wake-up time from Idle,
Standby, and Extended Standby
mode
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
120
2.0
0.2
twakeup
µs
4.5
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
320
9.0
Wake-up time from Power-save
and Power-down mode
5.0
Note:
1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-16. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 32-16.Wake-up Time Definition
Wakeup time
Wakeup request
Clock output
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
106
32.3.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 32-63. I/O Pin Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
mA
V
(1)
IOH
/
I/O pin source/sink current
-15
15
(2)
IOL
VCC = 2.7 - 3.6V
2
0.7*VCC
0.7*VCC
-0.3
VCC+0.3
VCC+0.3
VCC+0.3
0.3*VCC
0.3*VCC
0.3*VCC
VIH
High level input voltage
VCC = 2.0 - 2.7V
VCC = 1.6 - 2.0V
VCC = 2.7- 3.6V
VCC = 2.0 - 2.7V
VCC = 1.6 - 2.0V
VCC = 3.0 - 3.6V
VCC = 3.3V
VIL
Low level input voltage
High level output voltage
-0.3
-0.3
IOH = -2mA
IOH = -4mA
IOH = -3mA
IOH = -1mA
IOL = 2mA
IOL = 8mA
IOL = 5mA
IOL = 3mA
2.4
0.94*VCC
2.9
2.6
VOH
VCC = 3.0V
2.1
2.6
VCC = 1.8V
1.4
1.6
VCC = 3.0 - 3.6V
VCC = 3.3V
0.05*VCC
0.4
0.4
0.76
0.64
0.46
0.1
VOL
Low level output voltage
VCC = 3.0V
0.3
VCC = 1.8V
0.2
IIN
RP
tr
Input leakage current
Pull/Buss keeper resistor
Rise time
T = 25°C
<0.001
24
µA
k
ns
No load
4
Notes:
1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC must not exceed 200mA.
The sum of all IOH for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOH for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC must not exceed 200mA.
The sum of all IOL for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOL for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
107
32.3.6 ADC Characteristics
Table 32-64. Power Supply, Reference and Input Range
Symbol
AVCC
Parameter
Condition
Min.
VCC- 0.3
1.0
Typ.
Max.
Units
Analog supply voltage
Reference voltage
Input resistance
VCC+ 0.3
AVCC- 0.6
V
VREF
Rin
Csample
RAREF
CAREF
VIN
Switched
4.0
4.4
>10
7.0
k
pF
Input capacitance
Reference input resistance
Switched
(leakage only)
M
pF
Reference input capacitance Static load
Input range
-0.1
-VREF
-V
AVCC+0.1
VREF
Conversion range
Conversion range
Fixed offset voltage
Differential mode, Vinp - Vinn
V
VIN
Single ended unsigned mode, Vinp
VREF-V
∆V
190
LSB
Table 32-65. Clock and Timing
Symbol
ClkADC
fClkADC
Parameter
Condition
Min.
100
100
Typ.
Max.
Units
Maximum is 1/4 of Peripheral clock
frequency
1400
ADC clock frequency
Sample rate
kHz
Measuring internal signals
125
200
200
150
100
50
Current limitation (CURRLIMIT) off
CURRLIMIT = LOW
14
ksps
µs
fADC
Sample rate
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
Sampling time
1/2 ClkADC cycle
0.25
5
5
(RES+2)/2+GAIN
RES = 8 or 12, GAIN = 0, 1, 2 or 3
ClkADC
cycles
Conversion time (latency)
Start-up time
7
10
ADC clock cycles
12
7
24
7
ClkADC
cycles
After changing reference or input mode
After ADC flush
ADC settling time
1
1
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
108
Table 32-66. Accuracy Characteristics
Symbol
Parameter
Condition(2)
Min.
Typ.
12
Max.
12
Units
RES
Resolution
Programmable to 8 or 12 bit
8
Bits
VCC-1.0V < VREF< VCC-0.6V
±1.2
±1.5
±1.0
±1.5
<±0.8
-1
±3
50ksps
All VREF
VCC-1.0V < VREF< VCC-0.6V
All VREF
±4
INL(1)
Integral non-linearity
±3
lsb
200ksps
±4
DNL(1)
Differential non-linearity
Offset error
guaranteed monotonic
<±1
mV
Temperature drift
<0.01
<0.6
-1
mV/K
mV/V
Operating voltage drift
External reference
AVCC/1.6
AVCC/2.0
Bandgap
10
Differential
mode
mV
8
Gain error
±5
Temperature drift
<0.02
<0.5
mV/K
mV/V
Operating voltage drift
Differential mode, shorted input
200ksps, VCC = 3.6V, ClkPER = 16MHz
mV
rms
Noise
0.4
Notes:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
109
Table 32-67. Gain Stage Characteristics
Symbol
Rin
Csample
Parameter
Condition
Switched in normal mode
Switched in normal mode
Gain stage output
Min.
Typ.
4.0
Max.
Units
k
pF
Input resistance
Input capacitance
Signal range
4.4
0
VCC- 0.6
V
ClkADC
cycles
Propagation delay
Sample rate
ADC conversion rate
Same as ADC
50ksps
1
14
200
±4
kHz
lsb
All gain
settings
INL(1)
Integral non-linearity
±1.5
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
-0.8
-2.5
-3.5
-2
Gain error
%
Offset error,
output referred
-5
mV
-4
0.5
1.5
11
VCC = 3.6V
Ext. VREF
mV
rms
Noise
Note:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
32.3.7 Analog Comparator Characteristics
Table 32-68. Analog Comparator Characteristics
Symbol
Voff
Parameter
Condition
Min.
Typ.
<±10
<1
Max.
Units
mV
nA
Input offset voltage
Input leakage current
Input voltage range
AC startup time
Hysteresis, none
Hysteresis, small
Hysteresis, large
Ilk
-0.1
AVCC
V
100
0
µs
Vhys1
Vhys2
Vhys3
13
30
30
30
0.3
mV
VCC = 3.0V, T= 85°C
mode = HS
90
tdelay
Propagation delay
ns
64-Level voltage scaler
Integral non-linearity (INL)
0.5
lsb
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
110
32.3.8 Bandgap and Internal 1.0V Reference Characteristics
Table 32-69. Bandgap and Internal 1.0V Reference Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
As reference for ADC
1 ClkPER + 2.5µs
Startup time
µs
As input voltage to ADC and AC
1.5
1.1
Bandgap voltage
V
INT1V
Internal 1.00V reference
T= 85°C, after calibration
0.99
1.0
1.01
Variation over voltage and temperature
Relative to T= 85°C, VCC = 3.0V
±1.5
%
32.3.9 Brownout Detection Characteristics
Table 32-70. Brownout Detection Characteristics
Symbol Parameter
BOD level 0 falling VCC
BOD level 1 falling VCC
BOD level 2 falling VCC
Condition
Min.
Typ.
1.62
1.8
Max.
Units
1.60
1.72
2.0
BOD level 3 falling VCC
VBOT
2.2
V
BOD level 4 falling VCC
2.4
BOD level 5 falling VCC
BOD level 6 falling VCC
BOD level 7 falling VCC
2.6
2.8
3.0
Continuous mode
Sampled mode
0.4
tBOD
Detection time
Hysteresis
µs
%
1000
1.2
VHYST
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
111
32.3.10 External Reset Characteristics
Table 32-71. External Reset Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
tEXT
Minimum reset pulse width
1000
95
ns
VCC = 2.7 - 3.6V
0.60*VCC
0.60*VCC
Reset threshold voltage (VIH)
VCC = 1.6 - 2.7V
VCC = 2.7 - 3.6V
VCC = 1.6 - 2.7V
0.50*VCC
0.40*VCC
0.50*VCC
VRST
V
Reset threshold voltage (VIL)
Reset pin pull-up resistor
RRST
25
k
32.3.11 Power-on Reset Characteristics
Table 32-72. Power-on Reset Characteristics
Symbol Parameter
Condition
Min.
0.4
Typ.
1.0
Max.
Units
VCC falls faster than 1V/ms
VCC falls at 1V/ms or slower
(1)
VPOT-
POR threshold voltage falling VCC
POR threshold voltage rising VCC
0.8
1.0
V
VPOT+
1.3
1.59
Note:
1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+
.
32.3.12 Flash and EEPROM Memory Characteristics
Table 32-73. Endurance and Data Retention
Symbol Parameter
Condition
Min.
10K
10K
2K
Typ.
Max.
Units
25°C
85°C
105°C
25°C
85°C
105°C
25°C
85°C
105°C
25°C
85°C
105°C
Write/Erase cycles
Cycle
Flash
100
25
Data retention
Year
Cycle
Year
10
100K
100K
30K
100
25
Write/Erase cycles
Data retention
EEPROM
10
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
112
Table 32-74. Programming Time
Symbol Parameter
Condition
64KB Flash, EEPROM(2) and SRAM erase
Page erase
Min.
Typ.(1)
Max.
Units
Chip erase
55
4
ms
Flash
Page write
4
Atomic Page Erase and write
Page erase
8
4
EEPROM
Page write
4
Atomic Page erase and write
8
Notes:
1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
32.3.13 Clock and Oscillator Characteristics
32.3.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 32-75. 32.768kHz Internal Oscillator Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Frequency
32.768
kHz
Factory calibration accuracy
User calibration accuracy
T = 85C, VCC = 3.0V
-0.5
-0.5
0.5
0.5
%
32.3.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 32-76. 2MHz Internal Oscillator Characteristics
Symbol Parameter
Frequency range
Condition
Min.
Typ.
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
1.8
2.2
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration stepsize
2.0
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.21
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
113
32.3.13.3 Calibrated and Tunable 32MHz Internal Oscillator Characteristics
Table 32-77. 32MHz Internal Oscillator Characteristics
Symbol Parameter
Frequency range
Condition
Min.
Typ.
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
30
55
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration step size
32
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.22
32.3.13.4 32kHz Internal ULP Oscillator Characteristics
Table 32-78. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Factory calibrated frequency
32
kHz
Factory calibration accuracy
Accuracy
T = 85C, VCC= 3.0V
-12
-30
12
30
%
32.3.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 32-79. Internal PLL Characteristics
Symbol Parameter
Condition
Min.
0.4
20
Typ.
Max.
64
Units
fIN
Input frequency
Output frequency must be within fOUT
VCC= 1.6 - 1.8V
48
MHz
fOUT
Output frequency(1)
VCC= 2.7 - 3.6V
20
128
Start-up time
Re-lock time
25
25
µs
Note:
1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
114
32.3.13.6 External Clock Characteristics
Figure 32-17.External Clock Drive Waveform
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 32-80. External Clock Used as System Clock without Prescaling
Symbol Parameter Condition
Clock frequency(1)
Min.
0
Typ.
Max.
12
Units
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
1/tCK
MHz
0
32
83.3
31.5
30.0
12.5
30.0
12.5
tCK
Clock period
tCH
Clock high time
tCL
Clock low time
ns
10
3
tCR
Rise time (for maximum frequency)
10
3
tCF
Fall time (for maximum frequency)
tCK
Change in period from one clock cycle to the next
10
%
Note:
1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
115
Table 32-81. External Clock with Prescaler(1) for System Clock
Symbo
l
Parameter
Condition
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
Min.
0
Typ.
Max.
90
Units
1/tCK
Clock frequency(2)
MHz
0
142
11
tCK
tCH
tCL
Clock period
7
4.5
2.4
4.5
2.4
Clock high time
Clock low time
ns
tCR
tCF
Rise time (for maximum frequency)
1.5
1.5
10
Fall time (for maximum frequency)
tCK
Change in period from one clock cycle to the next
%
Notes:
1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
32.3.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 32-82. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter
Condition
Min.
Typ.
<10
<1
Max.
Units
FRQRANGE=0
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
Cycle to cycle jitter
FRQRANGE=1, 2, or 3
<1
ns
FRQRANGE=0
<6
Long term jitter
Frequency error
FRQRANGE=1, 2, or 3
<0.5
<0.5
<0.1
<0.05
<0.005
<0.005
40
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
%
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
42
Duty cycle
45
48
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
116
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
0.4MHz resonator,
CL=100pF
2.4k
XOSCPWR=0,
FRQRANGE=0
1MHz crystal, CL=20pF
2MHz crystal, CL=20pF
2MHz crystal
8.7k
2.1k
4.2k
250
195
360
285
155
365
200
105
435
235
125
495
270
145
305
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
8MHz crystal
9MHz crystal
8MHz crystal
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
9MHz crystal
12MHz crystal
9MHz crystal
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
RQ
Negative impedance(1)
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
12MHz crystal
16MHz crystal
12MHz crystal
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
16MHz crystal
12MHz crystal
16MHz crystal
160
380
205
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
ESR
SF = safety factor
min(RQ)/SF
k
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF
1.0
2.6
0.8
1.0
1.4
XOSCPWR=0,
FRQRANGE=1
2MHz crystal, CL=20pF
8MHz crystal, CL=20pF
12MHz crystal, CL=20pF
16MHz crystal, CL=20pF
XOSCPWR=0,
FRQRANGE=2
Start-up time
ms
XOSCPWR=0,
FRQRANGE=3
XOSCPWR=1,
FRQRANGE=3
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
117
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Parasitic capacitance
XTAL1 pin
CXTAL1
5.9
Parasitic capacitance
XTAL2 pin
pF
CXTAL2
CLOAD
8.3
3.5
Parasitic capacitance load
Note:
1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
32.3.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 32-83. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Symbol Parameter
Condition
Crystal load capacitance 6.5pF
Crystal load capacitance 9.0pF
Normal mode
Min.
Typ.
Max.
60
Units
Recommended crystal equivalent
ESR/R1
CTOSC
k
series resistance (ESR)
35
4.7
5.2
Parasitic capacitance
pF
Low power mode
Capacitance load matched to
crystal specification
Recommended safety factor
3
Note:
1. See Figure 32-18 on page 118 for definition.
Figure 32-18.TOSC Input Capacitance
CL1
CL2
Device internal
External
TOSC1
TOSC2
32.768KHz crystal
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
118
32.3.14 SPI Characteristics
Figure 32-19.SPI Timing Requirements in Master Mode
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
tMIH
MSB
tSCK
MISO
(Data Input)
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Figure 32-20.SPI Timing Requirements in Slave Mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
tSIH
MSB
tSSCK
LSB
MOSI
(Data Input)
tSOSSS
tSOS
tSOSSH
MISO
(Data Output)
MSB
LSB
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
119
Table 32-84. SPI Timing Characteristics and Requirements
Symbol Parameter Condition
Min.
Typ.
Max.
Units
(See Table 17-4 in
XMEGA D Manual)
tSCK
SCK period
Master
tSCKW
tSCKR
tSCKF
tMIS
SCK high/low width
SCK rise time
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
0.5*SCK
2.7
2.7
SCK fall time
MISO setup to SCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Slave SCK period
SCK high/low width
SCK rise time
10
tMIH
10
tMOS
tMOH
tSSCK
tSSCKW
tSSCKR
tSSCKF
tSIS
0.5*SCK
1
4*t ClkPER
2*t ClkPER
ns
1600
1600
SCK fall time
MOSI setup to SCK
MOSI hold after SCK
SS setup to SCK
SS hold after SCK
MISO setup SCK
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
3
t ClkPER
21
tSIH
tSSS
tSSH
20
tSOS
8.0
13.0
11.0
8.0
tSOH
tSOSS
tSOSH
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
120
32.3.15 Two-Wire Interface Characteristics
Table 32-85 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA
Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-
21.
Figure 32-21.Two-wire Interface Bus Timing
tof
tHIGH
tLOW
tr
SCL
SDA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
tHD;STA
tBUF
Table 32-85. Two-wire Interface Characteristics
Symbol Parameter
Condition
Min.
0.7*VCC
-0.5
Typ.
Max.
Units
VIH
VIL
Vhys
VOL
tr
Input high voltage
VCC+0.5
0.3*VCC
Input low voltage
V
(1)
Hysteresis of Schmitt Trigger Inputs
Output low voltage
0.05*VCC
0
3mA, sink current
0.4
300
250
50
(1)(2)
Rise time for both SDA and SCL
Output fall time from VIHmin to VILmax
Spikes suppressed by input filter
Input current for each I/O pin
Capacitance for each I/O pin
SCL clock frequency
20+0.1Cb
20+0.1Cb
0
(1)(2)
tof
10pF < Cb < 400pF(2)
0.1VCC < VI < 0.9VCC
ns
tSP
II
-10
10
µA
pF
CI
10
fSCL
fPER(3)>max(10fSCL, 250kHz)
0
400
kHz
fSCL 100kHz
100ns
Cb
--------------
VCC – 0.4V
---------------------------
3mA
RP
Value of pull-up resistor
300ns
fSCL > 100kHz
--------------
Cb
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
121
Symbol Parameter
Condition
fSCL 100kHz
Min.
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
0
Typ.
Max.
Units
tHD;STA
Hold time (repeated) START condition
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
tLOW
Low period of SCL clock
High period of SCL clock
µs
tHIGH
Set-up time for a repeated START
condition
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
3.45
0.9
Data hold time
µs
ns
µs
µs
0
250
100
4.0
0.6
4.7
1.3
Data setup time
Setup time for STOP condition
Bus free time between a STOP and
START condition
Notes:
1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
122
32.4 ATxmega128D4
32.4.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 32-86 under may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 32-86. Absolute Maximum Ratings
Symbol
VCC
Parameter
Condition
Min.
Typ.
Max.
4
Units
Power supply voltage
Current into a VCC pin
Current out of a Gnd pin
-0.3
V
IVCC
200
200
mA
IGND
Pin voltage with respect to Gnd
and VCC
VPIN
-0.5
VCC+0.5
V
IPIN
TA
Tj
I/O pin sink/source current
Storage temperature
-25
-65
25
mA
150
150
°C
Junction temperature
32.4.2 General Operating Ratings
The device must operate within the ratings listed in Table 32-87 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 32-87. General Operating Conditions
Symbol
VCC
Parameter
Condition
Min.
1.60
1.60
-40
Typ.
Max.
3.6
Units
Power supply voltage
Analog supply voltage
Temperature range
Junction temperature
V
AVCC
TA
3.6
85
°C
Tj
-40
105
Table 32-88. Operating Voltage and Frequency
Symbol
Parameter
Condition
VCC = 1.6V
Min.
Typ.
Max.
12
Units
0
0
0
0
VCC = 1.8V
VCC = 2.7V
VCC = 3.6V
12
ClkCPU
CPU clock frequency
MHz
32
32
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
123
The maximum CPU clock frequency depends on VCC. As shown in Figure 32-22 the Frequency vs. VCC curve is linear
between 1.8V < VCC < 2.7V.
Figure 32-22.Maximum Frequency vs. VCC
MHz
32
Safe Operating Area
12
V
1.6
1.8
2.7
3.6
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
124
32.4.3 Current Consumption
Table 32-89. Current Consumption for Active Mode and Sleep Modes
Symbol Parameter
Condition
Min.
Typ.
55
Max.
Units
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
32kHz, Ext. Clk
135
255
535
460
1.0
9.5
2.9
3.9
62
µA
1MHz, Ext. Clk
Active power
consumption(1)
600
1.4
12
2MHz, Ext. Clk
32MHz, Ext. Clk
32kHz, Ext. Clk
VCC = 3.0V
mA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
1MHz, Ext. Clk
2MHz, Ext. Clk
µA
Idle power
118
125
240
3.8
0.1
1.5
0.1
consumption(1)
225
350
5.5
1.0
4.5
8.6
VCC = 3.0V
32MHz, Ext. Clk
T = 25°C
mA
ICC
T = 85°C
VCC = 3.0V
T = 105°C
WDT and sampled BOD enabled,
T = 25°C
Power-down power
consumption
1.4
2.8
1.4
3.0
6.0
8.8
WDT and sampled BOD enabled,
T = 85°C
VCC = 3.0V
WDT and sampled BOD enabled,
T = 105°C
µA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
1.2
1.5
0.6
0.7
0.8
1.0
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
2.0
2.0
3.0
3.0
Power-save power
consumption(2)
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
RTC from low power 32.768kHz
TOSC, T = 25°C
Current through RESET pin
substracted
Reset power consumption
VCC = 3.0V
300
Notes:
1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
125
Table 32-90. Current Consumption for Modules and Peripherals
Symbol Parameter
Condition(1)
Min.
Typ.
1.0
29
Max.
Units
ULP oscillator
32.768kHz int. oscillator
85
2MHz int. oscillator
32MHz int. oscillator
DFLL enabled with 32.768kHz int. osc. as reference
DFLL enabled with 32.768kHz int. osc. as reference
115
270
440
µA
20x multiplication factor,
32MHz int. osc. DIV4 as reference
PLL
320
Watchdog Timer
1.0
138
1.2
260
250
3.0
2.6
2.1
1.6
330
130
16
Continuous mode
BOD
Sampled mode, includes ULP oscillator
ICC
Internal 1.0V reference
Temperature sensor
CURRLIMIT = LOW
150ksps
VREF = Ext ref
ADC
mA
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
High Speed mode
AC
Low power mode
µA
Timer/Counter
USART
Rx and Tx enabled, 9600 BAUD
2.5
4.0
Flash memory and EEPROM programming
8.0
mA
Note:
1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
126
32.4.4 Wake-up Time from Sleep Modes
Table 32-91. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Symbol Parameter
Condition
External 2MHz clock
Min.
Typ.(1)
2.0
Max.
Units
Wake-up time from Idle,
Standby, and Extended Standby
mode
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
120
2.0
0.2
twakeup
µs
4.5
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
320
9.0
Wake-up time from Power-save
and Power-down mode
5.0
Note:
1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-23. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 32-23.Wake-up Time Definition
Wakeup time
Wakeup request
Clock output
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
127
32.4.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 32-92. I/O Pin Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
(1)
IOH
/
I/O pin source/sink current
-20
20
mA
(2)
IOL
VCC = 2.7 - 3.6V
2.0
0.7*VCC
0.8*VCC
-0.3
VCC+0.3
VCC+0.3
VCC+0.3
0.8
VIH
High level input voltage
VCC = 2.0 - 2.7V
VCC = 1.6 - 2.0V
VCC = 2.7- 3.6V
VCC = 2.0 - 2.7V
VCC = 1.6 - 2.0V
VCC = 3.0 - 3.6V
VIL
Low level input voltage
-0.3
0.3*VCC
0.2*VCC
-0.3
IOH = -2mA
IOH = -1mA
IOH = -2mA
IOH = -8mA
IOH = -6mA
IOH = -2mA
IOL = 2mA
IOL = 1mA
IOL = 2mA
IOL = 15mA
IOL = 10mA
IOL = 5mA
2.4
0.94*VCC
0.96*VCC
0.92*VCC
2.9
2.0
VCC = 2.3 - 2.7V
1.7
VOH
High level output voltage
V
VCC = 3.3V
2.6
VCC = 3.0V
2.1
2.6
VCC = 1.8V
1.4
1.6
VCC = 3.0 - 3.6V
0.05
0.03
0.06
0.4
0.4
0.4
VCC = 2.3 - 2.7V
0.7
VOL
Low level output voltage
VCC = 3.3V
VCC = 3.0V
VCC = 1.8V
T = 25°C
0.76
0.64
0.46
0.1
0.3
0.2
IIN
Input leakage current
<0.01
24
µA
RP
Pull/Buss keeper resistor
k
4.0
tr
Rise time
No load
ns
slew rate limitation
7.0
Notes:
1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC must not exceed 200mA.
The sum of all IOH for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOH for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC must not exceed 200mA.
The sum of all IOL for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOL for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
128
32.4.6 ADC Characteristics
Table 32-93. Power Supply, Reference and Input Range
Symbol
AVCC
VREF
Parameter
Condition
Min.
VCC- 0.3
1.0
Typ.
Max.
Units
Analog supply voltage
Reference voltage
Input resistance
VCC+ 0.3
AVCC- 0.6
V
Rin
Switched
4.0
4.4
>10
7.0
k
pF
Csample
RAREF
CAREF
VIN
Input capacitance
Reference input resistance
Switched
(leakage only)
M
pF
Reference input capacitance Static load
Input range
-0.1
-VREF
-V
AVCC+0.1
VREF
Conversion range
Conversion range
Fixed offset voltage
Differential mode, Vinp - Vinn
V
Single ended unsigned mode, Vinp
VREF-V
∆V
190
lsb
Table 32-94. Clock and Timing
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Maximum is 1/4 of Peripheral clock
frequency
100
1400
ClkADC
ADC clock frequency
kHz
Measuring internal signals
Current limitation (CURRLIMIT) off
CURRLIMIT = LOW
100
14
125
200
150
100
50
14
fADC
Sample rate
ksps
µs
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
14
Sampling time
1/2 ClkADC cycle
0.25
5
5
(RES+2)/2+GAIN
RES = 8 or 12, GAIN = 0, 1, 2 or 3
ClkADC
cycles
Conversion time (latency)
Start-up time
7
10
ADC clock cycles
12
7
24
7
ClkADC
cycles
After changing reference or input mode
After ADC flush
ADC settling time
1
1
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
129
Table 32-95. Accuracy Characteristics
Symbol
Parameter
Condition(2)
Min.
Typ.
12
Max.
12
Units
RES
Resolution
Programmable to 8 or 12 bit
8
Bits
VCC-1.0V < VREF< VCC-0.6V
±1.2
±1.5
±1.0
±1.5
<±0.8
-1
±2
50ksps
All VREF
VCC-1.0V < VREF< VCC-0.6V
All VREF
±3
INL(1)
Integral non-linearity
±2
lsb
200ksps
±3
DNL(1)
Differential non-linearity
Offset error
guaranteed monotonic
<±1
mV
Temperature drift
<0.01
<0.6
-1
mV/K
mV/V
Operating voltage drift
External reference
AVCC/1.6
AVCC/2.0
Bandgap
10
Differential
mode
mV
8
Gain error
±5
Temperature drift
<0.02
<0.5
mV/K
mV/V
Operating voltage drift
Differential mode, shorted input
200ksps, VCC = 3.6V, ClkPER = 16MHz
mV
rms
Noise
0.4
Notes:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
130
Table 32-96. Gain Stage Characteristics
Symbol
Rin
Parameter
Condition
Switched in normal mode
Switched in normal mode
Gain stage output
Min.
Typ.
4.0
Max.
Units
k
pF
Input resistance
Input capacitance
Signal range
Csample
4.4
0
VCC- 0.6
V
ClkADC
cycles
Propagation delay
Sample rate
ADC conversion rate
Same as ADC
50ksps
1
14
200
±4
kHz
lsb
All gain
settings
INL(1)
Integral non-linearity
±1.5
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
-0.8
-2.5
-3.5
-2
Gain error
%
Offset error,
output referred
-5
mV
-4
0.5
1.5
11
VCC = 3.6V
Ext. VREF
mV
rms
Noise
Note:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
32.4.7 Analog Comparator Characteristics
Table 32-97. Analog Comparator Characteristics
Symbol
Voff
Parameter
Condition
Min.
Typ.
<±10
<1
Max.
Units
mV
nA
Input offset voltage
Input leakage current
Input voltage range
AC startup time
Ilk
-0.1
AVCC
V
100
0
µs
Vhys1
Hysteresis, none
mV
mode = High Speed (HS)
mode = Low Power (LP)
mode = HS
13
30
30
60
Vhys2
Hysteresis, small
Hysteresis, large
mV
mV
Vhys3
mode = LP
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
131
Symbol
Parameter
Condition
VCC = 3.0V, T= 85°C
Min.
Typ.
30
Max.
Units
ns
mode = HS
90
tdelay
Propagation delay
64-Level voltage scaler
30
Integral non-linearity (INL)
0.3
0.5
lsb
32.4.8 Bandgap and Internal 1.0V Reference Characteristics
Table 32-98. Bandgap and Internal 1.0V Reference Characteristics
Symbol Parameter
Condition
As reference for ADC
Min.
Typ.
Max.
Units
1 ClkPER + 2.5µs
Startup time
µs
As input voltage to ADC and AC
1.5
1.1
Bandgap voltage
V
INT1V
Internal 1.00V reference
T= 85°C, after calibration
0.99
1.0
1.01
Variation over voltage and temperature
Relative to T= 85°C, VCC = 3.0V
±1.5
%
32.4.9 Brownout Detection Characteristics
Table 32-99. Brownout Detection Characteristics
Symbol Parameter
BOD level 0 falling VCC
BOD level 1 falling VCC
BOD level 2 falling VCC
Condition
Min.
Typ.
1.62
1.8
Max.
Units
1.60
1.72
2.0
BOD level 3 falling VCC
VBOT
2.2
V
BOD level 4 falling VCC
2.4
BOD level 5 falling VCC
BOD level 6 falling VCC
BOD level 7 falling VCC
2.6
2.8
3.0
Continuous mode
Sampled mode
0.4
tBOD
Detection time
Hysteresis
µs
%
1000
1.2
VHYST
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
132
32.4.10 External Reset Characteristics
Table 32-100.External Reset Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
tEXT
Minimum reset pulse width
1000
95
ns
VCC = 2.7 - 3.6V
0.60*VCC
0.60*VCC
Reset threshold voltage (VIH)
VCC = 1.6 - 2.7V
VCC = 2.7 - 3.6V
VCC = 1.6 - 2.7V
0.50*VCC
0.40*VCC
0.50*VCC
VRST
V
Reset threshold voltage (VIL)
Reset pin pull-up resistor
RRST
25
k
32.4.11 Power-on Reset Characteristics
Table 32-101.Power-on Reset Characteristics
Symbol Parameter
Condition
Min.
0.4
Typ.
1.0
Max.
Units
VCC falls faster than 1V/ms
VCC falls at 1V/ms or slower
(1)
VPOT-
POR threshold voltage falling VCC
POR threshold voltage rising VCC
0.8
1.0
V
VPOT+
1.3
1.59
Note:
1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+
.
32.4.12 Flash and EEPROM Memory Characteristics
Table 32-102.Endurance and Data Retention
Symbol Parameter
Condition
Min.
10K
10K
2K
Typ.
Max.
Units
25°C
85°C
105°C
25°C
85°C
105°C
25°C
85°C
105°C
25°C
85°C
105°C
Write/Erase cycles
Cycle
Flash
100
25
Data retention
Year
Cycle
Year
10
100K
100K
30K
100
25
Write/Erase cycles
Data retention
EEPROM
10
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
133
Table 32-103.Programming Time
Symbol Parameter
Chip erase
Condition
128KB Flash, EEPROM(2) and SRAM erase
Section erase
Min.
Typ.(1)
Max.
Units
75
6
ms
Application erase
Page erase
4
Flash
Page write
4
Atomic Page Erase and write
Page erase
8
4
EEPROM
Page write
4
Atomic Page erase and write
8
Notes:
1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
32.4.13 Clock and Oscillator Characteristics
32.4.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 32-104. 32.768kHz Internal Oscillator Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Frequency
32.768
kHz
Factory calibration accuracy
User calibration accuracy
T = 85C, VCC = 3.0V
-0.5
-0.5
0.5
0.5
%
32.4.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 32-105. 2MHz Internal Oscillator Characteristics
Symbol Parameter
Frequency range
Condition
Min.
Typ.
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
1.8
2.2
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration stepsize
2.0
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.21
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
134
32.4.13.3 Calibrated and Tunable 32MHz Internal Oscillator Characteristics
Table 32-106. 32MHz Internal Oscillator Characteristics
Symbol Parameter
Frequency range
Condition
Min.
Typ.
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
30
55
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration step size
32
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.22
32.4.13.4 32kHz Internal ULP Oscillator Characteristics
Table 32-107. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Factory calibrated frequency
32
kHz
Factory calibration accuracy
Accuracy
T = 85C, VCC= 3.0V
-12
-30
12
30
%
32.4.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 32-108. Internal PLL Characteristics
Symbol Parameter
Condition
Min.
0.4
20
Typ.
Max.
64
Units
fIN
Input frequency
Output frequency must be within fOUT
VCC= 1.6 - 1.8V
48
MHz
fOUT
Output frequency(1)
VCC= 2.7 - 3.6V
20
128
Start-up time
Re-lock time
25
25
µs
Note:
1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
135
32.4.13.6 External Clock Characteristics
Figure 32-24.External Clock Drive Waveform
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 32-109. External Clock Used as System Clock without Prescaling
Symbol Parameter Condition
Clock frequency(1)
Min.
0
Typ.
Max.
12
Units
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
1/tCK
MHz
0
32
83.3
31.5
30.0
12.5
30.0
12.5
tCK
Clock period
tCH
Clock high time
tCL
Clock low time
ns
10
3
tCR
Rise time (for maximum frequency)
10
3
tCF
Fall time (for maximum frequency)
tCK
Change in period from one clock cycle to the next
10
%
Note:
1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
136
Table 32-110. External Clock with Prescaler(1) for System Clock
Symbol Parameter
Condition
Min.
0
Typ.
Max.
90
Units
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
1/tCK
Clock frequency(2)
Clock period
MHz
0
142
11
tCK
7
4.5
2.4
4.5
2.4
tCH
Clock high time
Clock low time
ns
tCL
tCR
tCF
Rise time (for maximum frequency)
1.5
1.5
10
Fall time (for maximum frequency)
tCK
Change in period from one clock cycle to the next
%
Notes:
1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
32.4.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 32-111. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter
Condition
Min.
Typ.
<10
<1
Max.
Units
FRQRANGE=0
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
Cycle to cycle jitter
FRQRANGE=1, 2, or 3
<1
ns
FRQRANGE=0
<6
Long term jitter
Frequency error
FRQRANGE=1, 2, or 3
<0.5
<0.5
<0.1
<0.05
<0.005
<0.005
40
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
%
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
42
Duty cycle
45
48
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
137
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
0.4MHz resonator,
CL=100pF
2.4k
XOSCPWR=0,
FRQRANGE=0
1MHz crystal, CL=20pF
2MHz crystal, CL=20pF
2MHz crystal
8.7k
2.1k
4.2k
250
195
360
285
155
365
200
105
435
235
125
495
270
145
305
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
8MHz crystal
9MHz crystal
8MHz crystal
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
9MHz crystal
12MHz crystal
9MHz crystal
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
RQ
Negative impedance(1)
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
12MHz crystal
16MHz crystal
12MHz crystal
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
16MHz crystal
12MHz crystal
16MHz crystal
160
380
205
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
ESR
SF = safety factor
min(RQ)/SF
k
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF
1.0
2.6
0.8
1.0
1.4
XOSCPWR=0,
FRQRANGE=1
2MHz crystal, CL=20pF
8MHz crystal, CL=20pF
12MHz crystal, CL=20pF
16MHz crystal, CL=20pF
XOSCPWR=0,
FRQRANGE=2
Start-up time
ms
XOSCPWR=0,
FRQRANGE=3
XOSCPWR=1,
FRQRANGE=3
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
138
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Parasitic capacitance
XTAL1 pin
CXTAL1
5.9
Parasitic capacitance
XTAL2 pin
pF
CXTAL2
CLOAD
8.3
3.5
Parasitic capacitance load
Note:
1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
32.4.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 32-112. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Symbol Parameter
Condition
Crystal load capacitance 6.5pF
Crystal load capacitance 9.0pF
Normal mode
Min.
Typ.
Max.
60
Units
Recommended crystal equivalent
ESR/R1
CTOSC
k
series resistance (ESR)
35
4.7
5.2
Parasitic capacitance
pF
Low power mode
Capacitance load matched to
crystal specification
Recommended safety factor
3
Note:
1. See Figure 32-25 for definition.
Figure 32-25.TOSC Input Capacitance
CL1
CL2
Device internal
External
TOSC1
TOSC2
32.768KHz crystal
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
139
32.4.14 SPI Characteristics
Figure 32-26.SPI Timing Requirements in Master Mode
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
tMIH
MSB
tSCK
MISO
(Data Input)
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Figure 32-27.SPI Timing Requirements in Slave Mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
tSIH
MSB
tSSCK
LSB
MOSI
(Data Input)
tSOSSS
tSOS
tSOSSH
MISO
(Data Output)
MSB
LSB
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
140
Table 32-113. SPI Timing Characteristics and Requirements
Symbol Parameter Condition
Min.
Typ.
Max.
Units
(See Table 17-4 in
XMEGA D Manual)
tSCK
SCK period
Master
tSCKW
tSCKR
tSCKF
tMIS
SCK high/low width
SCK rise time
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
0.5*SCK
2.7
2.7
SCK fall time
MISO setup to SCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Slave SCK period
SCK high/low width
SCK rise time
10
tMIH
10
tMOS
tMOH
tSSCK
tSSCKW
tSSCKR
tSSCKF
tSIS
0.5*SCK
1
4*t ClkPER
2*t ClkPER
ns
1600
1600
SCK fall time
MOSI setup to SCK
MOSI hold after SCK
SS setup to SCK
SS hold after SCK
MISO setup SCK
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
3
t ClkPER
21
tSIH
tSSS
tSSH
20
tSOS
8.0
13.0
11.0
8.0
tSOH
tSOSS
tSOSH
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
141
32.4.15 Two-Wire Interface Characteristics
Table 32-114 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA
Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-
28.
Figure 32-28.Two-wire Interface Bus Timing
tof
tHIGH
tLOW
tr
SCL
SDA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
tHD;STA
tBUF
Table 32-114. Two-wire Interface Characteristics
Symbol Parameter
Condition
Min.
0.7*VCC
-0.5
Typ.
Max.
Units
VIH
VIL
Input high voltage
VCC+0.5
0.3*VCC
Input low voltage
V
(1)
Vhys
Hysteresis of Schmitt Trigger Inputs
Output low voltage
0.05*VCC
0
VOL
3mA, sink current
0.4
300
250
50
(1)(2)
tr
tof
Rise time for both SDA and SCL
Output fall time from VIHmin to VILmax
Spikes suppressed by input filter
Input current for each I/O pin
Capacitance for each I/O pin
SCL clock frequency
20+0.1Cb
20+0.1Cb
0
10pF < Cb < 400pF(2)
0.1VCC < VI < 0.9VCC
ns
(1)(2)
tSP
II
-10
10
µA
pF
CI
10
fSCL
fPER(3)>max(10fSCL, 250kHz)
0
400
kHz
fSCL 100kHz
100ns
Cb
--------------
VCC – 0.4V
---------------------------
3mA
RP
Value of pull-up resistor
300ns
fSCL > 100kHz
--------------
Cb
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
142
Symbol Parameter
Condition
fSCL 100kHz
Min.
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
0
Typ.
Max.
Units
tHD;STA
Hold time (repeated) START condition
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
tLOW
Low period of SCL clock
High period of SCL clock
µs
tHIGH
Set-up time for a repeated START
condition
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
3.45
0.9
Data hold time
µs
ns
µs
µs
0
250
100
4.0
0.6
4.7
1.3
Data setup time
Setup time for STOP condition
Bus free time between a STOP and
START condition
Notes:
1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
143
33. Typical Characteristics
33.1 ATxmega16D4
33.1.1 Current Consumption
33.1.1.1 Active Mode Supply Current
Figure 33-1. Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C.
700
600
500
400
300
200
100
0
3.3V
3.0V
2.7V
2.2V
1.8V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency [MHz]
Figure 33-2. Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C.
12
10
8
3.3V
3.0V
2.7V
6
2.2V
4
1.8V
2
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
144
Figure 33-3. Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
180
160
140
120
100
80
-40°C
25°C
85°C
105°C
60
40
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-4. Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock.
600
550
500
450
400
350
300
250
200
150
100
-40°C
25°C
85°C
105°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
145
Figure 33-5. Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
1350
1200
1050
900
-40°C
25°C
85°C
105°C
750
600
450
300
150
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-6. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
-40°C
25 °C
85°C
105°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
146
Figure 33-7. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
12.0
11.5
11.0
10.5
10.0
9.5
-40 °C
25°C
85°C
105°C
9.0
8.5
8.0
7.5
7.0
6.5
6.0
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
33.1.1.2 Idle Mode Supply Current
Figure 33-8. Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
140
120
100
80
3.3V
3.0V
2.7V
2.2V
1.8V
60
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency [MHz]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
147
Figure 33-9. Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
3.3V
3.0V
2.7V
2.2V
1.0
1.8V
0.5
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
Figure 33-10. Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
35.50
34.75
34.00
33.25
32.50
31.75
31.00
30.25
29.50
28.75
28.00
27.25
26.50
25.75
25.00
105°C
85°C
-40°C
25°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
148
Figure 33-11. Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
130
120
110
100
90
105°C
85°C
25°C
-40°C
80
70
60
50
40
30
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-12. Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
330
310
290
270
250
230
210
190
170
150
130
110
-40°C
25°C
85 °C
105 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
149
Figure 33-13. Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
1600
1500
1400
1300
1200
1100
1000
900
40 °C
-
25 °C
85°C
105°C
800
700
600
500
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-14. Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
-40°C
25°C
85°C
105°C
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
150
33.1.1.3 Power-down Mode Supply Current
Figure 33-15. Power-down Mode Supply Current vs. VCC
All functions disabled
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
105°C
85°C
25°C
-40°C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-16. Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
105°C
85°C
25°C
-40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
151
Figure 33-17. Power-down Mode Supply Current vs. Temperature
Watchdog and sampled BOD enabled and running from internal ULP oscillator
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
3.6V
3.0V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
33.1.1.4 Power-save Mode Supply Current
Figure 33-18. Power-save Mode Supply Current vs.VCC
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC
0.9
Normal mode
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Low-power mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
152
33.1.1.5 Standby Mode Supply Current
Figure 33-19. Standby Supply Current vs. VCC
Standby, fSYS = 1MHz
12.1
10.9
9.7
8.5
7.3
6.1
4.9
3.7
2.5
105°C
85°C
25°C
-40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-20. Standby Supply Current vs. VCC
25°C, running from different crystal oscillators
480
16MHz
12MHz
440
400
360
320
280
240
200
160
8MHz
2MHz
0.454MHz
3.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
153
33.1.2 I/O Pin Characteristics
33.1.2.1 Pull-up
Figure 33-21. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V
72
64
56
48
40
32
24
16
8
-40°C
25°C
85°C
105°C
0
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
VPIN [V]
Figure 33-22. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V
120
108
96
84
72
60
48
36
24
12
0
-40°C
25°C
85°C
105°C
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
VPIN [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
154
Figure 33-23. I/O pin pull-up Resistor Current vs. Input Voltage
VCC = 3.3V
135
120
105
90
75
60
45
30
15
0
-40°C
25°C
85°C
105°C
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
VPIN [V]
33.1.2.2 Output Voltage vs. Sink/Source Current
Figure 33-24. I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
25°C
85°C 105°C
-3.5
-40°C
0.2
0
-5
-4.5
-4
-3
-2.5
-2
-1.5
-1
-0.5
0
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
155
Figure 33-25. I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
3.15
2.80
2.45
2.10
1.75
1.40
1.05
-40°C
25°C
85°C
105°C
-10
0.70
0.35
0
-16
-14
-12
-8
-6
-4
-2
0
IPIN [mA]
Figure 33-26. I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
3.5
3.15
2.8
2.45
2.1
1.75
1.4
1.05
0.7
-40°C
25°C
85°C
105°C
-12
0.35
0
-20
-18
-16
-14
-10
-8
-6
-4
-2
0
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
156
Figure 33-27. I/O Pin Output Voltage vs. Source Current
3.6
3.3
3
3.6 V
3.3 V
2.7 V
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
2.2 V
1.8 V
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
IPIN [mA]
Figure 33-28. I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
105°C
25°C
-40°C
85°C
0
1
2
3
4
5
6
7
8
9
10
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
157
Figure 33-29. I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
105°C
85°C
25°C
-40°C
0
2
4
6
8
10
12
14
16
IPIN [mA]
Figure 33-30. I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
105°C
85°C
25°C
-40°C
0
2
4
6
8
10
12
14
16
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
158
Figure 33-31. I/O Pin Output Voltage vs. Sink Current
1.5
1.6V
1.8V
2.7V
1.35
1.2
3.0V
3.3V
3.6V
1.05
0.9
0.75
0.6
0.45
0.3
0.15
0
0
2
4
6
8
10
IPIN [mA]
12
14
16
18
20
33.1.2.3 Thresholds and Hysteresis
Figure 33-32. I/O Pin Input Threshold Voltage vs. VCC
T = 25C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VIH
VIL
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
159
Figure 33-33. I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
-40°C
25°C
85 °C
105 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-34. I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
1.75
1.60
1.45
1.30
1.15
1.00
0.85
0.70
0.55
0.40
-40°C
25°C
85 °C
105 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
160
Figure 33-35. I/O Pin Input Hysteresis vs. VCC
0.42
0.39
0.36
0.33
0.3
-40°C
25°C
0.27
0.24
0.21
0.18
0.15
85°C
105°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
33.1.3 ADC Characteristics
Figure 33-36. INL Error vs. External VREF
T = 25C, VCC = 3.6V, external reference
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Single-ended unsigned mode
Differential mode
Single-ended signed mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
161
Figure 33-37. INL Error vs. Sample Rate
T = 25C, VCC = 3.6V, VREF = 3.0V external
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
Single-ended unsigned mode
Differential mode
Single-ended signed mode
50
100
150
200
250
300
ADC sample rate [ksps]
Figure 33-38. INL Error vs. Input Code
1.25
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
-1.25
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
162
Figure 33-39. DNL Error vs. External VREF
T = 25C, VCC = 3.6V, external reference
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
Single-ended unsigned mode
Differential mode
Single-ended signed mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
Figure 33-40. DNL Error vs. Sample Rate
T = 25C, VCC = 3.6V, VREF = 3.0V external.
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
Single-ended unsigned mode
Differential mode
Single-ended signed mode
50
100
150
200
250
300
ADC sample rate [ksps]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
163
Figure 33-41. DNL Error vs. Input Code
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
Figure 33-42. Gain Error vs. VREF
T = 25C, VCC = 3.6V, ADC sample rate = 200ksps
-5
-6
-7
Differential mode
-8
-9
mode
Single-ended signed
-10
-11
-12
-13
-14
-15
Single-ended unsigned mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
164
Figure 33-43. Gain Error vs. VCC
T = 25C, VREF = external 1.0V, ADC sample rate = 200ksps
-2
-3
-4
-5
-6
-7
-8
-9
Differential mode
Single-ended signed
mode
Single-ended unsigned mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V
CC [V]
Figure 33-44. Offset Error vs. VREF
T = 25C, VCC = 3.6V, ADC sample rate = 200ksps
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
Differential mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
165
Figure 33-45. Gain Error vs. Temperature
VCC = 3.0V, VREF = external 2.0V
0
-2
Single-ended signed mode
Differentialmode
-4
-6
-8
-10
mode
Single-ended unsigned
-12
-14
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 33-46. Offset Error vs. VCC
T = 25C, VREF = external 1.0V, ADC sample rate = 200ksps
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
Differential mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
166
33.1.4 Analog Comparator Characteristics
Figure 33-47. Analog Comparator Hysteresis vs. VCC
High speed, small hysteresis
14
13
12
11
10
9
105°C
85°C
25°C
8
7
-40°C
6
5
4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-48. Analog Comparator Hysteresis vs. VCC
High speed, large hysteresis
32
30
28
26
24
22
20
18
16
14
105°C
85°C
25°C
-40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
167
Figure 33-49. Analog Comparator Hysteresis vs. VCC
Low power, small hysteresis
30
28
26
24
22
20
18
105°C
85°C
25°C
-40°C
16
14
12
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-50. Analog Comparator Hysteresis vs. VCC
Low power, large hysteresis
68
64
60
56
52
48
44
40
36
32
105°C
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
168
Figure 33-51. Analog Comparator Current Source vs. Calibration Value
T = 25C
8
7.25
6.5
5.75
5
3.6V
3.0V
4.25
3.5
2.75
2
2.2V
1.8V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CALIBA [3..0]
Figure 33-52. Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
7.0
6.6
6.2
5.8
5.4
5.0
4.6
4.2
3.8
3.4
3.0
-40°C
25°C
85°C
105°C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CALIBA [3..0]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
169
Figure 33-53. Voltage Scaler INL vs. SCALEFAC
T = 25C, VCC = 3.0V
0.050
0.025
0
-0.025
-0.050
-0.075
-0.100
-0.125
-0.150
25°C
0
10
20
30
40
SCALEFAC
50
60
70
33.1.5 Internal 1.0V Reference Characteristics
Figure 33-54. ADC Internal 1.0V Reference vs. Temperature
1.0088
1.008
1.0072
1.0064
1.0056
1.0048
1.004
1.0032
1.0024
1.0016
1.0008
1
0.9992
0.9984
0.9976
0.9968
1.8V
2.2V
2.7V
3.0V
3.6V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
170
33.1.6 BOD Characteristics
Figure 33-55. BOD Thresholds vs. Temperature
BOD level = 1.6V
1.574
1.57
Rising Vcc
Falling Vcc
1.566
1.562
1.558
1.554
1.55
1.546
1.542
1.538
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 33-56. BOD Thresholds vs. Temperature
BOD level = 3.0V
2.992
2.984
2.976
2.968
2.96
Rising Vcc
2.952
2.944
2.936
2.928
2.92
Falling Vcc
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
171
33.1.7 External Reset Characteristics
Figure 33-57. Minimum Reset Pin Pulse Width vs. VCC
145
140
135
130
125
120
115
110
105
100
95
105°C
85°C
25°C
90
-40°C
85
80
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-58. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
80
72
64
56
48
40
32
24
16
8
-40°C
25°C
85°C
105°C
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VRESET [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
172
Figure 33-59. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
135
120
105
90
75
60
45
30
15
0
-40°C
25°C
85°C
105°C
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
V
RESET [V]
Figure 33-60. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
150
135
120
105
90
75
60
45
30
-40°C
25°C
15
85°C
105°C
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
V
RESET [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
173
Figure 33-61. Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
-40°C
25°C
2.10
2.00
1.90
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
85°C
105°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-62. Reset Pin Input Threshold Voltage vs. VCC
VIL - Reset pin read as “0”
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
-40°C
25°C
85 °C
105 °C
0.9
0.8
0.7
0.6
0.5
0.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
174
33.1.8 Power-on Reset Characteristics
Figure 33-63. Power-on Reset Current Consumption vs. VCC
BOD level = 3.0V, enabled in continuous mode
700
600
500
400
300
200
100
0
-40°C
25°C
85°C
105°C
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
Figure 33-64. Power-on Reset Current Consumption vs. VCC
BOD level = 3.0V, enabled in sampled mode
650
585
520
455
390
325
260
195
130
65
-40°C
25°C
85°C
105°C
0
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
175
33.1.9 Oscillator Characteristics
33.1.9.1 Ultra Low-Power Internal Oscillator
Figure 33-65. Ultra Low-Power Internal Oscillator Frequency vs. Temperature
35.4
35.1
34.8
34.5
34.2
33.9
33.6
33.3
33.0
32.7
32.4
32.1
31.8
31.5
31.2
30.9
3.6V
3.3V
3.0V
2.7V
2.0V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95 105
Temperature [°C]
33.1.9.2 32.768kHz Internal Oscillator
Figure 33-66. 32.768kHz Internal Oscillator Frequency vs. Temperature
32.9
32.85
32.8
3.6V
3.3V
3.0V
2.7V
2.2V
32.75
32.7
1.8V
32.65
32.6
32.55
32.5
32.45
32.4
32.35
32.3
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
176
Figure 33-67. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
55
51
47
43
39
35
31
27
23
19
15
3.0V
0
16 32
48
64 80
96 112 128 144 160 176 192 208 224 240 256
RC32KCAL [7..0]
33.1.9.3 2MHz Internal Oscillator
Figure 33-68. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
2.16
2.14
2.12
2.10
2.08
2.06
2.04
2.02
2.00
1.98
1.96
1.94
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
177
Figure 33-69. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
2.012
2.008
2.004
2.00
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
1.996
1.992
1.988
1.984
1.98
1.976
1.972
1.968
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 33-70. 2MHz Internal Oscillator CALA Calibration Step Size
VCC = 3V
0.29
0.28
0.27
0.26
0.25
0.24
0.23
0.22
0.21
0.20
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
-40°C
25°C
85°C
105°C
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
178
33.1.9.4 32MHz Internal Oscillator
Figure 33-71. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
36.45
36
35.55
35.1
34.65
34.2
33.75
33.3
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
32.85
32.4
31.95
31.5
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 33-72. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
32.15
32.1
3.6V
3.3V
3.0V
32.05
32
2.7V
2.2V
1.8V
31.95
31.9
31.85
31.8
31.75
31.7
31.65
31.6
31.55
31.5
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
179
Figure 33-73. 32MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
0.18
0.16
0.14
0.12
-40°C
105°C
85°C
25°C
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
33.1.9.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 33-74. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
55.3
54.6
53.9
53.2
52.5
51.8
51.1
50.4
49.7
49.0
48.3
47.6
46.9
46.2
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
180
Figure 33-75. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
32.15
32.1
3.6V
3.3V
3.0V
32.05
32
2.7V
2.2V
1.8V
31.95
31.9
31.85
31.8
31.75
31.7
31.65
31.6
31.55
31.5
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 33-76. 48MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V
0.29
0.27
0.25
0.23
0.21
0.19
0.17
0.15
0.13
0.11
0.09
-40°C
25°C
105°C
85°C
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
181
33.1.10 Two-Wire Interface Characteristics
Figure 33-77. SDA Hold Time vs. Temperature
500
450
400
350
300
250
200
150
100
50
3
2
1
0
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 33-78. SDA Hold Time vs. Supply Voltage
500
450
400
350
300
250
200
150
100
50
3
2
1
0
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
182
33.1.11 PDI Characteristics
Figure 33-79. Maximum PDI Frequency vs. VCC
22
21
20
19
18
17
16
15
14
13
12
11
10
-40°C
25°C
85°C
105°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
183
33.2 ATxmega32D4
33.2.1 Current Consumption
33.2.1.1 Active Mode Supply Current
Figure 33-80. Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
600
550
500
450
400
350
300
250
200
150
100
50
3.6V
3.0V
2.7V
2.2V
1.8V
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 33-81. Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
11
10
9
3.6V
8
3.0V
2.7V
7
6
5
4
2.2V
3
2
1.8V
1
0
0
2
4
6
8
10 12
14
16 18
20 22
24 26
28 30
32
Frequency [MHz]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
184
Figure 33-82. Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
180
160
140
120
100
80
-40°C
25°C
85°C
105°C
60
40
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-83. Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock
600
550
500
450
400
350
300
250
200
150
100
-40°C
25°C
85°C
105°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
185
Figure 33-84. Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
1350
1200
1050
900
-40°C
25°C
85°C
105°C
750
600
450
300
150
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-85. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
-40°C
25 °C
85°C
105°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
186
Figure 33-86. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
12.0
11.5
11.0
10.5
10.0
9.5
-40 °C
25°C
85°C
105°C
9.0
8.5
8.0
7.5
7.0
6.5
6.0
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
33.2.1.2 Idle Mode Supply Current
Figure 33-87. Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
120
105
90
75
60
45
30
15
0
3.6V
3.0V
2.7V
2.2V
1.8V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
187
Figure 33-88. Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
3.6V
3.0V
2.7V
2.2V
1.8V
0.4
0
0
2
4
6
8
10 12
14
16 18
20 22
24 26
28 30
32
Frenquecy [MHz]
Figure 33-89. Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
35.50
34.75
34.00
33.25
32.50
31.75
31.00
30.25
29.50
28.75
28.00
27.25
26.50
25.75
25.00
105°C
85°C
-40°C
25°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
188
Figure 33-90. Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
130
120
110
100
90
105°C
85°C
25°C
-40°C
80
70
60
50
40
30
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-91. Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
330
310
290
270
250
230
210
190
170
150
130
110
-40°C
25°C
85 °C
105 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
189
Figure 33-92. Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
1600
1500
1400
1300
1200
1100
1000
900
40 °C
-
25 °C
85°C
105°C
800
700
600
500
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-93. Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
-40°C
25°C
85°C
105°C
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
190
33.2.1.3 Power-down Mode Supply Current
Figure 33-94. Power-down Mode Supply Current vs. VCC
All functions disabled
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
105°C
85°C
25°C
-40°C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-95. Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
105°C
85°C
25°C
-40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
191
Figure 33-96. Power-down Mode Supply Current vs. Temperature
Watchdog and sampled BOD enabled and running from internal ULP oscillator
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
3.6V
3.0V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
33.2.1.4 Power-save Mode Supply Current
Figure 33-97. Power-save Mode Supply Current vs.VCC
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC
0.9
Normal mode
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Low-power mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
192
33.2.1.5 Standby Mode Supply Current
Figure 33-98. Standby Supply Current vs. VCC
Standby, fSYS = 1MHz
12.1
10.9
9.7
8.5
7.3
6.1
4.9
3.7
2.5
105°C
85°C
25°C
-40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-99. Standby Supply Current vs. VCC
25°C, running from different crystal oscillators
480
440
400
360
320
280
240
200
160
16MHz
12MHz
8MHz
2MHz
0.454MHz
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
193
33.2.2 I/O Pin Characteristics
33.2.2.1 Pull-up
Figure 33-100. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V
72
64
56
48
40
32
24
16
8
-40°C
25°C
85°C
105°C
0
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
VPIN [V]
Figure 33-101. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V
120
108
96
84
72
60
48
36
24
12
0
-40°C
25°C
85°C
105°C
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
VPIN [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
194
Figure 33-102. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.3V
135
120
105
90
75
60
45
30
15
0
-40°C
25°C
85°C
105°C
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
VPIN [V]
33.2.2.2 Output Voltage vs. Sink/Source Current
Figure 33-103. I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
25°C
85°C 105°C
-3.5
-40°C
0.2
0
-5
-4.5
-4
-3
-2.5
-2
-1.5
-1
-0.5
0
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
195
Figure 33-104. I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
3.15
2.80
2.45
2.10
1.75
1.40
1.05
-40°C
25°C
85°C
105°C
-10
0.70
0.35
0
-16
-14
-12
-8
-6
-4
-2
0
IPIN [mA]
Figure 33-105. I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
3.5
3.15
2.8
2.45
2.1
1.75
1.4
1.05
0.7
-40°C
25°C
85°C
105°C
-12
0.35
0
-20
-18
-16
-14
-10
-8
-6
-4
-2
0
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
196
Figure 33-106. I/O Pin Output Voltage vs. Source Current
3.6
3.3
3
3.6 V
3.3 V
2.7 V
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
2.2 V
1.8 V
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
IPIN [mA]
Figure 33-107. I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
105°C
25°C
-40°C
85°C
0
1
2
3
4
5
6
7
8
9
10
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
197
Figure 33-108. I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
105°C
85°C
25°C
-40°C
0
2
4
6
8
10
12
14
16
IPIN [mA]
Figure 33-109. I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
105°C
85°C
25°C
-40°C
0
2
4
6
8
10
12
14
16
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
198
Figure 33-110. I/O Pin Output Voltage vs. Sink Current
1.5
1.6V
1.8V
2.7V
1.35
1.2
3.0V
3.3V
3.6V
1.05
0.9
0.75
0.6
0.45
0.3
0.15
0
0
2
4
6
8
10
IPIN [mA]
12
14
16
18
20
33.2.2.3 Thresholds and Hysteresis
Figure 33-111. I/O Pin Input Threshold Voltage vs. VCC
T = 25C
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
VIH
VIL
0.9
0.8
0.7
0.6
0.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
199
Figure 33-112. I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
-40°C
25°C
85 °C
105 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-113. I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
1.75
1.60
1.45
1.30
1.15
1.00
0.85
0.70
0.55
0.40
-40°C
25°C
85 °C
105 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
200
Figure 33-114. I/O Pin Input Hysteresis vs. VCC
0.42
0.39
0.36
0.33
0.3
-40°C
25°C
0.27
0.24
0.21
0.18
0.15
85°C
105°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
33.2.3 ADC Characteristics
Figure 33-115. INL Error vs. External VREF
T = 25C, VCC = 3.6V, external reference
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Single-ended unsigned mode
Differential mode
Single-ended signed mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
201
Figure 33-116. INL Error vs. Sample Rate
T = 25C, VCC = 3.6V, VREF = 3.0V external
0.70
0.65
0.60
0.55
Single-ended unsigned mode
0.50
0.45
0.40
0.35
0.30
0.25
Differential mode
Single-ended signed mode
50
100
150
200
250
300
ADC sample rate [ksps]
Figure 33-117. INL Error vs. Input Code
1.25
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
-1.25
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
202
Figure 33-118. DNL Error vs. External VREF
T = 25C, VCC = 3.6V, external reference
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
Single-ended unsigned mode
Differential mode
Single-ended signed mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
Figure 33-119. DNL Error vs. Sample Rate
T = 25C, VCC = 3.6V, VREF = 3.0V external
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
Single-ended unsigned mode
Differential mode
Single-ended signed mode
50
100
150
200
250
300
ADC sample rate [ksps]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
203
Figure 33-120. DNL Error vs. Input code
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
Figure 33-121. Gain Error vs. VREF
T = 25C, VCC = 3.6V, ADC sample rate = 200ksps
-5
-6
-7
Differential mode
-8
-9
mode
Single-ended signed
-10
-11
-12
-13
-14
-15
Single-ended unsigned mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
204
Figure 33-122. Gain Error vs. VCC
T = 25C, VREF = external 1.0V, ADC sample rate = 200ksps
-2
-3
-4
-5
-6
-7
-8
-9
Differential mode
Single-ended signed
mode
Single-ended unsigned mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V
CC [V]
Figure 33-123. Gain Error vs. Temperature
VCC = 3.0V, VREF = external 2.0V
0
-2
Single-ended signed mode
Differentialmode
-4
-6
-8
-10
mode
Single-ended unsigned
-12
-14
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
205
Figure 33-124. Offset Error vs. VREF
T = 25C, VCC = 3.6V, ADC sample rate = 200ksps
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
Differential mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
Figure 33-125. Offset Error vs. VCC
T = 25C, VREF = external 1.0V, ADC sample rate = 200ksps
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
Differential mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V
CC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
206
33.2.4 Analog Comparator Characteristics
Figure 33-126. Analog Comparator Hysteresis vs. VCC
High speed, small hysteresis
14
13
12
11
10
9
105°C
85°C
25°C
8
7
-40°C
6
5
4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-127. Analog Comparator Hysteresis vs. VCC
High speed, large hysteresis
32
30
28
26
24
22
20
18
16
14
105°C
85°C
25°C
-40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
207
Figure 33-128. Analog Comparator Hysteresis vs. VCC
Low power, small hysteresis
30
28
26
24
22
20
18
105°C
85°C
25°C
-40°C
16
14
12
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-129. Analog Comparator Hysteresis vs. VCC
Low power, large hysteresis
68
64
60
56
52
48
44
40
36
32
105°C
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
208
Figure 33-130. Analog Comparator Current Source vs. Calibration Value
T = 25C
8
7.25
6.5
5.75
5
3.6V
3.0V
4.25
3.5
2.75
2
2.2V
1.8V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CALIBA [3..0]
Figure 33-131. Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
7.0
6.6
6.2
5.8
5.4
5.0
4.6
4.2
3.8
3.4
3.0
-40°C
25°C
85°C
105°C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CALIBA [3..0]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
209
Figure 33-132. Voltage Scaler INL vs. SCALEFAC
T = 25C, VCC = 3.0V
0.050
0.025
0
-0.025
-0.050
-0.075
-0.100
-0.125
-0.150
25°C
0
10
20
30
40
SCALEFAC
50
60
70
33.2.5 Internal 1.0V reference Characteristics
Figure 33-133. ADC Internal 1.0V Reference vs. Temperature
1.0088
1.008
1.0072
1.0064
1.0056
1.0048
1.004
1.0032
1.0024
1.0016
1.0008
1
0.9992
0.9984
0.9976
0.9968
1.8V
2.2V
2.7V
3.0V
3.6V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
210
33.2.6 BOD Characteristics
Figure 33-134. BOD Thresholds vs. Temperature
BOD level = 1.6V
1.574
1.57
Rising Vcc
Falling Vcc
1.566
1.562
1.558
1.554
1.55
1.546
1.542
1.538
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 33-135. BOD thresholds vs. Temperature
BOD level = 3.0V
2.992
2.984
2.976
2.968
2.96
Rising Vcc
2.952
2.944
2.936
2.928
2.92
Falling Vcc
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
211
33.2.7 External Reset Characteristics
Figure 33-136. Minimum Reset Pin Pulse Width vs. VCC
145
140
135
130
125
120
115
110
105
100
95
105°C
85°C
25°C
90
-40°C
85
80
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-137. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
80
72
64
56
48
40
32
24
16
8
-40°C
25°C
85°C
105°C
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VRESET [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
212
Figure 33-138. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
135
120
105
90
75
60
45
30
15
0
-40°C
25°C
85°C
105°C
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
V
RESET [V]
Figure 33-139. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
150
135
120
105
90
75
60
45
30
-40°C
25°C
15
85°C
105°C
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
V
RESET [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
213
Figure 33-140. Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
-40°C
25°C
2.10
2.00
1.90
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
85°C
105°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-141. Reset Pin Input Threshold Voltage vs. VCC
VIL - Reset pin read as “0”
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
-40°C
25°C
85 °C
105 °C
0.9
0.8
0.7
0.6
0.5
0.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
214
33.2.8 Power-on Reset Characteristics
Figure 33-142. Power-on Reset Current Consumption vs. VCC
BOD level = 3.0V, enabled in continuous mode
700
600
500
400
300
200
100
0
-40°C
25°C
85°C
105°C
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
Figure 33-143. Power-on Reset Current Consumption vs. VCC
BOD level = 3.0V, enabled in sampled mode
650
585
520
455
390
325
260
195
130
65
-40°C
25°C
85°C
105°C
0
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
215
33.2.9 Oscillator Characteristics
33.2.9.1 Ultra Low-Power Internal Oscillator
Figure 33-144. Ultra Low-Power Internal Oscillator Frequency vs. Temperature
35.4
35.1
34.8
34.5
34.2
33.9
33.6
33.3
33.0
32.7
32.4
32.1
31.8
31.5
31.2
30.9
3.6V
3.3V
3.0V
2.7V
2.0V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95 105
Temperature [°C]
33.2.9.2 32.768kHz Internal Oscillator
Figure 33-145. 32.768kHz Internal Oscillator Frequency vs. Temperature
32.9
32.85
32.8
3.6V
3.3V
3.0V
2.7V
2.2V
32.75
32.7
1.8V
32.65
32.6
32.55
32.5
32.45
32.4
32.35
32.3
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
216
Figure 33-146. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
55
51
47
43
39
35
31
27
23
19
15
3.0V
0
16 32
48
64 80
96 112 128 144 160 176 192 208 224 240 256
RC32KCAL [7..0]
33.2.9.3 2MHz Internal Oscillator
Figure 33-147. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
2.16
2.14
2.12
2.10
2.08
2.06
2.04
2.02
2.00
1.98
1.96
1.94
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
217
Figure 33-148. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
2.012
2.008
2.004
2.00
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
1.996
1.992
1.988
1.984
1.98
1.976
1.972
1.968
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 33-149. 2MHz Internal Oscillator CALA Calibration Step Size
VCC = 3V
0.29
0.28
0.27
0.26
0.25
0.24
0.23
0.22
0.21
0.20
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
-40°C
25°C
85°C
105°C
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
218
33.2.9.4 32MHz Internal Oscillator
Figure 33-150. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
36.45
36
35.55
35.1
34.65
34.2
33.75
33.3
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
32.85
32.4
31.95
31.5
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 33-151. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
32.15
32.1
3.6V
3.3V
3.0V
32.05
32
2.7V
2.2V
1.8V
31.95
31.9
31.85
31.8
31.75
31.7
31.65
31.6
31.55
31.5
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
219
Figure 33-152. 32MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
0.18
0.16
0.14
0.12
-40°C
105°C
85°C
25°C
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
33.2.9.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 33-153. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
55.3
54.6
53.9
53.2
52.5
51.8
51.1
50.4
49.7
49.0
48.3
47.6
46.9
46.2
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
220
Figure 33-154. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
32.15
32.1
3.6V
3.3V
3.0V
32.05
32
2.7V
2.2V
1.8V
31.95
31.9
31.85
31.8
31.75
31.7
31.65
31.6
31.55
31.5
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 33-155. 48MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V
0.29
0.27
0.25
0.23
0.21
0.19
0.17
0.15
0.13
0.11
0.09
-40°C
25°C
105°C
85°C
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
221
33.2.10 Two-Wire Interface Characteristics
Figure 33-156. SDA Hold Time vs. Temperature
500
450
400
350
300
250
200
150
100
50
3
2
1
0
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 33-157. SDA Hold Time vs. Supply Voltage
500
450
400
350
300
250
200
150
100
50
3
2
1
0
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
222
33.2.11 PDI Characteristics
Figure 33-158. Maximum PDI Frequency vs. VCC
22
21
20
19
18
17
16
15
14
13
12
11
10
-40°C
25°C
85°C
105°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
223
33.3 ATxmega64D4
33.3.1 Current Consumption
33.3.1.1 Active Mode Supply Current
Figure 33-159. Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
700
600
500
400
300
200
100
0
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 33-160. Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
12
10
8
3.6V
3.0V
2.7V
6
4
2.2V
2
1.8V
1.6V
0
0
4
8
12
16
Frequency [MHz]
20
24
28
32
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
224
Figure 33-161. Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
250
230
210
190
170
150
130
110
90
- 40°C
25°C
85°C
105°C
70
50
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-162. Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock
680
630
580
530
480
430
380
330
280
230
180
- 40°C
25°C
85°C
105°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
225
Figure 33-163. Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
1300
1200
1100
1000
900
- 40°C
25°C
85°C
105°C
800
700
600
500
400
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-164. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
4.8
4.4
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
- 40°C
25°C
85°C
105°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
226
Figure 33-165. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
12.0
11.5
11.0
10.5
10.0
9.5
- 40°C
25°C
85°C
105°C
9.0
8.5
8.0
7.5
7.0
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
33.3.1.2 Idle Mode Supply Current
Figure 33-166. Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
150
135
120
105
90
3.6 V
3.0 V
2.7 V
75
2.2 V
60
1.8 V
1.6 V
45
30
15
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
227
Figure 33-167. Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
3.6 V
3.0 V
2.7 V
2.2 V
1.0
1.8 V
0.5
0.0
1.6 V
0
4
8
12
16
20
24
28
32
Figure 33-168. Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
34.75
34.00
33.25
32.50
31.75
31.00
30.25
29.50
28.75
28.00
105°C
- 40°C
85°C
25°C
1.6
1.8
2.0
2.2
2.4
2.6
VCC [V]
2.8
3.0
3.2
3.4
3.6
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
228
Figure 33-169. Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
153
141
129
117
105
93
105°C
85°C
25°C
- 40°C
81
69
57
45
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-170. Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
400
375
350
325
300
275
250
225
200
175
150
- 40°C
25°C
85°C
105°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
229
Figure 33-171. Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
1850
1700
1550
1400
1250
1100
950
- 40°C
25°C
85°C
105°C
800
650
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-172. Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
5.1
4.9
4.7
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
- 40°C
25°C
85°C
105°C
2.7
2.8
2.9
3.0
3.1
VCC [V]
3.2
3.3
3.4
3.5
3.6
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
230
33.3.1.3 Power-down Mode Supply Current
Figure 33-173. Power-down Mode Supply Current vs. Temperature
All functions disabled
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0.0
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 33-174. Power-down Mode Supply Current vs. VCC
All functions disabled
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0.0
105°C
85°C
25°C
- 40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
231
Figure 33-175. Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
4.10
3.80
3.50
3.20
2.90
2.60
2.30
2.00
1.70
1.40
1.10
105°C
85°C
25°C
- 40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
33.3.1.4 Power-save Mode Supply Current
Figure 33-176. Power-save Mode Supply Current vs.VCC
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC
0.9
Normal mode
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Low-power mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
232
33.3.1.5 Standby Mode Supply Current
Figure 33-177. Standby Supply Current vs. VCC
Standby, fSYS = 1MHz
12.5
11.5
10.5
9.5
105 °C
85 °C
8.5
25 °C
-40 °C
7.5
6.5
5.5
4.5
3.5
2.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-178. Standby Supply Current vs. VCC
25°C, running from different crystal oscillators
480
440
400
360
320
280
240
200
160
16MHz
12MHz
8MHz
2MHz
0.454MHz
3.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
233
33.3.2 I/O Pin Characteristics
33.3.2.1 Pull-up
Figure 33-179. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V
70
60
50
40
30
20
10
0
- 40°C
25°C
85°C
105°C
0.0
0.2
0.4
0.6
0.8
VPIN [V]
1.0
1.2
1.4
1.6
1.8
Figure 33-180. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V
120
105
90
75
60
45
30
15
0
- 40°C
25°C
85°C
105°C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VPIN [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
234
Figure 33-181. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.3V
135
120
105
90
75
60
45
30
15
0
- 40°C
25°C
85°C
105°C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VPIN [V]
33.3.2.2 Output Voltage vs. Sink/Source Current
Figure 33-182. I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
1.9
1.7
1.5
1.3
- 40°C
1.1
25°C
0.9
105°C
85°C
0.7
0.5
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
235
Figure 33-183. I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
3.2
2.8
2.4
2.0
1.6
- 40°C
1.2
25°C
85°C
0.8
0.4
0.0
105°C
-30
-27
-24
-21
-18
-15
-12
-9
-6
-3
0
IPIN [mA]
Figure 33-184. I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
3.6
3.2
2.8
2.4
- 40°C
2.0
1.6
25°C
1.2
105°C
0.8
85°C
0.4
0.0
-30
-27
-24
-21
-18
-15
-12
-9
-6
-3
0
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
236
Figure 33-185. I/O Pin Output Voltage vs. Source Current
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
0.5
3.6 V
3.3 V
3.0 V
2.7 V
1.8 V
1.6 V
-24
-21
-18
-15
-12
-9
-6
-3
0
IPIN [mA]
Figure 33-186. I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V
1.0
0.9
0.8
0.7
85°C
25°C
- 40°C
105°C
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
12
14
16
18
20
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
237
Figure 33-187. I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
105°C
85°C
25°C
- 40°C
0
3
6
9
12
15
18
21
24
27
30
IPIN [mA]
Figure 33-188. I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
105°C
85°C
25°C
- 40°C
0
3
6
9
12
15
18
21
24
27
30
IPIN [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
238
Figure 33-189. I/O Pin Output Voltage vs. Sink Current
1.50
1.6 V
1.8 V
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0.00
2.7 V
3.0 V
3.3 V
3.6 V
0
3
6
9
12
15
18
21
24
27
30
IPIN [mA]
33.3.2.3 Thresholds and Hysteresis
Figure 33-190. I/O Pin Input Threshold Voltage vs. VCC
T = 25°C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VIH
VIL
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
239
Figure 33-191. I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
-40 °C
25 °C
85 °C
105 °C
1.6
1.8
2.0
2.2
2.4
2.6
VCC [V]
2.8
3.0
3.2
3.4
3.6
Figure 33-192. I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
1.75
1.60
1.45
1.30
1.15
1.00
0.85
0.70
0.55
-40 °C
25 °C
85 °C
105 °C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
240
Figure 33-193. I/O Pin Input Hysteresis vs. VCC
0.32
0.29
0.26
0.23
-40 °C
25 °C
0.20
0.17
85 °C
0.14
0.11
105 °C
0.08
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
33.3.3 ADC Characteristics
Figure 33-194. INL Error vs. External VREF
T = 25C, VCC = 3.6V, external reference
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0.0
Single-ended unsigned mode
Differential mode
Single-ended signed mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
241
Figure 33-195. INL Error vs. Sample Rate
T = 25C, VCC = 2.7V, VREF = 1.0V external
1.6
1.4
Single-ended signed mode
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Differential mode
Single-ended signed mode
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC sample rate [kSps]
Figure 33-196. INL Error vs. Input Code
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
242
Figure 33-197. DNL Error vs. External VREF
T = 25C, VCC = 3.6V, external reference
1.1
1.0
Single-ended unsigned mode
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Differential mode
Single-ended signed mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
Figure 33-198. DNL Error vs. Sample rate
T = 25C, VCC = 2.7V, VREF = 1.0V external
0.43
0.41
0.38
0.36
0.33
0.31
0.28
0.26
0.23
Single-ended unsigned mode
Differential mode
Single-ended signed mode
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC sample rate [kSps]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
243
Figure 33-199. DNL Error vs. Input Code
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
Figure 33-200. Gain Error vs. VREF
T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps
12
10
8
Single-ended signed mode
Single-ended unsigned mode
6
4
2
Differential mode
0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
244
Figure 33-201. Gain Error vs. VCC
T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps
7
6
5
4
3
2
1
0
Single-ended signed mode
Single-ended unsigned mode
Differential mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 33-202. Offset Error vs. VREF
T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps
-1.0
-1.1
-1.1
-1.2
-1.2
-1.3
-1.3
-1.4
-1.4
-1.5
-1.5
Differential mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
245
Figure 33-203. Gain Error vs. Temperature
VCC = 2.7V, VREF = external 1.0V
8
7
Single-ended signed mode
6
5
4
3
2
1
0
Single-ended unsigned mode
Differential mode
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [oC]
Figure 33-204. Offset Error vs. VCC
T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
-1.1
Differential mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
246
Figure 33-205. Noise vs. VREF
T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Single-ended signed mode
Single-ended unsigend mode
Differential mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
Figure 33-206. Noise vs. VCC
T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps
0.8
Single-ended signed mode
Single-ended unsigned mode
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Differential mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
247
33.3.4 DAC Characteristics
Figure 33-207. DAC INL Error vs. VREF
VCC = 3.6V
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0.0
- 40°C
25°C
85°C
105°C
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
Figure 33-208. DNL Error vs. VREF
VCC = 3.6V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
- 40°C
25°C
85°C
105°C
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
248
Figure 33-209. DAC Noise vs. Temperature
VCC = 2.7V, VREF = 1.0V
0.178
0.176
0.174
0.172
0.170
0.168
0.166
0.164
0.162
0.160
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [oC]
33.3.5 Analog Comparator Characteristics
Figure 33-210. Analog Comparator Hysteresis vs. VCC
High-speed, small hysteresis
25
24
23
22
21
20
19
18
17
16
15
105°C
85°C
25°C
- 40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
249
Figure 33-211. Analog Comparator Hysteresis vs. VCC
Low power, small hysteresis
36
34
32
30
28
26
24
22
20
105°C
85°C
25°C
- 40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-212. Analog Comparator Hysteresis vs. VCC
High-speed mode, large hysteresis
47
45
43
41
39
37
35
33
31
29
27
105°C
85°C
25°C
- 40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
250
Figure 33-213. Analog Comparator Hysteresis vs. VCC
Low power, large hysteresis
76
73
70
67
64
61
58
55
52
49
46
105°C
85°C
25°C
- 40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-214. Analog Comparator Current Source vs. Calibration Value
Temperature = 25°C
8
7
6
5
4
3
2
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15
CURRCALIBA[3..0]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
251
Figure 33-215. Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
7.2
6.8
6.4
6.0
5.6
5.2
4.8
4.4
4.0
3.6
- 40°C
25°C
85°C
105°C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
Figure 33-216. Voltage Scaler INL vs. SCALEFAC
T = 25C, VCC = 3.0V
0.15
0.12
0.09
0.06
0.03
0.00
-0.03
-0.06
-0.09
-0.12
-0.15
0
8
16
24
32
40
48
56
64
SCALEFAC
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
252
33.3.6 Internal 1.0V Reference Characteristics
Figure 33-217. ADC/DAC Internal 1.0V Reference vs. Temperature
1.004
1.002
1.000
0.998
0.996
0.994
0.992
1.6 V
1.8 V
2.2 V
2.7 V
3.0 V
3.6 V
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
33.3.7 BOD Characteristics
Figure 33-218. BOD Thresholds vs. Temperature
BOD level = 1.6V
1.644
1.641
1.638
1.635
1.632
1.629
1.626
1.623
1.620
1.617
Rising Vcc
Falling Vcc
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
253
Figure 33-219. BOD Thresholds vs. Temperature
BOD level = 3.0V
3.08
3.07
3.06
3.05
3.04
3.03
3.02
3.01
3.00
Rising Vcc
Falling Vcc
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
33.3.8 External Reset Characteristics
Figure 33-220. Minimum Reset Pin Pulse Width vs. VCC
135
130
125
120
115
110
105
100
95
105°C
85°C
90
25°C
- 40°C
85
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
254
Figure 33-221. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
80
70
60
50
40
30
20
10
0
- 40°C
25°C
85°C
105°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VRESET [V]
Figure 33-222. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
120
105
90
75
60
45
30
15
0
- 40°C
25°C
85°C
105°C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VRESET [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
255
Figure 33-223. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
150
135
120
105
90
75
60
45
- 40°C
25°C
30
15
85°C
105°C
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VRESET [V]
Figure 33-224. Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
2.2
2.1
1.9
1.8
1.6
1.5
- 40°C
25°C
85°C
105°C
1.3
-
1.2
1.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
256
Figure 33-225. Reset Pin Input Threshold Voltage vs. VCC
VIL - Reset pin read as “0”
1.75
1.60
1.45
1.30
1.15
1.00
0.85
0.70
0.55
0.40
- 40°C
25°C
85°C
105°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
33.3.9 Power-on Reset Characteristics
Figure 33-226. Power-on Reset Current Consumption vs. VCC
BOD level = 3.0V, enabled in continuous mode
300
250
200
150
100
50
105°C
85°C
25°C
- 40°C
0
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
V
[V]
CC
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
257
Figure 33-227. Power-on Reset Current Consumption vs. VCC
BOD level = 3.0V, enabled in sampled mode
300
250
200
150
100
50
105°C
85°C
25°C
- 40°C
0
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
V
[V]
CC
33.3.10 Oscillator Characteristics
33.3.10.1 Ultra Low-Power Internal Oscillator
Figure 33-228. Ultra Low-Power Internal Oscillator Frequency vs. Temperature
34.0
33.7
33.4
33.1
32.8
32.5
32.2
31.9
31.6
31.3
31.0
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
258
33.3.10.2 32.768kHz Internal Oscillator
Figure 33-229. 32.768kHz Internal Oscillator Frequency vs. Temperature
32.85
32.82
32.79
32.76
32.73
32.70
32.67
32.64
32.61
32.58
32.55
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 33-230. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
53
50
47
44
41
38
35
32
29
26
23
0
30
60
90
120
150
180
210
240
270
RC32KCAL[7..0]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
259
33.3.10.3 2MHz Internal Oscillator
Figure 33-231. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
2.12
2.10
2.08
2.06
2.04
2.02
2.00
1.98
1.96
1.94
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 33-232. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
2.010
2.008
2.006
2.004
2.002
2.000
1.998
1.996
1.994
1.992
1.990
1.988
3.6 V
1.8 V
2.2 V
3.0 V
1.6 V
2.7 V
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
260
Figure 33-233. 2MHz Internal Oscillator CALA Calibration Step Size
VCC = 3V
0.28 %
0.26 %
0.24 %
0.22 %
0.20 %
0.18 %
0.16 %
0.14 %
0.12 %
- 40°C
25°C
105°C
85°C
0
16
32
48
64
80
96
112
128
CALA
33.3.10.4 32MHz Internal Oscillator
Figure 33-234. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
35.5
35.0
34.5
34.0
33.5
33.0
32.5
32.0
31.5
31.0
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
261
Figure 33-235. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
32.12
32.08
32.04
32.00
3.6 V
31.96
31.92
3.0 V
31.88
31.84
31.80
2.7 V
2.2 V
1.8 V
1.6 V
-30
-45
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 33-236. 32MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V
0.34 %
0.31 %
0.28 %
0.25 %
0.22 %
0.19 %
0.16 %
0.13 %
0.10 %
- 40°C
85°C
105°C
25°C
0
15
30
45
60
CALA
75
90
105
120
135
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
262
Figure 33-237. 32MHz Internal Oscillator CALB Calibration Step Size
VCC = 3.0V
2.80 %
2.60 %
2.40 %
2.20 %
2.00 %
1.80 %
1.60 %
1.40 %
1.20 %
1.00 %
0.80 %
- 40°C
25°C
85°C
105°C
0
8
16
24
32
40
48
56
64
CALB
33.3.10.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 33-238. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
53.4
52.6
51.8
51.0
50.2
49.4
48.6
47.8
47.0
46.2
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
263
Figure 33-239. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
48.15
48.10
48.05
48.00
47.95
47.90
47.85
47.80
47.75
47.70
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 33-240. 48MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V
0.30 %
0.28 %
0.26 %
0.24 %
0.22 %
0.20 %
0.18 %
0.16 %
0.14 %
0.12 %
0.10 %
- 40°C
105°C
25°C
85°C
0
16
32
48
64
80
96
112
128
CALA
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
264
33.3.11 Two-Wire Interface Characteristics
Figure 33-241. SDA Hold Time vs. Supply Voltage
300
295
290
285
280
275
270
265
260
105°C
85°C
25°C
- 40°C
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Vcc [V]
33.3.12 PDI Characteristics
Figure 33-242. Maximum PDI Frequency vs. VCC
30
28
26
24
-
- 40°C
85°C
22
20
18
16
14
12
10
25°C
105°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
265
33.4 ATxmega128D4
33.4.1 Current Consumption
33.4.1.1 Active Mode Supply Current
Figure 33-243. Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
800
700
600
500
400
300
200
100
0
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 33-244. Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
13.5
12.0
10.5
9.0
3.6V
3.0V
2.7V
7.5
6.0
4.5
2.2V
3.0
1.8V
1.5
0
0
4
8
12
16
Frequency [MHz]
20
24
28
32
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
266
Figure 33-245. Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
270
240
210
180
150
120
90
- 40 °C
25 °C
85 °C
105 °C
60
30
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-246. Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock
800
700
600
500
400
300
200
100
0
-40 °C
25 °C
85 °C
105 °C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
267
Figure 33-247. Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
-40 °C
25 °C
85 °C
1400
1225
1050
875
700
525
350
175
0
105 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
Figure 33-248. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
5800
-40 °C
5200
4600
4000
3400
2800
2200
1600
1000
25 °C
85 °C
105 °C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
268
Figure 33-249. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
13.4
12.6
11.8
11.0
10.2
9.4
-40 °C
25 °C
85 °C
105 °C
8.6
7.8
7.0
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
33.4.1.2 Idle Mode Supply Current
Figure 33-250. Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
160
140
120
100
80
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
60
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
269
Figure 33-251. Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
5.4
4.8
4.2
3.6
3.0
2.4
1.8
1.2
3.6V
3.0V
2.7V
2.2V
1.8V
0.6
0
0
4
8
12
16
20
24
28
32
Frenquecy [MHz]
Figure 33-252. Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
38
37
36
35
34
33
32
31
30
29
28
27
105 °C
-40 °C
85 °C
25 °C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
270
Figure 33-253. Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
160
150
140
130
120
110
100
90
105 °C
85 °C
25 °C
-40 °C
80
70
60
50
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-254. Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
330
310
290
270
250
230
210
190
170
150
130
110
90
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
271
Figure 33-255. Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
2000
1800
1600
1400
1200
1000
800
-40 °C
25 °C
85 °C
105 °C
600
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 33-256. Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
5000
4750
4500
4250
4000
3750
3500
3250
3000
-40 °C
25 °C
85 °C
105 °C
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
272
33.4.1.3 Power-down Mode Supply Current
Figure 33-257. Power-down Mode Supply Current vs. Temperature
All functions disabled
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 33-258. Power-down Mode Supply Current vs. VCC
All functions disabled
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
105 °C
85 °C
25 °C
-40 °C
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
273
Figure 33-259. Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
7.3
6.8
6.3
5.8
5.3
4.8
4.3
3.8
3.3
2.8
2.3
1.8
1.3
0.8
105 °C
85 °C
25 °C
-40 °C
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
33.4.1.4 Power-save Mode Supply Current
Figure 33-260. Power-save Mode Supply Current vs.VCC
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC
0.9
Normal mode
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Low-power mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
274
33.4.1.5 Standby Mode Supply Current
Figure 33-261. Standby Supply Current vs. VCC
Standby, fSYS = 1MHz
12.5
11.5
10.5
9.5
105 °C
85 °C
8.5
25 °C
-40 °C
7.5
6.5
5.5
4.5
3.5
2.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 33-262. Standby Supply Current vs. VCC
T = 25°C, running from different crystal oscillators
480
440
400
360
320
280
240
200
160
16MHz
12MHz
8MHz
2MHz
0.454MHz
3.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.6
VCC[V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
275
33.4.2 I/O Pin Characteristics
33.4.2.1 Pull-up
Figure 33-263. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V
72
64
56
48
40
32
24
16
8
-40 °C
25 °C
85 °C
105 °C
0
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
Vpin [V]
Figure 33-264. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V
120
105
90
75
60
45
30
15
0
-40 °C
25 °C
85 °C
105 °C
0.1
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vpin [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
276
Figure 33-265. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.3V
135
120
105
90
75
60
45
30
15
0
-40 °C
25 °C
85 °C
105 °C
0.1
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
3.1
3.4
Vpin [V]
33.4.2.2 Output Voltage vs. Sink/Source Current
Figure 33-266. I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
-40 °C
25 °C 85 °C 105 °C
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Ipin [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
277
Figure 33-267. I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
3.30
2.95
2.60
2.25
1.90
1.55
-40 °C
-27
85 °C
-21
105 °C
25 °C
-24
1.20
0.85
0.50
-30
-18
-15
Ipin [mA]
-12
-9
-6
-3
0
Figure 33-268. I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
3.5
3.2
2.9
2.6
2.3
2.0
-40 °C
1.7
1.4
25 °C
1.1
105 °C
85 °C
-27
0.8
0.5
-30
-24
-21
-18
-15
-12
-9
-6
-3
0
Ipin [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
278
Figure 33-269. I/O Pin Output Voltage vs. Source Current
3.65
3.30
2.95
2.60
2.25
1.90
1.55
1.20
0.85
0.50
3.6 V
3.3 V
3.0 V
2.7 V
1.8 V
1.6 V
-24
-21
-18
-15
-12
-9
-6
-3
0
Ipin [mA]
Figure 33-270. I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
85 °C
105 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
16
18
20
Ipin [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
279
Figure 33-271. I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
105 °C
85 °C
25 °C
-40 °C
0
3
6
9
12
15
18
21
24
27
30
Ipin [mA]
Figure 33-272. I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
105 °C
85 °C
25 °C
-40 °C
0
3
6
9
12
15
18
21
24
27
30
Ipin [mA]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
280
Figure 33-273. I/O Pin Output Voltage vs. Sink Current
1.50
1.35
1.20
1.05
1.8 V
2.7 V
3.0 V
3.3 V
3.6 V
1.6 V
0.90
0.75
0.60
0.45
0.30
0.15
0.00
0
3
6
9
12
15
18
21
24
27
30
Ipin [mA]
33.4.2.3 Thresholds and Hysteresis
Figure 33-274. I/O Pin Input Threshold Voltage vs. VCC
T = 25°C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VIH
VIL
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
281
Figure 33-275. I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
105 °C
85 °C
25 °C
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
-40 °C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 33-276. I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
1.75
1.60
1.45
1.30
1.15
1.00
0.85
0.70
0.55
0.40
105 °C
85 °C
25 °C
-40 °C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
282
Figure 33-277. I/O Pin Input Hysteresis vs. VCC
0.41
0.39
0.37
0.35
0.33
-40 °C
0.31
25 °C
0.29
0.27
0.25
85 °C
0.23
0.21
105 °C
0.19
0.17
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
33.4.3 ADC Characteristics
Figure 33-278. INL Error vs. External VREF
T = 25C, VCC = 3.6V, external reference
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
Differential Signed
Single-ended Unsigned
0.9
0.8
0.7
Single-ended Signed
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
283
Figure 33-279. INL Error vs. Sample rate
T = 25C, VCC = 3.6V, VREF = 3.0V external
1.4
1.35
1.3
Differential Mode
1.25
1.2
Single-ended Unsigned
1.15
1.1
1.05
Single-ended Signed
1
0.95
0.9
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC Sample Rate [kSPS]
Figure 33-280. INL Error vs. Input code
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
284
Figure 33-281. DNL Error vs. External VREF
T = 25C, VCC = 3.6V, external reference
0.9
0.88
0.86
Differential Mode
0.84
0.82
0.8
Single-ended Signed
0.78
0.76
0.74
0.72
Single-ended Unsigned
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 33-282. DNL Error vs. Sample Rate
T = 25C, VCC = 3.6V, VREF = 3.0V external
0.9
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.8
Differential Signed
Single-ended Signed
Single-ended Unsigned
0.79
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC Sample Rate [kSPS]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
285
Figure 33-283. DNL Error vs. Input Code
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0
512
1024
1536
2048
2560
3072
3584
4096
Figure 33-284. Gain Error vs. VREF
T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps
3
Single-ended Signed
Differential Mode
2
1
0
-1
-2
-3
-4
Single-ended Unsigned
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
REF [V]
V
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
286
Figure 33-285. Gain Error vs. VCC
T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps
2.2
1.9
1.6
1.3
1
Single-ended Signed
Differential Mode
0.7
0.4
0.1
-0.2
-0.5
Single-ended Unsigned
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 33-286. Offset Error vs. VREF
T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
Differential Mode
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
REF [V]
V
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
287
Figure 33-287. Gain Error vs. Temperature
VCC = 3.0V, VREF = external 2.0V
3
2
Single-ended Signed
1
Differential Signed
0
-1
-2
-3
-4
Single-ended Unsigned
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [ºC]
Figure 33-288. Offset Error vs. VCC
T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
Differential Signed
-1.1
-1.2
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
288
Figure 33-289. Noise vs. VREF
T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps
1.3
1.15
1
Single-ended Signed
Single-ended Unsigned
0.85
0.7
0.55
0.4
Differential Signed
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 33-290. Noise vs. VCC
T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps
1.3
1.2
1.1
1
Single-ended Signed
0.9
0.8
0.7
0.6
0.5
0.4
0.3
Single-ended Unsigned
Differential Signed
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
289
33.4.4 DAC Characteristics
Figure 33-291. DAC INL Error vs. VREF
VCC = 3.6V
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
25°C
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
VREF [V]
Figure 33-292. DNL Error vs. VREF
T = 25C, VCC = 3.6V
0.9
0.85
0.8
0.75
0.7
0.65
0.6
25ºC
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
290
Figure 33-293. DAC Noise vs. Temperature
VCC = 3.0V, VREF = 2.4V
0.185
0.180
0.175
0.170
0.165
0.160
0.155
0.150
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [ºC]
33.4.5 Analog Comparator Characteristics
Figure 33-294. Analog Comparator Hysteresis vs. VCC
High-speed, small hysteresis
14
13
12
11
10
9
105°
C
85°C
25°C
-40°
8
7
6
5
4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
291
Figure 33-295. Analog Comparator Hysteresis vs. VCC
Low power, small hysteresis
30
28
26
24
22
20
18
16
14
12
105°C
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-296. Analog Comparator Hysteresis vs. VCC
High-speed mode, large hysteresis
32
30
28
26
24
22
20
18
16
14
105°C
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
292
Figure 33-297. Analog Comparator Hysteresis vs. VCC
Low power, large hysteresis
68
64
60
56
52
48
44
40
36
32
105°C
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 33-298. Analog Comparator Current Source vs. Calibration Value
Temperature = 25°C
8
7.5
7
6.5
6
5.5
5
3.6V
4.5
4
3.0V
3.5
3
2.2V
1.8V
2.5
2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
293
Figure 33-299. Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
7
6.5
6
5.5
5
4.5
4
-40°C
25°C
85°C
3.5
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
Figure 33-300. Voltage Scaler INL vs. SCALEFAC
T = 25C, VCC = 3.0V
0.050
0.025
0
-0.025
-0.050
-0.075
-0.100
-0.125
-0.150
25°C
0
10
20
30
40
50
60
70
SCALEFAC
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
294
33.4.6 Internal 1.0V Reference Characteristics
Figure 33-301. ADC/DAC Internal 1.0V Reference vs. Temperature
1.0024
1.0020
1.0016
1.0012
1.0008
1.0004
1.0000
0.9996
0.9992
0.9988
1.6V
1.8V
2.7V
3.0V
3.6V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
33.4.7 BOD Characteristics
Figure 33-302. BOD Thresholds vs. Temperature
BOD level = 1.6V
1.596
1.593
1.590
1.587
1.584
1.581
1.578
1.575
1.572
Rising Vcc
Falling Vcc
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
295
Figure 33-303. BOD Thresholds vs. Temperature
BOD level = 3.0V
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
2.94
Rising Vcc
Falling Vcc
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
33.4.8 External Reset Characteristics
Figure 33-304. Minimum Reset Pin Pulse Width vs. VCC
135
130
125
120
115
110
105
100
95
105 °C
85 °C
90
25 °C
85
-40 °C
80
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
296
Figure 33-305. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
80
72
64
56
48
40
32
24
16
8
-40 °C
25 °C
85 °C
105 °C
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Vreset [V]
Figure 33-306. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
135
120
105
90
75
60
45
30
15
0
-40 °C
25 °C
85 °C
105 °C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
Vreset [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
297
Figure 33-307. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
150
135
120
105
90
75
60
45
30
-40 °C
25 °C
15
85 °C
0
105 °C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
Vreset [V]
Figure 33-308. Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
2.20
2.05
1.90
1.75
1.60
1.45
1.30
1.15
1.00
-40 °C
25 °C
85 °C
105 °C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
298
Figure 33-309. Reset Pin Input Threshold Voltage vs. VCC
VIL - Reset pin read as “0”
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
105 °C
85 °C
25 °C
-40 °C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
33.4.9 Power-on Reset Characteristics
Figure 33-310. Power-on Reset Current Consumption vs. VCC
BOD level = 3.0V, enabled in continuous mode
700
600
500
400
300
200
100
0
-40 °C
25 °C
85 °C
105 °C
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
299
Figure 33-311. Power-on Reset Current Consumption vs. VCC
BOD level = 3.0V, enabled in sampled mode
650
585
520
455
390
325
260
195
130
65
-40 °C
25 °C
85°C
°
105°°C
0
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
33.4.10 Oscillator Characteristics
33.4.10.1 Ultra Low-Power Internal Oscillator
Figure 33-312. Ultra Low-Power Internal Oscillator Frequency vs. Temperature
33.75
33.50
33.25
33.00
32.75
32.50
32.25
32.00
31.75
31.50
31.25
31.00
30.75
3.6 V
3.3 V
3.0 V
2.7 V
1.8 V
1.6 V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
300
33.4.10.2 32.768kHz Internal Oscillator
Figure 33-313. 32.768kHz Internal Oscillator Frequency vs. Temperature
32.82
32.79
32.76
32.73
32.70
32.67
32.64
32.61
32.58
32.55
32.52
32.49
32.46
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
Figure 33-314. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
52
49
46
43
40
37
34
31
28
25
22
3.0 V
0
24
48
72
96
120
144
168
192
216
240
264
RC32KCAL[7..0]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
301
33.4.10.3 2MHz Internal Oscillator
Figure 33-315. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
2.16
2.14
2.12
2.10
2.08
2.06
2.04
2.02
2.00
1.98
1.96
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
Figure 33-316. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
2.006
2.004
2.002
2.000
1.998
1.996
1.994
1.992
1.990
1.988
1.986
1.984
1.982
1.980
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
302
Figure 33-317. 2MHz Internal Oscillator CALA Calibration Step Size
VCC = 3V
0.30
0.28
0.26
0.24
0.22
0.20
0.18
0.16
0.14
-40 °C
25 °C
85 °C
105 °C
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
33.4.10.4 32MHz Internal Oscillator
Figure 33-318. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
36.00
35.55
35.10
34.65
34.20
33.75
33.30
32.85
32.40
31.95
31.50
31.05
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
303
Figure 33-319. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
32.05
32.02
31.99
31.96
31.93
31.90
31.87
31.84
31.81
31.78
31.75
31.72
31.69
31.66
1.8 V
2.2 V
2.7 V
3.0 V
3.3 V
3.6 V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
Figure 33-320. 32MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V
0.32
0.29
0.26
0.23
0.20
0.17
0.14
-40 °C
105 °C
85 °C
25 °C
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
304
33.4.10.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 33-321. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
53.9
53.2
52.5
51.8
51.1
50.4
49.7
49.0
48.3
47.6
46.9
46.2
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
Figure 33-322. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
48.3
48.2
48.1
48.0
47.9
47.8
47.7
47.6
47.5
1.8 V
2.2 V
2.7 V
3.0 V
3.3 V
3.6 V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
305
Figure 33-323. 48MHz Internal Oscillator CALA Calibration Step Size
VCC = 3V
0.28
0.26
0.24
0.22
0.2
-40 °C
105 °C
85 C
25 °C
0.18
0.16
0.14
°
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
33.4.11 Two-Wire Interface Characteristics
Figure 33-324. SDA Hold Time vs. Supply Voltage
300
295
290
285
280
275
270
265
260
105°C
85°C
25°C
- 40°C
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
306
33.4.12 PDI Characteristics
Figure 33-325. Maximum PDI Frequency vs. VCC
-40 °C
31
28
25
22
19
16
13
10
25 °C
85 °C
105 °C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
307
34. Errata
34.1 ATxmega16D4 / ATxmega32D4
34.1.1 Rev. I
Temperature sensor not calibrated
1. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/Workaround
None.
34.1.2 Rev. F/G/H
Not sampled.
34.1.3 Rev. E
ADC propagation delay is not correct when gain is used
CRC fails for Range CRC when end address is the last word address of a flash section
AWeX fault protection restore is not done correct in Pattern Generation Mode
Erroneous interrupt when using Timer/Counter with QDEC
AC system status flags are only valid if AC-system is enabled
Temperature sensor not calibrated
1. ADC propagation delay is not correct when gain is used
The propagation delay will increase by only one ADC clock cycle for all gain setting.
Problem fix/Workaround
None.
2. CRC fails for Range CRC when end address is the last word address of a flash section
If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If application
table read lock is enabled, the range CRC cannot end on the last address before the application table.
Problem fix/Workaround
Ensure that the end address used in Range CRC does not end at the last address before a section with read lock
enabled. Instead, use the dedicated CRC commands for complete applications sections.
3. AWeX fault protection restore is not done correct in Pattern Generation Mode
When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is
restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM),
this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM),
OUTOVEN should instead have been restored according to the DTILSBUF register.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
308
Problem fix/Workaround
For CWCM no workaround is required.
For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct
OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correct
outputs again.
For PGM in cycle-by-cycle mode there is no workaround.
4. Erroneous interrupt when using Timer/Counter with QDEC
When the Timer/Counter is set in Dual Slope mode with QDEC enabled, an additional underflow interrupt (and
event) will be given when the counter counts from BOTTOM to one.
Problem fix/Workaround
When receiving underflow interrupt check direction and value of counter. If direction is UP and counter value is
zero, change the counter value to one. This will also remove the additional event. If the counter value is above
zero, clear the interrupt flag.
5. AC system status flags are only valid if AC-system is enabled
The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not
possible to clear the AC interrupt flags without enabling either of the Analog comparators.
Problem fix/Workaround
Software should clear the AC system flags once, after enabling the AC system before using the AC system status
flags.
6. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/Workaround
None.
34.1.4 Rev. C/D
Not sampled.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
309
34.1.5 Rev. A/B
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4 V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8x -64x gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in XMEGA A Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD: BOD will be enabled at any reset
Sampled BOD in Active mode will cause noise when bandgap is used as reference
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
Flash Power Reduction Mode can not be enabled when entering sleep
Crystal start-up time required after power-save even if crystal is source for RTC
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
Inverted I/O enable does not affect Analog Comparator Output
TWIE is not available
CRC generator module is not available
ADC 1/x gain setting and VCC/2 reference setting is not available
TOSC alternate pin locations is not available
TWI SDAHOLD time configuration is not available
Timer/Counter 2 is not available
HIRES+ option is not available
Alternate pin locations for digital peripherals are not available
XOSCPWR high drive option for external crystal is not available
PLL divide by two option is not available
Real Time Counter non-prescaled 32kHZ clock options are not available
PLL lock detection failure function is not available
Non available functions and options
Temperature sensor not calibrated
Disabling the USART transmitter does not automatically set the TxD pin direction to output.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
310
1. Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input
for another AC, the first comparator will be affected for up to 1 ìs and could potentially give a wrong comparison
result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling
any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
Figure 34-1. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
3.5
3.3V
3
2.7V
2.5
2
1.8V
1.5
1
0.5
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
SCALEFAC
Problem fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed.
3. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
6LSB for reference voltage below 1.1V when VCC is above 3.0V.
20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/Workaround
None. Avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in
signed mode also for single ended measurements.
4. ADC gain stage output range is limited to 2.4V
The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only give cor-
rect output when below 2.4V/gain. For the available gain settings, this gives a differential input range of:
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
311
1x gain:
2x gain:
4x gain:
8x gain:
16x gain:
32x gain:
64x gain:
2.4V
1.2V
0.6v
300mV
150mV
75mV
38mV
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep
ADC voltage reference below 2.4V.
5. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to
BELOW or ABOVE.
Problem fix/Workaround
Enable and use interrupt on compare match when using the compare function.
6. ADC propagation delay is not correct when 8x -64x gain is used
The propagation delay will increase by only one ADC clock cycle for 8x and 16x gain setting, and 32x and 64x gain
settings.
Problem fix/Workaround
None.
7. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
None.
8. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disre-
garded to achieve 12-bit accuracy.
Problem fix/Workaround
Run three ADC conversions and discard these results after changing input channels to ADC gain stage.
9. Configuration of PGM and CWCM not as described in XMEGA A Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Wave-
form Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both
Pattern Generation Mode and Common Waveform Channel Mode.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
312
Problem fix/Workaround
Table 34-1. Configure PWM and CWCM According to this Table
PGM
CWCM
Description
0
0
1
1
0
1
0
1
PGM and CWCM disabled
PGM enabled
PGM and CWCM enabled
PGM enabled
10 PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation
at first update after fault condition is no longer present.
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
11. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below
the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the pro-
grammed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
12. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC or the Analog Comparator, the BOD must not be set in sam-
pled mode.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM
page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is
executed, will be ignored until the device is woken from another source or the source triggers again. This applies
when entering all sleep modes where the System Clock is stopped.
Problem fix/Workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator output.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
313
Problem fix/Workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the neg-
ative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output.
16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt
handler
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required
17. Flash Power Reduction Mode can not be enabled when entering sleep
If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby sleep mode, the
device will only wake up on every fourth wake-up request. If Flash Power Reduction Mode is enabled when enter-
ing Idle sleep mode, the wake-up time will vary with up to 16 CPU clock cycles.
Problem fix/Workaround
Disable Flash Power Reduction mode before entering sleep mode.
18. Crystal start-up time required after power-save even if crystal is source for RTC
Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be ready for the system
before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection " in XMEGA A Manual. If BOD
is used in active mode, the BOD will be on during this period (0.5s).
Problem fix/Workaround
If faster start-up is required, go to sleep with internal oscillator as system clock
19. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as
the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled
RTC clock cycle after wakeup. The value read will be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
20. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will
be ignored until the device is woken from another source or the source triggers again.
Problem fix/Workaround
None.
21. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on
start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
314
22. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this
flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the
bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the
SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
23. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the
transaction will be dropped.
Problem fix/Workaround
None.
24. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data
interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
25. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the
counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
26. Inverted I/O enable does not affect Analog Comparator Output
The inverted I/O pin function does not affect the Analog Comparator output function.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
315
Problem fix/Workaround
Configure the analog comparator setup to give an inverted result, or use an external inverter to change polarity of
Analog Comparator Output.
27. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or configure
these functions or options will have no effect, and will be as writing to a reserved address location.
●
●
●
●
●
●
TWIE, the TWI module on PORTE.
TWI SDAHOLD option in the TWI CTRL register is one bit.
CRC generator module.
ADC 1/2x gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register.
ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register.
ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the
MUXNEG bits in the ADC Channel MUXCTRL register.
●
●
●
●
ADC channel scan and the ADC SCAN register
ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register.
Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0 CTRLE
register.
●
●
Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers.
PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI,
and the PORT REMAP register.
●
●
PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register.
PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the
PORT CLKEVOUT register.
●
●
TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2
Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and
32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the Clock
RTCTRL register.
●
●
●
●
PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register.
PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register.
The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register.
The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control memory.
Problem fix/Workaround
None.
28. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/Workaround
None.
29. Disabling of USART transmitter does not automatically set the TxD pin direction to input
If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD
pin direction to input.
Problem fix/Workaround
The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register
to input will be immediate. Ongoing transmissions will be truncated.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
316
34.2 ATxmega64D4
34.2.1 Rev. D
Temperature sensor not calibrated
1. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/Workaround
None.
34.2.2 Rev. B/C
Not sampled.
34.2.3 Rev. A
ADC may have missing codes in SE unsigned mode at low temp and low VCC
Temperature sensor not calibrated
1. ADC may have missing codes in SE unsigned mode at low temp and low VCC
The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.
Problem fix/Workaround
Use the ADC in SE signed mode.
2. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/Workaround
None.
34.3 ATxmega128D4
34.3.1 Rev. A
Temperature sensor not calibrated
1. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/Workaround
None.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
317
35. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this
section are referring to the document revision.
35.1 8135S – 09/2016
1.
2.
Updated “Instruction Set Summary” on page 56. Removed “DES” instruction.
Updated “Gain Stage Characteristics” : Table 32-11 on page 72, Table 32-39 on page 91Table 32-67 on page 110 and
Table 32-96 on page 131. “Offset Error, input referred” is changed to “Offset Error, output referred.
35.2 8135R – 02/2015
1.
2.
3.
4.
Updated Figure 25-1 on page 45
Updated the “Packaging information” on page 61. Replaced “44M1” on page 62 by a correct package.
Updated tables Table 32-8 on page 70and Table 32-36 on page 89 with information on fixed voltage offset.
Updated use of capitals in heading, table headings and figure titles.
35.3 8135Q – 09/2014
1.
2.
3.
Updated the “Ordering Information” on page 2. Added ordering information for ATxmega16D4/32D4/64D4/128D4 @
105C.
Updated the Application table section from 4K/4K/4K/4K to 8K/4K/4K/4K in the Figure 7-1 on page 13
Updated Table 32-4 on page 66, Table 32-33 on page 86, Table 32-60 on page 104 and Table 32-89 on page 125.
Added Icc Power-down power consumption for T=105C for all functions disabled and for WDT and sampled BOD
enabled
Updated Table 32-17 on page 74, Table 32-45 on page 93, Table 32-73 on page 112 and Table 32-102 on page 133.
Updated all tables to include values for T=85C and T=105C. Removed T=55C
4.
5.
6.
Changed Vcc to AVcc in Figure 25-1 on page 45 and in the text in Section 25. “ADC – 12-bit Analog to Digital
Converter” on page 44 and in Section 26. “AC – Analog Comparator” on page 46
Changed unit parameter for tSU;DAT to ns in Table 32-28 on page 82, Table 32-56 on page 101, Table 32-85 on page
121 and Table 32-114 on page 142.
Added ERRATA information on disabling of USART transmitter to Section 34.1 “ATxmega16D4 / ATxmega32D4” on
page 308.
7.
8.
Updated the typical characteristics of “ATxmega64D4” and “ATxmega128D4” with characterizations @105C
35.4 8135P – 01/2014
1.
Updated the typical characteristics of “ATxmega16D4” and “ATxmega32D4” with characterizations @ 105C
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
318
35.5 8135O – 08/2013
1.
Updated “Errata” :
●
●
●
ATxmega16D4/32D4: Added Temperature sensor not calibrated to “Rev. I” , “Rev. E” and “Rev. A/B”
ATxmega64D4: Added Temperature sensor not calibrated to “Rev. D” and “Rev. A”
ATxmega128D4: Added Temperature sensor not calibrated to “Rev. A”
35.6 8135N – 04/2013
1.
2.
Updated description in “ADC – 12-bit Analog to Digital Converter” on page 44.
Updated “Errata” :
●
●
●
ATxmega16D4/32D4: Added revision F, G, H, I
ATxmega64D4: Added revision A, B, C
ATxmega128D4: Added revision A
35.7 8135M – 02/2013
1.
2.
3.
4.
5.
Updated the datasheet with the Atmel new datasheet template.
Updated Figure 2-1 on page 4. PE2/PE3 are now half gray.
Updated Figure 2-1 on page 4. Pin 19 is VCC and not VDD.
Updated Table 7-2 on page 16. FWORD column updated: Z[X,0] replaced by Z[X,1]. FPAGE column updated to Z[Y,8]
Updated “I/O Ports” on page 29. Removed “Optional slew rate control”. The feature doesn't exist in XMEGA C and
XMEGA D devices.
6.
Updated “Analog Comparator Overview” on page 47, Figure 26-1.
7.
Updated Table 32-25 on page 77, Table 32-53 on page 96 and Table 32-82 on page 116. Added ESR parameter.
Updated TWI specification. VIL Min is -0.5V and not 0.5V.
8.
9.
Added new “Electrical Characteristics” for “ATxmega16D4” on page 64 and “ATxmega32D4” on page 83.
Added new “Typical Characteristics” for “ATxmega16D4” on page 144 and “ATxmega32D4” on page 184.
Updated “Errata” on page 308. AC system status flags are only valid if AC-system is enabled.
10.
11.
35.8 8135L – 08/2012
1.
2.
3.
4.
5.
Editing updates.
Updated all tables in the “Electrical Characteristics” on page 64.
Added new “Typical Characteristics” on page 144.
Added new Errata “Rev. E” on page 308.
Added new ERRATA on “Rev. A/B” on page 310: Non available functions and options
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
319
35.9 8135K – 06/2012
1.
ATxmega64D4-CU is added in “Ordering Information” on page 2
35.10 8135J – 12/10
1.
2.
3.
4.
5.
6.
7.
Datasheet status changed to complete: Preliminary removed from the front page.
Updated all tables in the “Electrical Characteristics” on page 64.
Replaced Table 31-11 on page 64.
Replaced Table 31-17 on page 65 and added the figure ”TOSC input capacitance” on page 66.
Updated ERRATA ADC (ADC has increased INL for some operating conditions).
Updated ERRATA ”rev. A/B” on page 90 with TWIE (TWIE is not available).
Updated the last page with Atmel new Brand Style Guide.
35.11 8135I – 10/10
1.
Updated Table 31-1 on page 58.
35.12 8135H – 09/10
1.
Updated ”Errata” on page 90.
35.13 8135G – 08/10
1.
2.
3.
4.
5.
6.
7.
Updated the Footnote 3 of ”Ordering Information” on page 2.
All references to CRC removed. Updated Figure 3-1 on page 7.
Updated ”Features” on page 26. Event Channel 0 output on port pin 7.
Updated ”DC Characteristics” on page 58 by adding Icc for Flash/EEPROM Programming.
Added AVCC in ”ADC Characteristics” on page 62.
Updated Start up time in ”ADC Characteristics” on page 62.
Updated and fixed typo in “Errata” section.
35.14 8135F – 02/10
1.
Added ”PDI Speed” on page 89.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
320
35.15 8135E – 02/10
1.
Updated the device pin-out Figure 2-1 on page 3. PDI_CLK and PDI_DATA renamed only PDI.
2.
Updated Table 7-3 on page 18. No of Pages for ATxmega32D4: 32
Updated ”Alternate Port Functions” on page 29.
Updated ”ADC - 12-bit Analog to Digital Converter” on page 39.
Updated Figure 25-1 on page 50.
3.
4.
5.
6.
Updated ”Alternate Pin Functions” on page 48.
Updated ”Timer/Counter and AWEX functions” on page 46.
Added Table 31-17 on page 65.
7.
8.
9.
Added Table 31-18 on page 66.
10.
11.
Changed Internal Oscillator Speed to ”Oscillators and Wake-up Time” on page 85.
Updated ”Errata” on page 90.
35.16 8135D – 12/09
1.
2.
3.
4.
5.
Added ATxmega128D4 device and updated the datasheet accordingly.
Updated ”Electrical Characteristics” on page 58 with Max/Min numbers.
Added ”Flash and EEPROM Memory Characteristics” on page 61.
Updated Table 31-10 on page 64, Input hysteresis is in V and not in mV.
Added ”Errata” on page 90.
35.17 8135C – 10/09
1.
2.
3.
4.
5.
6.
7.
8.
Updated ”Features” on page 1 with Two Two-Wire Interfaces.
Updated ”Block Diagram and QFN/TQFP pinout” on page 3.
Updated ”Overview” on page 5.
Updated ”XMEGA D4 Block Diagram” on page 7.
Updated Table 13-1 on page 24.
Updated ”Overview” on page 35.
Updated Table 27-5 on page 49.
Updated ”Peripheral Module Address Map” on page 50.
35.18 8135B – 09/09
1.
2.
Added ”Electrical Characteristics” on page 58.
Added ”Typical Characteristics” on page 67.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
321
35.19 8135A – 03/09
1.
Initial revision.
XMEGA D4 [DATASHEET]
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
322
Table of Contents
Features1
1
2
3
Ordering Information ...............................................................................2
Pinout/Block diagram ..............................................................................4
Overview ...................................................................................................6
3.1Block Diagram ........................................................................................................... 7
4
Resources .................................................................................................8
4.1Recommended Reading............................................................................................ 8
5
6
Capacitive Touch Sensing .......................................................................8
AVR CPU ...................................................................................................9
6.1Features .................................................................................................................... 9
6.2Overview.................................................................................................................... 9
6.3Architectural Overview............................................................................................... 9
6.4ALU - Arithmetic Logic Unit ..................................................................................... 10
6.5Program Flow .......................................................................................................... 11
6.6Status Register........................................................................................................ 11
6.7Stack and Stack Pointer .......................................................................................... 11
6.8Register File ............................................................................................................ 11
7
Memories .................................................................................................12
7.1Features .................................................................................................................. 12
7.2Overview.................................................................................................................. 12
7.3Flash Program Memory........................................................................................... 13
7.4Fuses and Lock Bits ................................................................................................ 14
7.5Data Memory........................................................................................................... 14
7.6EEPROM................................................................................................................. 15
7.7I/O Memory.............................................................................................................. 15
7.8Data Memory and Bus Arbitration ........................................................................... 16
7.9Memory Timing........................................................................................................ 16
7.10Device ID and Revision ......................................................................................... 16
7.11I/O Memory Protection........................................................................................... 16
7.12Flash and EEPROM Page Size............................................................................. 16
8
Event System ..........................................................................................18
8.1Features .................................................................................................................. 18
8.2Overview.................................................................................................................. 18
XMEGA D4 [DATASHEET]
i
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
9
System Clock and Clock Options .........................................................19
9.1Features .................................................................................................................. 19
9.2Overview.................................................................................................................. 19
9.3Clock Sources ......................................................................................................... 20
10 Power Management and Sleep Modes .................................................22
10.1Features ................................................................................................................ 22
10.2Overview................................................................................................................ 22
10.3Sleep Modes.......................................................................................................... 22
11 System Control and Reset .....................................................................24
11.1Features ................................................................................................................ 24
11.2Overview................................................................................................................ 24
11.3Reset Sequence.................................................................................................... 24
11.4Reset Sources....................................................................................................... 25
12 WDT – Watchdog Timer .........................................................................26
12.1Features ................................................................................................................ 26
12.2Overview................................................................................................................ 26
13 Interrupts and Programmable Multilevel Interrupt Controller ............27
13.1Features ................................................................................................................ 27
13.2Overview................................................................................................................ 27
13.3Interrupt Vectors.................................................................................................... 27
14 I/O Ports ..................................................................................................29
14.1Features ................................................................................................................ 29
14.2Overview................................................................................................................ 29
14.3Output Driver ......................................................................................................... 30
14.4Input Sensing......................................................................................................... 31
14.5Alternate Port Functions........................................................................................ 32
15 TC0/1 – 16-bit Timer/Counter Type 0 and 1 ..........................................33
15.1Features ................................................................................................................ 33
15.2Overview................................................................................................................ 33
16 TC2 Timer/Counter Type 2 .....................................................................35
16.1Features ................................................................................................................ 35
16.2Overview................................................................................................................ 35
17 AWeX – Advanced Waveform Extension .............................................36
17.1Features ................................................................................................................ 36
XMEGA D4 [DATASHEET]
ii
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
17.2Overview................................................................................................................ 36
18 Hi-Res – High Resolution Extension ....................................................37
18.1Features ................................................................................................................ 37
18.2Overview................................................................................................................ 37
19 RTC – 16-bit Real-Time Counter ...........................................................38
19.1Features ................................................................................................................ 38
19.2Overview................................................................................................................ 38
20 TWI – Two-Wire Interface .......................................................................39
20.1Features ................................................................................................................ 39
20.2Overview................................................................................................................ 39
21 SPI – Serial Peripheral Interface ...........................................................40
21.1Features ................................................................................................................ 40
21.2Overview................................................................................................................ 40
22 USART .....................................................................................................41
22.1Features ................................................................................................................ 41
22.2Overview................................................................................................................ 41
23 IRCOM – IR Communication Module ....................................................42
23.1Features ................................................................................................................ 42
23.2Overview................................................................................................................ 42
24 CRC – Cyclic Redundancy Check Generator ......................................43
24.1Features ................................................................................................................ 43
24.2Overview................................................................................................................ 43
25 ADC – 12-bit Analog to Digital Converter ............................................44
25.1Features ................................................................................................................ 44
25.2Overview................................................................................................................ 44
26 AC – Analog Comparator .......................................................................46
26.1Features ................................................................................................................ 46
26.2Overview................................................................................................................ 46
27 Programming and Debugging ...............................................................48
27.1Features ................................................................................................................ 48
27.2Overview................................................................................................................ 48
28 Pinout and Pin Functions ......................................................................49
28.1Alternate Pin Function Description ........................................................................ 49
XMEGA D4 [DATASHEET]
iii
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
28.2Alternate Pin Functions ......................................................................................... 51
29 Peripheral Module Address Map ...........................................................54
30 Instruction Set Summary .......................................................................56
31 Packaging information ...........................................................................61
31.144A ........................................................................................................................ 61
31.244M1...................................................................................................................... 62
31.349C2...................................................................................................................... 63
32 Electrical Characteristics ......................................................................64
32.1ATxmega16D4....................................................................................................... 64
32.2ATxmega32D4....................................................................................................... 83
32.3ATxmega64D4..................................................................................................... 102
32.4ATxmega128D4................................................................................................... 123
33 Typical Characteristics ........................................................................144
33.1ATxmega16D4..................................................................................................... 144
33.2ATxmega32D4..................................................................................................... 184
33.3ATxmega64D4..................................................................................................... 224
33.4ATxmega128D4................................................................................................... 266
34 Errata .....................................................................................................308
34.1ATxmega16D4 / ATxmega32D4.......................................................................... 308
34.2ATxmega64D4..................................................................................................... 317
34.3ATxmega128D4................................................................................................... 317
35 Datasheet Revision History .................................................................318
35.18135S – 09/2016 ................................................................................................. 318
35.28135R – 02/2015................................................................................................. 318
35.38135Q – 09/2014................................................................................................. 318
35.48135P – 01/2014 ................................................................................................. 318
35.58135O – 08/2013................................................................................................. 319
35.68135N – 04/2013................................................................................................. 319
35.78135M – 02/2013................................................................................................. 319
35.88135L – 08/2012.................................................................................................. 319
35.98135K – 06/2012 ................................................................................................. 320
35.108135J – 12/10.................................................................................................... 320
35.118135I – 10/10..................................................................................................... 320
35.128135H – 09/10................................................................................................... 320
XMEGA D4 [DATASHEET]
iv
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
35.138135G – 08/10................................................................................................... 320
35.148135F – 02/10 ................................................................................................... 320
35.158135E – 02/10 ................................................................................................... 321
35.168135D – 12/09................................................................................................... 321
35.178135C – 10/09................................................................................................... 321
35.188135B – 09/09 ................................................................................................... 321
35.198135A – 03/09 ................................................................................................... 322
Table of Contentsi
XMEGA D4 [DATASHEET]
v
Atmel-8135S-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–09/2016
X
X X X X
X
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
www.atmel.com
© 2015 Atmel Corporation. / Rev.: Atmel-8135R-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet_09/2016.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
other countries. Other terms and product names may be trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right
is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT
SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES
FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this
document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information
contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,
authorized, or warranted for use as components in applications intended to support or sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where
the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written
consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.
Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are
not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.
相关型号:
©2020 ICPDF网 联系我们和版权申明