AT90CAN128-16M_技术文档

1. Features

• High-performance, Low-power AVR^®8-bit Microcontroller

• Advanced RISC Architecture

– 133 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers + Peripheral Control Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

• Non volatile Program and Data Memories

– 32K/64K Bytes of In-System Reprogrammable Flash (AT90CAN32/64)

• Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

• Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes

• In-System Programming by On-Chip Boot Program (CAN, UART)

• True Read-While-Write Operation

8-bit

Microcontroller

with

32/64K Bytes of

ISP Flash

and

– 1K/2K Bytes EEPROM (Endurance: 100,000 Write/Erase Cycles) (AT90CAN32/64)

– 2K/4K Bytes Internal SRAM (AT90CAN32/64)

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Programming Flash (Hardware ISP), EEPROM, Lock & Fuse Bits

– Extensive On-chip Debug Support

• CAN Controller 2.0A & 2.0B

– 15 Full Message Objects with Separate Identifier Tags and Masks

– Transmit, Receive, Automatic Reply and Frame Buffer Receive Modes

– 1Mbits/s Maximum Transfer Rate at 8 MHz

– Time stamping, TTC & Listening Mode (Spying or Autobaud)

• Peripheral Features

CAN Controller

– Programmable Watchdog Timer with On-chip Oscillator

– 8-bit Synchronous Timer/Counter-0

• 10-bit Prescaler

• External Event Counter

• Output Compare or 8-bit PWM Output

– 8-bit Asynchronous Timer/Counter-2

• 10-bit Prescaler

AT90CAN32

AT90CAN64

• External Event Counter

• Output Compare or 8-Bit PWM Output

• 32Khz Oscillator for RTC Operation

– Dual 16-bit Synchronous Timer/Counters-1 & 3

• 10-bit Prescaler

• Input Capture with Noise Canceler

Preliminary

• External Event Counter

• 3-Output Compare or 16-Bit PWM Output

• Output Compare Modulation

– 8-channel, 10-bit SAR ADC

• 8 Single-ended Channels

• 7 Differential Channels

• 2 Differential Channels With Programmable Gain at 1x, 10x, or 200x

– On-chip Analog Comparator

– Byte-oriented Two-wire Serial Interface

– Dual Programmable Serial USART

– Master/Slave SPI Serial Interface

• Programming Flash (Hardware ISP)

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– 8 External Interrupt Sources

– 5 Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down & Standby

– Software Selectable Clock Frequency

– Global Pull-up Disable

• I/O and Packages

– 53 Programmable I/O Lines

– 64-lead TQFP and 64-lead QFN

• Operating Voltages

– 2.7 - 5.5V

• Operating temperature

– Industrial (-40°C to +85°C)

• Maximum Frequency

– 8 MHz at 2.7V - Industrial range

– 16 MHz at 4.5V - Industrial range

Rev. 7538B–CAN–05/06

2. Description

2.1

Comparison Between AT90CAN32/64 and AT90CAN128

AT90CAN32/64 is hardware and software compatible with AT90CAN128, the only difference is

the memory size.

Table 2-1.

Device

Memory Size Summary

Flash

EEPROM

1K Byte

2K Bytes

4K Byte

RAM

AT90CAN32

AT90CAN64

AT90CAN128

32K Bytes

2K Bytes

4K Bytes

64K Bytes

128K Bytes

2.2

Part Desription

The AT90CAN32/64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the

AT90CAN32/64 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The AT90CAN32/64 provides the following features: 32K/64K bytes of In-System Programmable

Flash with Read-While-Write capabilities, 1K/2K bytes EEPROM, 2K/4K bytes SRAM, 53 gen-

eral purpose I/O lines, 32 general purpose working registers, a CAN controller, Real Time

Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte

oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differential input stage

with programmable gain, a programmable Watchdog Timer with Internal Oscillator, an SPI serial

port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip

Debug system and programming and five software selectable power saving modes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports and

interrupt system to continue functioning. The Power-down mode saves the register contents but

freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware

Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main-

tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops

the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise

during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the

rest of the device is sleeping. This allows very fast start-up combined with low power

consumption.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

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7538B–CAN–05/06

AT90CAN32/64

the Atmel AT90CAN32/64 is a powerful microcontroller that provides a highly flexible and cost

effective solution to many embedded control applications.

The AT90CAN32/64 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula-

tors, and evaluation kits.

2.3

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

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7538B–CAN–05/06

2.4

Block Diagram

Figure 2-1. Block Diagram

PF7 - PF0

PA7 - PA0

PC7 - PC0

VCC

GND

PORTA DRIVERS

PORTF DRIVERS

PORTC DRIVERS

DATA REGISTER

PORTF

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

DATA REGISTER

PORTC

DATA DIR.

REG. PORTC

8-BIT DATA BUS

POR - BOD

RESET

INTERNAL

OSCILLATOR

AVCC

CALIB. OSC

ADC

AGND

AREF

OSCILLATOR

WATCHDOG

TIMER

PROGRAM

COUNTER

STACK

POINTER

JTAG TAP

CAN

CONTROLLER

TIMING AND

CONTROL

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

ON-CHIP DEBUG

BOUNDARY-

SCAN

INSTRUCTION

REGISTER

TIMER/

COUNTERS

GENERAL

PURPOSE

REGISTERS

X

Y

Z

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

TWO-WIRE SERIAL

INTERFACE

USART0

SPI

USART1

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

DATA REG. DATA DIR.

PORTG

REG. PORTG

PORTB DRIVERS

PORTD DRIVERS

PORTG DRIVERS

PORTE DRIVERS

PE7 - PE0

PB7 - PB0

PD7 - PD0

PG4 - PG0

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AT90CAN32/64

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AT90CAN32/64

2.5

Pin Configurations

Figure 2-2. Pinout AT90CAN32/64 - TQFP

NC⁽¹⁾

(RXD0 / PDI) PE0

(TXD0 / PDO) PE1

(XCK0 / AIN0) PE2

(OC3A / AIN1) PE3

(OC3B / INT4) PE4

(OC3C / INT5) PE5

(T3 / INT6) PE6

1

2

3

48 PA3 (AD3)

47

PA4 (AD4)

INDEX CORNER

46 PA5 (AD5)

45 PA6 (AD6)

44 PA7 (AD7)

43 PG2 (ALE)

42 PC7 (A15 / CLKO)

41 PC6 (A14)

4

5

6

7

8

9

(64-lead TQFP top view)

40

39

PC5 (A13)

PC4 (A12)

(ICP3 / INT7) PE7

(SS) PB0 10

(SCK) PB1 11

(MOSI) PB2 12

38 PC3 (A11)

37 PC2 (A10)

36 PC1 (A9)

35 PC0 (A8)

34 PG1 (RD)

(MISO) PB3

13

(OC2A) PB4 14

(OC1A) PB5 15

(OC1B) PB6 16

33

PG0 (WR)

⁽¹⁾NC = Do not connect (May be used in future devices)

⁽²⁾Timer2 Oscillator

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7538B–CAN–05/06

Figure 2-3. Pinout AT90CAN32/64 - QFN

NC⁽¹⁾

1

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PG2 (ALE)

PC7 (A15 / CLKO)

PC6 (A14)

PC5 (A13)

PC4 (A12)

PC3 (A11)

PC2 (A10)

PC1 (A9)

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

(RXD0 / PDI) PE0

(TXD0 / PDO) PE1

(XCK0 / AIN0) PE2

(OC3A / AIN1) PE3

(OC3B / INT4) PE4

(OC3C / INT5) PE5

(T3 / INT6) PE6

(ICP3 / INT7) PE7

(SS) PB0

2

3

INDEX CORNER

4

5

6

7

8

9

(64-lead QFN top view)

10

11

12

13

14

15

16

(SCK) PB1

(MOSI) PB2

(MISO) PB3

(OC2A) PB4

PC0 (A8)

(OC1A) PB5

PG1 (RD)

(OC1B) PB6

PG0 (WR)

⁽¹⁾NC = Do not connect (May be used in future devices)

⁽²⁾Timer2 Oscillator

2.6

Pin Descriptions

2.6.1

VCC

Digital supply voltage.

2.6.2

2.6.3

GND

Ground.

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

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AT90CAN32/64

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the AT90CAN32/64 as listed on

page 74.

2.6.4

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the AT90CAN32/64 as listed on

page 76.

2.6.5

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of special features of the AT90CAN32/64 as listed on page 78.

2.6.6

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the AT90CAN32/64 as listed on

page 80.

2.6.7

Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port E also serves the functions of various special features of the AT90CAN32/64 as listed on

page 83.

2.6.8

Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port F pins

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that are externally pulled low will source current if the pull-up resistors are activated. The Port F

pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-

up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

2.6.9

Port G (PG4..PG0)

Port G is a 5-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output

buffers have symmetrical drive characteristics with both high sink and source capability. As

inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are

activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock

is not running.

Port G also serves the functions of various special features of the AT90CAN32/64 as listed on

page 88.

2.6.10

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteed

to generate a reset. The I/O ports of the AVR are immediately reset to their initial state even if

the clock is not running. The clock is needed to reset the rest of the AT90CAN32/64.

2.6.11

2.6.12

2.6.13

XTAL1

XTAL2

AVCC

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally con-

nected to V_CC, even if the ADC is not used. If the ADC is used, it should be connected to V_CC

through a low-pass filter.

2.6.14

AREF

This is the analog reference pin for the A/D Converter.

3. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

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AT90CAN32/64

4. AVR CPU Core

4.1

Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

4.2

Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Flash

Program

Memory

Interrupt

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

SPI

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

I/O Module 2

I/O Module n

Data

SRAM

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the program memory. This concept enables instructions to be executed

in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

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7538B–CAN–05/06

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the

Application Program section. Both sections have dedicated Lock bits for write and read/write

protection. The SPM (Store Program Memory) instruction that writes into the Application Flash

memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher is the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F. In addition, the

AT90CAN32/64 has Extended I/O space from 0x60 - 0xFF in SRAM where only the

ST/STS/STD and LD/LDS/LDD instructions can be used.

4.3

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set Summary” section for a detailed description.

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AT90CAN32/64

4.4

Status Register

The Status Register contains information about the result of the most recently executed arith-

metic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using the

dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

SREG

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set to enabled the interrupts. The individual interrupt

enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

^{• Bit 4 – S: Sign Bit, S = N}⊕ V

The S-bit is always an EXCLUSIVE OR between the negative flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

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• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

4.5

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

7

0

Addr.

R0

R1

0x00

0x01

0x02

R2

…

R13

R14

R15

R16

R17

…

0x0D

0x0E

0x0F

0x10

0x11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organization provides great flexibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

4.5.1

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 4-3.

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AT90CAN32/64

Figure 4-3. The X-, Y-, and Z-registers

15

XH

XL

0

X-register

7

0

7

R27 (0x1B)

R26 (0x1A)

15

YH

YL

ZL

0

Y-register

Z-register

7

R29 (0x1D)

R28 (0x1C)

15

ZH

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the instruction set reference for details).

4.5.2

Extended Z-pointer Register for ELPM/SPM – RAMPZ

Bit

7

6

5

4

–

3

–

2

–

1

–

0

RAMPZ0

R/W

–

RAMPZ

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bits 7..1 – Res: Reserved Bits

These bits are reserved for future use and will always read as zero. For compatibility with future

devices, be sure to write to write them to zero.

• Bit 0 – RAMPZ0: Extended RAM Page Z-pointer

The RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z-

pointer. As the AT90CAN32/64 does not support more than 64K of SRAM memory, this register

is used only to select which page in the program memory is accessed when the ELPM/SPM

instruction is used. The different settings of the RAMPZ0 bit have the following effects:

RAMPZ0 = 0: Program memory address 0x0000 - 0x7FFF (lower 64K bytes) is accessed by

ELPM/SPM

RAMPZ0 = 1: Program memory address 0x8000 - 0xFFFF (higher 64K bytes) is accessed by

ELPM/SPM

– AT90CAN32: RAMPZ0 exists as register bit but is not used for program memory

addressing.

– AT90CAN64: RAMPZ0 exists as register bit but is not used for program memory

addressing.

Figure 4-4. The Z-pointer used by ELPM and SPM

Bit (Individually)

7

0

7

0

8

7

0

RAMPZ

ZH

ZL

Bit (Z-pointer)

23

16 15

Note that LPM (different of ELPM) is never affected by the RAMPZ setting.

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7538B–CAN–05/06

4.6

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above 0xFF. The Stack Pointer is decremented by one when data is pushed onto the Stack

with the PUSH instruction, and it is decremented by two when the return address is pushed onto

the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is

popped from the Stack with the POP instruction, and it is incremented by two when data is

popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

Bit

15

SP15

SP7

7

14

SP14

SP6

6

13

SP13

SP5

5

12

SP12

SP4

4

11

SP11

SP3

3

10

SP10

SP2

2

9

SP9

SP1

1

8

SP8

SP0

0

SPH

SPL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

4.7

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 4-5. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clk_CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

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AT90CAN32/64

Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 4-6. Single Cycle ALU Operation

T1

T2

T3

T4

clk_CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

4.8

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate program vector in the program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt. Depending on the Program

Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12

are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 335 for details.

The lowest addresses in the program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 60. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL

bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 60 for more information.

The Reset Vector can also be moved to the start of the Boot Flash section by programming the

BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page

320.

4.8.1

Interrupt Behavior

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector

in order to execute the interrupt handling routine, and hardware clears the corresponding inter-

rupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be

cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,

the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared

by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable

bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global

Interrupt Enable bit is set, and will then be executed by order of priority.

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The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence.

Assembly Code Example

in

r16, SREG

; store SREG value

cli

sbi

out

; disable interrupts during timed sequence

EECR, EEMWE ; start EEPROM write

EECR, EEWE

SREG, r16

; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG;

/* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG;

/* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

Assembly Code Example

sei

; set Global Interrupt Enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI();

/* set Global Interrupt Enable */

_SLEEP();

/* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

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AT90CAN32/64

4.8.2

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the program vector address for the actual interrupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased by four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

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5. Memories

This section describes the different memories in the AT90CAN32/64. The AVR architecture has

two main memory spaces, the Data Memory and the Program Memory space. In addition, the

AT90CAN32/64 features an EEPROM Memory for data storage. All three memory spaces are

linear and regular.

Table 5-1.

Memory Mapping.

Memory

Mnemonic

Flash size

-

AT90CAN32

AT90CAN64

64 K bytes

0x00000

AT90CAN128⁽³⁾

Size

32 K bytes

128 K bytes

Start Address

Flash

0x07FFF⁽¹⁾

0x3FFF⁽²⁾

0x0FFFF⁽¹⁾

0x7FFF⁽²⁾

0x1FFFF⁽¹⁾

0xFFFF⁽²⁾

End Address

Flash end

Size

-

32 bytes

0x0000

32

Registers

Start Address

End Address

Size

-

0x001F

-

64 bytes

0x0020

I/O

Start Address

End Address

Size

-

Registers

-

0x005F

-

160 bytes

0x0060

Ext I/O

Start Address

End Address

Size

-

Registers

-

0x00FF

4 K bytes

0x0100

ISRAM size

ISRAM start

ISRAM end

XMem size

XMem start

XMem end

E2 size

-

2 K bytes

0x08FF

0x0900

4 K bytes

0x10FF

0x1100

Internal

SRAM

Start Address

End Address

Size

0x10FF

0-64 K bytes

0x1100

External

Memory

Start Address

End Address

Size

0xFFFF

2 K bytes

0x0000

1 K bytes

0x03FF

4 K bytes

0x0FFF

Start Address

End Address

EEPROM

E2 end

0x07FF

Notes: 1. Byte address.

2. Word (16-bit) address.

3. For information only.

5.1

In-System Reprogrammable Flash Program Memory

The AT90CAN32/64 contains On-chip In-System Reprogrammable Flash memory for program

storage (see “Flash size”). Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-

nized as 16 bits wide. For software security, the Flash Program memory space is divided into

two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The AT90CAN32/64

Program Counter (PC) address the program memory locations. The operation of Boot Program

section and associated Boot Lock bits for software protection are described in detail in “Boot

Loader Support – Read-While-Write Self-Programming” on page 320. “Memory Programming”

on page 335 contains a detailed description on Flash data serial downloading using the SPI pins

or the JTAG interface.

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AT90CAN32/64

Constant tables can be allocated within the entire program memory address space (see the

LPM – Load Program Memory and ELPM – Extended Load Program Memory instruction

description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 14.

Figure 5-1. Program Memory Map

Program Memory

0x0000

Application Flash Section

Boot Flash Section

Flash end

5.2

SRAM Data Memory

Figure 5-2 shows how the AT90CAN32/64 SRAM Memory is organized.

The AT90CAN32/64 is a complex microcontroller with more peripheral units than can be sup-

ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the

Extended I/O space in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower data memory locations address both the Register File, the I/O memory, Extended I/O

memory, and the internal data SRAM. The first 32 locations address the Register File, the next

64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next

locations address the internal data SRAM (see “ISRAM size”).

An optional external data SRAM can be used with the AT90CAN32/64. This SRAM will occupy

an area in the remaining address locations in the 64K address space. This area starts at the

address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM

occupies the lowest bytes, so when using 64 KB (65,536 bytes) of External Memory,

“XMem size” bytes of External Memory are available. See “External Memory Interface” on page

27 for details on how to take advantage of the external memory map.

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5.2.1

SRAM Data Access

When the addresses accessing the SRAM memory space exceeds the internal data memory

locations, the external data SRAM is accessed using the same instructions as for the internal

data memory access. When the internal data memories are accessed, the read and write strobe

pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is

enabled by setting the SRE bit in the XMCRA Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the

internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP

take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine

calls and returns take three clock cycles extra because the two-byte program counter is pushed

and popped, and external memory access does not take advantage of the internal pipe-line

memory access. When external SRAM interface is used with wait-state, one-byte external

access takes two, three, or four additional clock cycles for one, two, and three wait-states

respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles

more than specified in the instruction set manual for one, two, and three wait-states.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and

the “ISRAM size” bytes of internal data SRAM in the AT90CAN32/64 are all accessible through

all these addressing modes. The Register File is described in “General Purpose Register File”

on page 12.

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AT90CAN32/64

Figure 5-2. Data Memory Map

Data Memory

0x0000 - 0x001F

32 Registers

64 I/O Registers

160 Ext I/O Reg.

0x0020 - 0x005F

0x0060 - 0x00FF

ISRAM start

Internal SRAM

(ISRAM size)

ISRAM end

XMem start

External SRAM

(XMem size)

0xFFFF

5.2.2

SRAM Data Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk_CPUcycles as described in Figure 5-3.

Figure 5-3. On-chip Data SRAM Access Cycles

T1

T2

T3

clk_CPU

Address valid

Compute Address

Address

Data

WR

Data

RD

Memory Access Instruction

Next Instruction

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5.3

EEPROM Data Memory

The AT90CAN32/64 contains EEPROM memory (see “E2 size”). It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an endurance of at

least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described

in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and

the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

“SPI Serial Programming Overview” on page 347, “JTAG Programming Overview” on page 351,

and “Parallel Programming Overview” on page 338 respectively.

5.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 5-2. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, V_CCis likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See “Preventing EEPROM Corruption” on page 26.for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

5.3.2

The EEPROM Address Registers – EEARH and EEARL

Bit

15

14

13

12

11

EEAR11

EEAR3

3

10

EEAR10

EEAR2

2

9

EEAR9

EEAR1

1

8

EEAR8

EEAR0

0

–

EEARH

EEAR7

EEAR6

EEAR5

EEAR4

EEARL

7

R

6

R

5

R

4

R

Read/Write

Initial Value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

0

R/W

0

R/W

0

R/W

0

X

• Bits 15..12 – Reserved Bits

These bits are reserved bits in the AT90CAN32/64 and will always read as zero.

• Bits 11..0 – EEAR11..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the

EEPROM space (see “E2 size”). The EEPROM data bytes are addressed linearly between 0

and “E2 end”. The initial value of EEAR is undefined. A proper value must be written before the

EEPROM may be accessed.

– AT90CAN32: EEAR11 & EEAR10 exist as register bit but are not used for addressing.

– AT90CAN64: EEAR11 exists as register bit but is not used for addressing.

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AT90CAN32/64

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AT90CAN32/64

5.3.3

The EEPROM Data Register – EEDR

Bit

7

EEDR7

R/W

0

6

EEDR6

R/W

0

5

EEDR5

R/W

0

4

EEDR4

R/W

0

3

EEDR3

R/W

0

2

EEDR2

R/W

0

1

0

EEDR1

R/W

0

EEDR0

R/W

0

EEDR

Read/Write

Initial Value

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

5.3.4

The EEPROM Control Register – EECR

Bit

7

6

5

–

4

–

3

EERIE

R/W

0

2

EEMWE

R/W

0

1

EEWE

R/W

X

0

EERE

R/W

0

–

EECR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bits 7..4 – Reserved Bits

These bits are reserved bits in the AT90CAN32/64 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.

When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at

the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has

been written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEWE bit must be written to one to write the value into the

EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-

erwise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Mem-

ory Control and Status Register) becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the

Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader

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7538B–CAN–05/06

Support – Read-While-Write Self-Programming” on page 320 for details about Boot

programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is

interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the

interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared

during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,

the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 5-2 lists the typical pro-

gramming time for EEPROM access from the CPU.

Table 5-2.

Symbol

EEPROM Programming Time.

Number of Calibrated RC Oscillator Cycles Typ Programming Time

67 584 8.5 ms

EEPROM write (from CPU)

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AT90CAN32/64

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glo-

bally) so that no interrupts will occur during execution of these functions. The examples also

assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic

rjmp

EECR,EEWE

EEPROM_write

; Set up address (r18:r17) in address register

out

EEARH, r18

EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi

ret

EECR,EEWE

C Code Example

void EEPROM_write (unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE));

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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7538B–CAN–05/06

The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic

rjmp

EECR,EEWE

EEPROM_read

; Set up address (r18:r17) in address register

out

EEARH, r18

EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in

r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE));

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

5.3.5

Preventing EEPROM Corruption

During periods of low V_CC,the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V_CCreset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

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AT90CAN32/64

5.4

I/O Memory

The I/O space definition of the AT90CAN32/64 is shown in “Register Summary” on page 404.

All AT90CAN32/64 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O registers within the address range

0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

instruction set section for more details. When using the I/O specific commands IN and OUT, the

I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using

LD and ST instructions, 0x20 must be added to these addresses. The AT90CAN32/64 is a com-

plex microcontroller with more peripheral units than can be supported within the 64 location

reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -

0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other

AVR’s, the CBI and SBI instructions will only operate on the specified bit, and can therefore be

used on registers containing such status flags. The CBI and SBI instructions work with registers

0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

5.5

External Memory Interface

With all the features the External Memory Interface provides, it is well suited to operate as an

interface to memory devices such as External SRAM and Flash, and peripherals such as LCD-

display, A/D, and D/A. The main features are:

• Four different wait-state settings (including no wait-state).

• Independent wait-state setting for different extErnal Memory sectors (configurable sector

size).

• The number of bits dedicated to address high byte is selectable.

• Bus keepers on data lines to minimize current consumption (optional).

5.5.1

Overview

When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM

becomes available using the dedicated External Memory pins (see Figure 2-2 on page 5, Table

10-3 on page 74, Table 10-9 on page 78, and Table 10-21 on page 88). The memory configura-

tion is shown in Figure 5-4.

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7538B–CAN–05/06

Figure 5-4. External Memory with Sector Select

0x0000

Internal memory

ISRAM end

XMem start

Lower sector

SRW01

SRW00

SRL[2..0]

External Memory

(0-64K x 8)

Upper sector

SRW11

SRW10

0xFFFF

5.5.2

Using the External Memory Interface

The interface consists of:

• AD7:0: Multiplexed low-order address bus and data bus.

• A15:8: High-order address bus (configurable number of bits).

• ALE: Address latch enable.

• RD: Read strobe.

• WR: Write strobe.

The control bits for the External Memory Interface are located in two registers, the External

Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.

When the XMEM interface is enabled, the XMEM interface will override the setting in the data

direction registers that corresponds to the ports dedicated to the XMEM interface. For details

about the port override, see the alternate functions in section “I/O-Ports” on page 66. The XMEM

interface will auto-detect whether an access is internal or external. If the access is external, the

XMEM interface will output address, data, and the control signals on the ports according to Fig-

ure 5-6 (this figure shows the wave forms without wait-states). When ALE goes from high-to-low,

there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface

is enabled, also an internal access will cause activity on address, data and ALE ports, but the

RD and WR strobes will not toggle during internal access. When the External Memory Interface

is disabled, the normal pin and data direction settings are used. Note that when the XMEM inter-

face is disabled, the address space above the internal SRAM boundary is not mapped into the

internal SRAM. Figure 5-5 illustrates how to connect an external SRAM to the AVR using an

octal latch (typically “74x573” or equivalent) which is transparent when G is high.

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AT90CAN32/64

5.5.3

Address Latch Requirements

Due to the high-speed operation of the XRAM interface, the address latch must be selected with

care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-

tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The

External Memory Interface is designed in compliance to the 74AHC series latch. However, most

latches can be used as long they comply with the main timing parameters. The main parameters

for the address latch are:

• D to Q propagation delay (t_PD).

• Data setup time before G low (t_SU).

• Data (address) hold time after G low (_TH).

The External Memory Interface is designed to guaranty minimum address hold time after G is

asserted low of t_h= 5 ns. Refer to t_{LAXX_LD}/t_{LLAXX_ST}in “Memory Programming” Tables 27-7

through Tables 27-14. The D-to-Q propagation delay (t_PD) must be taken into consideration

when calculating the access time requirement of the external component. The data setup time

before G low (t_SU) must not exceed address valid to ALE low (t_AVLLC) minus PCB wiring delay

(dependent on the capacitive load).

Figure 5-5. External SRAM Connected to the AVR

D[7:0]

AD7:0

ALE

D

G

Q

A[7:0]

SRAM

A[15:8]

AVR

A15:8

RD

WR

5.5.4

Pull-up and Bus-keeper

The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to

one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by

writing the Port register to zero before entering sleep.

The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-

abled and enabled in software as described in “External Memory Control Register B – XMCRB”

on page 33. When enabled, the bus-keeper will ensure a defined logic level (zero or one) on the

AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.

5.5.5

Timing

External Memory devices have different timing requirements. To meet these requirements, the

AT90CAN32/64 XMEM interface provides four different wait-states as shown in Table 5-4. It is

important to consider the timing specification of the External Memory device before selecting the

wait-state. The most important parameters are the access time for the external memory com-

pared to the set-up requirement of the AT90CAN32/64. The access time for the External

Memory is defined to be the time from receiving the chip select/address until the data of this

29

7538B–CAN–05/06

address actually is driven on the bus. The access time cannot exceed the time from the ALE

pulse must be asserted low until data is stable during a read sequence (see t_LLRL+ t_RLRH- t_DVRH

in Tables 27-7 through Tables 27-14). The different wait-states are set up in software. As an

additional feature, it is possible to divide the external memory space in two sectors with individ-

ual wait-state settings. This makes it possible to connect two different memory devices with

different timing requirements to the same XMEM interface. For XMEM interface timing details,

please refer to Tables 27-7 through Tables 27-14 and Figure 27-6 to Figure 27-9 in the “External

Data Memory Characteristics” on page 374.

Note that the XMEM interface is asynchronous and that the waveforms in the following figures

are related to the internal system clock. The skew between the internal and external clock

(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-

quently, the XMEM interface is not suited for synchronous operation.

Figure 5-6. External Data Memory Cycles no Wait-state (SRWn1=0 and SRWn0=0)⁽¹⁾

T1

T2

T3

T4

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Address

Data

XXXXX

XXXXXXXX

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction

accesses the RAM (internal or external).

Figure 5-7. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1⁽¹⁾

T1

T2

T3

T4

T5

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Data

Address

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AT90CAN32/64

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal

or external).

Figure 5-8. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0⁽¹⁾

T1

T2

T3

T4

T5

T6

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Data

Address

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal

or external).

Figure 5-9. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1⁽¹⁾

T1

T2

T3

T4

T5

T6

T7

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Data

Address

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal

or external).

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5.5.6

External Memory Control Register A – XMCRA

Bit

7

6

SRL2

R/W

0

5

SRL1

R/W

0

4

SRL0

R/W

0

3

SRW11

R/W

0

2

SRW10

R/W

0

1

SRW01

R/W

0

SRW00

R/W

0

SRE

R/W

0

XMCRA

Read/Write

Initial Value

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,

ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin

direction settings in the respective data direction registers. Writing SRE to zero, disables the

External Memory Interface and the normal pin and data direction settings are used. Note that

when the XMEM interface is disabled, the address space above the internal SRAM boundary is

not mapped into the internal SRAM.

• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit

It is possible to configure different wait-states for different External Memory addresses. The

external memory address space can be divided in two sectors that have separate wait-state bits.

The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 5-3 and Figure 5-4. By

default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address

space is treated as one sector. When the entire SRAM address space is configured as one sec-

tor, the wait-states are configured by the SRW11 and SRW10 bits.

Table 5-3.

SRL2

Sector limits with different settings of SRL2..0

SRL1

SRL0

Sector

Lower sector

Addressing

N/A

0

1

0

Upper sector

Lower sector

Upper sector

Lower sector

Upper sector

Lower sector

Upper sector

Lower sector

Upper sector

Lower sector

Upper sector

Lower sector

Upper sector

Lower sector

Upper sector

“XMem start”⁽¹⁾- 0xFFFF

“XMem start”⁽¹⁾- 0x1FFF

0x2000 - 0xFFFF

0

1

0

1

0

1

0

1

0

1

“XMem start”⁽¹⁾- 0x3FFF

0x4000 - 0xFFFF

“XMem start”⁽¹⁾- 0x5FFF

0x6000 - 0xFFFF

“XMem start”⁽¹⁾- 0x7FFF

0x8000 - 0xFFFF

“XMem start”⁽¹⁾- 0x9FFF

0xA000 - 0xFFFF

“XMem start”⁽¹⁾- 0xBFFF

0xC000 - 0xFFFF

“XMem start”⁽¹⁾- 0xDFFF

0xE000 - 0xFFFF

Note:

1. See Table 5-1 on page 18 for “XMem start” setting.

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AT90CAN32/64

• Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector

The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-

nal memory address space, see Table 5-4.

• Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector

The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-

nal memory address space, see Table 5-4.

Table 5-4.

Wait States⁽¹⁾

SRWn1

SRWn0 Wait States

0

1

0

1

0

No wait-states

Wait one cycle during read/write strobe

Wait two cycles during read/write strobe

Wait two cycles during read/write and wait one cycle before driving out new

address

1

Note:

1. n = 0 or 1 (lower/upper sector).

For further details of the timing and wait-states of the External Memory Interface, see Figures

5-6 through Figures 5-9 for how the setting of the SRW bits affects the timing.

5.5.7

External Memory Control Register B – XMCRB

Bit

7

XMBK

R/W

0

6

–

5

–

4

–

3

–

2

XMM2

R/W

0

1

XMM1

R/W

0

XMM0

R/W

0

XMCRB

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 7– XMBK: External Memory Bus-keeper Enable

Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is

enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise

be tri-stated. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so

even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is

one.

• Bit 6..4 – Reserved Bits

These are reserved bits and will always read as zero. When writing to this address location,

write these bits to zero for compatibility with future devices.

• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask

When the External Memory is enabled, all Port C pins are default used for the high address byte.

If the full address space is not required to access the External Memory, some, or all, Port C pins

can be released for normal Port Pin function as described in Table 5-5. As described in “Using

all 64KB Locations of External Memory” on page 35, it is possible to use the XMMn bits to

access all 64KB locations of the External Memory.

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Table 5-5.

Port C Pins Released as Normal Port Pins when the External Memory is Enabled

XMM2

XMM1

XMM0

# Bits for External Memory Address

Released Port Pins

None

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8 (Full External Memory Space)

7

PC7

6

PC7 .. PC6

PC7 .. PC5

PC7 .. PC4

PC7 .. PC3

PC7 .. PC2

Full Port C

5

4

3

2

No Address high bits

5.5.8

Using all Locations of External Memory Smaller than 64 KB

Since the external memory is mapped after the internal memory as shown in Figure 5-4, the

external memory is not addressed when addressing the first “ISRAM size” bytes of data space. It

may appear that the first “ISRAM size” bytes of the external memory are inaccessible (external

memory addresses 0x0000 to “ISRAM end”). However, when connecting an external memory

smaller than 64 KB, for example 32 KB, these locations are easily accessed simply by address-

ing from address 0x8000 to “ISRAM end + 0x8000”. Since the External Memory Address bit A15

is not connected to the external memory, addresses 0x8000 to “ISRAM end + 0x8000” will

appear as addresses 0x0000 to “ISRAM end” for the external memory. Addressing above

address “ISRAM end + 0x8000” is not recommended, since this will address an external mem-

ory location that is already accessed by another (lower) address. To the Application software,

the external 32 KB memory will appear as one linear 32 KB address space from “XMem start” to

“XMem start + 0x8000”. This is illustrated in Figure 5-10.

Figure 5-10. Address Map with 32 KB External Memory

AVR Memory Map

External 32K SRAM (Size=0x8000)

0x0000

Internal Memory

ISRAM end

XMem start

ISRAM end

XMem start

External Memory

0x7FFF

0x8000

0x7FFF

ISRAM end + 0x8000

XMem start + 0x8000

(Unused)

0xFFFF

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AT90CAN32/64

5.5.9

Using all 64KB Locations of External Memory

Since the External Memory is mapped after the Internal Memory as shown in Figure 5-4, only

(64K-(“ISRAM size”+256)) bytes of External Memory is available by default (address space

0x0000 to “ISRAM end” is reserved for internal memory). However, it is possible to take advan-

tage of the entire External Memory by masking the higher address bits to zero. This can be done

by using the XMMn bits and control by software the most significant bits of the address. By set-

ting Port C to output 0x00, and releasing the most significant bits for normal Port Pin operation,

the Memory Interface will address 0x0000 - 0x1FFF. See the following code examples.

Assembly Code Example⁽¹⁾

; OFFSET is defined to 0x2000 to ensure

; external memory access

; Configure Port C (address high byte) to

; output 0x00 when the pins are released

; for normal Port Pin operation

ldi

out

ldi

out

r16, 0xFF

DDRC, r16

r16, 0x00

PORTC, r16

; release PC7:5

ldi

sts

r16, (1<<XMM1)|(1<<XMM0)

XMCRB, r16

; write 0xAA to address 0x0001 of external

; memory

ldi

sts

r16, 0xaa

0x0001+OFFSET, r16

; re-enable PC7:5 for external memory

ldi

sts

r16, (0<<XMM1)|(0<<XMM0)

XMCRB, r16

; store 0x55 to address (OFFSET + 1) of

; external memory

ldi

sts

r16, 0x55

0x0001+OFFSET, r16

C Code Example⁽¹⁾

#define OFFSET 0x2000

void XRAM_example(void)

{

unsigned char *p = (unsigned char *) (OFFSET + 1);

DDRC = 0xFF;

PORTC = 0x00;

XMCRB = (1<<XMM1) | (1<<XMM0);

*p = 0xaa;

XMCRB = 0x00;

*p = 0x55;

}

Note:

1. The example code assumes that the part specific header file is included.

Care must be exercised using this option as most of the memory is masked away.

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5.6

General Purpose I/O Registers

The AT90CAN32/64 contains three General Purpose I/O Registers. These registers can be

used for storing any information, and they are particularly useful for storing global variables and

status flags.

The General Purpose I/O Register 0, within the address range 0x00 - 0x1F, is directly bit-acces-

sible using the SBI, CBI, SBIS, and SBIC instructions.

5.6.1

5.6.2

5.6.3

General Purpose I/O Register 2 – GPIOR2

Bit

7

6

5

4

3

2

1

0

GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00

GPIOR2

GPIOR1

GPIOR0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

General Purpose I/O Register 1 – GPIOR1

Bit

7

6

5

4

3

2

1

0

GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

General Purpose I/O Register 0 – GPIOR0

Bit

7

6

5

4

3

2

1

0

GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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AT90CAN32/64

6. System Clock

6.1

Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to unused

modules can be halted by using different sleep modes, as described in “Power Management and

Sleep Modes” on page 46. The clock systems are detailed below.

Figure 6-1. Clock Distribution

Asynchronous

Timer/Counter2

CAN

Controller

General I/O

Modules

Flash and

EEPROM

ADC

CPU Core

RAM

clk_ADC

clk_I/O

clk_CPU

AVR Clock

Control Unit

CLKO

clk_ASY

clk_FLASH

CKOUT Fuse

Reset Logic

Watchdog Timer

Source clock

Watchdog clock

Prescaler

Watchdog

Oscillator

Clock

Multiplexer

Timer/Counter2

External Clock

Timer/Counter2

Oscillator

Crystal

Oscillator

Low-frequency

Crystal Oscillator

Calibrated RC

Oscillator

External Clock

TOSC1

TOSC2

XTAL1

XTAL2

6.1.1

6.1.2

CPU Clock – clk_CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

I/O Clock – clk_I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, CAN,

USART. The I/O clock is also used by the External Interrupt module, but note that some external

interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the

I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchro-

nously when clk_I/Ois halted, enabling TWI address reception in all sleep modes.

6.1.3

Flash Clock – clk_FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

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7538B–CAN–05/06

6.1.4

6.1.5

Asynchronous Timer Clock – clk_ASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly

from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows

using this Timer/Counter as a real-time counter even when the device is in sleep mode.

ADC Clock – clk_ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

6.2

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Table 6-1.

Device Clocking Options Select⁽¹⁾

Device Clocking Option

External Crystal/Ceramic Resonator

External Low-frequency Crystal

Calibrated Internal RC Oscillator

External Clock

CKSEL3..0

1111 - 1000

0111 - 0100

0010

0000

Reserved

0011, 0001

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU

wakes up from Power-down or Power-save, the selected clock source is used to time the start-

up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts

from reset, there is an additional delay allowing the power to reach a stable level before starting

normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up

time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-2. The

frequency of the Watchdog Oscillator is voltage dependent as shown in “AT90CAN32/64 Typical

Characteristics” on page 383.

Table 6-2.

Typ Time-out (V_CC= 5.0V)

4.1 ms

65 ms

Number of Watchdog Oscillator Cycles

Typ Time-out (V_CC= 3.0V)

4.3 ms

69 ms

Number of Cycles

4K (4,096)

64K (65,536)

6.3

Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default

clock source setting is the Internal RC Oscillator with longest start-up time and an initial system

clock prescaling of 8. This default setting ensures that all users can make their desired clock

source setting using an In-System or Parallel programmer.

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AT90CAN32/64

6.4

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-

figured for use as an On-chip Oscillator, as shown in Figure 6-2. Either a quartz crystal or a

ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 6-3. For ceramic resonators, the capacitor values given by

the manufacturer should be used. For more information on how to choose capacitors and other

details on Oscillator operation, refer to the Multi-purpose Oscillator Application Note.

Figure 6-2. Crystal Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

The Oscillator can operate in three different modes, each optimized for a specific frequency

range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-3.

Table 6-3.

CKSEL3..1

Crystal Oscillator Operating Modes

Recommended Range for Capacitors C1 and

C2 for Use with Crystals (pF)

Frequency Range (MHz)

100⁽¹⁾

101

110

0.4 - 0.9

0.9 - 3.0

3.0 - 8.0

8.0 - 16.0

12 - 22

111

Note:

1. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

6-4.

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Table 6-4.

CKSEL0

Start-up Times for the Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

SUT1..0

Recommended Usage

(V_CC= 5.0V)

Ceramic resonator, fast

rising power

0

1

00

01

10

11

00

01

10

11

258 CK⁽¹⁾

1K CK⁽²⁾

16K CK

14CK + 4.1 ms

14CK + 65 ms

14CK

Ceramic resonator, slowly

rising power

Ceramic resonator, BOD

enabled

Ceramic resonator, fast

rising power

14CK + 4.1 ms

14CK + 65 ms

14CK

Ceramic resonator, slowly

rising power

Crystal Oscillator, BOD

enabled

Crystal Oscillator, fast

rising power

14CK + 4.1 ms

14CK + 65 ms

Crystal Oscillator, slowly

rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

6.5

Low-frequency Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal

Oscillator must be selected by setting the CKSEL Fuses to “0100”, “0101”, “0110”, or “0111”.

The crystal should be connected as shown in Figure 6-3.

Figure 6-3. Low-frequency Crystal Oscillator Connections

12 - 22 pF

XTAL2

32.768 KHz

XTAL1

12 - 22 pF

GND

12-22 pF capacitors may be necessary if the parasitic impedance (pads, wires & PCB) is very

low.

40

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

When this Oscillator is selected, start-up times are determined by the SUT1..0 fuses as shown in

Table 6-5 and CKSEL1..0 fuses as shown in Table 6-6.

Table 6-5.

Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1..0

00

Additional Delay from Reset (V_CC= 5.0V)

Recommended Usage

14CK

Fast rising power or BOD enabled

Slowly rising power

01

14CK + 4.1 ms

14CK + 65 ms

10

Stable frequency at start-up

11

Reserved

Table 6-6.

CKSEL3..0

Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

Start-up Time from

Recommended Usage

Power-down and Power-save

0100⁽¹⁾

0101

1K CK

32K CK

1K CK

Stable frequency at start-up

0110⁽¹⁾

0111

32K CK

Note:

1. These options should only be used if frequency stability at start-up is not important for the

application

6.6

Calibrated Internal RC Oscillator

The calibrated internal RC Oscillator provides a fixed 8.0 MHz clock. The frequency is nominal

value at 3V and 25°C. If 8 MHz frequency exceeds the specification of the device (depends on

_CC), the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 dur-

V

ing start-up. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock

Prescaler” on page 44. for more details. This clock may be selected as the system clock by pro-

gramming the CKSEL Fuses as shown in Table 6-7. If selected, it will operate with no external

components. During reset, hardware loads the calibration byte into the OSCCAL Register and

thereby automatically calibrates the RC Oscillator. At 5V and 25°C, this calibration gives a fre-

quency within 10% of the nominal frequency. Using calibration methods as described in

application notes available at www.atmel.com/avr it is possible to achieve 2% accuracy at any

given V^CCand temperature. When this Oscillator is used as the chip clock, the Watchdog Oscil-

lator will still be used for the Watchdog Timer and for the Reset Time-out. For more information

on the pre-programmed calibration value, see the section “Calibration Byte” on page 338.

Table 6-7.

Internal Calibrated RC Oscillator Operating Modes⁽¹⁾

CKSEL3..0

Nominal Frequency

8.0 MHz

0010

Note:

1. The device is shipped with this option selected.

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7538B–CAN–05/06

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-8.

SUT1..0

Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

Recommended Usage

00

01

6 CK

14CK

BOD enabled

14CK + 4.1 ms

14CK + 65 ms

Reserved

Fast rising power

Slowly rising power

10⁽¹⁾

11

Note:

1. The device is shipped with this option selected.

6.6.1

Oscillator Calibration Register – OSCCAL

Bit

7

–

6

5

4

3

2

1

0

CAL6

R/W

CAL5

R/W

CAL4

R/W

CAL3

R/W

CAL2

R/W

CAL1

R/W

CAL0

OSCCAL

Read/Write

Initial Value

R

0

R/W

<----- ------

Device Specific Calibration Value

------ ----->

• Bit 7 – Reserved Bit

This bit is reserved for future use.

• Bits 6..0 – CAL6..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the internal Oscillator to remove process vari-

ations from the Oscillator frequency. This is done automatically during Chip Reset. When

OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this regis-

ter will increase the frequency of the internal Oscillator. Writing 0x7F to the register gives the

highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash

access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal fre-

quency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for

calibration to 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 6-9.

Table 6-9.

Internal RC Oscillator Frequency Range.

Min Frequency in Percentage of

Max Frequency in Percentage of

Nominal Frequency

OSCCAL Value

Nominal Frequency

0x00

0x3F

0x7F

50%

75%

100%

150%

200%

100%

6.7

External Clock

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure

6-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

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AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 6-4. External Clock Drive Configuration

XTAL2

NC

External

Clock

Signal

XTAL1

GND

Table 6-10. External Clock Frequency

CKSEL3..0

Frequency Range

0 - 16 MHz

0000

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-11.

Table 6-11. Start-up Times for the External Clock Selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

SUT1..0

Recommended Usage

00

01

10

11

6 CK

14CK

BOD enabled

14CK + 4.1 ms

14CK + 65 ms

Reserved

Fast rising power

Slowly rising power

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the

MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

44 for details.

6.8

Clock Output Buffer

When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is

suitable when chip clock is used to drive other circuits on the system. The clock will be output

also during reset and the normal operation of I/O pin will be overridden when the fuse is pro-

grammed. Any clock source, including internal RC Oscillator, can be selected when CLKO

serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that

is output (CKOUT Fuse programmed).

6.9

Timer/Counter2 Oscillator

For AVR microcontrollers with Timer/Counter2 Oscillator pins (TOSC1 and TOSC2), the crystal

is connected directly between the pins. The Oscillator is optimized for use with a 32.768 kHz

watch crystal. 12-22 pF capacitors may be necessary if the parasitic impedance (pads, wires &

PCB) is very low.

43

7538B–CAN–05/06

AT90CAN32/64 share the Timer/Counter2 Oscillator Pins (TOSC1 and TOSC2) with PG4 and

PG3. This means that both PG4 and PG3 can only be used when the Timer/Counter2 Oscillator

is not enable.

Applying an external clock source to TOSC1 can be done in asynchronous operation if EXTCLK

in the ASSR Register is written to logic one. See “Asynchronous operation of the

Timer/Counter2” on page 159 for further description on selecting external clock as input instead

of a 32 kHz crystal. In this configuration, PG4 cannot be used but PG3 is available.

6.10 System Clock Prescaler

The AT90CAN32/64 system clock can be divided by setting the Clock Prescaler Register –

CLKPR. This feature can be used to decrease power consumption when the requirement for

processing power is low. This can be used with all clock source options, and it will affect the

clock frequency of the CPU and all synchronous peripherals. clk_I/O, clk_ADC, clk_CPU, and clk_FLASH

are divided by a factor as shown in Table 6-12.

6.10.1

Clock Prescaler Register – CLKPR

Bit

7

6

–

5

–

4

–

3

2

1

0

CLKPCE

CLKPS3 CLKPS2 CLKPS1 CLKPS0

R/W R/W R/W R/W

See Bit Description

CLKPR

Read/Write

Initial Value

R/W

0

R

0

R

0

R

0

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the

CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bit 6..0 – Reserved Bits

These bits are reserved for future use.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-12.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to

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7538B–CAN–05/06

AT90CAN32/64

“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock

source has a higher frequency than the maximum frequency of the device at the present operat-

ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8

Fuse setting. The Application software must ensure that a sufficient division factor is chosen if

the selected clock source has a higher frequency than the maximum frequency of the device at

the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

Table 6-12. Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

Reserved

Note:

When the system clock is divided, Timer/Counter2 can be used with Asynchronous clock only.

The frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled

down Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter2 regis-

ters may fail.

45

7538B–CAN–05/06

7. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides various sleep modes allowing the user to tailor the power consump-

tion to the application’s requirements.

To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a

SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select

which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be

activated by the SLEEP instruction. See Table 7-1 for a summary. If an enabled interrupt occurs

while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in

addition to the start-up time, executes the interrupt routine, and resumes execution from the

instruction following SLEEP. The contents of the register file and SRAM are unaltered when the

device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and exe-

cutes from the Reset Vector.

Figure 6-1 on page 37 presents the different clock systems in the AT90CAN32/64, and their dis-

tribution. The figure is helpful in selecting an appropriate sleep mode.

7.0.1

Sleep Mode Control Register – SMCR

The Sleep Mode Control Register contains control bits for power management.

Bit

7

–

6

–

5

–

4

–

3

2

1

0

SE

R/W

0

SM2

R/W

0

SM1

R/W

0

SM0

R/W

0

SMCR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 7..4 – Reserved Bits

These bits are reserved for future use.

• Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 7-1.

Table 7-1.

Sleep Mode Select

SM2

SM1

SM0

Sleep Mode

Idle

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ADC Noise Reduction

Power-down

Power-save

Reserved

Standby⁽¹⁾

Reserved

Note:

1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 1 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

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AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

7.1

Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing SPI, CAN, USART, Analog Comparator, ADC, Two-wire

Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This

sleep mode basically halts clk_CPUand clk_FLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

7.2

ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the

Two-wire Serial Interface address watch, Timer/Counter2, CAN and the Watchdog to continue

operating (if enabled). This sleep mode basically halts clk_I/O, clk_CPU, and clk_FLASH, while allowing

the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter2 interrupt, an

SPM/EEPROM ready interrupt, an External Level Interrupt on INT7:4, or an External Interrupt on

INT3:0 can wake up the MCU from ADC Noise Reduction mode.

7.3

Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the External Oscillator is stopped, while the External Interrupts, the

Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).

Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface

address match interrupt, an External Level Interrupt on INT7:4, or an External Interrupt on

INT3:0 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing

operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 93

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL fuses that define the

Reset Time-out period, as described in “Clock Sources” on page 38.

7.4

Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-

save mode. This mode is identical to Power-down, with one exception:

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7538B–CAN–05/06

If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2

will run during sleep. The device can wake up from either Timer Overflow or Output Compare

event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in

TIMSK2, and the global interrupt enable bit in SREG is set.

If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended

instead of Power-save mode because the contents of the registers in the asynchronous timer

should be considered undefined after wake-up in Power-save mode if AS2 is 0.

This sleep mode basically halts all clocks except clk_ASY, allowing operation only of asynchronous

modules, including Timer/Counter2 if clocked asynchronously.

7.5

Standby Mode

When the SM2..0 bits are 110 and an External Crystal/Resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in 6 clock cycles.

Table 7-2.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains

Oscillators

Wake-up Sources

Main

Timer

Osc.

Enabled

TWI

Address

Match

SPM/

Timer

Sleep

Mode

Clock

Source

Enabled

Other

I/O

clk_CPU

clk_FLASHclk_IOclk_ADCclk_ASY

INT7:0

EEPROM

2

ADC

Ready

Idle

X

X⁽²⁾

X

ADC Noise

Reduction

X⁽³⁾

X⁽²⁾

Power-

down

X⁽³⁾

X

Power-

save

X⁽²⁾

X⁽³⁾

X

X⁽²⁾

Standby⁽¹⁾

X

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If AS2 bit in ASSR is set.

3. Only INT3:0 or level interrupt INT7:4.

7.6

Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

mode should be selected so that as few as possible of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

7.6.1

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to “Analog to Digital Converter - ADC” on page

272 for details on ADC operation.

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AT90CAN32/64

7.6.2

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,

the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up

to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all

sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep

mode. Refer to “Analog Comparator” on page 268 for details on how to configure the Analog

Comparator.

7.6.3

7.6.4

Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned off. If

the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep

modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-

nificantly to the total current consumption. Refer to “Brown-out Detection” on page 54 for details

on how to configure the Brown-out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 56 for details on the start-up time.

7.6.5

7.6.6

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to “Watchdog Timer” on page 57 for details on how to configure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important is then to ensure that no pins drive resistive loads. In sleep modes where both

the I/O clock (clk_I/O) and the ADC clock (clk_ADC) are stopped, the input buffers of the device will

be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 70 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or have

an analog signal level close to V_CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V_CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to “Digital Input Disable Register 1 – DIDR1” on page 271 and “Digital Input Dis-

able Register 0 – DIDR0” on page 291 for details.

7.6.7

JTAG Interface and On-chip Debug System

If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the

main clock source is enabled, and hence, always consumes power. In the deeper sleep modes,

49

7538B–CAN–05/06

this will contribute significantly to the total current consumption. There are three alternative ways

to avoid this:

• Disable OCDEN Fuse.

• Disable JTAGEN Fuse.

• Write one to the JTD bit in MCUCR.

The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is

not shifting data. If the hardware connected to the TDO pin does not pull up the logic level,

power consumption will increase. Note that the TDI pin for the next device in the scan chain con-

tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCR register to one or

leaving the JTAG fuse unprogrammed disables the JTAG interface.

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8. System Control and Reset

8.1

Reset

8.1.1

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute

Jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at these

locations. This is also the case if the Reset Vector is in the Application section while the Interrupt

Vectors are in the Boot section or vice versa. The circuit diagram in Figure 8-1 shows the reset

logic. Table 8-1 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections for the delay period are presented in “Clock Sources” on page 38.

8.1.2

Reset Sources

The AT90CAN32/64 has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V_POT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer

than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V_CCis below the Brown-out

Reset threshold (V_BOT) and the Brown-out Detector is enabled.

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one

of the scan chains of the JTAG system. Refer to the section “Boundary-scan IEEE 1149.1

(JTAG)” on page 299 for details.

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7538B–CAN–05/06

Figure 8-1. Reset Logic

DATA BUS

MCU Status

Register (MCUSR)

Power-on Reset

Circuit

Brown-out

Reset Circuit

BODLEVEL [2..0]

Pull-up Resistor

Spike

Filter

JTAG Reset

Register

Watchdog

Oscillator

Delay Counters

Clock

Generator

CK

TIMEOUT

CKSEL[3:0]

SUT[1:0]

Table 8-1.

Symbol Parameter

Power-on Reset Threshold Voltage (rising)

Reset Characteristics

Condition

Min.

Typ.

Max.

Units

1.4

1.3

2.3

V

V_POT

Power-on Reset Threshold Voltage

(falling)⁽¹⁾

2.3

V

0.2

V_CC

0.85

V_CC

V_RST

RESET Pin Threshold Voltage

V

t_RST

Note:

Minimum pulse width on RESET Pin

Vcc = 5 V, temperature = 25 °C

400

ns

1. The Power-on Reset will not work unless the supply voltage has been below V_POT(falling)

8.1.3

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in Table 8-1. The POR is activated whenever V_CCis below the detection level. The

POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply

voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V_CCrise. The RESET signal is activated again, without any delay,

when V_CCdecreases below the detection level.

52

AT90CAN32/64

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AT90CAN32/64

Figure 8-2. MCU Start-up, RESET Tied to V_CC

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 8-3. MCU Start-up, RESET Extended Externally

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

8.1.4

External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the

minimum pulse width (see Table 8-1) will generate a reset, even if the clock is not running.

Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the

Reset Threshold Voltage – V_RST– on its positive edge, the delay counter starts the MCU after

the Time-out period – t_TOUT– has expired.

Figure 8-4. External Reset During Operation

CC

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7538B–CAN–05/06

8.1.5

Brown-out Detection

AT90CAN32/64 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V_CClevel

during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be

selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free

Brown-out Detection. The hysteresis on the detection level should be interpreted as V_BOT+

_BOT+ V_HYST/2 and V_BOT-= V_BOT- V_HYST/2.

=

V

Table 8-2.

BODLEVEL Fuse Coding⁽¹⁾

BODLEVEL 2..0 Fuses Min V_BOT

Typ V_BOT

Max V_BOT

Units

111

110

101

100

011

010

001

000

BOD Disabled

4.1

4.0

3.9

3.8

2.7

2.6

2.5

V

Note:

1. V_BOTmay be below nominal minimum operating voltage for some devices. For devices where

this is the case, the device is tested down to V_CC= V_BOTduring the production test. This guar-

antees that a Brown-Out Reset will occur before V_CCdrops to a voltage where correct

operation of the microcontroller is no longer guaranteed. The test is performed using

BODLEVEL = 010 for Low Operating Voltage and BODLEVEL = 101 for High Operating Volt-

age .

Table 8-3.

Symbol

V_HYST

Brown-out Characteristics

Parameter

Min.

Typ.

70

Max.

Units

mV

Brown-out Detector Hysteresis

Min Pulse Width on Brown-out Reset

t_BOD

2

µs

When the BOD is enabled, and V_CCdecreases to a value below the trigger level (V_BOT-in Figure

8-5), the Brown-out Reset is immediately activated. When V_CCincreases above the trigger level

(V_BOT+in Figure 8-5), the delay counter starts the MCU after the Time-out period t_TOUThas

expired.

The BOD circuit will only detect a drop in V_CCif the voltage stays below the trigger level for

longer than t_BODgiven in Table 8-1.

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AT90CAN32/64

Figure 8-5. Brown-out Reset During Operation

V

BOT+

CC

V

BOT-

RESET

t

TOUT

TIME-OUT

INTERNAL

RESET

8.1.6

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t_TOUT. Refer to

page 57 for details on operation of the Watchdog Timer.

Figure 8-6. Watchdog Reset During Operation

CC

CK

8.1.7

MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit

7

–

6

–

5

–

4

3

2

1

0

JTRF

R/W

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

Read/Write

Initial Value

R

0

R

0

R

0

See Bit Description

• Bit 7..5 – Reserved Bits

These bits are reserved for future use.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

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• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset flags to identify a reset condition, the user should read and then reset

the MCUSR as early as possible in the program. If the register is cleared before another reset

occurs, the source of the reset can be found by examining the reset flags.

8.2

Internal Voltage Reference

AT90CAN32/64 features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator or the ADC.

8.2.1

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in Table 8-4. To save power, the reference is not always turned on. The

reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

8.2.2

Voltage Reference Characteristics

Table 8-4.

Symbol

V_BG

t_BG

Internal Voltage Reference Characteristics

Parameter

Condition

Min.

Typ.

1.1

40

Max.

1.2

Units

V

Bandgap reference voltage

Bandgap reference start-up time

1.0

70

µs

Bandgap reference current

consumption

I_BG

15

µA

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8.3

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is

the typical value at V_CC= 5V. See characterization data for typical values at other V_CClevels. By

controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as

shown in Table 8-6 on page 58. The WDR – Watchdog Reset – instruction resets the Watchdog

Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.

Eight different clock cycle periods can be selected to determine the reset period. If the reset

period expires without another Watchdog Reset, the AT90CAN32/64 resets and executes from

the Reset Vector. For timing details on the Watchdog Reset, refer to Table 8-6 on page 58.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,

two different safety levels are selected by the fuse WDTON as shown in Table 8-5. Refer to

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 59 for

details.

Table 8-5.

WDTON

WDT Configuration as a Function of the Fuse Settings of WDTON

Safety

Level

WDT Initial

State

How to Disable

the WDT

How to Change

Time-out

Unprogrammed

Programmed

1

2

Disabled

Enabled

Timed sequence

Always enabled

Timed sequence

Figure 8-7. Watchdog Timer

WATCHDOG

OSCILLATOR

~1 MHz

8.3.1

Watchdog Timer Control Register – WDTCR

Bit

7

–

6

–

5

–

4

WDCE

R/W

0

3

2

1

WDP1

R/W

0

WDE

R/W

0

WDP2

R/W

0

WDP0

WDTCR

Read/Write

Initial Value

R

0

R

0

R

0

R/W

0

• Bits 7..5 – Reserved Bits

These bits are reserved bits for future use.

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not

be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the

description of the WDE bit for a Watchdog disable procedure. This bit must also be set when

57

7538B–CAN–05/06

changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the

Watchdog Timer” on page 59.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written

to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit

has logic level one. To disable an enabled Watchdog Timer, the following procedure must be

followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-

ten to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm

described above. See “Timed Sequences for Changing the Configuration of the Watchdog

Timer” on page 59.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-

dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods

are shown in Table 8-6.

Table 8-6.

WDP2

Watchdog Timer Prescale Select

Number of WDT

Oscillator Cycles

Typical Time-out at

V_CC= 5.0V

WDP1

WDP0

V

_CC= 3.0V

17.1 ms

34.3 ms

68.5 ms

0.14 s

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16K cycles

16.3 ms

32.5 ms

65 ms

0.13 s

0.26 s

0.52 s

1.0 s

32K cycles

64K cycles

32/64K cycles

256K cycles

512K cycles

1,024K cycles

2,048K cycles

0.27 s

0.55 s

1.1 s

2.2 s

2.1 s

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The following code example shows one assembly and one C function for turning off the WDT.

The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that

no interrupts will occur during execution of these functions.

Assembly Code Example⁽¹⁾

WDT_off:

; Write logical one to WDCE and WDE

ldi

sts

r16, (1<<WDCE)|(1<<WDE)

WDTCR, r16

; Turn off WDT

ldi

sts

ret

r16, (0<<WDE)

WDTCR, r16

C Code Example⁽¹⁾

void WDT_off(void)

{

/* Write logical one to WDCE and WDE */

WDTCR = (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

Note:

1. The example code assumes that the part specific header file is included.

8.4

Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuration differs slightly between the two safety levels. Separate

procedures are described for each level.

8.4.1

Safety Level 1

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit

to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out

period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or

changing the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-

ten to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits

as desired, but with the WDCE bit cleared.

8.4.2

Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A

timed sequence is needed when changing the Watchdog Time-out period. To change the

Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE

always is set, the WDE must be written to one to start the timed sequence.

2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,

but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

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7538B–CAN–05/06

9. Interrupts

This section describes the specifics of the interrupt handling as performed in AT90CAN32/64.

For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”

on page 15.

9.1

Interrupt Vectors in AT90CAN32/64

Table 9-1.

Reset and Interrupt Vectors

Vector

No.

Program

Source

Interrupt Definition

Address⁽¹⁾

External Pin, Power-on Reset, Brown-out Reset,

Watchdog Reset, and JTAG AVR Reset

1

0x0000⁽²⁾

RESET

2

0x0002

0x0004

0x0006

0x0008

0x000A

0x000C

0x000E

0x0010

0x0012

0x0014

0x0016

0x0018

0x001A

0x001C

0x001E

0x0020

0x0022

0x0024

0x0026

0x0028

0x002A

0x002C

0x002E

0x0030

0x0032

0x0034

0x0036

INT0

External Interrupt Request 0

External Interrupt Request 1

External Interrupt Request 2

External Interrupt Request 3

External Interrupt Request 4

External Interrupt Request 5

External Interrupt Request 6

External Interrupt Request 7

Timer/Counter2 Compare Match

Timer/Counter2 Overflow

3

INT1

4

INT2

5

INT3

6

INT4

7

INT5

8

INT6

9

INT7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

TIMER2 COMP

TIMER2 OVF

TIMER1 CAPT

TIMER1 COMPA

TIMER1 COMPB

TIMER1 COMPC

TIMER1 OVF

TIMER0 COMP

TIMER0 OVF

CANIT

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match A

Timer/Counter1 Compare Match B

Timer/Counter1 Compare Match C

Timer/Counter1 Overflow

Timer/Counter0 Compare Match

Timer/Counter0 Overflow

CAN Transfer Complete or Error

CAN Timer Overrun

OVRIT

SPI, STC

SPI Serial Transfer Complete

USART0, Rx Complete

USART0, RX

USART0, UDRE

USART0, TX

ANALOG COMP

ADC

USART0 Data Register Empty

USART0, Tx Complete

Analog Comparator

ADC Conversion Complete

EEPROM Ready

EE READY

TIMER3 CAPT

Timer/Counter3 Capture Event

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AT90CAN32/64

Table 9-1.

Reset and Interrupt Vectors (Continued)

Vector

No.

Program

Source

Interrupt Definition

Timer/Counter3 Compare Match A

Address⁽¹⁾

0x0038

0x003A

0x003C

0x003E

0x0040

0x0042

0x0044

0x0046

0x0048

29

30

31

32

33

34

35

36

37

TIMER3 COMPA

TIMER3 COMPB

TIMER3 COMPC

TIMER3 OVF

USART1, RX

USART1, UDRE

USART1, TX

TWI

Timer/Counter3 Compare Match B

Timer/Counter3 Compare Match C

Timer/Counter3 Overflow

USART1, Rx Complete

USART1 Data Register Empty

USART1, Tx Complete

Two-wire Serial Interface

SPM READY

Store Program Memory Ready

Notes: 1. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot

Flash Section. The address of each Interrupt Vector will then be the address in this table

added to the start address of the Boot Flash Section.

2. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at

reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 320.

Table 9-2 shows reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt

Vectors are not used, and regular program code can be placed at these locations. This is also

the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the

Boot section or vice versa.

Table 9-2.

BOOTRST

Reset and Interrupt Vectors Placement⁽¹⁾

IVSEL

Reset Address

0x0000

Interrupt Vectors Start Address

0x0002

1

0

1

0

1

0x0000

Boot Reset Address + 0x0002

0x0002

Boot Reset Address

Boot Reset Address + 0x0002

Note:

1. The Boot Reset Address is shown in Table 25-6 on page 333. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

AT90CAN32/64 is:

;Address

0x0000

0x0002

0x0004

0x0006

0x0008

0x000A

0x000C

0x000E

0x0010

Labels Code

Comments

jmp

RESET

; Reset Handler

EXT_INT0 ; IRQ0 Handler

EXT_INT1 ; IRQ1 Handler

EXT_INT2 ; IRQ2 Handler

EXT_INT3 ; IRQ3 Handler

EXT_INT4 ; IRQ4 Handler

EXT_INT5 ; IRQ5 Handler

EXT_INT6 ; IRQ6 Handler

EXT_INT7 ; IRQ7 Handler

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7538B–CAN–05/06

0x0012

0x0014

0x0016

0x0018

0x001A

0x001C

0x001E

0x0020

0x0022

0x0024

0x0026

0x0028

0x002A

0x002C

0x002E

0x0030

0x0032

0x0034

0x0036

0x0038

0x003A

0x003C

0x003E

0x0040

0x0042

0x0044

0x0046

0x0048

;

jmp

TIM2_COMP ; Timer2 Compare Handler

TIM2_OVF ; Timer2 Overflow Handler

TIM1_CAPT ; Timer1 Capture Handler

TIM1_COMPA; Timer1 CompareA Handler

TIM1_COMPB; Timer1 CompareB Handler

TIM1_OVF ; Timer1 CompareC Handler

TIM1_OVF ; Timer1 Overflow Handler

TIM0_COMP ; Timer0 Compare Handler

TIM0_OVF ; Timer0 Overflow Handler

CAN_IT

CTIM_OVF ; CAN Timer Overflow Handler

SPI_STC ; SPI Transfer Complete Handler

; CAN Handler

USART0_RXC; USART0 RX Complete Handler

USART0_DRE; USART0,UDR Empty Handler

USART0_TXC; USART0 TX Complete Handler

ANA_COMP ; Analog Comparator Handler

ADC

; ADC Conversion Complete Handler

; EEPROM Ready Handler

EE_RDY

TIM3_CAPT ; Timer3 Capture Handler

TIM3_COMPA; Timer3 CompareA Handler

TIM3_COMPB; Timer3 CompareB Handler

TIM3_COMPC; Timer3 CompareC Handler

TIM3_OVF ; Timer3 Overflow Handler

USART1_RXC; USART1 RX Complete Handler

USART1_DRE; USART1,UDR Empty Handler

USART1_TXC; USART1 TX Complete Handler

TWI

; TWI Interrupt Handler

; SPM Ready Handler

SPM_RDY

0x004A RESET: ldi

r16, high(RAMEND) ; Main program start

0x004B

0x004C

0x004D

0x004E

0x004F

...

out

ldi

out

sei

SPH,r16

;Set Stack Pointer to top of RAM

r16, low(RAMEND)

SPL,r16

; Enable interrupts

<instr> xxx

... ...

...

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the

IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and

general program setup for the Reset and Interrupt Vector Addresses is:

;AddressLabels

Code

Comments

0x0000 RESET: ldi

r16,high(RAMEND) ; Main program start

0x0001

0x0002

0x0003

out

ldi

out

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

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7538B–CAN–05/06

AT90CAN32/64

0x0004

0x0005

;

sei

; Enable interrupts

<instr> xxx

.org (BootResetAdd + 0x0002)

0x..02

0x..04

...

jmp

...

jmp

EXT_INT0

PCINT0

...

; IRQ0 Handler

; PCINT0 Handler

;

0x..0C

SPM_RDY

; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most

typical and general program setup for the Reset and Interrupt Vector Addresses is:

;AddressLabels

.org 0x0002

0x0002

Code

Comments

jmp

...

jmp

EXT_INT0

PCINT0

...

; IRQ0 Handler

0x0004

; PCINT0 Handler

...

;

0x002C

SPM_RDY

; Store Program Memory Ready Handler

;

.org (BootResetAdd)

0x..00 RESET: ldi

r16,high(RAMEND) ; Main program start

0x..01

0x..02

0x..03

0x..04

0x..05

out

ldi

out

sei

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

; Enable interrupts

<instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL

bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general

program setup for the Reset and Interrupt Vector Addresses is:

;AddressLabels

Code

Comments

;

.org (BootResetAdd)

0x..00

0x0002

0x..04

...

jmp

...

jmp

RESET

; Reset handler

EXT_INT0

PCINT0

...

; IRQ0 Handler

; PCINT0 Handler

;

0x..44

;

SPM_RDY

; Store Program Memory Ready Handler

0x..46 RESET: ldi

r16,high(RAMEND) ; Main program start

0x..47

0x..48

0x..49

0x..4A

0x..4B

out

ldi

out

sei

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

; Enable interrupts

<instr> xxx

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7538B–CAN–05/06

9.2

Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table.

9.2.1

MCU Control Register – MCUCR

Bit

7

6

–

5

–

4

3

–

2

–

1

IVSEL

R/W

0

JTD

R/W

0

PUD

R/W

0

IVCE

R/W

0

MCUCR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash

memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot

Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-

mined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write

Self-Programming” on page 320 for details. To avoid unintentional changes of Interrupt Vector

tables, a special write procedure must be followed to change the IVSEL bit:

1. Write the Interrupt Vector Change Enable (IVCE) bit to one.

2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to

IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status

Register is unaffected by the automatic disabling.

Note:

If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-

grammed, interrupts are disabled while executing from the Application section. If Interrupt Vectors

are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are dis-

abled while executing from the Boot Loader section. Refer to the section “Boot Loader Support –

Read-While-Write Self-Programming” on page 320 for details on Boot Lock bits.

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• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by

hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable

interrupts, as explained in the IVSEL description above. See Code Example below.

Assembly Code Example

Move_interrupts:

; Get MCUCR

in

r16, MCUCR

r17, r16

mov

; Enable change of Interrupt Vectors

ori

out

r16, (1<<IVCE)

MCUCR, r16

; Move interrupts to Boot Flash section

ori

out

ret

r17, (1<<IVSEL)

MCUCR, r17

C Code Example

void Move_interrupts(void)

{

uchar temp;

/* Get MCUCR*/

temp = MCUCR;

/* Enable change of Interrupt Vectors */

MCUCR = temp | (1<<IVCE);

/* Move interrupts to Boot Flash section */

MCUCR = temp | (1<<IVSEL);

}

65

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10. I/O-Ports

10.1 Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as

input). Each output buffer has symmetrical drive characteristics with both high sink and source

capability. All port pins have individually selectable pull-up resistors with a supply-voltage invari-

ant resistance. All I/O pins have protection diodes to both V_CCand Ground as indicated in Figure

10-1. Refer to “Electrical Characteristics ⁽¹⁾” on page 364 for a complete list of parameters.

Figure 10-1. I/O Pin Equivalent Schematic

R_pu

Pxn

Logic

C_pin

See Figure

"General Digital I/O" for

Details

All registers and bit references in this section are written in general form. A lower case “x” repre-

sents the numbering letter for the port, and a lower case “n” represents the bit number. However,

when using the register or bit defines in a program, the precise form must be used. For example,

PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-

ters and bit locations are listed in “Register Description for I/O-Ports”.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data Register and the Data Direction Register are read/write.

However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-

ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O”. Most port

pins are multiplexed with alternate functions for the peripheral features on the device. How each

alternate function interferes with the port pin is described in “Alternate Port Functions” on page

71. Refer to the individual module sections for a full description of the alternate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

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10.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a func-

tional description of one I/O-port pin, here generically called Pxn.

Figure 10-2. General Digital I/O⁽¹⁾

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

1

0

Q

D

Pxn

PORTxn

Q _CLR

WPx

WRx

RESET

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

clk _I/O

WDx: WRITE DDRx

RDx: READ DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

SLEEP: SLEEP CONTROL

clk_I/O: I/O CLOCK

WPx: WRITE PINx REGISTER

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

SLEEP, and PUD are common to all ports.

,

10.2.1

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description for I/O-Ports” on page 89, the DDxn bits are accessed at the DDRx I/O address, the

PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to

be configured as an output pin

The port pins are tri-stated when reset condition becomes active, even if no clocks are running.

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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

10.2.2

10.2.3

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) occurs. Normally, the pull-up enabled state is fully acceptable, as

a high-impedant environment will not notice the difference between a strong high driver and a

pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-

ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 10-1 summarizes the control signals for the pin value.

Table 10-1. Port Pin Configurations

PUD

(in MCUCR)

DDxn

PORTxn

I/O

Pull-up

Comment

Default configuration after Reset.

Tri-state (Hi-Z)

0

X

Input

No

0

1

0

1

0

1

Input

Yes

No

Pxn will source current if ext. pulled low.

Tri-state (Hi-Z)

X

Output

Output Low (Sink)

Output High (Source)

10.2.4

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 10-2, the PINxn Register bit and the preceding latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, but it also introduces a delay. Figure 10-3 shows a timing dia-

gram of the synchronization when reading an externally applied pin value. The maximum and

minimum propagation delays are denoted t_pd,maxand t_pd,minrespectively.

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Figure 10-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

XXX

in r17, PINx

0x00

t_{pd, max}

0xFF

r17

t_{pd, min}

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows t_pd,maxand t_pd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay t_pdthrough the synchronizer is 1 system clock period.

Figure 10-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

0xFF

r16

out PORTx, r16

nop

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_pd

0xFF

r17

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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin

values are read back again, but as previously discussed, a nop instruction is included to be able

to read back the value recently assigned to some of the pins.

Assembly Code Example⁽¹⁾

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi

out

r16, (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

r17, (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

PORTB, r16

DDRB, r17

; Insert nop for synchronization

nop

; Read port pins

in

r16, PINB

...

C Code Example⁽¹⁾

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

_NOP();

/* Read port pins */

i = PINB;

...

Note:

1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3

as low and redefining bits 0 and 1 as strong high drivers.

10.2.5

Digital Input Enable and Sleep Modes

As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the

schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in

Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if

some input signals are left floating, or have an analog signal level close to V_CC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt

request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various

other alternate functions as described in “Alternate Port Functions” on page 71.

If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as

“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

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above mentioned sleep modes, as the clamping in these sleep modes produces the requested

logic change.

10.2.6

Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even

though most of the digital inputs are disabled in the deep sleep modes as described above, float-

ing inputs should be avoided to reduce current consumption in all other modes where the digital

inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a

defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be

disabled during reset. If low power consumption during reset is important, it is recommended to

use an external pull-up or pull-down. Connecting unused pins directly to V^CCor GND is not rec-

ommended, since this may cause excessive currents if the pin is accidentally configured as an

output.

10.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5

shows how the port pin control signals from the simplified Figure 10-2 can be overridden by

alternate functions. The overriding signals may not be present in all port pins, but the figure

serves as a generic description applicable to all port pins in the AVR microcontroller family.

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Figure 10-5. Alternate Port Functions⁽¹⁾

PUOExn

PUOVxn

1

0

PUD

DDOExn

DDOVxn

1

0

Q

D

DDxn

Q _CLR

WDx

RDx

PVOExn

PVOVxn

RESET

1

0

Pxn

Q

D

0

PORTxn

PTOExn

WPx

Q _CLR

DIEOExn

DIEOVxn

SLEEP

RESET

WRx

1

0

RRx

RPx

SYNCHRONIZER

SET

D

Q

D

L

Q

PINxn

_CLRQ

CLR

clk _I/O

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

PUD: PULLUP DISABLE

WDx: WRITE DDRx

RDx: READ DDRx

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

RRx: READ PORTx REGISTER

WRx: WRITE PORTx

RPx: READ PORTx PIN

WPx: WRITE PINx

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

SLEEP: SLEEP CONTROL

clk

:

I/O CLOCK

DIxn: DIGITAL INPUT PIN n ON PORTx

AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

I/O

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

,

Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from

Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated

internally in the modules having the alternate function.

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Table 10-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name

Full Name

Description

If this signal is set, the pull-up enable is controlled by the PUOV

signal. If this signal is cleared, the pull-up is enabled when

{DDxn, PORTxn, PUD} = 0b010.

Pull-up Override

Enable

PUOE

If PUOE is set, the pull-up is enabled/disabled when PUOV is

set/cleared, regardless of the setting of the DDxn, PORTxn,

and PUD Register bits.

Pull-up Override

Value

PUOV

DDOE

DDOV

If this signal is set, the Output Driver Enable is controlled by the

DDOV signal. If this signal is cleared, the Output driver is

enabled by the DDxn Register bit.

Data Direction

Override Enable

If DDOE is set, the Output Driver is enabled/disabled when

DDOV is set/cleared, regardless of the setting of the DDxn

Register bit.

Data Direction

Override Value

If this signal is set and the Output Driver is enabled, the port

value is controlled by the PVOV signal. If PVOE is cleared, and

the Output Driver is enabled, the port Value is controlled by the

PORTxn Register bit.

Port Value

Override Enable

PVOE

Port Value

Override Value

If PVOE is set, the port value is set to PVOV, regardless of the

setting of the PORTxn Register bit.

PVOV

PTOE

Port Toggle

Override Enable

If PTOE is set, the PORTxn Register bit is inverted.

Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input Enable

is determined by MCU state (Normal mode, sleep mode).

DIEOE

DIEOV

Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state (Normal

mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the

signal is connected to the output of the schmitt trigger but

before the synchronizer. Unless the Digital Input is used as a

clock source, the module with the alternate function will use its

own synchronizer.

DI

Digital Input

This is the Analog Input/output to/from alternate functions. The

signal is connected directly to the pad, and can be used bi-

directionally.

Analog

Input/Output

AIO

The following subsections shortly describe the alternate functions for each port, and relate the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

10.3.1

MCU Control Register – MCUCR

Bit

7

6

–

5

–

4

3

–

2

–

1

IVSEL

R/W

0

IVCE

R/W

0

JTD

R/W

0

PUD

R/W

0

MCUCR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

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• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” for more details about this feature.

10.3.2

Alternate Functions of Port A

The Port A has an alternate function as the address low byte and data lines for the External

Memory Interface.

The Port A pins with alternate functions are shown in Table 10-3.

Table 10-3. Port A Pins Alternate Functions

Port Pin

PA7

Alternate Function

AD7 (External memory interface address and data bit 7)

AD6 (External memory interface address and data bit 6)

AD5 (External memory interface address and data bit 5)

AD4 (External memory interface address and data bit 4)

AD3 (External memory interface address and data bit 3)

AD2 (External memory interface address and data bit 2)

AD1 (External memory interface address and data bit 1)

AD0 (External memory interface address and data bit 0)

PA6

PA5

PA4

PA3

PA2

PA1

PA0

The alternate pin configuration is as follows:

• AD7 – Port A, Bit 7

AD7, External memory interface address 7 and Data 7.

• AD6 – Port A, Bit 6

AD6, External memory interface address 6 and Data 6.

• AD5 – Port A, Bit 5

AD5, External memory interface address 5 and Data 5.

• AD4 – Port A, Bit 4

AD4, External memory interface address 4 and Data 4.

• AD3 – Port A, Bit 3

AD3, External memory interface address 3 and Data 3.

• AD2 – Port A, Bit 2

AD2, External memory interface address 2 and Data 2.

• AD1 – Port A, Bit 1

AD1, External memory interface address 1 and Data 1.

• AD0 – Port A, Bit 0

AD0, External memory interface address 0 and Data 0.

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Table 10-4 and Table 10-5 relates the alternate functions of Port A to the overriding signals

shown in Figure 10-5 on page 72.

Table 10-4. Overriding Signals for Alternate Functions in PA7..PA4

Signal Name

PA7/AD7

PA6/AD6

PA5/AD5

PA4/AD4

SRE •

PUOE

(ADA⁽¹⁾+ WR)

PUOV

DDOE

DDOV

PVOE

0

SRE

WR + ADA

SRE

WR + ADA

SRE

A7 • ADA⁽¹⁾+ D7

OUTPUT • WR

A6 • ADA⁽¹⁾+ D6

OUTPUT • WR

A5 • ADA⁽¹⁾+ D5

OUTPUT • WR

A4 • ADA⁽¹⁾+ D4

OUTPUT • WR

PVOV

PTOE

DIEOE

DIEOV

DI

0

D7 INPUT

–

D6 INPUT

–

D5 INPUT

–

D4 INPUT

–

AIO

Note:

1. ADA is short for ADdress Active and represents the time when address is output. See “Exter-

nal Memory Interface” on page 27 for details.

Table 10-5. Overriding Signals for Alternate Functions in PA3..PA0

Signal Name

PA3/AD3

PA2/AD2

PA1/AD1

PA0/AD0

SRE •

PUOE

(ADA⁽¹⁾+ WR)

PUOV

DDOE

DDOV

PVOE

0

SRE

WR + ADA

SRE

A3 • ADA⁽¹⁾+ D3

OUTPUT • WR

A2 • ADA⁽¹⁾+ D2

OUTPUT • WR

A1 • ADA⁽¹⁾+ D1

OUTPUT • WR

A0 • ADA⁽¹⁾+ D0

OUTPUT • WR

PVOV

PTOE

DIEOE

DIEOV

DI

0

D3 INPUT

–

D2 INPUT

–

D1 INPUT

–

D0 INPUT

–

AIO

Note:

1. ADA is short for ADdress Active and represents the time when address is output. See “Exter-

nal Memory Interface” on page 27 for details.

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10.3.3

Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 10-6.

Table 10-6. Port B Pins Alternate Functions

Port Pin

Alternate Functions

OC0A/OC1C (Output Compare and PWM Output A for Timer/Counter0 or Output Compare

and PWM Output C for Timer/Counter1)

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

OC1B (Output Compare and PWM Output B for Timer/Counter1)

OC1A (Output Compare and PWM Output A for Timer/Counter1)

OC2A (Output Compare and PWM Output A for Timer/Counter2 )

MISO (SPI Bus Master Input/Slave Output)

MOSI (SPI Bus Master Output/Slave Input)

SCK (SPI Bus Serial Clock)

SS (SPI Slave Select input)

The alternate pin configuration is as follows:

• OC0A/OC1C, Bit 7

OC0A, Output Compare Match A output. The PB7 pin can serve as an external output for the

Timer/Counter0 Output Compare A. The pin has to be configured as an output (DDB7 set “one”)

to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

OC1C, Output Compare Match C output. The PB7 pin can serve as an external output for the

Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set “one”)

to serve this function. The OC1C pin is also the output pin for the PWM mode timer function.

• OC1B, Bit 6

OC1B, Output Compare Match B output. The PB6 pin can serve as an external output for the

Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set “one”)

to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

• OC1A, Bit 5

OC1A, Output Compare Match A output. The PB5 pin can serve as an external output for the

Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set “one”)

to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

• OC2A, Bit 4

OC2A, Output Compare Match A output. The PB4 pin can serve as an external output for the

Timer/Counter2 Output Compare A. The pin has to be configured as an output (DDB4 set “one”)

to serve this function. The OC2A pin is also the output pin for the PWM mode timer function.

• MISO – Port B, Bit 3

MISO, Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a

master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is

enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to

be an input, the pull-up can still be controlled by the PORTB3 bit.

• MOSI – Port B, Bit 2

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MOSI, SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a

slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is

enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced

to be an input, the pull-up can still be controlled by the PORTB2 bit.

• SCK – Port B, Bit 1

SCK, Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a

slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is

enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced

to be an input, the pull-up can still be controlled by the PORTB1 bit.

• SS – Port B, Bit 0

SS, Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an

input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven

low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.

When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.

Table 10-7 and Table 10-8 relate the alternate functions of Port B to the overriding signals

shown in Figure 10-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the

MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

Table 10-7 and Table 10-8 relates the alternate functions of Port B to the overriding signals

shown in Figure 10-5 on page 72.

Table 10-7. Overriding Signals for Alternate Functions in PB7..PB4

Signal Name

PUOE

PB7/OC0A/OC1C

PB6/OC1B

PB5/OC1A

PB4/OC2A

0

PUOV

DDOE

DDOV

OC0A/OC1C

ENABLE⁽¹⁾

PVOE

OC1B ENABLE

OC1A ENABLE

OC2A ENABLE

PVOV

PTOE

DIEOE

DIEOV

DI

OC0A/OC1C⁽¹⁾

OC1B

OC1A

OC2A

0

–

0

–

0

–

0

–

AIO

Note:

1. See “Output Compare Modulator - OCM” on page 164 for details.

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Table 10-8. Overriding Signals for Alternate Functions in PB3..PB0

Signal Name

PUOE

PB3/MISO

SPE • MSTR

PORTB3 • PUD

SPE • MSTR

0

PB2/MOSI

SPE • MSTR

PORTB2 • PUD

SPE • MSTR

0

PB1/SCK

PB0/SS

SPE • MSTR

PORTB1 • PUD

SPE • MSTR

0

SPE • MSTR

PUOV

PORTB0 • PUD

DDOE

SPE • MSTR

DDOV

0

PVOE

SPE • MSTR

SPI SLAVE

OUTPUT

SPI MASTER

OUTPUT

PVOV

SCK OUTPUT

0

PTOE

0

DIEOE

DIEOV

SPI MASTER

INPUT

SPI SLAVE

INPUT • RESET

DI

SCK INPUT

–

SPI SS

–

AIO

–

10.3.4

Alternate Functions of Port C

The Port C has an alternate function as the address high byte for the External Memory Interface.

The Port C pins with alternate functions are shown in Table 10-9.

Table 10-9. Port C Pins Alternate Functions

Port Pin

Alternate Function

A15/CLKO (External memory interface address 15 or Divided System

Clock)

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

A14 (External memory interface address 14)

A13 (External memory interface address 13)

A12 (External memory interface address 12)

A11 (External memory interface address 11)

A10 (External memory interface address 10)

A9 (External memory interface address 9)

A8 (External memory interface address 8)

The alternate pin configuration is as follows:

• A15/CLKO – Port C, Bit 7

A15, External memory interface address 15.

CLKO, Divided System Clock: The divided system clock can be output on the PC7 pin. The

divided system clock will be output if the CKOUT Fuse is programmed, regardless of the

PORTC7 and DDC7 settings. It will also be output during reset.

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• A14 – Port C, Bit 6

A14, External memory interface address 14.

• A13 – Port C, Bit 5

A13, External memory interface address 13.

• A12 – Port C, Bit 4

A12, External memory interface address 12.

• A11 – Port C, Bit 3

A11, External memory interface address 11.

• A10 – Port C, Bit 2

A10, External memory interface address 10.

• A9 – Port C, Bit 1

A9, External memory interface address 9.

• A8 – Port C, Bit 0

A8, External memory interface address 8.

Table 10-10 and Table 10-11 relate the alternate functions of Port C to the overriding signals

shown in Figure 10-5 on page 72.

Table 10-10. Overriding Signals for Alternate Functions in PC7..PC4

Signal Name

PUOE

PC7/A15

PC6/A14

PC5/A13

PC4/A12

SRE • (XMM<1)

SRE • (XMM<2)

SRE • (XMM<3)

SRE • (XMM<4)

PUOV

0

CKOUT⁽¹⁾

(SRE • (XMM<1))

+

DDOE

DDOV

PVOE

SRE • (XMM<2)

1

SRE • (XMM<3)

1

SRE • (XMM<4)

1

CKOUT⁽¹⁾

(SRE • (XMM<1))

+

SRE • (XMM<2)

SRE • (XMM<3)

SRE • (XMM<4)

(A15 • CKOUT⁽¹⁾) +

PVOV

A14

A13

A12

(CLKO • CKOUT⁽¹⁾

)

PTOE

DIEOE

DIEOV

DI

0

–

0

–

0

–

0

–

AIO

Note:

1. CKOUT is one if the CKOUT Fuse is programmed

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7538B–CAN–05/06

Table 10-11. Overriding Signals for Alternate Functions in PC3..PC0

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PC3/A11

PC2/A10

PC1/A9

PC0/A8

SRE • (XMM<5)

SRE • (XMM<6)

SRE • (XMM<7)

0

SRE • (XMM<5)

SRE • (XMM<6)

SRE • (XMM<7)

1

SRE • (XMM<5)

SRE • (XMM<6)

SRE • (XMM<7)

A11

0

A10

0

A9

0

A8

0

–

AIO

–

10.3.5

Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 10-12.

Table 10-12. Port D Pins Alternate Functions

Port Pin

PD7

Alternate Function

T0 (Timer/Counter0 Clock Input)

PD6

RXCAN/T1 (CAN Receive Pin or Timer/Counter1 Clock Input)

PD5

TXCAN/XCK1 (CAN Transmit Pin or USART1 External Clock Input/Output)

ICP1 (Timer/Counter1 Input Capture Trigger)

PD4

PD3

INT3/TXD1 (External Interrupt3 Input or UART1 Transmit Pin)

INT2/RXD1 (External Interrupt2 Input or UART1 Receive Pin)

INT1/SDA (External Interrupt1 Input or TWI Serial DAta)

INT0/SCL (External Interrupt0 Input or TWI Serial CLock)

PD2

PD1

PD0

The alternate pin configuration is as follows:

• T0/CLKO – Port D, Bit 7

T0, Timer/Counter0 counter source.

• RXCAN/T1 – Port D, Bit 6

RXCAN, CAN Receive Data (Data input pin for the CAN). When the CAN controller is enabled

this pin is configured as an input regardless of the value of DDD6. When the CAN forces this pin

to be an input, the pull-up can still be controlled by the PORTD6 bit.

T1, Timer/Counter1 counter source.

• TXCAN/XCK1 – Port D, Bit 5

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TXCAN, CAN Transmit Data (Data output pin for the CAN). When the CAN is enabled, this pin is

configured as an output regardless of the value of DDD5.

XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock

is output (DDD5 set) or input (DDD45 cleared). The XCK1 pin is active only when the USART1

operates in Synchronous mode.

• ICP1 – Port D, Bit 4

ICP1, Input Capture Pin1. The PD4 pin can act as an input capture pin for Timer/Counter1.

• INT3/TXD1 – Port D, Bit 3

INT3, External Interrupt source 3. The PD3 pin can serve as an external interrupt source to the

MCU.

TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is

enabled, this pin is configured as an output regardless of the value of DDD3.

• INT2/RXD1 – Port D, Bit 2

INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the

MCU.

RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled

this pin is configured as an input regardless of the value of DDD2. When the USART forces this

pin to be an input, the pull-up can still be controlled by the PORTD2 bit.

• INT1/SDA – Port D, Bit 1

INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the

MCU.

SDA, Two-wire Serial Interface Data. When the TWEN bit in TWCR is set (one) to enable the

Two-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data

I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup-

press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver

with slew-rate limitation.

• INT0/SCL – Port D, Bit 0

INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the

MCU.

SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the

Two-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock

I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup-

press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver

with slew-rate limitation.

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Table 10-13 and Table 10-14 relates the alternate functions of Port D to the overriding signals

shown in Figure 10-5 on page 72.

Table 10-13. Overriding Signals for Alternate Functions PD7..PD4

Signal Name

PUOE

PD7/T0

PD6/T1/RXCAN

PD5/XCK1/TXCAN

PD4/ICP1

0

RXCANEN

TXCANEN +

0

PUOV

PORTD6 • PUD

0

DDOE

RXCANEN

TXCANEN

DDOV

0

1

PVOE

TXCANEN + UMSEL1

(XCK1 OUTPUT •

PVOV

0

UMSEL1 • TXCANEN) +

(TXCAN • TXCANEN)

0

PTOE

DIEOE

DIEOV

DI

0

T0 INPUT

–

T1 INPUT/RXCAN

–

XCK1 INPUT

–

ICP1 INPUT

–

AIO

Table 10-14. Overriding Signals for Alternate Functions in PD3..PD0⁽¹⁾

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PD3/INT3/TXD1

PD2/INT2/RXD1

PD1/INT1/SDA

TWEN

PD0/INT0/SCL

TWEN

TXEN1

RXEN1

0

PORTD2 • PUD

PORTD1 • PUD

0

PORTD0 • PUD

0

TXEN1

RXEN1

1

0

TXEN1

0

TWEN

TXD1

0

SDA_OUT

0

SCL_OUT

0

INT3 ENABLE

INT3 INPUT

–

INT2 ENABLE

INT2 INPUT/RXD1

–

INT1 ENABLE

INT1 INPUT

SDA INPUT

INT0 ENABLE

INT0 INPUT

SCL INPUT

AIO

Note:

1. When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins

PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between

the AIO outputs shown in the port figure and the digital logic of the TWI module.

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10.3.6

Alternate Functions of Port E

The Port E pins with alternate functions are shown in Table 10-15.

Table 10-15. Port E Pins Alternate Functions

Port Pin

PE7

Alternate Function

INT7/ICP3 (External Interrupt 7 Input or Timer/Counter3 Input Capture Trigger)

INT6/ T3 (External Interrupt 6 Input or Timer/Counter3 Clock Input)

PE6

INT5/OC3C (External Interrupt 5 Input or Output Compare and PWM Output C for

Timer/Counter3)

PE5

PE4

PE3

INT4/OC3B (External Interrupt4 Input or Output Compare and PWM Output B for

Timer/Counter3)

AIN1/OC3A (Analog Comparator Negative Input or Output Compare and PWM Output A

for Timer/Counter3)

PE2

PE1

PE0

AIN0/XCK0 (Analog Comparator Positive Input or USART0 external clock input/output)

PDO/TXD0 (Programming Data Output or UART0 Transmit Pin)

PDI/RXD0 (Programming Data Input or UART0 Receive Pin)

The alternate pin configuration is as follows:

• PCINT7/ICP3 – Port E, Bit 7

INT7, External Interrupt source 7. The PE7 pin can serve as an external interrupt source.

ICP3, Input Capture Pin3: The PE7 pin can act as an input capture pin for Timer/Counter3.

• INT6/T3 – Port E, Bit 6

INT6, External Interrupt source 6. The PE6 pin can serve as an external interrupt source.

T3, Timer/Counter3 counter source.

• INT5/OC3C – Port E, Bit 5

INT5, External Interrupt source 5. The PE5 pin can serve as an External Interrupt source.

OC3C, Output Compare Match C output. The PE5 pin can serve as an External output for the

Timer/Counter3 Output Compare C. The pin has to be configured as an output (DDE5 set “one”)

to serve this function. The OC3C pin is also the output pin for the PWM mode timer function.

• INT4/OC3B – Port E, Bit 4

INT4, External Interrupt source 4. The PE4 pin can serve as an External Interrupt source.

OC3B, Output Compare Match B output. The PE4 pin can serve as an External output for the

Timer/Counter3 Output Compare B. The pin has to be configured as an output (DDE4 set (one))

to serve this function. The OC3B pin is also the output pin for the PWM mode timer function.

• AIN1/OC3A – Port E, Bit 3

AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of

the Analog Comparator.

OC3A, Output Compare Match A output. The PE3 pin can serve as an External output for the

Timer/Counter3 Output Compare A. The pin has to be configured as an output (DDE3 set “one”)

to serve this function. The OC3A pin is also the output pin for the PWM mode timer function.

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• AIN0/XCK0 – Port E, Bit 2

AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of

the Analog Comparator.

XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether the clock

is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0

operates in Synchronous mode.

• PDO/TXD0 – Port E, Bit 1

PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is

used as data output line for the AT90CAN32/64.

TXD0, UART0 Transmit pin.

• PDI/RXD0 – Port E, Bit 0

PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used

as data input line for the AT90CAN32/64.

RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the

USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0.

When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the inter-

nal pull-up.

Table 10-16 and Table 10-17 relates the alternate functions of Port E to the overriding signals

shown in Figure 10-5 on page 72.

Table 10-16. Overriding Signals for Alternate Functions PE7..PE4

Signal Name

PUOE

PE7/INT7/ICP3

PE6/INT6/T3

PE5/INT5/OC3C

PE4/INT4/OC3B

0

PUOV

0

DDOE

DDOV

PVOE

0

OC3C ENABLE

OC3C

OC3B ENABLE

OC3B

PVOV

0

PTOE

0

DIEOE

DIEOV

INT7 ENABLE

INT6 ENABLE

INT5 ENABLE

INT4 ENABLE

INT7 INPUT

/ICP3 INPUT

INT6 INPUT

/T3 INPUT

DI

INT5 INPUT

–

INT4 INPUT

–

AIO

–

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Table 10-17. Overriding Signals for Alternate Functions in PE3..PE0

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PE3/AIN1/OC3A

PE2/AIN0/XCK0

PE1/PDO/TXD0

PE0/PDI/RXD0

0

TXEN0

RXEN0

0

PORTE0 • PUD

0

TXEN0

RXEN0

0

1

0

OC3A ENABLE

UMSEL0

XCK0 OUTPUT

0

TXEN0

0

OC3A

TXD0

0

–

0

AIN1D⁽¹⁾

AIN0D⁽¹⁾

0

XCK0 INPUT

AIN0 INPUT

RXD0

–

AIO

AIN1 INPUT

Note:

1. AIN0D and AIN1D is described in “Digital Input Disable Register 1 – DIDR1” on page 271.

10.3.7

Alternate Functions of Port F

The Port F has an alternate function as analog input for the ADC as shown in Table 10-18. If

some Port F pins are configured as outputs, it is essential that these do not switch when a con-

version is in progress. This might corrupt the result of the conversion. If the JTAG interface is

enabled, the pull-up resistors on pins PF7 (TDI), PF5 (TMS) and PF4 (TCK) will be activated

even if a reset occurs.

Table 10-18. Port F Pins Alternate Functions

Port Pin

PF7

Alternate Function

ADC7/TDI (ADC input channel 7 or JTAG Data Input)

ADC6/TDO (ADC input channel 6 or JTAG Data Output)

ADC5/TMS (ADC input channel 5 or JTAG mode Select)

ADC4/TCK (ADC input channel 4 or JTAG ClocK)

ADC3 (ADC input channel 3)

PF6

PF5

PF4

PF3

PF2

ADC2 (ADC input channel 2)

PF1

ADC1 (ADC input channel 1)

PF0

ADC0 (ADC input channel 0)

The alternate pin configuration is as follows:

• TDI, ADC7 – Port F, Bit 7

ADC7, Analog to Digital Converter, input channel 7.

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TDI, JTAG Test Data In. Serial input data to be shifted in to the Instruction Register or Data Reg-

ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TCK, ADC6 – Port F, Bit 6

ADC6, Analog to Digital Converter, input channel 6.

TDO, JTAG Test Data Out. Serial output data from Instruction Register or Data Register. When

the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TMS, ADC5 – Port F, Bit 5

ADC5, Analog to Digital Converter, input channel 5.

TMS, JTAG Test mode Select. This pin is used for navigating through the TAP-controller state

machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TDO, ADC4 – Port F, Bit 4

ADC4, Analog to Digital Converter, input channel 4.

TCK, JTAG Test Clock. JTAG operation is synchronous to TCK. When the JTAG interface is

enabled, this pin can not be used as an I/O pin.

• ADC3 – Port F, Bit 3

ADC3, Analog to Digital Converter, input channel 3.

• ADC2 – Port F, Bit 2

ADC2, Analog to Digital Converter, input channel 2.

• ADC1 – Port F, Bit 1

ADC1, Analog to Digital Converter, input channel 1.

• ADC0 – Port F, Bit 0

ADC0, Analog to Digital Converter, input channel 0.

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Table 10-19 and Table 10-20 relates the alternate functions of Port F to the overriding signals

shown in Figure 10-5 on page 72.

Table 10-19. Overriding Signals for Alternate Functions in PF7..PF4

Signal Name

PUOE

PF7/ADC7/TDI

JTAGEN

PF6/ADC6/TDO

JTAGEN

PF5/ADC5/TMS

JTAGEN

PF4/ADC4/TCK

JTAGEN

PUOV

JTAGEN

DDOE

JTAGEN

SHIFT_IR +

SHIFT_DR

DDOV

0

PVOE

PVOV

PTOE

JTAGEN

TDO

0

JTAGEN

0

JTAGEN +

ADC7D

JTAGEN +

ADC6D

JTAGEN +

ADC5D

JTAGEN +

ADC4D

DIEOE

DIEOV

DI

JTAGEN

TDI

0

JTAGEN

TMS

JTAGEN

TCK

–

AIO

ADC7 INPUT

ADC6 INPUT

ADC5 INPUT

ADC4 INPUT

Table 10-20. Overriding Signals for Alternate Functions in PF3..PF0

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PF3/ADC3

PF2/ADC2

PF1/ADC1

PF0/ADC0

0

ADC3D

ADC2D

ADC1D

ADC0D

0

–

AIO

ADC3 INPUT

ADC2 INPUT

ADC1 INPUT

ADC0 INPUT

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7538B–CAN–05/06

10.3.8

Alternate Functions of Port G

The alternate pin configuration is as follows:

Table 10-21. Port G Pins Alternate Functions

Port Pin

PG4

Alternate Function

TOSC1 (RTC Oscillator Timer/Counter2)

TOSC2 (RTC Oscillator Timer/Counter2)

ALE (Address Latch Enable to external memory)

RD (Read strobe to external memory)

WR (Write strobe to external memory)

PG3

PG2

PG1

PG0

The alternate pin configuration is as follows:

• TOSC1 – Port G, Bit 4

TOSC2, Timer/Counter2 Oscillator pin 1. When the AS2 bit in ASSR is set (one) to enable asyn-

chronous clocking of Timer/Counter2, pin PG4 is disconnected from the port, and becomes the

input of the inverting Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this

pin, and the pin can not be used as an I/O pin.

• TOSC2 – Port G, Bit 3

TOSC2, Timer/Counter2 Oscillator pin 2. When the AS2 bit in ASSR is set (one) to enable asyn-

chronous clocking of Timer/Counter2, pin PG3 is disconnected from the port, and becomes the

inverting output of the Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this

pin, and the pin can not be used as an I/O pin.

• ALE – Port G, Bit 2

ALE is the external data memory Address Latch Enable signal.

• RD – Port G, Bit 1

RD is the external data memory read control strobe.

• WR – Port G, Bit 0

WR is the external data memory write control strobe.

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Table 10-21 and Table 10-22 relates the alternate functions of Port G to the overriding signals

shown in Figure 10-5 on page 72.

Table 10-22. Overriding Signals for Alternate Function in PG4

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

-

PG4/TOSC1

AS2

0

AS2

0

AS2

EXCLK

–

AIO

T/C2 OSC INPUT

Table 10-23. Overriding Signals for Alternate Functions in PG3:0

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PG3/TOSC2

PG2/ALE

PG1/RD

PG0/WR

AS2 • EXCLK

SRE

0

SRE

0

AS2 • EXCLK

SRE

1

SRE

1

0

1

0

SRE

RD

0

SRE

WR

0

ALE

0

AS2

0

–

AIO

T/C2 OSC OUTPUT

–

10.4 Register Description for I/O-Ports

10.4.1

Port A Data Register – PORTA

Bit

7

6

5

4

3

2

1

0

PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0

PORTA

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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10.4.2

10.4.3

10.4.4

10.4.5

10.4.6

10.4.7

10.4.8

10.4.9

Port A Data Direction Register – DDRA

Bit

7

DDA7

R/W

0

6

DDA6

R/W

0

5

DDA5

R/W

0

4

DDA4

R/W

0

3

DDA3

R/W

0

2

DDA2

R/W

0

1

DDA1

R/W

0

DDA0

R/W

0

DDRA

Read/Write

Initial Value

Port A Input Pins Address – PINA

Bit

7

6

5

4

3

2

1

0

PINA7

R/W

N/A

PINA6

R/W

N/A

PINA5

R/W

N/A

PINA4

R/W

N/A

PINA3

R/W

N/A

PINA2

R/W

N/A

PINA1

R/W

N/A

PINA0

R/W

N/A

PINA

Read/Write

Initial Value

Port B Data Register – PORTB

Bit

7

6

5

4

3

2

1

0

PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0

PORTB

DDRB

PINB

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Port B Data Direction Register – DDRB

Bit

7

DDB7

R/W

0

6

DDB6

R/W

0

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

Read/Write

Initial Value

Port B Input Pins Address – PINB

Bit

7

6

5

4

3

2

1

0

PINB7

R/W

N/A

PINB6

R/W

N/A

PINB5

R/W

N/A

PINB4

R/W

N/A

PINB3

R/W

N/A

PINB2

R/W

N/A

PINB1

R/W

N/A

PINB0

R/W

N/A

Read/Write

Initial Value

Port C Data Register – PORTC

Bit

7

6

5

4

3

2

1

0

PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0

PORTC

DDRC

PINC

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Port C Data Direction Register – DDRC

Bit

7

DDC7

R/W

0

6

DDC6

R/W

0

5

DDC5

R/W

0

4

DDC4

R/W

0

3

DDC3

R/W

0

2

DDC2

R/W

0

1

DDC1

R/W

0

DDC0

R/W

0

Read/Write

Initial Value

Port C Input Pins Address – PINC

Bit

7

6

5

4

3

2

1

0

PINC7

R/W

N/A

PINC6

R/W

N/A

PINC5

R/W

N/A

PINC4

R/W

N/A

PINC3

R/W

N/A

PINC2

R/W

N/A

PINC1

R/W

N/A

PINC0

R/W

N/A

Read/Write

Initial Value

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AT90CAN32/64

10.4.10 Port D Data Register – PORTD

Bit

7

6

5

4

3

2

1

0

PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0

PORTD

DDRD

PIND

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

10.4.11 Port D Data Direction Register – DDRD

Bit

7

DDD7

R/W

0

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

DDD0

R/W

0

Read/Write

Initial Value

10.4.12 Port D Input Pins Address – PIND

Bit

7

6

5

4

3

2

1

0

PIND7

R/W

N/A

PIND6

R/W

N/A

PIND5

R/W

N/A

PIND4

R/W

N/A

PIND3

R/W

N/A

PIND2

R/W

N/A

PIND1

R/W

N/A

PIND0

R/W

N/A

Read/Write

Initial Value

10.4.13 Port E Data Register – PORTE

Bit

7

6

5

4

3

2

1

0

PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0

PORTE

DDRE

PINE

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

10.4.14 Port E Data Direction Register – DDRE

Bit

7

DDE7

R/W

0

6

DDE6

R/W

0

5

DDE5

R/W

0

4

DDE4

R/W

0

3

DDE3

R/W

0

2

DDE2

R/W

0

1

DDE1

R/W

0

DDE0

R/W

0

Read/Write

Initial Value

10.4.15 Port E Input Pins Address – PINE

Bit

7

6

5

4

3

2

1

0

PINE7

R/W

N/A

PINE6

R/W

N/A

PINE5

R/W

N/A

PINE4

R/W

N/A

PINE3

R/W

N/A

PINE2

R/W

N/A

PINE1

R/W

N/A

PINE0

R/W

N/A

Read/Write

Initial Value

10.4.16 Port F Data Register – PORTF

Bit

7

6

5

4

3

2

1

0

PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0

PORTF

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

10.4.17 Port F Data Direction Register – DDRF

Bit

7

DDF7

R/W

0

6

DDF6

R/W

0

5

DDF5

R/W

0

4

DDF4

R/W

0

3

DDF3

R/W

0

2

DDF2

R/W

0

1

DDF1

R/W

0

DDF0

R/W

0

DDRF

Read/Write

Initial Value

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10.4.18 Port F Input Pins Address – PINF

Bit

7

6

5

4

3

2

1

0

PINF7

R/W

N/A

PINF6

R/W

N/A

PINF5

R/W

N/A

PINF4

R/W

N/A

PINF3

R/W

N/A

PINF2

R/W

N/A

PINF1

R/W

N/A

PINF0

R/W

N/A

PINF

PORTG

DDRG

PING

Read/Write

Initial Value

10.4.19 Port G Data Register – PORTG

Bit

7

–

6

–

5

–

4

3

2

1

0

PORTG4 PORTG3 PORTG2 PORTG1 PORTG0

Read/Write

Initial Value

R

0

R

0

R

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

10.4.20 Port G Data Direction Register – DDRG

Bit

7

–

6

–

5

–

4

DDG4

R/W

0

3

DDG3

R/W

0

2

DDG2

R/W

0

1

DDG1

R/W

0

DDG0

R/W

0

Read/Write

Initial Value

R

0

R

0

R

0

10.4.21 Port G Input Pins Address – PING

Bit

7

–

6

–

5

–

4

3

2

1

0

PING4

R/W

N/A

PING3

R/W

N/A

PING2

R/W

N/A

PING1

R/W

N/A

PING0

R/W

N/A

Read/Write

Initial Value

R

0

R

0

R

0

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11. External Interrupts

The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts

will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of gen-

erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or

a low level. This is set up as indicated in the specification for the External Interrupt Control Reg-

isters – EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is

configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that

recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock,

described in “Clock Systems and their Distribution” on page 37. Low level interrupts and the

edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be

used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in

all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. This makes the MCU less sensitive to

noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the

Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla-

tor is voltage dependent as shown in the “Electrical Characteristics ⁽¹⁾” on page 364. The MCU

will wake up if the input has the required level during this sampling or if it is held until the end of

the start-up time. The start-up time is defined by the SUT fuses as described in “System Clock”

on page 37. If the level is sampled twice by the Watchdog Oscillator clock but disappears before

the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The

required level must be held long enough for the MCU to complete the wake up to trigger the level

interrupt.

11.0.1

External Interrupt Control Register A – EICRA

Bit

7

6

5

4

ISC20

R/W

0

3

ISC11

R/W

0

2

ISC10

R/W

0

1

ISC01

R/W

0

ISC00

R/W

0

ISC31

ISC30

ISC21

R/W

0

EICRA

Read/Write

Initial Value

R/W

0

R/W

0

• Bits 7..0 – ISC31, ISC30 – ISC01, ISC00: External Interrupt 3 - 0 Sense Control Bits

The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 11-1. Edges on INT3..INT0 are registered asynchro-

nously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 11-2 will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter-

rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur.

Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the

EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be

cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the

interrupt is re-enabled.

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Table 11-1.

Interrupt Sense Control⁽¹⁾

ISCn1

ISCn0

Description

0

1

0

1

0

1

The low level of INTn generates an interrupt request.

Reserved

The falling edge of INTn generates asynchronously an interrupt request.

The rising edge of INTn generates asynchronously an interrupt request.

Note:

1. n = 3, 2, 1 or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

Table 11-2. Asynchronous External Interrupt Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

Minimum pulse width for asynchronous

external interrupt

t_INT

50

ns

11.0.2

External Interrupt Control Register B – EICRB

Bit

7

ISC71

R/W

0

6

ISC70

R/W

0

5

ISC61

R/W

0

4

ISC60

R/W

0

3

ISC51

R/W

0

2

ISC50

R/W

0

1

0

ISC41

R/W

0

ISC40

R/W

0

EICRB

Read/Write

Initial Value

• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits

The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 11-3. The value on the INT7:4 pins are sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one

clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-

rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL

divider is enabled. If low level interrupt is selected, the low level must be held until the comple-

tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered

interrupt will generate an interrupt request as long as the pin is held low.

Table 11-3.

Interrupt Sense Control⁽¹⁾

ISCn1

ISCn0

Description

0

1

0

1

0

1

The low level of INTn generates an interrupt request.

Any logical change on INTn generates an interrupt request

The falling edge between two samples of INTn generates an interrupt request.

The rising edge between two samples of INTn generates an interrupt request.

Note:

1. n = 7, 6, 5 or 4.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

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11.0.3

External Interrupt Mask Register – EIMSK

Bit

7

6

INT6

R/W

0

5

INT5

R/W

0

4

INT4

R/W

0

3

2

1

0

INT7

R/W

0

INT3

R/W

0

INT2

R/W

0

INT1

R/W

0

IINT0

R/W

0

EIMSK

Read/Write

Initial Value

• Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable

When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set

(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the

External Interrupt Control Registers – EICRA and EICRB – defines whether the external inter-

rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger

an interrupt request even if the pin is enabled as an output. This provides a way of generating a

software interrupt.

11.0.4

External Interrupt Flag Register – EIFR

Bit

7

6

5

INTF5

R/W

0

4

INTF4

R/W

0

3

INTF3

R/W

0

2

INTF2

R/W

0

1

INTF1

R/W

0

IINTF0

R/W

0

INTF7

R/W

0

INTF6

R/W

0

EIFR

Read/Write

Initial Value

• Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0

When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes

set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are

set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine

is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are

always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep

mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This

may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input

Enable and Sleep Modes” on page 70 for more information.

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12. Timer/Counter3/1/0 Prescalers

Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the

Timer/Counters can have different prescaler settings. The description below applies to both

Timer/Counter3, Timer/Counter1 and Timer/Counter0.

12.1 Overview

Most bit references in this section are written in general form. A lower case “n” replaces the

Timer/Counter number.

12.1.1

Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/64, f_{CLK_I/O}/256, or

f

_{CLK_I/O}/1024.

12.1.2

Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the

Timer/Counter, and it is shared by Timer/Counter3, Timer/Counter1 and Timer/Counter0. Since

the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will

have implications for situations where a prescaled clock is used. One example of prescaling arti-

facts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The

number of system clock cycles from when the timer is enabled to the first count occurs can be

from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-

tion. However, care must be taken if the other Timer/Counter that shares the same prescaler

also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is

connected to.

12.1.3

External Clock Source

An external clock source applied to the T3/T1/T0 pin can be used as Timer/Counter clock

(clk_T3/clk_T1/clk_T0). The T3/T1/T0 pin is sampled once every system clock cycle by the pin syn-

chronization logic. The synchronized (sampled) signal is then passed through the edge detector.

Figure 12-1 shows a functional equivalent block diagram of the T3/T1/T0 synchronization and

edge detector logic. The registers are clocked at the positive edge of the internal system clock

(clk_I/O). The latch is transparent in the high period of the internal system clock.

The edge detector generates one clk_T3/clk_T1/clk_T0pulse for each positive (CSn2:0 = 7) or nega-

tive (CSn2:0 = 6) edge it detects.

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Figure 12-1. T3/T1/T0 Pin Sampling

Tn_sync

(To Clock

Tn

D

Q

D

Q

D

Q

Select Logic)

LE

clk_I/O

Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T3/T1/T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T3/T1/T0 has been stable for at

least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is

generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f_ExtClk< f_{clk_I/O}/2) given a 50/50 % duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.

An external clock source can not be prescaled.

Figure 12-2. Prescaler for Timer/Counter3, Timer/Counter1 and Timer/Counter0 ⁽¹⁾

CK

10-BIT T/C PRESCALER

Clear

PSR310

T3

T1

Synchronization

T0

0

CS00

CS01

CS02

CS10

CS11

CS12

CS30

CS31

CS32

TIMER/COUNTER0 CLOCK SOURCE

clk_T0

TIMER/COUNTER1 CLOCK SOURCE

clk_T1

TIMER/COUNTER3 CLOCK SOURCE

clk_T3

Note:

1. The synchronization logic on the input pins (T0/T1/T3) is shown in Figure 12-1.

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12.2 Timer/Counter0/1/3 Prescalers Register Description

12.2.1

General Timer/Counter Control Register – GTCCR

Bit

7

TSM

R

6

–

5

–

4

–

3

–

2

–

1

PSR2

R/W

0

PSR310

R/W

0

GTCCR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSR2 and PSR310 bits is kept, hence keeping the corresponding

prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted

and can be configured to the same value without the risk of one of them advancing during con-

figuration. When the TSM bit is written to zero, the PSR2 and PSR310 bits are cleared by

hardware, and the Timer/Counters start counting simultaneously.

• Bit 0 – PSR310: Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0

When this bit is one, Timer/Counter3, Timer/Counter1 and Timer/Counter0 prescaler will be

Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note

that Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset

of this prescaler will affect these three timers.

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13. 8-bit Timer/Counter0 with PWM

Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main

features are:

13.1 Features

• Single Channel Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• External Event Counter

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)

13.2 Overview

Many register and bit references in this section are written in general form.

• A lower case “n” replaces the Timer/Counter number, in this case 0. However, when using

the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for

accessing Timer/Counter0 counter value and so on.

• A lower case “x” replaces the Output Compare unit channel, in this case A. However, when

using the register or bit defines in a program, the precise form must be used, i.e., OCR0A for

accessing Timer/Counter0 output compare channel A value and so on.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 13-1. For the actual

placement of I/O pins, refer to “Pinout AT90CAN32/64 - TQFP” on page 5. CPU accessible I/O

Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register

and bit locations are listed in the “8-bit Timer/Counter Register Description” on page 109.

Figure 13-1. 8-bit Timer/Counter Block Diagram

TCCRn

count

clear

direction

TOVn

(Int.Req.)

Control Logic

Clock Select

clk

Tn

Edge

Detector

Tn

BOTTOM

TOP

( From Prescaler )

Timer/Counter

TCNTn

= 0

= 0xFF

OCn

(Int.Req.)

Waveform

Generation

OCnx

=

OCRnx

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13.2.1

Registers

The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter-

rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt

Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Reg-

ister (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk_T0).

The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the Waveform Generator to gener-

ate a PWM or variable frequency output on the Output Compare pin (OC0A). See “Output

Compare Unit” on page 101. for details. The compare match event will also set the Compare

Flag (OCF0A) which can be used to generate an Output Compare interrupt request.

13.2.2

Definitions

The following definitions are used extensively throughout the section:

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes 0x00.

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR0A Register. The assignment is depen-

dent on the mode of operation.

13.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits

located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and pres-

caler, see “Timer/Counter3/1/0 Prescalers” on page 96.

13.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

13-2 shows a block diagram of the counter and its surroundings.

Figure 13-2. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

Clock Select

count

clear

Edge

Detector

Tn

clk_Tn

TCNTn

Control Logic

direction

( From Prescaler )

bottom

top

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Signal description (internal signals):

count

direction

clear

Increment or decrement TCNT0 by 1.

Select between increment and decrement.

Clear TCNT0 (set all bits to zero).

clk_Tn

Timer/Counter clock, referred to as clk_T0in the following.

Signalize that TCNT0 has reached maximum value.

Signalize that TCNT0 has reached minimum value (zero).

top

bottom

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T0). clk_T0can be generated from an external or internal clock source,

selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the

timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of

whether clk_T0is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0A). There are close connections between how the

counter behaves (counts) and how waveforms are generated on the Output Compare output

OC0A. For more details about advanced counting sequences and waveform generation, see

“Modes of Operation” on page 104.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by

the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

13.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Register

(OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set

the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and

Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare

interrupt. The OCF0A flag is automatically cleared when the interrupt is executed. Alternatively,

the OCF0A flag can be cleared by software by writing a logical one to its I/O bit location. The

Waveform Generator uses the match signal to generate an output according to operating mode

set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom sig-

nals are used by the Waveform Generator for handling the special cases of the extreme values

in some modes of operation (See “Modes of Operation” on page 104.).

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Figure 13-3 shows a block diagram of the Output Compare unit.

Figure 13-3. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

=

(8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

FOCn

Waveform Generator

OCnx

WGMn1:0

COMnX1:0

The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-

ering is disabled. The double buffering synchronizes the update of the OCR0A Compare

Register to either top or bottom of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0A Register access may seem complex, but this is not case. When the double buffer-

ing is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is

disabled the CPU will access the OCR0A directly.

13.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the

OCF0A flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare

match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or

toggled).

13.5.2

13.5.3

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initial-

ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT0 when using the Output Compare channel,

independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform

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generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

downcounting.

The setup of the OC0A should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com-

pare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COM0A1:0 bits are not double buffered together with the compare value.

Changing the COM0A1:0 bits will take effect immediately.

13.6 Compare Match Output Unit

The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator

uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare

match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 13-4 shows a sim-

plified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits,

and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis-

ters (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the

OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. If a system reset

occur, the OC0A Register is reset to “0”.

Figure 13-4. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

13.6.1

Compare Output Function

The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform

Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is vis-

ible on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0A state before the

output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of

operation. See “8-bit Timer/Counter Register Description” on page 109.

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13.6.2

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM

modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on

the OC0A Register is to be performed on the next compare match. For compare output actions

in the non-PWM modes refer to Table 13-2 on page 110. For fast PWM mode, refer to Table 13-

3 on page 110, and for phase correct PWM refer to Table 13-4 on page 111.

A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC0A strobe bits.

13.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output

mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM0A1:0 bits control whether the PWM

output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM

modes the COM0A1:0 bits control whether the output should be set, cleared, or toggled at a

compare match (See “Compare Match Output Unit” on page 103.).

For detailed timing information refer to Figure 13-8, Figure 13-9, Figure 13-10 and Figure 13-11

in “Timer/Counter Timing Diagrams” on page 108.

13.7.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same

timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV0 flag, the timer resolution can be increased by software. There

are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

13.7.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the compare match output frequency. It

also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 13-5. The counter value (TCNT0)

increases until a compare match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

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Figure 13-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCnx

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the

TOP value. However, changing TOP to a value close to BOTTOM when the counter is running

with none or a low prescaler value must be done with care since the CTC mode does not have

the double buffering feature. If the new value written to OCR0A is lower than the current value of

TCNT0, the counter will miss the compare match. The counter will then have to count to its max-

imum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of f_OC0A

_{clk_I/O}/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

equation:

=

f

clk_I/O

2 ⋅ ⋅ (1

)

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

13.7.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency

PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-

gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In

non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare

match between TCNT0 and OCR0A, and set at BOTTOM. In inverting Compare Output mode,

the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation,

the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 13-6. The TCNT0 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

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inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare

matches between OCR0A and TCNT0.

Figure 13-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.

Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM0A1:0 to three (See Table 13-3 on page 110). The actual

OC0A value will only be visible on the port pin if the data direction for the port pin is set as out-

put. The PWM waveform is generated by setting (or clearing) the OC0A Register at the compare

match between OCR0A and TCNT0, and clearing (or setting) the OC0A Register at the timer

clock cycle the counter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

clk_I/O

⋅ 256

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The waveform

generated will have a maximum frequency of f_OC0A= f_{clk_I/O}/2 when OCR0A is set to zero. This

feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

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13.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM

waveform generation option. The phase correct PWM mode is based on a dual-slope operation.

The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-

inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match

between TCNT0 and OCR0A while upcounting, and set on the compare match while down-

counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation

has lower maximum operation frequency than single slope operation. However, due to the sym-

metric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct

PWM mode the counter is incremented until the counter value matches MAX. When the counter

reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one

timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 13-7.

The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0.

Figure 13-7. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM0A1:0 to three (See Table 13-4 on page 111).

The actual OC0A value will only be visible on the port pin if the data direction for the port pin is

set as output. The PWM waveform is generated by clearing (or setting) the OC0A Register at the

compare match between OCR0A and TCNT0 when the counter increments, and setting (or

clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter

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decrements. The PWM frequency for the output when using phase correct PWM can be calcu-

lated by the following equation:

clk_I/O

⋅ 510

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

13.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when interrupt

flags are set. Figure 13-8 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

Figure 13-8. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 13-9 shows the same timing data, but with the prescaler enabled.

Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

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Figure 13-10 shows the setting of OCF0A in all modes except CTC mode.

Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 13-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.

Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

13.9 8-bit Timer/Counter Register Description

13.9.1

Timer/Counter0 Control Register A – TCCR0A

Bit

7

FOC0A

W

6

5

4

3

2

CS02

R/W

0

1

0

CS00

R/W

0

WGM00 COM0A1 COM0A0 WGM01

CS01

TCCR0A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for

ensuring compatibility with future devices, this bit must be set to zero when TCCR0A is written

when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com-

pare match is forced on the Waveform Generation unit. The OC0A output is changed according

to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is

the value present in the COM0A1:0 bits that determines the effect of the forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0A as TOP.

The FOC0A bit is always read as zero.

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• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum (TOP)

counter value, and what type of waveform generation to be used. Modes of operation supported

by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and

two types of Pulse Width Modulation (PWM) modes. See Table 13-1 and “Modes of Operation”

on page 104.

Table 13-1. Waveform Generation Mode Bit Description⁽¹⁾

WGM01

(CTC0)

WGM00

(PWM0)

Timer/Counter

Mode of Operation

Update of

OCR0A at

TOV0 Flag

Set on

Mode

TOP

0

1

2

3

0

1

0

1

0

1

Normal

0xFF

Immediate

TOP

MAX

PWM, Phase Correct

CTC

0xFF

BOTTOM

MAX

OCR0A

0xFF

Immediate

TOP

Fast PWM

MAX

Note:

1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.

However, the functionality and location of these bits are compatible with previous versions of

the timer.

• Bit 5:4 – COM01:0: Compare Match Output Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM01:0 bit setting. Table 13-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits

are set to a normal or CTC mode (non-PWM).

Table 13-2. Compare Output Mode, non-PWM Mode

COM0A1

COM0A0

Description

0

1

0

1

0

1

Normal port operation, OC0A disconnected.

Toggle OC0A on compare match

Clear OC0A on compare match

Set OC0A on compare match

Table 13-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM

mode.

Table 13-3. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

1

Normal port operation, OC0A disconnected.

Reserved

Clear OC0A on compare match.

Set OC0A at TOP

1

0

1

Set OC0A on compare match.

Clear OC0A at TOP

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Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-

pare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 105

for more details.

Table 13-4 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-

rect PWM mode.

Table 13-4. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

1

Normal port operation, OC0A disconnected.

Reserved

Clear OC0A on compare match when up-counting.

Set OC0A on compare match when downcounting.

1

0

1

Set OC0A on compare match when up-counting.

Clear OC0A on compare match when downcounting.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-

pare match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 107 for more details.

• Bit 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

Table 13-5. Clock Select Bit Description

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped)

clk_I/O/(No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

13.9.2

Timer/Counter0 Register – TCNT0

Bit

7

6

5

4

3

2

1

0

TCNT0[7:0]

TCNT0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare

match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,

introduces a risk of missing a compare match between TCNT0 and the OCR0A Register.

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13.9.3

Output Compare Register A – OCR0A

Bit

7

6

5

4

3

2

1

0

OCR0A[7:0]

R/W R/W

OCR0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC0A pin.

13.9.4

Timer/Counter0 Interrupt Mask Register – TIMSK0

Bit

7

6

5

4

–

3

–

2

–

1

OCIE0A

R/W

0

TOIE0

R/W

0

–

TIMSK0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7..2 – Reserved Bits

These are reserved bits for future use.

• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

13.9.5

Timer/Counter0 Interrupt Flag Register – TIFR0

Bit

7

6

5

4

–

3

–

2

–

1

OCF0A

R/W

0

TOV0

R/W

0

–

TIFR0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 1 – OCF0A: Output Compare Flag 0 A

The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the

data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare match Interrupt

Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-

rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In

phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at

0x00.

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14. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)

The 16-bit Timer/Counter unit allows accurate program execution timing (event management),

wave generation, and signal timing measurement. The main features are:

14.1 Features

• True 16-bit Design (i.e., Allows 16-bit PWM)

• Three independent Output Compare Units

• Double Buffered Output Compare Registers

• One Input Capture Unit

• Input Capture Noise Canceler

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• External Event Counter

• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1 for Timer/Counter1 - TOV3,

OCF3A, OCF3B, and ICF3 for Timer/Counter3)

14.2 Overview

Many register and bit references in this section are written in general form.

• A lower case “n” replaces the Timer/Counter number, in this case 1 or 3. However, when

using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for

accessing Timer/Counter1 counter value and so on.

• A lower case “x” replaces the Output Compare unit channel, in this case A, B or C. However,

when using the register or bit defines in a program, the precise form must be used, i.e.,

OCRnA for accessing Timer/Countern output compare channel A value and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 14-1. For the actual

placement of I/O pins, refer to “Pinout AT90CAN32/64 - TQFP” on page 5. CPU accessible I/O

Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register

and bit locations are listed in the “16-bit Timer/Counter Register Description” on page 135.

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Figure 14-1. 16-bit Timer/Counter Block Diagram⁽¹⁾

Count

TOVn

(Int.Req.)

Clear

Control Logic

Direction

clk_Tn

Clock Select

Edge

Detector

Tn

TOP BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

= 0

OCFnA

(Int.Req.)

Waveform

Generation

OCnA

OCnB

OCnC

=

OCRnA

OCFnB

(Int.Req.)

Fixed

TOP

Values

Waveform

Generation

=

OCRnB

OCFnC

(Int.Req.)

Waveform

Generation

=

OCRnC

( From Analog

Comparator Ouput )

ICFn (Int.Req.)

Edge

Detector

Noise

Canceler

ICRn

ICPn

TCCRnA

TCCRnB

TCCRnC

Note:

1. Refer to Figure 2-2 on page 5, Table 10-6 on page 76, and Table 10-15 on page 83 for

Timer/Counter1 and 3 pin placement and description.

14.2.1

Registers

The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture Register

(ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit

registers. These procedures are described in the section “Accessing 16-bit Registers” on page

116. The Timer/Counter Control Registers (TCCRnx) are 8-bit registers and have no CPU

access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible

in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer

Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

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uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk ).

n

T

The double buffered Output Compare Registers (OCRnx) are compared with the Timer/Counter

value at all time. The result of the compare can be used by the Waveform Generator to generate

a PWM or variable frequency output on the Output Compare pin (OCnx). See “Output Compare

Units” on page 123.. The compare match event will also set the Compare Match Flag (OCFnx)

which can be used to generate an Output Compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-

gered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See

“Analog Comparator” on page 268.) The Input Capture unit includes a digital filtering unit (Noise

Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined

by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using

OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a

PWM output. However, the TOP value will in this case be double buffered allowing the TOP

value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used

as an alternative, freeing the OCRnA to be used as PWM output.

14.2.2

Definitions

The following definitions are used extensively throughout the section:

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes 0x0000.

The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65,535).

The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF,

or 0x03FF, or to the value stored in the OCRnA or ICRn Register. The assignment is

dependent of the mode of operation.

TOP

14.2.3

Compatibility

The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit

AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version

regarding:

• All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt

Registers.

• Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.

• Interrupt Vectors.

The following control bits have changed name, but have same functionality and register location:

• PWMn0 is changed to WGMn0.

• PWMn1 is changed to WGMn1.

• CTCn is changed to WGMn2.

The following registers are added to the 16-bit Timer/Counter:

• Timer/Counter Control Register C (TCCRnC).

• Output Compare Register C, OCRnCH and OCRnCL, combined OCRnC.

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The 16-bit Timer/Counter has improvements that will affect the compatibility in some special

cases.

The following bits are added to the 16-bit Timer/Counter Control Registers:

• COMnC1:0 are added to TCCRnA.

• FOCnA, FOCnB and FOCnC are added to TCCRnC.

• WGMn3 is added to TCCRnB.

Interrupt flag and mask bits for output compare unit C are added.

The 16-bit Timer/Counter has improvements that will affect the compatibility in some special

cases.

14.3 Accessing 16-bit Registers

The TCNTn, OCRnx, and ICRn are 16-bit registers that can be accessed by the AVR CPU via

the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.

Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit

access. The same temporary register is shared between all 16-bit registers within each 16-bit

timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a

16-bit register is written by the CPU, the high byte stored in the temporary register, and the low

byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of

a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the tempo-

rary register in the same clock cycle as the low byte is read.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCRnx 16-bit

registers does not involve using the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low

byte must be read before the high byte.

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14.3.1

Code Examples

The following code examples show how to access the 16-bit timer registers assuming that no

interrupts updates the temporary register. The same principle can be used directly for accessing

the OCRnx and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit

access.

Assembly Code Examples⁽¹⁾

...

; Set TCNTn to 0x01FF

ldi

sts

r17,0x01

r16,0xFF

TCNTnH,r17

TCNTnL,r16

; Read TCNTn into r17:r16

lds

...

r16,TCNTnL

r17,TCNTnH

C Code Examples⁽¹⁾

unsigned int i;

...

/* Set TCNTn to 0x01FF */

TCNTn = 0x1FF;

/* Read TCNTn into i */

i = TCNTn;

...

Note:

1. The example code assumes that the part specific header file is included.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 16-bit register, and the interrupt code

updates the temporary register by accessing the same or any other of the 16-bit timer registers,

then the result of the access outside the interrupt will be corrupted. Therefore, when both the

main code and the interrupt code update the temporary register, the main code must disable the

interrupts during the 16-bit access.

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The following code examples show how to do an atomic read of the TCNTn Register contents.

Reading any of the OCRnx or ICRn Registers can be done by using the same principle.

Assembly Code Example⁽¹⁾

TIM16_ReadTCNTn:

; Save global interrupt flag

in

r18,SREG

; Disable interrupts

cli

; Read TCNTn into r17:r16

lds

r16,TCNTnL

r17,TCNTnH

; Restore global interrupt flag

out

ret

SREG,r18

C Code Example⁽¹⁾

unsigned int TIM16_ReadTCNTn(void)

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNTn into i */

i = TCNTn;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

Note:

1. The example code assumes that the part specific header file is included.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

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The following code examples show how to do an atomic write of the TCNTn Register contents.

Writing any of the OCRnx or ICRn Registers can be done by using the same principle.

Assembly Code Example⁽¹⁾

TIM16_WriteTCNTn:

; Save global interrupt flag

in

r18,SREG

; Disable interrupts

cli

; Set TCNTn to r17:r16

sts

TCNTnH,r17

TCNTnL,r16

; Restore global interrupt flag

out

ret

SREG,r18

C Code Example⁽¹⁾

void TIM16_WriteTCNTn(unsigned int i)

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNTn to i */

TCNTn = i;

/* Restore global interrupt flag */

SREG = sreg;

}

Note:

1. The example code assumes that the part specific header file is included.

The assembly code example requires that the r17:r16 register pair contains the value to be writ-

ten to TCNTn.

14.3.2

Reusing the Temporary High Byte Register

If writing to more than one 16-bit register where the high byte is the same for all registers written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previously also applies in this case.

14.4 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits

located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and

prescaler, see “Timer/Counter3/1/0 Prescalers” on page 96.

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14.5 Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.

Figure 14-2 shows a block diagram of the counter and its surroundings.

Figure 14-2. Counter Unit Block Diagram

DATA BUS (8-bit)

TOVn

(Int.Req.)

TEMP (8-bit)

Clock Select

Edge

Count

Tn

Detector

TCNTnH (8-bit)

TCNTnL (8-bit)

Clear

clk_Tn

Control Logic

Direction

TCNTn (16-bit Counter)

( From Prescaler )

TOP BOTTOM

Signal description (internal signals):

Count

Increment or decrement TCNTn by 1.

Select between increment and decrement.

Clear TCNTn (set all bits to zero).

Timer/Counter clock.

Direction

Clear

clk_T

n

TOP

Signalize that TCNTn has reached maximum value.

BOTTOM

Signalize that TCNTn has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-

taining the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight

bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an

access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP).

The temporary register is updated with the TCNTnH value when the TCNTnL is read, and

TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the

CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.

It is important to notice that there are special cases of writing to the TCNTn Register when the

counter is counting that will give unpredictable results. The special cases are described in the

sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk ). The clk _ncan be generated from an external or internal clock source,

n

T

selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the

timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of

whether clk_Tis present or not. A CPU write overrides (has priority over) all counter clear or

n

count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bits

(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).

There are close connections between how the counter behaves (counts) and how waveforms

are generated on the Output Compare outputs OCnx. For more details about advanced counting

sequences and waveform generation, see “Modes of Operation” on page 126.

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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by

the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.

14.6 Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events and give

them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-

tiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit. The

time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-

nal applied. Alternatively the time-stamps can be used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 14-3. The elements of

the block diagram that are not directly a part of the Input Capture unit are gray shaded.

Figure 14-3. Input Capture Unit Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

ICRnH (8-bit)

ICRnL (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

ICRn (16-bit Register)

TCNTn (16-bit Counter)

WRITE

ICNC3

ICES3

Noise

Canceler

Edge

Detector

ICP3

ICP1

ICF3 (Int.Req.)

ICF1 (Int.Req.)

ACIC*

ICNC1

ICES1

Noise

Canceler

Edge

Detector

ACO*

Analog

Comparator

Note:

The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 IC Unit– not

Timer/Counter3.

When a change of the logic level (an event) occurs on the Input Capture pin (ICPn), alternatively

on the Analog Comparator output (ACO), and this change confirms to the setting of the edge

detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter

(TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at

the same system clock as the TCNTn value is copied into ICRn Register. If enabled (ICIEn = 1),

the Input Capture Flag generates an Input Capture interrupt. The ICFn flag is automatically

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cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by

writing a logical one to its I/O bit location.

Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low

byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied

into the high byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will

access the TEMP Register.

The ICRn Register can only be written when using a Waveform Generation mode that utilizes

the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera-

tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn

Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location

before the low byte is written to ICRnL.

For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 116.

14.6.1

Input Capture Trigger Source

The main trigger source for the Input Capture unit is the Input Capture pin (ICPn). Only

Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the

Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog

Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register

(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag

must therefore be cleared after the change.

Both the Input Capture pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled

using the same technique as for the Tn pin (Figure 12-1 on page 97). The edge detector is also

identical. However, when the noise canceler is enabled, additional logic is inserted before the

edge detector, which increases the delay by four system clock cycles. Note that the input of the

noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-

form Generation mode that uses ICRn to define TOP.

An Input Capture can be triggered by software by controlling the port of the ICPn pin.

14.6.2

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in

Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces addi-

tional four system clock cycles of delay from a change applied to the input, to the update of the

ICRn Register. The noise canceler uses the system clock and is therefore not affected by the

prescaler.

14.6.3

Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity

for handling the incoming events. The time between two events is critical. If the processor has

not read the captured value in the ICRn Register before the next event occurs, the ICRn will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICRn Register should be read as early in the inter-

rupt handler routine as possible. Even though the Input Capture interrupt has relatively high

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priority, the maximum interrupt response time is dependent on the maximum number of clock

cycles it takes to handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution) is

actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after

each capture. Changing the edge sensing must be done as early as possible after the ICRn

Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be

cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the clearing of the ICFn flag is not required (if an interrupt handler is used).

14.7 Output Compare Units

The 16-bit comparator continuously compares TCNTn with the Output Compare Register

(OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output

Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Com-

pare Flag generates an Output Compare interrupt. The OCFnx flag is automatically cleared

when the interrupt is executed. Alternatively the OCFnx flag can be cleared by software by writ-

ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to

generate an output according to operating mode set by the Waveform Generation mode

(WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals

are used by the Waveform Generator for handling the special cases of the extreme values in

some modes of operation (See “Modes of Operation” on page 126.)

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,

counter resolution). In addition to the counter resolution, the TOP value defines the period time

for waveforms generated by the Waveform Generator.

Figure 14-4 shows a block diagram of the Output Compare unit. The elements of the block dia-

gram that are not directly a part of the Output Compare unit are gray shaded.

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Figure 14-4. Output Compare Unit, Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

OCRnxH Buf.(8-bit)

OCRnxL Buf.(8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

OCRnx Buffer (16-bit Register)

TCNTn (16-bit Counter)

OCRnxH (8-bit)

OCRnxL (8-bit)

OCRnx (16-bit Register)

= (16-bit Comparator )

OCFnx

(Int.Req.)

TOP

Waveform Generator

OCnx

BOTTOM

WGMn3:0

COMnx1:0

The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation

(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the

double buffering is disabled. The double buffering synchronizes the update of the OCRnx Com-

pare Register to either TOP or BOTTOM of the counting sequence. The synchronization

prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out-

put glitch-free.

The OCRnx Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is dis-

abled the CPU will access the OCRnx directly. The content of the OCRnx (Buffer or Compare)

Register is only changed by a write operation (the Timer/Counter does not update this register

automatically as the TCNT1 and ICRn Register). Therefore OCRnx is not read via the high byte

temporary register (TEMP). However, it is a good practice to read the low byte first as when

accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Reg-

ister since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be

written first. When the high byte I/O location is written by the CPU, the TEMP Register will be

updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits,

the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare

Register in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 116.

14.7.1

Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the

OCFnx flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare

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match had occurred (the COMnx1:0 bits settings define whether the OCnx pin is set, cleared or

toggled).

14.7.2

14.7.3

Compare Match Blocking by TCNTn Write

All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer

clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the

same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.

Using the Output Compare Unit

Since writing TCNTn in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNTn when using any of the Output Compare

channels, independent of whether the Timer/Counter is running or not. If the value written to

TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect wave-

form generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP

values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.

Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting.

The setup of the OCnx should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OCnx value is to use the Force Output Com-

pare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COMnx1:0 bits are not double buffered together with the compare value.

Changing the COMnx1:0 bits will take effect immediately.

14.8 Compare Match Output Unit

The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses

the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match.

Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 14-5 shows a simplified

schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR

and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx

state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset occur,

the OCnx Register is reset to “0”.

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Figure 14-5. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

14.8.1

Compare Output Function

The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform

Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visi-

ble on the pin. The port override function is generally independent of the Waveform Generation

mode, but there are some exceptions. Refer to Table 14-1, Table 14-2 and Table 14-3 for

details.

The design of the Output Compare pin logic allows initialization of the OCnx state before the out-

put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of

operation. See “16-bit Timer/Counter Register Description” on page 135.

The COMnx1:0 bits have no effect on the Input Capture unit.

14.8.2

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the

OCnx Register is to be performed on the next compare match. For compare output actions in the

non-PWM modes refer to Table 14-1 on page 136. For fast PWM mode refer to Table 14-2 on

page 136, and for phase correct and phase and frequency correct PWM refer to Table 14-3 on

page 137.

A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOCnx strobe bits.

14.9 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output

mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence,

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while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare

match (See “Compare Match Output Unit” on page 125.)

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 134.

14.9.1

Normal Mode

The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in

the same timer clock cycle as the TCNTn becomes zero. The TOVn flag in this case behaves

like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow

interrupt that automatically clears the TOVn flag, the timer resolution can be increased by soft-

ware. There are no special cases to consider in the Normal mode, a new counter value can be

written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maximum

interval between the external events must not exceed the resolution of the counter. If the interval

between events are too long, the timer overflow interrupt or the prescaler must be used to

extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using the

Output Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

14.9.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register

are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 =

12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This

mode allows greater control of the compare match output frequency. It also simplifies the opera-

tion of counting external events.

The timing diagram for the CTC mode is shown in Figure 14-6. The counter value (TCNTn)

increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn)

is cleared.

Figure 14-6. CTC Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

OCnA

(Toggle)

(COMnA1:0 = 1)

1

2

3

4

Period

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An interrupt can be generated at each time the counter value reaches the TOP value by either

using the OCFnA or ICFn flag according to the register used to define the TOP value. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,

changing the TOP to a value close to BOTTOM when the counter is running with none or a low

prescaler value must be done with care since the CTC mode does not have the double buffering

feature. If the new value written to OCRnA or ICRn is lower than the current value of TCNTn, the

counter will miss the compare match. The counter will then have to count to its maximum value

(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many

cases this feature is not desirable. An alternative will then be to use the fast PWM mode using

OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered.

For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for

the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum fre-

quency of f_{OC A}= f_{clk_I/O}/2 when OCRnA is set to zero (0x0000). The waveform frequency is

n

defined by the following equation:

clk_I/O

2 ⋅ ⋅ (1

)

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOVn flag is set in the same timer clock cycle that the

counter counts from MAX to 0x0000.

14.9.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a

high frequency PWM waveform generation option. The fast PWM differs from the other PWM

options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts

from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is set on

the compare match between TCNTn and OCRnx, and cleared at TOP. In inverting Compare

Output mode output is cleared on compare match and set at TOP. Due to the single-slope oper-

ation, the operating frequency of the fast PWM mode can be twice as high as the phase correct

and phase and frequency correct PWM modes that use dual-slope operation. This high fre-

quency makes the fast PWM mode well suited for power regulation, rectification, and DAC

applications. High frequency allows physically small sized external components (coils, capaci-

tors), hence reduces total system cost.

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or

OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the max-

imum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be

calculated by using the following equation:

log(

log(2)

1)

In fast PWM mode the counter is incremented until the counter value matches either one of the

fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 =

14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer

clock cycle. The timing diagram for the fast PWM mode is shown in Figure 14-7. The figure

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shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the

timing diagram shown as a histogram for illustrating the single-slope operation. The diagram

includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn

slopes represent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be

set when a compare match occurs.

Figure 14-7. Fast PWM Mode, Timing Diagram

OCRnx/TOP Update and

TOVn Interrupt Flag Set and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

8

Period

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition

the OCnA or ICFn flag is set at the same timer clock cycle as TOVn is set when either OCRnA or

ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han-

dler routine can be used for updating the TOP and compare values.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.

Note that when using fixed TOP values the unused bits are masked to zero when any of the

OCRnx Registers are written.

The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP

value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low

value when the counter is running with none or a low prescaler value, there is a risk that the new

ICRn value written is lower than the current value of TCNTn. The result will then be that the

counter will miss the compare match at the TOP value. The counter will then have to count to the

MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.

The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location

to be written anytime. When the OCRnA I/O location is written the value written will be put into

the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value

in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done

at the same timer clock cycle as the TCNTn is cleared and the TOVn flag is set.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By using

ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,

if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA

as TOP is clearly a better choice due to its double buffer feature.

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In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.

Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COMnx1:0 to three (see Table on page 136). The actual OCnx

value will only be visible on the port pin if the data direction for the port pin is set as output

(DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at

the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at

the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

clk_I/O

⋅ (1

)

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCRnx Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the out-

put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP

will result in a constant high or low output (depending on the polarity of the output set by the

COMnx1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). The waveform

generated will have a maximum frequency of f_{OC A}= f_{clk_I/O}/2 when OCRnA is set to zero

n

(0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer fea-

ture of the Output Compare unit is enabled in the fast PWM mode.

14.9.4

Phase Correct PWM Mode

The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3,

10, or 11) provides a high resolution phase correct PWM waveform generation option. The

phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-

slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from

TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is

cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the

compare match while downcounting. In inverting Output Compare mode, the operation is

inverted. The dual-slope operation has lower maximum operation frequency than single slope

operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes

are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined

by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to

0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolu-

tion in bits can be calculated by using the following equation:

log(

log(2)

1)

In phase correct PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn

(WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the

TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock

cycle. The timing diagram for the phase correct PWM mode is shown on Figure 14-8. The figure

shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn

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value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The

diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on

the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx inter-

rupt flag will be set when a compare match occurs.

Figure 14-8. Phase Correct PWM Mode, Timing Diagram

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When

either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag is set accord-

ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer

value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter

reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.

Note that when using fixed TOP values, the unused bits are masked to zero when any of the

OCRnx Registers are written. As the third period shown in Figure 14-8 illustrates, changing the

TOP actively while the Timer/Counter is running in the phase correct mode can result in an

unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Reg-

ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This

implies that the length of the falling slope is determined by the previous TOP value, while the

length of the rising slope is determined by the new TOP value. When these two values differ the

two slopes of the period will differ in length. The difference in length gives the unsymmetrical

result on the output.

It is recommended to use the phase and frequency correct mode instead of the phase correct

mode when changing the TOP value while the Timer/Counter is running. When using a static

TOP value there are practically no differences between the two modes of operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on the

OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted

PWM output can be generated by setting the COMnx1:0 to three (See Table on page 137). The

actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as

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output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Regis-

ter at the compare match between OCRnx and TCNTn when the counter increments, and

clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when

the counter decrements. The PWM frequency for the output when using phase correct PWM can

be calculated by the following equation:

clk_I/O

2 ⋅

⋅

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCRnx Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

14.9.5

Phase and Frequency Correct PWM Mode

The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM

mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-

form generation option. The phase and frequency correct PWM mode is, like the phase correct

PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the

Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while

upcounting, and set on the compare match while downcounting. In inverting Compare Output

mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-

quency compared to the single-slope operation. However, due to the symmetric feature of the

dual-slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct PWM

mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 14-

8 and Figure 14-9).

The PWM resolution for the phase and frequency correct PWM mode can be defined by either

ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and

the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can

be calculated using the following equation:

log(

log(2)

1)

In phase and frequency correct PWM mode the counter is incremented until the counter value

matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The

counter has then reached the TOP and changes the count direction. The TCNTn value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency

correct PWM mode is shown on Figure 14-9. The figure shows phase and frequency correct

PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing dia-

gram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-

inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre-

sent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a

compare match occurs.

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Figure 14-9. Phase and Frequency Correct PWM Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

OCRnx/TOP Update and

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx

Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn

is used for defining the TOP value, the OCnA or ICFn flag set when TCNTn has reached TOP.

The interrupt flags can then be used to generate an interrupt each time the counter reaches the

TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.

As Figure 14-9 shows the output generated is, in contrast to the phase correct mode, symmetri-

cal in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising

and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore

frequency correct.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By using

ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,

if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as

TOP is clearly a better choice due to its double buffer feature.

In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-

forms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and

an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table on

page 137). The actual OCnx value will only be visible on the port pin if the data direction for the

port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing)

the OCnx Register at the compare match between OCRnx and TCNTn when the counter incre-

ments, and clearing (or setting) the OCnx Register at compare match between OCRnx and

TCNTn when the counter decrements. The PWM frequency for the output when using phase

and frequency correct PWM can be calculated by the following equation:

clk_I/O

2 ⋅

⋅

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The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCRnx Register represents special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be set to high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values.

14.10 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_Tn) is therefore shown as a

clock enable signal in the following figures. The figures include information on when interrupt

flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for

modes utilizing double buffering). Figure 14-10 shows a timing diagram for the setting of OCFnx.

Figure 14-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 14-11 shows the same timing data, but with the prescaler enabled.

Figure 14-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 14-12 shows the count sequence close to TOP in various modes. When using phase and

frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams

will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.

The same renaming applies for modes that set the TOVn flag at BOTTOM.

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Figure 14-12. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

New OCRnx Value

Old OCRnx Value

Figure 14-13 shows the same timing data, but with the prescaler enabled.

Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk

I/O

clk

Tn

(clk /8)

I/O

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn(FPWM)

and ICFn(if used

as TOP)

OCRnx

(Update at TOP)

Old OCRnx Value

New OCRnx Value

14.11 16-bit Timer/Counter Register Description

14.11.1 Timer/Counter1 Control Register A – TCCR1A

Bit

7

6

5

4

3

2

1

0

COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11

WGM10 TCCR1A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.11.2 Timer/Counter3 Control Register A – TCCR3A

Bit

7

6

5

4

3

2

1

0

COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31

WGM30 TCCR3A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A

• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B

• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C

The COMnA1:0, COMnB1:0 and COMnC1:0 control the Output Compare pins (OCnA, OCnB

and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the

OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or

both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port func-

tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bit are written to one,

the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-

ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or

OCnC pin must be set in order to enable the output driver.

When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is

dependent of the WGMn3:0 bits setting. Table 14-1 shows the COMnx1:0 bit functionality when

the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).

Table 14-1. Compare Output Mode, non-PWM

COMnA1/COMnB1/

COMnC1

COMnA0/COMnB0/

COMnC0

Description

Normal port operation, OCnA/OCnB/OCnC

disconnected.

0

1

0

1

0

Toggle OCnA/OCnB/OCnC on Compare Match.

Clear OCnA/OCnB/OCnC on Compare Match (Set

output to low level).

Set OCnA/OCnB/OCnC on Compare Match (Set

output to high level).

1

Table 14-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast

PWM mode.

Table 14-2. Compare Output Mode, Fast PWM ⁽¹⁾

COMnA1/COMnB1/

COMnC1

COMnA0/COMnB0/

COMnC0

Description

Normal port operation, OCnA/OCnB/OCnC

disconnected.

0

WGMn3=0: Normal port operation,

OCnA/OCnB/OCnC disconnected.

0

1

WGMn3=1: Toggle OCnA on Compare Match,

OCnB/OCnC reserved.

Clear OCnA/OCnB/OCnC on Compare Match

Set OCnA/OCnB/OCnC at TOP

1

0

1

Set OCnA/OCnB/OCnC on Compare Match

Clear OCnA/OCnB/OCnC at TOP

Note:

1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and

COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or

clear is done at TOP. See “Fast PWM Mode” on page 128. for more details.

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Table 14-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase

correct or the phase and frequency correct, PWM mode.

Table 14-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct

PWM⁽¹⁾

COMnA1/COMnB1/

COMnC1

COMnA0/COMnB0/

COMnC0

Description

Normal port operation, OCnA/OCnB/OCnC

disconnected.

0

WGMn3=0: Normal port operation,

OCnA/OCnB/OCnC disconnected.

0

1

WGMn3=1: Toggle OCnA on Compare Match,

OCnB/OCnC reserved.

Clear OCnA/OCnB/OCnC on Compare Match when

up-counting.

1

0

1

Set OCnA/OCnB/OCnC on Compare Match when

downcounting.

Set OCnA/OCnB/OCnC on Compare Match when up-

counting.

Clear OCnA/OCnB/OCnC on Compare Match when

downcounting.

Note:

1. A special case occurs when OCnA/OCnB/OCnC equals TOP and

COMnA1/COMnB1/COMnC1 is set. See “Phase Correct PWM Mode” on page 130. for more

details.

• Bit 1:0 – WGMn1:0: Waveform Generation Mode

Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 14-4. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types

of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 126.).

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Table 14-4. Waveform Generation Mode Bit Description ⁽¹⁾

WGMn2

(CTCn)

WGMn1

WGMn0

Timer/Counter

Update of

OCRnx at

TOVn Flag

Set on

Mode

WGMn3

TOP

(PWMn1) (PWMn0) Mode of Operation

0

1

2

0

1

0

1

0

Normal

0xFFFF Immediate

MAX

PWM, Phase Correct, 8-bit

PWM, Phase Correct, 9-bit

0x00FF

0x01FF

TOP

BOTTOM

PWM, Phase Correct, 10-

bit

3

0

1

0x03FF

TOP

BOTTOM

4

5

6

7

0

1

0

1

0

1

0

1

CTC

OCRnA

0x00FF

0x01FF

0x03FF

Immediate

TOP

MAX

TOP

Fast PWM, 8-bit

Fast PWM, 9-bit

Fast PWM, 10-bit

TOP

PWM, Phase and

Frequency Correct

8

9

1

0

1

ICRn

BOTTOM

PWM, Phase and

Frequency Correct

OCRnA

10

11

12

13

14

15

1

0

1

0

1

0

1

0

1

0

1

PWM, Phase Correct

CTC

ICRn

OCRnA

ICRn

–

TOP

Immediate

–

BOTTOM

MAX

(Reserved)

–

Fast PWM

ICRn

OCRnA

TOP

Fast PWM

TOP

Note:

1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

14.11.3 Timer/Counter1 Control Register B – TCCR1B

Bit

7

ICNC1

R/W

0

6

ICES1

R/W

0

5

–

4

WGM13

R/W

0

3

WGM12

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

CS10

R/W

0

TCCR1B

Read/Write

Initial Value

R

0

14.11.4 Timer/Counter3 Control Register B – TCCR3B

Bit

7

ICNC3

R/W

0

6

ICES3

R/W

0

5

–

4

WGM33

R/W

0

3

WGM32

R/W

0

2

CS32

R/W

0

1

CS31

R/W

0

CS30

R/W

0

TCCR3B

Read/Write

Initial Value

R

0

• Bit 7 – ICNCn: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is

activated, the input from the Input Capture pin (ICPn) is filtered. The filter function requires four

successive equal valued samples of the ICPn pin for changing its output. The Input Capture is

therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 6 – ICESn: Input Capture Edge Select

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This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture

event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.

When a capture is triggered according to the ICESn setting, the counter value is copied into the

Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this

can be used to cause an Input Capture Interrupt, if this interrupt is enabled.

When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the

TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap-

ture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be

written to zero when TCCRnB is written.

• Bit 4:3 – WGMn3:2: Waveform Generation Mode

See TCCRnA Register description.

• Bit 2:0 – CSn2:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure

14-10 and Figure 14-11.

Table 14-5. Clock Select Bit Description

CSn2

CSn1

CSn0

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped).

clk_I/O/1 (No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on Tn pin. Clock on falling edge.

External clock source on Tn pin. Clock on rising edge.

If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

14.11.5 Timer/Counter1 Control Register C – TCCR1C

Bit

7

6

5

4

–

3

–

2

–

1

–

0

–

FOC1A

FOC1B

FOC1C

R/W

0

TCCR1C

Read/Write

Initial Value

R/W

0

R/W

0

R

0

R

0

R

0

R

0

R

0

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14.11.6 Timer/Counter3 Control Register C – TCCR3C

Bit

7

FOC3A

R/W

0

6

FOC3B

R/W

0

5

FOC3C

R/W

0

4

–

3

–

2

–

1

–

0

–

TCCR3C

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 7 – FOCnA: Force Output Compare for Channel A

• Bit 6 – FOCnB: Force Output Compare for Channel B

• Bit 5 – FOCnC: Force Output Compare for Channel C

The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM

mode. However, for ensuring compatibility with future devices, these bits must be set to zero

when TCCRnA is written when operating in a PWM mode. When writing a logical one to the

FOCnA/FOCnB/FOCnC bit, an immediate compare match is forced on the Waveform Genera-

tion unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting.

Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value

present in the COMnx1:0 bits that determine the effect of the forced compare.

A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear

Timer on Compare match (CTC) mode using OCRnA as TOP.

The FOCnA/FOCnB/FOCnC bits are always read as zero.

14.11.7 Timer/Counter1 – TCNT1H and TCNT1L

Bit

7

6

5

4

3

2

1

0

TCNT1[15:8]

TCNT1[7:0]

TCNT1H

TCNT1L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

14.11.8 Timer/Counter3 – TCNT3H and TCNT3L

Bit

7

6

5

4

3

2

1

0

TCNT3[15:8]

TCNT3[7:0]

TCNT3H

TCNT3L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary high byte register

(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit

Registers” on page 116.

Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-

pare match between TCNTn and one of the OCRnx Registers.

Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock

for all compare units.

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14.11.9 Output Compare Register A – OCR1AH and OCR1AL

Bit

7

6

5

4

3

2

1

0

OCR1A[15:8]

OCR1A[7:0]

OCR1AH

OCR1AL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.11.10 Output Compare Register B – OCR1BH and OCR1BL

Bit

7

6

5

4

3

2

1

0

OCR1B[15:8]

OCR1B[7:0]

OCR1BH

OCR1BL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.11.11 Output Compare Register C – OCR1CH and OCR1CL

Bit

7

6

5

4

3

2

1

0

OCR1C[15:8]

OCR1C[7:0]

OCR1CH

OCR1CL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.11.12 Output Compare Register A – OCR3AH and OCR3AL

Bit

7

6

5

4

3

2

1

0

OCR3A[15:8]

OCR3A[7:0]

OCR3AH

OCR3AL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.11.13 Output Compare Register B – OCR3BH and OCR3BL

Bit

7

6

5

4

3

2

1

0

OCR3B[15:8]

OCR3B[7:0]

OCR3BH

OCR3BL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.11.14 Output Compare Register C – OCR3CH and OCR3CL

Bit

7

6

5

4

3

2

1

0

OCR3C[15:8]

OCR3C[7:0]

OCR3CH

OCR3CL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Registers contain a 16-bit value that is continuously compared with the

counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OCnx pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are

written simultaneously when the CPU writes to these registers, the access is performed using an

8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-

bit registers. See “Accessing 16-bit Registers” on page 116.

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14.11.15 Input Capture Register – ICR1H and ICR1L

Bit

7

6

5

4

3

2

1

0

ICR1[15:8]

ICR1[7:0]

ICR1H

ICR1L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.11.16 Input Capture Register – ICR3H and ICR3L

Bit

7

6

5

4

3

2

1

0

ICR3[15:8]

ICR3[7:0]

ICR3H

ICR3L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the

ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture

can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 116.

14.11.17 Timer/Counter1 Interrupt Mask Register – TIMSK1

Bit

7

6

5

4

–

3

2

1

OCIE1A

R/W

0

TOIE1

R/W

0

–

ICIE1

OCIE1C OCIE1B

TIMSK1

Read/Write

Initial Value

R

0

R

0

R/W

0

R

0

R/W

0

R/W

0

14.11.18 Timer/Counter3 Interrupt Mask Register – TIMSK3

Bit

7

–

6

–

5

ICIE3

R/W

0

4

–

3

2

1

OCIE3A

R/W

0

TOIE3

R/W

0

OCIE3C OCIE3B

TIMSK3

Read/Write

Initial Value

R

0

R

0

R

0

R/W

0

R/W

0

• Bit 7..6 – Reserved Bits

These bits are reserved for future use.

• Bit 5 – ICIEn: Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt

Vector (See “Interrupts” on page 60.) is executed when the ICFn flag, located in TIFRn, is set.

• Bit 4 – Reserved Bit

This bit is reserved for future use.

• Bit 3 – OCIEnC: Output Compare C Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 60.) is executed when the OCFnC flag, located in

TIFRn, is set.

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• Bit 2 – OCIEnB: Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 60.) is executed when the OCFnB flag, located in

TIFRn, is set.

• Bit 1 – OCIEnA: Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 60.) is executed when the OCFnA flag, located in

TIFRn, is set.

• Bit 0 – TOIEn: Timer/Counter Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector

(See “Interrupts” on page 60.) is executed when the TOVn flag, located in TIFRn, is set.

14.11.19 Timer/Counter1 Interrupt Flag Register – TIFR1

Bit

7

6

5

4

–

3

OCF1C

R/W

0

2

OCF1B

R/W

0

1

OCF1A

R/W

0

TOV1

R/W

0

–

ICF1

TIFR1

Read/Write

Initial Value

R

0

R

0

R/W

0

R

0

14.11.20 Timer/Counter3 Interrupt Flag Register – TIFR3

Bit

7

–

6

–

5

ICF3

R/W

0

4

–

3

OCF3C

R/W

0

2

OCF3B

R/W

0

1

OCF3A

R/W

0

TOV3

R/W

0

TIFR3

Read/Write

Initial Value

R

0

R

0

R

0

• Bit 7..6 – Reserved Bits

These bits are reserved for future use.

• Bit 5 – ICFn: Input Capture Flag

This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register

(ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn flag is set when the

counter reaches the TOP value.

ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICFn can be cleared by writing a logic one to its bit location.

• Bit 4 – Reserved Bit

This bit is reserved for future use.

• Bit 3 – OCFnC: Output Compare C Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output

Compare Register C (OCRnC).

Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC flag.

OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe-

cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.

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• Bit 2 – OCFnB: Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output

Compare Register B (OCRnB).

Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB flag.

OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is exe-

cuted. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.

• Bit 1 – OCFnA: Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output

Compare Register A (OCRnA).

Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA flag.

OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is exe-

cuted. Alternatively, OCFnA can be cleared by writing a logic one to its bit location.

• Bit 0 – TOVn: Timer/Counter Overflow Flag

The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,

the TOVn flag is set when the timer overflows. Refer to Table 14-4 on page 138 for the TOVn

flag behavior when using another WGMn3:0 bit setting.

TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed.

Alternatively, TOVn can be cleared by writing a logic one to its bit location.

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15. 8-bit Timer/Counter2 with PWM and Asynchronous Operation

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main

features are:

15.1 Features

• Single Channel Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)

• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

15.2 Overview

Many register and bit references in this section are written in general form.

• A lower case “n” replaces the Timer/Counter number, in this case 2. However, when using

the register or bit defines in a program, the precise form must be used, i.e., TCNT2 for

accessing Timer/Counter2 counter value and so on.

• A lower case “x” replaces the Output Compare unit channel, in this case A. However, when

using the register or bit defines in a program, the precise form must be used, i.e., OCR2A for

accessing Timer/Counter2 output compare channel A value and so on.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 15-1. For the actual

placement of I/O pins, refer to Figure 2-2 on page 5. CPU accessible I/O Registers, including I/O

bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed

in the “8-bit Timer/Counter Register Description” on page 156.

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Figure 15-1. 8-bit Timer/Counter2 Block Diagram

TCCRnx

count

TOVn

(Int.Req.)

clear

Control Logic

direction

clk_Tn

TOSC2

T/C

BOTTOM

TOP

Oscillator

Prescaler

TOSC1

Timer/Counter

TCNTn

= 0

= 0xFF

clk _I/O

OCnx

(Int.Req.)

Waveform

Generation

OCnx

=

OCRnx

clk _I/O

Synchronized Status flags

Synchronization Unit

clk _ASY

Status flags

ASSRn

asynchronous mode

select (ASn)

The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter-

rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register

(TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2).

TIFR2 and TIMSK2 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from

the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by

the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock

source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-

tive when no clock source is selected. The output from the Clock Select logic is referred to as the

timer clock (clk_T2).

The double buffered Output Compare Register (OCR2A) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the Waveform Generator to gener-

ate a PWM or variable frequency output on the Output Compare pin (OC2A). See “Output

Compare Unit” on page 148. for details. The compare match event will also set the compare flag

(OCF2A) which can be used to generate an Output Compare interrupt request.

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15.2.1

Definitions

The following definitions are used extensively throughout the section:

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes zero (0x00).

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR2A Register. The assignment is depen-

dent on the mode of operation.

15.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal synchronous or an external asynchronous

clock source. The clock source is selected by the clock select logic which is controlled by the

clock select (CS22:0) bits located in the Timer/Counter control register (TCCR2).The clock

source clk_T2is by default equal to the MCU clock, clk_I/O. When the AS2 bit in the ASSR Register

is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to

TOSC1 and TOSC2 or directly from TOSC1. For details on asynchronous operation, see “Asyn-

chronous Status Register – ASSR” on page 159. For details on clock sources and prescaler, see

“Timer/Counter2 Prescaler” on page 162.

15.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

15-2 shows a block diagram of the counter and its surrounding environment.

Figure 15-2. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

TOSC2

count

T/C

clk _Tn

clk_TnS

Oscillator

clear

TCNTn

Control Logic

Prescaler

direction

TOSC1

bottom

top

clk

I/O

Figure 15-3.

Signal description (internal signals):

count

direction

clear

Increment or decrement TCNT2 by 1.

Selects between increment and decrement.

Clear TCNT2 (set all bits to zero).

Timer/Counter clock.

clk_T2

top

Signalizes that TCNT2 has reached maximum value.

Signalizes that TCNT2 has reached minimum value (zero).

bottom

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Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T2). clk_T2can be generated from an external or internal clock source,

selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the

timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of

whether clk_T2is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in

the Timer/Counter Control Register (TCCR2A). There are close connections between how the

counter behaves (counts) and how waveforms are generated on the Output Compare output

OC2A. For more details about advanced counting sequences and waveform generation, see

“Modes of Operation” on page 150.

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by

the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.

15.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2A). Whenever TCNT2 equals OCR2A, the comparator signals a match. A match will set

the Output Compare Flag (OCF2A) at the next timer clock cycle. If enabled (OCIE2A = 1), the

Output Compare Flag generates an Output Compare interrupt. The OCF2A flag is automatically

cleared when the interrupt is executed. Alternatively, the OCF2A flag can be cleared by software

by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to

generate an output according to operating mode set by the WGM21:0 bits and Compare Output

mode (COM2A1:0) bits. The max and bottom signals are used by the Waveform Generator for

handling the special cases of the extreme values in some modes of operation (“Modes of Oper-

ation” on page 150).

Figure 15-4 shows a block diagram of the Output Compare unit.

Figure 15-4. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

=

(8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

FOCn

Waveform Generator

OCnx

WGMn1:0

COMnX1:0

The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double

buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare

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Register to either top or bottom of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR2A Register access may seem complex, but this is not case. When the double buffer-

ing is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is

disabled the CPU will access the OCR2A directly.

15.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC2A) bit. Forcing compare match will not set the

OCF2A flag or reload/clear the timer, but the OC2A pin will be updated as if a real compare

match had occurred (the COM2A1:0 bits settings define whether the OC2A pin is set, cleared or

toggled).

15.5.2

15.5.3

Compare Match Blocking by TCNT2 Write

All CPU write operations to the TCNT2 Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR2A to be initial-

ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output Compare Unit

Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT2 when using the Output Compare channel,

independently of whether the Timer/Counter is running or not. If the value written to TCNT2

equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is

downcounting.

The setup of the OC2A should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC2A value is to use the Force Output Com-

pare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COM2A1:0 bits are not double buffered together with the compare value.

Changing the COM2A1:0 bits will take effect immediately.

15.6 Compare Match Output Unit

The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Generator

uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare

match. Also, the COM2A1:0 bits control the OC2A pin output source. Figure 15-5 shows a sim-

plified schematic of the logic affected by the COM2A1:0 bit setting. The I/O Registers, I/O bits,

and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis-

ters (DDR and PORT) that are affected by the COM2A1:0 bits are shown. When referring to the

OC2A state, the reference is for the internal OC2A Register, not the OC2A pin.

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Figure 15-5. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

15.6.1

Compare Output Function

The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform

Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC2A pin (DDR_OC2A) must be set as output before the OC2A value is vis-

ible on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC2A state before the

output is enabled. Note that some COM2A1:0 bit settings are reserved for certain modes of

operation. See “8-bit Timer/Counter Register Description” on page 156.

15.6.2

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM2A1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM2A1:0 = 0 tells the Waveform Generator that no action on the

OC2A Register is to be performed on the next compare match. For compare output actions in

the non-PWM modes refer to Table 15-2 on page 157. For fast PWM mode, refer to Table 15-3

on page 157, and for phase correct PWM refer to Table 15-4 on page 158.

A change of the COM2A1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC2A strobe bits.

15.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output

mode (COM2A1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM2A1:0 bits control whether the PWM

output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM

modes the COM2A1:0 bits control whether the output should be set, cleared, or toggled at a

compare match (See “Compare Match Output Unit” on page 149.).

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For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 154.

15.7.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same

timer clock cycle as the TCNT2 becomes zero. The TOV2 flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV2 flag, the timer resolution can be increased by software. There

are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

15.7.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the compare match output frequency. It

also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 15-6. The counter value (TCNT2)

increases until a compare match occurs between TCNT2 and OCR2A, and then counter

(TCNT2) is cleared.

Figure 15-6. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCnx

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF2A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the

TOP value. However, changing the TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR2A is lower than the current

value of TCNT2, the counter will miss the compare match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can

occur.

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For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of f_OC2A

_{clk_I/O}/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following

equation:

=

f

clk_I/O

2 ⋅ ⋅ (1

)

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

As for the Normal mode of operation, the TOV2 flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

15.7.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency

PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-

gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In

non-inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare

match between TCNT2 and OCR2A, and set at BOTTOM. In inverting Compare Output mode,

the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation,

the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 15-7. The TCNT2 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare

matches between OCR2A and TCNT2.

Figure 15-7. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

Period

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The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.

Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM2A1:0 to three (See Table 15-3 on page 157). The actual

OC2A value will only be visible on the port pin if the data direction for the port pin is set as out-

put. The PWM waveform is generated by setting (or clearing) the OC2A Register at the compare

match between OCR2A and TCNT2, and clearing (or setting) the OC2A Register at the timer

clock cycle the counter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

clk_I/O

⋅ 256

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC2A to toggle its logical level on each compare match (COM2A1:0 = 1). The waveform

generated will have a maximum frequency of f_oc2A= f_{clk_I/O}/2 when OCR2A is set to zero. This

feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

15.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM

waveform generation option. The phase correct PWM mode is based on a dual-slope operation.

The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-

inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match

between TCNT2 and OCR2A while upcounting, and set on the compare match while down-

counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation

has lower maximum operation frequency than single slope operation. However, due to the sym-

metric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct

PWM mode the counter is incremented until the counter value matches MAX. When the counter

reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one

timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 15-8.

The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2.

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Figure 15-8. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

Period

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The

interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM2A1:0 to three (See Table 15-4 on page 158).

The actual OC2A value will only be visible on the port pin if the data direction for the port pin is

set as output. The PWM waveform is generated by clearing (or setting) the OC2A Register at the

compare match between OCR2A and TCNT2 when the counter increments, and setting (or

clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the counter

decrements. The PWM frequency for the output when using phase correct PWM can be calcu-

lated by the following equation:

clk_I/O

⋅ 510

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

15.8 Timer/Counter Timing Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk_T2)

is therefore shown as a clock enable signal. In asynchronous mode, clk_I/Oshould be replaced by

the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are

set. Figure 15-9 contains timing data for basic Timer/Counter operation. The figure shows the

count sequence close to the MAX value in all modes other than phase correct PWM mode.

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Figure 15-9. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 15-10 shows the same timing data, but with the prescaler enabled.

Figure 15-10. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 15-11 shows the setting of OCF2A in all modes except CTC mode.

Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

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Figure 15-12 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.

Figure 15-12. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

15.9 8-bit Timer/Counter Register Description

15.9.1

Timer/Counter2 Control Register A– TCCR2A

Bit

7

FOC2A

W

6

5

4

3

WGM21

R/W

0

2

CS22

R/W

0

1

0

CS20

R/W

0

WGM20 COM2A1 COM2A0

CS21

TCCR2A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – FOC2A: Force Output Compare A

The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-

ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when

operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare

match is forced on the Waveform Generation unit. The OC2A output is changed according to its

COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the

value present in the COM2A1:0 bits that determines the effect of the forced compare.

A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR2A as TOP.

The FOC2A bit is always read as zero.

• Bit 6, 3 – WGM21:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum (TOP)

counter value, and what type of waveform generation to be used. Modes of operation supported

by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and

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two types of Pulse Width Modulation (PWM) modes. See Table 15-1 and “Modes of Operation”

on page 150.

Table 15-1. Waveform Generation Mode Bit Description⁽¹⁾

WGM21

(CTC2)

WGM20

(PWM2)

Timer/Counter

Mode of Operation

Update of

OCR2A at

TOV2 Flag

Set on

Mode

TOP

0

1

2

3

0

1

0

1

0

1

Normal

0xFF

Immediate

TOP

MAX

PWM, Phase Correct

CTC

0xFF

BOTTOM

MAX

OCR2A

0xFF

Immediate

TOP

Fast PWM

MAX

Note:

1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.

However, the functionality and location of these bits are compatible with previous versions of

the timer.

• Bit 5:4 – COM2A1:0: Compare Match Output Mode A

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be

set in order to enable the output driver.

When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the

WGM21:0 bit setting. Table 15-2 shows the COM2A1:0 bit functionality when the WGM21:0 bits

are set to a normal or CTC mode (non-PWM).

Table 15-2. Compare Output Mode, non-PWM Mode

COM2A1

COM2A0

Description

0

1

0

1

0

1

Normal port operation, OC2A disconnected.

Toggle OC2A on compare match.

Clear OC2A on compare match.

Set OC2A on compare match.

Table 15-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM

mode.

Table 15-3. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM2A1

COM2A0

Description

0

1

Normal port operation, OC2A disconnected.

Reserved

Clear OC2A on compare match.

Set OC2A at TOP.

1

0

1

Set OC2A on compare match.

Clear OC2A at TOP.

Note:

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-

pare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 152

for more details.

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Table 15-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase cor-

rect PWM mode.

Table 15-4. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM2A1

COM2A0

Description

0

1

Normal port operation, OC2A disconnected.

Reserved

Clear OC2A on compare match when up-counting.

Set OC2A on compare match when downcounting.

1

0

1

Set OC2A on compare match when up-counting.

Clear OC2A on compare match when downcounting.

Note:

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-

pare match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 153 for more details.

• Bit 2:0 – CS22:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table

15-5.

Table 15-5. Clock Select Bit Description

CS22

CS21

CS20

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped).

clk_T2S/(No prescaling)

clk_T2S/8 (From prescaler)

clk_T2S/32 (From prescaler)

clk_T2S/64 (From prescaler)

clk_T2S/128 (From prescaler)

clk_{T S}/256 (From prescaler)

2

clk_{T S}/1024 (From prescaler)

2

15.9.2

Timer/Counter2 Register – TCNT2

Bit

7

6

5

4

3

2

1

0

TCNT2[7:0]

TCNT2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare

match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,

introduces a risk of missing a compare match between TCNT2 and the OCR2A Register.

15.9.3

Output Compare Register A – OCR2A

Bit

7

6

5

4

3

2

1

0

OCR2A[7:0]

R/W R/W

OCR2A

Read/Write

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Initial Value

0

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The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC2A pin.

15.10 Asynchronous operation of the Timer/Counter2

15.10.1 Asynchronous Status Register – ASSR

Bit

7

–

6

–

5

–

4

EXCLK

R/W

0

3

2

1

0

AS2

R/W

0

TCN2UB

OCR2UB

TCR2UB

ASSR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7..5 – Reserved Bits

These bits are reserved for future use.

• Bit 4 – EXCLK: Enable External Clock Input

When EXCLK is written to one, and asynchronous clock is selected, the external clock input

buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead

of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is

selected. Note that the crystal Oscillator will only run when this bit is zero.

• Bit 3 – AS2: Asynchronous Timer/Counter2

When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk_I/Oand the crystal

Oscillator connected to the Timer/Counter2 Oscillator (TOSC) does nor run. When AS2 is written

to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer/Counter2

Oscillator (TOSC) or from external clock on TOSC1 depending on EXCLK setting. When the

value of AS2 is changed, the contents of TCNT2, OCR2A, and TCCR2A might be corrupted.

• Bit 2 – TCN2UB: Timer/Counter2 Update Busy

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.

When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.

• Bit 1 – OCR2UB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.

When OCR2A has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.

• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.

When TCCR2A has been updated from the temporary storage register, this bit is cleared by

hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new

value.

If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is

set, the updated value might get corrupted and cause an unintentional interrupt to occur.

The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When reading

TCNT2, the actual timer value is read. When reading OCR2A or TCCR2A, the value in the tem-

porary storage register is read.

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15.10.2 Asynchronous Operation of Timer/Counter2

When Timer/Counter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the timer registers TCNT2, OCR2A, and TCCR2A might be corrupted. A

safe procedure for switching clock source is:

a. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2.

b. Select clock source by setting AS2 and EXCLK as appropriate.

c. Write new values to TCNT2, OCR2A, and TCCR2A.

d. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.

e. Clear the Timer/Counter2 interrupt flags.

f. Enable interrupts, if needed.

• The Oscillator is optimized for use with a 32.768 kHz watch crystal. The CPU main clock

frequency must be more than four times the Oscillator or external clock frequency.

• When writing to one of the registers TCNT2, OCR2A, or TCCR2A, the value is transferred to

a temporary register, and latched after two positive edges on TOSC1. The user should not

write a new value before the contents of the temporary register have been transferred to its

destination. Each of the three mentioned registers have their individual temporary register,

which means that e.g. writing to TCNT2 does not disturb an OCR2A write in progress. To

detect that a transfer to the destination register has taken place, the Asynchronous Status

Register – ASSR has been implemented.

• When entering Power-save or Extended Standby mode after having written to TCNT2,

OCR2A, or TCCR2A, the user must wait until the written register has been updated if

Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode

before the changes are effective. This is particularly important if the Output Compare2

interrupt is used to wake up the device, since the Output Compare function is disabled during

writing to OCR2A or TCNT2. If the write cycle is not finished, and the MCU enters sleep

mode before the OCR2UB bit returns to zero, the device will never receive a compare match

interrupt, and the MCU will not wake up.

• If Timer/Counter2 is used to wake the device up from Power-save or Extended Standby

mode, precautions must be taken if the user wants to re-enter one of these modes: The

interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-

entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the

device will fail to wake up. If the user is in doubt whether the time before re-entering Power-

save mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle

has elapsed:

a. Write a value to TCCR2A, TCNT2, or OCR2A.

b. Wait until the corresponding Update Busy flag in ASSR returns to zero.

c. Enter Power-save or ADC Noise Reduction mode.

• When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2

is always running, except in Power-down and Standby modes. After a Power-up Reset or

wake-up from Power-down or Standby mode, the user should be aware of the fact that this

Oscillator might take as long as one second to stabilize. The user is advised to wait for at

least one second before using Timer/Counter2 after power-up or wake-up from Power-down

or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after

a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no

matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

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• Description of wake up from Power-save mode when the timer is clocked asynchronously:

When the interrupt condition is met, the wake up process is started on the following cycle of

the timer clock, that is, the timer is always advanced by at least one before the processor can

read the counter value. After wake-up, the MCU is halted for four cycles, it executes the

interrupt routine, and resumes execution from the instruction following SLEEP.

• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect

result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be

done through a register synchronized to the internal I/O clock domain. Synchronization takes

place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O

clock (clk_I/O) again becomes active, TCNT2 will read as the previous value (before entering

sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from

Power-save mode is essentially unpredictable, as it depends on the wake-up time. The

recommended procedure for reading TCNT2 is thus as follows:

a. Write any value to either of the registers OCR2A or TCCR2A.

b. Wait for the corresponding Update Busy Flag to be cleared.

c. Read TCNT2.

• During asynchronous operation, the synchronization of the interrupt flags for the

asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore

advanced by at least one before the processor can read the timer value causing the setting of

the interrupt flag. The Output Compare pin is changed on the timer clock and is not

synchronized to the processor clock.

15.10.3 Timer/Counter2 Interrupt Mask Register – TIMSK2

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

OCIE2A

R/W

0

TOIE2

R/W

0

TIMSK2

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7..2 – Reserved Bits

These bits are reserved for future use.

• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable

When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the

Timer/Counter2 Interrupt Flag Register – TIFR2.

• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt

Flag Register – TIFR2.

15.10.4 Timer/Counter2 Interrupt Flag Register – TIFR2

Bit

7

6

5

4

–

3

–

2

–

1

OCF2A

R/W

0

TOV2

R/W

0

–

TIFR2

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

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• Bit 7..2 – Reserved Bits

These bits are reserved for future use.

• Bit 1 – OCF2A: Output Compare Flag 2 A

The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare match Interrupt

Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.

• Bit 0 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Inter-

rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In

PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.

15.11 Timer/Counter2 Prescaler

Figure 15-13. Prescaler for Timer/Counter2

AS2

EXCLK

clk_I/O

Enable

TOSC2

TOSC1

0

1

clk_T2S

32 kHz

Oscillator

10-BIT T/C PRESCALER

0

1

Clear

EXCLK

AS2

0

PSR2

CS20

CS21

CS22

TIMER/COUNTER2 CLOCK SOURCE

clk_T2

The clock source for Timer/Counter2 is named clk_T2S. clk_T2Sis by default connected to the main

system I/O clock clk_IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously

clocked from the TOSC oscillator or TOSC1 pin. This enables use of Timer/Counter2 as a Real

Time Counter (RTC).

A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an indepen-

dent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz

crystal. Setting AS2 and resetting EXCLK enables the TOSC oscillator.

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Figure 15-14. Timer/Counter2 Crystal Oscillator Connections

12 - 22 pF

TOSC2

32.768 KHz

12 - 22 pF

TOSC1

GND

A external clock can also be used using TOSC1 as input. Setting AS2 and EXCLK enables this

configuration.

Figure 15-15. Timer/Counter2 External Clock Connections

TOSC2

TOSC1

NC

External

Clock

Signal

For Timer/Counter2, the possible prescaled selections are: clk_T2S/8, clk_T2S/32, clk_T2S/64,

clk_T2S/128, clk_T2S/256, and clk_T2S/1024. Additionally, clk_T2Sas well as 0 (stop) may be selected.

Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a pre-

dictable prescaler.

15.11.1 General Timer/Counter Control Register – GTCCR

Bit

7

6

5

4

–

3

–

2

–

1

PSR2

R/W

0

PSR310

R/W

0

TSM

–

GTCCR

Read/Write

Initial Value

R/W

0

R

0

R

0

R

0

R

0

R

0

• Bit 1 – PSR2: Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared

immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous

mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by

hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Syn-

chronization Mode” on page 98 for a description of the Timer/Counter Synchronization mode.

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16. Output Compare Modulator - OCM

16.1 Overview

Many register and bit references in this section are written in general form.

• A lower case “n” replaces the Timer/Counter number, in this case 0 and 1. However, when

using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for

accessing Timer/Counter0 counter value and so on.

• A lower case “x” replaces the Output Compare unit channel, in this case A or C. However,

when using the register or bit defines in a program, the precise form must be used, i.e.,

OCR0A for accessing Timer/Counter0 output compare channel A value and so on.

The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier

frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit

Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details

about these Timer/Counters see “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)”

on page 113 and “8-bit Timer/Counter0 with PWM” on page 99.

Figure 16-1. Output Compare Modulator, Block Diagram

OC1C

OC0A

Timer/Counter 1

Timer/Counter 0

OC0A / OC1C / PB7

When the modulator is enabled, the two output compare channels are modulated together as

shown in the block diagram (Figure 16-1).

16.2 Description

The Output Compare unit 1C and Output Compare unit 0A shares the PB7 port pin for output.

The outputs of the Output Compare units (OC1C and OC0A) overrides the normal PORTB7

Register when one of them is enabled (i.e., when COMnx1:0 is not equal to zero). When both

OC1C and OC0A are enabled at the same time, the modulator is automatically enabled.

When the modulator is enabled the type of modulation (logical AND or OR) can be selected by

the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the

COMnx1:0 bit setting.

The functional equivalent schematic of the modulator is shown on Figure 16-2. The schematic

includes part of the Timer/Counter units and the port B pin 7 output driver circuit.

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Figure 16-2. Output Compare Modulator, Schematic

COM0A1

COM0A0

Vcc

COM1C1

COM1C0

Modulator

0

1

(From T/C1

Waveform Generator)

D

Q

1

0

OC1C

OC0A / OC1C / PB7

(From T/C0

Waveform Generator)

D

Q

OC0A

D

Q

D

Q

PORTB7

DDRB7

DATABUS

16.2.1

Timing Example

Figure 16-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to oper-

ate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle

Compare Output mode (COMnx1:0 = 1).

Figure 16-3. Output Compare Modulator, Timing Diagram

clk_I/O

OC1C

(FPWM Mode)

OC0A

(CTC Mode)

PB7

(PORTB7 = 0)

PB7

(PORTB7 = 1)

1

2

3

(Period)

In this example, Timer/Counter0 provides the carrier, while the modulating signal is generated

by the Output Compare unit C of the Timer/Counter1.

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16.2.2

Resolution of the PWM Signal

The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is

equal to the number of system clock cycles of one period of the carrier (OC0A). In this example

the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure

16-3 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2

high time is one cycle longer than the period 3 high time, but the result on the PB7 output is

equal in both periods.

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17. Serial Peripheral Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

AT90CAN32/64 and peripheral devices or between several AVR devices. The AT90CAN32/64

SPI includes the following features:

17.1 Features

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

Figure 17-1. SPI Block Diagram⁽¹⁾

clk_IO

DIVIDER

/2/4/8/16/32/64/128

Note:

1. Refer to Figure 2-2 on page 5, and Table 10-6 on page 76 for SPI pin placement.

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The interconnection between Master and Slave CPUs with SPI is shown in Figure 17-2. The sys-

tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the

communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and

Slave prepare the data to be sent in their respective shift Registers, and the Master generates

the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-

ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In

– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling

high the Slave Select, SS, line.

When configured as a Master, the SPI interface has no automatic control of the SS line. This

must be handled by user software before communication can start. When this is done, writing a

byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight

bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of

transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an

interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or

signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be

kept in the Buffer Register for later use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long

as the SS pin is driven high. In this state, software may update the contents of the SPI Data

Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin

until the SS pin is driven low. As one byte has been completely shifted, the end of transmission

flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is

requested. The Slave may continue to place new data to be sent into SPDR before reading the

incoming data. The last incoming byte will be kept in the Buffer Register for later use.

Figure 17-2. SPI Master-slave Interconnection

SHIFT

ENABLE

The system is single buffered in the transmit direction and double buffered in the receive direc-

tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before

the entire shift cycle is completed. When receiving data, however, a received character must be

read from the SPI Data Register before the next character has been completely shifted in. Oth-

erwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure

correct sampling of the clock signal, the frequency of the SPI clock should never exceed f_clkio/4.

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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden

according to Table 17-1. For more details on automatic port overrides, refer to “Alternate Port

Functions” on page 71.

Table 17-1. SPI Pin Overrides⁽¹⁾

MOSI

MISO

SCK

SS

Direction, Master SPI

User Defined

Input

Direction, Slave SPI

Input

User Defined

Input

User Defined

Input

Note:

1. See “Alternate Functions of Port B” on page 76 for a detailed description of how to define the

direction of the user defined SPI pins.

The following code examples show how to initialize the SPI as a Master and how to perform a

simple transmission.

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DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the

SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits

for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI

with DDRB.

Assembly Code Example⁽¹⁾

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi

out

r17,(1<<DD_MOSI)|(1<<DD_SCK)

DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi

out

ret

r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

SPCR,r17

SPI_MasterTransmit:

; Start transmission of data (r16)

out

SPDR,r16

Wait_Transmit:

; Wait for transmission complete

in

r17,SPSR

sbrs

rjmp

ret

r17,SPIF

Wait_Transmit

C Code Example⁽¹⁾

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)));

}

Note:

1. The example code assumes that the part specific header file is included.

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The following code examples show how to initialize the SPI as a Slave and how to perform a

simple reception.

Assembly Code Example⁽¹⁾

SPI_SlaveInit:

; Set MISO output, all others input

ldi

out

r17,(1<<DD_MISO)

DDR_SPI,r17

; Enable SPI

ldi

out

ret

r17,(1<<SPE)

SPCR,r17

SPI_SlaveReceive:

; Wait for reception complete

sbis

rjmp

SPSR,SPIF

SPI_SlaveReceive

; Read received data and return

in

r16,SPDR

ret

C Code Example⁽¹⁾

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)));

/* Return data register */

return SPDR;

}

Note:

1. The example code assumes that the part specific header file is included.

17.2 SS Pin Functionality

17.2.1

Slave Mode

When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is

held low, the SPI is activated, and MISO becomes an output if configured so by the user. All

other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which

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means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin

is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous

with the master clock generator. When the SS pin is driven high, the SPI slave will immediately

reset the send and receive logic, and drop any partially received data in the Shift Register.

17.2.2

Master Mode

When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the

direction of the SS pin.

If SS is configured as an output, the pin is a general output pin which does not affect the SPI

system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin

is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin

defined as an input, the SPI system interprets this as another master selecting the SPI as a

slave and starting to send data to it. To avoid bus contention, the SPI system takes the following

actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of

the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG

is set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-

bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the

MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master

mode.

17.2.3

SPI Control Register – SPCR

Bit

7

6

5

DORD

R/W

0

4

MSTR

R/W

0

3

CPOL

R/W

0

2

CPHA

R/W

0

1

SPR1

R/W

0

SPR0

R/W

0

SPIE

R/W

0

SPE

R/W

0

SPCR

Read/Write

Initial Value

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the

Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI

operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,

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and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL functionality is sum-

marized below:

Table 17-2. CPOL Functionality

CPOL

Leading Edge

Rising

Trailing Edge

Falling

0

1

Falling

Rising

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL

functionality is summarized below:

Table 17-3. CPHA Functionality

CPHA

Leading Edge

Sample

Trailing Edge

Setup

0

1

Setup

Sample

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have

no effect on the Slave. The relationship between SCK and the clk_IOfrequency f_clkiois shown in

the following table:

Table 17-4. Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f_clkio/4

f_clkio/16

f_clkio/64

f_clkio/128

f_clkio/2

f_clkio/8

f_clkio/32

f_clkio/64

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17.2.4

SPI Status Register – SPSR

Bit

7

SPIF

R

6

5

–

4

–

3

–

2

–

1

–

0

SPI2X

R/W

0

WCOL

SPSR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in

SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is

in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the

SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The

WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,

and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the AT90CAN32/64 and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI

is in Master mode (see Table 17-4). This means that the minimum SCK period will be two CPU

clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f_clkio/4

or lower.

The SPI interface on the AT90CAN32/64 is also used for program memory and EEPROM down-

loading or uploading. See page 347 for serial programming and verification.

17.2.5

SPI Data Register – SPDR

Bit

7

SPD7

R/W

X

6

SPD6

R/W

X

5

SPD5

R/W

X

4

SPD4

R/W

X

3

SPD3

R/W

X

2

SPD2

R/W

X

1

SPD1

R/W

X

0

SPD0

R/W

X

SPDR

Read/Write

Initial Value

Undefined

• Bits 7:0 - SPD7:0: SPI Data

The SPI Data Register is a read/write register used for data transfer between the Register File

and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-

ter causes the Shift Register Receive buffer to be read.

17.3 Data Modes

There are four combinations of SCK phase and polarity with respect to serial data, which are

determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure

17-3 and Figure 17-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-

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nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing

Table 17-2 and Table 17-3, as done below:

Table 17-5. CPOL Functionality

Leading Edge

Sample (Rising)

Setup (Rising)

Sample (Falling)

Setup (Falling)

Trailing Edge

Setup (Falling)

Sample (Falling)

Setup (Rising)

Sample (Rising)

SPI Mode

CPOL=0, CPHA=0

CPOL=0, CPHA=1

CPOL=1, CPHA=0

CPOL=1, CPHA=1

0

1

2

3

Figure 17-3. SPI Transfer Format with CPHA = 0

SCK (CPOL = 0)

mode 0

SCK (CPOL = 1)

mode 2

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0) MSB

LSB first (DORD = 1) LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

Figure 17-4. SPI Transfer Format with CPHA = 1

SCK (CPOL = 0)

mode 1

SCK (CPOL = 1)

mode 3

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0)

LSB first (DORD = 1)

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

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18. USART (USART0 and USART1)

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a

highly flexible serial communication device. The main features are:

18.1 Features

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

18.2 Overview

Many registers and bit references in this section are written in general form.

• A lower case “n” replaces the USART number, in this case 0 or 1. However, when using the

register or bit defines in a program, the precise form must be used, i.e., UDR0 for accessing

USART0 I/O data value and so on.

18.3 Dual USART

The AT90CAN32/64 has two USART’s, USART0 and USART1. The functionality for both

USART’s is described below. USART0 and USART1 have different I/O registers as shown in

“Register Summary” on page 404.

A simplified block diagram of the USARTn Transmitter is shown in Figure 18-1. CPU accessible

I/O Registers and I/O pins are shown in bold.

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Figure 18-1. USARTn Block Diagram ⁽¹⁾

Clock Generator

UBRRn[H:L]

CLKio

BAUD RATE GENERATOR

SYNC LOGIC

CONTROL

XCKn

Transmitter

TX

CONTROL

UDRn (Transmit)

PARITY

GENERATOR

TxDn

TRANSMIT SHIFT REGISTER

CONTROL

Receiver

CLOCK

RX

RECOVERY

CONTROL

DATA

RECOVERY

CONTROL

RECEIVE SHIFT REGISTER

RxDn

PARITY

CHECKER

UDRn (Receive)

UCSRAn

UCSRBn

UCSRCn

Note:

1. Refer to Figure 2-2 on page 5, Table 10-15 on page 83, and Table 10-10 on page 79 for

USARTn pin placement.

The dashed boxes in the block diagram separate the three main parts of the USARTn (listed

from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all

units. The Clock Generation logic consists of synchronization logic for external clock input used

by synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is

only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a

serial Shift Register, Parity Generator and Control logic for handling different serial frame for-

mats. The write buffer allows a continuous transfer of data without any delay between frames.

The Receiver is the most complex part of the USARTn module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception. In addition to the recovery

units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and

can detect Frame Error, Data OverRun and Parity Errors.

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18.4 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The

USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn-

chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USARTn

Control and Status Register C (UCSRnC) selects between asynchronous and synchronous

operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the

UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register

for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or

external (Slave mode). The XCKn pin is only active when using synchronous mode.

Figure 18-2 shows a block diagram of the clock generation logic.

Figure 18-2. USARTn Clock Generation Logic, Block Diagram

UBRRn

U2Xn

f

clk_io

UBRRn+1

Prescaling

Down-Counter

/2

/4

/2

0

1

0

1

clk_io

txn clk

UMSELn

rxn clk

DDR_XCKn

Sync

Register

Edge

Detector

0

1

xn cki

XCKn

xn cko

DDR_XCKn

UCPOLn

1

0

Signal description:

txn clk

Transmitter clock (Internal Signal).

Receiver base clock (Internal Signal).

rxn clk

xn cki

Input from XCK pin (internal Signal). Used for synchronous slave

operation.

xn cko

fclk_io

Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

System I/O Clock frequency.

18.4.1

Internal Clock Generation – Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of

operation. The description in this section refers to Figure 18-2.

The USARTn Baud Rate Register (UBRRn) and the down-counter connected to it function as a

programmable prescaler or baud rate generator. The down-counter, running at system clock

(fclk_io), is loaded with the UBRRn value each time the counter has counted down to zero or

when the UBRRnL Register is written. A clock is generated each time the counter reaches zero.

This clock is the baud rate generator clock output (= fclk_io/(UBRRn+1)). The Transmitter divides

the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator

output is used directly by the Receiver’s clock and data recovery units. However, the recovery

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units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the

UMSELn, U2Xn and DDR_XCKn bits.

Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculat-

ing the UBRRn value for each mode of operation using an internally generated clock source.

Table 18-1. Equations for Calculating Baud Rate Register Setting

Equation for Calculating Baud

Rate ⁽¹⁾

Equation for Calculating

UBRRn Value

Operating Mode

Asynchronous Normal mode

(U2Xn = 0)

1

16(

1)

16

Asynchronous Double Speed

mode (U2Xn = 1)

1

8(

2(

1)

8

1

Synchronous Master mode

1)

2

Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD

fclk_io

Baud rate (in bits per second, bps).

System I/O Clock frequency.

UBRRn

Contents of the UBRRnH and UBRRnL Registers, (0-4095).

Some examples of UBRRn values for some system clock frequencies are found in Table 18-9

(see page 199).

18.4.2

Double Speed Operation (U2X)

The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has

effect for the asynchronous operation. Set this bit to zero when using synchronous operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling

the transfer rate for asynchronous communication. Note however that the Receiver will in this

case only use half the number of samples (reduced from 16 to 8) for data sampling and clock

recovery, and therefore a more accurate baud rate setting and system clock are required when

this mode is used. For the Transmitter, there are no downsides.

18.4.3

External Clock

External clocking is used by the synchronous slave modes of operation. The description in this

section refers to Figure 18-2 for details.

External clock input from the XCKn pin is sampled by a synchronization register to minimize the

chance of meta-stability. The output from the synchronization register must then pass through

an edge detector before it can be used by the Transmitter and Receiver. This process intro-

duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency

is limited by the following equation:

<

4

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Note that fclk_iodepends on the stability of the system clock source. It is therefore recommended

to add some margin to avoid possible loss of data due to frequency variations.

18.4.4

Synchronous Clock Operation

When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input

(Slave) or clock output (Master). The dependency between the clock edges and data sampling

or data change is the same. The basic principle is that data input (on RxDn) is sampled at the

opposite XCKn clock edge of the edge the data output (TxDn) is changed.

Figure 18-3. Synchronous Mode XCKn Timing.

UCPOLn = 1

XCKn

RxDn / TxDn

Sample

UCPOLn = 0

XCKn

RxDn / TxDn

The UCPOLn bit UCRSnC selects which XCKn clock edge is used for data sampling and which

is used for data change. As Figure 18-3 shows, when UCPOLn is zero the data will be changed

at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be

changed at falling XCKn edge and sampled at rising XCKn edge.

18.5 Serial Frame

A serial frame is defined to be one character of data bits with synchronization bits (start and stop

bits), and optionally a parity bit for error checking.

18.5.1

Frame Formats

The USARTn accepts all 30 combinations of the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit. Then the next data bits,

up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit

is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can

be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Figure 18-4 illustrates the possible combinations of the frame formats. Bits inside brackets are

optional.

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Figure 18-4. Frame Formats

FRAME

[5]

(IDLE)

St

0

1

2

3

4

[6]

[7]

[8]

[P] Sp1 [Sp2] (St / IDLE)

St

Start bit, always low.

Data bits (0 to 8).

(n)

P

Parity bit. Can be odd or even.

Stop bit, always high.

Sp

IDLE

No transfers on the communication line (RxDn or TxDn).

An IDLE line must be high.

The frame format used by the USARTn is set by the UCSZn2:0, UPMn1:0 and USBSn bits in

UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing

the setting of any of these bits will corrupt all ongoing communication for both the Receiver and

Transmitter.

The USARTn Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The

USARTn Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection

between one or two stop bits is done by the USARTn Stop Bit Select (USBSn) bit. The Receiver

ignores the second stop bit. An FEn (Frame Error) will therefore only be detected in the cases

where the first stop bit is zero.

18.5.2

Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the

result of the exclusive or is inverted. The relation between the parity bit and data bits is as

follows:

⊕ … ⊕

⊕

⊕ 0

⊕ 1

1

3

2

1

0

P_even

P^odd

d_n

Parity bit using even parity

Parity bit using odd parity

Data bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial frame.

18.6 USART Initialization

The USARTn has to be initialized before any communication can take place. The initialization

process normally consists of setting the baud rate, setting frame format and enabling the Trans-

mitter or the Receiver depending on the usage. For interrupt driven USARTn operation, the

Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the

initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that there are no

ongoing transmissions during the period the registers are changed. The TXCn flag can be used

to check that the Transmitter has completed all transfers, and the RXCn flag can be used to

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check that there are no unread data in the receive buffer. Note that the TXCn flag must be

cleared before each transmission (before UDRn is written) if it is used for this purpose.

The following simple USART0 initialization code examples show one assembly and one C func-

tion that are equal in functionality. The examples assume asynchronous operation using polling

(no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.

For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16

Registers.

Assembly Code Example ⁽¹⁾

USART0_Init:

; Set baud rate

sts

UBRR0H, r17

UBRR0L, r16

; Set frame format: 8data, no parity & 2 stop bits

ldi

sts

r16, (0<<UMSEL0)|(0<<UPM0)|(1<<USBS0)|(3<<UCSZ0)

UCSR0C, r16

; Enable receiver and transmitter

ldi

sts

ret

r16, (1<<RXEN0)|(1<<TXEN0)

UCSR0B, r16

C Code Example ⁽¹⁾

void USART0_Init (unsigned int baud)

{

/* Set baud rate */

UBRR0H = (unsigned char) (baud>>8);

UBRR0L = (unsigned char) baud;

/* Set frame format: 8data, no parity & 2 stop bits */

UCSR0C = (0<<UMSEL0) | (0<<UPM0) | (1<<USBS0) | (3<<UCSZ0);

/* Enable receiver and transmitter */

UCSR0B = (1<<RXEN0) | (1<<TXEN0);

}

Note:

1. The example code assumes that the part specific header file is included.

More advanced initialization routines can be made that include frame format as parameters, dis-

able interrupts and so on. However, many applications use a fixed setting of the baud and

control registers, and for these types of applications the initialization code can be placed directly

in the main routine, or be combined with initialization code for other I/O modules.

18.7 Data Transmission – USART Transmitter

The USARTn Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB

Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid-

den by the USARTn and given the function as the Transmitter’s serial output. The baud rate,

mode of operation and frame format must be set up once before doing any transmissions. If syn-

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chronous operation is used, the clock on the XCKn pin will be overridden and used as

transmission clock.

18.7.1

Sending Frames with 5 to 8 Data Bit

A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The

CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the

transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new

frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or

immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is

loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,

U2Xn bit or by XCKn depending on mode of operation.

The following code examples show a simple USART0 transmit function based on polling of the

Data Register Empty (UDRE0) flag. When using frames with less than eight bits, the most signif-

icant bits written to the UDR0 are ignored. The USART0 has to be initialized before the function

can be used. For the assembly code, the data to be sent is assumed to be stored in Register

R16

Assembly Code Example ⁽¹⁾

USART0_Transmit:

; Wait for empty transmit buffer

lds

r17, UCSR0A

r17, UDRE0

sbrs

rjmp

USART0_Transmit

; Put data (r16) into buffer, sends the data

sts

ret

UDR0, r16

C Code Example ⁽¹⁾

void USART0_Transmit (unsigned char data)

{

/* Wait for empty transmit buffer */

while ( ! ( UCSRA0 & (1<<UDRE0)));

/* Put data into buffer, sends the data */

UDR0 = data;

}

Note:

1. The example code assumes that the part specific header file is included.

The function simply waits for the transmit buffer to be empty by checking the UDRE0 flag, before

loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the

interrupt routine writes the data into the buffer.

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18.7.2

Sending Frames with 9 Data Bit

If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8n bit in UCS-

RnB before the low byte of the character is written to UDRn. The following code examples show

a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is

assumed to be stored in registers R17:R16.

Assembly Code Example ⁽¹⁾⁽²⁾

USART0_Transmit:

; Wait for empty transmit buffer

lds

r18, UCSR0A

r18, UDRE0

sbrs

rjmp

USART0_Transmit

; Copy 9th bit from r17-bit0 to TXB80 via T-bit of SREG

lds

bst

bld

sts

r18, UCSR0B

r17, 0

r18, TXB80

UCSR0B, r18

; Put LSB data (r16) into buffer, sends the data

sts

ret

UDR0, r16

C Code Example ⁽¹⁾⁽²⁾

void USART0_Transmit (unsigned int data)

{

/* Wait for empty transmit buffer */

while ( !( UCSR0A & (1<<UDRE0)));

/* Copy 9th bit to TXB8 */

UCSR0B &= ~(1<<TXB80);

if ( data & 0x0100 )

UCSR0B |= (1<<TXB80);

/* Put data into buffer, sends the data */

UDR0 = data;

}

Notes: 1. These transmit functions are written to be general functions. They can be optimized if the con-

tents of the UCSR0B is static. For example, only the TXB80 bit of the UCSRB0 Register is

used after initialization.

2. The example code assumes that the part specific header file is included.

The ninth bit can be used for indicating an address frame when using multi processor communi-

cation mode or for other protocol handling as for example synchronization.

18.7.3

Transmitter Flags and Interrupts

The USARTn Transmitter has two flags that indicate its state: USART Data Register Empty

(UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts.

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The Data Register Empty (UDREn) flag indicates whether the transmit buffer is ready to receive

new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer

contains data to be transmitted that has not yet been moved into the Shift Register. For compat-

ibility with future devices, always write this bit to zero when writing the UCSRnA Register.

When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRBn is written to one, the

USARTn Data Register Empty Interrupt will be executed as long as UDREn is set (provided that

global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data

transmission is used, the Data Register Empty interrupt routine must either write new data to

UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new

interrupt will occur once the interrupt routine terminates.

The Transmit Complete (TXCn) flag bit is set one when the entire frame in the Transmit Shift

Register has been shifted out and there are no new data currently present in the transmit buffer.

The TXCn flag bit is automatically cleared when a transmit complete interrupt is executed, or it

can be cleared by writing a one to its bit location. The TXCn flag is useful in half-duplex commu-

nication interfaces (like the RS-485 standard), where a transmitting application must enter

receive mode and free the communication bus immediately after completing the transmission.

When the Transmit Complete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USARTn

Transmit Complete Interrupt will be executed when the TXCn flag becomes set (provided that

global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-

dling routine does not have to clear the TXCn flag, this is done automatically when the interrupt

is executed.

18.7.4

18.7.5

Parity Generator

The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled

(UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the

first stop bit of the frame that is sent.

Disabling the Transmitter

The disabling of the Transmitter (setting the TXENn to zero) will not become effective until ongo-

ing and pending transmissions are completed, i.e., when the Transmit Shift Register and

Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter

will no longer override the TxDn pin.

18.8 Data Reception – USART Receiver

The USARTn Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB

Register to one. When the Receiver is enabled, the normal pin operation of the RxDn pin is over-

ridden by the USARTn and given the function as the Receiver’s serial input. The baud rate,

mode of operation and frame format must be set up once before any serial reception can be

done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer clock.

18.8.1

Receiving Frames with 5 to 8 Data Bits

The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start

bit will be sampled at the baud rate or XCKn clock, and shifted into the Receive Shift Register

until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver.

When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift

Register, the contents of the Shift Register will be moved into the receive buffer. The receive

buffer can then be read by reading the UDRn I/O location.

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The following code example shows a simple USART0 receive function based on polling of the

Receive Complete (RXC0) flag. When using frames with less than eight bits the most significant

bits of the data read from the UDR0 will be masked to zero. The USART0 has to be initialized

before the function can be used.

Assembly Code Example ⁽¹⁾

USART0_Receive:

; Wait for data to be received

lds

r18, UCSR0A

r18, RXC0

sbrs

rjmp

USART0_Receive

; Get and return received data from buffer

lds

ret

r16, UDR0

C Code Example ⁽¹⁾

unsigned char USART0_Receive (void)

{

/* Wait for data to be received */

while ( ! (UCSR0A & (1<<RXC0)));

/* Get and return received data from buffer */

return UDR0;

}

Note:

1. The example code assumes that the part specific header file is included.

The function simply waits for data to be present in the receive buffer by checking the RXC0 flag,

before reading the buffer and returning the value.

18.8.2

Receiving Frames with 9 Data Bits

If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in UCS-

RnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn

Status Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O

location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn,

DORn and UPEn bits, which all are stored in the FIFO, will change.

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The following code example shows a simple USART0 receive function that handles both nine bit

characters and the status bits.

Assembly Code Example ⁽¹⁾

USART0_Receive:

; Wait for data to be received

lds

r18, UCSR0A

r18, RXC0

sbrs

rjmp

USART0_Receive

; Get status and 9th bit, then data from buffer

lds

r17, UCSR0B

r16, UDR0

; If error, return -1

andi

breq

ldi

r18, (1<<FE0) | (1<<DOR0) | (1<<UPE0)

USART0_ReceiveNoError

r17, HIGH(-1)

ldi

r16, LOW(-1)

USART0_ReceiveNoError:

; Filter the 9th bit, then return

lsr

r17

andi

ret

r17, 0x01

C Code Example ⁽¹⁾

unsigned int USART0_Receive(void)

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( ! (UCSR0A & (1<<RXC0)));

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSR0A;

resh = UCSR0B;

resl = UDR0;

/* If error, return -1 */

if ( status & (1<<FE0)|(1<<DOR0)|(1<<UPE0) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

Note:

1. The example code assumes that the part specific header file is included.

The receive function example reads all the I/O Registers into the Register File before any com-

putation is done. This gives an optimal receive buffer utilization since the buffer location read will

be free to accept new data as early as possible.

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18.8.3

Receive Complete Flag and Interrupt

The USARTn Receiver has one flag that indicates the Receiver state.

The Receive Complete (RXCn) flag indicates if there are unread data present in the receive

buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0),

the receive buffer will be flushed and consequently the RXCn bit will become zero.

When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USARTn

Receive Complete interrupt will be executed as long as the RXCn flag is set (provided that glo-

bal interrupts are enabled). When interrupt-driven data reception is used, the receive complete

routine must read the received data from UDRn in order to clear the RXCn flag, otherwise a new

interrupt will occur once the interrupt routine terminates.

18.8.4

Receiver Error Flags

The USARTn Receiver has three error flags: Frame Error (FEn), Data OverRun (DORn) and

Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the error flags is

that they are located in the receive buffer together with the frame for which they indicate the

error status. Due to the buffering of the error flags, the UCSRnA must be read before the receive

buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another

equality for the error flags is that they can not be altered by software doing a write to the flag

location. However, all flags must be set to zero when the UCSRnA is written for upward compat-

ibility of future USART implementations. None of the error flags can generate interrupts.

The Frame Error (FEn) flag indicates the state of the first stop bit of the next readable frame

stored in the receive buffer. The FEn flag is zero when the stop bit was correctly read (as one),

and the FEn flag will be one when the stop bit was incorrect (zero). This flag can be used for

detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn flag

is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except

for the first, stop bits. For compatibility with future devices, always set this bit to zero when writ-

ing to UCSRnA.

The Data OverRun (DORn) flag indicates data loss due to a receiver buffer full condition. A Data

OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in

the Receive Shift Register, and a new start bit is detected. If the DORn flag is set there was one

or more serial frame lost between the frame last read from UDRn, and the next frame read from

UDRn. For compatibility with future devices, always write this bit to zero when writing to UCS-

RnA. The DORn flag is cleared when the frame received was successfully moved from the Shift

Register to the receive buffer.

The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity

Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For

compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more

details see “Parity Bit Calculation” on page 181 and “Parity Checker” on page 188.

18.8.5

Parity Checker

The Parity Checker is active when the high USARTn Parity mode (UPMn1) bit is set. Type of

Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the

Parity Checker calculates the parity of the data bits in incoming frames and compares the result

with the parity bit from the serial frame. The result of the check is stored in the receive buffer

together with the received data and stop bits. The Parity Error (UPEn) flag can then be read by

software to check if the frame had a Parity Error.

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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity

Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is

valid until the receive buffer (UDRn) is read.

18.8.6

18.8.7

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing

receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will

no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be

flushed when the Receiver is disabled. Remaining data in the buffer will be lost

Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be

emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal

operation, due to for instance an error condition, read the UDRn I/O location until the RXCn flag

is cleared.

The following code example shows how to flush the receive buffer.

Assembly Code Example ⁽¹⁾

USART0_Flush:

lds

r16, UCSR0A

r16, RXC0

sbrs

ret

lds

r16, UDR0

rjmp

USART0_Flush

C Code Example ⁽¹⁾

void USART0_Flush (void)

{

unsigned char dummy;

while (UCSR0A & (1<<RXC0) ) dummy = UDR0;

}

Note:

1. The example code assumes that the part specific header file is included.

18.9 Asynchronous Data Reception

The USARTn includes a clock recovery and a data recovery unit for handling asynchronous data

reception. The clock recovery logic is used for synchronizing the internally generated baud rate

clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam-

ples and low pass filters each incoming bit, thereby improving the noise immunity of the

Receiver. The asynchronous reception operational range depends on the accuracy of the inter-

nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

18.9.1

Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 18-5

illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times

the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-

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izontal arrows illustrate the synchronization variation due to the sampling process. Note the

larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples

denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).

Figure 18-5. Start Bit Sampling

RxDn

IDLE

START

BIT 0

Sample

(U2Xn = 0)

0

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

2

3

Sample

(U2Xn = 1)

0

2

When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the

start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in

the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-

ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the

figure), to decide if a valid start bit is received. If two or more of these three samples have logical

high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts

looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-

ery logic is synchronized and the data recovery can begin. The synchronization process is

repeated for each start bit.

18.9.2

Asynchronous Data Recovery

When the receiver clock is synchronized to the start bit, the data recovery can begin. The data

recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight

states for each bit in Double Speed mode. Figure 18-6 shows the sampling of the data bits and

the parity bit. Each of the samples is given a number that is equal to the state of the recovery

unit.

Figure 18-6. Sampling of Data and Parity Bit

RxDn

BIT x

Sample

(U2Xn = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

Sample

(U2Xn = 1)

The decision of the logic level of the received bit is taken by doing a majority voting of the logic

value to the three samples in the center of the received bit. The center samples are emphasized

on the figure by having the sample number inside boxes. The majority voting process is done as

follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.

If two or all three samples have low levels, the received bit is registered to be a logic 0. This

majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The

recovery process is then repeated until a complete frame is received. Including the first stop bit.

Note that the Receiver only uses the first stop bit of a frame.

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Figure 18-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit

of the next frame.

Figure 18-7. Stop Bit Sampling and Next Start Bit Sampling

(A)

(B)

(C)

RxDn

STOP 1

Sample

(U2Xn = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

0/1 0/1 0/1

Sample

(U2Xn = 1)

6

0/1

The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop

bit is registered to have a logic 0 value, the Frame Error (FEn) flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after the last of

the bits used for majority voting. For Normal Speed mode, the first low level sample can be at

point marked (A) in Figure 18-7. For Double Speed mode the first low level must be delayed to

(B). (C) marks a stop bit of full length. The early start bit detection influences the operational

range of the Receiver.

18.9.3

Asynchronous Operational Range

The operational range of the Receiver is dependent on the mismatch between the received bit

rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too

slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see

Table 18-2) base frequency, the Receiver will not be able to synchronize the frames to the start

bit.

The following equations can be used to calculate the ratio of the incoming data rate and internal

receiver baud rate.

(

2)

(

1

1)

⋅

(

1)

D

Sum of character size and parity size (D = 5 to 10 bit)

S

Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode.

S_F

First sample number used for majority voting. S_F= 8 for normal speed and

S_F= 4 for Double Speed mode.

S_M

Middle sample number used for majority voting. S_M= 9 for normal speed and

S_M= 5 for Double Speed mode.

R_slowis the ratio of the slowest incoming data rate that can be accepted in relation to

the receiver baud rate.

R_fast

is the ratio of the fastest incoming data rate that can be accepted in relation to the

receiver baud rate.

Table 18-2 and Table 18-3 list the maximum receiver baud rate error that can be tolerated. Note

that Normal Speed mode has higher toleration of baud rate variations.

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Table 18-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode

(U2Xn = 0)

D

Recommended Max

Receiver Error (%)

R

_slow(%)

R_fast(%)

Max Total Error (%)

# (Data+Parity Bit)

5

6

93.20

94.12

94.81

95.36

95.81

96.17

106.67

105.79

105.11

104.58

104.14

103.78

+6.67/-6.8

+5.79/-5.88

+5.11/-5.19

+4.58/-4.54

+4.14/-4.19

+3.78/-3.83

3.0

2.5

2.0

1.5

7

8

9

10

Table 18-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode

(U2Xn = 1)

D

Recommended Max

Receiver Error (%)

R

_slow(%)

R_fast(%)

Max Total Error (%)

# (Data+Parity Bit)

5

6

94.12

94.92

95.52

96.00

96.39

96.70

105.66

104.92

104,35

103.90

103.53

103.23

+5.66/-5.88

+4.92/-5.08

+4.35/-4.48

+3.90/-4.00

+3.53/-3.61

+3.23/-3.30

2.5

2.0

1.5

1.0

7

8

9

10

The recommendations of the maximum receiver baud rate error was made under the assump-

tion that the Receiver and Transmitter equally divides the maximum total error.

There are two possible sources for the receivers baud rate error. The Receiver’s system clock

(XTAL) will always have some minor instability over the supply voltage range and the tempera-

ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a

resonator the system clock may differ more than 2% depending of the resonators tolerance. The

second source for the error is more controllable. The baud rate generator can not always do an

exact division of the system frequency to get the baud rate wanted. In this case an UBRRn value

that gives an acceptable low error can be used if possible.

18.10 Multi-processor Communication Mode

Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering

function of incoming frames received by the USARTn Receiver. Frames that do not contain

address information will be ignored and not put into the receive buffer. This effectively reduces

the number of incoming frames that has to be handled by the CPU, in a system with multiple

MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn

setting, but has to be used differently when it is a part of a system utilizing the Multi-processor

Communication mode.

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18.10.1 MPCM Protocol

If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-

cates if the frame contains data or address information. If the Receiver is set up for frames with

nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When

the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the

frame type bit is zero the frame is a data frame.

The Multi-processor Communication mode enables several slave MCUs to receive data from a

master MCU. This is done by first decoding an address frame to find out which MCU has been

addressed. If a particular slave MCU has been addressed, it will receive the following data

frames as normal, while the other slave MCUs will ignore the received frames until another

address frame is received.

18.10.2 Using MPCM

For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The

ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame

(TXBn = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit charac-

ter frame format.

The following procedure should be used to exchange data in Multi-processor Communication

mode:

1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in

UCSRnA is set).

2. The Master MCU sends an address frame, and all slaves receive and read this frame.

In the Slave MCUs, the RXCn flag in UCSRnA will be set as normal.

3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If

so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and

keeps the MPCMn setting.

4. The addressed MCU will receive all data frames until a new address frame is received.

The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.

5. When the last data frame is received by the addressed MCU, the addressed MCU sets

the MPCMn bit and waits for a new address frame from master. The process then

repeats from 2.

Using any of the 5- to 8-bit character frame formats is possible, but impractical since the

Receiver must change between using N and N+1 character frame formats. This makes full-

duplex operation difficult since the Transmitter and Receiver use the same character size set-

ting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit

(USBSn = 1) since the first stop bit is used for indicating the frame type.

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18.11 USART Register Description

18.11.1 USART0 I/O Data Register – UDR0

Bit

7

6

5

4

3

2

1

0

RXB0[7:0]

TXB0[7:0]

UDR0 (Read)

UDR0 (Write)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

18.11.2 USART1 I/O Data Register – UDR1

Bit

7

6

5

4

3

2

1

0

RXB1[7:0]

TXB1[7:0]

UDR1 (Read)

UDR1 (Write)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7:0 – RxBn7:0: Receive Data Buffer (read access)

• Bit 7:0 – TxBn7:0: Transmit Data Buffer (write access)

The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share

the same I/O address referred to as USARTn Data Register or UDRn. The Transmit Data Buffer

Register (TXBn) will be the destination for data written to the UDRn Register location. Reading

the UDRn Register location will return the contents of the Receive Data Buffer Register (RXBn).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to

zero by the Receiver.

The transmit buffer can only be written when the UDREn flag in the UCSRnA Register is set.

Data written to UDRn when the UDREn flag is not set, will be ignored by the USARTn Transmit-

ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter

will load the data into the Transmit Shift Register when the Shift Register is empty. Then the

data will be serially transmitted on the TxDn pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the

receive buffer is accessed.

18.11.3 USART0 Control and Status Register A – UCSR0A

Bit

7

6

5

4

FE0

R

3

DOR0

R

2

UPE0

R

1

U2X0

R/W

0

MPCM0

R/W

0

RXC0

TXC0

UDRE0

UCSR0A

Read/Write

Initial Value

R

0

R/W

0

R

1

0

18.11.4 USART1 Control and Status Register A – UCSR1A

Bit

7

RXC1

R

6

TXC1

R/W

0

5

4

FE1

R

3

DOR1

R

2

UPE1

R

1

U2X1

R/W

0

MPCM1

R/W

0

UDRE1

UCSR1A

Read/Write

Initial Value

R

1

0

• Bit 7 – RXCn: USARTn Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be

used to generate a Receive Complete interrupt (see description of the RXCIEn bit).

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• Bit 6 – TXCn: USARTn Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDRn). The TXCn flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXCn flag can generate a Transmit Complete interrupt (see descrip-

tion of the TXCIEn bit).

• Bit 5 – UDREn: USARTn Data Register Empty

The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is

one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a Data

Register Empty interrupt (see description of the UDRIEn bit).

UDREn is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FEn: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.,

when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the

receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.

Always set this bit to zero when writing to UCSRnA.

• Bit 3 – DORn: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive

buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a

new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this

bit to zero when writing to UCSRnA.

• Bit 2 – UPEn: USARTn Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received and the

Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer

(UDRn) is read. Always set this bit to zero when writing to UCSRnA.

• Bit 1 – U2Xn: Double the USARTn Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-

chronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-

bling the transfer rate for asynchronous communication.

• Bit 0 – MPCMn: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to

one, all the incoming frames received by the USARnT Receiver that do not contain address

information will be ignored. The Transmitter is unaffected by the MPCMn setting. For more

detailed information see “Multi-processor Communication Mode” on page 192.

18.11.5 USART0 Control and Status Register B – UCSR0B

Bit

7

6

5

4

RXEN0

R/W

0

3

TXEN0

R/W

0

2

UCSZ02

R/W

0

1

0

TXB80

R/W

0

RXCIE0

TXCIE0

UDRIE0

RXB80

UCSR0B

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R

0

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18.11.6 USART1 Control and Status Register B – UCSR1B

Bit

7

RXCIE1

R/W

0

6

TXCIE1

R/W

0

5

UDRIE1

R/W

0

4

RXEN1

R/W

0

3

TXEN1

R/W

0

2

UCSZ12

R/W

0

1

0

TXB81

R/W

0

RXB81

UCSR1B

Read/Write

Initial Value

R

0

• Bit 7 – RXCIEn: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXCn flag. A USARTn Receive Complete inter-

rupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG

is written to one and the RXCn bit in UCSRnA is set.

• Bit 6 – TXCIEn: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXCn flag. A USARTn Transmit Complete inter-

rupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG

is written to one and the TXCn bit in UCSRnA is set.

• Bit 5 – UDRIEn: USARTn Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDREn flag. A Data Register Empty interrupt will

be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written

to one and the UDREn bit in UCSRnA is set.

• Bit 4 – RXENn: Receiver Enable

Writing this bit to one enables the USARTn Receiver. The Receiver will override normal port

operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer

invalidating the FEn, DORn, and UPEn Flags.

• Bit 3 – TXENn: Transmitter Enable

Writing this bit to one enables the USARTn Transmitter. The Transmitter will override normal

port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn

to zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxDn port.

• Bit 2 – UCSZn2: Character Size

The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

• Bit 1 – RXB8n: Receive Data Bit 8

RXB8n is the ninth data bit of the received character when operating with serial frames with nine

data bits. Must be read before reading the low bits from UDRn.

• Bit 0 – TXB8n: Transmit Data Bit 8

TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames

with nine data bits. Must be written before writing the low bits to UDRn.

18.11.7 USART0 Control and Status Register C – UCSR0C

Bit

7

6

5

4

UPM00

R/W

0

3

USBS0

R/W

0

2

1

0

–

UMSEL0 UPM01

UCSZ01 UCSZ00 UCPOL0

UCSR0C

Read/Write

Initial Value

R

0

R/W

0

R/W

0

R/W

1

R/W

1

R/W

0

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18.11.8 USART1 Control and Status Register C – UCSR1C

Bit

7

–

6

UMSEL1

R/W

5

UPM11

R/W

0

4

UPM10

R/W

0

3

USBS1

R/W

0

2

1

0

UCSZ11 UCSZ10 UCPO1L

UCSR1C

Read/Write

Initial Value

R

0

R/W

1

R/W

1

R/W

0

• Bit 7 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, these bit must be written

to zero when UCSRnC is written.

• Bit 6 – UMSELn: USARTn Mode Select

This bit selects between asynchronous and synchronous mode of operation.

Table 18-4. UMSELn Bit Settings

UMSELn

Mode

0

1

Asynchronous Operation

Synchronous Operation

• Bit 5:4 – UPMn1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting.

If a mismatch is detected, the UPEn Flag in UCSRnA will be set.

Table 18-5. UPMn Bits Settings

UPMn1

UPMn0

Parity Mode

0

1

0

1

0

1

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

• Bit 3 – USBSn: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

Table 18-6. USBSn Bit Settings

USBSn

Stop Bit(s)

1-bit

0

1

2-bit

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• Bit 2:1 – UCSZn1:0: Character Size

The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

Table 18-7. UCSZn Bits Settings

UCSZn2

UCSZn1

UCSZn0

Character Size

5-bit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6-bit

7-bit

8-bit

Reserved

9-bit

• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOLn bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCKn).

Table 18-8. UCPOLn Bit Settings

Transmitted Data Changed

(Output of TxDn Pin)

Received Data Sampled

(Input on RxDn Pin)

UCPOLn

0

1

Rising XCK Edge

Falling XCK Edge

Rising XCK Edge

18.11.9 USART0 Baud Rate Registers – UBRR0L and UBRR0H

Bit

15

14

13

12

11

10

9

8

–

UBRR0[11:8]

UBRR0H

UBRR0L

UBRR0[7:0]

7

R

6

R

5

R

4

R

3

R/W

0

2

R/W

0

1

R/W

0

R/W

0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

18.11.10 USART1 Baud Rate Registers – UBRR1L and UBRR1H

Bit

15

14

13

12

11

10

9

8

–

UBRR1[11:8]

UBRR1H

UBRR1L

UBRR1[7:0]

7

R

6

R

5

R

4

R

3

R/W

0

2

R/W

0

1

R/W

0

R/W

0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

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• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRnH is written.

• Bit 11:0 – UBRRn11:0: USARTn Baud Rate Register

This is a 12-bit register which contains the USARTn baud rate. The UBRRnH contains the four

most significant bits, and the UBRRnL contains the eight least significant bits of the USARTn

baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud

rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.

18.12 Examples of Baud Rate Setting

For standard crystal, resonator and external oscillator frequencies, the most commonly used

baud rates for asynchronous operation can be generated by using the UBRRn settings in Table

18-9 up to Table 18-12. UBRRn values which yield an actual baud rate differing less than 0.5%

from the target baud rate, are bold in the table. Higher error ratings are acceptable, but the

Receiver will have less noise resistance when the error ratings are high, especially for large

serial frames (see “Asynchronous Operational Range” on page 191). The error values are calcu-

lated using the following equation:

BaudRate_{Closest Match}

Error[%]

1

• 100%

BaudRate

Table 18-9. Examples of UBRRn Settings for Commonly Frequencies

fclk_io= 1.0000 MHz

fclk_io= 1.8432 MHz

fclk_io= 2.0000 MHz

Baud

Rate

(bps)

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

UBRRn Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

25

12

6

0.2%

51

25

12

8

0.2%

47

23

11

7

0.0%

95

47

23

15

11

7

0.0%

51

25

12

8

0.2%

103

51

25

16

12

8

0.2%

-7.0%

8.5%

-18.6%

8.5%

–

0.2%

-3.5%

-7.0%

8.5%

-18.6%

8.5%

–

0.0%

-25.0%

0.0%

–

0.0%

–

0.2%

-3.5%

-7.0%

8.5%

-18.6%

8.5%

–

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

–

3

2

6

5

6

1

3

1

2

5

2

6

0

1

3

1

3

–

1

2

1

2

–

0

1

0

1

–

0

–

500k

–

1M

–

Max. ⁽¹⁾

62.5 kbps

125 kbps

115.2 kbps

230.4 Kbps

125 kpbs

250 kbps

Note:

1. UBRRn = 0, Error = 0.0%

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Table 18-10. Examples of UBRRn Settings for Commonly Frequencies (Continued)

fclk_io= 3.6864 MHz

U2Xn = 0

fclk_io= 4.0000 MHz

U2Xn = 0

fclk_io= 7.3728 MHz

U2Xn = 0

Baud

Rate

(bps)

U2Xn = 1

UBRRn Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

95

47

23

15

11

7

0.0%

-7.8%

–

191

95

47

31

23

15

11

7

0.0%

103

51

25

16

12

8

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

207

103

51

34

25

16

12

8

0.2%

191

95

47

31

23

15

11

7

0.0%

-7.8%

–

383

191

95

63

47

31

23

15

11

7

0.0%

-7.8%

–

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

0.0%

-7.8%

5

6

3

2

5

2

6

5

1

3

1

3

0

1

0

1

3

0

1

0

1

3

500k

–

0

–

0

1

1M

–

0

Max.⁽¹⁾

230.4 kbps

460.8 kbps

250 kbps

0.5 Mbps

460.8 kpbs

921.6 kbps

Note:

1. UBRRn = 0, Error = 0.0%

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Table 18-11. Examples of UBRRn Settings for Commonly Frequencies (Continued)

fclk_io= 8.0000 MHz

fclk_io= 10.000 MHz

fclk_io= 11.0592 MHz

Baud

Rate

(bps)

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

UBRRn Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

207

103

51

34

25

16

12

8

0.2%

416

207

103

68

51

34

25

16

12

8

-0.1%

259

129

64

42

32

21

15

10

7

0.2%

520

259

129

86

64

42

32

21

15

10

4

0.0%

287

143

71

47

35

23

17

11

8

0.0%

575

287

143

95

71

47

35

23

17

11

5

0.0%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

8.5%

0.0%

0.2%

0.9%

-1.4%

1.8%

-1.5%

1.9%

9.6%

-16.8%

-33.3%

–

0.2%

0.9%

-1.4%

1.8%

-1.5%

9.6%

0.0%

-33.3%

–

0.0%

-7.8%

–

0.0%

-7.8%

–

6

3

4

5

1

3

2

1

3

2

4

2

5

500k

0

1

–

2

–

2

1M

–

0

–

Max. ⁽¹⁾

0.5 Mbps

1 Mbps

625 kbps

1.25 Mbps

691.2 kbps

1.3824 Mbps

Note:

1. UBRRn = 0, Error = 0.0%

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Table 18-12. Examples of UBRRn Settings for Commonly Frequencies (Continued)

fclk_io= 12.0000 MHz

fclk_io= 14.7456 MHz

fclk_io= 16.0000 MHz

Baud

Rate

(bps)

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

UBRRn Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

312

155

77

51

38

25

19

12

9

-0.2%

624

312

155

103

77

51

38

25

19

12

6

0.0%

383

191

95

63

47

31

23

15

11

7

0.0%

767

383

191

127

95

63

47

31

23

15

7

0.0%

416

207

103

68

51

34

25

16

12

8

-0.1%

832

416

207

138

103

68

51

34

25

16

8

0.0%

0.2%

-2.5%

0.2%

-2.7%

-8.9%

11.3%

0.0%

–

-0.2%

0.2%

-2.5%

0.2%

-8.9%

0.0%

–

0.0%

-7.8%

0.0%

5.3%

-7.8%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

8.5%

0.0%

-0.1%

0.2%

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

-3.5%

0.0%

6

2

3

2

5

3

6

3

7

500k

–

2

1

3

1

3

1M

–

0

1

0

1

Max. ⁽¹⁾

750 kbps

1.5 Mbps

921.6 kbps

1.8432 Mbps

1 Mbps

2 Mbps

Note:

1. UBRRn = 0, Error = 0.0%

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19. Two-wire Serial Interface

19.1 Features

• Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed

• Both Master and Slave Operation Supported

• Device can Operate as Transmitter or Receiver

• 7-bit Address Space allows up to 128 Different Slave Addresses

• Multi-master Arbitration Support

• Up to 400 kHz Data Transfer Speed

• Slew-rate Limited Output Drivers

• Noise Suppression Circuitry Rejects Spikes on Bus Lines

• Fully Programmable Slave Address with General Call Support

• Address Recognition Causes Wake-up when AVR is in Sleep Mode

19.2 Two-wire Serial Interface Bus Definition

The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The

TWI protocol allows the systems designer to interconnect up to 128 different devices using only

two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-

ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All

devices connected to the bus have individual addresses, and mechanisms for resolving bus

contention are inherent in the TWI protocol.

Figure 19-1. TWI Bus Interconnection

Device 1

Device 3

Device 2

Device n

........

V_CC

R1

R2

SDA

SCL

19.2.1

TWI Terminology

The following definitions are frequently encountered in this section.

Table 19-1. TWI Terminology

Term

Description

The device that initiates and terminates a transmission. The master also generates the

SCL clock

Master

Slave

The device addressed by a master

The device placing data on the bus

The device reading data from the bus

Transmitter

Receiver

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19.2.2

Electrical Interconnection

As depicted in Figure 19-1, both bus lines are connected to the positive supply voltage through

pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.

This implements a wired-AND function which is essential to the operation of the interface. A low

level on a TWI bus line is generated when one or more TWI devices output a zero. A high level

is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line

high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any

bus operation.

The number of devices that can be connected to the bus is only limited by the bus capacitance

limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-

acteristics of the TWI is given in “Two-wire Serial Interface Characteristics” on page 368. Two

different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,

and one valid for bus speeds up to 400 kHz.

19.3 Data Transfer and Frame Format

19.3.1

Transferring Bits

Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level

of the data line must be stable when the clock line is high. The only exception to this rule is for

generating start and stop conditions.

Figure 19-2. Data Validity

SDA

SCL

Data Stable

Data Change

19.3.2

START and STOP Conditions

The master initiates and terminates a data transmission. The transmission is initiated when the

master issues a START condition on the bus, and it is terminated when the master issues a

STOP condition. Between a START and a STOP condition, the bus is considered busy, and no

other master should try to seize control of the bus. A special case occurs when a new START

condition is issued between a START and STOP condition. This is referred to as a REPEATED

START condition, and is used when the master wishes to initiate a new transfer without relin-

quishing control of the bus. After a REPEATED START, the bus is considered busy until the next

STOP. This is identical to the START behaviour, and therefore START is used to describe both

START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As

depicted below, START and STOP conditions are signalled by changing the level of the SDA

line when the SCL line is high.

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Figure 19-3. START, REPEATED START and STOP Conditions

SDA

SCL

START

STOP START

REPEATED START

STOP

19.3.3

Address Packet Format

All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one

READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read opera-

tion is to be performed, otherwise a write operation should be performed. When a slave

recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL

(ACK) cycle. If the addressed slave is busy, or for some other reason can not service the mas-

ter’s request, the SDA line should be left high in the ACK clock cycle. The master can then

transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An

address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or

SLA+W, respectively.

The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the

designer, but the address 0000 000 is reserved for a general call.

When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK

cycle. A general call is used when a master wishes to transmit the same message to several

slaves in the system. When the general call address followed by a Write bit is transmitted on the

bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle.

The following data packets will then be received by all the slaves that acknowledged the general

call. Note that transmitting the general call address followed by a Read bit is meaningless, as

this would cause contention if several slaves started transmitting different data.

All addresses of the format 1111 xxx should be reserved for future purposes.

Figure 19-4. Address Packet Format

Addr MSB

Addr LSB

R/W

ACK

SDA

SCL

1

2

7

8

9

START

19.3.4

Data Packet Format

All data packets transmitted on the TWI bus are 9 bits long, consisting of one data byte and an

acknowledge bit. During a data transfer, the master generates the clock and the START and

STOP conditions, while the receiver is responsible for acknowledging the reception. An

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Acknowledge (ACK) is signalled by the receiver pulling the SDA line low during the ninth SCL

cycle. If the receiver leaves the SDA line high, a NACK is signalled. When the receiver has

received the last byte, or for some reason cannot receive any more bytes, it should inform the

transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.

Figure 19-5. Data Packet Format

Data MSB

Data LSB

ACK

Aggregate

SDA

SDA from

Transmitter

SDA from

Receiver

SCL from

Master

1

2

7

8

9

STOP, REPEATED

START or Next

Data Byte

SLA+R/W

Data Byte

19.3.5

Combining Address and Data Packets Into a Transmission

A transmission basically consists of a START condition, a SLA+R/W, one or more data packets

and a STOP condition. An empty message, consisting of a START followed by a STOP condi-

tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement

handshaking between the master and the slave. The slave can extend the SCL low period by

pulling the SCL line low. This is useful if the clock speed set up by the master is too fast for the

slave, or the slave needs extra time for processing between the data transmissions. The slave

extending the SCL low period will not affect the SCL high period, which is determined by the

master. As a consequence, the slave can reduce the TWI data transfer speed by prolonging the

SCL duty cycle.

Figure 19-6 shows a typical data transmission. Note that several data bytes can be transmitted

between the SLA+R/W and the STOP condition, depending on the software protocol imple-

mented by the application software.

Figure 19-6. Typical Data Transmission

Addr MSB

Addr LSB R/W

ACK

Data MSB

Data LSB ACK

SDA

SCL

1

2

7

8

9

1

2

7

8

9

START

SLA+R/W

Data Byte

STOP

19.4 Multi-master Bus Systems, Arbitration and Synchronization

The TWI protocol allows bus systems with several masters. Special concerns have been taken

in order to ensure that transmissions will proceed as normal, even if two or more masters initiate

a transmission at the same time. Two problems arise in multi-master systems:

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• An algorithm must be implemented allowing only one of the masters to complete the

transmission. All other masters should cease transmission when they discover that they have

lost the selection process. This selection process is called arbitration. When a contending

master discovers that it has lost the arbitration process, it should immediately switch to slave

mode to check whether it is being addressed by the winning master. The fact that multiple

masters have started transmission at the same time should not be detectable to the slaves,

i.e., the data being transferred on the bus must not be corrupted.

• Different masters may use different SCL frequencies. A scheme must be devised to

synchronize the serial clocks from all masters, in order to let the transmission proceed in a

lockstep fashion. This will facilitate the arbitration process.

The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from

all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one

from the master with the shortest high period. The low period of the combined clock is equal to

the low period of the master with the longest low period. Note that all masters listen to the SCL

line, effectively starting to count their SCL high and low time-out periods when the combined

SCL line goes high or low, respectively.

Figure 19-7. SCL Synchronization between Multiple Masters

TA_low

TA_high

SCL from

master A

SCL from

master B

SCL Bus

Line

TB_low

TB_high

Masters Start

Counting Low Period

Counting High Period

Arbitration is carried out by all masters continuously monitoring the SDA line after outputting

data. If the value read from the SDA line does not match the value the master had output, it has

lost the arbitration. Note that a master can only lose arbitration when it outputs a high SDA value

while another master outputs a low value. The losing master should immediately go to slave

mode, checking if it is being addressed by the winning master. The SDA line should be left high,

but losing masters are allowed to generate a clock signal until the end of the current data or

address packet. Arbitration will continue until only one master remains, and this may take many

bits. If several masters are trying to address the same slave, arbitration will continue into the

data packet.

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Figure 19-8. Arbitration Between two Masters

START

Master A loses

Arbitration, SDA SDA

A

SDA from

Master A

SDA from

Master B

SDA Line

Synchronized

SCL Line

Note that arbitration is not allowed between:

• A REPEATED START condition and a data bit

• A STOP condition and a data bit

• A REPEATED START and a STOP condition

It is the user software’s responsibility to ensure that these illegal arbitration conditions never

occur. This implies that in multi-master systems, all data transfers must use the same composi-

tion of SLA+R/W and data packets. In other words: All transmissions must contain the same

number of data packets, otherwise the result of the arbitration is undefined.

19.5 Overview of the TWI Module

The TWI module is comprised of several submodules, as shown in Figure 19-9. All registers

drawn in a thick line are accessible through the AVR data bus.

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Figure 19-9. Overview of the TWI Module

SCL

SDA

Spike

Filter

Spike

Filter

Slew-rate

Control

Slew-rate

Control

Bus Interface Unit

Bit Rate Generator

START / STOP

Control

Spike Suppression

Prescaler

Address/Data Shift

Register (TWDR)

Bit Rate Register

(TWBR)

Arbitration detection

Ack

Address Match Unit

Control Unit

Address Register

(TWAR)

Status Register

(TWSR)

Control Register

(TWCR)

TWI

Unit

State Machine and

Status control

Address Comparator

19.5.1

SCL and SDA Pins

These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a

slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike

suppression unit removing spikes shorter than 50 ns. Note that the internal pullups in the AVR

pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as

explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need

for external ones.

19.5.2

Bit Rate Generator Unit

This unit controls the period of SCL when operating in a Master mode. The SCL period is con-

trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status

Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the

CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note

that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock

period. The SCL frequency is generated according to the following equation:

CLKio

SCL frequency

16 2(TWBR) ⋅ 4

• TWBR = Value of the TWI Bit Rate Register

• TWPS = Value of the prescaler bits in the TWI Status Register

Note:

TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than 10, the

master may produce an incorrect output on SDA and SCL for the reminder of the byte. The prob-

lem occurs when operating the TWI in Master mode, sending Start + SLA + R/W to a slave (a

slave does not need to be connected to the bus for the condition to happen).

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19.5.3

Bus Interface Unit

This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and

Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,

or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also

contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-

ter is not directly accessible by the application software. However, when receiving, it can be set

or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the

value of the received (N)ACK bit can be determined by the value in the TWSR.

The START/STOP Controller is responsible for generation and detection of START, REPEATED

START, and STOP conditions. The START/STOP controller is able to detect START and STOP

conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up

if addressed by a master.

If the TWI has initiated a transmission as master, the Arbitration Detection hardware continu-

ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost

an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate

status codes generated.

19.5.4

Address Match Unit

The Address Match unit checks if received address bytes match the 7-bit address in the TWI

Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the

TWAR is written to one, all incoming address bits will also be compared against the General Call

address. Upon an address match, the Control Unit is informed, allowing correct action to be

taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.

The Address Match unit is able to compare addresses even when the AVR MCU is in sleep

mode, enabling the MCU to wake up if addressed by a master. If another interrupt (e.g., INT0)

occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera-

tion and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the

only enabled interrupt when entering Power-down.

19.5.5

Control Unit

The Control unit monitors the TWI bus and generates responses corresponding to settings in the

TWI Control Register (TWCR). When an event requiring the attention of the application occurs

on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Sta-

tus Register (TWSR) is updated with a status code identifying the event. The TWSR only

contains relevant status information when the TWI Interrupt Flag is asserted. At all other times,

the TWSR contains a special status code indicating that no relevant status information is avail-

able. As long as the TWINT flag is set, the SCL line is held low. This allows the application

software to complete its tasks before allowing the TWI transmission to continue.

The TWINT flag is set in the following situations:

• After the TWI has transmitted a START/REPEATED START condition

• After the TWI has transmitted SLA+R/W

• After the TWI has transmitted an address byte

• After the TWI has lost arbitration

• After the TWI has been addressed by own slave address or general call

• After the TWI has received a data byte

• After a STOP or REPEATED START has been received while still addressed as a slave

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• When a bus error has occurred due to an illegal START or STOP condition

19.6 TWI Register Description

19.6.1

TWI Bit Rate Register – TWBR

Bit

7

TWBR7

R/W

0

6

TWBR6

R/W

0

5

TWBR5

R/W

0

4

TWBR4

R/W

0

3

TWBR3

R/W

0

2

TWBR2

R/W

0

1

TWBR1

R/W

0

TWBR0

R/W

0

TWBR

Read/Write

Initial Value

• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency

divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator

Unit” on page 209 for calculating bit rates.

19.6.2

TWI Control Register – TWCR

Bit

7

6

TWEA

R/W

0

5

TWSTA

R/W

0

4

TWSTO

R/W

0

3

2

TWEN

R/W

0

1

–

0

TWIE

R/W

0

TWINT

R/W

0

TWWC

TWCR

Read/Write

Initial Value

R

0

R

0

The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a

master access by applying a START condition to the bus, to generate a receiver acknowledge,

to generate a stop condition, and to control halting of the bus while the data to be written to the

bus are written to the TWDR. It also indicates a write collision if data is attempted written to

TWDR while the register is inaccessible.

• Bit 7 – TWINT: TWI Interrupt Flag

This bit is set by hardware when the TWI has finished its current job and expects application

software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the

TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT

flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-

cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag

starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta-

tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this

flag.

• Bit 6 – TWEA: TWI Enable Acknowledge Bit

The TWEA bit controls the generation of the ACK pulse. If the TWEA bit is written to one, the

ACK pulse is generated on the TWI bus if the following conditions are met:

1. The device’s own slave address has been received.

2. A general call has been received, while the TWGCE bit in the TWAR is set.

3. A data byte has been received in Master Receiver or Slave Receiver mode.

By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-wire

Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one

again.

• Bit 5 – TWSTA: TWI START Condition Bit

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The application writes the TWSTA bit to one when it desires to become a master on the Two-

wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START con-

dition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition

is detected, and then generates a new START condition to claim the bus Master status. TWSTA

must be cleared by software when the START condition has been transmitted.

• Bit 4 – TWSTO: TWI STOP Condition Bit

Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire

Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto-

matically. In slave mode, setting the TWSTO bit can be used to recover from an error condition.

This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed

Slave mode and releases the SCL and SDA lines to a high impedance state.

• Bit 3 – TWWC: TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is

low. This flag is cleared by writing the TWDR Register when TWINT is high.

• Bit 2 – TWEN: TWI Enable Bit

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to

one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the

slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI

transmissions are terminated, regardless of any ongoing operation.

• Bit 1 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, this must be written to

zero when TWCR is written.

• Bit 0 – TWIE: TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-

vated for as long as the TWINT flag is high.

19.6.3

TWI Status Register – TWSR

Bit

7

6

TWS6

R

5

TWS5

R

4

TWS4

R

3

TWS3

R

2

–

1

TWPS1

R/W

0

TWPS0

R/W

0

TWS7

TWSR

Read/Write

Initial Value

R

1

R

0

1

• Bits 7..3 – TWS: TWI Status

These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status

codes are described later in this section. Note that the value read from TWSR contains both the

5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-

caler bits to zero when checking the Status bits. This makes status checking independent of

prescaler setting. This approach is used in this datasheet, unless otherwise noted.

• Bit 2 – Res: Reserved Bit

This bit is reserved and will always read as zero.

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• Bits 1..0 – TWPS: TWI Prescaler Bits

These bits can be read and written, and control the bit rate prescaler.

Table 19-2. TWI Bit Rate Prescaler

TWPS1

TWPS0

Prescaler Value

0

1

0

1

0

1

4

16

64

To calculate bit rates, see “Bit Rate Generator Unit” on page 209. The value of TWPS1..0 is

used in the equation.

19.6.4

TWI Data Register – TWDR

Bit

7

TWD7

R/W

1

6

TWD6

R/W

1

5

TWD5

R/W

1

4

TWD4

R/W

1

3

TWD3

R/W

1

2

TWD2

R/W

1

TWD1

R/W

1

0

TWD0

R/W

1

TWDR

Read/Write

Initial Value

In Transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR

contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.

This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the Data Register

cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains sta-

ble as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted

in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep

mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost

bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is

controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.

• Bits 7..0 – TWD: TWI Data Register

These eight bits constitute the next data byte to be transmitted, or the latest data byte received

on the TWI Serial Bus.

19.6.5

TWI (Slave) Address Register – TWAR

Bit

7

6

5

TWA4

R/W

1

4

TWA3

R/W

1

3

TWA2

R/W

1

2

TWA1

R/W

1

TWA0

R/W

1

0

TWGCE

R/W

0

TWA6

R/W

1

TWA5

R/W

1

TWAR

Read/Write

Initial Value

• Bits 7..1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TWI unit. The TWAR should be loaded with

the 7-bit slave address to which the TWI will respond when programmed as a slave transmitter

or receiver, and not needed in the master modes. In multimaster systems, TWAR must be set in

masters which can be addressed as slaves by other masters.

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

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TWGCE is used to enable recognition of the general call address (0x00). There is an associated

address comparator that looks for the slave address (or general call address if enabled) in the

received serial address. If a match is found, an interrupt request is generated. If set, this bit

enables the recognition of a General Call given over the TWI Serial Bus.

19.7 Using the TWI

The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like

reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,

the application software is free to carry on other operations during a TWI byte transfer. Note that

the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in

SREG allow the application to decide whether or not assertion of the TWINT flag should gener-

ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT flag in

order to detect actions on the TWI bus.

When the TWINT flag is asserted, the TWI has finished an operation and awaits application

response. In this case, the TWI Status Register (TWSR) contains a value indicating the current

state of the TWI bus. The application software can then decide how the TWI should behave in

the next TWI bus cycle by manipulating the TWCR and TWDR Registers.

Figure 19-10 is a simple example of how the application can interface to the TWI hardware. In

this example, a master wishes to transmit a single data byte to a slave. This description is quite

abstract, a more detailed explanation follows later in this section. A simple code example imple-

menting the desired behaviour is also presented.

Figure 19-10. Interfacing the Application to the TWI in a Typical Transmission

1. Application

writes to TWCR

to initiate

transmission of

START.

3. Check TWSR to see if

5. Check TWSR to see if SLA+W

was sent and ACK received.

Application loads data into TWDR,

and loads appropriate control signals

into TWCR, making sure that TWINT

is written to one.

7. Check TWSR to see if data

was sent and ACK received.

Application loads appropriate

control signals to send STOP

into TWCR, making sure that

TWINT is written to one.

START was sent. Application

loads SLA+W into TWDR, and

loads appropriate control signals

into TWCR, making sure that

TWINT is written to one.

TWI bus

START

SLA+W

A

Data

A

STOP

Indicates

TWINT set

2. TWINT set.

Status code indicates

START condition sent

4. TWINT set.

Status code indicates

SLA+W sendt,

6. TWINT set.

Status code indicates

data sent,

TWI

Hardware

Action

ACK received

1. The first step in a TWI transmission is to transmit a START condition. This is done by

writing a specific value into TWCR, instructing the TWI hardware to transmit a START

condition. Which value to write is described later on. However, it is important that the

TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI

will not start any operation as long as the TWINT bit in TWCR is set. Immediately after

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the application has cleared TWINT, the TWI will initiate transmission of the START

condition.

2. When the START condition has been transmitted, the TWINT flag in TWCR is set, and

TWSR is updated with a status code indicating that the START condition has success-

fully been sent.

3. The application software should now examine the value of TWSR, to make sure that

the START condition was successfully transmitted. If TWSR indicates otherwise, the

application software might take some special action, like calling an error routine.

Assuming that the status code is as expected, the application must load SLA+W into

TWDR. Remember that TWDR is used both for address and data. After TWDR has

been loaded with the desired SLA+W, a specific value must be written to TWCR,

instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to

write is described later on. However, it is important that the TWINT bit is set in the value

written. Writing a one to TWINT clears the flag. The TWI will not start any operation as

long as the TWINT bit in TWCR is set. Immediately after the application has cleared

TWINT, the TWI will initiate transmission of the address packet.

4. When the address packet has been transmitted, the TWINT flag in TWCR is set, and

TWSR is updated with a status code indicating that the address packet has success-

fully been sent. The status code will also reflect whether a slave acknowledged the

packet or not.

5. The application software should now examine the value of TWSR, to make sure that

the address packet was successfully transmitted, and that the value of the ACK bit was

as expected. If TWSR indicates otherwise, the application software might take some

special action, like calling an error routine. Assuming that the status code is as

expected, the application must load a data packet into TWDR. Subsequently, a specific

value must be written to TWCR, instructing the TWI hardware to transmit the data

packet present in TWDR. Which value to write is described later on. However, it is

important that the TWINT bit is set in the value written. Writing a one to TWINT clears

the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.

Immediately after the application has cleared TWINT, the TWI will initiate transmission

of the data packet.

6. When the data packet has been transmitted, the TWINT flag in TWCR is set, and

TWSR is updated with a status code indicating that the data packet has successfully

been sent. The status code will also reflect whether a slave acknowledged the packet

or not.

7. The application software should now examine the value of TWSR, to make sure that

the data packet was successfully transmitted, and that the value of the ACK bit was as

expected. If TWSR indicates otherwise, the application software might take some spe-

cial action, like calling an error routine. Assuming that the status code is as expected,

the application must write a specific value to TWCR, instructing the TWI hardware to

transmit a STOP condition. Which value to write is described later on. However, it is

important that the TWINT bit is set in the value written. Writing a one to TWINT clears

the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.

Immediately after the application has cleared TWINT, the TWI will initiate transmission

of the STOP condition. Note that TWINT is NOT set after a STOP condition has been

sent.

Even though this example is simple, it shows the principles involved in all TWI transmissions.

These can be summarized as follows:

• When the TWI has finished an operation and expects application response, the TWINT flag is

set. The SCL line is pulled low until TWINT is cleared.

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• When the TWINT flag is set, the user must update all TWI Registers with the value relevant

for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be

transmitted in the next bus cycle.

• After all TWI Register updates and other pending application software tasks have been

completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a

one to TWINT clears the flag. The TWI will then commence executing whatever operation

was specified by the TWCR setting.

In the following an assembly and C implementation of the example is given. Note that the code

below assumes that several definitions have been made for example by using include-files.

Assembly Code Example

C Example

Comments

ldi

r16, (1<<TWINT)|

(1<<TWSTA)|

(1<<TWEN)

TWCR = (1<<TWINT)|

(1<<TWSTA)|

Send START condition

1

2

(1<<TWEN)

sts

TWCR, r16

wait1:

lds

sbrs

rjmp

r16,TWCR

r16,TWINT

wait1

Wait for TWINT flag set. This indicates that

the START condition has been transmitted

while (!(TWCR & (1<<TWINT)));

lds

andi

cpi

r16,TWSR

r16, 0xF8

r16, START

ERROR

Check value of TWI Status Register. Mask

prescaler bits. If status different from START

go to ERROR

if ((TWSR & 0xF8) != START)

ERROR();

brne

3

4

5

ldi

sts

ldi

r16, SLA_W

TWDR, r16

r16, (1<<TWINT)|

(1<<TWEN)

TWDR = SLA_W;

TWCR = (1<<TWINT)|(1<<TWEN);

Load SLA_W into TWDR Register. Clear

TWINT bit in TWCR to start transmission of

address

sts

TWCR, r16

wait2:

lds

sbrs

rjmp

Wait for TWINT flag set. This indicates that

the SLA+W has been transmitted, and

ACK/NACK has been received.

r16,TWCR

r16,TWINT

wait2

while (!(TWCR & (1<<TWINT)));

lds

andi

cpi

r16,TWSR

Check value of TWI Status Register. Mask

prescaler bits. If status different from

MT_SLA_ACK go to ERROR

if ((TWSR & 0xF8)!= MT_SLA_ACK)

r16, 0xF8

r16, MT_SLA_ACK

ERROR

ERROR();

brne

ldi

sts

ldi

r16, DATA

TWDR, r16

r16, (1<<TWINT)|

(1<<TWEN)

TWDR = DATA;

TWCR = (1<<TWINT)|(1<<TWEN);

Load DATA into TWDR Register. Clear TWINT

bit in TWCR to start transmission of data

sts

TWCR, r16

wait3:

lds

sbrs

rjmp

while (!(TWCR & (1<<TWINT)));

Wait for TWINT flag set. This indicates that

the DATA has been transmitted, and

ACK/NACK has been received.

r16,TWCR

r16,TWINT

wait3

6

7

lds

andi

cpi

r16,TWSR

Check value of TWI Status Register. Mask

prescaler bits. If status different from

MT_DATA_ACK go to ERROR

if ((TWSR & 0xF8)!=MT_DATA_ACK)

r16, 0xF8

r16, MT_DATA_ACK

ERROR

ERROR();

brne

ldi

sts

r16, (1<<TWINT)|

(1<<TWEN) |

TWCR = (1<<TWINT)|

(1<<TWEN) |

Transmit STOP condition

(1<<TWSTO)

(1<<TWSTO);

TWCR, r16

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19.8 Transmission Modes

The TWI can operate in one of four major modes. These are named Master Transmitter (MT),

Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these

modes can be used in the same application. As an example, the TWI can use MT mode to write

data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters

are present in the system, some of these might transmit data to the TWI, and then SR mode

would be used. It is the application software that decides which modes are legal.

The following sections describe each of these modes. Possible status codes are described

along with figures detailing data transmission in each of the modes. These figures contain the

following abbreviations:

S:

START condition

Rs:

R:

REPEATED START condition

Read bit (high level at SDA)

Write bit (low level at SDA)

Acknowledge bit (low level at SDA)

Not acknowledge bit (high level at SDA)

W:

A:

Data: 8-bit data byte

P: STOP condition

SLA: Slave Address

In Figure 19-12 to Figure 19-18, circles are used to indicate that the TWINT flag is set. The num-

bers in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At

these points, actions must be taken by the application to continue or complete the TWI transfer.

The TWI transfer is suspended until the TWINT flag is cleared by software.

When the TWINT flag is set, the status code in TWSR is used to determine the appropriate soft-

ware action. For each status code, the required software action and details of the following serial

transfer are given in Table 19-3 to Table 19-6. Note that the prescaler bits are masked to zero in

these tables.

19.8.1

Master Transmitter Mode

In the Master Transmitter mode, a number of data bytes are transmitted to a slave receiver (see

Figure 19-11). In order to enter a Master mode, a START condition must be transmitted. The for-

mat of the following address packet determines whether Master Transmitter or Master Receiver

mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted,

MR mode is entered. All the status codes mentioned in this section assume that the prescaler

bits are zero or are masked to zero.

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Figure 19-11. Data Transfer in Master Transmitter Mode

Device 1

MASTER

TRANSMITTER

Device 2

SLAVE

RECEIVER

Device 3

Device n

........

V_CC

R1

R2

SDA

SCL

A START condition is sent by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to

transmit a START condition and TWINT must be written to one to clear the TWINT flag. The TWI

will then test the Two-wire Serial Bus and generate a START condition as soon as the bus

becomes free. After a START condition has been transmitted, the TWINT flag is set by hard-

ware, and the status code in TWSR will be 0x08 (See Table 19-3). In order to enter MT mode,

SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit

should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing

the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

When SLA+W have been transmitted and an acknowledgment bit has been received, TWINT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes

is detailed in Table 19-3.

When SLA+W has been successfully transmitted, a data packet should be transmitted. This is

done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,

the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-

ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the

transfer. This is accomplished by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

This scheme is repeated until the last byte has been sent and the transfer is ended by generat-

ing a STOP condition or a repeated START condition. A STOP condition is generated by writing

the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

1

X

1

0

X

A REPEATED START condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

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After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the

same slave again, or a new slave without transmitting a STOP condition. Repeated START

enables the master to switch between slaves, Master Transmitter mode and Master Receiver

mode without losing control of the bus.

Table 19-3. Status Codes for Master Transmitter Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

To TWCR

Status of the Two-wire Serial Bus

and Two-wire Serial Interface

Hardware

Next Action Taken by TWI Hardware

To/from TWDR

STA

X

STO

0

TWINT

1

TWEA

X

0x08

A

START condition has been Load SLA+W

SLA+W will be transmitted;

transmitted

ACK or NOT ACK will be received

0x10

A repeated START condition has Load SLA+W or

been transmitted

X

0

1

X

SLA+W will be transmitted;

ACK or NOT ACK will be received

SLA+R will be transmitted;

Load SLA+R

Logic will switch to master receiver mode

0x18

0x20

0x28

0x30

0x38

SLA+W has been transmitted;

ACK has been received

Load data byte or

0

1

X

Data byte will be transmitted and ACK or NOT ACK will be

received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO flag will be reset

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

Load data byte or

1

0

1

0

1

X

SLA+W has been transmitted;

NOT ACK has been received

Data byte will be transmitted and ACK or NOT ACK will be

received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO flag will be reset

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

1

0

1

0

1

X

Data byte has been transmitted; Load data byte or

ACK has been received

Data byte will be transmitted and ACK or NOT ACK will be

received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO flag will be reset

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

1

0

1

0

1

X

Data byte has been transmitted; Load data byte or

NOT ACK has been received

No TWDR action or

Data byte will be transmitted and ACK or NOT ACK will be

received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO flag will be reset

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

1

0

1

X

No TWDR action or

No TWDR action

1

X

Arbitration lost in SLA+W or data No TWDR action or

bytes

0

1

0

1

X

Two-wire Serial Bus will be released and not addressed

slave mode entered

A START condition will be transmitted when the bus be-

comes free

No TWDR action

219

7538B–CAN–05/06

Figure 19-12. Formats and States in the Master Transmitter Mode

MT

Successfull

S

SLA

W

A

DATA

A

P

transmission

to a slave

receiver

0x08

0x18

0x28

Next transfer

started with a

repeated start

condition

R_S

SLA

W

R

0x10

Not acknowledge

received after the

slave address

A

P

0x20

MR

Not acknowledge

received after a data

byte

A

P

0x30

Arbitration lost in slave

address or data byte

Other master

continues

Other master

continues

A or A

0x38

A

0x38

Arbitration lost and

addressed as slave

Other master

continues

To corresponding

states in slave mode

0x68 0x78 0xB0

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-wire Serial Bus. The

prescaler bits are zero or masked to zero

n

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19.8.2

Master Receiver Mode

In the Master Receiver Mode, a number of data bytes are received from a slave transmitter (see

Figure 19-13). In order to enter a Master mode, a START condition must be transmitted. The for-

mat of the following address packet determines whether Master Transmitter or Master Receiver

mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted,

MR mode is entered. All the status codes mentioned in this section assume that the prescaler

bits are zero or are masked to zero.

Figure 19-13. Data Transfer in Master Receiver Mode

Device 1

MASTER

RECEIVER

Device 2

Device 3

SLAVE

Device n

........

TRANSMITTER

V_CC

R1

R2

SDA

SCL

A START condition is sent by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to

one to transmit a START condition and TWINT must be set to clear the TWINT flag. The TWI will

then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes

free. After a START condition has been transmitted, the TWINT flag is set by hardware, and the

status code in TWSR will be 0x08 (See Table 19-3). In order to enter MR mode, SLA+R must be

transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be

cleared (by writing it to one) to continue the transfer. This is accomplished by writing the follow-

ing value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

When SLA+R have been transmitted and an acknowledgment bit has been received, TWINT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes

is detailed in Table 19-12. Received data can be read from the TWDR Register when the TWINT

flag is set high by hardware. This scheme is repeated until the last byte has been received. After

the last byte has been received, the MR should inform the ST by sending a NACK after the last

received data byte. The transfer is ended by generating a STOP condition or a repeated START

condition. A STOP condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

1

X

1

0

X

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A REPEATED START condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the

same slave again, or a new slave without transmitting a STOP condition. Repeated START

enables the master to switch between slaves, Master Transmitter mode and Master Receiver

mode without losing control over the bus.

Figure 19-14. Formats and States in the Master Receiver Mode

MR

Successfull

reception

S

SLA

R

A

DATA

A

DATA

A

P

from a slave

receiver

0x08

0x40

0x50

0x58

Next transfer

started with a

repeated start

condition

R_S

SLA

R

0x10

Not acknowledge

received after the

slave address

W

A

P

0x48

MT

Arbitration lost in slave

address or data byte

Other master

continues

Other master

continues

A or A

A

0x38

A

0x38

Arbitration lost and

addressed as slave

Other master

continues

To corresponding

states in slave mode

0x68 0x78 0xB0

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-wire Serial Bus. The

prescaler bits are zero or masked to zero

n

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Table 19-4. Status Codes for Master Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

Status of the Two-wire Serial Bus

and Two-wire Serial Interface

Hardware

To TWCR

Next Action Taken by TWI Hardware

To/from TWDR

STA

X

STO

0

TWINT

1

TWEA

X

0x08

A

START condition has been Load SLA+R

SLA+R will be transmitted

transmitted

ACK or NOT ACK will be received

0x10

A repeated START condition has Load SLA+R or

been transmitted

X

0

1

X

SLA+R will be transmitted

ACK or NOT ACK will be received

SLA+W will be transmitted

Load SLA+W

Logic will switch to master transmitter mode

0x38

0x40

0x48

Arbitration lost in SLA+R or NOT No TWDR action or

0

1

0

1

X

Two-wire Serial Bus will be released and not addressed

slave mode will be entered

A START condition will be transmitted when the bus

becomes free

ACK bit

No TWDR action

SLA+R has been transmitted;

ACK has been received

No TWDR action or

No TWDR action

0

1

0

1

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

SLA+R has been transmitted;

NOT ACK has been received

No TWDR action or

1

0

1

X

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO flag will

be reset

No TWDR action

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

0x50

0x58

Data byte has been received;

ACK has been returned

Read data byte or

Read data byte

0

1

0

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0

1

Data byte has been received;

NOT ACK has been returned

Read data byte or

1

0

1

X

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO flag will

be reset

Read data byte

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

19.8.3

Slave Receiver Mode

In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see

Figure 19-15). All the status codes mentioned in this section assume that the prescaler bits are

zero or are masked to zero.

Figure 19-15. Data Transfer in Slave Receiver Mode

Device 1

Device 2

MASTER

TRANSMITTER

Device 3

SLAVE

Device n

........

RECEIVER

V_CC

R1

R2

SDA

SCL

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To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

The upper seven bits are the address to which the Two-wire Serial Interface will respond when

addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00),

otherwise it will ignore the general call address.

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

0

1

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgment of the device’s own slave address or the general call address. TWSTA and

TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After

its own slave address and the write bit have been received, the TWINT flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 19-5.

The slave receiver mode may also be entered if arbitration is lost while the TWI is in the master

mode (see states 0x68 and 0x78).

If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA

after the next received data byte. This can be used to indicate that the slave is not able to

receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave

address. However, the Two-wire Serial Bus is still monitored and address recognition may

resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily

isolate the TWI from the Two-wire Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep

and the TWI will hold the SCL clock low during the wake up and until the TWINT flag is cleared

(by writing it to one). Further data reception will be carried out as normal, with the AVR clocks

running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may

be held low for a long time, blocking other data transmissions.

Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte

present on the bus when waking up from these sleep modes.

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Table 19-5. Status Codes for Slave Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

Status of the Two-wire Serial Bus

and Two-wire Serial Interface Hard-

ware

To TWCR

Next Action Taken by TWI Hardware

To/from TWDR

STA

X

STO

0

TWINT

1

TWEA

0

0x60

0x68

0x70

0x78

Own SLA+W has been received;

ACK has been returned

No TWDR action or

No TWDR action

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

X

0

1

0

Arbitration lost in SLA+R/W as mas- No TWDR action or

ter; own SLA+W has been

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

received; ACK has been returned

No TWDR action

X

0

1

0

General call address has been

received; ACK has been returned

No TWDR action or

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

No TWDR action

X

0

1

0

Arbitration lost in SLA+R/W as mas- No TWDR action or

ter; General call address has been

Data byte will be received and NOT ACK will be

returned

received; ACK has been

returned

No TWDR action

X

0

1

0

Data byte will be received and ACK will be returned

0x80

0x88

Previously addressed with own Read data byte or

SLA+W; data has been received;

Data byte will be received and NOT ACK will be

returned

ACK has been returned

Read data byte

X

0

1

0

Data byte will be received and ACK will be returned

Previously addressed with own Read data byte or

SLA+W; data has been received;

NOT ACK has been returned

Switched to the not addressed slave mode;

no recognition of own SLA or GCA

Switched to the not addressed slave mode;

own SLA will be recognized;

Read data byte or

0

1

GCA will be recognized if TWGCE = “1”

Switched to the not addressed slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Switched to the not addressed slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

Read data byte or

1

0

1

0

Read data byte

1

0

1

0

0x90

0x98

Previously addressed with

general call; data has been re-

ceived; ACK has been returned

Read data byte or

X

Data byte will be received and NOT ACK will be

returned

Read data byte

X

0

1

0

Data byte will be received and ACK will be returned

Previously addressed with

general call; data has been

received; NOT ACK has been

returned

Read data byte or

Switched to the not addressed slave mode;

no recognition of own SLA or GCA

Switched to the not addressed slave mode;

own SLA will be recognized;

Read data byte or

0

1

GCA will be recognized if TWGCE = “1”

Switched to the not addressed slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Read data byte or

1

0

1

0

Read data byte

1

0

1

Switched to the not addressed slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

0xA0

A

STOP condition or repeated Read data byte or

0

1

0

1

Switched to the not addressed slave mode;

no recognition of own SLA or GCA

Switched to the not addressed slave mode;

own SLA will be recognized;

START condition has been

received while still addressed as Read data byte or

slave

GCA will be recognized if TWGCE = “1”

Switched to the not addressed slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Switched to the not addressed slave mode;

own SLA will be recognized;

Read data byte or

1

0

1

0

1

Read data byte

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

225

7538B–CAN–05/06

Figure 19-16. Formats and States in the Slave Receiver Mode

Reception of the

S

SLA

W

A

DATA

A

DATA

A

P or S

own slave address

and one or more

data bytes. All are

acknowledged

0x60

0x80

A

0xA0

Last data byte received

is not acknowledged

P or S

0x88

Arbitration lost as master

and addressed as slave

A

0x68

A

Reception of the general call

address and one or more data

bytes

General Call

DATA

A

DATA

A

P or S

0x70

0x90

A

0xA0

Last data byte received is

not acknowledged

P or S

0x98

Arbitration lost as master and

addressed as slave by general call

A

0x78

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-wire Serial Bus. The

prescaler bits are zero or masked to zero

n

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19.8.4

Slave Transmitter Mode

In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see

Figure 19-17). All the status codes mentioned in this section assume that the prescaler bits are

zero or are masked to zero.

Figure 19-17. Data Transfer in Slave Transmitter Mode

Device 1

Device 2

MASTER

RECEIVER

Device 3

SLAVE

Device n

........

TRANSMITTER

V_CC

R1

R2

SDA

SCL

To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

The upper seven bits are the address to which the Two-wire Serial Interface will respond when

addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00),

otherwise it will ignore the general call address.

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

0

1

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgment of the device’s own slave address or the general call address. TWSTA and

TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After

its own slave address and the write bit have been received, the TWINT flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 19-6.

The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the

Master mode (see state 0xB0).

If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-

fer. State 0xC0 or state 0xC8 will be entered, depending on whether the master receiver

transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed slave

mode, and will ignore the master if it continues the transfer. Thus the master receiver receives

all “1” as serial data. State 0xC8 is entered if the master demands additional data bytes (by

transmitting ACK), even though the slave has transmitted the last byte (TWEA zero and expect-

ing NACK from the master).

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While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire

Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.

This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire

Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep

and the TWI will hold the SCL clock will low during the wake up and until the TWINT flag is

cleared (by writing it to one). Further data transmission will be carried out as normal, with the

AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the

SCL line may be held low for a long time, blocking other data transmissions.

Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte

present on the bus when waking up from these sleep modes.

Table 19-6. Status Codes for Slave Transmitter Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

To TWCR

Status of the Two-wire Serial Bus

and Two-wire Serial Interface Hard-

ware

Next Action Taken by TWI Hardware

To/from TWDR

STA

X

STO

0

TWINT TWEA

0xA8

0xB0

0xB8

0xC0

Own SLA+R has been received;

ACK has been returned

Load data byte or

Load data byte

1

0

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be received

X

0

1

0

Arbitration lost in SLA+R/W as mas- Load data byte or

ter; own SLA+R has been

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be received

received; ACK has been returned

Load data byte

X

0

1

0

Data byte in TWDR has been

transmitted; ACK has been

received

Load data byte or

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be received

Load data byte

X

0

1

0

Data byte in TWDR has been

transmitted; NOT ACK has been

received

No TWDR action or

Switched to the not addressed slave mode;

no recognition of own SLA or GCA

Switched to the not addressed slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

No TWDR action or

0

1

0

1

0

No TWDR action

1

0

1

Switched to the not addressed slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

0xC8

Last data byte in TWDR has been No TWDR action or

transmitted (TWEA = “0”); ACK has

0

1

0

1

Switched to the not addressed slave mode;

no recognition of own SLA or GCA

Switched to the not addressed slave mode;

own SLA will be recognized;

been received

No TWDR action or

GCA will be recognized if TWGCE = “1”

Switched to the not addressed slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

No TWDR action or

1

0

1

0

1

No TWDR action

Switched to the not addressed slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

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Figure 19-18. Formats and States in the Slave Transmitter Mode

Reception of the

own slave address

and one or

S

SLA

R

A

DATA

A

DATA

A

P or S

more data bytes

0xA8

A

0xB8

0xC0

Arbitration lost as master

and addressed as slave

0xB0

Last data byte transmitted.

Switched to not addressed

slave (TWEA = ’0’)

A

All 1’s

P or S

0xC8

Any number of data bytes

and their associated acknowledge bits

From master to slave

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-wire Serial Bus. The

prescaler bits are zero or masked to zero

From slave to master

n

19.8.5

Miscellaneous States

There are two status codes that do not correspond to a defined TWI state, see Table 19-7.

Status 0xF8 indicates that no relevant information is available because the TWINT flag is not

set. This occurs between other states, and when the TWI is not involved in a serial transfer.

Status 0x00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus

error occurs when a START or STOP condition occurs at an illegal position in the format frame.

Examples of such illegal positions are during the serial transfer of an address byte, a data byte,

or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the

TWSTO flag must set and TWINT must be cleared by writing a logic one to it. This causes the

TWI to enter the not addressed slave mode and to clear the TWSTO flag (no other bits in TWCR

are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.

Table 19-7. Miscellaneous States

Status Code

(TWSR)

Prescaler Bits

Hardware

are 0

Application Software Response

To TWCR

Status of the Two-wire Serial Bus

and Two-wire Serial Interface

Next Action Taken by TWI Hardware

To/from TWDR

STA

STO

TWINT

TWEA

X

0xF8

No relevant state information No TWDR action

available; TWINT = “0”

No TWCR action

Wait or proceed current transfer

0x00

Bus error due to an illegal START No TWDR action

or STOP condition

0

1

Only the internal hardware is affected, no STOP condition

is sent on the bus. In all cases, the bus is released and

TWSTO is cleared.

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19.8.6

Combining Several TWI Modes

In some cases, several TWI modes must be combined in order to complete the desired action.

Consider for example reading data from a serial EEPROM. Typically, such a transfer involves

the following steps:

1. The transfer must be initiated

2. The EEPROM must be instructed what location should be read

3. The reading must be performed

4. The transfer must be finished

Note that data is transmitted both from master to slave and vice versa. The master must instruct

the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data

must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must

be changed. The master must keep control of the bus during all these steps, and the steps

should be carried out as an atomical operation. If this principle is violated in a multimaster sys-

tem, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the

master will read the wrong data location. Such a change in transfer direction is accomplished by

transmitting a REPEATED START between the transmission of the address byte and reception

of the data. After a REPEATED START, the master keeps ownership of the bus. The following

figure shows the flow in this transfer.

Figure 19-19. Combining Several TWI Modes to Access a Serial EEPROM

Master Transmitter

Master Receiver

DATA

S

SLA+W

A

ADDRESS

A

Rs

SLA+R

A

P

S = START

Transmitted from master to slave

Rs = REPEATED START

Transmitted from slave to master

P = STOP

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19.9 Multi-master Systems and Arbitration

If multiple masters are connected to the same bus, transmissions may be initiated simulta-

neously by one or more of them. The TWI standard ensures that such situations are handled in

such a way that one of the masters will be allowed to proceed with the transfer, and that no data

will be lost in the process. An example of an arbitration situation is depicted below, where two

masters are trying to transmit data to a slave receiver.

Figure 19-20. An Arbitration Example

Device 1

MASTER

TRANSMITTER

Device 2

SLAVE

RECEIVER

Device 3

SLAVE

RECEIVER

Device n

........

V_CC

R1

R2

SDA

SCL

Several different scenarios may arise during arbitration, as described below:

• Two or more masters are performing identical communication with the same slave. In this

case, neither the slave nor any of the masters will know about the bus contention.

• Two or more masters are accessing the same slave with different data or direction bit. In this

case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters

trying to output a one on SDA while another master outputs a zero will lose the arbitration.

Losing masters will switch to not addressed slave mode or wait until the bus is free and

transmit a new START condition, depending on application software action.

• Two or more masters are accessing different slaves. In this case, arbitration will occur in the

SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose

the arbitration. Masters losing arbitration in SLA will switch to slave mode to check if they are

being addressed by the winning master. If addressed, they will switch to SR or ST mode,

depending on the value of the READ/WRITE bit. If they are not being addressed, they will

switch to not addressed slave mode or wait until the bus is free and transmit a new START

condition, depending on application software action.

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This is summarized in Figure 19-21. Possible status values are given in circles.

Figure 19-21. Possible Status Codes Caused by Arbitration

START

SLA

Data

STOP

Arbitration lost in SLA

Arbitration lost in Data

Own

No

0x38

TWI bus will be released and not addressed slave mode will be entered

A START condition will be transmitted when the bus becomes free

Address / General Call

received

Yes

Write

0x68 / 0x78

0xB0

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be returned

Direction

Read

Last data byte will be transmitted and NOT ACK should be received

Data byte will be transmitted and ACK should be received

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20. Controller Area Network - CAN

The Controller Area Network (CAN) protocol is a real-time, serial, broadcast protocol with a very

high level of security. The AT90CAN32/64 CAN controller is fully compatible with the CAN Spec-

ification 2.0 Part A and Part B. It delivers the features required to implement the kernel of the

CAN bus protocol according to the ISO/OSI Reference Model:

• The Data Link Layer

- the Logical Link Control (LLC) sublayer

- the Medium Access Control (MAC) sublayer

• The Physical Layer

- the Physical Signalling (PLS) sublayer

- not supported - the Physical Medium Attach (PMA)

- not supported - the Medium Dependent Interface (MDI)

The CAN controller is able to handle all types of frames (Data, Remote, Error and Overload) and

achieves a bitrate of 1 Mbit/s.

20.1 Features

• Full Can Controller

• Fully Compliant with CAN Standard rev 2.0 A and rev 2.0 B

• 15 MOb (Message Object) with their own:

– 11 bits of Identifier Tag (rev 2.0 A), 29 bits of Identifier Tag (rev 2.0 B)

– 11 bits of Identifier Mask (rev 2.0 A), 29 bits of Identifier Mask (rev 2.0 B)

– 8 Bytes Data Buffer (Static Allocation)

– Tx, Rx, Frame Buffer or Automatic Reply Configuration

– Time Stamping

• 1 Mbit/s Maximum Transfer Rate at 8 MHz

• TTC Timer

• Listening Mode (for Spying or Autobaud)

20.2 CAN Protocol

The CAN protocol is an international standard defined in the ISO 11898 for high speed and ISO

11519-2 for low speed.

20.2.1

Principles

CAN is based on a broadcast communication mechanism. This broadcast communication is

achieved by using a message oriented transmission protocol. These messages are identified by

using a message identifier. Such a message identifier has to be unique within the whole network

and it defines not only the content but also the priority of the message.

The priority at which a message is transmitted compared to another less urgent message is

specified by the identifier of each message. The priorities are laid down during system design in

the form of corresponding binary values and cannot be changed dynamically. The identifier with

the lowest binary number has the highest priority.

Bus access conflicts are resolved by bit-wise arbitration on the identifiers involved by each node

observing the bus level bit for bit. This happens in accordance with the "wired and" mechanism,

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by which the dominant state overwrites the recessive state. The competition for bus allocation is

lost by all nodes with recessive transmission and dominant observation. All the "losers" automat-

ically become receivers of the message with the highest priority and do not re-attempt

transmission until the bus is available again.

20.2.2

Message Formats

The CAN protocol supports two message frame formats, the only essential difference being in

the length of the identifier. The CAN standard frame, also known as CAN 2.0 A, supports a

length of 11 bits for the identifier, and the CAN extended frame, also known as CAN 2.0 B, sup-

ports a length of 29 bits for the identifier.

20.2.2.1

Can Standard Frame

Figure 20-1. CAN Standard Frames

Data Frame

Bus Idle

11-bit identifier

ID10..0

4-bit DLC

DLC4..0

CRC

del.

ACK

del.

Intermission

3 bits

Bus Idle

(Indefinite)

RTR IDE r0

15-bit CRC

ACK

7 bits

SOF

0 - 8 bytes

Interframe

Space

Arbitration

Field

Control

Field

Data

Field

CRC

Field

ACK

Field

End of

Frame

Interframe

Space

Remote Frame

Bus Idle

11-bit identifier

ID10..0

4-bit DLC

DLC4..0

CRC

del.

ACK

del.

Intermission

3 bits

Bus Idle

(Indefinite)

RTR IDE r0

15-bit CRC

ACK

7 bits

SOF

Interframe

Space

Arbitration

Field

Control

Field

CRC

Field

ACK

Field

End of

Frame

Interframe

Space

A message in the CAN standard frame format begins with the "Start Of Frame (SOF)", this is fol-

lowed by the "Arbitration field" which consist of the identifier and the "Remote Transmission

Request (RTR)" bit used to distinguish between the data frame and the data request frame

called remote frame. The following "Control field" contains the "IDentifier Extension (IDE)" bit

and the "Data Length Code (DLC)" used to indicate the number of following data bytes in the

"Data field". In a remote frame, the DLC contains the number of requested data bytes. The "Data

field" that follows can hold up to 8 data bytes. The frame integrity is guaranteed by the following

"Cyclic Redundant Check (CRC)" sum. The "ACKnowledge (ACK) field" compromises the ACK

slot and the ACK delimiter. The bit in the ACK slot is sent as a recessive bit and is overwritten as

a dominant bit by the receivers which have at this time received the data correctly. Correct mes-

sages are acknowledged by the receivers regardless of the result of the acceptance test. The

end of the message is indicated by "End Of Frame (EOF)". The "Intermission Frame Space

(IFS)" is the minimum number of bits separating consecutive messages. If there is no following

bus access by any node, the bus remains idle.

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20.2.2.2

CAN Extended Frame

Figure 20-2. CAN Extended Frames

Data Frame

Bus Idle

11-bit base identifier

IDT28..18

18-bit identifier extension

ID17..0

4-bit DLC

DLC4..0

CRC

del.

ACK

del.

Intermission Bus Idle

3 bits (Indefinite)

SRR IDE

RTR r1

r0

15-bit CRC

ACK

7 bits

SOF

0 - 8 bytes

Interframe

Space

Arbitration

Field

Control

Field

Data

Field

CRC

Field

ACK

Field

End of

Frame

Interframe

Space

Remote Frame

Bus Idle

11-bit base identifier

IDT28..18

18-bit identifier extension

ID17..0

4-bit DLC

DLC4..0

CRC

del.

ACK

del.

Intermission

3 bits

Bus Idle

(Indefinite)

SRR IDE

RTR r1

r0

15-bit CRC

ACK

7 bits

SOF

Interframe

Space

Arbitration

Field

Control

Field

CRC

Field

ACK

Field

End of

Frame

Interframe

Space

A message in the CAN extended frame format is likely the same as a message in CAN standard

frame format. The difference is the length of the identifier used. The identifier is made up of the

existing 11-bit identifier (base identifier) and an 18-bit extension (identifier extension). The dis-

tinction between CAN standard frame format and CAN extended frame format is made by using

the IDE bit which is transmitted as dominant in case of a frame in CAN standard frame format,

and transmitted as recessive in the other case.

20.2.2.3

Format Co-existence

As the two formats have to co-exist on one bus, it is laid down which message has higher priority

on the bus in the case of bus access collision with different formats and the same identifier /

base identifier: The message in CAN standard frame format always has priority over the mes-

sage in extended format.

There are three different types of CAN modules available:

– 2.0A - Considers 29 bit ID as an error

– 2.0B Passive - Ignores 29 bit ID messages

– 2.0B Active - Handles both 11 and 29 bit ID Messages

20.2.3

CAN Bit Timing

To ensure correct sampling up to the last bit, a CAN node needs to re-synchronize throughout

the entire frame. This is done at the beginning of each message with the falling edge SOF and

on each recessive to dominant edge.

20.2.3.1

Bit Construction

One CAN bit time is specified as four non-overlapping time segments. Each segment is con-

structed from an integer multiple of the Time Quantum. The Time Quantum or TQ is the smallest

discrete timing resolution used by a CAN node.

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Figure 20-3. CAN Bit Construction

CAN Frame

(producer)

Transmission Point

(producer)

Nominal CAN Bit Time

Time Quantum

(producer)

Segments

(producer)

SYNC_SEG

PROP_SEG

PHASE_SEG_1

PHASE_SEG_2

Sample Point

propagation

delay

Segments

(consumer)

SYNC_SEG

PROP_SEG

PHASE_SEG_1

PHASE_SEG_2

20.2.3.2

20.2.3.3

Synchronization Segment

The first segment is used to synchronize the various bus nodes.

On transmission, at the start of this segment, the current bit level is output. If there is a bit state

change between the previous bit and the current bit, then the bus state change is expected to

occur within this segment by the receiving nodes.

Propagation Time Segment

This segment is used to compensate for signal delays across the network.

This is necessary to compensate for signal propagation delays on the bus line and through the

transceivers of the bus nodes.

20.2.3.4

20.2.3.5

Phase Segment 1

Phase Segment 1 is used to compensate for edge phase errors.

This segment may be lengthened during re-synchronization.

Sample Point

The sample point is the point of time at which the bus level is read and interpreted as the value

of the respective bit. Its location is at the end of Phase Segment 1 (between the two Phase

Segments).

20.2.3.6

Phase Segment 2

This segment is also used to compensate for edge phase errors.

This segment may be shortened during re-synchronization, but the length has to be at least as

long as the Information Processing Time (IPT) and may not be more than the length of Phase

Segment 1.

20.2.3.7

Information Processing Time

It is the time required for the logic to determine the bit level of a sampled bit.

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The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN.

Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time,

PS2 minimum shall not be less than the IPT.

20.2.3.8

Bit Lengthening

As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2

may be shortened to compensate for oscillator tolerances. If, for example, the transmitter oscilla-

tor is slower than the receiver oscillator, the next falling edge used for resynchronization may be

delayed. So Phase Segment 1 is lengthened in order to adjust the sample point and the end of

the bit time.

20.2.3.9

Bit Shortening

If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling

edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in

order to adjust the sample point for bit N+1 and the end of the bit time

20.2.3.10

Synchronization Jump Width

The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resyn-

chronization Jump Width.

This segment may not be longer than Phase Segment 2.

20.2.3.11

Programming the Sample Point

Programming of the sample point allows "tuning" of the characteristics to suit the bus.

Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchronization Jump

Width can be programmed to its maximum. This maximum capacity to shorten or lengthen the

bit time decreases the sensitivity to node oscillator tolerances, so that lower cost oscillators such

as ceramic resonators may be used.

Late sampling allows more Time Quanta in the Propagation Time Segment which allows a

poorer bus topology and maximum bus length.

20.2.3.12

Synchronization

Hard synchronization occurs on the recessive-to-dominant transition of the start bit. The bit time

is restarted from that edge.

Re-synchronization occurs when a recessive-to-dominant edge doesn't occur within the Syn-

chronization Segment in a message.

20.2.4

Arbitration

The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple

Access with Arbitration on Message Priority”.

During transmission, arbitration on the CAN bus can be lost to a competing device with a higher

priority CAN Identifier. This arbitration concept avoids collisions of messages whose transmis-

sion was started by more than one node simultaneously and makes sure the most important

message is sent first without time loss.

The bus access conflict is resolved during the arbitration field mostly over the identifier value. If a

data frame and a remote frame with the same identifier are initiated at the same time, the data

frame prevails over the remote frame (c.f. RTR bit).

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Figure 20-4. Bus Arbitration

Arbitration lost

node A

TXCAN

Node A loses the bus

Node B wins the bus

node B

TXCAN

CAN bus

ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

SOF

RTR IDE - - - - - - - - -

20.2.5

Errors

The CAN protocol signals any errors immediately as they occur. Three error detection mecha-

nisms are implemented at the message level and two at the bit level:

20.2.5.1

Error at Message Level

• Cyclic Redundancy Check (CRC)

The CRC safeguards the information in the frame by adding redundant check bits at the

transmission end. At the receiver these bits are re-computed and tested against the received

bits. If they do not agree there has been a CRC error.

• Frame Check

This mechanism verifies the structure of the transmitted frame by checking the bit fields

against the fixed format and the frame size. Errors detected by frame checks are designated

"format errors".

• ACK Errors

As already mentioned frames received are acknowledged by all receivers through positive

acknowledgement. If no acknowledgement is received by the transmitter of the message an

ACK error is indicated.

20.2.5.2

Error at Bit Level

• Monitoring

The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each

node which transmits also observes the bus level and thus detects differences between the

bit sent and the bit received. This permits reliable detection of global errors and errors local to

the transmitter.

• Bit Stuffing

The coding of the individual bits is tested at bit level. The bit representation used by CAN is

"Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency in bit coding. The

synchronization edges are generated by means of bit stuffing.

20.2.5.3

Error Signalling

If one or more errors are discovered by at least one node using the above mechanisms, the cur-

rent transmission is aborted by sending an "error flag". This prevents other nodes accepting the

message and thus ensures the consistency of data throughout the network. After transmission

of an erroneous message that has been aborted, the sender automatically re-attempts

transmission.

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20.3 CAN Controller

The CAN controller implemented into AT90CAN32/64 offers V2.0B Active.

This full-CAN controller provides the whole hardware for convenient acceptance filtering and

message management. For each message to be transmitted or received this module contains

one so called message object in which all information regarding the message (e.g. identifier,

data bytes etc.) are stored.

During the initialization of the peripheral, the application defines which messages are to be sent

and which are to be received. Only if the CAN controller receives a message whose identifier

matches with one of the identifiers of the programmed (receive-) message objects the message

is stored and the application is informed by interrupt. Another advantage is that incoming remote

frames can be answered automatically by the full-CAN controller with the corresponding data

frame. In this way, the CPU load is strongly reduced compared to a basic-CAN solution.

Using full-CAN controller, high baudrates and high bus loads with many messages can be

handled.

Figure 20-5. CAN Controller Structure

Low priority

Control

Status

IDtag+IDmask

Time Stamp

Buffer MOb14

MOb14

MOb

Scanning

Control

Status

IDtag+IDmask

Time Stamp

Gen. Control

Gen. Status

Enable MOb

Interrupt

Buffer MOb2

Buffer MOb1

LCC

MAC

PLS

TxDcan

RxDcan

MOb2

Bit Timing

Line Error

CAN Timer

Control

Status

IDtag+IDmask

Time Stamp

CAN Channel

MOb1

Control

Status

IDtag+IDmask

Time Stamp

Buffer MOb0

MOb0

High priority

CAN Data Buffers

Message Objets

Mailbox

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20.4 CAN Channel

20.4.1

Configuration

The CAN channel can be in:

• Enabled mode

In this mode:

– the CAN channel (internal TXDCAN & RXDCAN) is enabled,

– the input clock is enabled.

• Standby mode

In standby mode:

– the transmitter constantly provides a recessive level (on internal TXDCAN) and the

receiver is disabled,

– input clock is enabled,

– the registers and pages remain accessible.

• Listening mode

This mode is transparent for the CAN channel:

– enables a hardware loop back, internal TXDCAN on internal RXDCAN

– provides a recessive level on TXDCAN pin

– does not disable RXDCAN

– freezes TEC and REC error counters

Figure 20-6. Listening Mode

internal

PD5

TXDcan

RXDcan

LISTEN

internal

1

0

PD6

RXDcan

20.4.2

Bit Timing

FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum.

So, the input clock for bit timing is the clock used into CAN channel FSM’s.

Field and segment abbreviations:

• BRP: Baud Rate Prescaler.

• TQ: Time Quantum (output of Baud Rate Prescaler).

• SYNS: SYNchronization Segment is 1 TQ long.

• PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long.

• PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.

• PHS2: PHase Segment 2 is programmable to be ≤ PHS1 and ≥ INFORMATION

PROCESSING TIME.

• INFORMATION PROCESSING TIME is 2 TQ.

• SJW: (Re) Synchronization Jump Width is programmable between 1 and min(4, PHS1).

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The total number of TQ in a bit time has to be programmed at least from 8 to 25.

Figure 20-7. Sample and Transmission Point

Bit Timing

PRS (3-bit length)

Sample

Point

PHS1 (3-bit length)

PHS2 (3-bit length)

SJW (2-bit length)

Fcan (Tscl)

Time Quantum

CLK

Prescaler BRP

IO

Transmission

Point

Figure 20-8. General Structure of a Bit Period

1

/

CLK

IO

CLK

IO

Bit Rate Prescaler

Tscl (TQ)

F

CAN

one nominal bit

Data

Tsyns(5)

Tprs

Tphs1 (1)

or

Tphs2 (2)

or

Notes: 1. Phase error < 0

2. Phase error > 0

Tphs1+Tsjw (3)

Tphs2+Tsjw (4)

3. Phase error > 0

4. Phase error < 0

5. Synchronization Segment: SYNS

Tbit

Tsyns=1xTscl (fixed)

Sample

Point

Transmission

Point

20.4.3

Baud Rate

The baud rate selection is made by T calculation:

bit

Tbit⁽¹⁾= Tsyns + Tprs + Tphs1 + Tphs2

1. Tsyns = 1 x Tscl = (BRP[5..0]+ 1)/clk_IO(= 1TQ)

2. Tprs = (1 to 8) x Tscl = (PRS[2..0]+ 1) x Tscl

3. Tphs1 = (1 to 8) x Tscl = (PHS1[2..0]+ 1) x Tscl

4. Tphs2 = (1 to 8) x Tscl = (PHS2[2..0]⁽²⁾+ 1) x Tscl

5. Tsjw = (1 to 4) x Tscl = (SJW[1..0]+ 1) x Tscl

Notes: 1. The total number of Tscl (Time Quanta) in a bit time must be between 8 to 25.

2. PHS2[2..0] 2 is programmable to be ≤ PHS1[2..0] and ≥ 1.

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20.4.4

20.4.5

Fault Confinement

(c.f. Section 20.7 ”Error Management” on page 246).

Overload Frame

An overload frame is sent by setting an overload request (OVRQ). After the next reception, the

CAN channel sends an overload frame in accordance with the CAN specification. A status or

flag is set (OVRF) as long as the overload frame is sent.

Figure 20-9. Overload Frame

Instructions

Setting OVRQ bit

Resetting OVRQ bit

OVRQ bit

OVFG bit

RXCDAN

TXCDAN

Ident "A"

Cmd

Message Data "A"

CRC

A

Interframe

Overload Frame

Ident "B"

20.5 Message Objects

The MOb is a CAN frame descriptor. It contains all information to handle a CAN frame. This

means that a MOb has been outlined to allow to describe a CAN message like an object. The set

of MObs is the front end part of the “mailbox” where the messages to send and/or to receive are

pre-defined as well as possible to decrease the work load of the software.

The MObs are numbered from 0 up to 14 (no MOb [15]). They are independent but priority is

given to the lower one in case of multi matching. The operating modes are:

– Disabled mode

– Transmit mode

– Receive mode

– Automatic reply

– Frame buffer receive mode

20.5.1

Operating Modes

Every MOb has its own fields to control the operating mode. There is no default mode after

RESET. Before enabling the CAN peripheral, each MOb must be configured (ex: disabled mode

- CONMOB=00).

Table 20-1. MOb Configuration

MOb Configuration

Reply Valid

RTR Tag

Operating Mode

0

x

0

1

x

0

1

0

Disabled

Tx Data Frame

0

1

Tx Remote Frame

Rx Data Frame

1

0

1

Rx Remote Frame

1

x

Rx Remote Frame then, Tx Data Frame (reply)

Frame Buffer Receive Mode

1

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20.5.1.1

20.5.1.2

Disabled

In this mode, the MOb is “free”.

Tx Data & Remote Frame

1. Several fields must be initialized before sending:

– Identifier tag (IDT)

– Identifier extension (IDE)

– Remote transmission request (RTRTAG)

– Data length code (DLC)

– Reserved bit(s) tag (RBnTAG)

– Data bytes of message (MSG)

2. The MOb is ready to send a data or a remote frame when the MOb configuration is set

(CONMOB).

3. Then, the CAN channel scans all the MObs in Tx configuration, finds the MOb having the

highest priority and tries to send it.

4. When the transmission is completed the TXOK flag is set (interrupt).

5. All the parameters and data are available in the MOb until a new initialization.

20.5.1.3

Rx Data & Remote Frame

1. Several fields must be initialized before receiving:

– Identifier tag (IDT)

– Identifier mask (IDMSK)

– Identifier extension (IDE)

– Identifier extension mask (IDEMSK)

– Remote transmission request (RTRTAG)

– Remote transmission request mask (RTRMSK)

– Data length code (DLC)

– Reserved bit(s) tag (RBnTAG)

2. The MOb is ready to receive a data or a remote frame when the MOb configuration is set

(CONMOB).

3. When a frame identifier is received on CAN network, the CAN channel scans all the MObs

in receive mode, tries to find the MOb having the highest priority which is matching.

4. On a hit, the IDT, the IDE and the DLC of the matched MOb are updated from the incoming

(frame) values.

5. Once the reception is completed, the data bytes of the received message are stored (not

for remote frame) in the data buffer of the matched MOb and the RXOK flag is set

(interrupt).

6. All the parameters and data are available in the MOb until a new initialization.

20.5.1.4

Automatic Reply

A reply (data frame) to a remote frame can be automatically sent after reception of the expected

remote frame.

1. Several fields must be initialized before receiving the remote frame:

– (c.f. Section 20.5.1.3 ”Rx Data & Remote Frame” on page 243)

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2. When a remote frame matches, automatically the RTRTAG and the reply valid bit (RPLV)

are reset. No flag (or interrupt) is set at this time. Since the CAN data buffer has not been

used by the incoming remote frame, the MOb is then ready to be in transmit mode without

any more setting. The IDT, the IDE, the other tags and the DLC of the received remote

frame are used for the reply.

3. When the transmission of the reply is completed the TXOK flag is set (interrupt).

4. All the parameters and data are available in the MOb until a new initialization.

20.5.1.5

Frame Buffer Receive Mode

This mode is useful to receive multi frames. The priority between MObs offers a management for

these incoming frames. One set MObs (including non-consecutive MObs) is created when the

MObs are set in this mode. Due to the mode setting, only one set is possible. A frame buffer

completed flag (or interrupt) - BXOK - will rise only when all the MObs of the set will have

received their dedicated CAN frame.

1. MObs in frame buffer receive mode need to be initialized as MObs in standard receive mode.

2. The MObs are ready to receive data (or a remote) frames when their respective configura-

tions are set (CONMOB).

3. When a frame identifier is received on CAN network, the CAN channel scans all the MObs

in receive mode, tries to find the MOb having the highest priority which is matching.

4. On a hit, the IDT, the IDE and the DLC of the matched MOb are updated from the incoming

(frame) values.

5. Once the reception is completed, the data bytes of the received message are stored (not for

remote frame) in the data buffer of the matched MOb and the RXOK flag is set (interrupt).

6. When the reception in the last MOb of the set is completed, the frame buffer completed

BXOK flag is set (interrupt). BXOK flag can be cleared only if all CONMOB fields of the set

have been re-written before.

7. All the parameters and data are available in the MObs until a new initialization.

20.5.2

Acceptance Filter

Upon a reception hit (i.e., a good comparison between the ID + RTR + RBn + IDE received and an

IDT+ RTRTAG + RBnTAG + IDE specified while taking the comparison mask into account) the IDT

+ RTRTAG + RBnTAG + IDE received are updated in the MOb (written over the registers).

Figure 20-10. Acceptance Filter Block Diagram

internal RxDcan

Rx Shift Register (internal)

ID &RB RTR IDE

13(32)

=

13(32)

Hit MOb[i]

Write

Enable

1

13(32)

ID &RB

RTRTAG

IDE

IDMSK

RTRMSK IDEMSK

CANIDM Registers (MOb[i])

CANIDT Registers & CANCDMOB (MOb[i])

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Note:

Examples:

To accept only ID = 0x317 in part A.

To accept ID from 0x310 up to 0x317 in part A.

- ID MSK = 111 1111 1111

- ID TAG = 011 0001 0111

- ID MSK = 111 1111 1000

- ID TAG = 011 0001 0xxx

b

20.5.3

MOb Page

Every MOb is mapped into a page to save place. The page number is the MOb number. This

page number is set in CANPAGE register. The number 15 is reserved for factory tests.

CANHPMOB register gives the MOb having the highest priority in CANSIT registers. It is format-

ted to provide a direct entry for CANPAGE register. Because CANHPMOB codes CANSIT

registers, it will be only updated if the corresponding enable bits (ENRX, ENTX, ENERR) are

enabled (c.f. Figure 20-14).

20.5.4

CAN Data Buffers

To preserve register allocation, the CAN data buffer is seen such as a FIFO (with address

pointer accessible) into a MOb selection.This also allows to reduce the risks of un-controlled

accesses.

There is one FIFO per MOb. This FIFO is accessed into a MOb page thanks to the CAN mes-

sage register.

The data index (INDX) is the address pointer to the required data byte. The data byte can be

read or write. The data index is automatically incremented after every access if the AINC* bit is

reset. A roll-over is implemented, after data index=7 it is data index=0.

The first byte of a CAN frame is stored at the data index=0, the second one at the data index=1,

...

20.6 CAN Timer

A programmable 16-bit timer is used for message stamping and time trigger communication

(TTC).

Figure 20-11. CAN Timer Block Diagram

clk

CANTCON

ENFG

8

IO

clk

CANTIM

TTC SYNCTTC

overrun

OVRTIM

CANTIM

TXOK[i]

RXOK[i]

"EOF "

"SOF "

CANSTM[i]

CANTTC

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20.6.1

Prescaler

An 8-bit prescaler is initialized by CANTCON register. It receives the clk_IOfrequency divided by

8. It provides clk_CANTIMfrequency to the CAN Timer if the CAN controller is enabled.

Tclk_CANTIM= Tclk_IOx 8 x (CANTCON [7:0] + 1)

20.6.2

20.6.3

16-bit Timer

This timer starts counting from 0x0000 when the CAN controller is enabled (ENFG bit). When

the timer rolls over from 0xFFFF to 0x0000, an interrupt is generated (OVRTIM).

Time Triggering

Two synchronization modes are implemented for TTC (TTC bit):

– synchronization on Start of Frame (SYNCTTC=0),

– synchronization on End of Frame (SYNCTTC=1).

In TTC mode, a frame is sent once, even if an error occurs.

20.6.4

Stamping Message

The capture of the timer value is done in the MOb which receives or sends the frame. All man-

aged MOb are stamped, the stamping of a received (sent) frame occurs on RxOk (TXOK).

20.7 Error Management

20.7.1

Fault Confinement

The CAN channel may be in one of the three following states:

• Error active (default):

The CAN channel takes part in bus communication and can send an active error frame when

the CAN macro detects an error.

• Error passive:

The CAN channel cannot send an active error frame. It takes part in bus communication, but

when an error is detected, a passive error frame is sent. Also, after a transmission, an error

passive unit will wait before initiating further transmission.

• Bus off:

The CAN channel is not allowed to have any influence on the bus.

For fault confinement, a transmit error counter (TEC) and a receive error counter (REC) are

implemented. BOFF and ERRP bits give the information of the state of the CAN channel. Setting

BOFF to one may generate an interrupt.

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Figure 20-12. Line Error Mode

Reset

ERRP = 0

BOFF = 0

Error

Active

TEC > 127 or

REC > 127

128 occurrences

of 11 consecutive

recessive bit

TEC < 127 and

REC < 127

ERRP = 0

BOFF = 1

ERRP = 1

BOFF = 0

Bus

Off

Error

Passive

TEC > 255

BOFFIT interrupt

Note:

More than one REC/TEC change may apply during a given message transfer.

20.7.2

Error Types

• BERR: Bit error. The bit value which is monitored is different from the bit value sent.

Note:

Exceptions:

- Recessive bit sent monitored as dominant bit during the arbitration field and the acknowl-

edge slot.

- Detecting a dominant bit during the sending of an error frame.

• SERR: Stuff error. Detection of more than five consecutive bit with the same polarity.

• CERR: CRC error (Rx only). The receiver performs a CRC check on every destuffed received

message from the start of frame up to the data field. If this checking does not match with the

destuffed CRC field, an CRC error is set.

• FERR: Form error. The form error results from one (or more) violations of the fixed form of

the following bit fields:

– CRC delimiter

– acknowledgement delimiter

– end-of-frame

– error delimiter

– overload delimiter

• AERR: Acknowledgment error (Tx only). No detection of the dominant bit in the acknowledge

slot.

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7538B–CAN–05/06

Figure 20-13. Error Detection Procedures in a Data Frame

Arbitration

Bit error

Stuff error

Form error

ACK error

Tx

Rx

CRC

ACK

EOF

SOF

Identifier

RTR Command

Message Data

CRC

inter.

del.

Bit error

Stuff error

Form error

CRC error

20.7.3

Error Setting

The CAN channel can detect some errors on the CAN network.

• In transmission:

The error is set at MOb level.

• In reception:

- The identified has matched:

The error is set at MOb level.

- The identified has not or not yet matched:

The error is set at general level.

After detecting an error, the CAN channel sends an error frame on network. If the CAN channel

detects an error frame on network, it sends its own error frame.

20.8 Interrupts

20.8.1

Interrupt organization

The different interrupts are:

• Interrupt on receive completed OK,

• Interrupt on transmit completed OK,

• Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error),

• Interrupt on frame buffer full,

• Interrupt on “Bus Off” setting,

• Interrupt on overrun of CAN timer.

The general interrupt enable is provided by ENIT bit and the specific interrupt enable for CAN

timer overrun is provided by ENORVT bit.

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Figure 20-14. CAN Controller Interrupt Structure

CANGIE.4

CANGIE.5

CANGIE.3

ENTX

ENRX

ENERR

CANSIT 1/2

SIT[i]

CANSTMOB.6

CANSTMOB.5

CANSTMOB.4

CANSTMOB.3

CANSTMOB.2

CANSTMOB.1

CANSTMOB.0

TXOK[i]

RXOK[i]

BERR[i]

SERR[i]

CERR[i]

FERR[i]

AERR[i]

CANIE 1/2

IEMOB[i]

i=0

CANGIT.7

CANIT

i=14

CANGIE.7

CANGIE.2

CANGIE.1

ENERG

CANGIE.6

ENIT

ENBX

ENBOFF

CANGIT.4

BXOK

CAN IT

CANGIT.3

CANGIT.2

CANGIT.1

CANGIT.0

SERG

CERG

FERG

AERG

CANGIE.0

CANGIT.6

CANGIT.5

BOFFI

ENOVRT

OVR IT

OVRTIM

20.8.2

Interrupt Behavior

When an interrupt occurs, the corresponding bit is set in the CANSITn or CANGIT registers.

To acknowledge a MOb interrupt, the corresponding bits of CANSTMOB register (RXOK,

TXOK,...) must be cleared by the software application. This operation needs a read-modify-write

software routine.

To acknowledge a general interrupt, the corresponding bits of CANGIT register (BXOK, BOF-

FIT,...) must be cleared by the software application. This operation is made writing a logical one

in these interrupt flags (writing a logical zero doesn’t change the interrupt flag value).

OVRTIM interrupt flag is reset as the other interrupt sources of CANGIT register and is also

reset entering in its dedicated interrupt handler.

When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also

be raised. Consequently, two consecutive interrupts can occur, both due to the same error.

When a MOb error occurs and is set in its own CANSTMOB register, no general error is set in

CANGIT register.

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7538B–CAN–05/06

20.9 CAN Register Description

Figure 20-15. Registers Organization

AVR Registers

Registers in Pages

General Control

General Status

General Interrupt

Bit Timing 1

Bit Timing 2

Bit Timing 3

Enable MOb 2

Enable MOb 1

Enable Interrupt

Enable Interrupt MOb 2

Enable Interrupt MOb 1

Status Interrupt MOb 2

Status Interrupt MOb 1

CAN Timer Control

CAN Timer Low

CAN Timer High

CAN TTC Low

CAN TTC High

TEC Counter

REC Counter

Hightest Priority MOb

Page MOb

MOb14 - MOb Status

MOb Number

Data Index

MOb14 - MOb Ctrl & DLC

MOb14 - ID Tag 4

MOb14 - ID Tag 3

MOb14 - ID Tag 2

MOb14 - ID Tag 1

Page MOb

MOb Status

MOb0 - MOb Status

MOb Control & DLC

MOb0 - MOb Ctrl & DLC

MOb14 - ID Mask 4

MOb14 - ID Mask 3

MOb14 - ID Mask 2

MOb14 - ID Mask 1

ID Tag 4

ID Tag 3

ID Tag 2

ID Tag 1

MOb0 - ID Tag 4

MOb0 - ID Tag 3

MOb0 - ID Tag 2

MOb0 - ID Tag 1

MOb14 - Time Stamp Low

MOb14 - Time Stamp High

ID Mask 4

ID Mask 3

ID Mask 2

ID Mask 1

MOb0 - ID Mask 4

MOb0 - ID Mask 3

MOb0 - ID Mask 2

MOb0 - ID Mask 1

MOb14 - Mess. Data - byte 0

Time Stamp Low

Time Stamp High

MOb0 - Time Stamp Low

MOb0 - Time Stamp High

Message Data

MOb0 - Mess. Data - byte 0

8 bytes

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20.10 General CAN Registers

20.10.1 CAN General Control Register - CANGCON

Bit

7

6

5

4

3

2

1

0

ABRQ

R/W

0

OVRQ

R/W

0

TTC

R/W

0

SYNTTC LISTEN

TEST

R/W

0

ENA/STB SWRES CANGCON

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – ABRQ: Abort Request

This is not an auto resettable bit.

– 0 - no request.

– 1 - abort request: a reset of CANEN1 and CANEN2 registers is done. The pending

communications are immediately disabled and the on-going one will be normally

terminated, setting the appropriate status flags.

Note that CONCDMOB register remain unchanged.

• Bit 6 – OVRQ: Overload Frame Request

This is not an auto resettable bit.

– 0 - no request.

– 1 - overload frame request: send an overload frame after the next received frame.

The overload frame can be traced observing OVFG in CANGSTA register (c.f. Figure 20-9 on

page 242).

• Bit 5 – TTC: Time Trigger Communication

– 0 - no TTC.

– 1- TTC mode.

• Bit 4 – SYNTTC: Synchronization of TTC

This bit is only used in TTC mode.

– 0 - the TTC timer is caught on SOF.

– 1 - the TTC timer is caught on the last bit of the EOF.

• Bit 3 – LISTEN: Listening Mode

– 0 - no listening mode.

– 1 - listening mode.

• Bit 2 – TEST: Test Mode

– 0 - no test mode

– 1 - test mode: intend for factory testing and not for customer use.

Note:

CAN may malfunction if this bit is set.

• Bit 1 – ENA/STB: Enable / Standby Mode

Because this bit is a command and is not immediately effective, the ENFG bit in CANGSTA reg-

ister gives the true state of the chosen mode.

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7538B–CAN–05/06

– 0 - standby mode: the on-going communication is normally terminated and the CAN

channel is frozen (the CONMOB bits of every MOb do not change). The transmitter

constantly provides a recessive level. In this mode, the receiver is not enabled but all the

registers and mailbox remain accessible from CPU.

– 1 - enable mode: the CAN channel enters in enable mode once 11 recessive bits has

been read.

• Bit 0 – SWRES: Software Reset Request

This auto resettable bit only resets the CAN controller.

– 0 - no reset

– 1 - reset: this reset is “ORed” with the hardware reset.

20.10.2 CAN General Status Register - CANGSTA

Bit

7

6

5

-

4

3

2

ENFG

R

1

BOFF

R

0

ERRP

R

-

OVFG

TXBSY

RXBSY

CANGSTA

Read/Write

Initial Value

-

R

0

-

R

0

R

0

-

0

• Bit 7 – Reserved Bit

This bit is reserved for future use.

• Bit 6 – OVFG: Overload Frame Flag

This flag does not generate an interrupt.

– 0 - no overload frame.

– 1 - overload frame: set by hardware as long as the produced overload frame is sent.

• Bit 5 – Reserved Bit

This bit is reserved for future use.

• Bit 4 – TXBSY: Transmitter Busy

This flag does not generate an interrupt.

– 0 - transmitter not busy.

– 1 - transmitter busy: set by hardware as long as a frame (data, remote, overload or

error frame) or an ACK field is sent. Also set when an inter frame space is sent.

• Bit 3 – RXBSY: Receiver Busy

This flag does not generate an interrupt.

– 0 - receiver not busy

– 1 - receiver busy: set by hardware as long as a frame is received or monitored.

• Bit 2 – ENFG: Enable Flag

This flag does not generate an interrupt.

– 0 - CAN controller disable: because an enable/disable command is not immediately

effective, this status gives the true state of the chosen mode.

– 1 - CAN controller enable.

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• Bit 1 – BOFF: Bus Off Mode

BOFF gives the information of the state of the CAN channel. Only entering in bus off mode gen-

erates the BOFFIT interrupt.

– 0 - no bus off mode.

– 1 - bus off mode.

• Bit 0 – ERRP: Error Passive Mode

ERRP gives the information of the state of the CAN channel. This flag does not generate an

interrupt.

– 0 - no error passive mode.

– 1 - error passive mode.

20.10.3 CAN General Interrupt Register - CANGIT

Bit

7

6

5

4

BXOK

R/W

0

3

SERG

R/W

0

2

CERG

R/W

0

1

FERG

R/W

0

AERG

R/W

0

CANIT

BOFFIT OVRTIM

CANGIT

Read/Write

Initial Value

R

0

R/W

0

R/W

0

• Bit 7 – CANIT: General Interrupt Flag

This is a read only bit.

– 0 - no interrupt.

– 1 - CAN interrupt: image of all the CAN controller interrupts except for OVRTIM

interrupt. This bit can be used for polling method.

• Bit 6 – BOFFIT: Bus Off Interrupt Flag

Writing a logical one resets this interrupt flag. BOFFIT flag is only set when the CAN enters in

bus off mode (coming from error passive mode).

– 0 - no interrupt.

– 1 - bus off interrupt when the CAN enters in bus off mode.

• Bit 5 – OVRTIM: Overrun CAN Timer

Writing a logical one resets this interrupt flag. Entering in CAN timer overrun interrupt handler

also reset this interrupt flag

– 0 - no interrupt.

– 1 - CAN timer overrun interrupt: set when the CAN timer switches from 0xFFFF to 0.

• Bit 4 – BXOK: Frame Buffer Receive Interrupt

Writing a logical one resets this interrupt flag. BXOK flag can be cleared only if all CONMOB

fields of the MOb’s of the buffer have been re-written before.

– 0 - no interrupt.

– 1 - burst receive interrupt: set when the frame buffer receive is completed.

• Bit 3 – SERG: Stuff Error General

Writing a logical one resets this interrupt flag.

– 0 - no interrupt.

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7538B–CAN–05/06

– 1 - stuff error interrupt: detection of more than 5 consecutive bits with the same

polarity.

• Bit 2 – CERG: CRC Error General

Writing a logical one resets this interrupt flag.

– 0 - no interrupt.

– 1 - CRC error interrupt: the CRC check on destuffed message does not fit with the

CRC field.

• Bit 1 – FERG: Form Error General

Writing a logical one resets this interrupt flag.

– 0 - no interrupt.

– 1 - form error interrupt: one or more violations of the fixed form in the CRC delimiter,

acknowledgment delimiter or EOF.

• Bit 0 – AERG: Acknowledgment Error General

Writing a logical one resets this interrupt flag.

– 0 - no interrupt.

– 1 - acknowledgment error interrupt: no detection of the dominant bit in acknowledge

slot.

20.10.4 CAN General Interrupt Enable Register - CANGIE

Bit

7

6

5

4

ENTX

R/W

0

3

ENERR

R/W

0

2

ENBX

R/W

0

1

0

ENIT

ENBOFF

ENRX

ENERG ENOVRT

CANGIE

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – ENIT: Enable all Interrupts (Except for CAN Timer Overrun Interrupt)

– 0 - interrupt disabled.

– 1- CANIT interrupt enabled.

• Bit 6 – ENBOFF: Enable Bus Off Interrupt

– 0 - interrupt disabled.

– 1- bus off interrupt enabled.

• Bit 5 – ENRX: Enable Receive Interrupt

– 0 - interrupt disabled.

– 1- receive interrupt enabled.

• Bit 4 – ENTX: Enable Transmit Interrupt

– 0 - interrupt disabled.

– 1- transmit interrupt enabled.

• Bit 3 – ENERR: Enable MOb Errors Interrupt

– 0 - interrupt disabled.

– 1- MOb errors interrupt enabled.

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• Bit 2 – ENBX: Enable Frame Buffer Interrupt

– 0 - interrupt disabled.

– 1- frame buffer interrupt enabled.

• Bit 1 – ENERG: Enable General Errors Interrupt

– 0 - interrupt disabled.

– 1- general errors interrupt enabled.

• Bit 0 – ENOVRT: Enable CAN Timer Overrun Interrupt

– 0 - interrupt disabled.

– 1- CAN timer interrupt overrun enabled.

20.10.5 CAN Enable MOb Registers -

CANEN2 and CANEN1

Bit

7

6

5

4

3

2

1

0

ENMOB7 ENMOB6 ENMOB5 ENMOB4 ENMOB3 ENMOB2 ENMOB1 ENMOB0 CANEN2

-

15

R

0

ENMOB14 ENMOB13 ENMOB12 ENMOB11 ENMOB10 ENMOB9 ENMOB8 CANEN1

Bit

14

R

0

13

R

0

12

R

0

11

R

0

10

R

0

9

R

0

8

R

0

Read/Write

Initial Value

Read/Write

Initial Value

-

R

0

R

0

R

0

R

0

R

0

R

0

R

0

-

• Bits 14:0 - ENMOB14:0: Enable MOb

This bit provides the availability of the MOb.

It is set to one when the MOb is enabled (i.e. CONMOB1:0 of CANCDMOB register).

Once TXOK or RXOK is set to one (TXOK for automatic reply), the corresponding ENMOB is

reset. ENMOB is also set to zero configuring the MOb in disabled mode, applying abortion or

standby mode.

– 0 - message object disabled: MOb available for a new transmission or reception.

– 1 - message object enabled: MOb in use.

• Bit 15 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when CANIE1 is written.

20.10.6 CAN Enable Interrupt MOb Registers -

CANIE2 and CANIE1

Bit

7

6

5

4

3

2

1

0

IEMOB7 IEMOB6 IEMOB5 IEMOB4 IEMOB3 IEMOB2 IEMOB1 IEMOB0

CANIE2

CANIE1

-

15

R/W

0

IEMOB14 IEMOB13 IEMOB12 IEMOB11 IEMOB10 IEMOB9 IEMOB8

Bit

14

R/W

0

13

R/W

0

12

R/W

0

11

R/W

0

10

R/W

0

9

R/W

0

8

R/W

0

Read/Write

Initial Value

Read/Write

Initial Value

-

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

-

255

7538B–CAN–05/06

• Bits 14:0 - IEMOB14:0: Interrupt Enable by MOb

– 0 - interrupt disabled.

– 1 - MOb interrupt enabled

Note:

Example: CANIE2 = 0000 1100_b: enable of interrupts on MOb 2 & 3.

• Bit 15 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when CANIE1 is written.

20.10.7 CAN Status Interrupt MOb Registers - CANSIT2 and CANSIT1

Bit

7

6

5

4

3

2

SIT2

SIT10

10

1

SIT1

SIT9

9

0

SIT0

SIT8

8

SIT7

SIT6

SIT5

SIT4

SIT3

CANSIT2

CANSIT1

-

15

R

0

SIT14

SIT13

SIT12

SIT11

Bit

14

R

0

13

R

0

12

R

0

11

R

0

Read/Write

Initial Value

Read/Write

Initial Value

R

0

-

R

0

R

0

R

0

R

0

R

-

0

• Bits 14:0 - SIT14:0: Status of Interrupt by MOb

– 0 - no interrupt.

– 1- MOb interrupt.

Note:

Example: CANSIT2 = 0010 0001_b: MOb 0 & 5 interrupts.

• Bit 15 – Reserved Bit

This bit is reserved for future use.

20.10.8 CAN Bit Timing Register 1 - CANBT1

Bit

7

6

BRP5

R/W

0

5

BRP4

R/W

0

4

BRP3

R/W

0

3

BRP2

R/W

0

2

BRP1

R/W

0

1

BRP0

R/W

0

-

CANBT1

Read/Write

Initial Value

-

• Bit 7– Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when CANBT1 is written.

• Bit 6:1 – BRP5:0: Baud Rate Prescaler

The period of the CAN controller system clock Tscl is programmable and determines the individ-

ual bit timing.

BRP[5:0] + 1

Tscl =

clk_IOfrequency

• Bit 0 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when CANBT1 is written.

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20.10.9 CAN Bit Timing Register 2 - CANBT2

Bit

7

-

6

SJW1

R/W

0

5

SJW0

R/W

0

4

-

3

PRS2

R/W

0

2

PRS1

R/W

0

1

0

PRS0

R/W

0

-

CANBT2

Read/Write

Initial Value

-

• Bit 7– Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when CANBT2 is written.

• Bit 6:5 – SJW1:0: Re-Synchronization Jump Width

To compensate for phase shifts between clock oscillators of different bus controllers, the control-

ler must re-synchronize on any relevant signal edge of the current transmission.

The synchronization jump width defines the maximum number of clock cycles. A bit period may

be shortened or lengthened by a re-synchronization.

Tsjw = Tscl x (SJW [1:0] +1)

• Bit 4 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when CANBT2 is written.

• Bit 3:1 – PRS2:0: Propagation Time Segment

This part of the bit time is used to compensate for the physical delay times within the network. It

is twice the sum of the signal propagation time on the bus line, the input comparator delay and

the output driver delay.

Tprs = Tscl x (PRS [2:0] + 1)

• Bit 0 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when CANBT2 is written.

20.10.10 CAN Bit Timing Register 3 - CANBT3

Bit

7

6

PHS22

R/W

0

5

PHS21

R/W

0

4

PHS20

R/W

0

3

PHS12

R/W

0

2

PHS11

R/W

0

1

PHS10

R/W

0

SMP

R/W

0

-

CANBT3

Read/Write

Initial Value

• Bit 7– Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when CANBT3 is written.

• Bit 6:4 – PHS22:0: Phase Segment 2

This phase is used to compensate for phase edge errors. This segment may be shortened by

the re-synchronization jump width. PHS2[2..0] shall be ≥1 and ≤PHS1[2..0] (c.f. Section 20.2.3

”CAN Bit Timing” on page 235 and Section 20.4.3 ”Baud Rate” on page 241).

Tphs2 = Tscl x (PHS2 [2:0] + 1)

257

7538B–CAN–05/06

• Bit 3:1 – PHS12:0: Phase Segment 1

This phase is used to compensate for phase edge errors. This segment may be lengthened by

the re-synchronization jump width.

Tphs1 = Tscl x (PHS1 [2:0] + 1)

• Bit 0 – SMP: Sample Point(s)

– 0 - once, at the sample point.

– 1 - three times, the threefold sampling of the bus is the sample point and twice over

a distance of a 1/2 period of the Tscl. The result corresponds to the majority decision

of the three values.

20.10.11 CAN Timer Control Register - CANTCON

Bit

7

6

5

4

3

2

1

0

TPRSC7 TPRSC6 TPRSC5 TPRSC4 TPRSC3 TPRSC2 TRPSC1 TPRSC0 CANTCON

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7:0 – TPRSC7:0: CAN Timer Prescaler

Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer

if the CAN controller is enabled.

Tclk_CANTIM= Tclk_IOx 8 x (CANTCON [7:0] + 1)

20.10.12 CAN Timer Registers - CANTIML and CANTIMH

Bit

7

6

5

4

3

2

1

0

CANTIM7 CANTIM6 CANTIM5 CANTIM4 CANTIM3 CANTIM2 CANTIM1 CANTIM0 CANTIML

CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8 CANTIMH

Bit

15

R

14

R

13

R

12

R

11

R

10

R

9

R

0

8

R

0

Read/Write

Initial Value

0

• Bits 15:0 - CANTIM15:0: CAN Timer Count

CAN timer counter range 0 to 65,535.

20.10.13 CAN TTC Timer Registers - CANTTCL and CANTTCH

Bit

7

6

5

4

3

2

1

0

TIMTTC7 TIMTTC6 TIMTTC5 TIMTTC4 TIMTTC3 TIMTTC2 TIMTTC1 TIMTTC0 CANTTCL

TIMTTC15 TIMTTC14 TIMTTC13 TIMTTC12 TIMTTC11 TIMTTC10 TIMTTC9 TIMTTC8 CANTTCH

Bit

15

R

14

R

13

R

12

R

11

R

10

R

9

R

0

8

R

0

Read/Write

Initial Value

0

• Bits 15:0 - TIMTTC15:0: TTC Timer Count

CAN TTC timer counter range 0 to 65,535.

258

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

20.10.14 CAN Transmit Error Counter Register - CANTEC

Bit

7

TEC7

R

6

TEC6

R

5

TEC5

R

4

TEC4

R

3

TEC3

R

2

TEC2

R

1

0

TEC1

TEC0

CANTEC

Read/Write

Initial Value

R

0

R

0

• Bit 7:0 – TEC7:0: Transmit Error Count

CAN transmit error counter range 0 to 255.

20.10.15 CAN Receive Error Counter Register - CANREC

Bit

7

REC7

R

6

REC6

R

5

REC5

R

4

REC4

R

3

REC3

R

2

REC2

R

1

REC1

R

0

REC0

R

CANREC

Read/Write

Initial Value

0

• Bit 7:0 – REC7:0: Receive Error Count

CAN receive error counter range 0 to 255.

20.10.16 CAN Highest Priority MOb Register - CANHPMOB

Bit

7

6

5

4

3

CGP3

R/W

0

2

CGP2

R/W

0

1

CGP1

R/W

0

HPMOB3 HPMOB2 HPMOB1 HPMOB0

CGP0

CANHPMOB

Read/Write

Initial Value

R

1

R

1

R

1

R

1

R/W

0

• Bit 7:4 – HPMOB3:0: Highest Priority MOb Number

MOb having the highest priority in CANSIT registers.

If CANSIT = 0 (no MOb), the return value is 0xF.

• Bit 3:0 – CGP3:0: CAN General Purpose Bits

These bits can be pre-programmed to match with the wanted configuration of the CANPAGE

register (i.e., AINC and INDX2:0 setting).

20.10.17 CAN Page MOb Register - CANPAGE

Bit

7

6

5

4

3

2

1

0

MOBNB3 MOBNB2 MOBNB1 MOBNB0

AINC

R/W

0

INDX2

R/W

0

INDX1

R/W

0

INDX0

R/W

0

CANPAGE

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7:4 – MOBNB3:0: MOb Number

Selection of the MOb number, the available numbers are from 0 to 14.

• Bit 3 – AINC: Auto Increment of the FIFO CAN Data Buffer Index (Active Low)

– 0 - auto increment of the index (default value).

– 1- no auto increment of the index.

• Bit 2:0 – INDX2:0: FIFO CAN Data Buffer Index

Byte location of the CAN data byte into the FIFO for the defined MOb.

259

7538B–CAN–05/06

20.11 MOb Registers

The MOb registers has no initial (default) value after RESET.

20.11.1 CAN MOb Status Register - CANSTMOB

Bit

7

DLCW

R/W

-

6

TXOK

R/W

-

5

RXOK

R/W

-

4

BERR

R/W

-

3

SERR

R/W

-

2

CERR

R/W

-

1

FERR

R/W

-

0

AERR

R/W

-

CANSTMOB

Read/Write

Initial Value

• Bit 7 – DLCW: Data Length Code Warning

The incoming message does not have the DLC expected. Whatever the frame type, the DLC

field of the CANCDMOB register is updated by the received DLC.

• Bit 6 – TXOK: Transmit OK

This flag can generate an interrupt. It must be cleared using a read-modify-write software routine

on the whole CANSTMOB register.

The communication enabled by transmission is completed. TxOK rises at the end of EOF field.

When the controller is ready to send a frame, if two or more message objects are enabled as

producers, the lower MOb index (0 to 14) is supplied first.

• Bit 5 – RXOK: Receive OK

This flag can generate an interrupt. It must be cleared using a read-modify-write software routine

on the whole CANSTMOB register.

The communication enabled by reception is completed. RxOK rises at the end of the 6^thbit of

EOF field. In case of two or more message object reception hits, the lower MOb index (0 to 14)

is updated first.

• Bit 4 – BERR: Bit Error (Only in Transmission)

This flag can generate an interrupt. It must be cleared using a read-modify-write software routine

on the whole CANSTMOB register.

The bit value monitored is different from the bit value sent.

Exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the

acknowledge slot detecting a dominant bit during the sending of an error frame.

• Bit 3 – SERR: Stuff Error

This flag can generate an interrupt. It must be cleared using a read-modify-write software routine

on the whole CANSTMOB register.

Detection of more than five consecutive bits with the same polarity. This flag can generate an

interrupt.

• Bit 2 – CERR: CRC Error

This flag can generate an interrupt. It must be cleared using a read-modify-write software routine

on the whole CANSTMOB register.

The receiver performs a CRC check on every de-stuffed received message from the start of

frame up to the data field. If this checking does not match with the de-stuffed CRC field, a CRC

error is set.

260

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

• Bit 1 – FERR: Form Error

This flag can generate an interrupt. It must be cleared using a read-modify-write software routine

on the whole CANSTMOB register.

The form error results from one or more violations of the fixed form in the following bit fields:

• CRC delimiter.

• Acknowledgment delimiter.

• EOF

• Bit 0 – AERR: Acknowledgment Error

This flag can generate an interrupt. It must be cleared using a read-modify-write software routine

on the whole CANSTMOB register.

No detection of the dominant bit in the acknowledge slot.

20.11.2 CAN MOb Control and DLC Register - CANCDMOB

Bit

7

6

5

4

3

2

1

0

CONMOB1 CONMOB0

RPLV

IDE

R/W

DLC3

R/W

DLC2

R/W

DLC1

R/W

DLC0

R/W

CANCDMOB

Read/Write

Initial Value

R/W

-

R/W

-

R/W

-

• Bit 7:6 – CONMOB1:0: Configuration of Message Object

These bits set the communication to be performed (no initial value after RESET).

– 00 - disable.

– 01 - enable transmission.

– 10 - enable reception.

– 11 - enable frame buffer reception

These bits are not cleared once the communication is performed. The user must re-write the

configuration to enable a new communication.

• This operation is necessary to be able to reset the BXOK flag.

• This operation also set the corresponding bit in the CANEN registers.

• Bit 5 – RPLV: Reply Valid

Used in the automatic reply mode after receiving a remote frame.

– 0 - reply not ready.

– 1 - reply ready and valid.

• Bit 4 – IDE: Identifier Extension

IDE bit of the remote or data frame to send.

This bit is updated with the corresponding value of the remote or data frame received.

– 0 - CAN standard rev 2.0 A (identifiers length = 11 bits).

– 1 - CAN standard rev 2.0 B (identifiers length = 29 bits).

• Bit 3:0 – DLC3:0: Data Length Code

Number of Bytes in the data field of the message.

261

7538B–CAN–05/06

DLC field of the remote or data frame to send. The range of DLC is from 0 up to 8. If DLC field >8

then effective DLC=8.

This field is updated with the corresponding value of the remote or data frame received. If the

expected DLC differs from the incoming DLC, a DLC warning appears in the CANSTMOB

register.

20.11.3 CAN Identifier Tag Registers -

CANIDT1, CANIDT2, CANIDT3, and CANIDT4

V2.0 part A

Bit

15/7

14/6

13/5

12/4

11/3

10/2

9/1

8/0

-

RTRTAG

-

RB0TAG CANIDT4

-

CANIDT3

CANIDT2

CANIDT1

IDT

2

IDT

1

9

IDT

0

8

IDT10

31/23

R/W

-

IDT

7

IDT

6

IDT5

IDT

25/17

R/W

-

4

IDT3

Bit

30/22

R/W

-

29/21

R/W

-

28/20

R/W

-

27/19

R/W

-

26/18

R/W

-

24/16

R/W

-

Read/Write

Initial Value

V2.0 part B

Bit

15/7

14/6

13/5

12/4

11/3

10/2

9/1

8/0

IDT

4

IDT

3

IDT

2

IDT

1

9

IDT

0

8

RTRTAG RB1TAG RB0TAG CANIDT4

IDT12

IDT20

IDT28

31/23

R/W

-

IDT11

IDT19

IDT27

30/22

R/W

-

IDT10

IDT18

IDT26

29/21

R/W

-

IDT

7

IDT6

IDT

5

CANIDT3

CANIDT2

CANIDT1

IDT17

IDT25

28/20

R/W

-

IDT16

IDT24

27/19

R/W

-

IDT15

IDT23

26/18

R/W

-

IDT14

IDT22

25/17

R/W

-

IDT13

IDT21

24/16

R/W

-

Bit

Read/Write

Initial Value

V2.0 part A

• Bit 31:21 – IDT10:0: Identifier Tag

Identifier field of the remote or data frame to send.

This field is updated with the corresponding value of the remote or data frame received.

• Bit 20:3 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, they must be written

to zero when CANIDTn are written.

When a remote or data frame is received, these bits do not operate in the comparison but they

are updated with un-predicted values.

• Bit 2 – RTRTAG: Remote Transmission Request Tag

RTR bit of the remote or data frame to send.

This tag is updated with the corresponding value of the remote or data frame received. In case

of Automatic Reply mode, this bit is automatically reset before sending the response.

• Bit 1 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when CANIDTn are written.

262

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

When a remote or data frame is received, this bit does not operate in the comparison but it is

updated with un-predicted values.

• Bit 0 – RB0TAG: Reserved Bit 0 Tag

RB0 bit of the remote or data frame to send.

This tag is updated with the corresponding value of the remote or data frame received.

V2.0 part B

• Bit 31:3 – IDT28:0: Identifier Tag

Identifier field of the remote or data frame to send.

This field is updated with the corresponding value of the remote or data frame received.

• Bit 2 – RTRTAG: Remote Transmission Request Tag

RTR bit of the remote or data frame to send.

This tag is updated with the corresponding value of the remote or data frame received. In case

of Automatic Reply mode, this bit is automatically reset before sending the response.

• Bit 1 – RB1TAG: Reserved Bit 1 Tag

RB1 bit of the remote or data frame to send.

This tag is updated with the corresponding value of the remote or data frame received.

• Bit 0 – RB0TAG: Reserved Bit 0 Tag

RB0 bit of the remote or data frame to send.

This tag is updated with the corresponding value of the remote or data frame received.

20.11.4 CAN Identifier Mask Registers -

CANIDM1, CANIDM2, CANIDM3, and CANIDM4

V2.0 part A

Bit

15/7

14/6

13/5

12/4

11/3

10/2

9/1

8/0

-

RTRMSK

-

IDEMSK CANIDM4

-

CANIDM3

CANIDM2

CANIDM1

IDMSK

2

IDMSK

1

9

IDMSK

0

8

IDMSK10

31/23

R/W

IDMSK

7

IDMSK

27/19

R/W

-

6

IDMSK

5

IDMSK

4

IDMSK3

Bit

30/22

R/W

-

29/21

R/W

-

28/20

R/W

-

26/18

R/W

-

25/17

R/W

-

24/16

R/W

-

Read/Write

Initial Value

-

V2.0 part B

Bit

15/7

14/6

13/5

12/4

11/3

10/2

9/1

8/0

IDMSK

4

IDMSK

3

IDMSK

2

IDMSK

1

IDMSK

0

RTRMSK

-

IDEMSK CANIDM4

IDMSK CANIDM3

IDMSK12 IDMSK11 IDMSK10

IDMSK

9

IDMSK

8

IDMSK

7

IDMSK

6

5

IDMSK20 IDMSK19 IDMSK18 IDMSK17 IDMSK16 IDMSK15 IDMSK14 IDMSK13 CANIDM2

IDMSK28 IDMSK27 IDMSK26 IDMSK25 IDMSK24 IDMSK23 IDMSK22 IDMSK21 CANIDM1

Bit

31/23

R/W

30/22

R/W

29/21

R/W

28/20

R/W

27/19

R/W

26/18

R/W

25/17

R/W

24/16

R/W

Read/Write

Initial Value

-

263

7538B–CAN–05/06

V2.0 part A

• Bit 31:21 – IDMSK10:0: Identifier Mask

– 0 - comparison true forced

– 1 - bit comparison enabled.

• Bit 20:3 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, they must be written

to zero when CANIDMn are written.

• Bit 2 – RTRMSK: Remote Transmission Request Mask

– 0 - comparison true forced

– 1 - bit comparison enabled.

• Bit 1 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when CANIDTn are written.

• Bit 0 – IDEMSK: Identifier Extension Mask

– 0 - comparison true forced

– 1 - bit comparison enabled.

V2.0 part B

• Bit 31:3 – IDMSK28:0: Identifier Mask

– 0 - comparison true forced

– 1 - bit comparison enabled.

• Bit 2 – RTRMSK: Remote Transmission Request Mask

– 0 - comparison true forced

– 1 - bit comparison enabled.

• Bit 1 – Reserved Bit

Writing zero in this bit is recommended.

• Bit 0 – IDEMSK: Identifier Extension Mask

– 0 - comparison true forced

– 1 - bit comparison enabled.

20.11.5 CAN Time Stamp Registers - CANSTML and CANSTMH

Bit

7

6

5

4

3

2

1

0

TIMSTM7 TIMSTM6 TIMSTM5 TIMSTM4 TIMSTM3 TIMSTM2 TIMSTM1 TIMSTM0 CANSTML

TIMSTM15 TIMSTM14 TIMSTM13 TIMSTM12 TIMSTM11 TIMSTM10 TIMSTM9 TIMSTM8 CANSTMH

Bit

15

R

-

14

R

-

13

R

-

12

R

-

11

R

-

10

R

-

9

R

-

8

R

-

Read/Write

Initial Value

• Bits 15:0 - TIMSTM15:0: Time Stamp Count

CAN time stamp counter range 0 to 65,535.

264

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

20.11.6 CAN Data Message Register - CANMSG

Bit

7

MSG 7

R/W

-

6

MSG 6

R/W

-

5

MSG 5

R/W

-

4

MSG 4

R/W

-

3

MSG 3

R/W

-

2

MSG 2

R/W

-

1

0

MSG 1

R/W

-

MSG 0

R/W

-

CANMSG

Read/Write

Initial Value

• Bit 7:0 – MSG7:0: Message Data

This register contains the CAN data byte pointed at the page MOb register.

After writing in the page MOb register, this byte is equal to the specified message location of the

pre-defined identifier + index. If auto-incrementation is used, at the end of the data register writ-

ing or reading cycle, the index is auto-incremented.

The range of the counting is 8 with no end of loop (0, 1,..., 7, 0,...).

20.12 Examples of CAN Baud Rate Setting

The CAN bus requires very accurate timing especially for high baud rates. It is recommended to

use only an external crystal for CAN operations.

(Refer to “Bit Timing” on page 240 for timing description and page 256 to page 257 for “CAN Bit

Timing Registers”).

Table 20-2. Examples of CAN Baud Rate Settings for Commonly Frequencies

CAN

Description

Segments

Registers

Baud

Rate

(Kbps)

fclk_io

(MHz)

Sampling

Point

TQ

(µs)

Tbit

(TQ)

Tprs

(TQ)

Tph1

(TQ)

Tph2

(TQ)

Tsjw

(TQ)

CANBT1 CANBT2

CANBT3

0x37

0x13

0x37

0x13

0x37

0x13

0x37

0x13

0x37

0x13

0x37

0x13

0.0625

0.125

0.250

0.500

0.3125

0.625

0.500

1.000

0.625

1.250

16

8

7

3

7

3

7

3

7

3

7

3

7

3

4

2

4

2

4

2

4

2

4

2

4

2

1

0x00

0x02

0x06

0x0E

0x08

0x12

0x0E

0x1E

0x12

0x26

0x0C

0x04

0x0C

0x04

0x0C

0x04

0x0C

0x04

0x0C

0x04

0x0C

0x04

1000

500

250

200

125

100

75 %

2

16

8

4

2

16

8

4

2

16.000

16

8

4

2

16

8

4

2

16

8

4

2

265

7538B–CAN–05/06

Table 20-2. Examples of CAN Baud Rate Settings for Commonly Frequencies (Continued)

CAN

Description

Segments

Registers

Baud

Rate

(Kbps)

fclk_io

(MHz)

Sampling

Point

TQ

(µs)

Tbit

(TQ)

Tprs

(TQ)

Tph1

(TQ)

Tph2

(TQ)

Tsjw

(TQ)

CANBT1 CANBT2

CANBT3

0.083333

12

x

5

3

1

0x00

0x08

0x25

1000

500

250

200

125

100

1000

500

250

200

125

100

75 %

- - - n o d a t a - - -

0.166666

0.250

12

8

5

3

7

3

8

5

7

3

8

5

3

2

4

2

6

3

4

2

6

3

2

4

2

5

3

4

2

5

3

1

0x02

0x04

0x0A

0x04

0x08

0x0A

0x16

0x0A

0x12

0x08

0x04

0x0C

0x04

0x0E

0x08

0x0C

0x04

0x0E

0x08

0x25

0x13

0x37

0x13

0x4B

0x25

0x37

0x13

0x4B

0x25

0.250

16

8

0.500

12.000

0.250

20

12

16

8

0.416666

0.500

1.000

0.500

20

12

x

0.833333

- - - n o d a t a - - -

0.125

0.250

0.500

0.250

0.625

0.500

1.000

0.625

1.250

8

3

7

3

7

3

8

3

7

3

7

3

2

4

2

4

2

6

2

4

2

4

2

4

2

4

2

5

2

4

2

4

2

1

0x00

0x02

0x06

0x02

0x08

0x06

0x0E

0x08

0x12

0x04

0x0C

0x04

0x0C

0x04

0x0E

0x04

0x0C

0x04

0x0C

0x04

0x13

0x37

0x13

0x37

0x13

0x4B

0x13

0x37

0x13

0x37

0x13

16

8

16

8

8.000

20

8

16

8

16

8

266

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Table 20-2. Examples of CAN Baud Rate Settings for Commonly Frequencies (Continued)

CAN

Description

Segments

Registers

Baud

Rate

(Kbps)

fclk_io

(MHz)

Sampling

Point

TQ

(µs)

Tbit

(TQ)

Tprs

(TQ)

Tph1

(TQ)

Tph2

(TQ)

Tsjw

(TQ)

CANBT1 CANBT2

CANBT3

1000

- - - n o t a p p l i c a b l e - - -

0.166666

12

x

5

3

1

0x00

0x08

0x25

500

75 %

80 %

75 %

- - - n o d a t a - - -

0.333333

0.500

12

8

5

3

7

4

7

3

8

5

3

2

4

3

4

2

6

3

2

3

2

4

2

5

3

1

0x02

0x04

0x02

0x04

0x0A

0x04

0x08

0x04

0x0C

0x06

0x0C

0x04

0x0E

0x08

0x25

0x13

0x35

0x23

0x37

0x13

0x4B

0x25

250

200

125

6.000

0.333333

0.500

15

10

16

8

0.500

1.000

0.500

20

12

100

0.833333

1000

500

- - - n o t a p p l i c a b l e - - -

- - - n o d a t a - - -

x

8

75 %

0.250

0.500

0.250

3

7

3

8

2

4

2

6

2

4

2

5

1

0x00

0x02

0x00

0x04

0x0C

0x04

0x0E

0x13

0x37

0x13

0x4B

16

8

250

200

125

100

4.000

20

x

- - - n o d a t a - - -

0.500

1.000

0.500

1.250

16

8

7

3

8

3

4

2

6

2

4

2

5

2

1

0x02

0x06

0x02

0x08

0x0C

0x04

0x0E

0x04

0x37

0x13

0x4B

0x13

20

8

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21. Analog Comparator

The Analog Comparator compares the input values on the positive pin AIN0 and negative pin

AIN1.

21.1 Overview

When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1,

the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the

Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate inter-

rupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator

output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown

in Figure 21-1

Figure 21-1. Analog Comparator Block Diagram⁽¹⁾⁽²⁾

BANDGAP

REFERENCE

ACBG

ACME

ADEN

T/C1 INPUT CAPTURE

ADC

MULTIPLEXER

OUTPUT

Notes: 1. ADC multiplexer output: see Table 21-2 on page 270.

2. Refer to Figure 2-2 on page 5 and Table 10-15 on page 83 for Analog Comparator pin

placement.

21.2 Analog Comparator Register Description

21.2.1

ADC Control and Status Register B – ADCSRB

Bit

7

-

6

ACME

R/W

0

5

–

4

–

3

–

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

ADCSRB

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 6 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the

ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written

logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed

description of this bit, see “Analog Comparator Multiplexed Input” on page 270.

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21.2.2

Analog Comparator Control and Status Register – ACSR

Bit

7

6

ACBG

R/W

0

5

ACO

R

4

3

ACIE

R/W

0

2

ACIC

R/W

0

1

0

ACD

R/W

0

ACI

R/W

0

ACIS1

R/W

0

ACIS0

R/W

0

ACSR

Read/Write

Initial Value

N/A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This bit

can be set at any time to turn off the Analog Comparator. This will reduce power consumption in

Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be

disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is

changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog

Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-

ator. See “Internal Voltage Reference” on page 56.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The

synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set

and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-

parator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the input capture function in Timer/Counter1 to be trig-

gered by the Analog Comparator. The comparator output is in this case directly connected to the

input capture front-end logic, making the comparator utilize the noise canceler and edge select

features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection

between the Analog Comparator and the input capture function exists. To make the comparator

trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask

Register (TIMSK1) must be set.

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• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The

different settings are shown in Table 21-1.

Table 21-1. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the

bits are changed.

21.3 Analog Comparator Multiplexed Input

It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Com-

parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be

switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in

ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX

select the input pin to replace the negative input to the Analog Comparator, as shown in Table

21-2. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog

Comparator.

Table 21-2. Analog Comparator Multiplexed Input

ACME

ADEN

MUX2..0

xxx

Analog Comparator Negative Input

0

1

x

1

0

AIN1

xxx

AIN1

000

001

010

011

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

100

101

110

111

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21.3.1

Digital Input Disable Register 1 – DIDR1

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

0

AIN1D

R/W

0

AIN0D

R/W

0

DIDR1

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-

sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is

applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-

ten logic one to reduce power consumption in the digital input buffer.

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22. Analog to Digital Converter - ADC

22.1 Features

• 10-bit Resolution

• 0.5 LSB Integral Non-linearity

• ± 2 LSB Absolute Accuracy

• 65 - 260 µs Conversion Time

• Up to 15 kSPS at Maximum Resolution

• Eight Multiplexed Single Ended Input Channels

• Seven Differential input channels

• Optional Left Adjustment for ADC Result Readout

• 0 - V_CCADC Input Voltage Range

• Selectable 2.56 V ADC Reference Voltage

• Free Running or Single Conversion Mode

• ADC Start Conversion by Auto Triggering on Interrupt Sources

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

The AT90CAN32/64 features a 10-bit successive approximation ADC. The ADC is connected to

an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed

from the pins of Port F. The single-ended voltage inputs refer to 0V (GND).

The device also supports 16 differential voltage input combinations. Two of the differential inputs

(ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing

amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage

before the A/D conversion. Seven differential analog input channels share a common negative

terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x

or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit resolution can be

expected.

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 22-1.

The ADC has a separate analog supply voltage pin, AV_CC. AV_CCmust not differ more than

0.3V from V_CC. See the paragraph “ADC Noise Canceler” on page 279 on how to connect this

pin.

Internal reference voltages of nominally 2.56V or AV_CCare provided On-chip. The voltage refer-

ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.

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Figure 22-1. Analog to Digital Converter Block Schematic

ADC CONVERSION

COMPLETE IRQ

INTERRUPT

FLAGS

ADTS[2:0]

8-BIT DATA BUS

15

0

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL. & STATUS

REGISTER (ADCSRA)

ADC DATA REGISTER

(ADCH/ADCL)

TRIGGER

SELECT

MUX DECODER

PRESCALER

START

CONVERSION LOGIC

AVCC

INTERNAL

SAMPLE & HOLD

REFERENCE

COMPARATOR

AREF

GND

10-BIT DAC

-

+

BANDGAP

REFERENCE

ADC7

SINGLE ENDED / DIFFERENTIAL SELECTION

ADC6

POS.

INPUT

ADC MULTIPLEXER

OUTPUT

ADC5

MUX

ADC4

DIFFERENTIAL

AMPLIFIER

ADC3

+

ADC2

-

ADC1

ADC0

NEG.

INPUT

MUX

22.2 Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the voltage on

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the AREF pin minus 1 LSB. Optionally, AV_CCor an internal 2.56V reference voltage may be con-

nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal

voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve

noise immunity.

The analog input channel and differential gain are selected by writing to the MUX bits in

ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can

be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as

positive and negative inputs to the differential amplifier.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and

input channel selections will not go into effect until ADEN is set. The ADC does not consume

power when ADEN is cleared, so it is recommended to switch off the ADC before entering power

saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data

Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers

is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. The ADC

access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt

will trigger even if the result is lost.

22.3 Starting a Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware

when the conversion is completed. If a different data channel is selected while a conversion is in

progress, the ADC will finish the current conversion before performing the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS

bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,

the ADC prescaler is reset and a conversion is started. This provides a method of starting con-

versions at fixed intervals. If the trigger signal is still set when the conversion completes, a new

conversion will not be started. If another positive edge occurs on the trigger signal during con-

version, the edge will be ignored. Note that an interrupt flag will be set even if the specific

interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus

be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to

trigger a new conversion at the next interrupt event.

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Figure 22-2. ADC Auto Trigger Logic

ADTS[2:0]

PRESCALER

CLK_ADC

START

ADATE

ADIF

SOURCE 1

.

CONVERSION

LOGIC

EDGE

DETECTOR

SOURCE n

ADSC

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon

as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-

stantly sampling and updating the ADC Data Register. The first conversion must be started by

writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive

conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to

one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be

read as one during a conversion, independently of how the conversion was started.

22.4 Prescaling and Conversion Timing

Figure 22-3. ADC Prescaler

ADEN

START

Reset

7-BIT ADC PRESCALER

CK

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

By default, the successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously

reset when ADEN is low.

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When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle. See “Differential Channels” on page

277 for details on differential conversion timing.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-

sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion

mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new

conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures

a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold

takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-

tional CPU clock cycles are used for synchronization logic.

In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high. For a summary of conversion times, see Table 22-1.

Figure 22-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

Conversion

Cycle Number

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

3

ADC Clock

ADEN

ADSC

ADIF

Sign and MSB of Result

ADCH

ADCL

LSB of Result

MUX

MUX and REFS

Update

Conversion

Complete

and REFS

Update

Sample & Hold

Figure 22-5. ADC Timing Diagram, Single Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

3

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

Sign and MSB of Result

LSB of Result

ADCL

Sample & Hold

Conversion

Complete

MUX and REFS

Update

MUX and REFS

Update

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Figure 22-6. ADC Timing Diagram, Auto Triggered Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

Cycle Number

ADC Clock

Trigger

Source

ADATE

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample &

Hold

Prescaler

Reset

Conversion

Complete

Prescaler

Reset

MUX and REFS

Update

Figure 22-7. ADC Timing Diagram, Free Running Conversion

One Conversion

Next Conversion

11

12

13

1

2

3

4

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample & Hold

Conversion

Complete

MUX and REFS

Update

Table 22-1. ADC Conversion Time

Normal

Conversion,

Single Ended

Auto

Triggered

Conversion

First

Conversion

Condition

Sample & Hold (Cycles from Start of

Convention)

14.5

25

1.5

13

2

Conversion Time (Cycles)

13.5

22.4.1

Differential Channels

When using differential channels, certain aspects of the conversion need to be taken into

consideration.

Differential conversions are synchronized to the internal clock CK_ADC2equal to half the ADC

clock frequency. This synchronization is done automatically by the ADC interface in such a way

that the sample-and-hold occurs at a specific phase of CK_ADC2. A conversion initiated by the

user (i.e., all single conversions, and the first free running conversion) when CK_ADC2is low will

take the same amount of time as a single ended conversion (13 ADC clock cycles from the next

prescaled clock cycle). A conversion initiated by the user when CK_ADC2is high will take 14 ADC

clock cycles due to the synchronization mechanism. In Free Running mode, a new conversion is

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initiated immediately after the previous conversion completes, and since CK_ADC2is high at this

time, all automatically started (i.e., all but the first) Free Running conversions will take 14 ADC

clock cycles.

If differential channels are used and conversions are started by Auto Triggering, the ADC must

be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset

before the conversion is started. Since the stage is dependent of a stable ADC clock prior to the

conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between

each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended conversions are

performed. The result from the extended conversions will be valid. See “Prescaling and Conver-

sion Timing” on page 275 for timing details.

The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequencies may

be subjected to non-linear amplification. An external low-pass filter should be used if the input

signal contains higher frequency components than the gain stage bandwidth. Note that the ADC

clock frequency is independent of the gain stage bandwidth limitation. E.g. the ADC clock period

may be 6 µs, allowing a channel to be sampled at 12 kSPS, regardless of the bandwidth of this

channel.

22.5 Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary

register to which the CPU has random access. This ensures that the channels and reference

selection only takes place at a safe point during the conversion. The channel and reference

selection is continuously updated until a conversion is started. Once the conversion starts, the

channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-

tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or reference selection values

to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

1. When ADATE or ADEN is cleared.

2. During conversion, minimum one ADC clock cycle after the trigger event.

3. After a conversion, before the interrupt flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

Special care should be taken when changing differential channels. Once a differential channel

has been selected, the stage may take as much as 125 µs to stabilize to the new value. Thus

conversions should not be started within the first 125 µs after selecting a new differential chan-

nel. Alternatively, conversion results obtained within this period should be discarded.

The same settling time should be observed for the first differential conversion after changing

ADC reference (by changing the REFS1:0 bits in ADMUX).

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22.5.1

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

• In Single Conversion mode, always select the channel before starting the conversion. The

channel selection may be changed one ADC clock cycle after writing one to ADSC. However,

the simplest method is to wait for the conversion to complete before changing the channel

selection.

• In Free Running mode, always select the channel before starting the first conversion. The

channel selection may be changed one ADC clock cycle after writing one to ADSC. However,

the simplest method is to wait for the first conversion to complete, and then change the

channel selection. Since the next conversion has already started automatically, the next

result will reflect the previous channel selection. Subsequent conversions will reflect the new

channel selection.

When switching to a differential gain channel, the first conversion result may have a poor accu-

racy due to the required settling time for the automatic offset cancellation circuitry. The user

should preferably disregard the first conversion result.

22.5.2

ADC Voltage Reference

The reference voltage for the ADC (V_REF) indicates the conversion range for the ADC. Single

ended channels that exceed V_REFwill result in codes close to 0x3FF. V_REFcan be selected as

either AV_CC, internal 2.56V reference, or external AREF pin.

AV_CCis connected to the ADC through a passive switch. The internal 2.56V reference is gener-

ated from the internal bandgap reference (V_BG) through an internal amplifier. In either case, the

external AREF pin is directly connected to the ADC, and the reference voltage can be made

more immune to noise by connecting a capacitor between the AREF pin and ground. V_REFcan

also be measured at the AREF pin with a high impedant voltmeter. Note that V_REFis a high

impedant source, and only a capacitive load should be connected in a system.

If the user has a fixed voltage source connected to the AREF pin, the user may not use the other

reference voltage options in the application, as they will be shorted to the external voltage. If no

external voltage is applied to the AREF pin, the user may switch between AV_CCand 2.56V as

reference selection. The first ADC conversion result after switching reference voltage source

may be inaccurate, and the user is advised to discard this result.

If differential channels are used, the selected reference should not be closer to AV_CCthan indi-

cated in Table 27-5 on page 372.

22.6 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise

induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC

Noise Reduction and Idle mode. To make use of this feature, the following procedure should be

used:

1. Make sure that the ADC is enabled and is not busy converting. Single Conversion

mode must be selected and the ADC conversion complete interrupt must be enabled.

2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once

the CPU has been halted.

3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt

will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If

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another interrupt wakes up the CPU before the ADC conversion is complete, that inter-

rupt will be executed, and an ADC Conversion Complete interrupt request will be

generated when the ADC conversion completes. The CPU will remain in active mode

until a new sleep command is executed.

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

If the ADC is enabled in such sleep modes and the user wants to perform differential conver-

sions, the user is advised to switch the ADC off and on after waking up from sleep to prompt an

extended conversion to get a valid result.

22.6.1

Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 22-8. An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must drive the S/H capacitor through the series resistance (combined resistance in the

input path).

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources

with slowly varying signals, since this minimizes the required charge transfer to the S/H

capacitor.

If differential gain channels are used, the input circuitry looks somewhat different, although

source impedances of a few hundred kΩ or less is recommended.

Signal components higher than the Nyquist frequency (f_ADC/2) should not be present for either

kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised

to remove high frequency components with a low-pass filter before applying the signals as

inputs to the ADC.

Figure 22-8. Analog Input Circuitry

I

IH

ADCn

1..100 kO

C

= 14 pF

V

S/H

I

IL

/2

CC

22.6.2

Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. If conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

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1. Keep analog signal paths as short as possible. Make sure analog tracks run over the

analog ground plane, and keep them well away from high-speed switching digital

tracks.

2. The AV_CCpin on the device should be connected to the digital V_CCsupply voltage via

an LC network as shown in Figure 22-9.

3. Use the ADC noise canceler function to reduce induced noise from the CPU.

4. If any ADC port pins are used as digital outputs, it is essential that these do not switch

while a conversion is in progress.

Figure 22-9. ADC Power Connections

(AD0) PA0 51

VCC

52

GND 53

(ADC7) PF7 54

(ADC6) PF6 55

(ADC5) PF5 56

(ADC4) PF4 57

(ADC3) PF3 58

(ADC2) PF2 59

(ADC1) PF1

(ADC0) PF0

60

61

10uH

62

63

64

AREF

GND

AVCC

100nF

1

Analog Ground Plane

22.6.3

22.6.4

Offset Compensation Schemes

The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-

surements as much as possible. The remaining offset in the analog path can be measured

directly by selecting the same channel for both differential inputs. This offset residue can be then

subtracted in software from the measurement results. Using this kind of software based offset

correction, offset on any channel can be reduced below one LSB.

ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V_REFin 2ⁿsteps

(LSBs). The lowest code is read as 0, and the highest code is read as 2ⁿ-1.

Several parameters describe the deviation from the ideal behavior:

• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition

(at 0.5 LSB). Ideal value: 0 LSB.

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Figure 22-10. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset

Error

V_REF

Input Voltage

• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last

transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).

Ideal value: 0 LSB

Figure 22-11. Gain Error

Gain

Error

Output Code

Ideal ADC

Actual ADC

V

Input Voltage

REF

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum

deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB.

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Figure 22-12. Integral Non-linearity (INL)

Output Code

Ideal ADC

Actual ADC

V_REFInput Voltage

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval

between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 22-13. Differential Non-linearity (DNL)

Output Code

0x3FF

1 LSB

DNL

0x000

0

V

Input Voltage

REF

• Quantization Error: Due to the quantization of the input voltage into a finite number of codes,

a range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB.

• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to

an ideal transition for any code. This is the compound effect of offset, gain error, differential

error, non-linearity, and quantization error. Ideal value: 0.5 LSB.

22.7 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH).

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For single ended conversion, the result is:

⋅ 1023

where V_INis the voltage on the selected input pin and V_REFthe selected voltage reference (see

Table 22-3 on page 286 and Table 22-4 on page 287). 0x000 represents analog ground, and

0x3FF represents the selected reference voltage minus one LSB.

If differential channels are used, the result is:

(

) ⋅

⋅ 512

where V_POSis the voltage on the positive input pin, V_NEGthe voltage on the negative input pin,

GAIN the selected gain factor and V_REFthe selected voltage reference. The result is presented

in two’s complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user

wants to perform a quick polarity check of the result, it is sufficient to read the MSB of the result

(ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is posi-

tive. Figure 22-14 shows the decoding of the differential input range.

Table 82 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is

selected with a reference voltage of V_REF

.

Figure 22-14. Differential Measurement Range

Output Code

0x1FF

0x000

0

Differential Input

Voltage (Volts)

- V_REF

V_REF

0x3FF

0x200

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Table 22-2. Correlation Between Input Voltage and Output Codes

V_ADCn

Read code

0x1FF

0x1FE

...

Corresponding decimal value

V_ADCm+ V_REF/GAIN

V_ADCm+ 0.999 V_REF/GAIN

V_ADCm+ 0.998 V_REF/GAIN

...

511

510

...

V_ADCm+ 0.001 V_REF/GAIN

V_ADCm

0x001

0x000

0x3FF

...

1

0

V_ADCm- 0.001 V_REF/GAIN

...

-1

...

V_ADCm- 0.999 V_REF/GAIN

V_ADCm- V_REF/GAIN

0x201

0x200

-511

-512

Example 1:

– ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)

– Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.

– ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270

– ADCL will thus read 0x00, and ADCH will read 0x9C.

Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02.

Example 2:

– ADMUX = 0xFB (ADC3 - ADC2, 1x gain, 2.56V reference, left adjusted result)

– Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.

– ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029

– ADCL will thus read 0x40, and ADCH will read 0x0A.

Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29.

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22.8 ADC Register Description

22.8.1

ADC Multiplexer Selection Register – ADMUX

Bit

7

REFS1

R/W

0

6

REFS0

R/W

0

5

ADLAR

R/W

0

4

MUX4

R/W

0

3

MUX3

R/W

0

2

MUX2

R/W

0

1

MUX1

R/W

0

MUX0

R/W

0

ADMUX

Read/Write

Initial Value

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 22-3. If these bits are

changed during a conversion, the change will not go in effect until this conversion is complete

(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external

reference voltage is being applied to the AREF pin.

Table 22-3. Voltage Reference Selections for ADC

REFS1

REFS0

Voltage Reference Selection

0

1

0

1

0

1

AREF, Internal Vref turned off

AV_CCwith external capacitor on AREF pin

Reserved

Internal 2.56V Voltage Reference with external capacitor on AREF pin

•

Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a complete description of this bit, see “The ADC Data Register – ADCL and ADCH” on

page 289.

• Bits 4:0 – MUX4:0: Analog Channel Selection Bits

The value of these bits selects which combination of analog inputs are connected to the ADC.

These bits also select the gain for the differential channels. See Table 22-4 for details. If these

bits are changed during a conversion, the change will not go in effect until this conversion is

complete (ADIF in ADCSRA is set).

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Table 22-4. Input Channel and Gain Selections

Single Ended

Input

Positive Differential

Input

Negative Differential

Input

MUX4..0

Gain

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

N/A

(ADC0 / ADC0 / 10x)

ADC1

ADC0

ADC2

10x

(ADC0 / ADC0 / 200x)

ADC1

200x

10x

(ADC2 / ADC2 / 10x)

ADC3

(ADC2 / ADC2 / 200x)

ADC3

ADC2

ADC1

200x

1x

ADC0

(ADC1 / ADC1 / 1x)

ADC2

ADC1

ADC2

1x

N/A

ADC3

ADC4

ADC5

ADC6

ADC7

ADC0

ADC1

(ADC2 / ADC2 / 1x)

ADC3

ADC2

1x

ADC4

ADC5

1.1V (V_{Band Gap}

0V (GND)

)

N/A

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22.8.2

ADC Control and Status Register A – ADCSRA

Bit

7

ADEN

R/W

0

6

ADSC

R/W

0

5

ADATE

R/W

0

4

ADIF

R/W

0

3

ADIE

R/W

0

2

ADPS2

R/W

0

1

ADPS1

R/W

0

ADPS0

R/W

0

ADCSRA

Read/Write

Initial Value

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,

write this bit to one to start the first conversion. The first conversion after ADSC has been written

after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,

will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-

tion of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete,

it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive edge of the selected trigger signal. The trigger source is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The

ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.

ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-

natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-

Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI

instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

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• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input clock to the

ADC.

Table 22-5. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

22.8.3

The ADC Data Register – ADCL and ADCH

ADLAR = 0

Bit

15

14

13

12

11

10

9

8

–

ADC9

ADC8

ADCH

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

Bit

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

R

0

Read/Write

Initial Value

0

ADLAR = 1

Bit

15

ADC9

ADC1

7

14

13

12

11

10

9

8

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

ADCL

ADC0

–

5

–

4

–

3

–

2

–

1

–

0

6

R

0

Read/Write

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Initial Value

0

When an ADC conversion is complete, the result is found in these two registers. If differential

channels are used, the result is presented in two’s complement form.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input

channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then

ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result

is right adjusted.

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• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on

page 283.

22.8.4

ADC Control and Status Register B – ADCSRB

Bit

7

6

5

4

–

3

–

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

–

ACME

–

ADCSRB

Read/Write

Initial Value

R

0

R/W

0

R

0

R

0

R

0

• Bit 7– Reserved Bit

This bit is reserved for future use. For compatibility with future devices, it must be written to zero

when ADCSRB is written.

• Bit 5:3– Reserved Bits

These bits are reserved for future use. For compatibility with future devices, they must be written

to zero when ADCSRB is written.

• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected interrupt flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set

Table 22-6. ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Free Running mode

Analog Comparator

External Interrupt Request 0

Timer/Counter0 Compare Match

Timer/Counter0 Overflow

Timer/Counter1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter1 Capture Event

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22.8.5

Digital Input Disable Register 0 – DIDR0

Bit

7

ADC7D

R/W

0

6

ADC6D

R/W

0

5

ADC5D

R/W

0

4

ADC4D

R/W

0

3

ADC3D

R/W

0

2

ADC2D

R/W

0

1

0

ADC1D

R/W

0

ADC0D

R/W

0

DIDR0

Read/Write

Initial Value

• Bit 7:0 – ADC7D..ADC0D: ADC7:0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

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23. JTAG Interface and On-chip Debug System

23.1 Features

• JTAG (IEEE std. 1149.1 Compliant) Interface

• Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard

• Debugger Access to:

– All Internal Peripheral Units

– Internal and External RAM

– The Internal Register File

– Program Counter

– EEPROM and Flash Memories

• Extensive On-chip Debug Support for Break Conditions, Including

– AVR Break Instruction

– Break on Change of Program Memory Flow

– Single Step Break

– Program Memory Break Points on Single Address or Address Range

– Data Memory Break Points on Single Address or Address Range

• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• On-chip Debugging Supported by AVR Studio^®

23.2 Overview

The AVR IEEE std. 1149.1 compliant JTAG interface can be used for:

• Testing PCBs by using the JTAG Boundary-scan capability

• Programming the non-volatile memories, Fuses and Lock bits

• On-chip debugging

A brief description is given in the following sections. Detailed descriptions for Programming via

the JTAG interface, and using the Boundary-scan Chain can be found in the sections “JTAG

Programming Overview” on page 351 and “Boundary-scan IEEE 1149.1 (JTAG)” on page 299,

respectively. The On-chip Debug support is considered being private JTAG instructions, and dis-

tributed within ATMEL and to selected third party vendors only.

Figure 23-1 shows a block diagram of the JTAG interface and the On-chip Debug system. The

TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller

selects either the JTAG Instruction Register or one of several Data Registers as the scan chain

(Shift Register) between the TDI – input and TDO – output. The Instruction Register holds JTAG

instructions controlling the behavior of a Data Register.

The ID-Register (IDentifier Register), Bypass Register, and the Boundary-scan Chain are the

Data Registers used for board-level testing. The JTAG Programming Interface (actually consist-

ing of several physical and virtual Data Registers) is used for serial programming via the JTAG

interface. The Internal Scan Chain and Break Point Scan Chain are used for On-chip debugging

only.

23.3 Test Access Port – TAP

The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins

constitute the Test Access Port – TAP. These pins are:

• TMS: Test mode select. This pin is used for navigating through the TAP-controller state

machine.

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• TCK: Test Clock. JTAG operation is synchronous to TCK.

• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register

(Scan Chains).

• TDO: Test Data Out. Serial output data from Instruction Register or Data Register (Scan

Chains).

The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not

provided.

When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the

TAP controller is in reset. When programmed and the JTD bit in MCUCR is cleared, the TAP

input signals are internally pulled high and the JTAG is enabled for Boundary-scan and program-

ming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG TAP

controller is not shifting data, and must therefore be connected to a pull-up resistor or other

hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The

device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-

tored by the debugger to be able to detect external reset sources. The debugger can also pull

the RESET pin low to reset the whole system, assuming only open collectors on the reset line

are used in the application.

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Figure 23-1. Block Diagram

I/O PORT 0

DEVICE BOUNDARY

BOUNDARY SCAN CHAIN

TDI

JTAG PROGRAMMING

INTERFACE

TDO

TCK

TMS

TAP

CONTROLLER

INTERNAL

SCAN

CHAIN

FLASH

MEMORY

Address

Data

PC

Instruction

INSTRUCTION

REGISTER

AVR CPU

ID

REGISTER

BREAKPOINT

UNIT

M

U

X

FLOW CONTROL

UNIT

BYPASS

REGISTER

DIGITAL

PERIPHERAL

UNITS

ANALOG

PERIPHERIAL

UNITS

BREAKPOINT

SCAN CHAIN

JTAG / AVR CORE

COMMUNICATION

INTERFACE

ADDRESS

DECODER

OCD STATUS

AND CONTROL

I/O PORT n

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Figure 23-2. TAP Controller State Diagram

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

1

Capture-DR

Capture-IR

0

Shift-DR

0

Shift-IR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-IR

1

Pause-DR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

23.4 TAP Controller

The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-

scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions

depicted in Figure 23-2 depend on the signal present on TMS (shown adjacent to each state

transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-

Logic-Reset.

As a definition in this document, the LSB is shifted in and out first for all Shift Registers.

Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:

• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift

Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG

instructions into the JTAG Instruction Register from the TDI input at the rising edge of TCK.

The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR

state. The MSB of the instruction is shifted in when this state is left by setting TMS high.

While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on

the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI

and TDO and controls the circuitry surrounding the selected Data Register.

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• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched

onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR,

Pause-IR, and Exit2-IR states are only used for navigating the state machine.

• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift

Data Register – Shift-DR state. While in this state, upload the selected data register (selected

by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the

rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low

during input of all bits except the MSB. The MSB of the data is shifted in when this state is left

by setting TMS high. While the data register is shifted in from the TDI pin, the parallel inputs

to the data register captured in the Capture-DR state is shifted out on the TDO pin.

• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected data

register has a latched parallel-output, the latching takes place in the Update-DR state. The

Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.

As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting

JTAG instruction and using data registers, and some JTAG instructions may select certain func-

tions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.

Note:

Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be

entered by holding TMS high for five TCK clock periods.

For detailed information on the JTAG specification, refer to the literature listed in “Bibliography”

on page 298.

23.5 Using the Boundary-scan Chain

A complete description of the Boundary-scan capabilities are given in the section “Boundary-

scan IEEE 1149.1 (JTAG)” on page 299.

23.6 Using the On-chip Debug System

As shown in Figure 23-1, the hardware support for On-chip Debugging consists mainly of

• A scan chain on the interface between the internal AVR CPU and the internal peripheral

units.

• Break Point unit.

• Communication interface between the CPU and JTAG system.

All read or modify/write operations needed for implementing the Debugger are done by applying

AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O

memory mapped location which is part of the communication interface between the CPU and the

JTAG system.

The Break Point Unit implements Break on Change of Program Flow, Single Step Break, two

Program Memory Break Points, and two combined Break Points. Together, the four Break

Points can be configured as either:

• 4 single Program Memory Break Points.

• 3 single Program Memory Break Points + 1 single Data Memory Break Point.

• 2 single Program Memory Break Points + 2 single Data Memory Break Points.

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• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range

Break Point”).

• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range

Break Point”).

A debugger, like the AVR Studio, may however use one or more of these resources for its inter-

nal purpose, leaving less flexibility to the end-user.

A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG

Instructions” on page 297.

The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the

OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system

to work. As a security feature, the On-chip debug system is disabled when either of the LB1 or

LB2 Lock bits are set. Otherwise, the On-chip debug system would have provided a back-door

into a secured device.

The AVR Studio enables the user to fully control execution of programs on an AVR device with

On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator.

AVR Studio^®supports source level execution of Assembly programs assembled with Atmel Cor-

poration’s AVR Assembler and C programs compiled with third party vendors’ compilers.

AVR Studio runs under Microsoft^®Windows^®95/98/2000/NT/XP.

For a full description of the AVR Studio, please refer to the AVR Studio User Guide. Only high-

lights are presented in this document.

All necessary execution commands are available in AVR Studio, both on source level and on

disassembly level. The user can execute the program, single step through the code either by

tracing into or stepping over functions, step out of functions, place the cursor on a statement and

execute until the statement is reached, stop the execution, and reset the execution target. In

addition, the user can have an unlimited number of code Break Points (using the BREAK

instruction) and up to two data memory Break Points, alternatively combined as a mask (range)

Break Point.

23.7 On-chip Debug Specific JTAG Instructions

The On-chip debug support is considered being private JTAG instructions, and distributed within

ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference.

23.7.1

23.7.2

23.7.3

23.7.4

PRIVATE0 (0x8)

Private JTAG instruction for accessing On-chip debug system.

PRIVATE1 (0x9)

Private JTAG instruction for accessing On-chip debug system.

PRIVATE2 (0xA)

Private JTAG instruction for accessing On-chip debug system.

PRIVATE3 (0xB)

Private JTAG instruction for accessing On-chip debug system.

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23.8 On-chip Debug Related Register in I/O Memory

23.8.1

On-chip Debug Register – OCDR

Bit

7

6

5

4

3

2

1

0

IDRD/OCDR7 OCDR6

OCDR5 OCDR4 OCDR3

OCDR2 OCDR1 OCDR0

OCDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The OCDR Register provides a communication channel from the running program in the micro-

controller to the debugger. The CPU can transfer a byte to the debugger by writing to this

location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate

to the debugger that the register has been written. When the CPU reads the OCDR Register the

7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the

IDRD bit when it has read the information.

In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR

Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables

access to the OCDR Register. In all other cases, the standard I/O location is accessed.

Refer to the debugger documentation for further information on how to use this register.

23.9 Using the JTAG Programming Capabilities

Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and

TDO. These are the only pins that need to be controlled/observed to perform JTAG program-

ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse

must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the

JTAG Test Access Port.

The JTAG programming capability supports:

• Flash programming and verifying.

• EEPROM programming and verifying.

• Fuse programming and verifying.

• Lock bit programming and verifying.

The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are

programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a

security feature that ensures no back-door exists for reading out the content of a secured

device.

The details on programming through the JTAG interface and programming specific JTAG

instructions are given in the section “JTAG Programming Overview” on page 351.

23.10 Bibliography

For more information about general Boundary-scan, the following literature can be consulted:

• IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan

Architecture, IEEE, 1993.

• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley,

1992.

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24. Boundary-scan IEEE 1149.1 (JTAG)

24.1 Features

• JTAG (IEEE std. 1149.1 compliant) Interface

• Boundary-scan Capabilities According to the JTAG Standard

• Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections

• Supports the Optional IDCODE Instruction

• Additional Public AVR_RESET Instruction to Reset the AVR

24.2 System Overview

The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-

tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by

the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to

drive values at their output pins, and observe the input values received from other devices. The

controller compares the received data with the expected result. In this way, Boundary-scan pro-

vides a mechanism for testing interconnections and integrity of components on Printed Circuits

Boards by using the four TAP signals only.

The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-

LOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be

used for testing the Printed Circuit Board. Initial scanning of the data register path will show the

ID-Code of the device, since IDCODE is the default JTAG instruction. It may be desirable to

have the AVR device in reset during test mode. If not reset, inputs to the device may be deter-

mined by the scan operations, and the internal software may be in an undetermined state when

exiting the test mode. Entering reset, the outputs of any port pin will instantly enter the high

impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction

can be issued to make the shortest possible scan chain through the device. The device can be

set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET

instruction with appropriate setting of the Reset Data Register.

The EXTEST instruction is used for sampling external pins and loading output pins with data.

The data from the output latch will be driven out on the pins as soon as the EXTEST instruction

is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for

setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST

instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the

external pins during normal operation of the part.

The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR must be

cleared to enable the JTAG Test Access Port.

When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher

than the internal chip frequency is possible. The chip clock is not required to run.

24.3 Data Registers

The data registers relevant for Boundary-scan operations are:

• Bypass Register

• Device Identification Register

• Reset Register

• Boundary-scan Chain

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24.3.1

24.3.2

Bypass Register

The Bypass Register consists of a single Shift Register stage. When the Bypass Register is

selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR

controller state. The Bypass Register may be used to shorten the scan chain on a system when

the other devices are to be tested.

Device Identification Register

Figure 24-1 shows the structure of the Device Identification Register.

Figure 24-1. The Format of the Device Identification Register

MSB

LSB

0

Bit

31

28 27

12 11

1

Device ID

Version

Part Number

Manufacturer ID

1

4 bits

16 bits

11 bits

1-bit

24.3.2.1

Version

Version is a 4-bit number identifying the revision of the component. The relevant version number

is shown in Table 24-1.

Table 24-1. JTAG Version Numbers

Version

JTAG Version Number (Hex)

AT90CAN32 revision A

AT90CAN64 revision A

AT90CAN128⁽¹⁾revision A

0x0

Note:

1. For information only.

24.3.2.2

Part Number

The part number is a 16-bit code identifying the component. The JTAG Part Number for

AT90CAN32/64 is listed in Table 24-2.

Table 24-2. AVR JTAG Part Number

Part Number

AT90CAN32

AT90CAN64

AT90CAN128⁽¹⁾

JTAG Part Number (Hex)

0x9581

0x9681

0x9781

Note:

1. For information only.

24.3.2.3

Manufacturer ID

The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID

for ATMEL is listed in Table 24-3.

Table 24-3. Manufacturer ID

Manufacturer

JTAG Manufacturer ID (Hex)

ATMEL

0x01F

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24.3.2.4

Device ID

The full Device ID is listed in Table 24-4 following the AT90CAN32/64 version.

Table 24-4. Device ID

Version

JTAG Device ID (Hex)

0x0958103F

AT90CAN32 revision A

AT90CAN64 revision A

AT90CAN128⁽¹⁾revision A

0x0968103F

0x0978103F

Note:

1. For information only.

24.3.3

Reset Register

The Reset Register is a test data register used to reset the part. Since the AVR tri-states Port

Pins when reset, the Reset Register can also replace the function of the unimplemented optional

JTAG instruction HIGHZ.

A high value in the Reset Register corresponds to pulling the external Reset low. The part is

reset as long as there is a high value present in the Reset Register. Depending on the fuse set-

tings for the clock options, the part will remain reset for a reset time-out period (refer to “System

Clock” on page 37) after releasing the Reset Register. The output from this data register is not

latched, so the reset will take place immediately, as shown in Figure 24-2.

Figure 24-2. Reset Register

From Other Internal and

Internal reset

To TDO

External Reset Sources

From TDI

D

Q

ClockDR • AVR_RESET

24.3.4

Boundary-scan Chain

The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-

ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connections.

See “Boundary-scan Chain” on page 303 for a complete description.

24.4 Boundary-scan Specific JTAG Instructions

The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG

instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not

implemented, but all outputs with tri-state capability can be set in high-impedant state by using

the AVR_RESET instruction, since the initial state for all port pins is tri-state.

As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

describes which data register is selected as path between TDI and TDO for each instruction.

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24.4.1

EXTEST (0x0)

Mandatory JTAG instruction for selecting the Boundary-scan Chain as data register for testing

circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output

Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip

connections, the interface between the analog and the digital logic is in the scan chain. The con-

tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-

Register is loaded with the EXTEST instruction.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Internal Scan Chain is shifted by the TCK input.

• Update-DR: Data from the scan chain is applied to output pins.

24.4.2

IDCODE (0x1)

Optional JTAG instruction selecting the 32 bit ID-Register as data register. The ID-Register con-

sists of a version number, a device number and the manufacturer code chosen by JEDEC. This

is the default instruction after power-up.

The active states are:

• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.

• Shift-DR: The IDCODE scan chain is shifted by the TCK input.

24.4.3

SAMPLE_PRELOAD (0x2)

Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the

input/output pins without affecting the system operation. However, the output latches are not

connected to the pins. The Boundary-scan Chain is selected as data register.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

• Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,

the output latches are not connected to the pins.

24.4.4

AVR_RESET (0xC)

The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or

releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit

Reset Register is selected as data register.

Note that the reset will be active as long as there is a logic “one” in the Reset Chain.

The output from this chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

24.4.5

BYPASS (0xF)

Mandatory JTAG instruction selecting the Bypass Register for data register.

The active states are:

• Capture-DR: Loads a logic “0” into the Bypass Register.

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• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

24.5 Boundary-scan Related Register in I/O Memory

24.5.1

MCU Control Register – MCUCR

The MCU Control Register contains control bits for general MCU functions.

Bit

7

6

–

5

–

4

3

–

2

–

1

IVSEL

R/W

0

IVCE

R/W

0

JTD

R/W

0

PUD

R/W

0

MCUCR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bits 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this

bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of

the JTAG interface, a timed sequence must be followed when changing this bit: The application

software must write this bit to the desired value twice within four cycles to change its value. Note

that this bit must not be altered when using the On-chip Debug system.

If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to

one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.

24.5.2

MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit

7

–

6

–

5

–

4

3

2

1

0

JTRF

R/W

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

Read/Write

Initial Value

R

0

R

0

R

0

See Bit Description

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

24.6 Boundary-scan Chain

The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-

tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connection.

24.6.1

Scanning the Digital Port Pins

Figure 24-3 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The

cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a

bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data –

ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are

not used in the following description

The Boundary-scan logic is not included in the figures in the datasheet. Figure 24-4 shows a

simple digital port pin as described in the section “I/O-Ports” on page 66. The Boundary-scan

details from Figure 24-3 replaces the dashed box in Figure 24-4.

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When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Reg-

ister value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output

Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor-

responds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 24-4 to make the

scan chain read the actual pin value. For Analog function, there is a direct connection from the

external pin to the analog circuit, and a scan chain is inserted on the interface between the digi-

tal logic and the analog circuitry.

Figure 24-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.

ShiftDR

To Next Cell

EXTEST

Vcc

Pullup Enable (PUE)

0

1

FF2

Q

LD2

0

1

D

Q

G

Output Control (OC)

FF1

D Q

LD1

0

1

0

1

D

G

Q

Output Data (OD)

0

1

FF0

D

LD0

0

1

0

1

Q

D

G

Q

Input Data (ID)

From Last Cell

ClockDR

UpdateDR

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Figure 24-4. General Port Pin Schematic Diagram

See Boundary-scan

Description for Details!

PUExn

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

OCxn

Q

D

Pxn

PORTxn

ODxn

Q _CLR

WPx

RRx

IDxn

RESET

SLEEP

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

CLK _I/O

PUD:

PULLUP DISABLE

WDx:

RDx:

WPx:

RRx:

RPx:

WRITE DDRx

PUExn:

OCxn:

ODxn:

IDxn:

PULLUP ENABLE for pin Pxn

OUTPUT CONTROL for pin Pxn

OUTPUT DATA to pin Pxn

INPUT DATA from pin Pxn

SLEEP CONTROL

READ DDRx

WRITE PORTx

READ PORTx REGISTER

READ PORTx PIN

I/O CLOCK

SLEEP:

CLK_I/O:

24.6.2

Boundary-scan and the Two-wire Interface

The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan-

chain; Two-wire Interface Enable – TWIEN. As shown in Figure 24-5, the TWIEN signal enables

a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general

scan cell as shown in Figure 24-9 is attached to the TWIEN signal.

Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan

support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in

the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-

scan.

2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to

drive contention.

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Figure 24-5. Additional Scan Signal for the Two-wire Interface

PUExn

OCxn

ODxn

Pxn

TWIEN

SRC

Slew-rate limited

IDxn

24.6.3

Scanning the RESET Pin

The RESET pin accepts 3V or 5V active low logic for standard reset operation, and 12V active

high logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 24-6

is inserted both for the 3V or 5V reset signal - RSTT, and the 12V reset signal - RSTHV.

Figure 24-6. Observe-only Cell for RESET pin

To

Cell

From System Pin

To System Logic

FF1

0

1

D

Q

From

ClockDR

24.6.4

Scanning the Clock Pins

The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-

tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and

Ceramic Resonator.

Figure 24-7 shows how each oscillator with external connection is supported in the scan chain.

The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock out-

put is attached to an observe-only cell. In addition to the main clock, the Timer2 Oscillator is

scanned in the same way. The output from the internal RC Oscillator is not scanned, as this

oscillator does not have external connections.

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Figure 24-7. Boundary-scan Cells for Oscillators and Clock Options

XTAL1 / TOSC1

XTAL2 / TOSC2

To

Oscillator

ShiftDR

EXTEST

ShiftDR

From Digital Logic

0

1

ENABLE

OUTPUT

To System Logic

0

1

FF1

D

Q

D

G

Q

0

1

D

Q

From

ClockDR

UpdateDR

From

ClockDR

Table 24-5 summaries the scan registers for the external clock pin XTAL1, oscillators with

XTAL1/XTAL2 connections as well as external Timer2 clock pin TOSC1 and 32kHz Timer2

Oscillator.

Table 24-5. Scan Signals for the Oscillators^(1)(2)(3)

Scanned Clock Line

Enable Signal

EXTCLKEN

OSCON

Scanned Clock Line

EXTCLK (XTAL1)

OSCCK

Clock Option

when not Used

External Main Clock

0

External Crystal

1

External Ceramic Resonator

OSC32EN

TOSKON

OSC32CK

TOSCK

Low Freq. External Crystal

32 kHz Timer2 Oscillator

1

Notes: 1. Do not enable more than one clock source as clock at a time.

2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between

the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is

preferred.

3. The main clock configuration is programmed by fuses. As a fuse is not changed run-time, the

main clock configuration is considered fixed for a given application. The user is advised to

scan the same clock option as to be used in the final system. The enable signals are sup-

ported in the scan chain because the system logic can disable clock options in sleep modes,

thereby disconnecting the Oscillator pins from the scan path if not provided.

24.6.5

Scanning the Analog Comparator

The relevant Comparator signals regarding Boundary-scan are shown in Figure 24-8. The

Boundary-scan cell from Figure 24-9 is attached to each of these signals. The signals are

described in Table 24-6.

The Comparator need not be used for pure connectivity testing, since all analog inputs are

shared with a digital port pin as well.

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Figure 24-8. Analog Comparator

BANDGAP

REFERENCE

ACBG

ACO

AC_IDLE

ACME

ADCEN

ADC MULTIPLEXER

OUTPUT

Figure 24-9. General Boundary-scan cell Used for Signals for Comparator and ADC

To

Cell

EXTEST

From Digital Logic/

From Analog Ciruitry

0

1

To Analog Circuitry/

To Digital Logic

0

1

D

Q

D

G

Q

From

ClockDR

UpdateDR

Table 24-6. Boundary-scan Signals for the Analog Comparator

Direction as

Seen from the

Comparator

Recommended

Input when Not

in Use

Output Values when

Recommended Inputs

are Used

Signal

Name

Description

Turns off Analog

Comparator when

true

Depends upon µC code

being executed

AC_IDLE

ACO

input

1

Will become input

to µC code being

executed

Analog Comparator

Output

output

0

Uses output signal

from ADC mux when

true

Depends upon µC code

being executed

ACME

ACBG

input

0

Bandgap Reference

enable

Depends upon µC code

being executed

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24.6.6

Scanning the ADC

Figure 24-10 shows a block diagram of the ADC with all relevant control and observe signals.

The Boundary-scan cell from Figure 24-9 is attached to each of these signals. The ADC need

not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin

as well.

Figure 24-10. Analog to Digital Converter

VCCREN

AREF

IREFEN

2.56V

ref

To Comparator

PASSEN

MUXEN_7

ADC_7

MUXEN_6

ADC_6

MUXEN_5

ADC_5

MUXEN_4

ADC_4

ADCBGEN

SCTEST

1.22V

ref

EXTCH

MUXEN_3

ADC_3

PRECH

AREF

DACOUT

COMP

MUXEN_2

ADC_2

DAC_9..0

ADCEN

+

-

10-bit DAC

MUXEN_1

ADC_1

G10

G20

MUXEN_0

ADC_0

ACTEN

GNDEN

+

NEGSEL_2

NEGSEL_1

NEGSEL_0

10x

-

20x

-

HOLD

ADC_2

ADC_1

ST

ACLK

AMPEN

ADC_0

The signals are described briefly in Table 24-7.

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Table 24-7. Boundary-scan Signals for the ADC⁽¹⁾

Direction

Output Values when

Recommended Inputs

are Used, and CPU is

not Using the ADC

Recommended

Input

when not in use

Signal

Name

as Seen

from the

ADC

Description

COMP

ACLK

Output

Comparator Output

0

Clock signal to gain

stages implemented as

Switch-cap filters

Input

0

Enable path from gain

stages to the comparator

ACTEN

Input

0

Enable Band-gap

reference as negative

input to comparator

ADCBGEN

Power-on signal to the

ADC

ADCEN

AMPEN

DAC_9

DAC_8

DAC_7

DAC_6

DAC_5

DAC_4

DAC_3

DAC_2

DAC_1

DAC_0

Input

0

1

0

1

0

Power-on signal to the

gain stages

Bit 9 of digital value to

DAC

Bit 8 of digital value to

DAC

Bit 7 of digital value to

DAC

Bit 6 of digital value to

DAC

Bit 5 of digital value to

DAC

Bit 4 of digital value to

DAC

Bit 3 of digital value to

DAC

Bit 2 of digital value to

DAC

Bit 1 of digital value to

DAC

Bit 0 of digital value to

DAC

Connect ADC channels 0

- 3 to by-pass path

EXTCH

Input

1

around gain stages

G10

G20

Input

Enable 10x gain

Enable 20x gain

0

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Table 24-7. Boundary-scan Signals for the ADC⁽¹⁾(Continued)

Direction

Output Values when

Recommended Inputs

are Used, and CPU is

Recommended

Input

when not in use

Signal

Name

as Seen

from the

ADC

Description

not Using the ADC

Ground the negative

input to comparator when

true

GNDEN

HOLD

Input

0

Sample & Hold signal.

Sample analog signal

when low. Hold signal

when high. If gain stages

are used, this signal

must go active when

ACLK is high.

1

Enables Band-gap

reference as AREF

signal to DAC

IREFEN

0

MUXEN_7

MUXEN_6

MUXEN_5

MUXEN_4

MUXEN_3

MUXEN_2

MUXEN_1

MUXEN_0

Input

Input Mux bit 7

Input Mux bit 6

Input Mux bit 5

Input Mux bit 4

Input Mux bit 3

Input Mux bit 2

Input Mux bit 1

Input Mux bit 0

0

1

0

1

Input Mux for negative

input for differential

signal, bit 2

NEGSEL_2 Input

NEGSEL_1 Input

NEGSEL_0 Input

0

Input Mux for negative

input for differential

signal, bit 1

Input Mux for negative

input for differential

signal, bit 0

Enable pass-gate of gain

stages.

PASSEN

PRECH

Input

1

Precharge output latch of

comparator. (Active low)

311

7538B–CAN–05/06

Table 24-7. Boundary-scan Signals for the ADC⁽¹⁾(Continued)

Direction

Output Values when

Recommended Inputs

are Used, and CPU is

not Using the ADC

Recommended

Input

when not in use

Signal

Name

as Seen

from the

ADC

Description

Switch-cap TEST

enable. Output from x10

gain stage send out to

Port Pin having ADC_4

SCTEST

Input

0

Output of gain stages will

settle faster if this signal

is high first two ACLK

periods after AMPEN

goes high.

ST

Input

0

Selects Vcc as the ACC

reference voltage.

VCCREN

Note:

1. Incorrect setting of the switches in Figure 24-10 will make signal contention and may damage

the part. There are several input choices to the S&H circuitry on the negative input of the out-

put comparator in Figure 24-10. Make sure only one path is selected from either one ADC pin,

Bandgap reference source, or Ground.

If the ADC is not to be used during scan, the recommended input values from Table 24-7 should

be used. The user is recommended not to use the Differential Gain stages during scan. Switch-

Cap based gain stages require fast operation and accurate timing which is difficult to obtain

when used in a scan chain. Details concerning operations of the differential gain stage is there-

fore not provided.

The AVR ADC is based on the analog circuitry shown in Figure 24-10 with a successive approx-

imation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is

usually to ensure that an applied analog voltage is measured within some limits. This can easily

be done without running a successive approximation algorithm: apply the lower limit on the digi-

tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit

on the digital DAC[9:0] lines, and verify the output from the comparator to be high.

The ADC need not be used for pure connectivity testing, since all analog inputs are shared with

a digital port pin as well.

When using the ADC, remember the following

• The port pin for the ADC channel in use must be configured to be an input with pull-up

disabled to avoid signal contention.

• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when

enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before

controlling/observing any ADC signal, or perform a dummy conversion before using the first

result.

• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal

low (Sample mode).

As an example, consider the task of verifying a 1.5V 5% input signal at ADC channel 3 when

the power supply is 5.0V and AREF is externally connected to V_CC.

The lower limit is: [ 1024 * 1.5V * 0.95 / 5V ] = 291 = 0x123

The upper limit is: [ 1024 * 1.5V * 1.05 / 5V ] = 323 = 0x143

312

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AT90CAN32/64

The recommended values from Table 24-7 are used unless other values are given in the algo-

rithm in Table 24-8. Only the DAC and port pin values of the Scan Chain are shown. The column

“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register

with the succeeding columns. The verification should be done on the data scanned out when

scanning in the data on the same row in the table.

Table 24-8. Algorithm for Using the ADC

PA3.

Pullup_

Enable

PA3.

Data

PA3.

Control

Step

Actions

ADCEN

DAC

MUXEN

HOLD

PRECH

SAMPLE_

PRELOAD

1

0x200

0x08

1

0

2

3

4

5

EXTEST

1

0x200

0x123

0x08

0

1

0

Verify the

COMP bit

scanned out

to be 0

6

1

0x200

0x08

1

0

7

1

0x200

0x143

0x08

0

1

0

8

9

10

Verify the

COMP bit

scanned out

to be 1

11

1

0x200

0x08

1

0

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-

quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at

least five times the number of scan bits divided by the maximum hold time, t_hold,max

24.7 AT90CAN32/64 Boundary-scan Order

Table 24-9 shows the Scan order between TDI and TDO when the Boundary-scan chain is

selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The

scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in

the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the

analog circuits, which constitute the most significant bits of the scan chain regardless of which

physical pin they are connected to. In Figure 24-3, PXn. Data corresponds to FF0, PXn. Control

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7538B–CAN–05/06

corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is

not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.

Table 24-9. AT90CAN32/64 Boundary-scan Order

Bit Number

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

Signal Name

AC_IDLE

ACO

Comment

Module

Comparator

ADC

ACME

AINBG

COMP

ACLK

ACTEN

PRIVATE_SIGNAL⁽¹⁾

ADCBGEN

ADCEN

AMPEN

DAC_9

DAC_8

DAC_7

DAC_6

DAC_5

DAC_4

DAC_3

DAC_2

DAC_1

DAC_0

EXTCH

G10

G20

GNDEN

HOLD

IREFEN

MUXEN_7

MUXEN_6

MUXEN_5

MUXEN_4

MUXEN_3

MUXEN_2

MUXEN_1

MUXEN_0

NEGSEL_2

314

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AT90CAN32/64

Table 24-9. AT90CAN32/64 Boundary-scan Order (Continued)

Bit Number

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

Signal Name

NEGSEL_1

NEGSEL_0

PASSEN

Comment

Module

ADC

PRECH

SCTEST

ST

VCCREN

PE0.Data

Port E

PE0.Control

PE0.Pullup_Enable

PE1.Data

PE1.Control

PE1.Pullup_Enable

PE2.Data

PE2.Control

PE2.Pullup_Enable

PE3.Data

PE3.Control

PE3.Pullup_Enable

PE4.Data

PE4.Control

PE4.Pullup_Enable

PE5.Data

PE5.Control

PE5.Pullup_Enable

PE6.Data

PE6.Control

PE6.Pullup_Enable

PE7.Data

PE7.Control

PE7.Pullup_Enable

PB0.Data

Port B

PB0.Control

PB0.Pullup_Enable

PB1.Data

PB1.Control

PB1.Pullup_Enable

PB2.Data

315

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Table 24-9. AT90CAN32/64 Boundary-scan Order (Continued)

Bit Number

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

Signal Name

PB2.Control

PB2.Pullup_Enable

PB3.Data

Comment

Module

Port B

PB3.Control

PB3.Pullup_Enable

PB4.Data

PB4.Control

PB4.Pullup_Enable

PB5.Data

PB5.Control

PB5.Pullup_Enable

PB6.Data

PB6.Control

PB6.Pullup_Enable

PB7.Data

PB7.Control

PB7.Pullup_Enable

PG3.Data

Port G

PG3.Control

PG3.Pullup_Enable

PG4.Data

PG4.Control

PG4.Pullup_Enable

PRIVATE_SIGNAL⁽¹⁾

RSTT

–

(Observe Only)

RESET Logic

RSTHV

EXTCLKEN

OSCON

Oscillators

98

OSC32EN

97

TOSKON

96

EXTCLK

(XTAL1)

95

OSCCK

94

OSC32CK

93

TOSK

92

PD0.Data

Port D

91

PD0.Control

PD0.Pullup_Enable

PD1.Data

90

89

316

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AT90CAN32/64

Table 24-9. AT90CAN32/64 Boundary-scan Order (Continued)

Bit Number

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

Signal Name

PD1.Control

Comment

Module

Port D

PD1.Pullup_Enable

PD2.Data

PD2.Control

PD2.Pullup_Enable

PD3.Data

PD3.Control

PD3.Pullup_Enable

PD4.Data

PD4.Control

PD4.Pullup_Enable

PD5.Data

PD5.Control

PD5.Pullup_Enable

PD6.Data

PD6.Control

PD6.Pullup_Enable

PD7.Data

PD7.Control

PD7.Pullup_Enable

PG0.Data

Port G

PG0.Control

PG0.Pullup_Enable

PG1.Data

PG1.Control

PG1.Pullup_Enable

PC0.Data

Port C

PC0.Control

PC0.Pullup_Enable

PC1.Data

PC1.Control

PC1.Pullup_Enable

PC2.Data

PC2.Control

PC2.Pullup_Enable

PC3.Data

PC3.Control

PC3.Pullup_Enable

317

7538B–CAN–05/06

Table 24-9. AT90CAN32/64 Boundary-scan Order (Continued)

Bit Number

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

Signal Name

PC4.Data

Comment

Module

Port C

PC4.Control

PC4.Pullup_Enable

PC5.Data

PC5.Control

PC5.Pullup_Enable

PC6.Data

PC6.Control

PC6.Pullup_Enable

PC7.Data

PC7.Control

PC7.Pullup_Enable

PG2.Data

Port G

Port A

PG2.Control

PG2.Pullup_Enable

PA7.Data

PA7.Control

PA7.Pullup_Enable

PA6.Data

PA6.Control

PA6.Pullup_Enable

PA5.Data

PA5.Control

PA5.Pullup_Enable

PA4.Data

PA4.Control

PA4.Pullup_Enable

PA3.Data

PA3.Control

PA3.Pullup_Enable

PA2.Data

PA2.Control

PA2.Pullup_Enable

PA1.Data

PA1.Control

PA1.Pullup_Enable

PA0.Data

PA0.Control

318

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AT90CAN32/64

Table 24-9. AT90CAN32/64 Boundary-scan Order (Continued)

Bit Number

Signal Name

PA0.Pullup_Enable

PF3.Data

Comment

Module

Port A

Port F

12

11

10

9

PF3.Control

PF3.Pullup_Enable

PF2.Data

8

7

PF2.Control

6

PF2.Pullup_Enable

PF1.Data

5

4

PF1.Control

3

PF1.Pullup_Enable

PF0.Data

2

1

PF0.Control

0

PF0.Pullup_Enable

Notes: 1. PRIVATE_SIGNAL should always be scanned-in as zero.

24.8 Boundary-scan Description Language Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in

a standard format used by automated test-generation software. The order and function of bits in

the Boundary-scan Data Register are included in this description. A BSDL file for

AT90CAN32/64 is available.

319

7538B–CAN–05/06

25. Boot Loader Support – Read-While-Write Self-Programming

The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for

downloading and uploading program code by the MCU itself. This feature allows flexible applica-

tion software updates controlled by the MCU using a Flash-resident Boot Loader program. The

Boot Loader program can use any available data interface and associated protocol to read code

and write (program) that code into the Flash memory, or read the code from the program mem-

ory. The program code within the Boot Loader section has the capability to write into the entire

Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it

can also erase itself from the code if the feature is not needed anymore. The size of the Boot

Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot

Lock bits which can be set independently. This gives the user a unique flexibility to select differ-

ent levels of protection.

25.1 Features

• Read-While-Write Self-Programming

• Flexible Boot Memory Size

• High Security (Separate Boot Lock Bits for a Flexible Protection)

• Separate Fuse to Select Reset Vector

• Optimized Page⁽¹⁾Size

• Code Efficient Algorithm

• Efficient Read-Modify-Write Support

Note:

1. A page is a section in the Flash consisting of several bytes (see Table 26-11 on page 340)

used during programming. The page organization does not affect normal operation.

25.2 Application and Boot Loader Flash Sections

The Flash memory is organized in two main sections, the Application section and the Boot

Loader section (see Figure 25-2). The size of the different sections is configured by the

BOOTSZ Fuses as shown in Table 25-6 on page 333 and Figure 25-2. These two sections can

have different level of protection since they have different sets of Lock bits.

25.2.1

25.2.2

AS - Application Section

The Application section is the section of the Flash that is used for storing the application code.

The protection level for the Application section can be selected by the application Boot Lock bits

(BLB02 and BLB01 bits), see Table 25-2 on page 324. The Application section can never store

any Boot Loader code since the SPM instruction is disabled when executed from the Application

section.

BLS – Boot Loader Section

While the Application section is used for storing the application code, the The Boot Loader soft-

ware must be located in the BLS since the SPM instruction can initiate a programming when

executing from the BLS only. The SPM instruction can access the entire Flash, including the

BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader

Lock bits (BLB12 and BLB11 bits), see Table 25-3 on page 324.

25.3 Read-While-Write and No Read-While-Write Flash Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-

ware update is dependent on which address that is being programmed. In addition to the two

320

AT90CAN32/64

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AT90CAN32/64

sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also

divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-

Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 25-

7 on page 333 and Figure 25-2 on page 323. The main difference between the two sections is:

• When erasing or writing a page located inside the RWW section, the NRWW section can be

read during the operation.

• When erasing or writing a page located inside the NRWW section, the CPU is halted during

the entire operation.

Note that the user software can never read any code that is located inside the RWW section dur-

ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which

section that is being programmed (erased or written), not which section that actually is being

read during a Boot Loader software update.

25.3.1

RWW – Read-While-Write Section

If a Boot Loader software update is programming a page inside the RWW section, it is possible

to read code from the Flash, but only code that is located in the NRWW section. During an on-

going programming, the software must ensure that the RWW section never is being read. If the

user software is trying to read code that is located inside the RWW section (i.e., by a

call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown

state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader sec-

tion. The Boot Loader section is always located in the NRWW section. The RWW Section Busy

bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read

as logical one as long as the RWW section is blocked for reading. After a programming is com-

pleted, the RWWSB must be cleared by software before reading code located in the RWW

section. See “Store Program Memory Control and Status Register – SPMCSR” on page 325. for

details on how to clear RWWSB.

25.3.2

NRWW – No Read-While-Write Section

The code located in the NRWW section can be read when the Boot Loader software is updating

a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU

is halted during the entire Page Erase or Page Write operation.

Table 25-1. Read-While-Write Features

Which Section Can

be Read During

Programming?

Which Section does the Z-pointer

Address During the Programming?

Is the CPU

Halted?

Read-While-Write

Supported?

RWW Section

NRWW Section

None

No

Yes

No

NRWW Section

Yes

321

7538B–CAN–05/06

Figure 25-1. Read-While-Write vs. No Read-While-Write

Read-While-Write

(RWW) Section

Z-pointer

Addresses NRWW

Section

Z-pointer

No Read-While-Write

(NRWW) Section

Addresses RWW

Section

CPU is Halted

During the Operation

Code Located in

NRWW Section

Can be Read During

the Operation

322

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 25-2. Memory Sections

Program Memory

BOOTSZ = ’10’

Program Memory

BOOTSZ = ’11’

0x0000

Application Flash Section

End RWW

Start NRWW

Application Flash Section

Boot Loader Flash Section

Application Flash Section

Boot Loader Flash Section

End Application

Start Boot Loader

Flashend

Start Boot Loader

Flashend

0x0000

Program Memory

BOOTSZ = ’01’

Program Memory

BOOTSZ = ’00’

0x0000

Application Flash Section

End RWW

End RWW, End Application

Start NRWW

Start NRWW, Start Boot Loader

Application Flash Section

Boot Loader Flash Section

End Application

Boot Loader Flash Section

Start Boot Loader

Flash end

Note:

The parameters in the figure above are given in Table 25-6 on page 333.

25.4 Boot Loader Lock Bits

If no Boot Loader capability is needed, the entire Flash is available for application code. The

Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives

the user a unique flexibility to select different levels of protection.

The user can select:

• To protect the entire Flash from a software update by the MCU.

• To protect only the Boot Loader Flash section from a software update by the MCU.

• To protect only the Application Flash section from a software update by the MCU.

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7538B–CAN–05/06

• Allow software update in the entire Flash.

See Table 25-2 and Table 25-3 for further details. The Boot Lock bits can be set in software and

in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command

only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash

memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not

control reading nor writing by LPM/SPM (Load Program Memory / Store Program Memory)

instructions, if it is attempted.

Table 25-2. Boot Lock Bit0 Protection Modes (Application Section)⁽¹⁾

Lock Bit

Mode

BLB02

BLB01

Protection

1

2

1

0

No restrictions for SPM or LPM accessing the Application section.

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and LPM

executing from the Boot Loader section is not allowed to read

from the Application section. If Interrupt Vectors are placed in the

Boot Loader section, interrupts are disabled while executing from

the Application section.

3

4

0

1

LPM executing from the Boot Loader section is not allowed to

read from the Application section. If Interrupt Vectors are placed

in the Boot Loader section, interrupts are disabled while executing

from the Application section.

Note:

1. “1” means unprogrammed, “0” means programmed

Table 25-3. Boot Lock Bit1 Protection Modes (Boot Loader Section)⁽¹⁾

Lock Bit

Mode

BLB12

BLB11

Protection

No restrictions for SPM or LPM accessing the Boot Loader

section.

1

2

1

0

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section, and LPM

executing from the Application section is not allowed to read from

the Boot Loader section. If Interrupt Vectors are placed in the

Application section, interrupts are disabled while executing from

the Boot Loader section.

3

4

0

LPM executing from the Application section is not allowed to read

from the Boot Loader section. If Interrupt Vectors are placed in the

Application section, interrupts are disabled while executing from

the Boot Loader section.

1

Note:

1. “1” means unprogrammed, “0” means programmed

25.5 Entering the Boot Loader Program

Entering the Boot Loader takes place by a jump or call from the application program. This may

be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively,

the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash

start address after a reset. In this case, the Boot Loader is started after a reset. After the applica-

tion code is loaded, the program can start executing the application code. Note that the fuses

cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is pro-

324

AT90CAN32/64

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AT90CAN32/64

grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be

changed through the serial or parallel programming interface.

Table 25-4. Boot Reset Fuse⁽¹⁾

BOOTRST

Reset Address

1

0

Reset Vector = Application Reset (address 0x0000)

Reset Vector = Boot Loader Reset (see Table 25-6 on page 333)

Note:

1. “1” means unprogrammed, “0” means programmed

25.5.1

Store Program Memory Control and Status Register – SPMCSR

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Boot Loader operations.

Bit

7

SPMIE

R/W

0

6

5

–

4

3

2

1

PGERS

R/W

0

SPMEN

R/W

0

RWWSB

RWWSRE BLBSET PGWRT

SPMCSR

Read/Write

Initial Value

R

0

R

0

R/W

0

R/W

0

R/W

0

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM

ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN

bit in the SPMCSR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-

ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section

cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a

Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be

cleared if a page load operation is initiated.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the AT90CAN32/64 and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section is

blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the

user software must wait until the programming is completed (SPMEN will be cleared). Then, if

the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while

the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is writ-

ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will

be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z-

pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock

bit set, or if no SPM instruction is executed within four clock cycles.

325

7538B–CAN–05/06

An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Reg-

ister, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the

destination register. See “Reading the Fuse and Lock Bits from Software” on page 329 for

details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Write, with the data stored in the temporary buffer. The page address is

taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit

will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four

clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is

addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The

data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,

or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire

Page Write operation if the NRWW section is addressed.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a spe-

cial meaning, see description above. If only SPMEN is written, the following SPM instruction will

store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of

the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,

or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write,

the SPMEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

25.6 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers

ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is

implementation dependent. Note that the RAMPZ register is only implemented when the pro-

gram space is larger than 64K bytes.

Bit

23

15

–

22

14

–

21

13

–

20

12

–

19

11

–

18

10

–

17

9

16

8

RAMPZ

ZH (R31)

ZL (R30)

–

RAMPZ0

Z15

Z7

7

Z14

Z6

6

Z13

Z5

5

Z12

Z4

4

Z11

Z3

3

Z10

Z2

2

Z9

Z1

1

Z8

Z0

0

Since the Flash is organized in pages (see Table 26-11 on page 340), the Program Counter can

be treated as having two different sections. One section, consisting of the least significant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is shown in Figure 25-3. Note that the page erase and page write operations are addressed

independently. Therefore it is of major importance that the Boot Loader software addresses the

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same page in both the page erase and page write operation. Once a programming operation is

initiated, the address is latched and the Z-pointer can be used for other operations.

The (E)LPM instruction use the Z-pointer to store the address. Since this instruction addresses

the Flash byte-by-byte, also bit Z0 of the Z-pointer is used.

Figure 25-3. Addressing the Flash During SPM⁽¹⁾

BIT 23

ZPCMSB

ZPAGEMSB

1

0

Z - POINTER

PCMSB

PAGEMSB

PROGRAM COUNTER

PCPAGE

PCWORD

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. The different variables used in Figure 25-3 are listed in Table 25-8 on page 334.

25.7 Self-Programming the Flash

The program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page

buffer is filled one word at a time using SPM and the buffer can be filled either before the Page

Erase command or between a Page Erase and a Page Write operation:

Alternative 1: fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2: fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

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If only a part of the page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,

the Boot Loader provides an effective Read-Modify-Write feature which allows the user software

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not possible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page address used in both the Page Erase and Page Write operation is addressing the

same page. See “Simple Assembly Code Example for a Boot Loader” on page 331 for an

assembly code example.

25.7.1

Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will

be ignored during this operation.

• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.

• Page Erase to the NRWW section: The CPU is halted during the operation.

25.7.2

Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each address without erasing the temporary buffer.

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

25.7.3

Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE. Other bits in the Z-pointer will be ignored during

this operation.

• Page Write to the RWW section: The NRWW section can be read during the Page Write.

• Page Write to the NRWW section: The CPU is halted during the operation.

25.7.4

Using the SPM Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the

SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling

the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should

be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is

blocked for reading. How to move the interrupts is described in “Interrupts” on page 60.

25.7.5

Consideration While Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving

Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the

entire Boot Loader, and further software updates might be impossible. If it is not necessary to

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change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to

protect the Boot Loader software from any internal software changes.

25.7.6

Prevent Reading the RWW Section During Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is always

blocked for reading. The user software itself must prevent that this section is addressed during

the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW

section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS

as described in “Interrupts” on page 60, or the interrupts must be disabled. Before addressing

the RWW section after the programming is completed, the user software must clear the

RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on

page 331 for an example.

25.7.7

Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR

and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits

are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft-

ware update by the MCU.

Bit

7

6

5

4

3

2

1

0

R0

1

BLB12

BLB11

BLB02

BLB01

1

See Table 25-2 and Table 25-3 for how the different settings of the Boot Loader bits affect the

Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an

SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.

The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to

load the Z-pointer with 0x0001 (same as used for reading the Lock bits). For future compatibility

it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When

programming the Lock bits the entire Flash can be read during the operation.

25.7.8

25.7.9

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruc-

tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR,

the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN

bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed

within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-

SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.

Bit

7

6

5

4

3

2

1

0

Rd (Z=0x0001)

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

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The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET

and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the

BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be

loaded in the destination register as shown below. Refer to Table 26-5 on page 337 for a

detailed description and mapping of the Fuse Low byte.

Bit

7

6

5

4

3

2

1

0

Rd (Z=0x0000)

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-

tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,

the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.

Refer to Table 26-4 on page 336 for detailed description and mapping of the Fuse High byte.

Bit

7

6

5

4

3

2

1

0

Rd (Z=0x0003)

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction

is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the

value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below.

Refer to Table 26-3 on page 336 for detailed description and mapping of the Extended Fuse

byte.

Bit

7

6

5

4

3

2

1

0

Rd (Z=0x0002)

–

EFB3

EFB2

EFB1

EFB0

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

25.7.10 Preventing Flash Corruption

During periods of low V_CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low.

• First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.

• Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for

executing instructions is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. If there is no need for a Boot Loader update in the system, program the Boot Loader

Lock bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating

voltage matches the detection level. If not, an external low V_CCreset protection circuit

can be used. If a reset occurs while a write operation is in progress, the write operation

will be completed provided that the power supply voltage is sufficient.

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3. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

25.7.11 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 25-5 shows the typical pro-

gramming time for Flash accesses from the CPU.

Table 25-5. SPM Programming Time

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

25.7.12 Simple Assembly Code Example for a Boot Loader

;- the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y-pointer

; the first data location in Flash is pointed to by the Z-pointer

;- error handling is not included

;- the routine must be placed inside the Boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during Self-Programming (Page Erase and Page Write).

;- registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcsrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;- it is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2

.org SMALLBOOTSTART

;PAGESIZEB is page size in BYTES, not words

Write_page:

; Page Erase

ldi spmcsrval, (1<<PGERS) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB)

;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld

r0, Y+

r1, Y+

ldi spmcsrval, (1<<SPMEN)

call Do_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2

brne Wrloop

;use subi for PAGESIZEB<=256

;restore pointer

; execute Page Write

subi ZL, low(PAGESIZEB)

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sbci ZH, high(PAGESIZEB)

;not required for PAGESIZEB<=256

ldi spmcsrval, (1<<PGWRT) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB)

;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB)

sbci YH, high(PAGESIZEB)

;restore pointer

Rdloop:

lpm r0, Z+

ld

r1, Y+

cpse r0, r1

jmp Error

sbiw loophi:looplo, 1

brne Rdloop

;use subi for PAGESIZEB<=256

; return to RWW section

; verify that RWW section is safe to read

Return:

in

temp1, SPMCSR

sbrs temp1, RWWSB

ret

; If RWWSB is set, the RWW section is not ready yet

; re-enable the RWW section

ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in

temp1, SPMCSR

sbrc temp1, SPMEN

rjmp Wait_spm

; input: spmcsrval determines SPM action

; disable interrupts if enabled, store status

in

temp2, SREG

cli

; check that no EEPROM write access is present

Wait_ee:

sbic EECR, EEWE

rjmp Wait_ee

; SPM timed sequence

out SPMCSR, spmcsrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

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25.7.13 Boot Loader Parameters

In Table 25-6 through Table 25-8, the parameters used in the description of the Self-Program-

ming are given.

Table 25-6. Boot Size Configuration (Word Addresses)⁽¹⁾

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

512 words

1024 words

2048 words

4096 words

512 words

1024 words

2048 words

4096 words

512 words

1024 words

2048 words

4

8

0x0000 - 0x3DFF

0x0000 - 0x3BFF

0x3E00 - 0x3FFF

0x3C00 - 0x3FFF

0x3800 - 0x3FFF

0x3000 - 0x3FFF

0x7E00 - 0x7FFF

0x7C00 - 0x7FFF

0x7800 - 0x7FFF

0x7000 - 0x7FFF

0xFE00 - 0xFFFF

0xFC00 - 0xFFFF

0xF800 - 0xFFFF

0x3DFF

0x3BFF

0x37FF

0x2FFF

0x7DFF

0x7BFF

0x77FF

0x6FFF

0xFDFF

0xFBFF

0xF7FF

0x3E00

0x3C00

0x3800

0x3000

0x7E00

0x7C00

0x7800

0x7000

0xFE00

0xFC00

0xF800

16 0x0000 - 0x37FF

32 0x0000 - 0x2FFF

4

8

0x0000 - 0x7DFF

0x0000 - 0x7BFF

16 0x0000 - 0x77FF

32 0x0000 - 0x6FFF

4

8

0x0000 - 0xFDFF

0x0000 - 0xFBFF

16 0x0000 - 0xF7FF

32 0x0000 - 0xEFFF

0

4096 words

0xF000 - 0xFFFF

0xEFFF

0xF000

Notes: 1. The different BOOTSZ Fuse configurations are shown in Figure 25-2

2. For information only.

Table 25-7. Read-While-Write Limit (Word Addresses)⁽¹⁾

Device

Section

Pages

96

Address

Read-While-Write section (RWW)

No Read-While-Write section (NRWW)

Read-While-Write section (RWW)

No Read-While-Write section (NRWW)

Read-While-Write section (RWW)

No Read-While-Write section (NRWW)

0x0000 - 0x2FFF

0x3000 - 0x3FFF

0x0000 - 0x6FFF

0x7000 - 0x7FFF

0x0000 - 0xEFFF

0xF000 - 0xFFFF

AT90CAN32

32

224

32

AT90CAN64

480

32

AT90CAN128⁽²⁾

Notes: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on page

321 and “RWW – Read-While-Write Section” on page 321.

2. For information only.

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Table 25-8. Explanation of Different Variables Used in Figure 25-3 on page 327 and the Mapping to the Z-Pointer⁽¹⁾

Corresponding

Description⁽²⁾

Z-value

PCMSB

13

6

Most significant bit in the program counter. (The program counter is 14 bits PC[13:0])

Most significant bit which is used to address the words within one page (128 words in a page

requires 7 bits PC [6:0]).

PAGEMSB

Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals

PCMSB + 1.

ZPCMSB

Z14

Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB

equals PAGEMSB + 1.

ZPAGEMSB

PCPAGE

Z7

PC[13:7]

PC[6:0]

14

Z14:Z7

Z7:Z1

Program counter page address: Page select, for Page Erase and Page Write.

Program counter word address: Word select, for filling temporary buffer (must be zero during

PAGE WRITE operation).

PCWORD

PCMSB

Most significant bit in the program counter. (The program counter is 15 bits PC[14:0])

Most significant bit which is used to address the words within one page (128 words in a page

requires 7 bits PC [6:0]).

PAGEMSB

6

Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals

PCMSB + 1.

ZPCMSB

Z15

Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB

equals PAGEMSB + 1.

ZPAGEMSB

PCPAGE

Z7

PC[14:7]

PC[6:0]

15

Z15:Z7

Z7:Z1

Program counter page address: Page select, for Page Erase and Page Write.

Program counter word address: Word select, for filling temporary buffer (must be zero during

PAGE WRITE operation).

PCWORD

PCMSB

Most significant bit in the program counter. (The program counter is 16 bits PC[15:0])

Most significant bit which is used to address the words within one page (128 words in a page

requires 7 bits PC [6:0]).

PAGEMSB

6

Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals

PCMSB + 1.

ZPCMSB

Z16⁽³⁾

Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB

equals PAGEMSB + 1.

ZPAGEMSB

PCPAGE

Z7

PC[15:7]

PC[6:0]

Z16⁽³⁾:Z7

Z7:Z1

Program counter page address: Page select, for Page Erase and Page Write.

Program counter word address: Word select, for filling temporary buffer (must be zero during

PAGE WRITE operation).

PCWORD

Notes: 1. See “Addressing the Flash During Self-Programming” on page 326 for details about the use of

Z-pointer during self-programming.

2. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.

3. The Z-register is only 16 bits wide. Bit 16 is located in RAMPZ register in I/O map.

4. For information only.

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26. Memory Programming

26.1 Program and Data Memory Lock Bits

The AT90CAN32/64 provides six Lock bits which can be left unprogrammed (“1”) or can be pro-

grammed (“0”) to obtain the additional features listed in Table 26-2. The Lock bits can only be

erased to “1” with the Chip Erase command.

Table 26-1. Lock Bit Byte⁽¹⁾

Lock Bit Byte

Bit No

Description

–

Default Value

7

6

5

4

3

2

1

0

1 (unprogrammed)

–

BLB12

BLB11

BLB02

BLB01

LB2

Boot Lock bit

Lock bit

LB1

Lock bit

Note:

Table 26-2. Lock Bit Protection Modes⁽¹⁾⁽²⁾

Memory Lock Bits Protection Type

1. “1” means unprogrammed, “0” means programmed.

LB Mode

LB2

LB1

1

No memory lock features enabled.

Further programming of the Flash and EEPROM is disabled in Parallel and

Serial Programming mode. The Fuse bits are locked in both Serial and

Parallel Programming mode.⁽¹⁾

2

1

0

Further programming and verification of the Flash and EEPROM is disabled

in Parallel and Serial Programming mode. The Boot Lock bits and Fuse bits

are locked in both Serial and Parallel Programming mode.⁽¹⁾

3

BLB0 Mode BLB02 BLB01

No restrictions for SPM (Store Program Memory) or LPM (Load Program

Memory) accessing the Application section.

1

2

1

0

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and LPM executing

from the Boot Loader section is not allowed to read from the Application

section. If Interrupt Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

3

4

0

1

LPM executing from the Boot Loader section is not allowed to read from the

Application section. If Interrupt Vectors are placed in the Boot Loader

section, interrupts are disabled while executing from the Application section.

BLB1 Mode BLB12 BLB11

1

No restrictions for SPM or LPM accessing the Boot Loader section.

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Table 26-2. Lock Bit Protection Modes⁽¹⁾⁽²⁾(Continued)

Memory Lock Bits

Protection Type

2

3

1

0

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section, and LPM executing

from the Application section is not allowed to read from the Boot Loader

section. If Interrupt Vectors are placed in the Application section, interrupts

are disabled while executing from the Boot Loader section.

0

LPM executing from the Application section is not allowed to read from the

Boot Loader section. If Interrupt Vectors are placed in the Application

section, interrupts are disabled while executing from the Boot Loader

section.

4

0

1

Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

26.2 Fuse Bits

The AT90CAN32/64 has three Fuse bytes. Table 26-3, Table 26-4 and Table 26-5 describe

briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that

the fuses are read as logical zero, “0”, if they are programmed.

Table 26-3. Extended Fuse Byte

Fuse Extended Byte

Bit No

Description

Default Value

–

7

6

5

4

3

2

1

0

–

1

–

1

–

1

–

1

BODLEVEL2⁽¹⁾

BODLEVEL1⁽¹⁾

BODLEVEL0⁽¹⁾

TA0SEL

Brown-out Detector trigger level

(Reserved for factory tests)

1 (unprogrammed)

Note:

1. See Table 8-2 on page 54 for BODLEVEL Fuse decoding.

Table 26-4. Fuse High Byte

Fuse High Byte

OCDEN⁽⁴⁾

Bit No

Description

Enable OCD

Enable JTAG

Default Value

7

6

1 (unprogrammed, OCD disabled)

0 (programmed, JTAG enabled)

JTAGEN⁽⁵⁾

Enable Serial Program and

Data Downloading

SPIEN⁽¹⁾

WDTON⁽³⁾

EESAVE

5

4

3

0 (programmed, SPI prog. enabled)

1 (unprogrammed)

Watchdog Timer always on

EEPROM memory is preserved

through the Chip Erase

1 (unprogrammed, EEPROM not preserved)

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Table 26-4. Fuse High Byte (Continued)

Fuse High Byte

Bit No

Description

Default Value

Select Boot Size⁽⁶⁾

(see Table 25-6 for details)

BOOTSZ1

2

0 (programmed)⁽²⁾

1 (unprogrammed)

Select Boot Size⁽⁶⁾

(see Table 25-6 for details)

BOOTSZ0

BOOTRST

1

0

Select Reset Vector⁽⁷⁾

(see Table 25-6 for details)

Notes: 1. The SPIEN Fuse is not accessible in serial programming mode.

2. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 25-6 on page 333

for details.

3. See “Watchdog Timer Control Register – WDTCR” on page 57 for details.

4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits

and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to

be running in all sleep modes. This may increase the power consumption.

5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This

to avoid static current at the TDO pin in the JTAG interface.

6. The boot sizes of all the AVR CAN microcontrollers are identical.

7. Due to the flash size, the boot reset address differs from one AVR CAN microcontroller to

another.

Table 26-5. Fuse Low Byte

Fuse Low Byte

CKDIV8⁽⁴⁾

CKOUT⁽³⁾

SUT1

Bit No

Description

Default Value

7

6

5

4

3

2

1

0

Divide clock by 8

Clock output

0 (programmed)

1 (unprogrammed)

1 (unprogrammed)⁽¹⁾

0 (programmed)⁽¹⁾

0 (programmed)⁽²⁾

1 (unprogrammed)⁽²⁾

0 (programmed)⁽²⁾

Select start-up time

Select Clock source

SUT0

CKSEL3

CKSEL2

CKSEL1

CKSEL0

Notes: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source.

See Table 6-8 on page 42 for details.

2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 6-1 on

page 38 for details.

3. The CKOUT Fuse allow the system clock to be output on Port PC7. See “Clock Output Buffer”

on page 43 for details.

4. See “System Clock Prescaler” on page 44 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if

Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.

26.2.1

Latching of Fuses

The fuse values are latched when the device enters programming mode and changes of the

fuse values will have no effect until the part leaves Programming mode. This does not apply to

the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on

Power-up in Normal mode.

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26.3 Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This

code can be read in both serial and parallel mode, also when the device is locked. The three

bytes reside in a separate address space.

Table 26-6. Signature Bytes

Device

Address

Value

0x1E

0x95

0x81

0x1E

0x96

0x81

0x1E

0x97

0x81

Signature Byte Description

0

1

2

0

1

2

0

1

2

Indicates manufactured by Atmel

Indicates 32 KB Flash memory

AT90CAN32

Indicates AT90CAN32 device when address 1 contains 0x95

Indicates manufactured by Atmel

Indicates 64 KB Flash memory

AT90CAN64

Indicates AT90CAN64 device when address 1 contains 0x96

Indicates manufactured by Atmel

AT90CAN128⁽¹⁾

Indicates 128 KB Flash memory

Indicates AT90CAN128 device when address 1 contains 0x97

Note:

1. For information only.

26.4 Calibration Byte

The AT90CAN32/64 has a byte calibration value for the internal RC Oscillator. This byte resides

in the high byte of address 0x000 in the signature address space. During reset, this byte is auto-

matically written into the OSCCAL Register to ensure correct frequency of the calibrated RC

Oscillator.

26.5 Parallel Programming Overview

This section describes how to parallel program and verify Flash Program memory, EEPROM

Data memory, Memory Lock bits, and Fuse bits in the AT90CAN32/64. Pulses are assumed to

be at least 250 ns unless otherwise noted.

26.5.1

Signal Names

In this section, some pins of the AT90CAN32/64 are referenced by signal names describing their

functionality during parallel programming, see Figure 26-1 and Table 26-7. Pins not described in

the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 26-9.

When pulsing WR or OE, the command loaded determines the action executed. The different

Commands are shown in Table 26-10.

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Figure 26-1. Parallel Programming

+2.7 - +5.5V

RDY/BSY

OE

PD1

PD2

PD3

PD4

PD5

PD6

PD7

VCC

+2.7 - +5.5V

WR

AVCC

BS1

XA0

XA1

PB7 - PB0

DATA

PAGEL

+12 V

BS2

RESET

PA0

XTAL1

GND

26.5.2

Pin Mapping

Table 26-7. Pin Name Mapping

Signal Name in

Pin Name

I/O Function

Programming Mode

0: Device is busy programming,

1: Device is ready for new command.

RDY/BSY

PD1

O

OE

WR

PD2

PD3

PD4

PD5

PD6

PD7

PA0

I

Output Enable (Active low).

I

Write Pulse (Active low).

BS1

I

Byte Select 1 (“0” selects low byte, “1” selects high byte).

XTAL Action Bit 0

XA0

I

XA1

I

XTAL Action Bit 1

PAGEL

BS2

I

Program Memory and EEPROM data Page Load.

Byte Select 2 (“0” selects low byte, “1” selects 2’nd high byte).

Bi-directional Data bus (Output when OE is low).

DATA

PB7-0

I/O

26.5.3

Commands

Table 26-8. Pin Values Used to Enter Programming Mode

PAGEL

XA1

Symbol

Value

Prog_enable[3]

Prog_enable[2]

Prog_enable[1]

Prog_enable[0]

0

XA0

BS1

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Table 26-9. XA1 and XA0 Coding

XA1

XA0

Action when XTAL1 is Pulsed

0

1

0

1

0

1

Load Flash or EEPROM Address (High or low address byte determined by BS1).

Load Data (High or Low data byte for Flash determined by BS1).

Load Command

No Action, Idle

Table 26-10. Command Byte Bit Coding

Command Byte

1000 0000

0100 0000

0010 0000

0001 0000

0001 0001

0000 1000

0000 0100

0000 0010

0000 0011

Command Executed

Chip Erase

Write Fuse bits

Write Lock bits

Write Flash

Write EEPROM

Read Signature bytes and Calibration byte

Read Fuse and Lock bits

Read Flash

Read EEPROM

26.5.4

Parameters

Table 26-11. No. of Words in a Page and No. of Pages in the Flash

Device

Flash Size

16K words

32K words

64K words

Page Size

128 words

PCWORD

PC[6:0]

No. of Pages

PCPAGE

PC[13:7]

PC[14:7]

PC[15:7]

PCMSB

AT90CAN32

AT90CAN64

AT90CAN128⁽¹⁾

128

256

512

13

14

15

PC[6:0]

Note:

1. For information only.

Table 26-12. No. of Words in a Page and No. of Pages in the EEPROM

Device

EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB

AT90CAN32

AT90CAN64

AT90CAN128⁽¹⁾

1K bytes

2K bytes

4K bytes

8 bytes

EEA[2:0]

128

256

512

EEA[9:3]

EEA[10:3]

EEA[11:3]

9

10

11

Note:

1. For information only.

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26.6 Parallel Programming

26.6.1

Enter Programming Mode

The following algorithm puts the device in parallel programming mode:

1. Apply 4.5 - 5.5V between V_CCand GND.

2. Set RESET to “0” and toggle XTAL1 at least six times.

3. Set the Prog_enable pins listed in Table 26-8 on page 339 to “0000” and wait at least

100 ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after

+12V has been applied to RESET, will cause the device to fail entering programming

mode.

5. Wait at least 50 µs before sending a new command.

26.6.2

Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory

locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes

reading.

26.6.3

Chip Erase

The Chip Erase will erase the Flash and EEPROM⁽¹⁾memories plus Lock bits. The Lock bits are

not reset until the program memory has been completely erased. The Fuse bits are not

changed. A Chip Erase must be performed before the Flash and/or EEPROM are

reprogrammed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

Note:

1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.

26.6.4

Programming the Flash

The Flash is organized in pages, see Table 26-11 on page 340. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory:

A. Load Command “Write Flash”

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1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte (0x00 - 0xFF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. This selects high data byte.

2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 26-3 for signal

waveforms)

F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.

While the lower bits in the address are mapped to words within the page, the higher bits

address the pages within the FLASH. This is illustrated in Figure 26-2 on page 343. Note that

if less than eight bits are required to address words in the page (pagesize < 256), the most

significant bit(s) in the address low byte are used to address the page when performing a

Page Write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

1. Give WR a negative pulse. This starts programming of the entire page of data.

RDY/BSY goes low.

2. Wait until RDY/BSY goes high (See Figure 26-3 for signal waveforms).

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

J. End Page Programming

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1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals

are reset.

Figure 26-2. Addressing the Flash Which is Organized in Pages⁽¹⁾

PCMSB

PAGEMSB

PROGRAM COUNTER

PCPAGE

PCWORD

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. PCPAGE and PCWORD are listed in Table 26-11 on page 340.

Figure 26-3. Programming the Flash Waveforms⁽¹⁾

F

A

B

C

D

E

B

C

D

E

G

H

0x10

ADDR. LOW

DATA LOW

DATA HIGH

ADDR. LOW

DATA LOW

DATA HIGH

ADDR. HIGH

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

Note:

1. “XX” is don’t care. The letters refer to the programming description above.

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26.6.5

Programming the EEPROM

The EEPROM is organized in pages, see Table 26-12 on page 340. When programming the

EEPROM, the program data is latched into a page buffer. This allows one page of data to be

programmed simultaneously. The programming algorithm for the EEPROM data memory is as

follows (refer to “Programming the Flash” on page 341 for details on Command, Address and

Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

5. E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page

1. Set BS1 to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY

goes low.

3. Wait until to RDY/BSY goes high before programming the next page (See Figure 26-4

for signal waveforms).

Figure 26-4. Programming the EEPROM Waveforms

K

A

G

B

C

E

B

C

E

L

0x11

ADDR. HIGH

ADDR. LOW

DATA

ADDR. LOW

DATA

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

26.6.6

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on

page 341 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

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26.6.7

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash”

on page 341 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5. Set OE to “1”.

26.6.8

Programming the Fuse Low Bits

The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash”

on page 341 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

26.6.9

Programming the Fuse High Bits

The algorithm for programming the Fuse High bits is as follows (refer to “Programming the

Flash” on page 341 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

26.6.10 Programming the Extended Fuse Bits

The algorithm for programming the Extended Fuse bits is as follows (refer to “Programming the

Flash” on page 341 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS2 to “0”. This selects low data byte.

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Figure 26-5. Programming the FUSES Waveforms

Write Fuse Low byte

Write Fuse high byte

Write Extended Fuse byte

C

A

C

A

C

A

0x40

DATA

XX

0x40

DATA

XX

0x40

DATA

XX

DATA

XA1

XA0

BS1

BS2

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

26.6.11 Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on

page 341 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed

(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any

External Programming mode.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

26.6.12 Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash”

on page 341 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be

read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be

read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now

be read at DATA (“0” means programmed).

5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at

DATA (“0” means programmed).

6. Set OE to “1”.

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Figure 26-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

0

1

0

1

Fuse Low Byte

Extended Fuse Byte

Lock Bits

0

1

DATA

BS2

BS1

Fuse High Byte

BS2

26.6.13 Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on

page 341 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA

4. Set OE to “1”.

.

26.6.14 Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on

page 341 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

26.7 SPI Serial Programming Overview

This section describes how to serial program and verify Flash Program memory, EEPROM Data

memory, Memory Lock bits, and Fuse bits in the AT90CAN32/64.

26.7.1

Signal Names

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). After RESET is set low, the Programming Enable instruction needs to be executed first

before program/erase operations can be executed. NOTE, in Table 26-13 on page 348, the pin

mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal

SPI interface. Note that throughout the description about Serial downloading, MOSI and MISO

are used to describe the serial data in and serial data out respectively. For AT90CAN32/64

these pins are mapped to PDI (PE0) and PDO (PE1).

347

7538B–CAN–05/06

Figure 26-7. Serial Programming and Verify⁽¹⁾

+2.7 - +5.5V

VCC

PDI

PDO

SCK

PE0

PE1

PB1

AVCC

XTAL1

RESET

GND

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck≥ 12 MHz

High: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck≥ 12 MHz

26.7.2

Pin Mapping

Table 26-13. Pin Mapping Serial Programming

Symbol

MOSI (PDI)

MISO (PDO)

SCK

Pins

PE0

PE1

PB1

I/O

Description

Serial Data in

Serial Data out

Serial Clock

I

O

I

26.7.3

Parameters

The Flash parameters are given in Table 26-11 on page 340 and the EEPROM parameters in

Table 26-12 on page 340.

26.8 SPI Serial Programming

When writing serial data to the AT90CAN32/64, data is clocked on the rising edge of SCK. When

reading data from the AT90CAN32/64, data is clocked on the falling edge of SCK.

To program and verify the AT90CAN32/64 in the serial programming mode, the following

sequence is recommended (See four byte instruction formats in Table 26-15

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AT90CAN32/64

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of syn-

chronization. When in sync. the second byte (0x53), will echo back when issuing the

third byte of the Programming Enable instruction. Whether the echo is correct or not, all

four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give

RESET a positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one byte at

a time by supplying the 7 LSB of the address and data together with the Load Program

Memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program Memory

Page is stored by loading the Write Program Memory Page instruction with the 9 MSB

of the address. If polling is not used, the user must wait at least t_{WD_FLASH}before issuing

the next page. (See Table 26-14.) Accessing the serial programming interface before

the Flash write operation completes can result in incorrect programming.

5. The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is

first automatically erased before new data is written. If polling is not used, the user must

wait at least t_{WD_EEPROM}before issuing the next byte. (See Table 26-14.) In a chip

erased device, no 0xFFs in the data file(s) need to be programmed.

6. Any memory location can be verified by using the Read instruction which returns the

content at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn V_CCpower off.

26.8.1

Data Polling Flash

When a page is being programmed into the Flash, reading an address location within the page

being programmed will give the value 0xFF. At the time the device is ready for a new page, the

programmed value will read correctly. This is used to determine when the next page can be writ-

ten. Note that the entire page is written simultaneously and any address within the page can be

used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming

this value, the user will have to wait for at least t_{WD_FLASH}before programming the next page. As

a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to

contain 0xFF, can be skipped. See Table 26-14 for t_{WD_FLASH}value.

26.8.2

Data Polling EEPROM

When a new byte has been written and is being programmed into EEPROM, reading the

address location being programmed will give the value 0xFF. At the time the device is ready for

a new byte, the programmed value will read correctly. This is used to determine when the next

byte can be written. This will not work for the value 0xFF, but the user should have the following

in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that

are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re-pro-

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grammed without chip erasing the device. In this case, data polling cannot be used for the value

0xFF, and the user will have to wait at least t_{WD_EEPROM}before programming the next byte. See

Table 26-14 for t_{WD_EEPROM}value.

Table 26-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

t_{WD_FUSE}

4.5 ms

9.0 ms

t_{WD_FLASH}

t_{WD_EEPROM}

t_{WD_ERASE}

Figure 26-8. Serial Programming Waveforms

SERIAL DATA INPUT

MSB

LSB

(MOSI-PDI)

SERIAL DATA OUTPUT

MSB

(MISO-PDO)

SERIAL CLOCK INPUT

(SCK)

Sample

Table 26-15. Serial Programming Instruction Set

Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, = data in, x = don’t care

Instruction Format⁽¹⁾

Instruction

Operation⁽¹⁾

Byte 1

Byte 2⁽²⁾

Byte 3

Byte4

Programming

Enable

Enable Serial Programming after RESET goes low.

Chip Erase EEPROM and Flash.

Chip Erase

Read

Program Memory

Read H (high or low) data o from Program memory at

word address a:b.

Write H (high or low) data to Program Memory page

at word address b. Data low byte must be loaded

before Data high byte is applied within the same

address.

Load

Program Memory

Page

Write

Program Memory

Page

Write Program Memory Page at address a:b.

Read

EEPROM Memory

Read data o from EEPROM memory at address a:b.

Write data to EEPROM memory at address a:b.

Write

EEPROM Memory

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Table 26-15. Serial Programming Instruction Set (Continued)

Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, = data in, x = don’t care

Instruction Format⁽¹⁾

Instruction

Operation⁽¹⁾

Byte 1

Byte 2⁽²⁾

Byte 3

Byte4

Load

EEPROM Memory

Page (page access)

Load data to EEPROM memory page buffer. After

data is loaded, program EEPROM page.

Write

EEPROM Memory

Page (page access)

Write EEPROM page at address a:b.

Read Lock bits. “0”=programmed, “1”=unprogrammed

See Table 26-1 on page 335 for details.

.

Read Lockbits

Write

Lock bits

Write Lock bits. Set bits = “0” to program Lock bits.

See Table 26-1 on page 335 for details.

Read

Signature Byte

Read Signature Byte o at address b.

Write

Fuse Low bits

Set bits = “0” to program, “1” to unprogram.

See Table 26-5 on page 337 for details.

Write

Fuse High bits

Set bits = “0” to program, “1” to unprogram.

See Table 26-4 on page 336 for details.

Write

Extended Fuse Bits

Set bits = “0” to program, “1” to unprogram.

See Table 26-3 on page 336 for details.

Read

Fuse Low bits

Read Fuse bits. “0”=programmed, “1”=unprogrammed

See Table 26-5 on page 337 for details.

.

Read Fuse High bits.

“0”=programmed, “1”=unprogrammed.

See Table 26-4 on page 336 for details.

Read

Fuse High bits

Read Extended Fuse bits.

“0”=programmed, “1”=unprogrammed.

See Table 26-3 on page 336 for details.

Read

Extended Fuse Bits

Read

Calibration Byte

Read Calibration Byte

If o = “1”, a programming operation is still busy. Wait

until this bit returns to “0” before applying another

command.

Poll RDY/BSY

Notes: 1. All bytes are represented by binary digits (0b...).

2. Address bits exceeding PCMSB and EEAMSB (see Table 26-11 on page 340 and Table 26-12 on page 340) are don’t care.

26.9 JTAG Programming Overview

Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,

TMS, TDI, and TDO. Control of the reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is

default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared.

Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be

cleared after two chip clocks, and the JTAG pins are available for programming. This provides a

means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys-

tem Programming via the JTAG interface. Note that this technique can not be used when using

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the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded-

icated for this purpose.

During programming the clock frequency of the TCK Input must be less than the maximum fre-

quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input

into a sufficiently low frequency.

As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.

26.9.1

Programming Specific JTAG Instructions

The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions

useful for programming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

describes which data register is selected as path between TDI and TDO for each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be

used as an idle state between JTAG sequences. The state machine sequence for changing the

instruction word is shown in Figure 26-9.

Figure 26-9. State Machine Sequence for Changing the Instruction Word

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

1

Capture-DR

Capture-IR

0

Shift-IR

1

Shift-DR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-DR

1

0

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

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26.9.1.1

AVR_RESET (0xC)

The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking

the device out from the Reset mode. The TAP controller is not reset by this instruction. The one

bit Reset Register is selected as data register. Note that the reset will be active as long as there

is a logic “one” in the Reset Chain. The output from this chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

26.9.1.2

PROG_ENABLE (0x4)

The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-

bit Programming Enable Register is selected as data register. The active states are the

following:

• Shift-DR: The programming enable signature is shifted into the data register.

• Update-DR: The programming enable signature is compared to the correct value, and

Programming mode is entered if the signature is valid.

26.9.1.3

PROG_COMMANDS (0x5)

The AVR specific public JTAG instruction for entering programming commands via the JTAG

port. The 15-bit Programming Command Register is selected as data register. The active states

are the following:

• Capture-DR: The result of the previous command is loaded into the data register.

• Shift-DR: The data register is shifted by the TCK input, shifting out the result of the previous

command and shifting in the new command.

• Update-DR: The programming command is applied to the Flash inputs

• Run-Test/Idle: One clock cycle is generated, executing the applied command (not always

required, see Table 26-16 below).

26.9.1.4

PROG_PAGELOAD (0x6)

The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.

An 8-bit Flash Data Byte Register is selected as the data register. This is physically the 8 LSBs

of the Programming Command Register. The active states are the following:

• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.

• Update-DR: The content of the Flash Data Byte Register is copied into a temporary register.

A write sequence is initiated that within 11 TCK cycles loads the content of the temporary

register into the Flash page buffer. The AVR automatically alternates between writing the low

and the high byte for each new Update-DR state, starting with the low byte for the first

Update-DR encountered after entering the PROG_PAGELOAD command. The Program

Counter is pre-incremented before writing the low byte, except for the first written byte. This

ensures that the first data is written to the address set up by PROG_COMMANDS, and

loading the last location in the page buffer does not make the program counter increment into

the next page.

26.9.1.5

PROG_PAGEREAD (0x7)

The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port.

An 8-bit Flash Data Byte Register is selected as the data register. This is physically the 8 LSBs

of the Programming Command Register. The active states are the following:

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• Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte

Register. The AVR automatically alternates between reading the low and the high byte for

each new Capture-DR state, starting with the low byte for the first Capture-DR encountered

after entering the PROG_PAGEREAD command. The Program Counter is post-incremented

after reading each high byte, including the first read byte. This ensures that the first data is

captured from the first address set up by PROG_COMMANDS, and reading the last location

in the page makes the program counter increment into the next page.

• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.

26.9.2

Data Registers

The data registers are selected by the JTAG instruction registers described in section “Program-

ming Specific JTAG Instructions” on page 352. The data registers relevant for programming

operations are:

• Reset Register

• Programming Enable Register

• Programming Command Register

• Flash Data Byte Register

26.9.2.1

Reset Register

The Reset Register is a Test Data Register used to reset the part during programming. It is

required to reset the part before entering Programming mode.

A high value in the Reset Register corresponds to pulling the external reset low. The part is reset

as long as there is a high value present in the Reset Register. Depending on the Fuse settings

for the clock options, the part will remain reset for a Reset Time-out period (refer to “Clock

Sources” on page 38) after releasing the Reset Register. The output from this data register is not

latched, so the reset will take place immediately, as shown in Figure 24-2 on page 301.

26.9.2.2

Programming Enable Register

The Programming Enable Register is a 16-bit register. The contents of this register is compared

to the programming enable signature, binary code 0b1010_0011_0111_0000. When the con-

tents of the register is equal to the programming enable signature, programming via the JTAG

port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when

leaving Programming mode.

Figure 26-10. Programming Enable Register

TDI

0xA370

D

Q

A

T

A

Programming Enable

=

ClockDR & PROG_ENABLE

TDO

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26.9.2.3

Programming Command Register

The Programming Command Register is a 15-bit register. This register is used to serially shift in

programming commands, and to serially shift out the result of the previous command, if any. The

JTAG Programming Instruction Set is shown in Table 26-16. The state sequence when shifting

in the programming commands is illustrated in Figure 26-12.

Figure 26-11. Programming Command Register

TDI

S

T

R

O

B

E

S

Flash

EEPROM

Fuses

Lock Bits

A

D

R

E

S

/

D

A

T

A

TDO

Table 26-16. JTAG Programming Instruction

Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, = data in, x = don’t care

Instruction

TDI Sequence⁽¹⁾⁽²⁾

TDO Sequence⁽¹⁾⁽²⁾

Notes

1a. Chip Erase

(4)

1b. Poll for Chip Erase Complete

2a. Enter Flash Write

(11)

2b. Load Address High Byte

2c. Load Address Low Byte

2d. Load Data Low Byte

2e. Load Data High Byte

(3)

2f. Latch Data

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Table 26-16. JTAG Programming Instruction (Continued)

Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, = data in, x = don’t care

Instruction

TDI Sequence⁽¹⁾⁽²⁾

TDO Sequence⁽¹⁾⁽²⁾

Notes

(3)

2g. Write Flash Page

(4)

2h. Poll for Page Write Complete

3a. Enter Flash Read

(11)

3b. Load Address High Byte

3c. Load Address Low Byte

3d. Read Data Low and High Byte

Low byte

High byte

4a. Enter EEPROM Write

4b. Load Address High Byte

4c. Load Address Low Byte

4d. Load Data Byte

(11)

(3)

4e. Latch Data

4f. Write EEPROM Page

(4)

4g. Poll for Page Write Complete

5a. Enter EEPROM Read

(11)

5b. Load Address High Byte

5c. Load Address Low Byte

5d. Read Data Byte

6a. Enter Fuse Write

(5)

(3)

6b. Load Data Low Byte⁽⁸⁾

6c. Write Fuse Extended Byte

(4)

(5)

6d. Poll for Fuse Write Complete

6e. Load Data Low Byte⁽⁹⁾

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Table 26-16. JTAG Programming Instruction (Continued)

Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, = data in, x = don’t care

Instruction

TDI Sequence⁽¹⁾⁽²⁾

TDO Sequence⁽¹⁾⁽²⁾

Notes

(3)

6f. Write Fuse High Byte

(4)

(5)

6g. Poll for Fuse Write Complete

6h. Load Data Low Byte⁽⁹⁾

xxxxxxx_xxxxxxxx

(3)

6i. Write Fuse Low Byte

(4)

(6)

6j. Poll for Fuse Write Complete

7a. Enter Lock Bit Write

7b. Load Data Byte⁽¹¹⁾

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(3)

(4)

7c. Write Lock Bits

7d. Poll for Lock Bit Write complete

8a. Enter Fuse/Lock Bit Read

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

8b. Read Extended Fuse Byte⁽⁸⁾

8c. Read Fuse High Byte⁽⁹⁾

8d. Read Fuse Low Byte⁽¹⁰⁾

8e. Read Lock Bits⁽¹¹⁾

xxxxxxx_oooooooo

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

xxxxxxx_xxxxxxxx

(7)

xxxxxxx_xxoooooo

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

Fuse Ext. byte

Fuse High byte

Fuse Low byte

Lock bits

8f. Read Fuses and Lock Bits

9a. Enter Signature Byte Read

9b. Load Address Byte

xxxxxxx_xxxxxxxx

9c. Read Signature Byte

xxxxxxx_oooooooo

10a. Enter Calibration Byte Read

xxxxxxx_xxxxxxxx

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Table 26-16. JTAG Programming Instruction (Continued)

Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, = data in, x = don’t care

Instruction

TDI Sequence⁽¹⁾⁽²⁾

TDO Sequence⁽¹⁾⁽²⁾

Notes

10b. Load Address Byte

xxxxxxx_xxxxxxxx

10c. Read Calibration Byte

xxxxxxx_oooooooo

xxxxxxx_xxxxxxxx

11a. Load No Operation Command

Notes: 1. Address bits exceeding PCMSB and EEAMSB (Table 26-11 and Table 26-12) are don’t care.

2. All TDI and TDO sequences are represented by binary digits (0b...).

3. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is

normally the case).

4. Repeat until o = “1”.

5. Set bits to “0” to program the corresponding Fuse, “1” to unprogram the Fuse.

6. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged.

7. “0” = programmed, “1” = unprogrammed.

8. The bit mapping for Fuses Extended byte is listed in Table 26-3 on page 336.

9. The bit mapping for Fuses High byte is listed in Table 26-4 on page 336.

10. The bit mapping for Fuses Low byte is listed in Table 26-5 on page 337.

11. The bit mapping for Lock bits byte is listed in Table 26-1 on page 335.

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Figure 26-12. State Machine Sequence for Changing/Reading the Data Word

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

1

Capture-DR

Capture-IR

0

Shift-DR

0

Shift-IR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-IR

1

Pause-DR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

26.9.2.4

Flash Data Byte Register

The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer

before executing Page Write, or to read out/verify the content of the Flash. A state machine sets

up the control signals to the Flash and senses the strobe signals from the Flash, thus only the

data words need to be shifted in/out.

The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8-bit temporary reg-

ister. During page load, the Update-DR state copies the content of the scan chain over to the

temporary register and initiates a write sequence that within 11 TCK cycles loads the content of

the temporary register into the Flash page buffer. The AVR automatically alternates between

writing the low and the high byte for each new Update-DR state, starting with the low byte for the

first Update-DR encountered after entering the PROG_PAGELOAD command. The Program

Counter is pre-incremented before writing the low byte, except for the first written byte. This

ensures that the first data is written to the address set up by PROG_COMMANDS, and loading

the last location in the page buffer does not make the Program Counter increment into the next

page.

During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte

Register during the Capture-DR state. The AVR automatically alternates between reading the

low and the high byte for each new Capture-DR state, starting with the low byte for the first Cap-

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ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is

post-incremented after reading each high byte, including the first read byte. This ensures that

the first data is captured from the first address set up by PROG_COMMANDS, and reading the

last location in the page makes the program counter increment into the next page.

Figure 26-13. Flash Data Byte Register

STROBES

State

Machine

ADDRESS

TDI

Flash

EEPROM

Fuses

Lock Bits

D

A

T

A

TDO

The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal

operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate

through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis-

ter with sufficient number of clock pulses to complete its operation transparently for the user.

However, if too few bits are shifted between each Update-DR state during page load, the TAP

controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at

least 11 TCK cycles between each Update-DR state.

26.9.3

Programming Algorithm

All references below of type “1a”, “1b”, and so on, refer to Table 26-16 on page 355.

26.9.3.1

Entering Programming Mode

1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.

2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Program-

ming Enable Register.

26.9.3.2

Leaving Programming Mode

1. Enter JTAG instruction PROG_COMMANDS.

2. Disable all programming instructions by using no operation instruction 11a.

3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the program-

ming Enable Register.

4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

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26.9.3.3

26.9.3.4

Performing Chip Erase

1. Enter JTAG instruction PROG_COMMANDS.

2. Start Chip Erase using programming instruction 1a.

3. Poll for Chip Erase complete using programming instruction 1b, or wait for t_{WLRH_CE}

(refer to Table 27-15 on page 381).

Programming the Flash

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load address High byte using programming instruction 2b.

4. Load address Low byte using programming instruction 2c.

5. Load data using programming instructions 2d, 2e and 2f.

6. Repeat steps 4 and 5 for all instruction words in the page.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for t_WLRH(refer

to ).

9. Repeat steps 3 to 7 until all data have been programmed.

A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to

Table 26-11 on page 340) is used to address within one page and must be written as 0.

4. Enter JTAG instruction PROG_PAGELOAD.

5. Load the entire page by shifting in all instruction words in the page byte-by-byte, start-

ing with the LSB of the first instruction in the page and ending with the MSB of the last

instruction in the page. Use Update-DR to copy the contents of the Flash Data Byte

Register into the Flash page location and to auto-increment the Program Counter

before each new word.

6. Enter JTAG instruction PROG_COMMANDS.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for t_WLRH(refer

to Table 27-15 on page 381).

9. Repeat steps 3 to 8 until all data have been programmed.

26.9.3.5

Reading the Flash

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load address using programming instructions 3b and 3c.

4. Read data using programming instruction 3d.

5. Repeat steps 3 and 4 until all data have been read.

A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to

Table 26-11 on page 340) is used to address within one page and must be written as 0.

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4. Enter JTAG instruction PROG_PAGEREAD.

5. Read the entire page (or Flash) by shifting out all instruction words in the page (or

Flash), starting with the LSB of the first instruction in the page (Flash) and ending with

the MSB of the last instruction in the page (Flash). The Capture-DR state both captures

the data from the Flash, and also auto-increments the program counter after each word

is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte

which is shifted out contains valid data.

6. Enter JTAG instruction PROG_COMMANDS.

7. Repeat steps 3 to 6 until all data have been read.

26.9.3.6

Programming the EEPROM

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM write using programming instruction 4a.

3. Load address High byte using programming instruction 4b.

4. Load address Low byte using programming instruction 4c.

5. Load data using programming instructions 4d and 4e.

6. Repeat steps 4 and 5 for all data bytes in the page.

7. Write the data using programming instruction 4f.

8. Poll for EEPROM write complete using programming instruction 4g, or wait for t_WLRH

(refer to Table 27-15 on page 381).

9. Repeat steps 3 to 8 until all data have been programmed.

Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM.

26.9.3.7

Reading the EEPROM

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM read using programming instruction 5a.

3. Load address using programming instructions 5b and 5c.

4. Read data using programming instruction 5d.

5. Repeat steps 3 and 4 until all data have been read.

Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM.

26.9.3.8

Programming the Fuses

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse write using programming instruction 6a.

3. Load data high byte using programming instructions 6b. A bit value of “0” will program

the corresponding fuse, a “1” will unprogram the fuse.

4. Write Fuse High byte using programming instruction 6c.

5. Poll for Fuse write complete using programming instruction 6d, or wait for t_WLRH(refer to

Table 27-15 on page 381).

6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a

“1” will unprogram the fuse.

7. Write Fuse low byte using programming instruction 6f.

8. Poll for Fuse write complete using programming instruction 6g, or wait for t_WLRH(refer to

Table 27-15 on page 381).

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26.9.3.9

Programming the Lock Bits

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Lock bit write using programming instruction 7a.

3. Load data using programming instructions 7b. A bit value of “0” will program the corre-

sponding lock bit, a “1” will leave the lock bit unchanged.

4. Write Lock bits using programming instruction 7c.

5. Poll for Lock bit write complete using programming instruction 7d, or wait for t_WLRH

(refer to Table 27-15 on page 381).

26.9.3.10

Reading the Fuses and Lock Bits

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse/Lock bit read using programming instruction 8a.

3. To read all Fuses and Lock bits, use programming instruction 8f.

To only read Extended Fuse byte, use programming instruction 8b.

To only read Fuse High byte, use programming instruction 8c.

To only read Fuse Low byte, use programming instruction 8d.

To only read Lock bits, use programming instruction 8e.

26.9.3.11

Reading the Signature Bytes

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Signature byte read using programming instruction 9a.

3. Load address 0x00 using programming instruction 9b.

4. Read first signature byte using programming instruction 9c.

5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third

signature bytes, respectively.

26.9.3.12

Reading the Calibration Byte

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Calibration byte read using programming instruction 10a.

3. Load address 0x00 using programming instruction 10b.

4. Read the calibration byte using programming instruction 10c.

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27. Electrical Characteristics ⁽¹⁾

27.1 Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Industrial Operating Temperature ...................– 40°C to +85°C

Storage Temperature ....................................– 65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ..............................– 0.5V to V_CC+0.5V

Voltage on RESET with respect to Ground....– 0.5V to +13.0V

Voltage on V_CCwith respect to Ground............. – 0.5V to 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins................................ 200.0 mA

Note:

1. Electrical Characteristics for this product have not yet been finalized. Please consider all values listed herein as preliminary

and non-contractual.

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27.2 DC Characteristics

T_A= -40°C to +85°C, V_CC= 2.7V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Except XTAL1 and

RESET pins

V_IL

Input Low Voltage

– 0.5

0.2 Vcc ⁽¹⁾

V

XTAL1 pin - External

Clock Selected

V_IL1

V_IL2

V_IH

Input Low Voltage

Input High Voltage

– 0.5

0.1 Vcc ⁽¹⁾

0.2 Vcc ⁽¹⁾

Vcc + 0.5

V

RESET pin

Except XTAL1 and

RESET pins

0.6 Vcc ⁽²⁾

XTAL1 pin - External

Clock Selected

V_IH1

V_IH2

V_OL

Input High Voltage

0.7 Vcc ⁽²⁾

Vcc + 0.5

V

RESET pin

0.85 Vcc ⁽²⁾

Output Low Voltage ⁽³⁾

(Ports A, B, C, D, E, F, G)

0.7

0.5

I_OL= 20 mA, V_CC= 5V

I

_OL= 10 mA, V_CC= 3V

I_OH= – 20 mA, V_CC= 5V

_OH= – 10 mA, V_CC= 3V

Output High Voltage ⁽⁴⁾

(Ports A, B, C, D, E, F, G)

4.2

2.4

V_OH

V

I

Input Leakage

Current I/O Pin

V_CC= 5.5V, pin low

(absolute value)

I_IL

1.0

µA

Input Leakage

Current I/O Pin

V_CC= 5.5V, pin high

(absolute value)

I_IH

R_RST

R_pu

Reset Pull-up Resistor

I/O Pin Pull-up Resistor

30

20

100

50

20

37

5.5

10.5

12

23

3

kΩ

8 MHz, V_CC= 5V

mA

µA

Power Supply Current

Active Mode

(external clock)

16 MHz, V_CC= 5V

4 MHz, V_CC= 3V

8 MHz, V_CC= 3V

8 MHz, V_CC= 5V

Power Supply Current

Idle Mode

(external clock)

16 MHz, V_CC= 5V

4 MHz, V_CC= 3V

I_CC

8 MHz, V_CC= 3V

7

WDT enabled, V_CC= 5V

WDT disabled, V_CC= 5V

WDT enabled, V_CC= 3V

WDT disabled, V_CC= 3V

V_CC= 5V

40

18

25

10

µA

Power Supply Current

Power-down Mode

µA

Analog Comparator

Input Offset Voltage

V_ACIO

1.0

8.0

20

mV

V

_in= V_CC/2

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T_A= -40°C to +85°C, V_CC= 2.7V to 5.5V (unless otherwise noted) (Continued)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Analog Comparator

Input Leakage Current

V_CC= 5V

I_ACLK

– 50

50

nA

V

_in= V_CC/2

Analog Comparator

Propagation Delay

Common Mode Vcc/2

V

_CC= 2.7V

170

180

ns

t_ACID

V

_CC= 5.0V

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low

2. “Min” means the lowest value where the pin is guaranteed to be read as high

3. Although each I/O port can sink more than the test conditions (20 mA at V_CC= 5V, 10 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

TQFP and QFN Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports A0 - A7, G2, C3 - C7 should not exceed 300 mA.

3] The sum of all IOL, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 150 mA.

4] The sum of all IOL, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 150 mA.

5] The sum of all IOL, for ports F0 - F7, should not exceed 200 mA.

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (-20 mA at V_CC= 5V, -10 mA at V_CC= 3V) under steady

state conditions (non-transient), the following must be observed:

TQFP and QFN Package:

1] The sum of all I_OH, for all ports, should not exceed -400 mA.

2] The sum of all I_OH, for ports A0 - A7, G2, C3 - C7 should not exceed -300 mA.

3] The sum of all I_OH, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 1-50 mA.

4] The sum of all I_OH, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed -150 mA.

5] The sum of all I_OH, for ports F0 - F7, should not exceed -200 mA.

If I_OHexceeds the test condition, V_OHmay exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

27.3 External Clock Drive Characteristics

Figure 27-1. External Clock Drive Waveforms

V_IH1

V_IL1

Table 27-1. External Clock Drive

V

_CC= 2.7 - 5.5V

V_CC= 4.5 - 5.5V

Symbol

Parameter

Units

Min.

Max.

Min.

0

Max.

1/t_CLCL

t_CLCL

Oscillator Frequency

Clock Period

0

8

16

MHz

ns

125

50

62.5

25

t_CHCX

High Time

ns

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Table 27-1. External Clock Drive (Continued)

V

_CC= 2.7 - 5.5V

V_CC= 4.5 - 5.5V

Units

Symbol

Parameter

Min.

50

Max.

Min.

Max.

t_CLCX

t_CLCH

t_CHCL

Low Time

Rise Time

Fall Time

25

ns

μs

1.6

0.5

Change in period from one clock cycle

to the next

Δt_CLCL

2

%

27.4 Maximum Speed vs. V_CC

Maximum frequency is depending on V_CC. As shown in Figure 27-2., the Maximum Frequency

vs. V_CCcurve is linear between 1.8V < V_CC< 4.5V. To calculate the maximum frequency at a

given voltage in this interval, use this equation:

a • (V Vx) + Fy

To calculate required voltage for a given frequency, use this equation:

b • (F Fy) + Vx

Table 27-2. Constants used to calculate maximum speed vs. V_CC

Voltage and Frequency range

a

b

Vx

Fy

2.7 < VCC < 4.5 or 8 < Frequency < 16

8/1.8

1.8/8

2.7

8

1,8

At 3 Volt, this gives:

• (3 2,7)

8

9,33

Thus, when V_CC= 3V, maximum frequency will be 9.33 MHz.

1,8

At 8 MHz this gives:

• (8 8) 2,7

2,7

8

Thus, a maximum frequency of 8 MHz requires V_CC= 2.7V.

Figure 27-2. Maximum Frequency vs. V_CC, AT90CAN32/64

Frequency

16 MHz

8 MHz

Safe Operating Area

Voltage

2.7V

4.5V

5.5V

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27.5 Two-wire Serial Interface Characteristics

Table 27-3 describes the requirements for devices connected to the Two-wire Serial Bus. The

AT90CAN32/64 Two-wire Serial Interface meets or exceeds these requirements under the noted

conditions.

Timing symbols refer to Figure 27-3.

Table 27-3. Two-wire Serial Bus Requirements

Symbol Parameter

Condition

Min

– 0.5

Max

0.3 Vcc

Vcc + 0.5

–

Units

Input Low-voltage

V

VIL

Input High-voltage

0.7 Vcc

0.05 Vcc ⁽²⁾

0

VIH

Vhys

(1)

Hysteresis of Schmitt Trigger Inputs

Output Low-voltage

3 mA sink current

0.4

VOL

20 + 0.1C_b

(1)

tr

Rise Time for both SDA and SCL

300

ns

(3)(2)

20 + 0.1C_b

Output Fall Time from V_IHminto V_ILmax

10 pF < C_b< 400 pF ⁽³⁾

0.1 V_CC< V_i< 0.9 V_CC

250

(1)

(3)(2)

tof

Spikes Suppressed by Input Filter

Input Current each I/O Pin

Capacitance for each I/O Pin

SCL Clock Frequency

0

– 10

–

50 ⁽²⁾

10

ns

µA

(1)

tSP

I_i

C_i⁽¹⁾

10

pF

f_SCL

f_CK⁽⁴⁾> max(16f_SCL, 250kHz) ⁽⁵⁾

0

400

kHz

0,4V

3mA

f_SCL≤ 100 kHz

1000ns

Ω

Rp

Value of Pull-up resistor

0,4V

3mA

f_SCL> 100 kHz

300ns

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz ⁽⁶⁾

f_SCL> 100 kHz ⁽⁷⁾

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

4.0

0.6

4.7

1.3

4.0

0.6

4.7

0.6

0

–

µs

ns

µs

t_HD;STA

Hold Time (repeated) START Condition

Low Period of the SCL Clock

–

t_LOW

–

t_HIGH

High period of the SCL clock

–

Set-up time for a repeated START

condition

t_SU;STA

t_HD;DAT

t_SU;DAT

–

3.45

0.9

–

Data hold time

0

250

100

4.0

0.6

Data setup time

–

t_SU;STO

Setup time for STOP condition

–

Bus free time between a STOP and

START condition

t_BUF

f_SCL≤ 100 kHz

4.7

–

µs

Notes: 1. In AT90CAN32/64, this parameter is characterized and not 100% tested.

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2. Required only for f_SCL> 100 kHz.

3. C_b= capacitance of one bus line in pF.

4. f_CK= CPU clock frequency

5. This requirement applies to all AT90CAN32/64 Two-wire Serial Interface operation. Other devices connected to the Two-

wire Serial Bus need only obey the general f_SCLrequirement.

6. The actual low period generated by the AT90CAN32/64 Two-wire Serial Interface is (1/f_SCL- 2/f_CK), thus f_CKmust be greater

than 6 MHz for the low time requirement to be strictly met at f_SCL= 100 kHz.

7. The actual low period generated by the AT90CAN32/64 Two-wire Serial Interface is (1/f_SCL- 2/f_CK), thus the low time require-

ment will not be strictly met for f_SCL> 308 kHz when f_CK= 8 MHz. Still, AT90CAN32/64 devices connected to the bus may

communicate at full speed (400 kHz) with other AT90CAN32/64 devices, as well as any other device with a proper t_LOW

acceptance margin.

Figure 27-3. Two-wire Serial Bus Timing

t

HIGH

t

r

of

t

LOW

SCL

SDA

t

HD;DAT

SU;STA

HD;STA

t

SU;DAT

t

SU;STO

t

BUF

27.6 SPI Timing Characteristics

See Figure 27-4 and Figure 27-5 for details.

Table 27-4. SPI Timing Parameters

Description

SCK period

SCK high/low

Rise/Fall time

Setup

Mode

Master

Slave

Min.

Typ.

Max.

1

2

See Table 17-4

50% duty cycle

3

3.6

10

4

5

Hold

10

ns

6

Out to SCK

SCK to out

SCK to out high

SS low to out

SCK period

SCK high/low ⁽¹⁾

Rise/Fall time

0.5 • t_sck

10

7

8

10

9

15

10

11

12

Slave

4 • t_ck

2 • t_ck

Slave

1.6

µs

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7538B–CAN–05/06

Table 27-4. SPI Timing Parameters (Continued)

Description

Setup

Mode

Slave

Min.

10

Typ.

Max.

13

14

15

16

17

18

Hold

t_ck

SCK to out

15

10

ns

SCK to SS high

SS high to tri-state

SS low to SCK

20

2 • t_ck

Note:

In SPI Programming mode the minimum SCK high/low period is:

- 2 t_CLCLfor f_CK< 12 MHz

- 3 t_CLCLfor f_CK>12 MHz

Figure 27-4. SPI Interface Timing Requirements (Master Mode)

SS

6

1

SCK

(CPOL = 0)

2

SCK

(CPOL = 1)

4

5

3

MISO

(Data Input)

MSB

...

LSB

7

8

MOSI

(Data Output)

MSB

...

LSB

Figure 27-5. SPI Interface Timing Requirements (Slave Mode)

18

SS

10

16

9

SCK

(CPOL = 0)

11

SCK

(CPOL = 1)

13

14

12

MOSI

(Data Input)

MSB

...

LSB

15

17

MISO

(Data Output)

MSB

...

LSB

X

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27.7 CAN Physical Layer Characteristics

Only pads dedicated to the CAN communication belong to the physical layer.

Table : CAN Physical Layer Characteristics ⁽¹⁾

Parameter

Condition

Min.

Max.

Units

Vcc=2.7 V

Load=20 pF

9

V

_OL/V_OH=V_CC/2

1

2

TxCAN output delay

Vcc=4.5 V

Load=20 pF

5.3

ns

V_OL/V_OH=V_CC/2

Vcc=2.7 V

1

(2)

9 + / fCLK

1

IO

V_IL/V_IH=V_CC/2

RxCAN input delay

Vcc=4.5 V

(2)

IO

7.2 + / fCLK

V_IL/V_IH=V_CC/2

Notes: 1. Characteristics for CAN physical layer have not yet been finalized.

2. Metastable immunity flip-flop.

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27.8 ADC Characteristics

Table 27-5. ADC Characteristics, Single Ended Channels

Symbol Parameter

Condition

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

Units

Resolution

Single Ended Conversion

10

Bits

V

_REF= 4V, Vcc = 4V

1.5

LSB

ADC clock = 200 kHz

Single Ended Conversion

V

_REF= 4V, Vcc = 4V

ADC clock = 1 MHz

Absolute accuracy

(Included INL, DNL,

Quantization Error, Gain and

Offset Error)

Single Ended Conversion

V

_REF= 4V, Vcc = 4V

1.5

LSB

ADC clock = 200 kHz

Noise Reduction Mode

Single Ended Conversion

V

_REF= 4V, Vcc = 4V

ADC clock = 1 MHz

Noise Reduction Mode

Single Ended Conversion

Integral Non-linearity (INL)

Differential Non-linearity (DNL)

Gain Error

V

_REF= 4V, Vcc = 4V

0.5

0.3

0

1

LSB

ADC clock = 200 kHz

Single Ended Conversion

V

ADC clock = 200 kHz

_REF= 4V, Vcc = 4V

1

Single Ended Conversion

V

ADC clock = 200 kHz

_REF= 4V, Vcc = 4V

– 2

+ 2

Single Ended Conversion

V

Offset Error

_REF= 4V, Vcc = 4V

1

ADC clock = 200 kHz

Clock Frequency

Free Running Conversion

50

65

1000

260

kHz

µs

V

Conversion Time

AV_CC

V_REF

V_IN

Analog Supply Voltage

External Reference Voltage

Input voltage

V_CC– 0.3 ⁽²⁾

V_CC+ 0.3 ⁽³⁾

2.0

AV_CC

V

GND

V_REF

V

Input bandwidth

38.5

2.56

32

kHz

V

V_INT

R_REF

R_AIN

Internal Voltage Reference

Reference Input Resistance

Analog Input Resistance

2.4

2.7

kΩ

MΩ

100

Notes: 1. Values are guidelines only.

2. Minimum for AV_CCis 2.7 V.

3. Maximum for AV_CCis 5.5 V

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Table 27-6. ADC Characteristics, Differential Channels

Symbol

Parameter

Condition

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

Units

Differential Conversion

Gain = 1x or 10x

8

Bits

Resolution

Differential Conversion

Gain = 200x

7

1

Bits

Gain = 1x, 10x or 200x

Absolute accuracy

V

_REF= 4V, Vcc = 5V

LSB

ADC clock = 50 - 200 kHz

Integral Non-linearity (INL)

(Accuracy after Calibration

for Offset and Gain Error)

Gain = 1x, 10x or 200x

V

_REF= 4V, Vcc = 5V

0.5

0

1

LSB

ADC clock = 50 - 200 kHz

Gain = 1x, 10x or 200x

Gain Error

– 2

– 1

+ 2

+ 1

Offset Error

V

_REF= 4V, Vcc = 5V

0

ADC clock = 50 - 200 kHz

Free Running Conversion

Clock Frequency

50

200

260

kHz

µs

V

Conversion Time

65

V_CC– 0.3 ⁽²⁾

2.0

AV_CC

V_REF

V_IN

Analog Supply Voltage

External Reference Voltage

Input voltage

V_CC+ 0.3 ⁽³⁾

AV_{CC - 0.5}

AV_CC

Differential Conversion

V

0

V

V_DIFF

Input Differential Voltage

ADC Conversion Output

Input bandwidth

–V_REF/Gain

–511

+V_REF/Gain

511

V

LSB

kHz

V

Differential Conversion

4

V_INT

R_REF

R_AIN

Internal Voltage Reference

Reference Input Resistance

Analog Input Resistance

2.4

2.56

32

2.7

kΩ

MΩ

100

Notes: 1. Values are guidelines only.

2. Minimum for AV_CCis 2.7 V.

3. Maximum for AV_CCis 5.5 V

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27.9 External Data Memory Characteristics

Table 27-7. External Data Memory Characteristics, V_CC= 4.5 - 5.5 Volts, No Wait-state

8 MHz Oscillator

Variable Oscillator

Symbol

Parameter

Unit

Min.

Max.

Min.

0.0

Max.

0

1

2

1/t_CLCL

t_LHLL

Oscillator Frequency

ALE Pulse Width

16

MHz

ns

115

1.0 t_CLCL– 10

0.5 t_CLCL– 5 ⁽¹⁾

t_AVLL

Address Valid A to ALE Low

57.5

ns

Address Hold After ALE Low,

write access

3a

3b

t_{LLAX_ST}

t_{LLAX_LD}

5

ns

Address Hold after ALE Low,

read access

5

4

t_AVLLC

t_AVRL

t_AVWL

t_LLWL

t_LLRL

Address Valid C to ALE Low

Address Valid to RD Low

Address Valid to WR Low

ALE Low to WR Low

ALE Low to RD Low

57.5

115

47.5

40

0.5 t_CLCL– 5 ⁽¹⁾

1.0 t_CLCL– 10

0.5 t_CLCL– 15 ⁽²⁾

40

ns

5

6

7

67.5

0.5 t_CLCL+ 5 ⁽²⁾

8

9

t_DVRH

t_RLDV

t_RHDX

t_RLRH

t_DVWL

t_WHDX

t_DVWH

t_WLWH

Data Setup to RD High

Read Low to Data Valid

Data Hold After RD High

RD Pulse Width

10

11

12

13

14

15

16

75

1.0 t_CLCL– 50

0

115

42.5

115

125

115

1.0 t_CLCL– 10

0.5 t_CLCL– 20 ⁽¹⁾

1.0 t_CLCL– 10

1.0 t_CLCL

Data Setup to WR Low

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

1.0 t_CLCL– 10

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 27-8. External Data Memory Characteristics, V_CC= 4.5 - 5.5 Volts, 1 Cycle Wait-state

8 MHz Oscillator

Variable Oscillator

Min. Max.

Symbol

Parameter

Unit

Min.

Max.

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

16

MHz

ns

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

200

2.0 t_CLCL– 50

240

2.0 t_CLCL– 10

2.0 t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

2.0 t_CLCL– 10

ns

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Table 27-9. External Data Memory Characteristics, V_CC= 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

8 MHz Oscillator

Variable Oscillator

Min. Max.

Symbol

Parameter

Unit

Min.

Max.

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

16

MHz

ns

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

325

3.0 t_CLCL– 50

365

375

365

3.0 t_CLCL– 10

3.0 t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

3.0 t_CLCL– 10

ns

Table 27-10. External Data Memory Characteristics, V_CC= 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

8 MHz Oscillator

Variable Oscillator

Symbol

Parameter

Unit

Min.

Max.

Min.

Max.

16

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

MHz

ns

10 t_RLDV

12 t_RLRH

14 t_WHDX

15 t_DVWH

16 t_WLWH

200

3.0 t_CLCL– 50

365

240

375

365

3.0 t_CLCL– 10

2.0 t_CLCL– 10

3.0 t_CLCL

ns

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

ns

3.0 t_CLCL– 10

ns

Table 27-11. External Data Memory Characteristics, V_CC= 2.7 - 5.5 Volts, No Wait-state

4 MHz Oscillator

Variable Oscillator

Symbol

Parameter

Unit

Min.

Max.

Min.

0.0

Max.

0

1

2

1/t_CLCL

t_LHLL

Oscillator Frequency

ALE Pulse Width

16

MHz

ns

235

115

t_CLCL– 15

0.5 t_CLCL– 10 ⁽¹⁾

t_AVLL

Address Valid A to ALE Low

ns

Address Hold After ALE Low,

write access

3a t_{LLAX_ST}

3b t_{LLAX_LD}

5

ns

Address Hold after ALE Low,

read access

5

4

5

6

7

8

9

t_AVLLC

t_AVRL

t_AVWL

t_LLWL

t_LLRL

Address Valid C to ALE Low

Address Valid to RD Low

Address Valid to WR Low

ALE Low to WR Low

115

235

115

45

0.5 t_CLCL– 10 ⁽¹⁾

1.0 t_CLCL– 15

0.5 t_CLCL– 10 ⁽²⁾

45

ns

130

0.5 t_CLCL+ 5 ⁽²⁾

ALE Low to RD Low

t_DVRH

Data Setup to RD High

Read Low to Data Valid

10 t_RLDV

190

1.0 t_CLCL– 60

375

7538B–CAN–05/06

Table 27-11. External Data Memory Characteristics, V_CC= 2.7 - 5.5 Volts, No Wait-state (Continued)

4 MHz Oscillator

Min. Max.

Variable Oscillator

Min. Max.

Symbol

Parameter

Unit

11

t_RHDX

Data Hold After RD High

RD Pulse Width

0

ns

12 t_RLRH

13 t_DVWL

14 t_WHDX

15 t_DVWH

16 t_WLWH

235

105

235

250

235

1.0 t_CLCL– 15

0.5 t_CLCL– 20 ⁽¹⁾

1.0 t_CLCL– 15

1.0 t_CLCL

Data Setup to WR Low

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

1.0 t_CLCL– 15

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 27-12. External Data Memory Characteristics, V_CC= 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1

4 MHz Oscillator

Variable Oscillator

Min. Max.

Symbol

Parameter

Unit

Min.

Max.

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

8

MHz

ns

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

440

2.0 t_CLCL– 60

485

500

485

2.0 t_CLCL– 15

2.0 t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

2.0 t_CLCL– 15

ns

Table 27-13. External Data Memory Characteristics, V_CC= 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

4 MHz Oscillator

Variable Oscillator

Symbol

Parameter

Unit

Min.

Max.

Min.

Max.

8

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

MHz

ns

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

690

3.0 t_CLCL– 60

735

750

735

3.0 t_CLCL– 15

3.0 t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

3.0 t_CLCL– 15

ns

Table 27-14. External Data Memory Characteristics, V_CC= 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

4 MHz Oscillator

Variable Oscillator

Symbol

Parameter

Unit

Min.

Max.

Min.

Max.

8

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

MHz

ns

10 t_RLDV

12 t_RLRH

690

3.0 t_CLCL– 60

735

3.0 t_CLCL– 15

ns

376

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Table 27-14. External Data Memory Characteristics, V_CC= 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1 (Continued)

4 MHz Oscillator

Min. Max.

Variable Oscillator

Symbol

Parameter

Unit

Min.

Max.

14 t_WHDX

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

485

750

735

2.0 t_CLCL– 15

3.0 t_CLCL

ns

15 t_DVWH

16 t_WLWH

3.0 t_CLCL– 15

Figure 27-6. External Memory Timing (SRWn1 = 0, SRWn0 = 0)

T1

T2

T3

T4

System Clock (CLK_CPU

)

1

ALE

4

2

7

A15:8 Prev. addr.

Address

15

3a

13

DA7:0 Prev. data

Address

6

XX

Data

16

14

WR

3b

9

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

377

7538B–CAN–05/06

Figure 27-7. External Memory Timing (SRWn1 = 0, SRWn0 = 1)

T1

T2

T3

T4

T5

System Clock (CLK_CPU

)

1

ALE

4

2

7

A15:8 Prev. addr.

Address

15

3a

13

Data

16

DA7:0 Prev. data

Address

6

XX

14

WR

3b

9

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

Figure 27-8. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

T1

T2

T3

T4

T5

T6

System Clock (CLK_CPU

)

1

ALE

4

2

7

Address

15

A15:8 Prev. addr.

3a

13

DA7:0 Prev. data

Address

6

XX

Data

16

14

WR

9

3b

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

378

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 27-9. External Memory Timing (SRWn1 = 1, SRWn0 = 1)⁽¹⁾

T6

T1

T2

T3

T4

T5

T7

System Clock (CLK_CPU

)

1

ALE

4

2

7

Address

15

A15:8 Prev. addr.

3a

13

DA7:0 Prev. data

Address

6

XX

Data

16

14

WR

9

3b

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

Note:

1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the

RAM (internal or external).

27.10 Parallel Programming Characteristics

Figure 27-10. Parallel Programming Timing, Including some General Timing Requirements

t_XLWL

t_XLDX

t_XHXL

XTAL1

t_DVXH

Data & Contol

(DATA, XA0/1, BS1, BS2)

t_BVPH

t_PLBXt_BVWL

t_WLBX

PAGEL

t_PHPL

t_WLWH

WR

t_PLWL

WLRL

RDY/BSY

t_WLRH

379

7538B–CAN–05/06

Figure 27-11. Parallel Programming Timing, Loading Sequence with Timing Requirements⁽¹⁾

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLPH

t_XLXH

t_PLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 27-10 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to

loading operation.

Figure 27-12. Parallel Programming Timing, Reading Sequence (within the Same Page) with

Timing Requirements⁽¹⁾

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLOL

XTAL1

BS1

t_BVDV

t_OLDV

OE

t_OHDZ

ADDR1 (Low Byte)

DATA (High Byte)

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

XA0

XA1

380

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Note:

1. The timing requirements shown in Figure 27-10 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to

reading operation.

Table 27-15. Parallel Programming Characteristics, V_CC= 5V 10%

Symbol

V_PP

Parameter

Min.

Typ.

Max.

12.5

250

Units

V

Programming Enable Voltage

Programming Enable Current

Data and Control Valid before XTAL1 High

XTAL1 Low to XTAL1 High

XTAL1 Pulse Width High

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

11.5

I_PP

μA

ns

μs

ms

ns

t_DVXH

t_XLXH

67

200

150

67

0

t_XHXL

t_XLDX

t_XLWL

t_XLPH

XTAL1 Low to PAGEL high

PAGEL low to XTAL1 high

BS1 Valid before PAGEL High

PAGEL Pulse Width High

BS1 Hold after PAGEL Low

BS2/1 Hold after WR Low

PAGEL Low to WR Low

0

t_PLXH

150

67

150

67

150

0

t_BVPH

t_PHPL

t_PLBX

t_WLBX

t_PLWL

t_BVWL

t_WLWH

t_WLRL

t_WLRH

t_{WLRH_CE}

t_XLOL

BS1 Valid to WR Low

WR Pulse Width Low

WR Low to RDY/BSY Low

WR Low to RDY/BSY High⁽¹⁾

WR Low to RDY/BSY High for Chip Erase⁽²⁾

XTAL1 Low to OE Low

1

5

3.7

7.5

0

10

t_BVDV

t_OLDV

t_OHDZ

Notes: 1.

BS1 Valid to DATA valid

0

250

OE Low to DATA Valid

OE High to DATA Tri-stated

t

_WLRHis valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits

commands.

2. t_{WLRH_CE}is valid for the Chip Erase command.

381

7538B–CAN–05/06

28. Decoupling Capacitors

The operating frequency (i.e. system clock) of the processor determines in 95% of cases the

value needed for microcontroller decoupling capacitors.

The hypotheses used as first evaluation for decoupling capacitors are:

• The operating frequency (fop) supplies itself the maximum peak levels of noise. The main

peaks are located at fop and 2 • fop.

• An SMC capacitor connected to 2 micro-vias on a PCB has the following characteristics:

– 1.5 nH from the connection of the capacitor to the PCB,

– 1.5 nH from the capacitor intrinsic inductance.

Figure 28-1. Capacitor description

1.5 nH

0.75 nH

Capacitor

PCB

According to the operating frequency of the product, the decoupling capacitances are chosen

considering the frequencies to filter, fop and 2 • fop.

The relation between frequencies to cut and decoupling characteristics are defined by:

1

and

f

2 • f

2Π

1

2

where:

– L: the inductance equivalent to the global inductance on the Vcc/Gnd lines.

– C₁& C₂: decoupling capacitors (C₁= 4 • C₂).

Then, in normalized value range, the decoupling capacitors become:

Table 28-1. Decoupling Capacitors vs. Frequency

f_op, operating frequency

C₁

C₂

16 MHz

12 MHz

10 MHz

8 MHz

6 MHz

4 MHz

33 nF

56 nF

82 nF

120 nF

220 nF

560 nF

10 nF

15 nF

22 nF

33 nF

56 nF

120 nF

These decoupling capacitors must to be implemented as close as possible to each pair of power

supply pins:

– 21-22 and 52-53 for logic sub-system,

– 64-63 for analogic sub-system.

Nevertheless, a bulk capacitor of 10-47 µF is also needed on the power distribution network of

the PCB, near the power source.

For further information, please refer to Application Notes AVR040 “EMC Design Considerations“

and AVR042 “Hardware Design Considerations“ on the Atmel web site.

382

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

29. AT90CAN32/64 Typical Characteristics

• The following charts show typical behavior. These figures are not tested during

manufacturing. All current consumption measurements are performed with all I/O pins

configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail

output is used as clock source.

• The power consumption in Power-down mode is independent of clock selection.

• The current consumption is a function of several factors such as: operating voltage, operating

frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient

temperature. The dominating factors are operating voltage and frequency.

• The current drawn from capacitive loaded pins may be estimated (for one pin) as C_L*V_CC*f

where C_L= load capacitance, V_CC= operating voltage and f = average switching frequency of

I/O pin.

• The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to

function properly at frequencies higher than the ordering code indicates.

• The difference between current consumption in Power-down mode with Watchdog Timer

enabled and Power-down mode with Watchdog Timer disabled represents the differential

current drawn by the Watchdog Timer.

29.1 Active Supply Current

Figure 29-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLYCURRENT vs. FREQUENCY(25°C, 0.1 - 1 MHz)

3

2.5

2

5.50V

5.00V

4.50V

4.00V

3.30V

3.00V

2.70V

1.5

1

0.5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

383

7538B–CAN–05/06

Figure 29-2. Active Supply Current vs. Frequency (1 - 16 MHz)

ACTIVE SUPPLYCURRENT vs. FREQUENCY(25°C, 1 - 16 MHz)

40

35

30

25

20

15

10

5

5.50V

5.00V

4.50V

4.00V

3.30V

3.00V

2.70V

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

Frequency (MHz)

Figure 29-3. Active Supply Current vs. Vcc (Internal RC Oscillator 8 MHz)

ACTIVE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 8 MHz)

20

18

16

14

12

10

8

85°C

25°C

-40°C

6

4

2

0

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

384

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 29-4. Active Supply Current vs. Vcc (Internal RC Oscillator 1 MHz)

ACTIVE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 1 MHz)

3

2.5

2

85°C

25°C

-40°C

1.5

1

0.5

0

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Figure 29-5. Active Supply Current vs. Vcc (32 kHz Watch Crystal)

ACTIVE SUPPLYCURRENT vs. Vcc (32 kHz Watch Crystal)

140

120

100

80

25°C

60

40

20

0

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

385

7538B–CAN–05/06

29.2 Idle Supply Current

Figure 29-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY(25°C, 0.1 - 1 MHz)

1.6

1.4

1.2

1

5.50V

5.00V

4.50V

4.00V

3.30V

3.00V

2.70V

0.8

0.6

0.4

0.2

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 29-7. Idle Supply Current vs. Frequency (1 - 16 MHz)

IDLE SUPPLYCURRENT vs. FREQUENCY(25°C, 1 - 16 MHz)

25

20

15

10

5

5.50V

5.00V

4.50V

4.00V

3.30V

3.00V

2.70V

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

Frequency (MHz)

386

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 29-8. Idle Supply Current vs. Vcc (Internal RC Oscillator 8 MHz)

IDLE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 8 MHz)

14

12

10

8

85°C

25°C

-40°C

6

4

2

0

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Figure 29-9. Idle Supply Current vs. Vcc (Internal RC Oscillator 1 MHz)

IDLE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 1 MHz)

1.8

1.6

1.4

1.2

1

85°C

25°C

-40°C

0.8

0.6

0.4

0.2

0

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

387

7538B–CAN–05/06

Figure 29-10. Idle Supply Current vs. Vcc (32 kHz Watch Crystal)

IDLE SUPPLY CURRENT vs. Vcc (32 KHz Watch Crystal)

60

50

40

30

20

10

0

25°C

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

29.3 Power-down Supply Current

Figure 29-11. Power-down Supply Current vs. Vcc (Watchdog Timer Disabled)

POWER-DOWN SUPPLY CURRENT vs. Vcc (Watchdog Timer Disabled)

9

8

7

6

5

4

3

2

1

0

85°C

25°C

-40°C

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

388

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 29-12. Power-down Supply Current vs. Vcc (Watchdog Timer Enabled)

POWER-DOWN SUPPLY CURRENT vs. Vcc (Watchdog Timer Enabled)

25

22.5

20

17.5

15

85°C

25°C

-40°C

12.5

10

7.5

5

2.5

0

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

29.4 Power-save Supply Current

Figure 29-13. Power-save Supply Current vs. Vcc (Watchdog Timer Disabled)

POWER-SAVE SUPPLY CURRENT vs. Vcc (Watchdog Timer Disabled)

25

22.5

20

17.5

15

12.5

10

25°C

7.5

5

2.5

0

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

389

7538B–CAN–05/06

29.5 Standby Supply Current

Figure 29-14. Power-save Supply Current vs. Vcc (25°C, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. Vcc (25°C, Watchdog Timer Disabled)

0.2

0.18

0.16

0.14

0.12

0.1

6 MHZ Xtal

4 MHZ Res

2 MHZ Xtal

2 MHZ Res

0.08

0.06

0.04

0.02

0

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

29.6 Pin Pull-up

Figure 29-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (Vcc = 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (Vcc = 5V)

0

-20

-40

-60

85°C

25°C

-40°C

-80

-100

-120

-140

-160

0

1

2

3

4

5

6

IO

V

(V)

390

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 29-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (Vcc = 2.7V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (Vcc = 2.7V)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

85°C

25°C

-40°C

0

0.5

1

1.5

2

2.5

3

IO

V

(V)

Figure 29-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (Vcc = 5V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (Vcc = 5V)

0

-20

-40

85°C

25°C

-40°C

-60

-80

-100

-120

0

1

2

3

4

5

6

RESET

V

(V)

391

7538B–CAN–05/06

Figure 29-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (Vcc = 2.7V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (Vcc = 2.7V)

0

-10

-20

-30

-40

-50

-60

-70

85°C

25°C

-40°C

0

0.5

1

1.5

2

2.5

3

RESET

V

(V)

29.7 Pin Driver Strength

Figure 29-19. I/O Pin Source Current vs. Output Voltage (Vcc = 5V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE (Vcc = 5V)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

85°C

25°C

-40°C

2.5

3

3.5

4

4.5

5

OH

V

(V)

392

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 29-20. I/O Pin Source Current vs. Output Voltage (Vcc = 2.7V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE (Vcc = 2.7V)

0

-5

-10

-15

-20

-25

-30

85°C

25°C

-40°C

0.5

1

1.5

2

2.5

3

OH

V

(V)

Figure 29-21. I/O Pin Sink Current vs. Output Voltage (Vcc = 5V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE (Vcc = 5V)

90

80

70

60

50

40

30

20

10

0

85°C

25°C

-40°C

0

0.5

1

1.5

2

2.5

OL

V

(V)

393

7538B–CAN–05/06

Figure 29-22. I/O Pin Sink Current vs. Output Voltage (Vcc = 2.7V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE (Vcc = 2.7V)

35

30

25

20

15

10

5

85°C

25°C

-40°C

0

0.5

1

1.5

2

2.5

OL

V

(V)

29.8 Pin Thresholds and Hysteresis

Figure 29-23. I/O Input Threshold Voltage vs. Vcc (V_IH, I/O Pin Read as “1”)

I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (VIH, I/O PIN READ AS "1")

2

1.75

1.5

85°C

1.25

1

25°C

-40°C

0.75

0.5

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

394

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 1. I/O Input Threshold Voltage vs. Vcc (V_IL, I/O Pin Read as “0”)

I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (VIL, I/O PIN READ AS "0")

2

1.75

1.5

85°C

25°C

-40°C

1.25

1

0.75

0.5

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Figure 2. I/O Input Hysteresis vs. Vcc

I/O PIN INPUT HYSTERESIS vs. VCC

0.6

0.5

0.4

0.3

0.2

0.1

0

85°C

25°C

-40°C

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

395

7538B–CAN–05/06

29.9 BOD Thresholds and Analog Comparator Offset

Figure 29-24. BOD Thresholds vs. Temperature (BOD level is 4.1V)

BOD THRESHOLDS vs. TEMPERATURE (BOD level is 4.1V)

4.4

4.2

4

Rising Vcc

Falling Vcc

3.8

3.6

3.4

-60

-40

-20

0

20

40

60

80

100

Temp (°C)

Figure 29-25. BOD Thresholds vs. Temperature (BOD level is 2.7V)

BOD THRESHOLDS vs. TEMPERATURE (BOD level is 2.7V)

3

2.8

2.6

2.4

2.2

2

Rising Vcc

Falling Vcc

-60

-40

-20

0

20

40

60

80

100

Temp (°C)

396

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 29-26. Bandgap Voltage vs. Operating Voltage

BANDGAP VOLTAGE vs. OPERATING VOLTAGE

1.14

1.13

1.12

1.11

1.1

85°C

25°C

-40°C

1.09

1.08

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Figure 29-27. Analog Comparator Offset vs. Common Mode Voltage (Vcc = 5V)

ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE (Vcc = 5V)

0.012

0.01

0.008

0.006

0.004

0.002

0

85°C

25°C

-40°C

-0.002

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

Common Voltage Mode (V)

397

7538B–CAN–05/06

29.10 Internal Oscillator Speed

Figure 29-28. Watchdog Oscillator Frequency vs. Operating Voltage

WATCHDOG OSCILLATOR FREQUENCY vs. VCC

1200

1150

1100

1050

1000

950

85°C

25°C

-40°C

900

850

800

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Figure 29-29. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 8MHz RC OSCILLATOR FREQUENCYvs. TEMPERATURE

8.8

8.6

8.4

8.2

8

2.7V

4.0V

5.5V

7.8

7.6

7.4

7.2

-60

-40

-20

0

20

40

60

80

100

Temp (°C)

398

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 29-30. Calibrated 8 MHz RC Oscillator Frequency vs. Operating Voltage

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC

10

9.5

9

8.5

8

85°C

25°C

-40°C

7.5

7

6.5

6

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Figure 29-31. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value

CALIBRATED 8MHz RC OSCILLATOR FREQUENCYvs. OSCCAL VALUE

16

15

14

13

12

11

10

9

85°C

25°C

-40°C

8

7

6

5

4

0

16

32

48

64

80

96

112

128

OSCCAL Value

399

7538B–CAN–05/06

29.11 Current Consumption of Peripheral Units

Figure 29-32. Brownout Detector Current vs. Operating Voltage

BROWNOUT DETECTOR CURRENT vs. Vcc

35

30

25

20

15

10

5

85°C

25°C

-40°C

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Figure 29-33. ADC Current vs. Operating Voltage (ADC at 1 MHz)

ADC CURRENT vs. Vcc (ADC at 1 MHz)

300

250

200

150

100

50

85°C

25°C

-40°C

0

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

400

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 29-34. AREF External Reference Current vs. Operating Voltage

AREF EXTERNAL REFERENCE CURRENT vs. Vcc

200

180

160

140

120

100

80

85°C

25°C

-40°C

60

40

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Figure 29-35. Analog Comparator Current vs. Operating Voltage

ANALOG COMPARATOR CURRENT vs. Vcc

120

100

80

60

40

20

0

85°C

25°C

-40°C

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

401

7538B–CAN–05/06

Figure 29-36. Programming Current vs. Operating Voltage

PROGRAMMING CURRENT vs. Vcc

25

20

15

10

5

85°C

25°C

-40°C

0

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

29.12 Current Consumption in Reset and Reset Pulse Width

Figure 29-37. Reset Supply Current vs. Operating Voltage (0.1 - 1.0 MHz)

(Excluding Current Through the Reset Pull-up)

RESET SUPPLY CURRENT vs. FREQUENCY (25°C, 0.1 - 1 MHz)

(EXCLUDING CURRENT THROUGH THE RESET PULL-UP)

0.25

0.2

0.15

0.1

5.50V

5.00V

4.50V

4.00V

3.30V

3.00V

2.70V

0.05

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

402

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Figure 29-38. Reset Supply Current vs. Operating Voltage (1 - 16 MHz)

(Excluding Current Through the Reset Pull-up)

RESET SUPPLY CURRENT vs. FREQUENCY (1 - 16 MHz)

(EXCLUDING CURRENT THROUGH THE RESET PULL-UP)

3.5

3

5.50V

5.00V

4.50V

4.00V

3.30V

3.00V

2.70V

2.5

2

1.5

1

0.5

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

Frequency (MHz)

Figure 29-39. Minimum Reset Pulse Width vs. Operating Voltage

MINIMUM RESET PULSE WIDTH vs. Vcc

1500

1250

1000

750

500

250

0

85°C

25°C

-40°C

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

403

7538B–CAN–05/06

30. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

(0xBF)

Reserved

CANMSG

CANSTMH

CANSTML

CANIDM1

CANIDM2

CANIDM3

CANIDM4

CANIDT1

CANIDT2

CANIDT3

CANIDT4

CANCDMOB

CANSTMOB

CANPAGE

CANHPMOB

CANREC

CANTEC

CANTTCH

CANTTCL

CANTIMH

CANTIML

CANTCON

CANBT3

CANBT2

CANBT1

CANSIT1

CANSIT2

CANIE1

MSG 7

TIMSTM15

TIMSTM7

IDMSK28

IDMSK20

IDMSK12

MSG 6

TIMSTM14

TIMSTM6

IDMSK27

IDMSK19

IDMSK11

MSG 5

TIMSTM13

TIMSTM5

IDMSK26

IDMSK18

IDMSK10

MSG 4

TIMSTM12

TIMSTM4

IDMSK25

IDMSK17

MSG 3

TIMSTM11

TIMSTM3

IDMSK24

IDMSK16

MSG 2

TIMSTM10

TIMSTM2

IDMSK23

IDMSK15

MSG 1

TIMSTM9

TIMSTM1

IDMSK22

IDMSK14

MSG 0

TIMSTM8

TIMSTM0

IDMSK21

IDMSK13

page 265

page 264

page 263

page 262

page 261

page 260

page 259

page 258

page 257

page 256

page 255

page 254

page 253

page 252

page 251

IDMSK

9

1

IDMSK

8

0

IDMSK

7

IDMSK

6

IDMSK5

IDMSK

4

IDMSK

3

IDMSK

2

IDMSK

RTRMSK

IDT23

–

IDEMSK

IDT21

IDT28

IDT20

IDT12

IDT27

IDT19

IDT11

IDT26

IDT18

IDT10

IDT25

IDT17

IDT24

IDT16

IDT22

IDT14

IDT15

IDT13

IDT

9

1

IDT

8

0

IDT

7

IDT

6

IDT5

IDT4

IDT3

IDT

2

RTRTAG

DLC2

RB1TAG

DLC1

RB0TAG

DLC0

CONMOB1

DLCW

MOBNB3

HPMOB3

REC7

TEC7

TIMTTC15

TIMTTC7

CANTIM15

CANTIM7

TPRSC7

–

CONMOB0

TXOK

RPLV

RXOK

IDE

BERR

DLC3

SERR

CERR

FERR

AERR

MOBNB2

HPMOB2

REC6

MOBNB1

HPMOB1

REC5

MOBNB0

HPMOB0

REC4

AINC

INDX2

INDX1

INDX0

CGP0

CGP3

CGP2

CGP1

REC3

REC2

REC1

REC0

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

TEC0

TIMTTC14

TIMTTC6

CANTIM14

CANTIM6

TPRSC6

PHS22

TIMTTC13

TIMTTC5

CANTIM13

CANTIM5

TPRSC5

PHS21

SJW0

TIMTTC12

TIMTTC4

CANTIM12

CANTIM4

TPRSC4

PHS20

–

TIMTTC11

TIMTTC3

CANTIM11

CANTIM3

TPRSC3

PHS12

PRS2

TIMTTC10

TIMTTC2

CANTIM10

CANTIM2

TPRSC2

PHS11

PRS1

TIMTTC9

TIMTTC1

CANTIM9

CANTIM1

TRPSC1

PHS10

PRS0

TIMTTC8

TIMTTC0

CANTIM8

CANTIM0

TPRSC0

SMP

–

SJW1

–

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

–

SIT14

SIT13

SIT12

SIT11

SIT10

SIT9

SIT8

SIT7

SIT6

SIT5

SIT4

SIT3

SIT2

SIT1

SIT0

–

IEMOB14

IEMOB6

ENMOB14

ENMOB6

ENBOFF

BOFFIT

OVRG

IEMOB13

IEMOB5

ENMOB13

ENMOB5

ENRX

IEMOB12

IEMOB4

ENMOB12

ENMOB4

ENTX

IEMOB11

IEMOB3

ENMOB11

ENMOB3

ENERR

SERG

IEMOB10

IEMOB2

ENMOB10

ENMOB2

ENBX

IEMOB9

IEMOB1

ENMOB9

ENMOB1

ENERG

FERG

IEMOB8

IEMOB0

ENMOB8

ENMOB0

ENOVRT

AERG

CANIE2

IEMOB7

–

CANEN1

CANEN2

CANGIE

ENMOB7

ENIT

CANGIT

CANIT

–

OVRTIM

–

BXOK

CERG

CANGSTA

CANGCON

Reserved

UDR1

TXBSY

SYNTTC

RXBSY

LISTEN

ENFG

BOFF

ERRP

ABRQ

OVRQ

TTC

TEST

ENA/STB

SWRES

UDR17

–

UDR16

–

UDR15

–

UDR14

–

UDR13

UBRR111

UBRR13

UDR12

UBRR110

UBRR12

UDR11

UBRR19

UBRR11

UDR10

UBRR18

UBRR10

page 194

page 198

UBRR1H

UBRR1L

Reserved

UCSR1C

UCSR1B

UCSR1A

Reserved

UDR0

UBRR17

UBRR16

UBRR15

UBRR14

–

UMSEL1

TXCIE1

TXC1

UPM11

UDRIE1

UDRE1

UPM10

RXEN1

FE1

USBS1

TXEN1

DOR1

UCSZ11

UCSZ12

UPE1

UCSZ10

RXB81

U2X1

UCPOL1

TXB81

page 197

page 196

page 194

RXCIE1

RXC1

MPCM1

UDR07

–

UDR06

–

UDR05

–

UDR04

–

UDR03

UBRR011

UBRR03

UDR02

UBRR010

UBRR02

UDR01

UBRR09

UBRR01

UDR00

UBRR08

UBRR00

page 194

page 198

UBRR0H

UBRR0L

Reserved

UCSR0C

UCSR0B

UCSR0A

Reserved

UBRR07

UBRR06

UBRR05

UBRR04

–

UMSEL0

TXCIE0

TXC0

UPM01

UDRIE0

UDRE0

UPM00

RXEN0

FE0

USBS0

TXEN0

DOR0

UCSZ01

UCSZ02

UPE0

UCSZ00

RXB80

U2X0

UCPOL0

TXB80

page 196

page 195

page 194

RXCIE0

RXC0

MPCM0

404

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

(0x7D)

Reserved

TWCR

TWINT

TWDR7

TWAR6

TWS7

TWEA

TWDR6

TWAR5

TWS6

TWSTA

TWDR5

TWAR4

TWS5

TWSTO

TWDR4

TWAR3

TWS4

TWWC

TWDR3

TWAR2

TWS3

TWEN

TWDR2

TWAR1

–

TWIE

page 211

page 213

page 212

page 211

TWDR

TWDR1

TWAR0

TWPS1

TWBR1

TWDR0

TWGCE

TWPS0

TWBR0

TWAR

TWSR

TWBR

TWBR7

TWBR6

TWBR5

TWBR4

TWBR3

TWBR2

Reserved

ASSR

–

EXCLK

AS2

TCN2UB

OCR2UB

TCR2UB

page 159

Reserved

OCR2A

OCR2A7

TCNT27

OCR2A6

TCNT26

OCR2A5

TCNT25

OCR2A4

TCNT24

OCR2A3

TCNT23

OCR2A2

TCNT22

OCR2A1

TCNT21

OCR2A0

TCNT20

page 158

TCNT2

Reserved

TCCR2A

Reserved

OCR3CH

OCR3CL

OCR3BH

OCR3BL

OCR3AH

OCR3AL

ICR3H

FOC2A

WGM20

COM2A1

COM2A0

WGM21

CS22

CS21

CS20

page 163

OCR3C15

OCR3C7

OCR3B15

OCR3B7

OCR3A15

OCR3A7

ICR315

OCR3C14

OCR3C6

OCR3B14

OCR3B6

OCR3A14

OCR3A6

ICR314

OCR3C13

OCR3C5

OCR3B13

OCR3B5

OCR3A13

OCR3A5

ICR313

OCR3C12

OCR3C4

OCR3B12

OCR3B4

OCR3A12

OCR3A4

ICR312

OCR3C11

OCR3C3

OCR3B11

OCR3B3

OCR3A11

OCR3A3

ICR311

OCR3C10

OCR3C2

OCR3B10

OCR3B2

OCR3A10

OCR3A2

ICR310

OCR3C9

OCR3C1

OCR3B9

OCR3B1

OCR3A9

OCR3A1

ICR39

OCR3C8

OCR3C0

OCR3B8

OCR3B0

OCR3A8

OCR3A0

ICR38

page 141

page 142

page 140

ICR3L

ICR37

ICR36

ICR35

ICR34

ICR33

ICR32

ICR31

ICR30

TCNT3H

TCNT3L

Reserved

TCCR3C

TCCR3B

TCCR3A

Reserved

OCR1CH

OCR1CL

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

TCNT315

TCNT37

TCNT314

TCNT36

TCNT313

TCNT35

TCNT312

TCNT34

TCNT311

TCNT33

TCNT310

TCNT32

TCNT39

TCNT31

TCNT38

TCNT30

FOC3A

ICNC3

FOC3B

ICES3

FOC3C

–

page 140

page 138

page 135

WGM33

COM3B0

WGM32

COM3C1

CS32

CS31

CS30

COM3A1

COM3A0

COM3B1

COM3C0

WGM31

WGM30

OCR1C15

OCR1C7

OCR1B15

OCR1B7

OCR1A15

OCR1A7

ICR115

OCR1C14

OCR1C6

OCR1B14

OCR1B6

OCR1A14

OCR1A6

ICR114

OCR1C13

OCR1C5

OCR1B13

OCR1B5

OCR1A13

OCR1A5

ICR113

OCR1C12

OCR1C4

OCR1B12

OCR1B4

OCR1A12

OCR1A4

ICR112

OCR1C11

OCR1C3

OCR1B11

OCR1B3

OCR1A11

OCR1A3

ICR111

OCR1C10

OCR1C2

OCR1B10

OCR1B2

OCR1A10

OCR1A2

ICR110

OCR1C9

OCR1C1

OCR1B9

OCR1B1

OCR1A9

OCR1A1

ICR19

OCR1C8

OCR1C0

OCR1B8

OCR1B0

OCR1A8

OCR1A0

ICR18

page 141

page 142

page 140

ICR1L

ICR17

ICR16

ICR15

ICR14

ICR13

ICR12

ICR11

ICR10

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

TCNT115

TCNT17

TCNT114

TCNT16

TCNT113

TCNT15

TCNT112

TCNT14

TCNT111

TCNT13

TCNT110

TCNT12

TCNT19

TCNT11

TCNT18

TCNT10

FOC1A

ICNC1

COM1A1

–

FOC1B

ICES1

COM1A0

–

FOC1C

–

page 139

page 138

page 135

page 271

page 291

WGM13

COM1B0

–

WGM12

COM1C1

–

CS12

COM1C0

–

CS11

CS10

COM1B1

–

WGM11

AIN1D

ADC1D

WGM10

AIN0D

ADC0D

DIDR0

ADC7D

ADC6D

ADC5D

ADC4D

ADC3D

ADC2D

Reserved

405

7538B–CAN–05/06

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7C)

(0x7B)

ADMUX

ADCSRB

ADCSRA

ADCH

REFS1

–

REFS0

ACME

ADLAR

–

MUX4

–

MUX3

–

MUX2

ADTS2

ADPS2

- / ADC4

ADC2 / -

MUX1

ADTS1

MUX0

ADTS0

page 286

page 290, 268

page 288

(0x7A)

ADEN

- / ADC9

ADSC

ADATE

- / ADC7

ADC5 / -

ADIF

ADIE

ADPS1

ADPS0

(0x79)

- / ADC8

- / ADC6

ADC4 / -

- / ADC5

ADC3 / -

ADC9 / ADC3

ADC1 / -

ADC8 / ADC2

ADC0 /

page 289

(0x78)

ADCL

ADC7 / ADC1 ADC6 / ADC0

page 289

(0x77)

Reserved

XMCRB

XMCRA

Reserved

TIMSK3

TIMSK2

TIMSK1

TIMSK0

Reserved

EICRB

(0x76)

(0x75)

XMBK

SRE

–

XMM2

XMM1

XMM0

page 33

page 32

(0x74)

SRL2

SRL1

SRL0

SRW11

SRW10

SRW01

SRW00

(0x73)

(0x72)

(0x71)

–

ICIE3

–

OCIE3C

OCIE3B

OCIE3A

OCIE2A

OCIE1A

OCIE0A

TOIE3

TOIE2

TOIE1

TOIE0

page 142

page 161

page 142

page 112

(0x70)

–

OCIE1C

–

OCIE1B

–

(0x6F)

ICIE1

–

(0x6E)

(0x6D)

(0x6C)

(0x6B)

(0x6A)

ISC71

ISC31

ISC70

ISC30

ISC61

ISC21

ISC60

ISC20

ISC51

ISC11

ISC50

ISC10

ISC41

ISC01

ISC40

ISC00

page 94

page 93

(0x69)

EICRA

(0x68)

Reserved

OSCCAL

Reserved

CLKPR

(0x67)

(0x66)

–

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

page 42

(0x65)

(0x64)

(0x63)

(0x62)

(0x61)

CLKPCE

–

WDCE

S

CLKPS3

WDE

V

CLKPS2

WDP2

N

CLKPS1

WDP1

Z

CLKPS0

WDP0

C

page 44

page 57

page 11

page 14

(0x60)

WDTCR

SREG

–

I

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

T

H

SPH

SP15

SP7

SP14

SP6

SP13

SP5

SP12

SP4

SP11

SP3

SP10

SP2

SP9

SP8

SPL

SP1

SP0

Reserved

RAMPZ⁽¹⁾

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

–

RAMPZ0

page 13

SPMIE

RWWSB

–

RWWSRE

BLBSET

PGWRT

–

PGERS

–

SPMEN

–

page 325

–

JTD

–

PUD

JTRF

–

IVSEL

EXTRF

SM0

IVCE

PORF

SE

page 64, 73, 303

page 55, 303

page 46

WDRF

SM2

BORF

SM1

–

Reserved

OCDR

IDRD/OCDR7

ACD

OCDR6

ACBG

OCDR5

ACO

OCDR4

ACI

OCDR3

ACIE

OCDR2

ACIC

OCDR1

ACIS1

OCDR0

ACIS0

page 298

page 269

ACSR

Reserved

SPDR

SPD7

SPIF

SPD6

WCOL

SPD5

–

SPD4

–

SPD3

–

SPD2

–

SPD1

–

SPD0

SPI2X

page 174

page 172

page 36

SPSR

SPCR

SPIE

SPE

DORD

GPIOR25

GPIOR15

MSTR

GPIOR24

GPIOR14

CPOL

CPHA

SPR1

SPR0

GPIOR2

GPIOR1

Reserved

OCR0A

TCNT0

GPIOR27

GPIOR17

GPIOR26

GPIOR16

GPIOR23

GPIOR13

GPIOR22

GPIOR12

GPIOR21

GPIOR11

GPIOR20

GPIOR10

OCR0A7

TCNT07

OCR0A6

TCNT06

OCR0A5

TCNT05

OCR0A4

TCNT04

OCR0A3

TCNT03

OCR0A2

TCNT02

OCR0A1

TCNT01

OCR0A0

TCNT00

page 112

page 111

Reserved

TCCR0A

GTCCR

EEARH⁽²⁾

EEARL

FOC0A

TSM

WGM00

–

COM0A1

–

COM0A0

–

WGM01

–

CS02

–

CS01

PSR2

CS00

PSR310

EEAR8

EEAR0

EEDR0

EERE

page 109

page 98, 163

page 22

–

EEAR11

EEAR3

EEDR3

EERIE

GPIOR03

INT3

EEAR10

EEAR2

EEDR2

EEMWE

GPIOR02

INT2

EEAR9

EEAR1

EEDR1

EEWE

GPIOR01

INT1

EEAR7

EEDR7

–

EEAR6

EEDR6

–

EEAR5

EEDR5

–

EEAR4

EEDR4

–

page 22

EEDR

page 23

EECR

page 23

GPIOR0

EIMSK

GPIOR07

INT7

GPIOR06

INT6

GPIOR05

INT5

GPIOR04

INT4

GPIOR00

INT0

page 36

page 95

EIFR

INTF7

INTF6

INTF5

INTF4

INTF3

INTF2

INTF1

INTF0

page 95

Reserved

406

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

Reserved

TIFR3

TIFR2

TIFR1

TIFR0

PORTG

DDRG

PING

–

ICF3

–

OCF3C

–

OCF3B

–

OCF3A

OCF2A

OCF1A

OCF0A

PORTG1

DDG1

TOV3

TOV2

page 143

page 161

page 143

page 112

page 92

page 91

page 92

page 91

page 90

page 89

page 90

–

ICF1

–

OCF1C

–

OCF1B

–

TOV1

–

TOV0

–

PORTG4

DDG4

PING4

PORTF4

DDF4

PINF4

PORTE4

DDE4

PINE4

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

PORTA4

DDA4

PINA4

PORTG3

DDG3

PING3

PORTF3

DDF3

PORTG2

DDG2

PING2

PORTF2

DDF2

PORTG0

DDG0

–

PING1

PORTF1

DDF1

PING0

PORTF0

DDF0

PORTF

DDRF

PINF

PORTF7

DDF7

PINF7

PORTE7

DDE7

PINE7

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

PORTA7

DDA7

PINA7

PORTF6

DDF6

PINF6

PORTE6

DDE6

PINE6

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

PORTA6

DDA6

PINA6

PORTF5

DDF5

PINF5

PORTE5

DDE5

PINE5

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

PORTA5

DDA5

PINA5

PINF3

PORTE3

DDE3

PINF2

PORTE2

DDE2

PINF1

PINF0

PORTE

DDRE

PINE

PORTE1

DDE1

PORTE0

DDE0

PINE3

PORTD3

DDD3

PINE2

PORTD2

DDD2

PINE1

PINE0

PORTD0

DDD0

PORTD

DDRD

PIND

PORTD1

DDD1

PIND3

PORTC3

DDC3

PIND2

PORTC2

DDC2

PIND1

PORTC1

DDC1

PIND0

PORTC0

DDC0

PORTC

DDRC

PINC

PINC3

PORTB3

DDB3

PINC2

PORTB2

DDB2

PINC1

PORTB1

DDB1

PINC0

PORTB0

DDB0

PORTB

DDRB

PINB

PINB3

PORTA3

DDA3

PINB2

PORTA2

DDA2

PINB1

PINB0

PORTA0

DDA0

PORTA

DDRA

PINA

PORTA1

DDA1

PINA3

PINA2

PINA1

PINA0

Notes: 1. Address bits exceeding PCMSB (Table 26-11 on page 340) are don’t care.

2. Address bits exceeding EEAMSB (Table 26-12 on page 340) are don’t care.

3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

4. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

5. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

6. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90CAN32/64 is a

complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the

IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

407

7538B–CAN–05/06

31. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Clear Register

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

Indirect Jump to (Z)

PC ← PC + k + 1

PC ← Z

None

I

2

JMP

k

Direct Jump

PC ← k

3

RCALL

ICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

k

Direct Subroutine Call

Subroutine Return

PC ← k

4

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

k

408

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRIE

BRID

k

Branch if Interrupt Enabled

Branch if Interrupt Disabled

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H ← 0

H

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

Rd+1:Rd ← Rr+1:Rr

Rd ← K

None

1

2

3

-

Load Immediate

LD

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

LD

LDD

LD

Rd ← (Z)

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

LD

LDD

LDS

ST

Rd ← (k)

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

ELPM

SPM

(k) ← Rr

Load Program Memory

R0 ← (Z)

Rd, Z

Load Program Memory

Rd ← (Z)

Rd, Z+

Load Program Memory and Post-Inc

Extended Load Program Memory

Extended Load Program Memory and Post-Inc

Store Program Memory

Rd ← (Z), Z ← Z+1

R0 ← (RAMPZ:Z)

Rd ← (RAMPZ:Z)

Rd ← (RAMPZ:Z), RAMPZ:Z ← RAMPZ:Z+1

(Z) ← R1:R0

Rd, Z

Rd, Z+

409

7538B–CAN–05/06

Mnemonics

Operands

Description

Operation

Flags

#Clocks

IN

Rd, P

P, Rr

Rr

In Port

Rd ← P

P ← Rr

None

1

2

OUT

PUSH

POP

Out Port

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

SLEEP

WDR

No Operation

Sleep

None

1

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

410

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

4. Ordering Information

(1)

Ordering Code

Speed (MHz)

Power Supply (V)

Package

Operation Range

Product Marking

AT90CAN32-16AI

AT90CAN32-16MI

16

2.7 - 5.5

64A

Industrial (-40° to +85°C)

AT90CAN32-IL

64M1

Industrial (-40° to +85°C)

Green

AT90CAN32-16AU

AT90CAN32-16MU

16

2.7 - 5.5

64A

AT90CAN32-UL

Industrial (-40° to +85°C)

Green

64M1

AT90CAN64-16AI⁽³⁾

AT90CAN64-16MI⁽³⁾

16

2.7 - 5.5

64A

Industrial (-40° to +85°C)

AT90CAN64-IL

64M1

Industrial (-40° to +85°C)

Green

AT90CAN64-16AU⁽³⁾

AT90CAN64-16MU⁽³⁾

16

2.7 - 5.5

64A

AT90CAN64-UL

Industrial (-40° to +85°C)

Green

64M1

AT90CAN128-16AI⁽²⁾

AT90CAN128-16MI⁽²⁾

16

2.7 - 5.5

64A

Industrial (-40° to +85°C)

AT90CAN128-IL

64M1

Industrial (-40° to +85°C)

Green

AT90CAN128-16AU⁽²⁾

AT90CAN128-16MU⁽²⁾

16

2.7 - 5.5

64A

AT90CAN128-UL

Industrial (-40° to +85°C)

Green

64M1

Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-

tion and minimum quantities.

2. For information only.

3. Check for Availability.

5. Packaging Information

Package Type

64A

64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

64-Lead, Quad Flat No lead (QFN)

64M1

13

7538B–CAN–05/06

5.1

TQFP64

14

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

5.2

QFN64

15

7538B–CAN–05/06

34. Errata

34.1 Errata Summary

34.1.1

AT90CAN32 RevA (Date code ≤ 0531, lot number ≤ A05320)

• Reset of Timer-2 flags in asynchronous mode

• Miss-functioning when code stack is in XRAM

• Asynchronous Timer-2 wakes up without interrupt

• SPI programming timing

34.1.2

AT90CAN64 RevA (Date code ≤ ..., lot number ≤ ...)

• Asynchronous Timer-2 wakes up without interrupt

• SPI programming timing

34.2 Errata Description

4. Reset of Timer-2 flags in asynchronous mode

In asynchronous mode, a writing in any register of the TIMER-2 (TCCR2A, TCNT2 &

OCR2A) automatically clears TOV2 and OCF2A flags in TFIR register.

Problem fix / workaround

– TOV2: Do not write in Timer-2 registers if TCNT2 is equal to 0xFF, 0x00 or 0x01.

– OCF2A: Do not write in Timer-2 registers if TCNT2 and OCR2A differ from -1, 0 or 1.

3. Miss-functioning when code stack is in XRAM

If the stack pointer (SP) targets the XRAM and if the execution of an instruction is split to

serve a rising interrupt, the last operation of this instruction, executed after pushing out the

return address from XRAM, may be disturbed providing wrong data to the system.

Example: - the “OUT” instruction can be executed twice

- the “MOV” instruction can update a register with un-predictable data.

Problem fix / workaround

Map the code stack in internal SRAM.

2. Asynchronous Timer-2 wakes up without interrupt

The asynchronous timer can wake from sleep without giving interrupt. The error only occurs

if the interrupt flag(s) is cleared by software less than 4 cycles before going to sleep and this

clear is done exactly when it is supposed to be set (compare match or overflow). Only the

interrupts flags are affected by the clear, not the signal witch is used to wake up the part.

Problem fix / workaround

No known workaround, try to lock the code to avoid such a timing.

1. SPI programming timing

When the fuse high byte or the extended fuse byte has been written, it is necessary to wait

the end of the programming using “Poll RDY/BSY” instruction. If this instruction is entered

too speedily after the “Write Fuse” instruction, the fuse low byte is written instead of high

fuse /extended fuse byte.

414

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AT90CAN32/64

Problem fix / workaround

Wait sometime before applying the “Poll RDY/BSY” instruction. For 8MHz system clock,

waiting 1 µs is sufficient.

415

7538B–CAN–05/06

35. Datasheet Revision History for AT90CAN32/64

Please note that the referring page numbers in this section are referring to this document.

The referring revision in this section are referring to the document revision.

35.1 Changes from 7538A-09/05 to 7538B-05/06

1. Update package drawings QFN64 and TQFP64.

35.2 Creation:

7538A-09/05

416

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AT90CAN32/64

1

2

Features .................................................................................................... 1

Description ............................................................................................... 2

2.1

2.2

2.3

2.4

2.5

2.6

Comparison Between AT90CAN32/64 and AT90CAN128 .................................2

Part Desription ....................................................................................................2

Disclaimer ...........................................................................................................3

Block Diagram .....................................................................................................4

Pin Configurations ...............................................................................................5

Pin Descriptions ..................................................................................................6

3

4

About Code Examples ............................................................................. 8

AVR CPU Core .......................................................................................... 9

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

Introduction .........................................................................................................9

Architectural Overview ........................................................................................9

ALU – Arithmetic Logic Unit ..............................................................................10

Status Register .................................................................................................11

General Purpose Register File ..........................................................................12

Stack Pointer .....................................................................................................14

Instruction Execution Timing .............................................................................14

Reset and Interrupt Handling ............................................................................15

5

Memories ................................................................................................ 18

5.1

5.2

5.3

5.4

5.5

5.6

In-System Reprogrammable Flash Program Memory ......................................18

SRAM Data Memory .........................................................................................19

EEPROM Data Memory ....................................................................................22

I/O Memory .......................................................................................................27

External Memory Interface ................................................................................27

General Purpose I/O Registers .........................................................................36

6

System Clock .......................................................................................... 37

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

Clock Systems and their Distribution ................................................................37

Clock Sources ...................................................................................................38

Default Clock Source ........................................................................................38

Crystal Oscillator ...............................................................................................39

Low-frequency Crystal Oscillator ......................................................................40

Calibrated Internal RC Oscillator ......................................................................41

External Clock ...................................................................................................42

Clock Output Buffer ...........................................................................................43

i

7538B–CAN–05/06

6.9

Timer/Counter2 Oscillator .................................................................................43

6.10 System Clock Prescaler ....................................................................................44

7

Power Management and Sleep Modes ................................................. 46

7.1

7.2

7.3

7.4

7.5

7.6

Idle Mode ..........................................................................................................47

ADC Noise Reduction Mode .............................................................................47

Power-down Mode ............................................................................................47

Power-save Mode .............................................................................................47

Standby Mode ...................................................................................................48

Minimizing Power Consumption ........................................................................48

8

9

System Control and Reset .................................................................... 51

8.1

8.2

8.3

8.4

Reset .................................................................................................................51

Internal Voltage Reference ...............................................................................56

Watchdog Timer ................................................................................................57

Timed Sequences for Changing the Configuration of the Watchdog Timer ......59

Interrupts ................................................................................................ 60

9.1

9.2

Interrupt Vectors in AT90CAN32/64 .................................................................60

Moving Interrupts Between Application and Boot Space ..................................64

10 I/O-Ports .................................................................................................. 66

10.1 Introduction .......................................................................................................66

10.2 Ports as General Digital I/O ..............................................................................67

10.3 Alternate Port Functions ...................................................................................71

10.4 Register Description for I/O-Ports .....................................................................89

11 External Interrupts ................................................................................. 93

12 Timer/Counter3/1/0 Prescalers ............................................................. 96

12.1 Overview ...........................................................................................................96

12.2 Timer/Counter0/1/3 Prescalers Register Description ........................................98

13 8-bit Timer/Counter0 with PWM ............................................................ 99

13.1 Features ............................................................................................................99

13.2 Overview ...........................................................................................................99

13.3 Timer/Counter Clock Sources .........................................................................100

13.4 Counter Unit ....................................................................................................100

13.5 Output Compare Unit ......................................................................................101

13.6 Compare Match Output Unit ...........................................................................103

13.7 Modes of Operation ........................................................................................104

ii

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AT90CAN32/64

13.8 Timer/Counter Timing Diagrams .....................................................................108

13.9 8-bit Timer/Counter Register Description ........................................................109

14 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) ........... 113

14.1 Features ..........................................................................................................113

14.2 Overview .........................................................................................................113

14.3 Accessing 16-bit Registers .............................................................................116

14.4 Timer/Counter Clock Sources .........................................................................119

14.5 Counter Unit ....................................................................................................120

14.6 Input Capture Unit ...........................................................................................121

14.7 Output Compare Units ....................................................................................123

14.8 Compare Match Output Unit ...........................................................................125

14.9 Modes of Operation ........................................................................................126

14.10 Timer/Counter Timing Diagrams .....................................................................134

14.11 16-bit Timer/Counter Register Description ......................................................135

15 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 145

15.1 Features ..........................................................................................................145

15.2 Overview .........................................................................................................145

15.3 Timer/Counter Clock Sources .........................................................................147

15.4 Counter Unit ....................................................................................................147

15.5 Output Compare Unit ......................................................................................148

15.6 Compare Match Output Unit ...........................................................................149

15.7 Modes of Operation ........................................................................................150

15.8 Timer/Counter Timing Diagrams .....................................................................154

15.9 8-bit Timer/Counter Register Description ........................................................156

15.10 Asynchronous operation of the Timer/Counter2 .............................................159

15.11 Timer/Counter2 Prescaler ...............................................................................162

16 Output Compare Modulator - OCM ..................................................... 164

16.1 Overview .........................................................................................................164

16.2 Description ......................................................................................................164

17 Serial Peripheral Interface – SPI ......................................................... 167

17.1 Features ..........................................................................................................167

17.2 SS Pin Functionality ........................................................................................171

17.3 Data Modes .....................................................................................................174

18 USART (USART0 and USART1) .......................................................... 176

iii

7538B–CAN–05/06

18.1 Features ..........................................................................................................176

18.2 Overview .........................................................................................................176

18.3 Dual USART ...................................................................................................176

18.4 Clock Generation ............................................................................................178

18.5 Serial Frame ...................................................................................................180

18.6 USART Initialization ........................................................................................181

18.7 Data Transmission – USART Transmitter .......................................................182

18.8 Data Reception – USART Receiver ................................................................185

18.9 Asynchronous Data Reception .......................................................................189

18.10 Multi-processor Communication Mode ...........................................................192

18.11 USART Register Description ..........................................................................194

18.12 Examples of Baud Rate Setting ......................................................................199

19 Two-wire Serial Interface ..................................................................... 203

19.1 Features ..........................................................................................................203

19.2 Two-wire Serial Interface Bus Definition .........................................................203

19.3 Data Transfer and Frame Format ...................................................................204

19.4 Multi-master Bus Systems, Arbitration and Synchronization ..........................206

19.5 Overview of the TWI Module ...........................................................................208

19.6 TWI Register Description ................................................................................211

19.7 Using the TWI .................................................................................................214

19.8 Transmission Modes .......................................................................................217

19.9 Multi-master Systems and Arbitration .............................................................231

20 Controller Area Network - CAN ........................................................... 233

20.1 Features ..........................................................................................................233

20.2 CAN Protocol ..................................................................................................233

20.3 CAN Controller ................................................................................................239

20.4 CAN Channel ..................................................................................................240

20.5 Message Objects ............................................................................................242

20.6 CAN Timer ......................................................................................................245

20.7 Error Management ..........................................................................................246

20.8 Interrupts .........................................................................................................248

20.9 CAN Register Description ...............................................................................250

20.10 General CAN Registers ..................................................................................251

20.11 MOb Registers ................................................................................................260

20.12 Examples of CAN Baud Rate Setting .............................................................265

iv

AT90CAN32/64

7538B–CAN–05/06

AT90CAN32/64

21 Analog Comparator .............................................................................. 268

21.1 Overview .........................................................................................................268

21.2 Analog Comparator Register Description .......................................................268

21.3 Analog Comparator Multiplexed Input .............................................................270

22 Analog to Digital Converter - ADC ...................................................... 272

22.1 Features ..........................................................................................................272

22.2 Operation ........................................................................................................273

22.3 Starting a Conversion .....................................................................................274

22.4 Prescaling and Conversion Timing .................................................................275

22.5 Changing Channel or Reference Selection .....................................................278

22.6 ADC Noise Canceler .......................................................................................279

22.7 ADC Conversion Result ..................................................................................283

22.8 ADC Register Description ...............................................................................286

23 JTAG Interface and On-chip Debug System ...................................... 292

23.1 Features ..........................................................................................................292

23.2 Overview .........................................................................................................292

23.3 Test Access Port – TAP ..................................................................................292

23.4 TAP Controller ................................................................................................295

23.5 Using the Boundary-scan Chain .....................................................................296

23.6 Using the On-chip Debug System ...................................................................296

23.7 On-chip Debug Specific JTAG Instructions .....................................................297

23.8 On-chip Debug Related Register in I/O Memory ............................................298

23.9 Using the JTAG Programming Capabilities ....................................................298

23.10 Bibliography ....................................................................................................298

24 Boundary-scan IEEE 1149.1 (JTAG) ................................................... 299

24.1 Features ..........................................................................................................299

24.2 System Overview ............................................................................................299

24.3 Data Registers ................................................................................................299

24.4 Boundary-scan Specific JTAG Instructions .....................................................301

24.5 Boundary-scan Related Register in I/O Memory ............................................303

24.6 Boundary-scan Chain .....................................................................................303

24.7 AT90CAN32/64 Boundary-scan Order ...........................................................313

24.8 Boundary-scan Description Language Files ...................................................319

25 Boot Loader Support – Read-While-Write Self-Programming ......... 320

25.1 Features ..........................................................................................................320

v

7538B–CAN–05/06

25.2 Application and Boot Loader Flash Sections ..................................................320

25.3 Read-While-Write and No Read-While-Write Flash Sections .........................320

25.4 Boot Loader Lock Bits .....................................................................................323

25.5 Entering the Boot Loader Program .................................................................324

25.6 Addressing the Flash During Self-Programming .............................................326

25.7 Self-Programming the Flash ...........................................................................327

26 Memory Programming ......................................................................... 335

26.1 Program and Data Memory Lock Bits .............................................................335

26.2 Fuse Bits .........................................................................................................336

26.3 Signature Bytes ...............................................................................................338

26.4 Calibration Byte ...............................................................................................338

26.5 Parallel Programming Overview .....................................................................338

26.6 Parallel Programming .....................................................................................341

26.7 SPI Serial Programming Overview .................................................................347

26.8 SPI Serial Programming .................................................................................348

26.9 JTAG Programming Overview ........................................................................351

27 Electrical Characteristics ^{(1) ............................................................................................... 364}

27.1 Absolute Maximum Ratings* ...........................................................................364

27.2 DC Characteristics ..........................................................................................365

27.3 External Clock Drive Characteristics ...............................................................366

27.4 Maximum Speed vs. VCC ...............................................................................367

27.5 Two-wire Serial Interface Characteristics .......................................................368

27.6 SPI Timing Characteristics ..............................................................................369

27.7 CAN Physical Layer Characteristics ...............................................................371

27.8 ADC Characteristics ........................................................................................372

27.9 External Data Memory Characteristics ...........................................................374

27.10 Parallel Programming Characteristics .............................................................379

28 Decoupling Capacitors ........................................................................ 382

29 AT90CAN32/64 Typical Characteristics ............................................. 383

29.1 Active Supply Current .....................................................................................383

29.2 Idle Supply Current .........................................................................................386

29.3 Power-down Supply Current ...........................................................................388

29.4 Power-save Supply Current ............................................................................389

29.5 Standby Supply Current ..................................................................................390

29.6 Pin Pull-up .......................................................................................................390

vi

AT90CAN32/64

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AT90CAN32/64

29.7 Pin Driver Strength ..........................................................................................392

29.8 Pin Thresholds and Hysteresis .......................................................................394

29.9 BOD Thresholds and Analog Comparator Offset ............................................396

29.10 Internal Oscillator Speed .................................................................................398

29.11 Current Consumption of Peripheral Units .......................................................400

29.12 Current Consumption in Reset and Reset Pulse Width ..................................402

30 Register Summary ............................................................................... 404

31 Instruction Set Summary ..................................................................... 408

32 Ordering Information ........................................................................... 411

33 Packaging Information ........................................................................ 411

33.1 TQFP64 ..........................................................................................................412

33.2 QFN64 ............................................................................................................413

34 Errata ..................................................................................................... 414

34.1 Errata Summary ..............................................................................................414

34.2 Errata Description ...........................................................................................414

35 Datasheet Change Log for AT90CAN32/64 ........................................ 416

35.1 Changes from 7538A-09/05 to 7538B-05/06 ... ...............................................416

35.2 Creation: .........................................................................................................416

vii

7538B–CAN–05/06

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Printed on recycled paper.

7538B–CAN–05/06


型号：	AT90CAN128-16M
厂家：	MICROCHIP
描述：	RISC Microcontroller, 8-Bit, FLASH, 16MHz, CMOS 时钟微控制器外围集成电路
文件：	总424页 (文件大小：5580K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT90CAN128-16M [MICROCHIP]

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