AT90CAN128-16MI [ATMEL]
8-bit Microcontroller with 128K Bytes of ISP Flash and CAN Controller; 8位微控制器，带有128K字节的ISP功能的Flash和CAN控制器
| 型号： | AT90CAN128-16MI |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 128K Bytes of ISP Flash and CAN Controller |
| 文件： | 总15页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Non volatile Program and Data Memories
– 128K Bytes of In-System Reprogrammable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes
In-System Programming by On-Chip Boot Program (CAN, UART)
True Read-While-Write Operation
8-bit
Microcontroller
with
128K Bytes of
ISP Flash
and
– 4K Bytes EEPROM (Endurance: 100,000 Write/Erase Cycles)
– 4K Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Programming Flash (Hardware ISP), EEPROM, Lock & Fuse Bits
– Extensive On-chip Debug Support
• CAN Controller 2.0A & 2.0B
– 15 Full Message Objects with Separate Identifier Tags and Masks
– Transmit, Receive, Automatic Reply and Frame Buffer Receive Modes
– 1Mbits/s Maximum Transfer Rate at 8 MHz
– Time stamping, TTC & Listening Mode (Psying or Autobaud)
• Peripheral Features
CAN Controller
– Programmable Watchdog Timer with On-chip Oscillator
– 8-bit Synchronous Timer/Counter-0
10-bit Prescaler
External Event Counter
Output Compare or 8-bit PWM Output
– 8-bit Asynchronous Timer/Counter-2
10-bit Prescaler
AT90CAN128
Preliminary
Summary
External Event Counter
Output Compare or 8-Bit PWM Output
32Khz Oscillator for RTC Operation
– Dual 16-bit Synchronous Timer/Counters-1 & 3
10-bit Prescaler
Input Capture with Noise Canceler
External Event Counter
3-Output Compare or 16-Bit PWM Output
Output Compare Modulation
– 8-channel, 10-bit SAR ADC
8 Single-ended channels
7 Differential Channels
2 Differential Channels With Programmable Gain at 1x, 10x, or 200x
– On-chip Analog Comparator
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USART
– Master/Slave SPI Serial Interface
Programming Flash (Hardware ISP)
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– 8 External Interrupt Sources
– 5 Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down & Standby
– Software Selectable Clock Frequency
– Global Pull-up Disable
• I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-lead QFN
• Operating Voltages
– 2.7 - 5.5V
• Operating temperature
– Industrial (-40°C to +85°C)
• Maximum Frequency
– 8 MHz at 2.7V - Industrial range
– 16 MHz at 4.5V - Industrial range
Rev. 4250CS–CAN–03/04
Note: This is a summary document. A complete document is
available on our web site at www.atmel.com.
1
Description
The AT90CAN128 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the AT90CAN128 achieves throughputs approaching 1 MIPS per MHz allowing the sys-
tem designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers.
All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The AT90CAN128 provides the following features: 128K bytes of In-System Program-
mable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM,
53 general purpose I/O lines, 32 general purpose working registers, a CAN controller,
Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM,
2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with
optional differential input stage with programmable gain, a programmable Watchdog
Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test
interface, also used for accessing the On-chip Debug system and programming and five
software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports
and interrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next inter-
rupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. The
ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous
Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode,
the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory. Soft-
ware in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90CAN128
is a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The AT90CAN128 AVR is supported with a full suite of program and system develop-
ment tools including: C compilers, macro assemblers, program debugger/simulators, in-
circuit emulators, and evaluation kits.
The ATmega128 AVR microcontroller can be made compatible with the AT90CAN128,
refer to Application Note AVR 096, on the Atmel web site.
Disclaimer
Typical values contained in this datasheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
2
AT90CAN128
4250CS–CAN–03/04
AT90CAN128
Block Diagram
Figure 1. Block Diagram
PF7 - PF0
PA7 - PA0
PC7 - PC0
VCC
GND
PORTA DRIVERS
PORTF DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
DATA DIR.
REG. PORTC
PORTC
8-BIT DATA BUS
POR - BOD
RESET
INTERNAL
OSCILLATOR
AVCC
CALIB. OSC
ADC
AGND
AREF
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
PROGRAM
COUNTER
STACK
POINTER
JTAG TAP
CAN
CONTROLLER
TIMING AND
CONTROL
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
ON-CHIP DEBUG
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
TIMER/
COUNTERS
GENERAL
PURPOSE
REGISTERS
X
Y
Z
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
INTERRUPT
UNIT
CONTROL
LINES
ALU
EEPROM
STATUS
REGISTER
TWO-WIRE SERIAL
INTERFACE
USART0
SPI
USART1
DATA REGISTER
DATA DIR.
REG. PORTE
DATA REGISTER
DATA DIR.
REG. PORTB
DATA REGISTER
DATA DIR.
REG. PORTD
DATA REG. DATA DIR.
PORTG
REG. PORTG
PORTE
PORTB
PORTD
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PORTE DRIVERS
PE7 - PE0
PB7 - PB0
PD7 - PD0
PG4 - PG0
3
4250CS–CAN–03/04
Pin Configurations
Figure 2. Pinout AT90CAN128- TQFP
NC(1)
(RXD0 / PDI) PE0
(TXD0 / PDO) PE1
(XCK0 / AIN0) PE2
(OC3A / AIN1) PE3
(OC3B / INT4) PE4
(OC3C / INT5) PE5
(T3 / INT6) PE6
1
2
3
48 PA3 (AD3)
47 PA4 (AD4)
46 PA5 (AD5)
45 PA6 (AD6)
44 PA7 (AD7)
43 PG2 (ALE)
42 PC7 (A15 / CLKO)
41 PC6 (A14)
INDEX CORNER
4
5
6
7
8
9
AT90CAN128
(64-lead TQFP top view)
40
39
38
(ICP3 / INT7) PE7
PC5 (A13)
PC4 (A12)
PC3 (A11)
(SS) PB0 10
(SCK) PB1 11
(MOSI) PB2 12
37 PC2 (A10)
36 PC1 (A9)
35 PC0 (A8)
34 PG1 (RD)
(MISO) PB3
13
(OC2A) PB4 14
(OC1A) PB5 15
(OC1B) PB6 16
33
PG0 (WR)
(1) NC = Do not connect (May be used in future devices)
(2) Timer2 Oscillator
4
AT90CAN128
4250CS–CAN–03/04
AT90CAN128
Figure 3. Pinout AT90CAN128- QFN
NC(1)
PA3 (AD3)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
(RXD0 / PDI) PE0
(TXD0 / PDO) PE1
(XCK0 / AIN0) PE2
(OC3A / AIN1) PE3
(OC3B / INT4) PE4
(OC3C / INT5) PE5
(T3 / INT6) PE6
(ICP3 / INT7) PE7
(SS) PB0
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2 (ALE)
PC7 (A15 / CLKO)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
2
3
INDEX CORNER
4
5
6
7
8
AT90CAN128
(64-lead QFN top view)
9
10
11
12
13
14
15
16
(SCK) PB1
(MOSI) PB2
(MISO) PB3
(OC2A) PB4
PC0 (A8)
(OC1A) PB5
PG1 (RD)
(OC1B) PB6
PG0 (WR)
(1) NC = Do not connect (May be used in future devices)
(2) Timer2 Oscillator
5
4250CS–CAN–03/04
Pin Descriptions
VCC
Digital supply voltage.
Ground.
GND
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the AT90CAN128 as
listed on page 70.
Port B (PB7..PB0)
Port C (PC7..PC0)
Port D (PD7..PD0)
Port E (PE7..PE0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the AT90CAN128 as
listed on page 72.
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port C also serves the functions of special features of the AT90CAN128 as listed on
page 74.
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the AT90CAN128 as
listed on page 77.
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the AT90CAN128 as
listed on page 79.
Port F (PF7..PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port F output
buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port F pins that are externally pulled low will source current if the pull-up
6
AT90CAN128
4250CS–CAN–03/04
AT90CAN128
resistors are activated. The Port F pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled,
the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even
if a reset occurs.
Port G (PG4..PG0)
Port G is a 5-bit I/O port with internal pull-up resistors (selected for each bit). The Port G
output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port G pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
Port G also serves the functions of various special features of the AT90CAN128 as
listed on page 84.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset. The minimum pulse length is given in caracteristics. Shorter pulses are not
guaranteed to generate a reset. The I/O ports of the AVR are immediately reset to their
initial state even if the clock is not running. The clock is needed to reset the rest of the
AT90CAN128.
XTAL1
XTAL2
AVCC
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be con-
nected to VCC through a low-pass filter.
AREF
This is the analog reference pin for the A/D Converter.
About Code Examples
This documentation contains simple code examples that briefly show how to use various
parts of the device. These code examples assume that the part specific header file is
included before compilation. Be aware that not all C compiler vendors include bit defini-
tions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation for more details.
7
4250CS–CAN–03/04
AT90CAN128
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
(0xC0)
Reserved
Reserved
Reserved
Reserved
Reserved
CANMSG
CANSTMH
CANSTML
CANIDM1
CANIDM2
CANIDM3
CANIDM4
CANIDT1
CANIDT2
CANIDT3
CANIDT4
CANCDMOB
CANSTMOB
CANPAGE
CANHPMOB
CANREC
CANTEC
CANTTCH
CANTTCL
CANTIMH
CANTIML
CANTCON
CANBT3
CANBT2
CANBT1
CANSIT1
CANSIT2
CANIE1
MSG 7
TIMSTM15
TIMSTM7
IDMSK28
IDMSK20
IDMSK12
MSG 6
TIMSTM14
TIMSTM6
IDMSK27
IDMSK19
IDMSK11
MSG 5
TIMSTM13
TIMSTM5
IDMSK26
IDMSK18
IDMSK10
MSG 4
TIMSTM12
TIMSTM4
IDMSK25
IDMSK17
MSG 3
TIMSTM11
TIMSTM3
IDMSK24
IDMSK16
MSG 2
TIMSTM10
TIMSTM2
IDMSK23
IDMSK15
MSG 1
TIMSTM9
TIMSTM1
IDMSK22
IDMSK14
MSG 0
TIMSTM8
TIMSTM0
IDMSK21
IDMSK13
page 259
page 259
page 259
page 258
page 258
page 258
page 258
page 257
page 257
page 257
page 257
page 256
page 254
page 254
page 254
page 253
page 253
page 253
page 253
page 253
page 253
page 252
page 252
page 251
page 251
page 250
page 250
page 250
page 250
page 250
page 250
page 249
page 248
page 247
page 246
IDMSK
9
1
IDMSK
8
0
IDMSK
7
IDMSK
6
IDMSK5
IDMSK
4
IDMSK
3
IDMSK
2
IDMSK
IDMSK
RTRMSK
IDT23
–
IDEMSK
IDT21
IDT28
IDT20
IDT12
IDT27
IDT19
IDT11
IDT26
IDT18
IDT10
IDT25
IDT17
IDT24
IDT16
IDT22
IDT14
IDT15
IDT13
IDT
IDT
9
1
IDT
IDT
8
0
IDT
7
IDT
6
IDT5
IDT4
IDT3
IDT
2
RTRTAG
DLC2
RB1TAG
DLC1
RB0TAG
DLC0
CONMOB1
DLCW
MOBNB3
HPMOB3
REC7
TEC7
TIMTTC15
TIMTTC7
CANTIM15
CANTIM7
TPRSC7
–
CONMOB0
TXOK
RPLV
RXOK
IDE
BERR
DLC3
SERR
CERR
FERR
AERR
MOBNB2
HPMOB2
REC6
MOBNB1
HPMOB1
REC5
MOBNB0
HPMOB0
REC4
AINC
INDX2
INDX1
INDX0
CGP0
CGP3
CGP2
CGP1
REC3
REC2
REC1
REC0
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
TIMTTC14
TIMTTC6
CANTIM14
CANTIM6
TPRSC6
PHS22
TIMTTC13
TIMTTC5
CANTIM13
CANTIM5
TPRSC5
PHS21
SJW0
TIMTTC12
TIMTTC4
CANTIM12
CANTIM4
TPRSC4
PHS20
–
TIMTTC11
TIMTTC3
CANTIM11
CANTIM3
TPRSC3
PHS12
PRS2
TIMTTC10
TIMTTC2
CANTIM10
CANTIM2
TPRSC2
PHS11
PRS1
TIMTTC9
TIMTTC1
CANTIM9
CANTIM1
TRPSC1
PHS10
PRS0
TIMTTC8
TIMTTC0
CANTIM8
CANTIM0
TPRSC0
SMP
–
SJW1
–
–
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
–
–
SIT14
SIT13
SIT12
SIT11
SIT10
SIT9
SIT8
SIT7
SIT6
SIT5
SIT4
SIT3
SIT2
SIT1
SIT0
–
IEMOB14
IEMOB6
ENMOB14
ENMOB6
ENBOFF
BOFFIT
OVRG
IEMOB13
IEMOB5
ENMOB13
ENMOB5
ENRX
IEMOB12
IEMOB4
ENMOB12
ENMOB4
ENTX
IEMOB11
IEMOB3
ENMOB11
ENMOB3
ENERR
SERG
IEMOB10
IEMOB2
ENMOB10
ENMOB2
ENBX
IEMOB9
IEMOB1
ENMOB9
ENMOB1
ENERG
FERG
IEMOB8
IEMOB0
ENMOB8
ENMOB0
ENOVRT
AERG
CANIE2
IEMOB7
–
CANEN1
CANEN2
CANGIE
ENMOB7
ENIT
CANGIT
CANIT
–
OVRTIM
–
BXOK
CERG
CANGSTA
CANGCON
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UDR1
TXBSY
SYNTTC
RXBSY
LISTEN
ENFG
BOFF
ERRP
ABRQ
OVRQ
TTC
TEST
ENA/STB
SWRES
UDR17
–
UDR16
–
UDR15
–
UDR14
–
UDR13
UBRR111
UBRR13
UDR12
UBRR110
UBRR12
UDR11
UBRR19
UBRR11
UDR10
UBRR18
UBRR10
page 189
page 193
page 193
UBRR1H
UBRR1L
Reserved
UCSR1C
UCSR1B
UCSR1A
Reserved
UDR0
UBRR17
UBRR16
UBRR15
UBRR14
–
UMSEL1
TXCIE1
TXC1
UPM11
UDRIE1
UDRE1
UPM10
RXEN1
FE1
USBS1
TXEN1
DOR1
UCSZ11
UCSZ12
UPE1
UCSZ10
RXB81
U2X1
UCPOL1
TXB81
page 192
page 191
page 189
RXCIE1
RXC1
MPCM1
UDR07
–
UDR06
–
UDR05
–
UDR04
–
UDR03
UBRR011
UBRR03
UDR02
UBRR010
UBRR02
UDR01
UBRR09
UBRR01
UDR00
UBRR08
UBRR00
page 189
page 193
page 193
UBRR0H
UBRR0L
Reserved
UCSR0C
UCSR0B
UCSR0A
UBRR07
UBRR06
UBRR05
UBRR04
–
UMSEL0
TXCIE0
TXC0
UPM01
UDRIE0
UDRE0
UPM00
RXEN0
FE0
USBS0
TXEN0
DOR0
UCSZ01
UCSZ02
UPE0
UCSZ00
RXB80
U2X0
UCPOL0
TXB80
page 191
page 190
page 189
RXCIE0
RXC0
MPCM0
9
4250CS–CAN–03/04
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xBF)
(0xBE)
(0xBD)
(0xBC)
(0xBB)
(0xBA)
(0xB9)
(0xB8)
(0xB7)
(0xB6)
(0xB5)
(0xB4)
(0xB3)
(0xB2)
(0xB1)
(0xB0)
(0xAF)
(0xAE)
(0xAD)
(0xAC)
(0xAB)
(0xAA)
(0xA9)
(0xA8)
(0xA7)
(0xA6)
(0xA5)
(0xA4)
(0xA3)
(0xA2)
(0xA1)
(0xA0)
(0x9F)
(0x9E)
(0x9D)
(0x9C)
(0x9B)
(0x9A)
(0x99)
(0x98)
(0x97)
(0x96)
(0x95)
(0x94)
(0x93)
(0x92)
(0x91)
(0x90)
(0x8F)
(0x8E)
(0x8D)
(0x8C)
(0x8B)
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
(0x85)
(0x84)
(0x83)
(0x82)
(0x81)
(0x80)
(0x7F)
(0x7E)
Reserved
Reserved
Reserved
TWCR
TWINT
TWDR7
TWAR6
TWS7
TWEA
TWDR6
TWAR5
TWS6
TWSTA
TWDR5
TWAR4
TWS5
TWSTO
TWDR4
TWAR3
TWS4
TWWC
TWDR3
TWAR2
TWS3
TWEN
TWDR2
TWAR1
–
–
TWIE
page 207
page 209
page 209
page 208
page 207
TWDR
TWDR1
TWAR0
TWPS1
TWBR1
TWDR0
TWGCE
TWPS0
TWBR0
TWAR
TWSR
TWBR
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
Reserved
ASSR
–
–
–
EXCLK
AS2
TCN2UB
OCR2UB
TCR2UB
page 155
Reserved
Reserved
OCR2A
OCR2A7
TCNT27
OCR2A6
TCNT26
OCR2A5
TCNT25
OCR2A4
TCNT24
OCR2A3
TCNT23
OCR2A2
TCNT22
OCR2A1
TCNT21
OCR2A0
TCNT20
page 155
page 154
TCNT2
Reserved
TCCR2A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OCR3CH
OCR3CL
OCR3BH
OCR3BL
OCR3AH
OCR3AL
ICR3H
FOC2A
WGM20
COM2A1
COM2A0
WGM21
CS22
CS21
CS20
page 152
OCR3C15
OCR3C7
OCR3B15
OCR3B7
OCR3A15
OCR3A7
ICR315
OCR3C14
OCR3C6
OCR3B14
OCR3B6
OCR3A14
OCR3A6
ICR314
OCR3C13
OCR3C5
OCR3B13
OCR3B5
OCR3A13
OCR3A5
ICR313
OCR3C12
OCR3C4
OCR3B12
OCR3B4
OCR3A12
OCR3A4
ICR312
OCR3C11
OCR3C3
OCR3B11
OCR3B3
OCR3A11
OCR3A3
ICR311
OCR3C10
OCR3C2
OCR3B10
OCR3B2
OCR3A10
OCR3A2
ICR310
OCR3C9
OCR3C1
OCR3B9
OCR3B1
OCR3A9
OCR3A1
ICR39
OCR3C8
OCR3C0
OCR3B8
OCR3B0
OCR3A8
OCR3A0
ICR38
page 137
page 137
page 137
page 137
page 137
page 137
page 138
page 138
page 136
page 136
ICR3L
ICR37
ICR36
ICR35
ICR34
ICR33
ICR32
ICR31
ICR30
TCNT3H
TCNT3L
Reserved
TCCR3C
TCCR3B
TCCR3A
Reserved
Reserved
OCR1CH
OCR1CL
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
TCNT315
TCNT37
TCNT314
TCNT36
TCNT313
TCNT35
TCNT312
TCNT34
TCNT311
TCNT33
TCNT310
TCNT32
TCNT39
TCNT31
TCNT38
TCNT30
FOC3A
ICNC3
FOC3B
ICES3
FOC3C
–
–
–
–
–
page 136
page 134
page 132
WGM33
COM3B0
WGM32
COM3C1
CS32
CS31
CS30
COM3A1
COM3A0
COM3B1
COM3C0
WGM31
WGM30
OCR1C15
OCR1C7
OCR1B15
OCR1B7
OCR1A15
OCR1A7
ICR115
OCR1C14
OCR1C6
OCR1B14
OCR1B6
OCR1A14
OCR1A6
ICR114
OCR1C13
OCR1C5
OCR1B13
OCR1B5
OCR1A13
OCR1A5
ICR113
OCR1C12
OCR1C4
OCR1B12
OCR1B4
OCR1A12
OCR1A4
ICR112
OCR1C11
OCR1C3
OCR1B11
OCR1B3
OCR1A11
OCR1A3
ICR111
OCR1C10
OCR1C2
OCR1B10
OCR1B2
OCR1A10
OCR1A2
ICR110
OCR1C9
OCR1C1
OCR1B9
OCR1B1
OCR1A9
OCR1A1
ICR19
OCR1C8
OCR1C0
OCR1B8
OCR1B0
OCR1A8
OCR1A0
ICR18
page 137
page 137
page 137
page 137
page 137
page 137
page 138
page 138
page 136
page 136
ICR1L
ICR17
ICR16
ICR15
ICR14
ICR13
ICR12
ICR11
ICR10
TCNT1H
TCNT1L
Reserved
TCCR1C
TCCR1B
TCCR1A
DIDR1
TCNT115
TCNT17
TCNT114
TCNT16
TCNT113
TCNT15
TCNT112
TCNT14
TCNT111
TCNT13
TCNT110
TCNT12
TCNT19
TCNT11
TCNT18
TCNT10
FOC1A
ICNC1
COM1A1
–
FOC1B
ICES1
COM1A0
–
FOC1C
–
–
–
–
CS12
COM1C0
–
–
–
page 135
page 134
page 137
page 262
page 281
WGM13
COM1B0
–
WGM12
COM1C1
–
CS11
CS10
COM1B1
–
WGM11
AIN1D
ADC1D
WGM10
AIN0D
ADC0D
DIDR0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
10
AT90CAN128
4250CS–CAN–03/04
AT90CAN128
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x7D)
(0x7C)
Reserved
ADMUX
ADCSRB
ADCSRA
ADCH
REFS1
ADHSM
ADEN
REFS0
ACME
ADLAR
–
MUX4
–
MUX3
–
MUX2
ADTS2
ADPS2
- / ADC4
ADC2 / -
MUX1
ADTS1
MUX0
ADTS0
page 277
page 279, 260
page 279
(0x7B)
(0x7A)
ADSC
ADATE
- / ADC7
ADC5 / -
ADIF
ADIE
ADPS1
ADPS0
(0x79)
- / ADC9
- / ADC8
- / ADC6
ADC4 / -
- / ADC5
ADC3 / -
ADC9 / ADC3
ADC1 / -
ADC8 / ADC2
ADC0 /
page 280
(0x78)
ADCL
ADC7 / ADC1 ADC6 / ADC0
page 280
(0x77)
Reserved
Reserved
XMCRB
XMCRA
Reserved
Reserved
TIMSK3
TIMSK2
TIMSK1
TIMSK0
Reserved
Reserved
Reserved
EICRB
(0x76)
(0x75)
XMBK
SRE
–
–
–
–
XMM2
XMM1
XMM0
page 31
page 29
(0x74)
SRL2
SRL1
SRL0
SRW11
SRW10
SRW01
SRW00
(0x73)
(0x72)
(0x71)
–
–
–
–
–
–
–
–
ICIE3
–
–
–
–
–
OCIE3C
OCIE3B
OCIE3A
OCIE2A
OCIE1A
OCIE0A
TOIE3
TOIE2
TOIE1
TOIE0
page 138
page 157
page 138
page 108
(0x70)
–
OCIE1C
–
–
OCIE1B
–
(0x6F)
ICIE1
–
(0x6E)
(0x6D)
(0x6C)
(0x6B)
(0x6A)
ISC71
ISC31
ISC70
ISC30
ISC61
ISC21
ISC60
ISC20
ISC51
ISC11
ISC50
ISC10
ISC41
ISC01
ISC40
ISC00
page 90
page 89
(0x69)
EICRA
(0x68)
Reserved
Reserved
OSCCAL
Reserved
Reserved
Reserved
Reserved
CLKPR
WDTCR
SREG
(0x67)
(0x66)
–
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
page 40
(0x65)
(0x64)
(0x63)
(0x62)
(0x61)
CLKPCE
–
–
–
–
–
WDCE
S
CLKPS3
WDE
V
CLKPS2
WDP2
N
CLKPS1
WDP1
Z
CLKPS0
WDP0
C
page 42
page 55
page 10
page 12
page 12
(0x60)
–
I
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
T
H
SPH
SP15
SP7
SP14
SP6
SP13
SP5
SP12
SP4
SP11
SP3
SP10
SP2
SP9
SP8
SPL
SP1
SP0
Reserved
RAMPZ
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
MCUSR
SMCR
–
–
–
–
–
–
–
RAMPZ0
page 12
SPMIE
RWWSB
–
–
–
–
–
RWWSRE
BLBSET
PGWRT
–
PGERS
–
SPMEN
–
page 314
–
JTD
–
–
–
–
–
–
–
–
PUD
JTRF
–
–
IVSEL
EXTRF
SM0
IVCE
PORF
SE
page 60, 70, 291
page 52, 291
page 44
WDRF
SM2
BORF
SM1
–
Reserved
OCDR
IDRD/OCDR7
ACD
OCDR6
ACBG
OCDR5
ACO
OCDR4
ACI
OCDR3
ACIE
OCDR2
ACIC
OCDR1
ACIS1
OCDR0
ACIS0
page 286
page 260
ACSR
Reserved
SPDR
SPD7
SPIF
SPD6
WCOL
SPD5
–
SPD4
–
SPD3
–
SPD2
–
SPD1
–
SPD0
SPI2X
page 169
page 169
page 169
page 34
page 34
SPSR
SPCR
SPIE
SPE
DORD
GPIOR25
GPIOR15
MSTR
GPIOR24
GPIOR14
CPOL
CPHA
SPR1
SPR0
GPIOR2
GPIOR1
Reserved
Reserved
OCR0A
TCNT0
GPIOR27
GPIOR17
GPIOR26
GPIOR16
GPIOR23
GPIOR13
GPIOR22
GPIOR12
GPIOR21
GPIOR11
GPIOR20
GPIOR10
OCR0A7
TCNT07
OCR0A6
TCNT06
OCR0A5
TCNT05
OCR0A4
TCNT04
OCR0A3
TCNT03
OCR0A2
TCNT02
OCR0A1
TCNT01
OCR0A0
TCNT00
page 108
page 107
Reserved
TCCR0A
GTCCR
EEARH
EEARL
FOC0A
TSM
WGM00
–
COM0A1
–
COM0A0
–
WGM01
–
CS02
–
CS01
PSR2
CS00
PSR310
EEAR8
EEAR0
EEDR0
EERE
page 105
page 93, 159
page 20
–
–
–
–
EEAR11
EEAR3
EEDR3
EERIE
GPIOR03
INT3
EEAR10
EEAR2
EEDR2
EEMWE
GPIOR02
INT2
EEAR9
EEAR1
EEDR1
EEWE
GPIOR01
INT1
EEAR7
EEDR7
–
EEAR6
EEDR6
–
EEAR5
EEDR5
–
EEAR4
EEDR4
–
page 20
EEDR
page 20
EECR
page 21
GPIOR0
EIMSK
GPIOR07
INT7
GPIOR06
INT6
GPIOR05
INT5
GPIOR04
INT4
GPIOR00
INT0
page 34
page 91
EIFR
INTF7
INTF6
INTF5
INTF4
INTF3
INTF2
INTF1
INTF0
page 91
11
4250CS–CAN–03/04
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
Reserved
Reserved
Reserved
TIFR3
TIFR2
TIFR1
TIFR0
PORTG
DDRG
PING
–
–
–
ICF3
–
–
OCF3C
–
OCF3B
–
OCF3A
OCF2A
OCF1A
OCF0A
PORTG1
DDG1
TOV3
TOV2
page 139
page 158
page 139
page 108
page 88
page 88
page 88
page 87
page 87
page 88
page 87
page 87
page 87
page 87
page 87
page 87
page 86
page 86
page 87
page 86
page 86
page 86
page 86
page 86
page 86
–
–
–
–
ICF1
–
OCF1C
–
OCF1B
–
TOV1
–
–
–
–
TOV0
–
–
–
PORTG4
DDG4
PING4
PORTF4
DDF4
PINF4
PORTE4
DDE4
PINE4
PORTD4
DDD4
PIND4
PORTC4
DDC4
PINC4
PORTB4
DDB4
PINB4
PORTA4
DDA4
PINA4
PORTG3
DDG3
PING3
PORTF3
DDF3
PORTG2
DDG2
PING2
PORTF2
DDF2
PORTG0
DDG0
–
–
–
–
–
–
PING1
PORTF1
DDF1
PING0
PORTF0
DDF0
PORTF
DDRF
PORTF7
DDF7
PINF7
PORTE7
DDE7
PINE7
PORTD7
DDD7
PIND7
PORTC7
DDC7
PINC7
PORTB7
DDB7
PINB7
PORTA7
DDA7
PINA7
PORTF6
DDF6
PINF6
PORTE6
DDE6
PINE6
PORTD6
DDD6
PIND6
PORTC6
DDC6
PINC6
PORTB6
DDB6
PINB6
PORTA6
DDA6
PINA6
PORTF5
DDF5
PINF5
PORTE5
DDE5
PINE5
PORTD5
DDD5
PIND5
PORTC5
DDC5
PINC5
PORTB5
DDB5
PINB5
PORTA5
DDA5
PINA5
PINF
PINF3
PORTE3
DDE3
PINF2
PORTE2
DDE2
PINF1
PINF0
PORTE
DDRE
PINE
PORTE1
DDE1
PORTE0
DDE0
PINE3
PORTD3
DDD3
PINE2
PORTD2
DDD2
PINE1
PINE0
PORTD0
DDD0
PORTD
DDRD
PIND
PORTD1
DDD1
PIND3
PORTC3
DDC3
PIND2
PORTC2
DDC2
PIND1
PORTC1
DDC1
PIND0
PORTC0
DDC0
PORTC
DDRC
PINC
PINC3
PORTB3
DDB3
PINC2
PORTB2
DDB2
PINC1
PORTB1
DDB1
PINC0
PORTB0
DDB0
PORTB
DDRB
PINB
PINB3
PORTA3
DDA3
PINB2
PORTA2
DDA2
PINB1
PINB0
PORTA0
DDA0
PORTA
DDRA
PINA
PORTA1
DDA1
PINA3
PINA2
PINA1
PINA0
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90CAN128 is a
complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the
IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
12
AT90CAN128
4250CS–CAN–03/04
Ordering Information
Ordering Code
AT90CAN128-16AE
AT90CAN128-16ME
AT90CAN128-16AI
AT90CAN128-16MI
Speed (MHz) Power Supply (V)
Package
64A
Operation Range
Engineering Sample
Product Marking
AT90CAN128-EL
AT90CAN128-EL
AT90CAN128-IL
AT90CAN128-IL
16
16
16
16
2.7 - 5.5
2.7 - 5.5
2.7 - 5.5
2.7 - 5.5
64M1
64A
Engineering Sample
Industrial (-40° to +85°C)
Industrial (-40° to +85°C)
64M1
Note:
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and
minimum quantities.
Packaging Information
Package Type
64A
64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64-Lead, Quad Flat No lead (QFN)
64M1
14
AT90CAN128
4250CS–CAN–03/04
AT90CAN128
TQFP64
64 LEADS Thin Quad Flat Package
PIN 64
PIN 1
B
INDEX CORNER
E1
E
e
D1
D
11˚~13˚
A1
C
0˚~7˚
A2
A
L
MM
NOM
–
INCH
MIN
–
MAX
1.20
MIN
–
MAX
. 047
. 006
. 041
. 640
. 555
. 640
. 555
. 018
. 008
. 030
NOM
SYMBOL
A
–
A1
A2
D
0.05
0.95
–
0.15
. 002
. 037
. 620
. 547
. 620
. 547
. 012
. 004
. 018
–
. 039
. 630
. 551
. 630
. 551
–
1.00
16.00
14.00
16.00
14.00
–
1.05
15.75
16.25
14.10
16.25
14.10
0.45
D1(2) 13.90
15.75
E1(2) 13.90
E
Notes:
1. This package conforms to JEDEC reference MS-026,
Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25 mm per side. Dimensions
D1 and E1 are maximum plastic body size dimensions
including mold mismatch.
B
C
L
0.30
0.09
0.45
–
0.20
–
–
0.75
–
3. Lead coplanarity is 0.10 mm maximum.
e
0.80 TYP
. 0315 TYP
15
4250CS–CAN–03/04
QFN64
64 LEADS Quad Flat No lead
A
A2
D
A1
INDEX CORNER
E
SEATING PLANE
0.08 C
TOP VIEW
SIDE VIEW
J
e
64x b
INDEX CORNER
62 63 64
MM
MIN NOM MAX MIN NOM MAX
0.80 1.00 . 031 . 039
J / K 6.47 6.57 6.67 . 255 . 259 . 263
INCH
1
2
3
A
D / E
9.00 BSC
. 354 BSC
K
A1 0.00
0.05 . 000
. 002
. 039
N
64
A2 0.75
e
1.00 . 029
0.50 BSC
. 020 BSC
L
b
0.40 0.45 0.50 . 016 . 018 . 020
0.17 0.25 0.27 . 007 . 010 . 011
64x L
EXPOSED DIE
ATTACH PAD
BOTTOM VIEW
Note: Compliant JEDEC MO-220
16
AT90CAN128
4250CS–CAN–03/04
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Europe
Microcontrollers
Atmel Sarl
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Data-
com
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
TEL (41) 26-426-5555
FAX (41) 26-426-5500
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
Japan
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
FAX 1(719) 540-1759
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
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