AT83C5132XXX-ROTIL [MICROCHIP]
Microcontroller, 8-Bit, MROM, 40MHz, PQFP80;
| 型号： | AT83C5132XXX-ROTIL |
| 厂家： | 
MICROCHIP |
| 描述： | Microcontroller, 8-Bit, MROM, 40MHz, PQFP80 时钟 微控制器 外围集成电路 |
| 文件： | 总162页 (文件大小：2227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Programmable Audio Output for Interfacing with Common Audio DAC
– PCM Format Compatible
– I2S Format Compatible
• 8-bit MCU C51 Core-based (FMAX = 20 MHz)
• 2304 Bytes of Internal RAM
• 64K Bytes of Code Memory
– Flash: AT89C5132, ROM: AT83C5132(1)
• 4K Bytes of Boot Flash Memory (AT89C5132)
– ISP: Download from USB or UART to any External Memory Cards
• USB Rev 1.1 Device Controller
USB
– “Full Speed” Data Transmission
• Built-in PLL
Microcontroller
with 64K Bytes
ROM or Flash
• MultiMedia Card® Interface Compatibility
• Atmel DataFlash® SPI Interface Compatibility
• IDE/ATAPI Interface
• 2 Channels 10-bit ADC, 8 kHz (8 True Bits)
– Battery Voltage Monitoring
– Voice Recording Controlled by Software
• Up to 44 Bits of General-purpose I/Os
– 4-bit Interrupt Keyboard Port for a 4 x n Matrix
– SmartMedia® Software Interface
• Two Standard 16-bit Timers/Counters
• Hardware Watchdog Timer
• Standard Full Duplex UART with Baud Rate Generator
• SPI Master and Slave Modes Controller
• Power Management
AT83C5132
AT89C5132
– Power-on Reset
– Software Programmable MCU Clock
– Idle Mode, Power-down Mode
• Operating Conditions
Preliminary
– 3V, 10%, 25 mA Typical Operating at 25°C
– Temperature Range: -40°C to +85°C
• Packages
– TQFP80, TQFP64 , BGA81(1), PLCC84 (Development Board Only)
– Dice
Note:
1. Contact Atmel for availability.
Description
The AT8xC5132 are mass storage devices controlling data exchange between various
Flash modules, HDD and CD-ROM.
The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Program-
ming through an embedded 4K Bytes of Boot Flash Memory.
The AT83C5132 includes 64K Bytes of ROM memory.
The AT8xC5132 include 2304 Bytes of RAM memory.
The AT8xC5132 provide all the necessary features for man-machine interface includ-
ing, timers, keyboard port, serial or parallel interface (USB, SPI, IDE), ADC input, I2S
output, and all external memory interface (NAND or NOR Flash, SmartMedia, Multi-
Media, DataFlash cards).
Typical Applications
•
•
•
Flash Recorder/Writer
PDA, Camera, Mobile Phone
PC Add-on
Rev. 4173A–8051–08/02
Block Diagram
Figure 1. AT8xC5132 Block Diagram
INT0
INT1 VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD
T0
T1
SS MISO MOSI SCK
1
1
1
1
1
1
2
2
2
2
Interrupt
Handler Unit
Flash
ROM
UART
and
BRG
RAM
2304 Bytes
10-bit A-to-D
Converter
or
Timers 0/1
Watchdog
SPI/DataFlash
Controller
64K Bytes
Flash Boot
4K Bytes
10-bit ADC
8-BIT INTERNAL BUS
C51 (X2 CORE)
I/O
I2S/PCM
Audio Interface
USB
Controller
Keyboard
Interface
Ports
IDE
MMC
Interface
Clock and PLL
Unit
Interface
1
FILT
X1 X2
RST
DOUT DCLK DSEL SCLK D+ D-
MCLK
KIN3:0
P0 - P5
MDAT MCMD
Notes: 1. Alternate function of Port 3
2. Alternate function of Port 4
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AT8xC5132
4173A–8051–08/02
AT8xC5132
Pin Configuration
Figure 2. AT8xC5132 80-pin TQFP Package
ALE
ISP#
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P4.5
2
P4.4
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
3
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
VSS
4
5
6
7
P1.5
8
TQFP80
P1.6
9
P1.7
10
11
12
13
14
15
16
17
18
19
20
VDD
VDD
PVDD
MCLK
MDAT
MCMD
RST
FILT
PVSS
VSS
SCLK
X2
DSEL
X1
DCLK
DOUT
VSS
TST#
UVDD
UVSS
VDD
3
4173A–8051–08/02
Figure 3. AT8xC5132 64-pin TQFP
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
64
48
47
ISP#
P1.0/KIN0
1
2
P4.5
P2.2/A10
P2.3/A11
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
46
45
3
4
P2.4/A12
P2.5/A13
P2.6/A14
44
43
42
5
6
7
P1.5
P2.7/A15
41
40
39
8
P1.6
VSS
VCC
TQFP64
9
P1.7
10
VDD
FILT
MCLK
MDAT
38
37
11
12
13
VSS
X2
MCMD
RST
36
35
14
15
16
X1
TST#
34
33
VSS
VDD
UVDD
3132
17 18 19 20 21 22 23 24 25 26 27 28 29
30
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AT8xC5132
Figure 4. AT8xC5132 84-pin PLCC Package(1)
ALE 12
ISP# 13
74 NC
73 P4.5
P1.0/KIN0 14
P1.1/KIN1 15
P1.2/KIN2 16
P1.3/KIN3 17
P1.4 18
72 P4.4
71 P2.2/A10
70 P2.3/A11
69 P2.4/A12
68 P2.5/A13
67 P2.6/A14
66 P2.7/A15
65 VSS
P1.5 19
P1.6 20
P1.7
21
VDD 22
PVDD 23
FILT 24
PVSS 25
VSS 26
X2 27
PLCC84
64 VDD
63 MCLK
62 MDAT
61 MCMD
60 RST
59 SCLK
58 DSEL
57 DCLK
56 DOUT
55 VSS
NC 28
X1 29
TST# 30
UVDD 31
UVSS 32
54 VDD
Note:
1. For development board only.
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Pin Description
All AT8xC5132 signals are detailed by functionality in Table 1 to Table 14.
Table 1. Ports Signal Description
Signal
Name
Alternate
Function
Type
Description
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have
1s written to them float and can be used as high impedance inputs.
To avoid any parasitic current consumption, floating P0 inputs must
P0.7:0
I/O
AD7:0
be polarized to VDD or VSS
.
KIN3:0
SCL
SDA
Port 1
P1.7:0
P2.7:0
I/O
I/O
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 2
A15:8
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
RXD
TXD
INT0
INT1
T0
Port 3
P3.7:0
I/O
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
T1
WR
RD
MISO
MOSI
SCK
Port 4
P4.7:0
P5.3:0
I/O
I/O
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
SS#
Port 5
-
P5 is a 4-bit bidirectional I/O port with internal pull-ups.
Table 2. Clock Signal Description
Signal
Name
Alternate
Function
Type
Description
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, its output is connected to this
pin. X1 is the clock source for internal timing.
X1
I
-
Output of the on-chip inverting oscillator amplifier
X2
O
I
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, leave X2 unconnected.
-
-
PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter.
FILT
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AT8xC5132
Table 3. Timer 0 and Timer 1 Signal Description
Signal
Name
Alternate
Function
Type
Description
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by
GATE0 bit in TCON register.
INT0#
I
P3.2
External Interrupt 0
INT0# input sets IE0 in the TCON register. If bit IT0 in this register is
set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0
is set by a low level on INT0#.
Timer 1 Gate Input
INT1 serves as external run control for Timer 1, when selected by
GATE1 bit in TCON register.
INT1#
I
P3.3
External Interrupt 1
INT1# input sets IE1 in the TCON register. If bit IT1 in this register is
set, bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1
is set by a low level on INT1#.
Timer 0 External Clock Input
T0
T1
I
I
When timer 0 operates as a counter, a falling edge on the T0 pin
increments the count.
P3.4
P3.5
Timer 1 External Clock Input
When Timer 1 operates as a counter, a falling edge on the T1 pin
increments the count.
Table 4. Audio Interface Signal Description
Signal
Alternate
Function
Name
DCLK
DOUT
Type
O
Description
DAC Data Bit Clock
DAC Audio Data
-
-
O
DAC Channel Select Signal
DSEL is the sample rate clock output.
DSEL
SCLK
O
O
-
-
DAC System Clock
SCLK is the oversampling clock synchronized to the digital audio data
(DOUT) and the channel selection signal (DSEL).
Table 5. USB Controller Signal Description
Signal
Name
Alternate
Function
Type
I/O
Description
USB Positive Data Upstream Port
This pin requires an external 1.5 kΩ pull-up to VDD for full speed
operation.
D+
-
-
D-
I/O
USB Negative Data Upstream Port
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4173A–8051–08/02
Table 6. MutiMediaCard Interface Signal Description
Signal
Name
Alternate
Function
Type
Description
MMC Clock output
Data or command clock transfer.
MCLK
O
-
MMC Command line
Bidirectional command channel used for card initialization and data
transfer commands. To avoid any parasitic current consumption,
MCMD
MDAT
I/O
I/O
-
unused MCMD input must be polarized to VDD or VSS
.
MMC Data line
Bidirectional data channel. To avoid any parasitic current consumption,
unused MDAT input must be polarized to VDD or VSS
-
.
Table 7. UART Signal Description
Signal
Name
Alternate
Function
Type
Description
Receive Serial Data
RXD
I/O
RXD sends and receives data in serial I/O mode 0 and receives data in
serial I/O modes 1, 2 and 3.
P3.0
P3.1
Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits data in
serial I/O modes 1, 2 and 3.
TXD
O
Table 8. Controller Signal Description
Signal
Name
Alternate
Function
Type
Description
SPI Master Input Slave Output Data Line
MISO
I/O
When in master mode, MISO receives data from the slave peripheral.
When in slave mode, MISO outputs data to the master controller.
P4.0
P4.1
SPI Master Output Slave Input Data Line
When in master mode, MOSI outputs data to the slave peripheral.
When in slave mode, MOSI receives data from the master controller.
MOSI
I/O
SPI Clock Line
SCK
SS#
I/O
I
When in master mode, SCK outputs clock to the slave peripheral. When
in slave mode, SCK receives clock from the master controller.
P4.2
P4.3
SPI Slave Select Line
When in controlled slave mode, SS enables the slave mode.
Table 9. Specific Controller
Signal
Name
Alternate
Function
Type
Description
Reserved
SCL
I/O
P1.6
P1.7
Do not set this bit.
Reserved
SDA
I/O
Do not set this bit.
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AT8xC5132
Table 10. A/D Converter Signal Description
Signal
Alternate
Function
Name
AIN1:0
AREFP
Type
Description
I
I
A/D Converter Analog Inputs
Analog Positive Voltage Reference Input
Analog Negative Voltage Reference Input
-
-
AREFN
I
-
This pin is internally connected to AVSS
.
Table 11. Keypad Interface Signal Description
Signal
Name
Alternate
Function
Type
Description
Keypad Input Lines
KIN3:0
I
Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt.
P1.3:0
Table 12. External Access Signal Description
Signal
Name
Alternate
Function
Type
Description
Address Lines
A15:8
I/O
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
P0.7:0
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the
IDE interface.
AD7:0
ALE
I/O
O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid
address information is available on lines A7:0. An external latch is used
to demultiplex the address from address/data bus.
-
-
ISP Enable Input
This signal must be held to GND through a pull-down resistor at the
falling reset to force execution of the internal bootloader.
ISP
I/O
Read Signal
RD
O
O
P3.7
P3.6
Read signal asserted during external data memory read operation.
Write Signal
WR
Write signal asserted during external data memory write operation.
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4173A–8051–08/02
Table 13. System Signal Description
Signal
Name
Alternate
Function
Type
Description
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is
running resets the device. The Port pins are driven to their reset
conditions when a voltage lower than VIL is applied, whether or not the
oscillator is running.
RST
I
-
This pin has an internal pull-down resistor which allows the device to be
reset by connecting a capacitor between this pin and VDD
.
Asserting RST when the chip is in Idle mode or Power-down mode
returns the chip to normal operation.
Test Input
TST
I
-
Test mode entry signal. This pin must be set to VDD
.
Table 14. Power Signal Description
Signal
Name
Alternate
Function
Type
Description
Digital Supply Voltage
Connect these pins to +3V supply voltage.
VDD
PWR
-
-
-
-
-
-
-
-
Circuit Ground
Connect these pins to ground.
VSS
GND
PWR
GND
PWR
GND
PWR
GND
Analog Supply Voltage
Connect this pin to +3V supply voltage.
AVDD
AVSS
PVDD
PVSS
UVDD
UVSS
Analog Ground
Connect this pin to ground.
PLL Supply voltage
Connect this pin to +3V supply voltage.
PLL Circuit Ground
Connect this pin to ground.
USB Supply Voltage
Connect this pin to +3V supply voltage.
USB Ground
Connect this pin to ground.
10
AT8xC5132
4173A–8051–08/02
AT8xC5132
Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Circuit(1)
Type
Pins
Input
TST#
VDD
P
Watchdog Output
Input/Output
RST
VSS
VDD VDD VDD
2 osc
periods
P1
P2(3)
P3
Latch Output
P1
P2
P3
Input/Output
P4
P53:0
N
VSS
VDD
P
P0
MCMD
MDAT
Input/Output
ISP#
N
VSS
VDD
ALE
SCLK
DCLK
P
Output
DOUT
DSEL
MCLK
N
VSS
D+
D-
Input/Output
D+
D-
Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the AT8xC5132 full Datasheet.
2. In Port 2, P1 transistor is continuously driven when outputing a high level bit address (A15:8).
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4173A–8051–08/02
Clock Controller
The AT8xC5132 clock controller is based on an on-chip oscillator feeding an on-chip
Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are gener-
ated by this controller.
Oscillator
The AT8xC5132 X1 and X2 pins are the input and the output of a single-stage on-chip
inverter (see Figure 5) that can be configured with off-chip components such as a Pierce
oscillator (see Figure 6). Value of capacitors and crystal characteristics are detailed in
the Section “DC Characteristics”.
The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU
core, and a clock for the peripherals as shown in Figure 5. These clocks are either
enabled or disabled, depending on the power reduction mode as detailed in “Power
Management” on page 46. The peripheral clock is used to generate the Timer 0, Timer
1, MMC, ADC, SPI, and Port sampling clocks.
Figure 5. Oscillator Block Diagram and Symbol
PER
CLOCK
0
1
X1
X2
÷ 2
Peripheral
Clock
Peripheral Clock Symbol
CPU Core
Clock
CPU
CLOCK
X2
CKCON.0
IDL
PCON.0
CPU Core Clock Symbol
PD
PCON.1
Oscillator
Clock
OSC
CLOCK
Oscillator Clock Symbol
X1
Figure 6. Crystal Connection
C1
C2
Q
VSS
X2
X2 Feature
Unlike standard C51 products that require 12 oscillator clock periods per machine cycle,
the AT8xC5132 need only 6 oscillator clock periods per machine cycle. This feature
called the “X2 feature” can be enabled using the X2 bit(1) in CKCON (see Table 16) and
allows the AT8xC5132 to operate in 6 or 12 oscillator clock periods per machine cycle.
As shown in Figure 5, both CPU and peripheral clocks are affected by this feature.
Figure 7 shows the X2 mode switching waveforms. After reset, the standard mode is
activated. In standard mode, the CPU and peripheral clock frequency is the oscillator
frequency divided by 2 while in X2 mode, it is the oscillator frequency.
Note:
1. The X2 bit reset value depends on the X2B bit in the Hardware Byte (see Table 21 on
page 23). Using the AT89C5132 (Flash Version) the system can boot either in stan-
dard or X2 mode depending on the X2B value. Using AT83C5132 (ROM Version) the
system always boots in standard mode. X2B bit can be changed to X2 mode later by
software.
12
AT8xC5132
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AT8xC5132
Figure 7. Mode Switching Waveforms
X1
X1 ÷ 2
X2 bit
Clock
STD Mode
X2 Mode
STD Mode
Note:
In order to prevent any incorrect operation while operating in X2 mode, the user must be aware that all peripherals using clock
frequency as time reference (timers…) will have their time reference divided by two. For example, a free running timer generat-
ing an interrupt every 20 ms will then generate an interrupt every 10 ms.
PLL
PLL Description
The AT8xC5132’s PLL is used to generate internal high frequency clock (the PLL Clock)
synchronized with an external low-frequency (the Oscillator Clock). The PLL clock pro-
vides the audio interface, and the USB interface clocks. Figure 8 shows the internal
structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register (see Table 17) is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PFILT pin (see
Figure 9). Value of the filter components are detailed in the Section “DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage Vref pro-
duced by the charge pump. It generates a square wave signal: the PLL clock.
Figure 8. PLL Block Diagram and Symbol
PFILT
CHP
PLLCON.1
PLLEN
N Divider
OSC
CLOCK
Up
VREF
N6:0
PFLD
VCO
PLL Clock
Down
PLOCK
PLLCON.0
R Divider
R9:0
PLL
CLOCK
OSCclk × (R + 1)
PLLclk = ----------------------------------------------
N + 1
PLL Clock Symbol
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Figure 9. PLL Filter Connection
PFILT
R
C2
C1
VSS
VSS
PLL Programming
The PLL is programmed using the flow shown in Figure 10. As soon as clock generation
is enabled, the user must wait until the lock indicator is set to ensure the clock output is
stable. The PLL clock frequency will depend on the audio interface clock frequencies.
Figure 10. PLL Programming Flow
PLL
Programming
Configure Dividers
N6:0 = xxxxxxb
R9:0 = xxxxxxxxxxb
Enable PLL
PLLRES = 0
PLLEN = 1
PLL Locked?
PLOCK = 1?
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AT8xC5132
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AT8xC5132
Registers
Table 16. CKCON Register
CKCON (S:8Fh) – Clock Control Register
7
-
6
5
-
4
-
3
-
2
1
0
WDX2
T1X2
T0X2
X2
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The values read from this bit is indeterminate. Do not set this bit.
Watchdog Clock Control Bit
Set to select the oscillator clock divided by two as watchdog clock input (X2
independent).
WDX2
-
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
Reserved
5 - 3
The values read from these Bits are indeterminate. Do not set these Bits.
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by two as Timer 1 clock input (X2
independent).
2
T1X2
Clear to select the peripheral clock as Timer 1 clock input (X2 dependent).
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by two as timer 0 clock input (X2
independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
1
0
T0X2
X2
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER
FOSC/2).
=
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
Reset Value = 0000 000Xb
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Table 17. PLLCON Register
PLLCON (S:E9h) – PLL Control Register
7
6
5
-
4
-
3
2
-
1
0
R1
R0
PLLRES
PLLEN
PLOCK
Bit
Bit
Number
Mnemonic Description
PLL Least Significant Bits R Divider
2 LSB of the 10-bit R divider.
7 - 6
5 - 4
R1:0
-
Reserved
The values read from these Bits are always 0. Do not set these Bits.
PLL Reset Bit
3
2
1
PLLRES Set this bit to reset the PLL.
Clear this bit to free the PLL and allow enabling.
Reserved
-
The values read from this bit is always 0. Do not set this bit.
PLL Enable Bit
PLLEN
Set to enable the PLL.
Clear to disable the PLL.
PLL Lock Indicator
0
PLOCK
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
Reset Value = 0000 1000b
Table 18. PLLNDIV Register
PLLNDIV (S:EEh) – PLL N Divider Register
7
-
6
5
4
3
2
1
0
N6
N5
N4
N3
N2
N1
N0
Bit
Bit
Number
Mnemonic Description
Reserved
7
-
The values read from this bit is always 0. Do not set this bit.
PLL N Divider
7-bit N divider.
6 - 0
N6:0
Reset Value = 0000 0000b
16
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AT8xC5132
Table 19. PLLRDIV Register
PLLRDIV (S:EFh) – PLL R Divider Register
7
6
5
4
3
2
1
0
R9
R8
R7
R6
R5
R4
R3
R2
Bit
Bit
Number
Mnemonic Description
PLL Most Significant Bits R Divider
8 MSB of the 10-bit R divider.
7 - 0
R9:2
Reset Value = 0000 0000b
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Program/Code
Memory
The AT89C5132 and AT83C5132 implement 64K Bytes of on-chip program/code mem-
ory. Figure 11 shows the split of internal and external program/code memory spaces
depending on the product.
The AT83C5132 product provides the internal program/code memory in ROM memory
while the AT89C5132 product provides it in Flash memory. These two products do not
allow external code memory execution.
The Flash memory increases EPROM and ROM functionality by in-circuit electrical era-
sure and programming. The high voltage needed for programming or erasing Flash cells
is generated on-chip using the standard VDD voltage, made possible by the internal
charge pump. Thus, the AT89C5132 can be programmed using only one voltage and
allows in application software programming. Hardware programming mode is also avail-
able using common programming tools.
The AT89C5132 implements an additional 4K Bytes of on-chip boot Flash memory pro-
vided in Flash memory. This boot memory is delivered programmed with a standard
bootloader software allowing In-System Programming (ISP). It also contains some
Application Programming Interfaces (API), allowing In Application Programming (IAP)
by using user’s own bootloader.
Figure 11. Program/Code Memory Organization
FFFFh
FFFFh
F000h
FFFFh
F000h
4K Bytes
Boot Flash
64K Bytes
Code ROM
64K Bytes
Code Flash
0000h
0000h
AT83C5132
AT89C5132
ROM Memory
Architecture
As shown in Figure 12, the AT83C5132 ROM memory is composed of two spaces
detailed in the following section.
Figure 12. ROM Memory Architecture
FFFFh
64K Bytes
User
ROM Memory
0000h
18
AT8xC5132
4173A–8051–08/02
AT8xC5132
User Space
This space is composed of a 64K Bytes ROM memory programmed during the manu-
facturing process. It contains the user’s application code.
Flash Memory
Architecture
As shown in Figure 13 the AT89C5132 Flash memory is composed of four spaces
detailed in the following paragraphs.
Figure 13. Flash Memory Architecture
Hardware Security
Extra Row
FFFFh
FFFFh
4K Bytes
Flash Memory
Boot
F000h
64K Bytes
User
Flash Memory
0000h
User Space
Boot Space
This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128
Bytes. It contains the user’s application code. This space can be read or written by both
software and hardware modes.
This space is composed of a 4K Bytes Flash memory. It contains the bootloader for In-
System Programming and the routines for In-System Application Programming.
This space can only be read or written by hardware mode using a parallel programming
tool.
Hardware Security Space
This space is composed of one byte: the Hardware Security Byte (HSB see Table 21)
divided in two separate nibbles see Table 21. The MSN contains the X2 mode configu-
ration bit and the Boot Loader Jump Bit as detailed in section “Boot Memory Execution”
and can be written by software while the LSN contains the lock system level to protect
the memory content against piracy as detailed in section “Hardware Security System”
and can only be written by hardware.
19
4173A–8051–08/02
Extra Row Space
This space is composed of two Bytes:
•
The Software Boot Vector (SBV see Table 22).
This byte is used by the software bootloader to build the boot address.
•
The Software Security Byte (SSB see Figure ).
This byte is used to lock the execution of some bootloader commands.
Hardware Security
System
The AT89C5132 implements three lock Bits LB2:0 in the LSN of HSB (see Table 21)
providing three levels of security for user’s program as described in Table 21 while the
AT83C5132 is always set in read disabled mode.
•
•
•
•
Level 0 is the level of an erased part and does not enable any security feature.
Level 1 locks the hardware programming of both user and boot memories.
Level 2 locks hardware verifying of both user and boot memories.
Level 3 locks the external execution.
Hardware
Verifying
Hardware
Programming
Software
Programming
Level
LB2(2)
LB1
U
LB0
U
Internal Execution External Execution
0
1
U
U
U
P
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
Enable
Enable
Disable
Disable
Enable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
U
P
2
P
X
3(3)
X
X
Notes: 1. U means unprogrammed, P means programmed and X means don’t care (programmed or unprogrammed).
2. LB2 is not implemented in the AT8xC5132 products.
3. AT89C5132 products are delivered with third level programmed to ensure that the code programmed by software using ISP
or user’s bootloader being secured from any hardware piracy.
Boot Memory Execution As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented
to allow boot memory to be mapped in the code space for execution at addresses from
F000h to FFFFh. The boot memory is enabled by setting the ENBOOT bit in AUXR1
(see Table 20). The three ways to set this bit are detailed in the following sections.
Software Boot Mapping
The software way to set ENBOOT consists in writing to AUXR1 from the user’s soft-
ware. This enables bootloader or API routines execution.
Hardware Condition Boot
Mapping
The hardware condition is based on the ISP pin. When driving this pin to low level, the
chip reset sets ENBOOT and forces the reset vector to F000h instead of 0000h in order
to execute the bootloader software.
As shown in Figure 14, the hardware condition always allows in-system recovery when
user’s memory has been corrupted.
Programmed Condition Boot
Mapping
The programmed condition is based on the Bootloader Jump Bit (BLJB) in HSB. As
shown in Figure 14, when this bit is programmed (by hardware or software programming
mode), the chip resets ENBOOT and forces the reset vector to F000h instead of 0000h,
in order to execute the bootloader software.
20
AT8xC5132
4173A–8051–08/02
AT8xC5132
Figure 14. Hardware Boot Process Algorithm
RESET
Hard Cond?
ISP = L?
Prog Cond?
BLJB = P?
Hard Cond Init
ENBOOT = 1
PC = F000h
FCON = 00h
Standard Init
ENBOOT = 0
PC = 0000h
FCON = F0h
Prog Cond Init
ENBOOT = 1
PC = F000h
FCON = F0h
User’s
Atmel’s
Application
Boot Loader
The software process (bootloader) is detailed in the section “In-System and In-Applica-
tion Programming”.
Preventing Flash Corruption
See “Reset Recommendation to Prevent Flash Corruption” on page 46 in the section
“Power Management”.
21
4173A–8051–08/02
Registers
Table 20. AUXR1 Register
AUXR1 (S:A2h) – Auxiliary Register 1
7
-
6
-
5
4
-
3
2
0
1
-
0
ENBOOT
GF3
DPS
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
-
The values read from these Bits are indeterminate. Do not set these Bits.
Enable Boot Flash
Set this bit to map the boot Flash in the code space between at addresses F000h
to FFFFh.
5
ENBOOT
Clear this bit to disable boot Flash.
Reserved
4
3
-
The values read from this bit is indeterminate. Do not set this bit.
General Flag
This bit is a general-purpose user flag.
GF3
Always Zero
2
1
0
0
-
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
Reserved for Data Pointer Extension.
Data Pointer Select Bit
Set to select second data pointer: DPTR1.
Clear to select first data pointer: DPTR0.
DPS
Reset Value = XXXX 00X0b
22
AT8xC5132
4173A–8051–08/02
AT8xC5132
Hardware Bytes
Table 21. HSB Byte – Hardware Security Byte
7
6
5
-
4
-
3
-
2
1
0
X2B
BLJB
LB2
LB1
LB0
Bit
Bit
Number
Mnemonic Description
X2 Bit
7
6
X2B(1)(2) Program this bit to start in X2 mode.
Unprogram (erase) this bit to start in standard mode.
Boot Loader Jump Bit
Program this bit to execute the bootloader at address F000h on next reset.
Unprogram (erase) this bit to execute user’s application at address 0000h on
next reset.
BLJB
Reserved
5 - 4
-
The values read from these Bits are always unprogrammed. Do not program
these Bits.
Reserved
3
The values read from this bit is always unprogrammed. Do not program this bit.
Hardware Lock Bits
Refer to Table 21 for Bits description.
2 - 0(3)
LB2:0
Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase.
Notes: 1. X2B initializes the X2 bit in CKCON during the reset phase.
2. Using the AT89C5132 (Flash Version) the system can boot either in standard or X2
mode depending on the X2B value. Using AT83C5132 (ROM Version) the system
always boots in standard mode. X2B bit can be changed to X2 mode later by
software.
3. Bits 0 to 3 (MSN) can only be programmed by hardware mode.
Table 22. SBV Byte – Software Boot Vector
7
6
5
4
3
2
1
0
ADD15
ADD14
ADD13
ADD12
ADD11
ADD10
ADD9
ADD8
Bit
Bit
Number
Mnemonic Description
MSB of the user’s bootloader 16-bit address location
7 - 0
ADD15:8 Refer to the AT8xC5132 datasheet for usage information (bootloader
dependent).
Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.
Table 23. SSB Byte – Software Security Byte
7
6
5
4
3
2
1
0
SSB7
SSB6
SSB5
SSB4
SSB3
SSB2
SSB1
SSB0
Bit
Bit
Number
Mnemonic Description
Software Security Byte Data
7 - 0
SSB7:0
Refer to the AT8xC5132 datasheet for usage information (bootloader
dependent).
Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.
23
4173A–8051–08/02
Data Memory
The AT8xC5132 provides data memory access in two different spaces:
1. The internal space mapped in three separate segments:
–
–
–
The lower 128 Bytes RAM segment
The upper 128 Bytes RAM segment
The expanded 2048 Bytes RAM segment
2. The external space.
A fourth internal segment is available but dedicated to Special Function Registers,
SFRs, (addresses 80h to FFh) accessible by direct addressing mode. For information
on this segment, refer to the section “Special Function Registers”, page 31.
Figure 15 shows the internal and external data memory spaces organization.
Figure 15. Internal and External Data Memory Organization
FFFFh
64K Bytes
External XRAM
7FFh
FFh
FFh
80h
Upper
128 Bytes
Special
Function
Internal RAM
indirect addressing
Registers
direct addressing
2K Bytes
Internal ERAM
EXTRAM = 0
80h
7Fh
Lower
128 Bytes
Internal RAM
direct or indirect
addressing
0800h
0000h
EXTRAM = 1
00h
00h
Internal Space
Lower 128 Bytes RAM
The lower 128 Bytes of RAM (see Figure 16) are accessible from address 00h to 7Fh
using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4
banks of 8 registers (R0 to R7). Two Bits RS0 and RS1 in PSW register (see Table 27)
select which bank is in use according to Table 24. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct address-
ing, and can be used for context switching in interrupt service routines.
Table 24. Register Bank Selection
RS1
RS0
Description
0
0
1
1
0
1
0
1
Register bank 0 from 00h to 07h
Register bank 1 from 08h to 0Fh
Register bank 2 from 10h to 17h
Register bank 3 from 18h to 1Fh
The next 16 Bytes above the register banks form a block of bit-addressable memory
space. The C51 instruction set includes a wide selection of single-bit instructions, and
the 128 Bits in this area can be directly addressed by these instructions. The bit
addresses in this area are 00h to 7Fh.
24
AT8xC5132
4173A–8051–08/02
AT8xC5132
Figure 16. Lower 128 Bytes Internal RAM Organization
7Fh
30h
2Fh
Bit-Addressable Space
(Bit Addresses 0 - 7Fh)
20h
18h
10h
08h
00h
1Fh
17h
0Fh
07h
4 Banks of
8 Registers
R0 - R7
Upper 128 Bytes RAM
Expanded RAM
The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
addressing mode.
The on-chip 2K Bytes of expanded RAM (ERAM) are accessible from address 0000h to
07FFh using indirect addressing mode through MOVX instructions. In this address
range, EXTRAM bit in AUXR register (see Table 28) is used to select the ERAM
(default) or the XRAM. As shown in Figure 15 when EXTRAM = 0, the ERAM is selected
and when EXTRAM = 1, the XRAM is selected.
The ERAM memory can be resized using XRS1:0 Bits in AUXR register to dynamically
increase external access to the XRAM space. Table 25 details the selected ERAM size
and address range.
Table 25. ERAM Size Selection
XRS1
XRS0
ERAM Size
256 Bytes
512 Bytes
1K Byte
Address
0
0
1
1
0
1
0
1
0 to 00FFh
0 to 01FFh
0 to 03FFh
0 to 07FFh
2K Bytes
Note:
Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile
memory cells. This means that the RAM content is indeterminate after power-up and
must then be initialized properly.
25
4173A–8051–08/02
External Space
Memory Interface
The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (RD, WR, and ALE).
Figure 17 shows the structure of the external address bus. P0 carries address A7:0
while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 26
describes the external memory interface signals.
Figure 17. External Data Memory Interface Structure
RAM
AT8xC5132
PERIPHERAL
A15:8
P2
ALE
P0
A15:8
AD7:0
Latch A7:0
A7:0
D7:0
RD#
OE
WR#
WR
Table 26. External Data Memory Interface Signals
Signal
Name
Alternate
Function
Type Description
Address Lines
Upper address lines for the external bus.
A15:8
O
P2.7:0
P0.7:0
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
AD7:0
ALE
I/O
O
Address Latch Enable
ALE signals indicates that valid address information are available on lines
AD7:0.
-
Read
RD#
O
O
P3.7
P3.6
Read signal output to external data memory.
Write
WR#
Write signal output to external memory.
Page Access Mode
The AT8xC5132 implement a feature called “Page Access” that disables the output of
DPH on P2 when executing MOVX @DPTR instruction. Page Access is enable by set-
ting the DPHDIS bit in AUXR register.
Page Access is useful when application uses both ERAM and 256 Bytes of XRAM. In
this case, software intensively modifies the EXTRAM bit to select access to ERAM or
XRAM and must save it if it is used in the interrupt service routine. Page Access allows
external access above 00FFh address without generating DPH on P2. Thus ERAM is
accessed using MOVX @Ri or MOVX @DPTR with DPTR < 0100h, and XRAM is
accessed using MOVX @DPTR with DPTR ≥ 0100h while keeping P2 for general-pur-
pose I/O usage.
26
AT8xC5132
4173A–8051–08/02
AT8xC5132
External Bus Cycles
This section describes the bus cycles that AT8xC5132 execute to read (see Figure 18),
and write data (see Figure 19) in the external data memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further
information on X2 mode, refer to the section “X2 Feature”, page 12.
Slow peripherals can be accessed by stretching the read and write cycles. This is done
using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR
signals from 3 to 15 CPU clock periods.
For simplicity, the accompanying figures depict the bus cycle waveforms in idealized
form and do not provide precise timing information. For bus cycle timing parameters
refer to the section “AC Characteristics”.
Figure 18. External Data Read Waveforms
CPU Clock
ALE
RD#(1)
DPL or Ri
D7:0
P0
P2
DPH or P2(2),(3)
P2
Notes: 1. RD signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),
P2 outputs SFR content instead of DPH.
Figure 19. External Data Write Waveforms
CPU Clock
ALE
WR(1)
DPL or Ri
D7:0
P0
P2
DPH or P2(2),(3)
P2
Notes: 1. WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),
P2 outputs SFR content instead of DPH.
27
4173A–8051–08/02
Dual Data Pointer
Description
The AT8xC5132 implement a second data pointer for speeding up code execution and
reducing code size in case of intensive usage of external memory accesses.
DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR
addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1
register (see Table 29) is used to select whether DPTR is the data pointer 0 or the data
pointer 1 (see Figure 20).
Figure 20. Dual Data Pointer Implementation
0
1
DPL0
DPL1
DPL
DPTR0
DPTR1
AUXR1.0
DPTR
DPS
0
1
DPH0
DPH1
DPH
Application
Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare, search …) are well
served by using one data pointer as a “source” pointer and the other one as a “destina-
tion” pointer.
Below is an example of block move implementation using the two pointers and coded in
assembler. The latest C compiler also takes advantage of this feature by providing
enhanced algorithm libraries.
The INC instruction is a short (2 Bytes) and fast (6 CPU clocks) way to manipulate the
DPS bit in the AUXR1 register. However, note that the INC instruction does not directly
forces the DPS bit to a particular state, but simply toggles it. In simple routines, such as
the block move example, only the fact that DPS is toggled in the proper sequence mat-
ters, not its actual value. In other words, the block move routine works the same whether
DPS is “0” or “1” on entry.
; ASCII block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; Ends when encountering NULL character
; Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added
AUXR1EQU0A2h
move:movDPTR,#SOURCE ; address of SOURCE
incAUXR1 ; switch data pointers
movDPTR,#DEST ; address of DEST
mv_loop:incAUXR1; switch data pointers
movxA,@DPTR; get a byte from SOURCE
incDPTR; increment SOURCE address
incAUXR1; switch data pointers
movx@DPTR,A; write the byte to DEST
incDPTR; increment DEST address
jnzmv_loop; check for NULL terminator
end_move:
28
AT8xC5132
4173A–8051–08/02
AT8xC5132
Registers
Table 27. PSW Register
PSW (S:8Eh) – Program Status Word Register
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Bit
Bit
Number
Mnemonic Description
Carry Flag
Carry out from bit 1 of ALU operands.
7
CY
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
6
5
AC
F0
User Definable Flag 0.
Register Bank Select Bits
Refer to Table 24 for Bits description.
4 - 3
RS1:0
Overflow Flag
Overflow set by arithmetic operations.
2
1
OV
F1
User Definable Flag 1
Parity Bit
0
P
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
Reset Value = 0000 0000b
29
4173A–8051–08/02
Table 28. AUXR Register
AUXR (S:8Eh) – Auxiliary Control Register
7
-
6
5
4
3
2
1
0
EXT16
M0
DPHDIS
XRS1
XRS0
EXTRAM
AO
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The values read from this bit is indeterminate. Do not set this bit.
External 16-bit Access Enable Bit
Set to enable 16-bit access mode during MOVX instructions.
Clear to disable 16-bit access mode and enable standard 8-bit access mode
during MOVX instructions.
EXT16
M0
External Memory Access Stretch Bit
Set to stretch RD or WR signals duration to 15 CPU clock periods.
Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.
5
DPH Disable Bit
4
DPHDIS Set to disable DPH output on P2 when executing MOVX @DPTR instruction.
Clear to enable DPH output on P2 when executing MOVX @DPTR instruction.
Expanded RAM Size Bits
XRS1:0
3 - 2
Refer to Table 25 for ERAM size description.
External RAM Enable Bit
Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR
EXTRAM instructions.
1
0
Clear to select the internal expanded RAM when executing MOVX @Ri or MOVX
@DPTR instructions.
ALE Output Enable Bit
AO
Set to output the ALE signal only during MOVX instructions.
Clear to output the ALE signal at a constant rate of FCPU/3.
Reset Value = X000 1101b
Table 29. AUXR1 Register
AUXR1 (S:A2h) – Auxiliary Control Register 1
7
-
6
-
5
-
4
-
3
2
0
1
-
0
GF3
DPS
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 4
3
-
The values read from these Bits are indeterminate. Do not set these Bits.
GF3
0
General Purpose Flag 3.
Always Zero
2
1
0
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
-
Reserved for Data Pointer Extension.
Data Pointer Select Bit
Set to select second data pointer: DPTR1.
Clear to select first data pointer: DPTR0.
DPS
Reset Value = XXXX 00X0b
30
AT8xC5132
4173A–8051–08/02
AT8xC5132
Special Function
Registers
The Special Function Registers (SFRs) of the AT8xC5132 derivatives fall into the cate-
gories detailed in Table 30 to Table 45. The relative addresses of these SFRs are
provided together with their reset values in Table 46. In this table, the bit-addressable
registers are identified by Note 1.
Table 30. C51 Core SFRs
Mnemonic
ACC
B
Add Name
7
6
5
4
3
2
1
0
E0h Accumulator
–
–
–
–
–
–
–
–
F0h B Register
–
CY
–
–
AC
–
–
F0
–
–
RS1
–
–
RS0
–
–
OV
–
–
F1
–
–
P
–
–
–
PSW
SP
D0h Program Status Word
81h Stack Pointer
DPL
82h Data Pointer Low byte
83h Data Pointer High byte
–
–
–
–
–
–
–
DPH
–
–
–
–
–
–
–
Table 31. System Management SFRs
Mnemonic
Add Name
7
6
5
–
4
3
2
1
PD
0
PCON
87h Power Control
8Eh Auxiliary Register 0
A2h Auxiliary Register 1
FBh Version Number
SMOD1
SMOD0
EXT16
–
–
DPHDIS
–
GF1
XRS1
GF3
NV3
GF0
XRS0
0
IDL
AO
AUXR
–
–
M0
EXTRAM
–
AUXR1
NVERS
ENBOOT
NV5
DPS
NV0
NV7
NV6
NV4
NV2
NV1
Table 32. PLL and System Clock SFRs
Mnemonic
Add Name
7
6
5
4
3
–
2
1
–
0
X2
CKCON
8Fh Clock Control
E9h PLL Control
EEh PLL N Divider
EFh PLL R Divider
–
–
–
–
–
PLLCON
PLLNDIV
PLLRDIV
R1
–
R0
N6
R8
–
–
PLLRES
N3
v
PLLEN
N1
PLOCK
N0
N5
R7
N4
R6
N2
R4
R9
R5
R3
R2
Table 33. Interrupt SFRs
Mnemonic
Add Name
7
EA
–
6
5
–
–
–
–
–
–
4
3
2
1
0
IEN0
A8h Interrupt Enable Control 0
B1h Interrupt Enable Control 1
B7h Interrupt Priority Control High 0
B8h Interrupt Priority Control Low 0
B3h Interrupt Priority Control High 1
B2h Interrupt Priority Control Low 1
EAUD
ES
ET1
EX1
ET0
EX0
IEN1
IPH0
IPL0
IPH1
IPL1
EUSB
EKB
IPHS
IPLS
IPHKB
IPLKB
EADC
IPHT1
IPLT1
IPHADC
IPLADC
ESPI
EI2C
EMMC
IPHX0
IPLX0
IPHMMC
IPLMMC
–
IPHAUD
IPLAUD
IPHUSB
IPLUSB
IPHX1
IPLX1
IPHSPI
IPLSPI
IPHT0
IPLT0
IPHI2C
IPLI2C
–
–
–
31
4173A–8051–08/02
Table 34. Port SFRs
Mnemonic
Add Name
7
6
5
4
3
2
1
0
P0
80h 8-bit Port 0
90h 8-bit Port 1
A0h 8-bit Port 2
B0h 8-bit Port 3
C0h 8-bit Port 4
D8h 4-bit Port 5
–
–
–
–
–
–
–
–
P1
P2
P3
P4
P5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Table 35. Flash Memory SFR
Mnemonic
Add Name
7
6
5
4
3
2
1
0
FCON
D1h Flash Control
FPL3
FPL2
FPL1
FPL0
FPS
FMOD1
FMOD0
FBUSY
Table 36. Timer SFRs
Mnemonic
TCON
TMOD
TL0
Add Name
7
6
5
TF0
M11
–
4
TR0
M01
–
3
2
1
0
88h Timer/Counter 0 and 1 Control
89h Timer/Counter 0 and 1 Modes
8Ah Timer/Counter 0 Low Byte
8Ch Timer/Counter 0 High Byte
8Bh Timer/Counter 1 Low Byte
8Dh Timer/Counter 1 High Byte
A6h WatchDog Timer Reset
A7h WatchDog Timer Program
TF1
TR1
IE1
IT1
IE0
IT0
GATE1
C/T1#
GATE0
C/T0#
M10
M00
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
TH0
–
–
–
–
–
TL1
–
–
–
–
–
TH1
–
–
–
–
–
–
–
–
WDTRST
WDTPRG
–
–
–
–
WTO2
WTO1
WTO0
Table 37. Audio Interface SFRs
Mnemonic
AUDCON0
AUDCON1
AUDSTA
Add Name
7
6
5
4
3
2
1
0
9Ah Audio Control 0
9Bh Audio Control 1
9Ch Audio Status
9Dh Audio Data
JUST4
SRC
SREQ
AUD7
–
JUST3
DRQEN
UDRN
AUD6
–
JUST2
MSREQ
AUBUSY
AUD5
–
JUST1
MUDRN
–
JUST0
–
POL
DUP1
–
DSIZ
DUP0
–
HLR
AUDEN
–
–
AUDDAT
AUD4
AUCD4
AUD3
AUCD3
AUD2
AUCD2
AUD1
AUCD1
AUD0
AUCD0
AUDCLK
ECh Audio Clock Divider
32
AT8xC5132
4173A–8051–08/02
AT8xC5132
Table 38. USB Controller SFRs
Mnemonic Add Name
7
6
5
SDRMWUP
UADD5
WUPCPU
EWUPCPU
–
4
3
2
1
0
USBCON
USBADDR
USBINT
BCh USB Global Control
USBE
SUSPCLK
–
UPRSM
UADD3
SOFINT
ESOFINT
–
RMWUPE
UADD2
–
CONFG
UADD1
–
FADDEN
UADD0
SPINT
C6h USB Address
FEN
UADD6
UADD4
BDh USB Global Interrupt
BEh USB Global Interrupt Enable
C7h USB Endpoint Number
D4h USB Endpoint X Control
CEh USB Endpoint X Status
D5h USB Endpoint Reset
EORINT
–
–
USBIEN
EEORINT
ESPINT
EPNUM0
EPTYPE0
TXCMP
EP0RST
EP0INT
EP0INTE
FDAT0
–
–
–
–
UEPNUM
UEPCONX
UEPSTAX
UEPRST
UEPINT
EPNUM1
EPTYPE1
RXOUT
EP1RST
EP1INT
EP1INTE
FDAT1
BYCT1
FNUM1
FNUM9
USBCD1
–
–
–
–
EPEN
DTGL
EPDIR
RXSETUP
EP2RST
EP2INT
EP2INTE
FDAT2
BYCT2
FNUM2
FNUM10
–
–
–
–
TXRDY
–
DIR
STALLRQ
–
STLCRC
EP3RST
EP3INT
EP3INTE
FDAT3
BYCT3
FNUM3
–
–
–
–
F8h USB Endpoint Interrupt
C2h USB Endpoint Interrupt Enable
CFh USB Endpoint X FIFO Data
E2h USB Endpoint X Byte Counter
BAh USB Frame Number Low
BBh USB Frame Number High
EAh USB Clock Divider
–
–
–
–
–
UEPIEN
–
–
–
UEPDATX
UBYCTX
UFNUML
UFNUMH
USBCLK
FDAT7
FDAT6
BYCT6
FNUM6
–
FDAT5
BYCT5
FNUM5
CRCOK
–
FDAT4
BYCT4
FNUM4
CRCERR
–
BYCT0
–
FNUM7
FNUM0
FNUM8
USBCD0
–
–
–
–
Table 39. MMC Controller SFRs
Mnemonic
MMCON0
MMCON1
MMCON2
MMSTA
Add Name
7
6
5
4
3
2
1
0
E4h MMC Control 0
E5h MMC Control 1
E6h MMC Control 2
DEh MMC Control and Status
E7h MMC Interrupt
DFh MMC Interrupt Mask
DDh MMC Command
DCh MMC Data
DRPTR
BLEN3
MMCEN
–
DTPTR
BLEN2
DCR
CRPTR
BLEN1
CCR
CTPTR
BLEN0
–
MBLOCK
DATDIR
–
DFMT
DATEN
DATD1
CRC7S
F1FI
RFMT
RESPEN
DATD0
RESPFS
F2EI
CRCDIS
CMDEN
FLOWC
CFLCK
F1EI
–
CBUSY
EOCI
CRC16S
EOFI
DATFS
F2FI
MMINT
MCBI
MCBM
MC7
EORI
EORM
MC6
MMMSK
MMCMD
MMDAT
EOCM
MC5
EOFM
MC4
F2FM
MC3
F1FM
MC2
F2EM
MC1
F1EM
MC0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MMCLK
EDh MMC Clock Divider
MMCD7
MMCD6
MMCD5
MMCD4
MMCD3
MMCD2
MMCD1
MMCD0
Table 40. IDE Interface SFR
Mnemonic
Add Name
7
6
5
4
3
2
1
0
DAT16H
F9h High Order Data Byte
D15
D14
D13
D12
D11
D10
D9
D8
33
4173A–8051–08/02
Table 41. Serial I/O Port SFRs
Mnemonic
Add Name
7
6
SM1
–
5
SM2
–
4
REN
–
3
2
1
TI
–
0
RI
–
SCON
98h Serial Control
FE/SM0
TB8
RB8
SBUF
99h Serial Data Buffer
B9h Slave Address Mask
A9h Slave Address
92h Baud Rate Control
91h Baud Rate Reload
–
–
–
–
–
–
–
SADEN
SADDR
BDRCON
BRL
–
–
–
–
–
–
–
–
–
–
–
TBCK
–
–
RBCK
–
–
–
–
–
BRR
–
SPD
–
SRC
–
–
–
Table 42. SPI Controller SFRs
Mnemonic
SPCON
SPSTA
Add Name
7
6
5
4
3
2
1
0
C3h SPI Control
C4h SPI Status
C5h SPI Data
SPR2
SPIF
SPD7
SPEN
WCOL
SPD6
SSDIS
–
MSTR
MODF
SPD4
CPOL
–
CPHA
–
SPR1
–
SPR0
–
SPDAT
SPD5
SPD3
SPD2
SPD1
SPD0
Table 43. Special Register
Mnemonic
SSCON
SSSTA
Add Name
7
6
5
4
3
2
1
0
93h Reserved
94h Reserved
95h Reserved
96h Reserved
SSCR2
SSC4
SSD7
SSA7
SSPE
SSC3
SSD6
SSA6
SSSTA
SSC2
SSD5
SSA5
SSSTO
SSC1
SSD4
SSA4
SSI
SSAA
0
SSCR1
0
SSCR0
0
SSC0
SSD3
SSA3
SSDAT
SSD2
SSA2
SSD1
SSA1
SSD0
SSGC
SSADR
Table 44. Keyboard Interface SFRs
Mnemonic
Add Name
7
6
KINL2
–
5
KINL1
–
4
KINL0
–
3
2
1
0
KBCON
A3h Keyboard Control
A4h Keyboard Status
KINL3
KPDE
KINM3
KINF3
KINM2
KINF2
KINM1
KINF1
KINM0
KINF0
KBSTA
Table 45. A/D Controller SFRs
Mnemonic
ADCON
ADCLK
ADDL
Add Name
7
6
ADIDL
–
5
ADEN
–
4
3
2
–
1
0
F3h ADC Control
–
ADEOC
ADCD4
–
ADSST
ADCD3
–
–
ADCS
ADCD0
ADAT0
ADAT2
F2h ADC Clock Divider
F4h ADC Data Low Byte
F5h ADC Data High Byte
–
–
ADCD2
–
ADCD1
ADAT1
ADAT3
–
–
ADDH
ADAT9
ADAT8
ADAT7
ADAT6
ADAT5
ADAT4
34
AT8xC5132
4173A–8051–08/02
AT8xC5132
Table 46. SFR Addresses and Reset Values
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
UEPINT
0000 0000
DAT16H
XXXX XXXX
NVERS(2)
1000 0010
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
FFh
B(1)
0000 0000
ADCLK
0000 0000
ADCON
0000 0000
ADDL
0000 0000
ADDH
0000 0000
F7h
PLLCON
0000 1000
USBCLK
0000 0000
AUDCLK
0000 0000
MMCLK
0000 0000
PLLNDIV
0000 0000
PLLRDIV
EFh
0000 0000
ACC(1)
UBYCTLX
0000 0000
MMCON0
0000 0000
MMCON1
0000 0000
MMCON2
0000 0000
MMINT
E7h
0000 0011
0000 0000
P5(1)
XXXX 1111
MMDAT
1111 1111
MMCMD
1111 1111
MMSTA
0000 0000
MMMSK
DFh
1111 1111
PSW1
0000 0000
FCON(3)
UEPCONX
0000 0000
UEPRST
0000 0000
D7h
1111 0000(4)
UEPSTAX
0000 0000
UEPDATX
CFh
0000 0000
P4(1)
1111 1111
UEPIEN
0000 0000
SPCON
0001 0100
SPSTA
0000 0000
SPDAT
XXXX XXXX
USBADDR
1000 0000
UEPNUM
C7h
0000 0000
IPL0(1)
X000 0000
SADEN
0000 0000
UFNUML
0000 0000
UFNUMH
0000 0000
USBCON
0000 0000
USBINT
0000 0000
USBIEN
0001 0000
BFh
P3(1)
1111 1111
IEN1
0000 0000
IPL1
0000 0000
IPH1
0000 0000
IPH0
B7h
X000 0000
IEN0(1)
0000 0000
SADDR
0000 0000
AFh
P2(1)
1111 1111
AUXR1
XXXX 00X0
KBCON
0000 1111
KBSTA
0000 0000
WDTRST
XXX XXXX
WDTPRG
A7h
XXXX X000
SCON
0000 0000
SBUF
XXXX XXXX
AUDCON0
0000 1000
AUDCON1
1011 0010
AUDSTA
1100 0000
AUDDAT
1111 1111
9Fh
97h
P1(1)
1111 1111
BRL
0000 0000
BDRCON
XXX0 0000
SSCON
0000 0000
SSSTA
1111 1000
SSDAT
1111 1111
SSADR
1111 1110
TCON(1)
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
X000 1101
CKCON
8Fh
0000 000X(5)
0000 0000
P0(1)
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
PCON
87h
XXXX 0000
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
Reserved
Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.
2. NVERS reset value depends on the silicon version.
3. FCON register is only available in AT89C5132 product.
4. FCON reset value is 00h in case of reset with hardware condition.
5. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte.
35
4173A–8051–08/02
Interrupt System
The AT8xC5132, like other control-oriented computer architectures, employ a program
interrupt method. This operation branches to a subroutine and performs some service in
response to the interrupt. When the subroutine terminates, execution resumes at the
point where the interrupt occurred. Interrupts may occur as a result of internal
AT8xC5132 activity (e.g., timer overflow) or at the initiation of electrical signals external
to the microcontroller (e.g., keyboard). In all cases, interrupt operation is programmed
by the system designer, who determines priority of interrupt service relative to normal
code execution and other interrupt service routines. All of the interrupt sources are
enabled or disabled by the system designer and may be manipulated dynamically.
A typical interrupt event chain occurs as follows:
1. An internal or external device initiates an interrupt-request signal. The
AT8xC5132, latch this event into a flag buffer.
2. The priority of the flag is compared to the priority of other interrupts by the inter-
rupt handler. A high priority causes the handler to set an interrupt flag.
3. This signals the instruction execution unit to execute a context switch. This con-
text switch breaks the current flow of instruction sequences. The execution unit
completes the current instruction prior to a save of the program counter (PC) and
reloads the PC with the start address of a software service routine.
4. The software service routine executes assigned tasks and as a final activity per-
forms a RETI (return from interrupt) instruction. This instruction signals
completion of the interrupt, resets the interrupt-in-progress priority and reloads
the program counter. Program operation then continues from the original point of
interruption.
Table 47. Interrupt System Signals
Signal
Name
Alternate
Function
Type Description
External Interrupt 0
See Section "External Interrupts", page 39.
INT0
INT1
I
I
I
P3.2
P3.3
External Interrupt 1
See Section “External Interrupts”, page 39.
Keyboard Interrupt Inputs
See Section “Keyboard Interface”, page 134.
KIN3:0
P1.3:0
Six interrupt registers are used to control the interrupt system. Two 8-bit registers are
used to enable separately the interrupt sources: IEN0 and IEN1 registers (see Table 50
and Table 51).
Four 8-bit registers are used to establish the priority level of the thirteen sources: IPH0,
IPL0, IPH1 and IPL1 registers (see Table 52 to Table 55).
Interrupt System
Priorities
Each of the eleven interrupt sources on the AT8xC5132 can be individually programmed
to one of four priority levels. This is accomplished by one bit in the Interrupt Priority High
registers (IPH0 and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and
IPL1). This provides each interrupt source four possible priority levels according to
Table 48.
36
AT8xC5132
4173A–8051–08/02
AT8xC5132
Table 48. Priority Levels
IPHxx
IPLxx
Priority Level
0
0
1
1
0
1
0
1
0 Lowest
1
2
3 Highest
A low-priority interrupt is always interrupted by a higher priority interrupt but not by
another interrupt of lower or equal priority. Higher priority interrupts are serviced before
lower priority interrupts. The response to simultaneous occurrence of equal priority inter-
rupts is determined by an internal hardware polling sequence detailed in Table 49. Thus
within each priority level there is a second priority structure determined by the polling
sequence. The interrupt control system is shown in Figure 21.
Table 49. Priority Within Same Level
Interrupt Request Flag
Interrupt Address
Vectors
Cleared by Hardware
(H) or by Software (S)
Interrupt Name
INT0
Priority Number
1 (Highest Priority)
C:0003h
C:000Bh
C:0013h
C:001Bh
C:0023h
C:0033h
C:003Bh
C:004Bh
C:0053h
C:005Bh
C:0063h
C:006Bh
C:0073h
H if edge, S if level
Timer 0
2
H
INT1
3
H if edge, S if level
Timer 1
4
H
S
S
S
S
S
S
-
Serial Port
Audio Interface
MMC Interface
SPI Controller
A-to-D Converter
Keyboard
Reserved
USB
5
7
8
10
11
12
13
14
S
-
Reserved
15 (Lowest Priority)
37
4173A–8051–08/02
Figure 21. Interrupt Control System
Highest
Priority
00
01
10
11
External
Interrupts
INT0
Interrupt 0
EX0
IEN0.0
00
01
10
11
Timer 0
ET0
IEN0.1
00
01
10
11
External
Interrupt 1
INT1
EX1
IEN0.2
00
01
10
11
Timer 1
ET1
IEN0.3
00
01
10
11
TXD
Serial
Port
RXD
ES
IEN0.4
00
01
10
11
Audio
Interface
EAUD
IEN0.6
00
01
10
11
MCLK
MDAT
MCMD
MMC
Controller
EI2C
IEN1.1
00
01
10
11
SCK
SI
SO
SPI
Controller
ESPI
IEN1.2
00
01
10
11
A-to-D
Converter
AIN1:0
EADC
IEN1.3
00
01
10
11
Keyboard
KIN3:0
EKB
IEN1.4
00
01
10
11
D+
USB
Controller
D-
EUSB
IEN1.6
EA
IEN0.7
IPH/L
Interrupt Enable
Priority Enable
Lowest Priority Interrupts
38
AT8xC5132
4173A–8051–08/02
AT8xC5132
External Interrupts
INT1:0# Inputs
External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to
be level-triggered or edge-triggered, dependent upon Bits IT0 and IT1 (ITn, n = 0 or 1) in
TCON register as shown in Figure 22. If ITn = 0, INTn is triggered by a low level at the
pin. If ITn = 1, INTn is negative-edge triggered. External interrupts are enabled with Bits
EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the interrupt request flag IEn
in TCON register. If the interrupt is edge-triggered, the request flag is cleared by hard-
ware when vectoring to the interrupt service routine. If the interrupt is level-triggered, the
interrupt service routine must clear the request flag and the interrupt must be deas-
serted before the end of the interrupt service routine.
INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low
level signals as detailed in Section “Exiting Power-down Mode”, page 48.
Figure 22. INT1:0# Input Circuitry
0
1
INT0/1#
Interrupt
Request
INT0/1#
IE0/1
TCON.1/3
EX0/1
IEN0.0/2
IT0/1
TCON.0/2
KIN3:0 Inputs
External interrupts KIN0 to KIN3 provide the capability to connect a matrix keyboard. For
detailed information on these inputs, refer to Section “Keyboard Interface”, page 134.
Input Sampling
External interrupt pins (INT1:0 and KIN3:0) are sampled once per peripheral cycle (6
peripheral clock periods) (see Figure 23). A level-triggered interrupt pin held low or high
for more than 6 peripheral clock periods (12 oscillator in standard mode or 6 oscillator
clock periods in X2 mode) guarantees detection. Edge-triggered external interrupts
must hold the request pin low for at least 6 peripheral clock periods.
Figure 23. Minimum Pulse Timings
Level-Triggered Interrupt
> 1 peripheral cycle
1 cycle
Edge-Triggered Interrupt
> 1 peripheral cycle
1 cycle
1 cycle
39
4173A–8051–08/02
Registers
Table 50. IEN0 Register
IEN0 (S:A8h) – Interrupt Enable Register 0
7
6
5
4
3
2
1
0
EA
EAUD
–
ES
ET1
EX1
ET0
EX0
Bit
Bit
Number
Mnemonic Description
Enable All Interrupt Bit
Set to enable all interrupts.
Clear to disable all interrupts.
7
EA
If EA = 1, each interrupt source is individually enabled or disabled by setting or
clearing its interrupt enable bit.
Audio Interface Interrupt Enable Bit
Set to enable audio interface interrupt.
Clear to disable audio interface interrupt.
6
5
4
EAUD
–
Reserved
The values read from this bit is always 0. Do not set this bit.
Serial Port Interrupt Enable Bit
Set to enable serial port interrupt.
Clear to disable serial port interrupt.
ES
Timer 1 Overflow Interrupt Enable Bit
Set to enable Timer 1 overflow interrupt.
Clear to disable Timer 1 overflow interrupt.
3
2
1
0
ET1
EX1
ET0
EX0
External Interrupt 1 Enable bit
Set to enable external interrupt 1.
Clear to disable external interrupt 1.
Timer 0 Overflow Interrupt Enable Bit
Set to enable timer 0 overflow interrupt.
Clear to disable timer 0 overflow interrupt.
External Interrupt 0 Enable Bit
Set to enable external interrupt 0.
Clear to disable external interrupt 0.
Reset Value = 0000 0000b
40
AT8xC5132
4173A–8051–08/02
AT8xC5132
Table 51. IEN1 Register
IEN1 (S:B1h) – Interrupt Enable Register 1
7
-
6
5
4
3
2
1
0
EUSB
–
EKB
EADC
ESPI
EI2C
EMMC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
-
The values read from this bit is always 0. Do not set this bit.
USB Interface Interrupt Enable Bit
Set this bit to enable USB interrupts.
Clear this bit to disable USB interrupts.
EUSB
–
Reserved
The values read from this bit is always 0. Do not set this bit.
Keyboard Interface Interrupt Enable Bit
Set to enable Keyboard interrupt.
EKB
Clear to disable Keyboard interrupt.
A-to-D Converter Interrupt Enable Bit
Set to enable ADC interrupt.
3
EADC
Clear to disable ADC interrupt.
SPI Controller Interrupt Enable Bit
Set to enable SPI interrupt.
Clear to disable SPI interrupt.
2
1
0
ESPI
EI2C
Reserved
The values read from this bit is always 0. Do not set this bit.
MMC Interface Interrupt Enable Bit
Set to enable MMC interrupt.
EMMC
Clear to disable MMC interrupt.
Reset Value = 0000 0000b
41
4173A–8051–08/02
Table 52. IPH0 Register
IPH0 (S:B7h) – Interrupt Priority High Register 0
7
-
6
5
4
3
2
1
0
IPHAUD
–
IPHS
IPHT1
IPHX1
IPHT0
IPHX0
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The values read from this bit is indeterminate. Do not set this bit.
Audio Interface Interrupt Priority Level MSB
Refer to Table 48 for priority level description.
IPHAUD
–
Reserved
The values read from this bit is always 0. Do not set this bit.
Serial Port Interrupt Priority Level MSB
Refer to Table 48 for priority level description.
IPHS
Timer 1 Interrupt Priority Level MSB
Refer to Table 48 for priority level description.
IPHT1
IPHX1
IPHT0
IPHX0
External Interrupt 1 Priority Level MSB
Refer to Table 48 for priority level description.
Timer 0 Interrupt Priority Level MSB
Refer to Table 48 for priority level description.
External Interrupt 0 Priority Level MSB
Refer to Table 48 for priority level description.
Reset Value = X000 0000b
42
AT8xC5132
4173A–8051–08/02
AT8xC5132
Table 53. IPH1 Register
IPH1 (S:B3h) – Interrupt Priority High Register 1
7
-
6
5
4
3
2
1
0
IPHUSB
–
IPHKB
IPHADC
IPHSPI
IPHI2C
IPHMMC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The values read from this bit is always 0. Do not set this bit.
USB Interrupt Priority Level MSB
Refer to Table 48 for priority level description.
IPHUSB
-
Reserved
The values read from this bit is always 0. Do not set this bit.
Keyboard Interrupt Priority Level MSB
Refer to Table 48 for priority level description.
IPHKB
IPHADC
IPHSPI
IPHI2C
IPHMMC
A-to-D Converter Interrupt Priority Level MSB
Refer to Table 48 for priority level description.
SPI Interrupt Priority Level MSB
Refer to Table 48 for priority level description.
Reserved
The values read from this bit is always 0. Do not set this bit.
MMC Interrupt Priority Level MSB
Refer to Table 48 for priority level description.
Reset Value = 0000 0000b
43
4173A–8051–08/02
Table 54. IPL0 Register
IPL0 (S:B8h) – Interrupt Priority Low Register 0
7
-
6
5
4
3
2
1
0
IPLAUD
–
IPLS
IPLT1
IPLX1
IPLT0
IPLX0
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The values read from this bit is indeterminate. Do not set this bit.
Audio Interface Interrupt Priority Level LSB
Refer to Table 48 for priority level description.
IPLAUD
–
Reserved
The values read from this bit is always 0. Do not set this bit.
Serial Port Interrupt Priority Level LSB
Refer to Table 48 for priority level description.
IPLS
Timer 1 Interrupt Priority Level LSB
Refer to Table 48 for priority level description.
IPLT1
IPLX1
IPLT0
IPLX0
External Interrupt 1 Priority Level LSB
Refer to Table 48 for priority level description.
Timer 0 Interrupt Priority Level LSB
Refer to Table 48 for priority level description.
External Interrupt 0 Priority Level LSB
Refer to Table 48 for priority level description.
Reset Value = X000 0000b
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AT8xC5132
Table 55. IPL1 Register
IPL1 (S:B2h) – Interrupt Priority Low Register 1
7
-
6
5
-
4
3
2
1
0
IPLUSB
IPLKB
IPLADC
IPLSPI
IPLI2C
IPLMMC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The values read from this bit is always 0. Do not set this bit.
USB Interrupt Priority Level LSB
Refer to Table 48 for priority level description.
IPLUSB
-
Reserved
The values read from this bit is always 0. Do not set this bit.
Keyboard Interrupt Priority Level LSB
Refer to Table 48 for priority level description.
IPLKB
IPLADC
IPLSPI
IPLI2C
IPLMMC
A-to-D Converter Interrupt Priority Level LSB
Refer to Table 48 for priority level description.
SPI Interrupt Priority Level LSB
Refer to Table 48 for priority level description.
Reserved
The values read from this bit is always 0. Do not set this bit.
MMC Interrupt Priority Level LSB
Refer to Table 48 for priority level description.
Reset Value = 0000 0000b
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4173A–8051–08/02
Power Management
Two power reduction modes are implemented in the AT8xC5132: the Idle mode and the
Power-down mode. In addition to these power reduction modes, the clocks of the core
and peripherals can be dynamically divided by 2 using the X2 mode detailed in
Section “X2 Feature”, page 12.
Reset
A reset is required after applying power at turn-on. To achieve a valid reset, the reset
signal must be maintained for at least 2 machine cycles (24 oscillator clock periods)
while the oscillator is running. A device reset initializes the AT8xC5132 and vectors the
CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset by
simply connecting an external capacitor to VDD as shown in Figure 24. Resistor value
and input characteristics are discussed in the Section “DC Characteristics”. The status
of the Port pins during reset is detailed in Table 56.
Figure 24. Reset Circuitry and Power-On Reset
VDD
To CPU core
and peripherals
RST
+
RST
VSS
a. RST input circuitry
b. Power-on Reset
Table 56. Pin Conditions in Special Operating Modes
Mode
Reset
Port 0
Floating
Data
Port 1
High
Port 2
High
Port 3
High
Port 4
High
Port 5
High
MMC
Floating
Data
Audio
1
Idle
Data
Data
Data
Data
Data
Data
Power-
down
Data
Data
Data
Data
Data
Data
Data
Data
Note:
1. Refer to Section “Audio Output Interface”, page 61.
Reset Recommendation A bad reset sequence will lead to bad microcontroller initialization and system registers
like SFR’s, Program Counter, etc. will not be correctly initialized. A bad initialization may
lead to unpredictable behaviour of the C51 microcontroller.
to Prevent Flash
Corruption
An example of this situation may occur in an instance where the bit ENBOOT in AUXR1
register is initialized from the hardware bit BLJB upon reset. Since this bit allows map-
ping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet
due to a bad reset) the bit ENBOOT in SFR’s may be set. If the value of Program
Counter is accidently in the range of the boot memory addresses then a Flash access
(write or erase) may corrupt the Flash on-chip memory .
It is recommended to use an external reset circuitry featuring power supply monitoring to
prevent system malfunction during periods of insufficient power supply voltage (power
supply failure, power supply switched off).
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AT8xC5132
Idle Mode
Idle mode is a power reduction mode that reduces the power consumption. In this mode,
program execution halts. Idle mode freezes the clock to the CPU at known states while
the peripherals continue to be clocked (refer to Section “Oscillator”, page 12). The CPU
status before entering Idle mode is preserved, i.e., the program counter and program
status word register retain their data for the duration of Idle mode. The contents of the
SFRs and RAM are also retained. The status of the Port pins during Idle mode is
detailed in Table 56.
Entering Idle Mode
Exiting Idle Mode
To enter Idle mode, the user must set the IDL bit in PCON register (see Table 57). The
AT8xC5132 enter Idle mode upon execution of the instruction that sets IDL bit. The
instruction that sets IDL bit is the last instruction executed.
Note:
If IDL bit and PD bit are set simultaneously, the AT8xC5132 enters Power-down mode.
Then they do not go in Idle mode when exiting Power-down mode.
There are two ways to exit Idle mode:
1. Generate an enabled interrupt.
–
Hardware clears IDL bit in PCON register which restores the clock to the
CPU. Execution resumes with the interrupt service routine. Upon completion
of the interrupt service routine, program execution resumes with the
instruction immediately following the instruction that activated Idle mode.
The general-purpose flags (GF1 and GF0 in PCON register) may be used to
indicate whether an interrupt occurred during normal operation or during Idle
mode. When Idle mode is exited by an interrupt, the interrupt service routine
may examine GF1 and GF0.
2. Generate a reset.
–
A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously. This restores the clock to the CPU. Program execution
momentarily resumes with the instruction immediately following the
instruction that activated the Idle mode and may continue for a number of
clock cycles before the internal reset algorithm takes control. Reset
initializes the AT8xC5132 and vectors the CPU to address C:0000h.
Note:
During the time that execution resumes, the internal RAM cannot be accessed; however,
it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port
pins, the instruction immediately following the instruction that activated Idle mode should
not write to a Port pin or to the external RAM.
Power-down Mode
The Power-down mode places the AT8xC5132 in a very low power state. Power-down
mode stops the oscillator and freezes all clocks at known states (refer to the Section
"Oscillator", page 12). The CPU status prior to entering Power-down mode is preserved,
i.e., the program counter, program status word register retain their data for the duration
of Power-down mode. In addition, the SFRs and RAM contents are preserved. The sta-
tus of the Port pins during Power-down mode is detailed in Table 56.
Note:
VDD may be reduced to as low as VRET during Power-down mode to further reduce
power dissipation. Take care, however, that VDD is not reduced until Power-down mode
is invoked.
Entering Power-down Mode
To enter Power-down mode, set PD bit in PCON register. The AT8xC5132 enter the
Power-down mode upon execution of the instruction that sets PD bit. The instruction
that sets PD bit is the last instruction executed.
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Exiting Power-down Mode
If VDD was reduced during the Power-down mode, do not exit Power-down mode until
DD is restored to the normal operating level.
V
There are two ways to exit the Power-down mode:
1. Generate an enabled external interrupt.
•
The AT8xC5132 provides capability to exit from Power-down using INT0, INT1, and
KIN3:0 inputs. In addition, using KIN input provides high or low level exit capability
(see Section “Keyboard Interface”, page 134).
Hardware clears PD bit in PCON register which starts the oscillator and restores the
clocks to the CPU and peripherals. Using INTx input, execution resumes when the
input is released (see Figure 25) while using KINx input, execution resumes after
counting 1024 clock ensuring the oscillator is restarted properly (see Figure 26).
This behavior is necessary for decoding the key while it is still pressed. In both
cases, execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Power-down mode.
Note:
1. The external interrupt used to exit Power-down mode must be configured as level
sensitive (INT0 and INT1) and must be assigned the highest priority. In addition, the
duration of the interrupt must be long enough to allow the oscillator to stabilize. The
execution will only resume when the interrupt is deasserted.
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
RAM content.
Figure 25. Power-down Exit Waveform Using INT1:0
INT1:0
OSC
Active phase
Power-down phase
Oscillator restart phase
Active phase
Figure 26. Power-down Exit Waveform Using KIN3:0
KIN3:01
OSC
Active phase
Power-down phase
1024 clock count
Active phase
Note:
1. KIN3:0 can be high or low level triggered.
2. Generate a reset.
–
A logic high on the RST pin clears the PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
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AT8xC5132
reset algorithm takes control. Reset initializes the AT8xC5132 and vectors
the CPU to address 0000h.
Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal
RAM content.
Registers
Table 57. PCON Register
PCON (S:87h) – Power Configuration Register
7
-
6
-
5
-
4
-
3
2
1
0
GF1
GF0
PD
IDL
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 4
3
-
The values read from these Bits are indeterminate. Do not set these Bits.
General-purpose flag 1
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
GF1
GF0
General-purpose flag 0
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
2
1
Power-down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-down mode.
If IDL and PD are both set, PD takes precedence.
PD
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
0
IDL
If IDL and PD are both set, PD takes precedence.
Reset Value = XXXX 0000b
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4173A–8051–08/02
Timers/Counters
The AT8xC5132 implement two general-purpose, 16-bit Timers/Counters. They are
identified as Timer 0 and Timer 1, and can be independently configured to operate in a
variety of modes as a Timer or as an event Counter. When operating as a Timer, the
Timer/Counter runs for a programmed length of time, then issues an interrupt request.
When operating as a Counter, the Timer/Counter counts negative transitions on an
external pin. After a preset number of counts, the Counter issues an interrupt request.
The various operating modes of each Timer/Counter are described in the following
sections.
Timer/Counter
Operations
For instance, a basic operation is Timer registers THx and TLx (x = 0, 1) connected in
cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see
Table 58) turns the Timer on by allowing the selected input to increment TLx. When TLx
overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in
TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer
registers can be accessed to obtain the current count or to enter preset values. They
can be read at any time but TRx bit must be cleared to preset their values, otherwise the
behavior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer operation or Counter operation by selecting the
divided-down peripheral clock or external pin Tx as the source for the counted signal.
TRx bit must be cleared when changing the mode of operation, otherwise the behavior
of the Timer/Counter is unpredictable.
For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral
clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock
periods). The Timer clock rate is FPER/6, i.e., FOSC/12 in standard mode or FOSC/6 in X2
mode.
For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on
the Tx external input pin. The external input is sampled every peripheral cycles. When
the sample is high in one cycle and low in the next one, the Counter is incremented.
Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,
the maximum count rate is FPER/12, i.e., FOSC/24 in standard mode or FOSC/12 in X2
mode. There are no restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes, it should be held for
at least one full peripheral cycle.
Timer Clock Controller
As shown in Figure 27, the Timer 0 (FT0) and Timer 1 (FT1) clocks are derived from
either the peripheral clock (FPER) or the oscillator clock (FOSC) depending on the T0X2
and T1X2 Bits in CKCON register. These clocks are issued from the Clock Controller
block as detailed in Section ’CKCON Register’, page 15. When T0X2 or T1X2 bit is set,
the Timer 0 or Timer 1 clock frequency is fixed and equal to the oscillator clock fre-
quency divided by 2. When cleared, the Timer clock frequency is equal to the oscillator
clock frequency divided by 2 in standard mode or to the oscillator clock frequency in X2
mode.
50
AT8xC5132
4173A–8051–08/02
AT8xC5132
Figure 27. Timer 0 and Timer 1 Clock Controller and Symbols
PER
CLOCK
PER
CLOCK
0
0
1
Timer 0 Clock
Timer 1 Clock
1
OSC
CLOCK
OSC
CLOCK
÷ 2
÷ 2
T0X2
CKCON.1
T1X2
CKCON.2
TIM0
TIM1
CLOCK
CLOCK
Timer 0 Clock Symbol
Timer 1 Clock Symbol
Timer 0
Timer 0 functions as either a Timer or event Counter in four modes of operation.
Figure 28 through Figure 34 show the logical configuration of each mode.
Timer 0 is controlled by the four lower Bits of TMOD register (see Table 59) and Bits 0,
1, 4 and 5 of TCON register (see Table 58). TMOD register selects the method of Timer
gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and
M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control
bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).
For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by
the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer
operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter-
rupt request.
It is important to stop Timer/Counter before changing mode.
Mode 0 (13-bit Timer)
Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 reg-
ister) with a modulo 32 prescaler implemented with the lower five Bits of TL0 register
(see Figure 28). The upper three Bits of TL0 register are indeterminate and should be
ignored. Prescaler overflow increments TH0 register. Figure 29 gives the overflow
period calculation formula.
Figure 28. Timer/Counter x (x = 0 or 1) in Mode 0
TIMx
CLOCK
Timer x
Interrupt
Request
÷ 6
0
1
TLx
(5 Bits)
THx
(8 Bits)
Overflow
TFx
TCON Reg
Tx
C/Tx#
TMOD Reg
INTx#
GATEx
TMOD Reg
TRx
TCON Reg
Figure 29. Mode 0 Overflow Period Formula
6 ⋅ (16384 – (THx, TLx))
TFxPER
=
FTIMx
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4173A–8051–08/02
Mode 1 (16-bit Timer)
Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in
cascade (see Figure 30). The selected input increments TL0 register. Figure 31 gives
the overflow period calculation formula when in timer mode.
Figure 30. Timer/Counter x (x = 0 or 1) in Mode 1
TIMx
CLOCK
Timer x
Interrupt
Request
÷ 6
0
1
Overflow
THx
(8 Bits)
TLx
(8 Bits)
TFx
TCON Reg
Tx
C/Tx#
TMOD Reg
INTx#
GATEx
TMOD Reg
TRx
TCON Reg
Figure 31. Mode 1 Overflow Period Formula
6 ⋅ (65536 – (THx, TLx))
TFxPER
=
FTIMx
Mode 2 (8-bit Timer with Auto- Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads
Reload)
from TH0 register (see Table 60). TL0 overflow sets TF0 flag in TCON register and
reloads TL0 with the contents of TH0, which is preset by software. When the interrupt
request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next
reload value may be changed at any time by writing it to TH0 register. Figure 33 gives
the autoreload period calculation formula when in timer mode.
Figure 32. Timer/Counter x (x = 0 or 1) in Mode 2
TIMx
CLOCK
Timer x
Interrupt
Request
÷ 6
0
1
Overflow
TLx
(8 Bits)
TFx
TCON Reg
Tx
C/Tx#
TMOD Reg
INTx#
THx
(8 Bits)
GATEx
TMOD Reg
TRx
TCON Reg
Figure 33. Mode 2 Autoreload Period Formula
6 ⋅ (256 – THx)
TFxPER
=
FTIMx
Mode 3 (Two 8-bit Timers)
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit
Timers (see Figure 34). This mode is provided for applications requiring an additional 8-
bit Timer or Counter. TL0 uses the Timer 0 control Bits C/T0# and GATE0 in TMOD reg-
ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a
Timer function (counting FT1/6) and takes over use of the Timer 1 interrupt (TF1) and run
control (TR1) Bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3.
Figure 33 gives the autoreload period calculation formulas for both TF0 and TF1 flags.
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AT8xC5132
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AT8xC5132
Figure 34. Timer/Counter 0 in Mode 3: Two 8-bit Counters
TIM0
CLOCK
Timer 0
Interrupt
Request
÷ 6
0
1
Overflow
TL0
(8 Bits)
TF0
TCON.5
T0
C/T0#
TMOD.2
INT0#
GATE0
TMOD.3
TR0
TCON.4
Timer 1
Interrupt
Request
Overflow
TIM0
CLOCK
TH0
(8 Bits)
÷ 6
TF1
TCON.7
TR1
TCON.6
Figure 35. Mode 3 Overflow Period Formula
6 ⋅ (256 – TH0)
6 ⋅ (256 – TL0)
TF1PER
=
TF0PER
=
FTIM0
FTIM0
Timer 1
Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. Follow-
ing comments help to understand the differences:
•
Timer 1 functions as either a Timer or event Counter in three modes of operation.
Figure 28 through Figure 32 show the logical configuration for modes 0, 1, and 2.
Timer 1’s mode 3 is a hold-count mode.
•
Timer 1 is controlled by the four high-order Bits of TMOD register (see Table 59)
and Bits 2, 3, 6 and 7 of TCON register (see Figure 58). TMOD register selects the
method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of
operation (M11 and M01). TCON register provides Timer 1 control functions:
overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type
control bit (IT1).
•
•
Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best
suited for this purpose.
For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented
by the selected input. Setting GATE1 and TR1 allows external pin INT1 to control
Timer operation.
•
•
Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating
an interrupt request.
When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit
(TR1). For this situation, use Timer 1 only for applications that do not require an
interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in
and out of mode 3 to turn it off and on.
•
It is important to stop the Timer/Counter before changing modes.
Mode 0 (13-bit Timer)
Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-
ister) with a modulo-32 prescaler implemented with the lower 5 Bits of the TL1 register
(see Figure 28). The upper 3 Bits of TL1 register are ignored. Prescaler overflow incre-
ments TH1 register.
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4173A–8051–08/02
Mode 1 (16-bit Timer)
Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in
cascade (see Figure 30). The selected input increments TL1 register.
Mode 2 (8-bit Timer with
Auto-Reload)
Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from
TH1 register on overflow (see Figure 32). TL1 overflow sets TF1 flag in TCON register
and reloads TL1 with the contents of TH1, which is preset by software. The reload
leaves TH1 unchanged.
Mode 3 (Halt)
Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt
Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
Interrupt
Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This
flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer
interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This
assumes interrupts are globally enabled by setting EA bit in IEN0 register.
Figure 36. Timer Interrupt System
Timer 0
Interrupt Request
TF0
TCON.5
ET0
IEN0.1
Timer 1
Interrupt Request
TF1
TCON.7
ET1
IEN0.3
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AT8xC5132
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AT8xC5132
Registers
Table 58. TCON Register
TCON (S:88h) – Timer/Counter Control Register
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
Bit
Number
Mnemonic Description
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
Timer 1 Run Control Bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.
Timer 0 Run Control Bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT1).
Set by hardware when external interrupt is detected on INT1 pin.
Interrupt 1 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1).
Set to select falling edge active (edge triggered) for external interrupt 1.
IT1
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT0).
Set by hardware when external interrupt is detected on INT0 pin.
IE0
Interrupt 0 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0).
Set to select falling edge active (edge triggered) for external interrupt 0.
IT0
Reset Value = 0000 0000b
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4173A–8051–08/02
Table 59. TMOD Register
TMOD (89:h) - Timer/Counter 0 and 1 Modes
7
6
5
4
3
2
1
0
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
Bit
Bit
Number Mnemonic Description
Timer 1 Gating Control Bit
Clear to enable Timer 1 whenever TR1 bit is set.
7
GATE1
Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set.
Timer 1 Counter/Timer Select Bit
6
5
C/T1#
M11
Clear for Timer operation: Timer 1 counts the divided-down system clock.
Set for Counter operation: Timer 1 counts negative transitions on external pin T1.
Timer 1 Mode Select Bits
M11 M01
Operating mode
0
0
1
0
1
0
Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1).
Mode 1: 16-bit Timer/Counter.
4
3
M01
Mode 2: 8-bit auto-reload Timer/Counter (TL1).(1)
1
1
Mode 3: Timer 1 halted. Retains count.
Timer 0 Gating Control Bit
Clear to enable Timer 0 whenever TR0 bit is set.
Set to enable Timer/Counter 0 only while INT0 pin is high and TR0 bit is set.
GATE0
Timer 0 Counter/Timer Select Bit
2
1
C/T0#
M10
Clear for Timer operation: Timer 0 counts the divided-down system clock.
Set for Counter operation: Timer 0 counts negative transitions on external pin T0.
Timer 0 Mode Select Bit
M10 M00
Operating mode
0
0
1
0
1
0
Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).
Mode 1: 16-bit Timer/Counter.
M00
Mode 2: 8-bit auto-reload Timer/Counter (TL0).(2)
0
1
1
Mode 3: TL0 is an 8-bit Timer/Counter.
TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 Bits.
Reset Value = 0000 0000b
Notes: 1. Reloaded from TH1 at overflow.
2. Reloaded from TH0 at overflow.
Table 60. TH0 Register
TH0 (S:8Ch) – Timer 0 High Byte Register
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
7:0
High Byte of Timer 0
Reset Value = 0000 0000b
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Table 61. TL0 Register
TL0 (S:8Ah) – Timer 0 Low Byte Register
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
7:0
Low Byte of Timer 0
Reset Value = 0000 0000b
Table 62. TH1 Register
TH1 (S:8Dh) – Timer 1 High Byte Register
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
7:0
High Byte of Timer 1
Reset Value = 0000 0000b
Table 63. TL1 Register
TL1 (S:8Bh) – Timer 1 Low Byte Register
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
7:0
Low Byte of Timer 1
Reset Value = 0000 0000b
57
4173A–8051–08/02
Watchdog Timer
The AT8xC5132 implement a hardware Watchdog Timer (WDT) that automatically
resets the chip if it is allowed to time out. The WDT provides a means of recovering from
routines that do not complete successfully due to software or hardware malfunctions.
Description
The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As
shown in Figure 37, the 14-bit prescaler is fed by the WDT clock detailed in section
"Watchdog Clock Controller", page 58.
The Watchdog Timer Reset register (WDTRST, see Table 64) provides control access
to the WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 65) pro-
vides time-out period programming.
Three operations control the WDT:
•
•
•
Chip reset clears and disables the WDT.
Programming the time-out value to the WDTPRG register.
Writing a specific two-byte sequence to the WDTRST register clears and enables
the WDT.
Figure 37. WDT Block Diagram
14-bit Prescaler
7-bit Counter
WDT
CLOCK
÷ 6
OV
To Internal Reset
RST
RST
SET
WTO2:0
WDTPRG.2:0
1Eh-E1h Decoder
EN
RST
System Reset
MATCH
OSC
CLOCK
Pulse Generator
RST
WDTRST
Watchdog Clock
Controller
As shown in Figure 38 the WDT clock (FWDT) is derived from either the peripheral clock
(FPER) or the oscillator clock (FOSC) depending on the WTX2 bit in CKCON register.
These clocks are issued from the Clock Controller block as detailed in section "Clock
Controller", page 12. When WTX2 bit is set, the WDT clock frequency is fixed and equal
to the oscillator clock frequency divided by 2. When cleared, the WDT clock frequency is
equal to the oscillator clock frequency divided by 2 in standard mode or to the oscillator
clock frequency in X2 mode.
Figure 38. WDT Clock Controller and Symbol
PER
CLOCK
0
WDT
CLOCK
WDT Clock
1
OSC
CLOCK
÷ 2
WDT Clock Symbol
WTX2
CKCON.6
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AT8xC5132
4173A–8051–08/02
AT8xC5132
Watchdog Operation
After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and
E1h into the WDTRST register. As soon as it is enabled, there is no way except the chip
reset to disable it. If it is not cleared using the previous sequence, the WDT overflows
and forces a chip reset. This overflow generates a high level 96 oscillator periods pulse
on the RST pin to globally reset the application.
The WDT time-out period can be adjusted using WTO2:0 Bits located in the WDTPRG
register accordingly to the formula shown in Figure 39. In this formula, WTOval repre-
sents the decimal value of WTO2:0 Bits. Table 65 reports the time-out period depending
on the WDT frequency.
Figure 39. WDT Time-Out Formula
6 ⋅ ((214 ⋅ 2WTOval) – 1)
WDTTO
=
FWDT
FWDT
WTO2
WTO1
WTO0
6 MHz(1)
16.38 ms
32.77 ms
65.54 ms
131.07 ms
262.14 ms
524.29 ms
1.05 s
8 MHz(1)
12.28 ms
24.57 ms
49.14 ms
98.28 ms
196.56 ms
393.12 ms
786.24 ms
1.57 s
10 MHz(1)
9.83 ms
12 MHz(2)
8.19 ms
16 MHz(2)
6.14 ms
20 MHz(2)
4.92 ms
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
19.66 ms
39.32 ms
78.64 ms
157.29 ms
314.57 ms
629.15 ms
1.26 s
16.38 ms
32.77 ms
65.54 ms
131.07 ms
262.14 ms
524.29 ms
1.05 s
12.28 ms
24.57 ms
49.14 ms
98.28 ms
196.56 ms
393.12 ms
786.24 ms
9.83 ms
19.66 ms
39.32 ms
78.64 ms
157.29 ms
314.57 ms
629.15 ms
2.10 s
Notes: 1. These frequencies are achieved in X1 mode, FWDT = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode, FWDT = FOSC
.
WDT Behavior During Idle and Operation of the WDT during power reduction modes deserves special attention.
Power-down Modes
The WDT continues to count while the AT8xC5132 are in Idle mode. This means that
the user must dedicate some internal or external hardware to service the WDT during
Idle mode. One approach is to use a peripheral Timer to generate an interrupt request
when the Timer overflows. The interrupt service routine then clears the WDT, reloads
the peripheral Timer for the next service period and puts the AT8xC5132 back into Idle
mode.
The Power-down mode stops all phase clocks. This causes the WDT to stop counting
and to hold its count. The WDT resumes counting from where it left off if the Power-
down mode is terminated by INT0, INT1 or keyboard interrupt. To ensure that the WDT
does not overflow shortly after exiting the Power-down mode, it is recommended to clear
the WDT just before entering Power-down mode.
The WDT is cleared and disabled if the Power-down mode is terminated by a reset.
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4173A–8051–08/02
Registers
Table 64. WDTRST Register
WDTRST (S:A6h Write only) – Watchdog Timer Reset Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Bit
Number
Mnemonic Description
7 - 0
-
Watchdog Control Value.
Reset Value = XXXX XXXXb
Table 65. WDTPRG Register
WDTPRG (S:A7h) – Watchdog Timer Program Register
7
6
5
4
3
2
1
0
-
-
-
-
-
WTO2
WTO1
WTO0
Bit
Bit
Number
Mnemonic Description
Reserved
7-3
2-0
-
The values read from these Bits are indeterminate. Do not set these Bits.
Watchdog Timer Time-Out Selection Bits
Refer to Table 64 for time-out periods.
WTO2:0
Reset Value = XXXX X000b
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AT8xC5132
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AT8xC5132
Audio Output
Interface
The AT8xC5132 implement an audio output interface allowing the audio bitstream to be
output in various formats. It is compatible with right and left justification PCM and I2S for-
mats and thanks to the on-chip PLL (see Section “Clock Controller”, page 12) allows
connection of almost all of the commercial audio DAC families available on the market.
Description
The C51 core interfaces to the audio interface through five special function registers:
AUDCON0 and AUDCON1, the Audio Control registers (see Table 67 and Table 68);
AUDSTA, the Audio Status register (see Table 69); AUDDAT, the Audio Data register
(see Table 70); and AUDCLK, the Audio Clock Divider register (see Table 71).
Figure 40 shows the audio interface block diagram, blocks are detailed in the following
sections.
Figure 40. Audio Interface Block Diagram
SCLK
DCLK
AUD
CLOCK
Clock Generator
0
1
DSEL
AUDEN
AUDCON1.0
HLR
AUDCON0.0
DSIZ
AUDCON0.1
POL
AUDCON0.2
Data Ready
Data Converter
DOUT
16
JUST4:0
AUDCON0.7:3
SREQ
AUDSTA.7
Audio Data
From C51
Audio Buffer
AUDDAT
8
UDRN
AUDSTA.6
AUBUSY
AUDSTA.5
DUP1:0
AUDCON1.2:1
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Clock Generator
The audio interface clock is generated by division of the PLL clock. The division factor is
given by AUCD4:0 Bits in AUDCLK register. Figure 41 shows the audio interface clock
generator and its calculation formula. The audio interface clock frequency depends on
the audio DAC used.
Figure 41. Audio Clock Generator and Symbol
AUDCLK
PLL
CLOCK
AUD
CLOCK
AUCD4:0
Audio Interface Clock
Audio Clock Symbol
PLLclk
AUCD + 1
AUDclk = ---------------------------
As soon as audio interface is enabled by setting AUDEN bit in AUDCON1 register, the
master clock generated by the PLL is output on the SCLK pin which is the DAC system
clock. This clock is output at 256 or 384 times the sampling frequency depending on the
DAC capabilities. HLR bit in AUDCON0 register must be set according to this rate for
properly generating the audio bit clock on the DCLK pin and the word selection clock on
the DSEL pin. These clocks are not generated when no data is available at the data
converter input.
For DAC compatibility, the bit clock frequency is programmable for outputting 16 Bits or
32 Bits per channel using the DSIZ bit in AUDCON0 register (see Section "Data Con-
verter", page 62), and the word selection signal is programmable for outputting left
channel on low or high level according to POL bit in AUDCON0 register as shown in
Figure 42.
Figure 42. DSEL Output Polarity
Left Channel
Left Channel
Right Channel
Right Channel
POL = 0
POL = 1
Data Converter
The data converter block converts the audio stream input from the 16-bit parallel format
to a serial format. For accepting all PCM formats and I2S format, JUST4:0 Bits in
AUDCON0 register are used to shift the data output point. As shown in Figure 43, these
Bits allow MSB justification by setting JUST4:0 = 00000, LSB justification by setting
JUST4:0 = 10000, I2S Justification by setting JUST4:0 = 00001, and more than 16-bit
LSB justification by filling the low significant Bits with logic 0.
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AT8xC5132
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AT8xC5132
Figure 43. Audio Output Format
Left Channel
Right Channel
DSEL
1
2
3
13
14
15
16
DCLK
DOUT
1
2
3
13
14
18
14
15
16
LSB MSB B14
B1 LSB MSB B14
I2S Format with DSIZ = 0 and JUST4:0 = 00001.
B1
Left Channel
Right Channel
DSEL
DCLK
DOUT
1
2
3
17
18
32
1
2
3
17
32
MSB B14
LSB
MSB B14
LSB
I2S Format with DSIZ = 1 and JUST4:0 = 00001.
Left Channel
Right Channel
DSEL
DCLK
DOUT
1
2
3
13
14
15
16
1
2
3
13
15
16
MSB B14
B1 LSB MSB B15
MSB/LSB Justified Format with DSIZ = 0 and JUST4:0 = 00000.
B1 LSB
Left Channel
16 17
Right Channel
16 17
DSEL
DCLK
DOUT
1
18
31
32
1
18
31
32
MSB B14
B1 LSB
MSB B14
B1 LSB
16-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 10000.
Left Channel
15 16
Right Channel
15 16
DSEL
DCLK
DOUT
1
30
31
32
1
30
31
32
MSB B16
B2
B1 LSB
MSB B16
B2
B1 LSB
18-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 01110.
The data converter receives its audio stream from two sources selected by the SRC bit
in AUDCON1 register.
As soon as first audio data is input to the data converter, it enables the clock generator
for generating the bit and word clocks.
Audio Buffer
In voice or sound playing mode, the audio stream comes from the C51 core through an
audio buffer. The data is in 8-bit format and is sampled at 8 kHz. The audio buffer
adapts the sample format and rate. The sample format is extended to 16 Bits by filling
the LSB to 00h. Rate is adapted to the DAC rate by duplicating the data using DUP1:0
Bits in AUDCON1 register according to Table 66.
The audio buffer interfaces to the C51 core through three flags: the sample request flag
(SREQ in AUDSTA register), the under-run flag (UNDR in AUDSTA register) and the
busy flag (AUBUSY in AUDSTA register). SREQ and UNDR can generate an interrupt
request as explained in Section "Interrupt Request", page 64. The buffer size is 8 Bytes
large. SREQ is set when the samples number switches from 4 to 3 and reset when the
samples number switches from 4 to 5; UNDR is set when the buffer becomes empty sig-
naling that the audio interface ran out of samples; and AUBUSY is set when the buffer is
full.
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Table 66. Sample Duplication Factor
DUP1
DUP0
Factor
0
0
1
1
0
1
0
1
No sample duplication, DAC rate = 8 kHz (C51 rate).
One sample duplication, DAC rate = 16 kHz (2 x C51 rate).
Two samples duplication, DAC rate = 32 kHz (4 x C51 rate).
Three samples duplication, DAC rate = 48 kHz (6 x C51 rate).
Interrupt Request
The audio interrupt request can be generated by two sources when in C51 audio mode:
a sample request when SREQ flag in AUDSTA register is set to logic 1, and an under-
run condition when UDRN flag in AUDSTA register is set to logic 1. Both sources can be
enabled separately by masking one of them using the MSREQ and MUDRN Bits in
AUDCON1 register. A global enable of the audio interface is provided by setting the
EAUD bit in IEN0 register.
The interrupt is requested each time one of the two sources is set to one. The source
flags are cleared by writing some data in the audio buffer through AUDDAT, but the glo-
bal audio interrupt flag is cleared by hardware when the interrupt service routine is
executed.
Figure 44. Audio Interface Interrupt System
UDRN
AUDSTA.6
Audio
Interrupt
Request
MUDRN
AUDCON1.4
SREQ
AUDSTA.7
EAUD
IEN0.6
MSREQ
AUDCON1.5
Voice or Sound Playing
In voice or sound playing mode, the operations required are to configure the PLL and
the audio interface according to the DAC selected. The audio clock is programmed to
generate the 256·Fs or 384·Fs. The data flow sent by the C51 is then regulated by inter-
rupt and data is loaded 4 Bytes by 4 Bytes. Figure 45 shows the configuration flow of the
audio interface when in voice or sound mode.
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AT8xC5132
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AT8xC5132
Figure 45. Voice or Sound Mode Audio Flows
Voice/Song Mode
Configuration
Audio Interrupt
Service Routine
Wait for DAC
Enable Time
Program Audio Clock
Sample Request?
SREQ = 1?
Configure Interface
HLR = X
Select Audio
SRC = 1
DSIZ = X
Load 4 Samples in the
Audio Buffer
Under-run Condition1
POL = X
JUST4:0 = XXXXXb
DUP1:0 = XX
Load 8 Samples in the
Audio Buffer
Enable DAC System
Clock
Enable Interrupt
Set MSREQ & MUDRN1
EAUD = 1
AUDEN = 1
Note:
1. An under-run occurrence signifies that the C51 core did not respond to the previous sample request interrupt. It may never
occur for a correct voice/sound generation. It is the user’s responsibility to mask it or not.
65
4173A–8051–08/02
Registers
Table 67. AUDCON0 Register
AUDCON0 (S:9Ah) – Audio Interface Control Register 0
7
6
5
4
3
2
1
0
JUST4
JUST3
JUST2
JUST1
JUST0
POL
DSIZ
HLR
Bit
Bit
Number
Mnemonic Description
Audio Stream Justification Bits
Refer to Section "Data Converter", page 62 for Bits description.
7 - 3
2
JUST4:0
POL
DSEL Signal Output Polarity
Set to output the left channel on high level of DSEL output (PCM mode).
Clear to output the left channel on the low level of DSEL output (I2S mode).
Audio Data Size
1
0
DSIZ
HLR
Set to select 32-bit data output format.
Clear to select 16-bit data output format.
High/Low Rate Bit
Set by software when the PLL clock frequency is 384·Fs.
Clear by software when the PLL clock frequency is 256·Fs.
Reset Value = 0000 1000b
Table 68. AUDCON1 Register
AUDCON1 (S:9Bh) – Audio Interface Control Register 1
7
6
5
4
3
-
2
1
0
–
–
MSREQ
MUDRN
DUP1
DUP0
AUDEN
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
–
The values read from this bit is always 0. Do not set this bit.
Reserved
–
The values read from this bit is always 0. Do not set this bit.
Audio Sample Request Flag Mask Bit
5
4
MSREQ Set to prevent the SREQ flag from generating an audio interrupt.
Clear to allow the SREQ flag to generate an audio interrupt.
Audio Sample Under-run Flag Mask Bit
MUDRN Set to prevent the UDRN flag from generating an audio interrupt.
Clear to allow the UDRN flag to generate an audio interrupt.
Reserved
3
–
The values read from this bit is always 0. Do not set this bit.
Audio Duplication Factor
DUP1:0
2 - 1
Refer to Table 66 for Bits description.
Audio Interface Enable Bit
AUDEN Set to enable the audio interface.
Clear to disable the audio interface.
0
Reset Value = 1011 0010b
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AT8xC5132
Table 69. AUDSTA Register
AUDSTA (S:9Ch Read Only) – Audio Interface Status Register
7
6
5
4
-
3
-
2
-
1
-
0
-
SREQ
UDRN
AUBUSY
Bit
Bit
Number
Mnemonic Description
Audio Sample Request Flag
Set in C51 audio source mode when the audio interface request samples (buffer
half empty). This bit generates an interrupt if not masked and if enabled in IEN0.
Cleared by hardware when samples are loaded in AUDDAT.
7
6
SREQ
UDRN
Audio Sample Under-run Flag
Set in C51 audio source mode when the audio interface runs out of samples
(buffer empty). This bit generates an interrupt if not masked and if enabled in
IEN0.
Cleared by hardware when samples are loaded in AUDDAT.
Audio Interface Busy Bit
Set in C51 audio source mode when the audio interface cannot accept more
sample (buffer full).
Cleared by hardware when buffer is no more full.
5
AUBUSY
-
Reserved
4-0
The values read from these Bits are always 0. Do not set these Bits.
Reset Value = 1100 0000b
Table 70. AUDDAT Register
AUDDAT (S:9Dh) – Audio Interface Data Register
7
6
5
4
3
2
1
0
AUD7
AUD6
AUD5
AUD4
AUD3
AUD2
AUD1
AUD0
Bit
Bit
Number
Mnemonic Description
Audio Data
8-bit sampling data for voice or sound playing.
7 - 0
AUD7:0
Reset Value = 1111 1111b
Table 71. AUDCLK Register
AUDCLK (S:ECh) – Audio Clock Divider Register
7
-
6
-
5
-
4
3
2
1
0
AUCD4
AUCD3
AUCD2
AUCD1
AUCD0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4 - 0
-
The values read from these Bits are always 0. Do not set these Bits.
Audio Clock Divider
5-bit divider for audio clock generation.
AUCD4:0
Reset Value = 0000 0000b
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4173A–8051–08/02
Universal Serial Bus The AT8xC5132 implement a USB device controller supporting Full-speed data transfer.
In addition to the default control endpoint 0, it provides 3 other endpoints, which can be
configured in Control, Bulk, Interrupt or Isochronous types.
This allows to develop firmware conforming to most USB device classes, for example
the AT8xC5132 support:
•
USB Mass Storage Class Control/Bulk/Interrupt (CBI) Transport, Revision 1.0 –
December 14, 1998
•
•
USB Mass Storage Class Bulk-Only Transport, Revision 1.0 – September 31, 1999
USB Device Firmware Upgrade Class, Revision 1.0 – May 13, 1999
USB Mass Storage Class CBI Within the CBI framework, the Control endpoint is used to transport command blocks as
Transport
well as to transport standard USB requests. One Bulk Out endpoint is used to transport
data from the host to the device. One Bulk In endpoint is used to transport data from the
device to the host. And one interrupt endpoint may also be used to signal command
completion (protocol 0) but it is optional and may not be used (protocol 1).
The following AT8xC5132 configuration adheres to that requirements:
•
•
•
•
Endpoint 0: 32 Bytes, Control In-Out
Endpoint 1: 64 Bytes, Bulk Out
Endpoint 2: 64 Bytes, Bulk In
Endpoint 3: 8 Bytes, Interrupt In
USB Mass Storage Class
Bulk-Only Transport
Within the Bulk-only framework, the Control endpoint is only used to transport class-
specific and standard USB requests for device set-up and configuration. One Bulk-out
endpoint is used to transport commands and data from the host to the device. One Bulk
in endpoint is used to transport status and data from the device to the host. No interrupt
endpoint is needed.
The following AT8xC5132 configuration adheres to that requirements:
•
•
•
•
Endpoint 0: 32 Bytes, Control In-Out
Endpoint 1: 64 Bytes, Bulk Out
Endpoint 2: 64 Bytes, Bulk In
Endpoint 3: not used
USB Device Firmware
Upgrade (DFU)
The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip
Flash memory of the AT89C5132. This allows installing product enhancements and
patches to devices that are already in the field. Two different configurations and descrip-
tor sets are used to support DFU functions. The Run-Time configuration co-exist with
the usual functions of the device, which shall be USB Mass Storage for AT89C5132. It is
used to initiate DFU from the normal operating mode. The DFU configuration is used to
perform the firmware update after device re-configuration and USB reset. It excludes
any other function. Only the default control pipe (endpoint 0) is used to support DFU ser-
vices in both configurations.
The only possible value for the MaxPacketSize in the DFU configuration is 32 Bytes,
which is the size of the FIFO implemented for endpoint 0.
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AT8xC5132
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AT8xC5132
Description
The USB device controller provides the hardware that the AT8xC5132 need to interface
a USB link to data flow stored in a double port memory.
It requires a 48 MHz reference clock provided by the clock controller as detailed in Sec-
tion "Clock Controller", page 69. This clock is used to generate a 12 MHz full speed bit
clock from the received USB differential data flow and to transmit data according to full
speed USB device tolerance. Clock recovery is done by a Digital Phase Locked Loop
(DPLL) block.
The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuff-
ing, CRC generation and checking, and the serial-parallel data conversion.
The Universal Function Interface (UFI) controls the interface between the data flow and
the Dual Port RAM, but also the interface with the C51 core itself.
Figure 46. USB Device Controller Block Diagram
USB
CLOCK
48 MHz
12 MHz
DPLL
D+
D-
USB
Buffer
UFI
To/From C51 Core
SIE
Clock Controller
The USB controller clock is generated by division of the PLL clock. The division factor is
given by USBCD1:0 Bits in USBCLK register (see Table 86). Figure 47 shows the USB
controller clock generator and its calculation formula. The USB controller clock fre-
quency must always be 48 MHz.
Figure 47. USB Clock Generator and Symbol
USBCLK
PLL
USB
CLOCK
USBCD1:0
CLOCK
48 MHz USB Clock
PLLclk
USB Clock Symbol
USBclk = --------------------------------
USBCD + 1
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4173A–8051–08/02
Serial Interface Engine (SIE)
The SIE performs the following functions:
•
•
•
•
•
•
•
NRZI data encoding and decoding
Bit stuffing and unstuffing
CRC generation and checking
ACKs and NACKs automatic generation
TOKEN type identifying
Address checking
Clock recovery (using DPLL)
Figure 48. SIE Block Diagram
End of Packet
Detector
SYNC Detector
PID Decoder
Start of Packet
Detector
NRZI ‘ NRZ
Bit Unstuffing
Packet Bit Counter
Address Decoder
Serial to Parallel
Converter
D+
D-
8
Data Out
Clock
Recover
SysClk
(12 MHz)
USB
CLOCK
48 MHz
CRC5 & CRC16
Generator/Check
USB Pattern Generator
Parallel to Serial Converter
Bit Stuffing
8
Data In
NRZI Converter
CRC16 Generator
Function Interface Unit (UFI)
The Function Interface Unit provides the interface between the AT8xC5132 and the SIE.
It manages transactions at the packet level with minimal intervention from the device
firmware, which reads and writes the endpoint FIFOs.
Figure 50 shows typical USB IN and OUT transactions reporting the split in the hard-
ware (UFI) and software (C51) load.
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AT8xC5132
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AT8xC5132
Figure 49. UFI Block Diagram
USBCON
USBADDR
USBINT
USBIEN
UEPNUM
UEPCONX
UEPSTAX
UEPRST
UEPINT
Transfer
Control
FSM
Asynchronous Information
12 MHz DPLL
To/From C51 Core
UEPIEN
UEPDATX
UBYCTX
UFNUMH
UFNUML
Endpoint 3
Endpoint 2
Endpoint 1
Endpoint 0
Endpoint Control
USB side
Endpoint Control
C51 side
To/From SIE
Figure 50. USB Typical Transaction Load
OUT Transactions:
OUT DATA0 (n Bytes)
OUT
DATA1
OUT
ACK
DATA1
HOST
ACK C51 interrupt
NACK
ACK
UFI
C51
Endpoint FIFO read (n Bytes)
IN Transactions:
IN
IN
IN
HOST
NACK
DATA1
DATA1
UFI
C51 interrupt
Endpoint FIFO write
Endpoint FIFO write
C51
USB Interrupt System
As shown in Figure 51, the USB controller of the AT8xC5132 handle sixteen interrupt
sources. These sources are separated in two groups: the endpoints interrupts and the
controller interrupts, combined together to appear as single interrupt source for the C51
core. The USB interrupt is enabled by setting the EUSB bit in IEN1.
Controller Interrupt Sources
There are four controller interrupt sources which can be enabled separately in USBIEN:
•
SPINT: Suspend Interrupt Flag.
This flag triggers an interrupt when a USB Suspend (Idle bus for three frame
periods: a J state for 3 ms) is detected.
•
•
SOFINT: Start Of Frame Interrupt Flag.
This flag triggers an interrupt when a USB start of frame packet has been received.
EORINT: End Of Reset Interrupt Flag.
This flag triggers an interrupt when a End Of Reset has been detected by the USB
controller.
•
WUPCPU: Wake Up CPU Interrupt Flag.
This flag triggers an interrupt when the USB controller is in SUSPEND state and is
re-activated by a non-idle signal from USB line.
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4173A–8051–08/02
Endpoint Interrupt Sources
Each endpoint supports four interrupt sources reported in UEPSTAX and combined
together to appear as a single endpoint interrupt source in UEPINT. Each endpoint inter-
rupt can be enabled separately in UEPIEN.
•
TXCMP: Transmitted In Data Interrupt Flag.
This flag triggers an interrupt after an IN packet has been transmitted for
Isochronous endpoints or after it has been accepted (ACK’ed) by the host for
Control, Bulk and Interrupt endpoints.
•
•
RXOUT: Received Out Data Interrupt Flag.
This flag triggers an interrupt after a new packet has been received.
RXSETUP: Receive Setup Interrupt Flag.
This flag triggers an interrupt when a valid SETUP packet has been received from
the host.
•
STLCRC: Stall Sent Interrupt Flag/CRC Error Interrupt Flag.
This flag triggers an interrupt after a STALL handshake has been sent on the bus,
for Control, Bulk and Interrupt endpoints.
This flag triggers an interrupt when the last data received is corrupted for
Isochronous endpoints.
Figure 51. USB Interrupt Control Block Diagram
Endpoint x (x = 0.3)
TXCMP
UEPSTAX.0
RXOUT
UEPSTAX.1
EPxINT
UEPINT.x
RXSETUP
UEPSTAX.2
EPxIE
UEPIEN.x
STLCRC
UEPSTAX.3
USB interrupt
WUPCPU
USBINT.5
EUSB
IEN1.6
EWUPCPU
USBIEN.5
EORINT
USBINT.4
EEORINT
USBIEN.4
SOFINT
USBINT.3
ESOFINT
USBIEN.3
SPINT
USBINT.0
ESPINT
USBIEN.0
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Registers
Table 72. USBCON Register
USBCON (S:BCh) – USB Global Control Register
7
6
5
4
-
3
2
1
0
USBE
SUSPCLK SDRMWUP
UPRSM
RMWUPE
CONFG
FADDEN
Bit
Bit Number Mnemonic Description
USB Enable Bit
7
USBE
Set to enable the USB controller.
Clear to disable and reset the USB controller.
Suspend USB Clock Bit
6
SUSPCLK Set to disable the 48 MHz clock input (Resume Detection is still active).
Clear to enable the 48 MHz clock input.
Send Remote Wake-up Bit
Set to force an external interrupt on the USB controller for Remote Wake UP
purpose.
5
SDRMWUP An upstream resume is send only if the bit RMWUPE is set, all USB clocks are
enabled AND the USB bus was in SUSPEND state for at least 5 ms. See
UPRSM below.
Cleared by software.
Reserved
4
3
-
The values read from this bit is always 0. Do not set this bit.
Upstream Resume Bit (read only)
Set by hardware when SDRMWUP has been set and if RMWUPE is enabled.
Cleared by hardware after the upstream resume has been sent.
UPRSM
Remote Wake-up Enable Bit
Set to enable request an upstream resume signalling to the host.
Clear after the upstream resume has been indicated by RSMINPR.
2
1
RMWUPE
Note: Do not set this bit if the host has not set the
DEVICE_REMOTE_WAKEUP feature for the device.
Configuration Bit
Set after a SET_CONFIGURATION request with a non-zero value has been
correctly processed.
Cleared by software when a SET_CONFIGURATION request with a zero value
CONFG
is received.
Cleared by hardware on hardware reset or when an USB reset is detected on
the bus.
Function Address Enable Bit
Set by the device firmware after a successful status phase of a
SET_ADDRESS transaction. It shall not be cleared afterwards by the device
firmware.
0
FADDEN
Cleared by hardware on hardware reset or when an USB reset is received.
When this bit is cleared, the default function address is used (0).
Reset Value = 0000 0000b
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Table 73. USBADDR Register
USBADDR (S:C6h) – USB Address Register
7
6
5
4
3
2
1
0
FEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
Bit
Bit
Number
Mnemonic Description
Function Enable Bit
Set to enable the function. The device firmware shall set this bit after it has
received a USB reset and participate in the following configuration process with
the default address (FEN is reset to 0).
7
FEN
Cleared by hardware at power-up, should not be cleared by the device firmware
once set.
USB Address Bits
This field contains the default address (0) after power-up or USB bus reset.
It shall be written with the value set by a SET_ADDRESS request received by
the device firmware.
6-0
UADD6:0
Reset Value = 0000 0000b
Table 74. USBINT Register
USBINT (S:BDh) – USB Global Interrupt Register
7
-
6
-
5
4
3
2
-
1
-
0
WUPCPU
EORINT
SOFINT
SPINT
Bit
Bit
Number Mnemonic Description
Reserved
7 - 6
-
The values read from these Bits are always 0. Do not set these Bits.
Wake Up CPU Interrupt Flag
Set by hardware when the USB controller is in SUSPEND state and is re-activated
5
WUPCPU by a non-idle signal from USB line (not by an upstream resume). This triggers a USB
interrupt when EWUPCPU is set in the USBIEN.
Cleared by software after re-enabling all USB clocks.
End of Reset Interrupt Flag
Set by hardware when a End of Reset has been detected by the USB controller. This
triggers a USB interrupt when EEORINT is set in USBIEN.
4
EORINT
Cleared by software.
Start of Frame Interrupt Flag
Set by hardware when a USB Start of Frame packet (SOF) has been properly
received. This triggers a USB interrupt when ESOFINT is set in USBIEN.
Cleared by software.
3
2 - 1
0
SOFINT
Reserved
-
The values read from these Bits are always 0. Do not set these Bits.
Suspend Interrupt Flag
Set by hardware when a USB Suspend (Idle bus for three frame periods: a J state for
3 ms) is detected. This triggers a USB interrupt when ESPINT is set in USBIEN.
SPINT
Cleared by software.
Reset Value = 0000 0000b
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Table 75. USBIEN Register
USBIEN (S:BEh) – USB Global Interrupt Enable Register
7
-
6
-
5
4
3
2
-
1
-
0
EWUPCPU EEORINT
ESOFINT
ESPINT
Bit
Bit
Number
Mnemonic Description
Reserved
7-6
5
-
The values read from these Bits are always 0. Do not set these Bits.
Wake up CPU Interrupt Enable Bit
EWUPCPU Set to enable the Wake Up CPU interrupt.
Clear to disable the Wake Up CPU interrupt.
End Of Reset Interrupt Enable Bit
4
EEOFINT Set to enable the End Of Reset interrupt. This bit is set after reset.
Clear to disable End Of Reset interrupt.
Start Of Frame Interrupt Enable Bit
ESOFINT Set to enable the SOF interrupt.
Clear to disable the SOF interrupt.
3
2-1
0
Reserved
-
The values read from these Bits are always 0. Do not set these Bits.
Suspend Interrupt Enable Bit
ESPINT
Set to enable Suspend interrupt.
Clear to disable Suspend interrupt.
Reset Value = 0001 0000b
Table 76. UEPNUM Register
UEPNUM (S:C7h) – USB Endpoint Number
7
-
6
-
5
-
4
-
3
-
2
-
1
0
EPNUM1
EPNUM0
Bit
Bit
Number Mnemonic Description
Reserved
7 - 2
1 - 0
-
The values read from these Bits are always 0. Do not set these Bits.
Endpoint Number Bits
Set this field with the number of the endpoint which shall be accessed when
reading or writing to registers UEPSTAX, UEPDATX, UBYCTLX or UEPCONX.
EPNUM1:
0
Reset Value = 0000 0000b
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Table 77. UEPCONX Register
UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM)
7
6
-
5
-
4
-
3
2
1
0
EPEN
DTGL
EPDIR
EPTYPE1
EPTYPE0
Bit
Bit
Number
Mnemonic Description
Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0 shall
always be enabled after a hardware or USB bus reset and participate in the
device configuration.
7
EPEN
Clear to disable the endpoint according to the device configuration.
Reserved
6 - 4
-
The values read from this bit is always 0. Do not set this bit.
Data Toggle Status Bit (Read-only)
Set by hardware when a DATA1 packet is received.
Cleared by hardware when a DATA0 packet is received.
Note: When a new data packet is received without DTGL toggling from 1 to 0 or 0
to 1, a packet may have been lost. When this occurs for a Bulk endpoint, the
device firmware shall consider the host has retried transmitting a properly
received packet because the host has not received a valid ACK, then the
firmware shall discard the new packet (N.B. The endpoint resets to DATA0 only
upon configuration).
3
DTGL
For interrupt endpoints, data toggling is managed as for Bulk endpoints when
used.
For Control endpoints, each SETUP transaction starts with a DATA0 and data
toggling is then used as for Bulk endpoints until the end of the Data stage (for a
control write transfer); the Status stage completes the data transfer with a DATA1
(for a control read transfer).
For Isochronous endpoints, the device firmware shall retrieve every new data
packet and may ignore this bit.
Endpoint Direction Bit
Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
This bit has no effect for Control endpoints.
2
EPDIR
Endpoint Type Bits
Set this field according to the endpoint configuration (Endpoint 0 shall always be
configured as Control):
EPTYPE1:
0
1 - 0
0
0
1
1
0
1
0
1
Control endpoint
Isochronous endpoint
Bulk endpoint
Interrupt endpoint
Reset Value = 0000 0000b
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Table 78. UEPSTAX Register
UEPSTAX (Soh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM)
7
6
-
5
4
3
2
1
0
DIR
STALLRQ
TXRDY
STLCRC
RXSETUP
RXOUT
TXCMP
Bit
Bit
Number
Mnemonic Description
Control Endpoint Direction Bit
This bit is relevant only if the endpoint is configured in Control type.
Set for the data stage. Clear otherwise.
7
DIR
Note: This bit should be configured on RXSETUP interrupt before any other bit is
changed. This also determines the status phase (IN for a control write and OUT
for a control read). This bit should be cleared for status stage of a Control Out
transaction.
Reserved
6
5
-
The values read from this Bits are always 0. Do not set this bit.
Stall Handshake Request Bit
Set to send a STALL answer to the host for the next handshake.Clear otherwise.
STALLRQ
TX Packet Ready Control Bit
Set after a packet has been written into the endpoint FIFO for IN data transfers.
Data shall be written into the endpoint FIFO only after this bit has been cleared.
Set this bit without writing data to the endpoint FIFO to send a Zero Length
Packet, which is generally recommended and may be required to terminate a
transfer when the length of the last data packet is equal to MaxPacketSize (e.g.,
for control read transfers).
4
TXRDY
Cleared by hardware, as soon as the packet has been sent for Isochronous
endpoints, or after the host has acknowledged the packet for Control, Bulk and
Interrupt endpoints.
Stall Sent Interrupt Flag/CRC Error Interrupt Flag
For Control, Bulk and Interrupt Endpoints:
Set by hardware after a STALL handshake has been sent as requested by
STALLRQ. Then, the endpoint interrupt is triggered if enabled in UEPIEN.
3
STLCRC Cleared by hardware when a SETUP packet is received (see RXSETUP).
For Isochronous Endpoints:
Set by hardware if the last data received is corrupted (CRC error on data). Then,
the endpoint interrupt is triggered if enabled in UEPIEN.
Cleared by hardware when a non corrupted data is received.
Received SETUP Interrupt Flag
Set by hardware when a valid SETUP packet has been received from the host.
RXSETUP Then, all the other Bits of the register are cleared by hardware and the endpoint
interrupt is triggered if enabled in UEPIEN.
2
1
Clear by software after reading the SETUP data from the endpoint FIFO.
Received OUT Data Interrupt Flag
Set by hardware after an OUT packet has been received. Then, the endpoint
interrupt is triggered if enabled in UEPIEN and all the following OUT packets to
RXOUT the endpoint are rejected (NACK’ed) until this bit is cleared. However, for Control
endpoints, an early SETUP transaction may overwrite the content of the endpoint
FIFO, even if its Data packet is received while this bit is set.
Clear by software after reading the OUT data from the endpoint FIFO.
Transmitted IN Data Complete Interrupt Flag
Set by hardware after an IN packet has been transmitted for Isochronous
endpoints and after it has been accepted (ACK’ed) by the host for Control, Bulk
and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled in
0
TXCMP
UEPIEN.
Clear by software before setting again TXRDY.
Reset Value = 0000 0000b
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Table 79. UEPRST Register
UEPRST (S:D5h) – USB Endpoint FIFO Reset Register
7
-
6
-
5
-
4
-
3
2
1
0
EP3RST
EP2RST
EP1RST
EP0RST
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 4
3
-
The values read from these Bits are always 0. Do not set these Bits.
Endpoint 3 FIFO Reset
EP3RST Set and clear to reset the endpoint 3 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 2 FIFO Reset
2
1
0
EP2RST Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 1 FIFO Reset
EP1RST Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 0 FIFO Reset
EP0RST Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Reset Value = 0000 0000b
Table 80. UEPINT Register
UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register
7
-
6
-
5
-
4
-
3
2
1
0
EP3INT
EP2INT
EP1INT
EP0INT
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 4
-
The values read from these Bits are always 0. Do not set these Bits.
Endpoint 3 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 3
interrupt is enabled in UEPIEN.
Must be cleared by software.
3
EP3INT
EP2INT
EP1INT
EP0INT
Endpoint 2 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 2
interrupt is enabled in UEPIEN.
2
1
0
Must be cleared by software.
Endpoint 1 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 1
interrupt is enabled in UEPIEN.
Must be cleared by software.
Endpoint 0 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 0
interrupt is enabled in UEPIEN.
Must be cleared by software.
Reset Value = 0000 0000b
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Table 81. UEPIEN Register
UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register
7
-
6
-
5
-
4
-
3
2
1
0
EP3INTE
EP2INTE
EP1INTE
EP0INTE
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 4
3
-
The values read from these Bits are always 0. Do not set these Bits.
Endpoint 3 Interrupt Enable Bit
EP3INTE Set to enable the interrupts for endpoint 3.
Clear to disable the interrupts for endpoint 3.
Endpoint 2 Interrupt Enable Bit
2
1
0
EP2INTE Set to enable the interrupts for endpoint 2.
Clear this bit to disable the interrupts for endpoint 2.
Endpoint 1 Interrupt Enable Bit
EP1INTE Set to enable the interrupts for the endpoint 1.
Clear to disable the interrupts for the endpoint 1.
Endpoint 0 Interrupt Enable Bit
EP0INTE Set to enable the interrupts for the endpoint 0.
Clear to disable the interrupts for the endpoint 0.
Reset Value = 0000 0000b
Table 82. UEPDATX Register
UEPDATX (S:CFh) – USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
Bit
Bit
Number
Mnemonic Description
Endpoint X FIFO Data
7 - 0
FDAT7:0 Data byte to be written to FIFO or data byte to be read from the FIFO, for the
Endpoint X (see EPNUM).
Reset Value = XXh
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Table 83. UBYCTLX Register
UBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM)
7
-
6
5
4
3
2
1
0
BYCT6
BYCT5
BYCT4
BYCT3
BYCT2
BYCT1
BYCT0
Bit
Bit
Number
Mnemonic Description
Reserved
7
-
The values read from this Bits are always 0. Do not set this bit.
Byte Count
6-0
BYCT7:0 Byte count of a received data packet. This byte count is equal to the number of
data Bytes received after the Data PID.
Reset Value = 0000 0000b
Table 84. UFNUML Register
UFNUML (S:BAh, Read-only) – USB Frame Number Low Register
7
6
5
4
3
2
1
0
FNUM7
FNUM6
FNUM5
FNUM4
FNUM3
FNUM2
FNUM1
FNUM0
Bit
Bit
Number
Mnemonic Description
Frame Number
Lower 8 Bits of the 11-bit Frame Number.
7 - 0
FNUM7:0
Reset Value = 00h
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Table 85. UFNUMH Register
UFNUMH (S:BBh, Read-only) – USB Frame Number High Register
7
-
6
-
5
4
3
-
2
1
0
CRCOK
CRCERR
FNUM10
FNUM9
FNUM8
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 3
-
The values read from these Bits are always 0. Do not set these Bits.
Frame Number CRC OK Bit
Set by hardware after a non corrupted Frame Number in Start of Frame Packet is
received.
Updated after every Start Of Frame packet reception.
5
4
CRCOK
Note: The Start Of Frame interrupt is generated just after the PID receipt.
Frame Number CRC Error Bit
Set by hardware after a corrupted Frame Number in Start of Frame Packet is
received.
CRCERR
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
Reserved
3
-
The values read from this Bits are always 0. Do not set this bit.
Frame Number
2 - 0
FNUM10:8 Upper 3 Bits of the 11-bit Frame Number. It is provided in the last received SOF
packet. FNUM does not change if a corrupted SOF is received.
Reset Value = 00h
Table 86. USBCLK Register
USBCLK (S:EAh) – USB Clock Divider Register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
USBCD1
USBCD0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 2
1 - 0
-
The values read from these Bits are always 0. Do not set these Bits.
USB Controller Clock Divider
2-bit divider for USB controller clock generation.
USBCD1:0
Reset Value = 0000 0000b
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MultiMedia Card
Controller
The AT8xC5132 implements a MultiMedia Card (MMC) controller. The MMC is used to
store files in removable Flash memory cards that can be easily plugged or removed
from the application.
Card Concept
The basic MultiMedia Card concept is based on transferring data via a minimal number
of signals.
Card Signals
The communication signals are:
•
CLK: with each cycle of this signal an one bit transfer on the command and data
lines is done. The frequency may vary from zero to the maximum clock frequency.
•
CMD: is a bidirectional command channel used for card initialization and data
transfer commands. The CMD signal has two operation modes: open-drain for
initialization mode and push-pull for fast command transfer. Commands are sent
from the MultiMedia Card bus master to the card and responses from the cards to
the host.
•
DAT: is a bidirectional data channel. The DAT signal operates in push-pull mode.
Only one card or the host is driving this signal at a time.
Card Registers
Bus Concept
82
Within the card interface five registers are defined: OCR, CID, CSD, RCA and DSR.
These can be accessed only by corresponding commands.
The 32-bit Operation Conditions Register (OCR) stores the VDD voltage profile of the
card. The register is optional and can be read only.
The 128-bit wide CID register carries the card identification information (Card ID) used
during the card identification procedure.
The 128-bit wide Card-Specific Data register (CSD) provides information on how to
access the card contents. The CSD defines the data format, error correction type, maxi-
mum data access time, data transfer speed, and whether the DSR register can be used.
The 16-bit Relative Card Address register (RCA) carries the card address assigned by
the host during the card identification. This address is used for the addressed host-card
communication after the card identification procedure
The 16-bit Driver Stage Register (DSR) can be optionally used to improve the bus per-
formance for extended operating conditions (depending on parameters like bus length,
transfer rate or number of cards).
The MultiMedia Card bus is designed to connect either solid-state mass-storage mem-
ory or I/O-devices in a card format to multimedia applications. The bus implementation
allows the coverage of application fields from low-cost systems to systems with a fast
data transfer rate. It is a single master bus with a variable number of slaves. The Multi-
Media Card bus master is the bus controller and each slave is either a single mass
storage card (with possibly different technologies such as ROM, OTP, Flash etc.) or an
I/O-card with its own controlling unit (on card) to perform the data transfer.
The MultiMedia Card bus also includes power connections to supply the cards.
The bus communication uses a special protocol (MultiMedia Card bus protocol) which is
applicable for all devices. Therefore, the payload data transfer between the host and the
cards can be bidirectional.
AT8xC5132
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AT8xC5132
Bus Lines
The MultiMedia Card bus architecture requires all cards to be connected to the same set
of lines. No card has an individual connection to the host or other devices, which
reduces the connection costs of the MultiMedia Card system.
The bus lines can be divided into three groups:
•
•
•
Power supply: VSS1 and VSS2, VDD – used to supply the cards.
Data transfer: MCMD, MDAT – used for bidirectional communication.
Clock: MCLK – used to synchronize data transfer across the bus.
Bus Protocol
After a Power-on reset, the host must initialize the cards by a special message-based
MultiMedia Card bus protocol. Each message is represented by one of the following
tokens:
•
Command: a command is a token which starts an operation. A command is
transferred serially from the host to the card on the MCMD line.
•
Response: a response is a token which is sent from an addressed card (or all
connected cards) to the host as an answer to a previously received command. It is
transferred serially on the MCMD line.
•
Data: data can be transferred from the card to the host or vice-versa. Data is
transferred serially on the MDAT line.
Card addressing is implemented using a session address assigned during the initializa-
tion phase, by the bus controller to all currently connected cards. Individual cards are
identified by their CID number. This method requires that every card will have an unique
CID number. To ensure uniqueness of CIDs the CID register contains 24 Bits (MID and
OID fields) which are defined by the MMCA. Every card manufacturers is required to
apply for an unique MID (and optionally OID) number.
MultiMedia Card bus data transfers are composed of these tokens. One data transfer is
a bus operation. There are different types of operations. Addressed operations always
contain a command and a response token. In addition, some operations have data
token, the others transfer their information directly within the command or response
structure. In this case no data token is present in an operation. The Bits on the MDAT
and the MCMD lines are transferred synchronous to the host clock.
Two types of data transfer commands are defined:
•
Sequential commands: These commands initiate a continuous data stream, they
are terminated only when a stop command follows on the MCMD line. This mode
reduces the command overhead to an absolute minimum.
•
Block-oriented commands: These commands send data block succeeded by CRC
Bits. Both read and write operations allow either single or multiple block
transmission. A multiple block transmission is terminated when a stop command
follows on the MCMD line similarly to the stream read.
Figure 52 to Figure 56 show the different types of operations, on these figures, grayed
tokens are from host to card(s) while white tokens are from card(s) to host.
Figure 52. Sequential Read Operation
Stop Command
MCMD
MDAT
Command Response
Command Response
Data Stream
Data Transfer Operation
Data Stop Operation
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Figure 53. (Multiple) Block Read Operation
Stop Command
MCMD
MDAT
Command Response
Command Response
Data Block CRC Data Block CRC Data Block CRC
Block Read Operation
Data Stop Operation
Multiple Block Read Operation
As shown in Figure 54 and Figure 55 the data write operation uses a simple busy signal-
ling of the write operation duration on the data line (MDAT).
Figure 54. Sequential Write Operation
Stop Command
MCMD
MDAT
Command Response
Command Response
Data Stream
Busy
Data Transfer Operation
Data Stop Operation
Figure 55. (Multiple) Block Write Operation
Stop Command
MCMD
MDAT
Command Response
Command Response
Data Block CRC Status Busy
Data Block CRC Status Busy
Data Stop Operation
Block Write Operation
Multiple Block Write Operation
Figure 56. No Response and No Data Operation
MCMD
MDAT
Command
Command Response
No Response Operation
No Data Operation
Command Token Format
As shown in Figure 57, commands have a fixed code length of 48 Bits. Each command
token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit:
a high level on MCMD line. The command content is preceded by a Transmission bit: a
high level on MCMD line for a command token (host to card) and succeeded by a 7-bit
CRC so that transmission errors can be detected and the operation may be repeated.
Command content contains the command index and address information or parameters.
Figure 57. Command Token Format
0
1
Content
CRC
1
Total Length = 48 Bits
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Table 87. Command Token Format
Bit Position
Width (Bits)
Value
47
1
46
1
45:40
39:8
32
-
7:1
7
0
6
-
1
‘0’
‘1’
-
‘1’
Transmission
bit
Command
Index
Start bit
Argument
CRC7
End bit
Description
Response Token Format
There are five types of response tokens (R1 to R5). As shown in Figure 58, responses
have a code length of 48 Bits or 136 Bits. A response token is preceded by a Start bit: a
low level on MCMD line and succeeded by an End bit: a high level on MCMD line. The
command content is preceded by a Transmission bit: a low level on MCMD line for a
response token (card to host) and succeeded (R1,R2,R4,R5) or not (R3) by a 7-bit
CRC.
Response content contains mirrored command and status information (R1 response),
CID register or CSD register (R2 response), OCR register (R3 response), or RCA regis-
ter (R4 and R5 response).
Figure 58. Response Token Format
R1, R4, R5
0
0
0
0
0
0
Content
CRC
1
1
Total Length = 48 Bits
R3
R2
Content
Total Length = 48 Bits
Content = CID or CSD
Total Length = 136 Bits
CRC
1
Table 88. R1 Response Format (Normal Response)
Bit Position
Width (Bits)
Value
47
1
46
1
45:40
39:8
32
-
7:1
7
0
6
-
1
‘0’
‘0’
-
‘1’
Transmission
bit
Command
Index
Start bit
Card Status
CRC7
End bit
Description
Table 89. R2 Response Format (CID and CSD registers)
Bit Position
Width (Bits)
Value
135
1
134
1
[133:128]
6
[127:1]
0
32
-
1
‘0’
‘0’
‘111111’
‘1’
Transmission
bit
Start bit
Reserved
Argument
End bit
Description
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Table 90. R3 Response Format (OCR Register)
Bit Position
Width (Bits)
Value
47
1
46
1
[45:40]
6
[39:8]
[7:1]
7
0
32
-
1
‘0’
‘0’
‘111111’
‘1111111’
‘1’
Transmission
bit
OCR
register
Start bit
Reserved
Reserved
End bit
Description
Table 91. R4 Response Format (Fast I/O)
Bit Position
Width (Bits)
Value
47
1
46
1
[45:40]
6
[39:8]
[7:1]
0
32
-
7
-
1
‘0’
‘0’
‘100111’
‘1’
Transmission
bit
Command
Index
Start bit
Argument
CRC7
End bit
Description
Table 92. R5 Response Format
Bit Position
Width (Bits)
Value
47
1
46
1
[45:40]
6
[39:8]
[7:1]
0
32
-
7
-
1
‘0’
‘0’
‘101000’
‘1’
Transmission
bit
Command
Index
Start bit
Argument
CRC7
End bit
Description
Data Packet Format
There are two types of data packets: stream and block. As shown in Figure 59, stream
data packets have an indeterminate length while block packets have a fixed length
depending on the block length. Each data packet is preceded by a Start bit: a low level
on MCMD line and succeeded by an End bit: a high level on MCMD line. Due to the fact
that there is no predefined end in stream packets, CRC protection is not included in this
case. The CRC protection algorithm for block data is a 16-bit CCITT polynomial.
Figure 59. Data Token Format
Sequential Data
0
0
Content
1
1
Block Data
Content
CRC
Block Length
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Clock Control
The MMC bus clock signal can be used by the host to turn the cards into energy saving
mode or to control the data flow (to avoid under-run or over-run conditions) on the bus.
The host is allowed to lower the clock frequency or shut it down.
There are a few restrictions the host must follow:
•
The bus frequency can be changed at any time (under the restrictions of maximum
data transfer frequency, defined by the cards, and the identification frequency
defined by the specification document).
•
It is an obvious requirement that the clock must be running for the card to output
data or response tokens. After the last MultiMedia Card bus transaction, the host is
required, to provide 8 (eight) clock cycles for the card to complete the operation
before shutting down the clock. Following is a list of the various bus transactions:
•
•
•
•
•
A command with no response. 8 clocks after the host command End bit.
A command with response. 8 clocks after the card command End bit.
A read data transaction. 8 clocks after the End bit of the last data block.
A write data transaction. 8 clocks after the CRC status token.
The host is allowed to shut down the clock of a “busy” card. The card will complete
the programming operation regardless of the host clock. However, the host must
provide a clock edge for the card to turn off its busy signal. Without a clock edge the
card (unless previously disconnected by a deselect command-CMD7) will force the
MDAT line down, forever.
Description
The MMC controller interfaces to the C51 core through the following eight special func-
tion registers:
MMCON0, MMCON1, MMCON2, the three MMC control registers (see Figure 94 to
Figure ); MMSTA, the MMC status register (see Figure 97); MMINT, the MMC interrupt
register (see Figure ); MMMSK, the MMC interrupt mask register (see Figure 99);
MMCMD, the MMC command register (see Figure 100); MMDAT, the MMC data regis-
ter (see Figure ); and MMCLK, the MMC clock register (see Figure 102).
As shown in Figure 60, the MMC controller is divided in four blocks: the clock generator
that handles the MCLK (formally the MMC CLK) output to the card, the command line
controller that handles the MCMD (formally the MMC CMD) line traffic to or from the
card, the data line controller that handles the MDAT (formally the MMC DAT) line traffic
to or from the card, and the interrupt controller that handles the MMC controller interrupt
sources. These blocks are detailed in the following sections.
Figure 60. MMC Controller Block Diagram
MCLK
OSC
CLOCK
Clock
Generator
Command Line
Controller
MCMD
MMC
Interrupt
Request
Interrupt
Controller
Data Line
Controller
MDAT
Internal
Bus
8
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Clock Generator
The MMC clock is generated by division of the oscillator clock (FOSC) issued from the
Clock Controller block as detailed in Section "Oscillator", page 12. The division factor is
given by MMCD7:0 Bits in MMCLK register. Figure 61 shows the MMC clock generator
and its output clock calculation formula.
Figure 61. MMC Clock Generator and Symbol
OSCclk
MMCD + 1
OSC
CLOCK
MMCclk = -----------------------------
Controller Clock
MMC Clock
MMCLK
MMC
CLOCK
MMCEN
MMCON2.7
MMCD7:0
MMC Clock Symbol
As soon as MMCEN bit in MMCON2 is set, the MMC controller receives its system
clock. The MMC command and data clock is generated on MCLK output and sent to the
command line and data line controllers. Figure 62 shows the MMC controller configura-
tion flow.
As exposed in Section “Clock Control”, MMCD7:0 Bits can be used to dynamically
increase or reduce the MMC clock.
Figure 62. Configuration Flow
MMC Controller
Configuration
Configure MMC Clock
MMCLK = XXh
MMCEN = 1
FLOWC = 0
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Command Line
Controller
As shown in Figure 63, the command line controller is divided in two channels: the com-
mand transmitter channel that handles the command transmission to the card through
the MCMD line and the command receiver channel that handles the response reception
from the card through the MCMD line. These channels are detailed in the following
sections.
Figure 63. Command Line Controller Block Diagram
Data Converter
// -> Serial
CRC7
Generator
TX Pointer
5-byte FIFO
MMCMD
Write
CTPTR
MMCON0.4
TX COMMAND Line
Finished State Machine
MMINT.5
EOCI
CFLCK
MMSTA.0
CMDEN
MMCON1.0
MCMD
Command Transmitter
MMSTA.2
MMSTA.1
CRC7S RESPFS
Data Converter
Serial -> //
CRC7 and Format
Checker
RX Pointer
17-byte FIFO
MMCMD
Read
CRPTR
MMCON0.5
RX COMMAND Line
Finished State Machine
MMINT.6
EORI
RESPEN RFMT CRCDIS
MMCON1.1 MMCON0.1 MMCON0.0
Command Receiver
Command Transmitter
To send a command to the card, the user must load the command index (1 byte) and
argument (4 Bytes) in the command transmit FIFO using the MMCMD register. Before
starting transmission by setting and clearing the CMDEN bit in MMCON1 register, the
user must first configure:
•
•
•
RESPEN bit in MMCON1 register to indicate whether a response is expected or not.
RFMT bit in MMCON0 register to indicate the response size expected.
CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the
response will be computed or not. In order to avoid CRC error, CRCDIS may be set
for responses that do not include CRC7.
Figure 64 summarizes the command transmission flow.
As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicat-
ing that write to the FIFO is locked. This mechanism is implemented to avoid command
over-run.
The end of the command transmission is signalled by the EOCI flag in MMINT register
becoming set. This flag may generate an MMC interrupt request as detailed in Section
"Interrupt", page 97. The end of the command transmission also resets the CFLCK flag.
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The user may abort command loading by setting and clearing the CTPTR bit in
MMCON0 register which resets the write pointer to the transmit FIFO.
Figure 64. Command Transmission Flow
Command
Transmission
Load Command in
Buffer
MMCMD = Index
MMCMD = Argument
Configure Response
RESPEN = X
RFMT = X
CRCDIS = X
Transmit Command
CMDEN = 1
CMDEN = 0
Command Receiver
The end of the response reception is signalled by the EORI flag in MMINT register. This
flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 97.
When this flag is set, two other flags in MMSTA register: RESPFS and CRC7S give a
status on the response received. RESPFS indicates if the response format is correct or
not: the size is the one expected (48 Bits or 136 Bits) and a valid End bit has been
received, and CRC7S indicates if the CRC7 computation is correct or not. These Flags
are cleared when a command is sent to the card and updated when the response has
been received.
The user may abort response reading by setting and clearing the CRPTR bit in
MMCON0 register which resets the read pointer to the receive FIFO.
According to the MMC specification delay between a command and a response (for-
mally NCR parameter) cannot exceed 64 MMC clock periods. To avoid any locking of the
MMC controller when card does not send its response (e.g. physically removed from the
bus), user must launch a timeout period to exit from such situation. In case of timeout
user may reset the command controller and its internal state machine by setting and
clearing the CCR bit in MMCON2 register.
This timeout may be disarmed when receiving the response.
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Data Line Controller
The data line controller is based on a 16-byte FIFO used both by the data transmitter
channel and by the data receiver channel.
Figure 65. Data Line Controller Block Diagram
MMINT.0
MMINT.2
MMSTA.3
MMSTA.4
F1EI
F1FI
DATFS CRC16S
CRC16 and Format
Checker
Data Converter
Serial -> //
8-byte
TX Pointer
FIFO 1
MCBI
MMINT.1
CBUSY
MMSTA.5
MDAT
DTPTR
MMCON0.6
16-byte FIFO
MMDAT
Data Converter
// -> Serial
CRC16
Generator
RX Pointer
DRPTR
MMCON0.7
8-byte
MMINT.4
DATA Line
Finished State Machine
FIFO 2
EOFI
DFMT
MBLOCK DATEN DATDIR BLEN3:0
MMCON0.2 MMCON0.3 MMCON1.2 MMCON1.3 MMCON1.7:4
F2EI
MMINT.1
F2FI
MMINT.3
FIFO Implementation
The 16-byte FIFO is based on a dual 8-byte FIFO managed using two pointers and four
flags indicating the status full and empty of each FIFO.
Pointers are not accessible to user but can be reset at any time by setting and clearing
DRPTR and DTPTR Bits in MMCON0 register. Resetting the pointers is equivalent to
abort the writing or reading of data.
F1EI and F2EI flags in MMINT register signal when set that respectively FIFO1 and
FIFO2 are empty. F1FI and F2FI flags in MMINT register signal when set that respec-
tively FIFO1 and FIFO2 are full. These flags may generate an MMC interrupt request as
detailed in Section “Interrupt”.
Data Configuration
Before sending or receiving any data, the data line controller must be configured accord-
ing to the type of the data transfer considered. This is achieved using the Data Format
bit: DFMT in MMCON0 register. Clearing DFMT bit enables the data stream format
while setting DFMT bit enables the data block format. In data block format, user must
also configure the single or multi-block mode by clearing or setting the MBLOCK bit in
MMCON0 register and the block length using BLEN3:0 Bits in MMCON1 according to
Table 93. Figure 66 summarizes the data modes configuration flows.
Table 93. Block Length Programming
BLEN3:0
BLEN = 0000 to 1011
> 1011
Block Length (Byte)
Length = 2BLEN: 1 to 2048
Reserved: do not program BLEN3:0 > 1011
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Figure 66. Data Controller Configuration Flows
Data Stream
Configuration
Data Single Block
Configuration
Data Multi-block
Configuration
Configure Format
Configure Format
DFMT = 1
Configure Format
DFMT = 1
DFMT = 0
MBLOCK = 0
MBLOCK = 1
BLEN3:0 = XXXXb
BLEN3:0 = XXXXb
Data Transmitter
Configuration
For transmitting data to the card, user must first configure the data controller in trans-
mission mode by setting the DATDIR bit in MMCON1 register.
Figure 67 summarizes the data stream transmission flows in both polling and interrupt
modes while Figure 68 summarizes the data block transmission flows in both polling
and interrupt modes, these flows assume that block length is greater than 16 data.
Data Loading
Data is loaded in the FIFO by writing to MMDAT register. Number of data loaded may
vary from 1 to 16 Bytes. Then if necessary (more than 16 Bytes to send) user must wait
that one FIFO becomes empty (F1EI or F2EI set) before loading 8 new data.
Data Transmission
Transmission is enabled by setting and clearing DATEN bit in MMCON1 register.
Data is transmitted immediately if the response has already been received, or is delayed
after the response reception if its status is correct. In both cases transmission is delayed
if a card sends a busy state on the data line until the end of this busy condition.
According to the MMC specification, the data transfer from the host to the card may not
start sooner than 2 MMC clock periods after the card response was received (formally
NWR parameter). To address all card types, this delay can be programmed using
DATD1:0 Bits in MMCON2 register from 2 MMC clock periods when DATD1:0 Bits are
cleared to 8 MMC clock periods when DATD2:0 Bits are set, by step of 2 MMC clock
periods.
End of Transmission
The end of data frame (block or stream) transmission is signalled by the EOFI flag in
MMINT register. This flag may generate an MMC interrupt request as detailed in Section
"Interrupt", page 97.
In data stream mode, EOFI flag is set, after reception of the End bit. This assumes user
has previously sent the STOP command to the card, which is the only way to stop
stream transfer.
In data block mode, EOFI flag is set, after reception of the CRC status token (see
Figure 55). Two other flags in MMSTA register: DATFS and CRC16S report a status on
the frame sent. DATFS indicates if the CRC status token format is correct or not, and
CRC16S indicates if the card has found the CRC16 of the block correct or not.
Busy Status
As shown in Figure 55 the card uses a busy token during a block write operation. This
busy status is reported by the CBUSY flag in MMSTA register and by the MCBI flag in
MMINT which is set every time CBUSY toggles, i.e. when the card enters and exits its
busy state. This flag may generate an MMC interrupt request as detailed in Section
"Interrupt", page 97.
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Figure 67. Data Stream Transmission Flows
Data Stream
Transmission
Data Stream
Initialization
Data Stream
Transmission ISR
FIFOs Filling
Write 16 Data to MMDAT
FIFOs Filling
Write 16 Data to MMDAT
FIFO Empty?
F1EI or F2EI = 1?
Start Transmission
DATEN = 1
Unmask FIFOs Empty
F1EM = 0
DATEN = 0
F2EM = 0
FIFO Filling
Write 8 Data to MMDAT
Start Transmission
DATEN = 1
FIFO Empty?
F1EI or F2EI = 1?
No More Data
To Send?
DATEN = 0
FIFO Filling
Write 8 Data to MMDAT
Mask FIFOs Empty
F1EM = 1
F2EM = 1
No More Data
to Send?
Send
STOP Command
Send
STOP Command
b. Interrupt Mode
a. Polling Mode
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Figure 68. Data Block Transmission Flows
Data Block
Data Block
Data Block
Transmission
Initialization
Transmission ISR
FIFOs Filling
Write 16 Data to MMDAT
FIFOs Filling
Write 16 Data to MMDAT
FIFO Empty?
F1EI or F2EI = 1?
Start Transmission
DATEN = 1
Unmask FIFOs Empty
F1EM = 0
DATEN = 0
F2EM = 0
FIFO Filling
Write 8 Data to MMDAT
Start Transmission
DATEN = 1
FIFO Empty?
F1EI or F2EI = 1?
No More Data
To Send?
DATEN = 0
FIFO Filling
Write 8 Data to MMDAT
Mask FIFOs Empty
F1EM = 1
F2EM = 1
No More Data
to Send?
b. Interrupt Mode
a. Polling Mode
Data Receiver
Configuration
To receive data from the card, the user must first configure the data controller in recep-
tion mode by clearing the DATDIR bit in MMCON1 register.
Figure 69 summarizes the data stream reception flows in both polling and interrupt
modes while Figure 70 summarizes the data block reception flows in both polling and
interrupt modes, these flows assume that block length is greater than 16 Bytes.
Data Reception
The end of data frame (block or stream) reception is signalled by the EOFI flag in
MMINT register. This flag may generate an MMC interrupt request as detailed in Section
"Interrupt", page 97. When this flag is set, two other flags in MMSTA register: DATFS
and CRC16S give a status on the frame received. DATFS indicates if the frame format
is correct or not: a valid End bit has been received, and CRC16S indicates if the CRC16
computation is correct or not. In case of data stream CRC16S has no meaning and
stays cleared.
According to the MMC specification data transmission, the card starts after the access
time delay (formally NAC parameter) beginning from the End bit of the read command.
To avoid any locking of the MMC controller when card does not send its data (e.g. phys-
ically removed from the bus), the user must launch a time-out period to exit from such
situation. In case of time-out the user may reset the data controller and its internal state
machine by setting and clearing the DCR bit in MMCON2 register.
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This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving
end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4).
Data Reading
Data is read from the FIFO by reading to MMDAT register. Each time one FIFO
becomes full (F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data.
Figure 69. Data Stream Reception Flows
Data Stream
Reception
Data Stream
Initialization
Data Stream
Reception ISR
Unmask FIFOs Full
F1FM = 0
FIFO Full?
F1FI or F2FI = 1?
FIFO Full?
F1FI or F2FI = 1?
F2FM = 0
FIFO Reading
read 8 data from MMDAT
FIFO Reading
read 8 data from MMDAT
No More Data
To Receive?
No More Data
To Receive?
Mask FIFOs Full
F1FM = 1
Send
STOP Command
F2FM = 1
Send
a. Polling Mode
STOP Command
b. Interrupt Mode
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Figure 70. Data Block Reception Flows
Data Block
Reception
Data Block
Initialization
Data Block
Reception ISR
Start Transmission
DATEN = 1
Unmask FIFOs Full
F1FM = 0
FIFO Full?
F1EI or F2EI = 1?
DATEN = 0
F2FM = 0
Start Transmission
DATEN = 1
FIFO Reading
read 8 data from MMDAT
FIFO Full?
F1EI or F2EI = 1?
DATEN = 0
No More Data
To Receive?
FIFO Reading
read 8 data from MMDAT
Mask FIFOs Full
F1FM = 1
No More Data
To Receive?
F2FM = 1
b. Interrupt Mode
a. Polling Mode
Flow Control
To allow transfer at high speed without taking care of CPU oscillator frequency, the
FLOWC bit in MMCON2 allows control of the data flow in both transmission and
reception.
During transmission, setting the FLOWC bit has the following effects:
•
•
MMCLK is stopped when both FIFOs become empty: F1EI and F2EI set.
MMCLK is restarted when one of the FIFOs becomes full: F1EI or F2EI cleared.
During reception, setting the FLOWC bit has the following effects:
•
•
MMCLK is stopped when both FIFOs become full: F1FI and F2FI set.
MMCLK is restarted when one of the FIFOs becomes empty: F1FI or F2FI cleared.
As soon as the clock is stopped, the MMC bus is frozen and remains in its state until the
clock is restored by writing or reading data in MMDAT.
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Interrupt
Description
As shown in Figure 71, the MMC controller implements eight interrupt sources reported
in MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These
flags were detailed in the previous sections.
All of these sources are maskable separately using MCBM, EORM, EOCM, EOFM,
F2FM, F1FM, and F2EM mask bits, respectively, in MMMSK register.
The interrupt request is generated each time an unmasked flag is set, and the global
MMC controller interrupt enable bit is set (EMMC in IEN1 register).
Reading the MMINT register automatically clears the interrupt flags (acknowledgment).
This implies that register content must be saved and tested interrupt flag by interrupt
flag to be sure not to overlook any interrupts.
Figure 71. MMC Controller Interrupt System
MCBI
MMINT.7
MCBM
MMMSK.7
EORI
MMINT.6
EORM
MMMSK.6
EOCI
MMINT.5
EOCM
MMMSK.5
EOFI
MMINT.4
MMC Interface
Interrupt Request
EOFM
MMMSK.4
F2FI
MMINT.3
EMMC
IEN1.0
F2FM
MMMSK.3
F1FI
MMINT.2
F1FM
MMMSK.2
F2EI
MMINT.1
F2EM
MMMSK.1
F1EI
MMINT.0
F1EM
MMMSK.0
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Registers
Table 94. MMCON0 Register
MMCON0 (S:E4h) – MMC Control Register 0
7
6
5
4
3
2
1
0
DRPTR
DTPTR
CRPTR
CTPTR
MBLOCK
DFMT
RFMT
CRCDIS
Bit
Bit
Number
Mnemonic Description
Data Receive Pointer Reset Bit
7
6
5
4
3
2
1
0
DRPTR
DTPTR
CRPTR
CTPTR
Set to reset the read pointer of the data FIFO.
Clear to release the read pointer of the data FIFO.
Data Transmit Pointer Reset Bit
Set to reset the write pointer of the data FIFO.
Clear to release the write pointer of the data FIFO.
Command Receive Pointer Reset Bit
Set to reset the read pointer of the receive command FIFO.
Clear to release the read pointer of the receive command FIFO.
Command Transmit Pointer Reset Bit
Set to reset the write pointer of the transmit command FIFO.
Clear to release the read pointer of the transmit command FIFO.
Multi-block Enable Bit
MBLOCK Set to select multi-block data format.
Clear to select single block data format.
Data Format Bit
Set to select the block-oriented data format.
Clear to select the stream data format.
DFMT
RFMT
Response Format Bit
Set to select the 48-bit response format.
Clear to select the 136-bit response format.
CRC7 Disable Bit
CRCDIS Set to disable the CRC7 computation when receiving a response.
Clear to enable the CRC7 computation when receiving a response.
Reset Value = 0000 0000b
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Table 95. MMCON1 Register
MMCON1 (S:E5h) – MMC Control Register 1
7
6
5
4
3
2
1
0
BLEN3
BLEN2
BLEN1
BLEN0
DATDIR
DATEN
RESPEN
CMDEN
Bit
Bit
Number
Mnemonic Description
Block Length Bits
Refer to Table 93 for Bits description. Do not program value > 1011b.
7 - 4
3
BLEN3:0
Data Direction Bit
DATDIR Set to select data transfer from host to card (write mode).
Clear to select data transfer from card to host (read mode).
Data Transmission Enable Bit
2
DATEN
Set and clear to enable data transmission immediately or after response has
been received.
Response Enable Bit
1
0
RESPEN Set and clear to enable the reception of a response following a command
transmission.
Command Transmission Enable Bit
CMDEN
Set and clear to enable transmission of the command FIFO to the card.
Reset Value = 0000 0000b
Table 96. MMCON2 Register
MMCON2 (S:E6h) – MMC Control Register 2
7
6
5
4
-
3
-
2
1
0
MMCEN
DCR
CCR
DATD1
DATD0
FLOWC
Bit
Bit
Number
Mnemonic Description
MMC Clock Enable Bit
7
MMCEN Set to enable the MCLK clocks and activate the MMC controller.
Clear to disable the MMC clocks and freeze the MMC controller.
Data Controller Reset Bit
Set and clear to reset the data line controller in case of transfer abort.
6
5
DCR
Command Controller Reset Bit
Set and clear to reset the command line controller in case of transfer abort.
CCR
Reserved
4 - 3
-
The values read from these Bits are always 0. Do not set these Bits.
Data Transmission Delay Bits
Used to delay the data transmission after a response from 2 MMC clock periods
(all Bits cleared) to 8 MMC clock periods (all Bits set) by step of 2 MMC clock
periods.
2 - 1
DATD1:0
MMC Flow Control Bit
0
FLOWC Set to enable the flow control during data transfers.
Clear to disable the flow control during data transfers.
Reset Value = 0000 0000b
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Table 97. MMSTA Register
MMSTA (S:DEh Read Only) – MMC Control and Status Register
7
-
6
-
5
4
3
2
1
0
CBUSY
CRC16S
DATFS
CRC7S
RESPFS
CFLCK
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
5
-
The values read from these Bits are always 0. Do not set these Bits.
Card Busy Flag
CBUSY
Set by hardware when the card sends a busy state on the data line.
Cleared by hardware when the card no more sends a busy state on the data line.
CRC16 Status Bit
Transmission mode
Set by hardware when the token response reports a good CRC.
4
3
CRC16S Cleared by hardware when the token response reports a bad CRC.
Reception mode
Set by hardware when the CRC16 received in the data block is correct.
Cleared by hardware when the CRC16 received in the data block is not correct.
Data Format Status Bit
Transmission mode
Set by hardware when the format of the token response is correct.
DATFS
CRC7S
Cleared by hardware when the format of the token response is not correct.
Reception mode
Set by hardware when the format of the frame is correct.
Cleared by hardware when the format of the frame is not correct.
CRC7 Status Bit
Set by hardware when the CRC7 computed in the response is correct.
Cleared by hardware when the CRC7 computed in the response is not correct.
2
1
This bit is not relevant when CRCDIS is set.
Response Format Status Bit
RESPFS Set by hardware when the format of a response is correct.
Cleared by hardware when the format of a response is not correct.
Command FIFO Lock Bit
Set by hardware to signal user not to write in the transmit command FIFO: busy
0
CFLCK
state.
Cleared by hardware to signal user the transmit command FIFO is available: idle
state.
Reset Value = 0000 0000b
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Table 98. MMINT Register
MMINT (S:E7h Read Only) – MMC Interrupt Register
7
6
5
4
3
2
1
0
MCBI
EORI
EOCI
EOFI
F2FI
F1FI
F2EI
F1EI
Bit
Bit
Number
Mnemonic Description
MMC Card Busy Interrupt Flag
Set by hardware when the card enters or exits its busy state (when the busy
signal is asserted or deasserted on the data line).
Cleared when reading MMINT.
7
MCBI
End of Response Interrupt Flag
6
5
4
3
2
1
0
EORI
EOCI
EOFI
F2FI
F1FI
F2EI
F1EI
Set by hardware at the end of response reception.
Cleared when reading MMINT.
End of Command Interrupt Flag
Set by hardware at the end of command transmission.
Clear when reading MMINT.
End of Frame Interrupt Flag
Set by hardware at the end of frame (stream or block) transfer.
Clear when reading MMINT.
FIFO 2 Full Interrupt Flag
Set by hardware when second FIFO becomes full.
Cleared by hardware when second FIFO becomes empty.
FIFO 1 Full Interrupt Flag
Set by hardware when first FIFO becomes full.
Cleared by hardware when first FIFO becomes empty.
FIFO 2 Empty Interrupt Flag
Set by hardware when second FIFO becomes empty.
Cleared by hardware when second FIFO becomes full.
FIFO 1 Empty Interrupt Flag
Set by hardware when first FIFO becomes empty.
Cleared by hardware when first FIFO becomes full.
Reset Value = 0000 0011b
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Table 99. MMMSK Register
MMMSK (S:DFh) – MMC Interrupt Mask Register
7
6
5
4
3
2
1
0
MCBM
EORM
EOCM
EOFM
F2FM
F1FM
F2EM
F1EM
Bit
Bit
Number
Mnemonic Description
MMC Card Busy Interrupt Mask Bit
7
6
5
4
3
2
1
0
MCBM
EORM
EOCM
EOFM
F2FM
F1FM
F2EM
F1EM
Set to prevent MCBI flag from generating an MMC interrupt.
Clear to allow MCBI flag to generate an MMC interrupt.
End Of Response Interrupt Mask Bit
Set to prevent EORI flag from generating an MMC interrupt.
Clear to allow EORI flag to generate an MMC interrupt.
End Of Command Interrupt Mask Bit
Set to prevent EOCI flag from generating an MMC interrupt.
Clear to allow EOCI flag to generate an MMC interrupt.
End Of Frame Interrupt Mask Bit
Set to prevent EOFI flag from generating an MMC interrupt.
Clear to allow EOFI flag to generate an MMC interrupt.
FIFO 2 Full Interrupt Mask Bit
Set to prevent F2FI flag from generating an MMC interrupt.
Clear to allow F2FI flag to generate an MMC interrupt.
FIFO 1 Full Interrupt Mask Bit
Set to prevent F1FI flag from generating an MMC interrupt.
Clear to allow F1FI flag to generate an MMC interrupt.
FIFO 2 Empty Interrupt Mask Bit
Set to prevent F2EI flag from generating an MMC interrupt.
Clear to allow F2EI flag to generate an MMC interrupt.
FIFO 1 Empty Interrupt Mask Bit
Set to prevent F1EI flag from generating an MMC interrupt.
Clear to allow F1EI flag to generate an MMC interrupt.
Reset Value = 1111 1111b
Table 100. MMCMD Register
MMCMD (S:DDh) – MMC Command Register
7
6
5
4
3
2
1
0
MC7
MC6
MC5
MC4
MC3
MC2
MC1
MC0
Bit
Bit
Number
Mnemonic Description
MMC Command Receive Byte
Output (read) register of the response FIFO.
7 - 0
MC7:0
MMC Command Transmit Byte
Input (write) register of the command FIFO.
Reset Value = 1111 1111b
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Table 101. MMDAT Register
MMDAT (S:DCh) – MMC Data Register
7
6
5
4
3
2
1
0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit
Bit
Number
Mnemonic Description
MMC Data Byte
Input (write) or output (read) register of the data FIFO.
7 - 0
MD7:0
Reset Value = 1111 1111b
Table 102. MMCLK Register
MMCLK (S:EDh) – MMC Clock Divider Register
7
6
5
4
3
2
1
0
MMCD7
MMCD6
MMCD5
MMCD4
MMCD3
MMCD2
MMCD1
MMCD0
Bit
Bit
Number
Mnemonic Description
MMC Clock Divider
8-bit divider for MMC clock generation.
7 - 0
MMCD7:0
Reset Value = 0000 0000b
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IDE/ATAPI Interface
The AT8xC5132 provide an IDE/ATAPI interface allowing connection of devices such as
CD-ROM reader, CompactFlash cards, hard disk drive, etc. It consists of a 16-bit data
transfer (read or write) between the AT8xC5132 and the IDE devices.
Description
The IDE interface mode is enabled by setting the EXT16 bit in AUXR (see Table 28 on
page 30). As soon as this bit is set, all MOVX instructions read or write are done in a 16-
bit mode compare to the standard 8-bit mode. P0 carries the low order multiplexed
address and data bus (A7:0, D7:0) while P2 carries the high order multiplexed address
and data bus (A15:8, D15:8). When writing data in IDE mode, the ACC contains D7:0
data (as in 8-bit mode) while DAT16H register (see Table 104) contains D15:8 data.
When reading data in IDE mode, D7:0 data is returned in ACC while D15:8 data is
returned in DAT16H.
Figure 72 shows the IDE read bus cycle while Figure 73 shows the IDE write bus cycle.
For simplicity, these figures depict the bus cycle waveforms in idealized form and do not
provide precise timing information. For IDE bus cycle timing parameters refer to the
Section “AC Characteristics”.
IDE cycle takes 6 CPU clock periods which is equivalent to 12 oscillator clock periods in
standard mode or 6 oscillator clock periods in X2 mode. For further information on X2
mode, refer to the Section “X2 Feature”, page 12.
Slow IDE devices can be accessed by stretching the read and write cycles. This is done
using the M0 bit in AUXR. Setting this bit changes the width of the RD and WR signals
from 3 to 15 CPU clock periods.
Figure 72. IDE Read Waveforms
CPU Clock
ALE
RD(1)
DPL or Ri
D7:0
P0
P2
P2
DPH or P2(2),(3)
D15:8
P2
Notes: 1. RD signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),
P2 outputs SFR content instead of DPH.
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Figure 73. IDE Write Waveforms
CPU Clock
ALE
WR(1)
DPL or Ri
D7:0
P0
P2
P2
DPH or P2(2),(3)
D15:8
P2
Notes: 1. WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),
P2 outputs SFR content instead of DPH.
IDE Device Connection
Figure 74 and Figure 75 show two examples on how to interface up to two IDE devices
to the AT8xC5132. In both examples P0 carries IDE low order data Bits D7:0, P2 carries
IDE high order data Bits D15:8, while RD# and WR# signals are respectively connected
to the IDE nIOR and nIOW signals. Other IDE control signals are generated by the
address latch outputs in the first example – they are generated by port I/Os in the sec-
ond example.
Figure 74. IDE Device Connection Example 1
AT8xC5132
IDE Device 0
IDE Device 1
P2
D15-8
D7:0
D15-8
D7:0
A2:0
A2:0
P0
Latch
nCS1:0
nRESET
nIOR
nCS1:0
nRESET
nIOR
ALE
RD
WR
nIOW
nIOW
Figure 75. IDE Device Connection Example 2
AT8xC5132
IDE Device 0
IDE Device 1
P2/A15:8
P0/AD7:0
D15-8
D7:0
D15-8
D7:0
P4.2:0
P4.4:3
P4.5
RD
A2:0
A2:0
nCS1:0
nRESET
nIOR
nCS1:0
nRESET
nIOR
WR
nIOW
nIOW
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Table 103. External Data Memory Interface Signals
Signal
Name
Alternate
Function
Type Description
Address Lines
A15:8
I/O Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
P0.7:0
-
Address/Data Lines
Multiplexed lower address and data lines for the IDE interface.
AD7:0
ALE
I/O
Address Latch Enable
O
ALE signals indicates that valid address information is available on lines
AD7:0.
Read
RD
O
O
P3.7
P3.6
Read signal output to external data memory.
Write
WR
Write signal output to external memory.
Registers
Table 104. DAT16H Register
DAT16H (S:F9h) – Data 16 High Order Byte
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
Bit
Bit
Number
Mnemonic Description
Data 16 High Order Byte
When EXT16 bit is set, DAT16H is set by software with the high order data byte
prior any MOVX write instruction.
7 - 0
D15:8
When EXT16 bit is set, DAT16H contains the high order data byte after any
MOVX read instruction.
Reset Value = 0000 0000b
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AT8xC5132
Serial I/O Port
The serial I/O port in the AT8xC5132 provides both synchronous and asynchronous
communication modes. It operates as a Synchronous Receiver and Transmitter in one
single mode (Mode 0) and operates as an Universal Asynchronous Receiver and Trans-
mitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous modes
support framing error detection and multiprocessor communication with automatic
address recognition.
Mode Selection
SM0 and SM1 Bits in SCON register (see Figure 107) are used to select a mode among
the single synchronous and the three asynchronous modes according to Table 105.
Table 105. Serial I/O Port Mode Selection
SM0
SM1
Mode
Description
Baud Rate
Fixed/Variable
Variable
0
0
1
1
0
1
0
1
0
1
2
3
Synchronous Shift Register
8-bit UART
9-bit UART
Fixed
9-bit UART
Variable
Baud Rate Generator
Depending on the mode and the source selection, the baud rate can be generated from
either the Timer 1 or the Internal Baud Rate Generator. The Timer 1 can be used in
Modes 1 and 3 while the Internal Baud Rate Generator can be used in Modes 0, 1
and 3.
The addition of the Internal Baud Rate Generator allows freeing of the Timer 1 for other
purposes in the application. It is highly recommended to use the Internal Baud Rate
Generator as it allows higher and more accurate baud rates than Timer 1.
Baud rate formulas depend on the modes selected and are given in the following mode
sections.
Timer 1
When using Timer 1, the Baud Rate is derived from the overflow of the timer. As shown
in Figure 76 Timer 1 is used in its 8-bit auto-reload mode (detailed in Section "Mode 2
(8-bit Timer with Auto-Reload)", page 52). SMOD1 bit in PCON register allows doubling
of the generated baud rate.
Figure 76. Timer 1 Baud Rate Generator Block Diagram
PER
CLOCK
÷ 6
0
1
Overflow
TL1
(8 Bits)
÷ 2
0
1
To Serial Port
T1
C/T1#
TMOD.6
SMOD1
PCON.7
T1
CLOCK
INT1#
TH1
(8 Bits)
GATE1
TMOD.7
TR1
TCON.6
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Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the over-
flow of the timer. As shown in Figure 77, the Internal Baud Rate Generator is an 8-bit
auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6
depending on the SPD bit in BDRCON register (see Table 111). The Internal Baud Rate
Generator is enabled by setting BBR bit in BDRCON register. SMOD1 bit in PCON reg-
ister allows doubling of the generated baud rate.
Figure 77. Internal Baud Rate Generator Block Diagram
PER
CLOCK
÷ 6
0
1
Overflow
BRG
(8 Bits)
÷ 2
0
1
To Serial Port
SPD
BDRCON.1
BRR
BDRCON.4
SMOD1
PCON.7
IBRG
CLOCK
BRL
(8 Bits)
Synchronous Mode
(Mode 0)
Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0
capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of
eight clock pulses while the receive data (RXD) pin transmits or receives a byte of data.
The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur
at a fixed Baud Rate (see Section "Baud Rate Selection (Mode 0)", page 109).
Figure 78 shows the serial port block diagram in Mode 0.
Figure 78. Serial I/O Port Block Diagram (Mode 0)
SCON.6
SCON.7
SM1
SM0
SBUF Tx SR
SBUF Rx SR
RXD
Mode Decoder
M3 M2 M1 M0
Mode
Controller
PER
CLOCK
Baud Rate
Controller
TI
SCON.1
RI
SCON.0
TXD
BRG
CLOCK
Transmission (Mode 0)
To start a transmission mode 0, write to SCON register clearing Bits SM0, SM1.
As shown in Figure 79, writing the byte to transmit to SBUF register starts the transmis-
sion. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle
composed of a high level then low level signal on TXD. During the eighth clock cycle the
MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to
indicate the end of the transmission.
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Figure 79. Transmission Waveforms (Mode 0)
TXD
Write to SBUF
RXD
TI
D0
D1
D2
D3
D4
D5
D6
D7
Reception (Mode 0)
To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI Bits
and setting the REN bit.
As shown in Figure 80, Clock is pulsed and the LSB (D0) is sampled on the RXD pin.
The D0 bit is then shifted into the shift register. After eight sampling, the MSB (D7) is
shifted into the shift register, and hardware asserts RI bit to indicate a completed recep-
tion. Software can then read the received byte from SBUF register.
Figure 80. Reception Waveforms (Mode 0)
TXD
Set REN, Clear RI
Write to SCON
RXD
RI
D0
D1
D2
D3
D4
D5
D6
D7
Baud Rate Selection (Mode 0) In mode 0, the baud rate can be either fixed or variable.
As shown in Figure 81, the selection is done using M0SRC bit in BDRCON register.
Figure 82 gives the baud rate calculation formulas for each baud rate source.
Figure 81. Baud Rate Source Selection (mode 0)
PER
CLOCK
÷ 6
0
To Serial Port
1
IBRG
CLOCK
M0SRC
BDRCON.0
Figure 82. Baud Rate Formulas (Mode 0)
2SMOD1 ⋅ FPER
Baud_Rate =
6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
FPER
2SMOD1 ⋅ FPER
Baud_Rate =
6
BRL = 256 -
6(1-SPD) ⋅ 32 ⋅ Baud_Rate
a. Fixed Formula
b. Variable Formula
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Asynchronous Modes
(Modes 1, 2 and 3)
The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 83
shows the Serial Port block diagram in asynchronous modes.
Figure 83. Serial I/O Port Block Diagram (Modes 1, 2 and 3)
SCON.6
SCON.7
SCON.3
SM1
SM0
TB8
SBUF Tx SR
Rx SR
TXD
RXD
Mode Decoder
M3 M2 M1 M0
T1
CLOCK
IBRG
CLOCK
Mode & Clock
Controller
SBUF Rx
RB8
SCON.2
PER
CLOCK
SM2
SCON.4
TI
SCON.1
RI
SCON.0
Mode 1
Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 84) consists of
10 Bits: one start, eight data Bits and one stop bit. Serial data is transmitted on the TXD
pin and received on the RXD pin. When data is received, the stop bit is read in the RB8
bit in SCON register.
Figure 84. Data Frame Format (Mode 1)
Mode 1
D0
D1
D2
D3
D4
D5
D6
D7
Start bit
8-bit data
Stop bit
Modes 2 and 3
Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 85)
consists of 11 Bits: one start bit, eight data Bits (transmitted and received LSB first), one
programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin
and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON
register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alterna-
tively, the ninth bit can be used as a command/data flag.
Figure 85. Data Frame Format (Modes 2 and 3)
Modes 2 and 3
D0
D1
D2
D3
D4
D5
D6
D7
D8
Start bit
9-bit data
Stop bit
Transmission (Modes 1, 2
and 3)
To initiate a transmission, write to SCON register, setting SM0 and SM1 Bits according
to Table 105, and setting the ninth bit by writing to TB8 bit. Then, writing the byte to be
transmitted to SBUF register starts the transmission.
Reception (Modes 1, 2 and 3)
To prepare for reception, write to SCON register, setting SM0 and SM1 Bits according to
Table 105, and set the REN bit. The actual reception is then initiated by a detected high-
to-low transition on the RXD pin.
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Framing Error Detection
(Modes 1, 2 and 3)
Framing error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register as shown in
Figure 86.
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two devices. If a valid stop bit is not found, the software sets FE bit in
SCON register.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a chip reset clears FE bit. Subsequently received frames with valid stop
Bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on
stop bit instead of the last data bit as detailed in Figure 92.
Figure 86. Framing Error Block Diagram
Framing Error
Controller
FE
1
0
SM0/FE
SCON.7
SM0
SMOD0
PCON.6
Baud Rate Selection (Modes 1 In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud
and 3)
Rate Generator and allows different baud rate in reception and transmission.
As shown in Figure 87, the selection is done using RBCK and TBCK Bits in BDRCON
register.
Figure 88 gives the baud rate calculation formulas for each baud rate source. Table 106
details Internal Baud Rate Generator configuration for different peripheral clock frequen-
cies and gives baud rates closer to the standard baud rates.
Figure 87. Baud Rate Source Selection (Modes 1 and 3)
T1
T1
CLOCK
CLOCK
0
0
1
To Serial
Reception Port
To Serial
Transmission Port
÷ 16
÷ 16
1
IBRG
IBRG
CLOCK
CLOCK
RBCK
BDRCON.2
TBCK
BDRCON.3
Figure 88. Baud Rate Formulas (Modes 1 and 3)
2SMOD1 ⋅ FPER
2SMOD1 ⋅ FPER
6 Þ 32 Þ (256 -TH1)
Baud_Rate=
Baud_Rate=
TH1= 256 -
6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
2SMOD1 ⋅ FPER
6(1-SPD) ⋅ 32 ⋅ Baud_Rate
2SMOD1 ⋅ FPER
192 ⋅ Baud_Rate
BRL= 256 -
A. IBRG Formula
B. T1 Formula
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Table 106. Baud Rate Generator Configuration
FPER = 6 MHz(1)
FPER = 8 MHz(1)
FPER = 10 MHz(1)
Baud Rate
115200
57600
38400
19200
9600
SPD
SMOD1
BRL
-
Error%
-
SPD
SMOD1
BRL
-
Error%
-
SPD
SMOD1
BRL
-
Error%
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
247
243
230
204
152
3.55
0.16
0.16
0.16
0.16
1
1
1
1
1
1
1
1
1
1
245
240
223
191
126
1.36
1.73
1.36
0.16
0.16
1
1
1
1
1
1
1
1
246
236
217
178
2.34
2.34
0.16
0.16
4800
F
PER = 12 MHz(2)
FPER = 16 MHz(2)
FPER = 20 MHz(2)
Baud Rate
115200
57600
38400
19200
9600
SPD
SMOD1
BRL
-
Error%
-
SPD
SMOD1
BRL
247
239
230
204
152
48
Error%
3.55
SPD
SMOD1
BRL
245
234
223
191
126
126
Error%
1.36
-
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
243
236
217
178
100
0.16
2.34
0.16
0.16
0.16
2.12
1.36
0.16
1.36
0.16
0.16
0.16
0.16
4800
0.16
0.16
Notes: 1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode, FPER = FOSC
.
Baud Rate Selection (Mode 2) In mode 2, the baud rate can only be programmed to two fixed values: 1/16 or 1/32 of
the peripheral clock frequency.
As shown in Figure 89 the selection is done using SMOD1 bit in PCON register.
Figure 90 gives the baud rate calculation formula depending on the selection.
Figure 89. Baud Rate Generator Selection (mode 2)
PER
CLOCK
÷ 2
0
1
÷ 16
To Serial Port
SMOD1
PCON.7
Figure 90. Baud Rate Formula (Mode 2)
2SMOD1 ⋅ FPER
Baud_Rate =
32
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AT8xC5132
Multiprocessor
Communication (Modes
2 and 3)
Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To
enable this feature, set SM2 bit in SCON register. When the multiprocessor communica-
tion feature is enabled, the Serial Port can differentiate between data frames (ninth bit
clear) and address frames (ninth bit set). This allows the AT8xC5132 to function as a
slave processor in an environment where multiple slave processors share a single serial
line.
When the multiprocessor communication feature is enabled, the receiver ignores frames
with the ninth bit clear. The receiver examines frames with the ninth bit set for an
address match. If the received address matches the slaves address, the receiver hard-
ware sets RB8 and RI Bits in SCON register, generating an interrupt.
The addressed slave’s software then clears SM2 bit in SCON register and prepares to
receive the data Bytes. The other slaves are unaffected by these data Bytes because
they are waiting to respond to their own addresses.
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor commu-
nication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the Serial Port to examine the address of each
incoming command frame. Only when the Serial Port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, the user may enable the automatic address recognition feature in mode 1. In
this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when
the received command frame address matches the device’s address and is terminated
by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e, setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t care Bits (defined by zeros) to form the
device’s given address. The don’t care Bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be
1111 1111b.
For example:
SADDR = 0101 0110b
SADEN = 1111 1100b
Given = 0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR = 1111 0001b
SADEN = 1111 1010b
Given = 1111 0X0Xb
Slave B:SADDR = 1111 0011b
SADEN = 1111 1001b
Given = 1111 0XX1b
Slave C:SADDR = 1111 0010b
SADEN = 1111 1101b
Given = 1111 00X1b
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4173A–8051–08/02
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To commu-
nicate with slave A only, the master must send an address where bit 0 is clear (e.g.
1111 0000B).
For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves A and B, but not slave C, the master must send an address with Bits 0 and 1 both
set (e.g. 1111 0011B).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e.g. 1111 0001B).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t care Bits, e.g.:
SADDR = 0101 0110b
SADEN = 1111 1100b
(SADDR | SADEN)=1111 111Xb
The use of don’t care Bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh.
The following is an example of using broadcast addresses:
Slave A:SADDR = 1111 0001b
SADEN = 1111 1010b
Given = 1111 1X11b,
Slave B:SADDR = 1111 0011b
SADEN = 1111 1001b
Given = 1111 1X11b,
Slave C:SADDR = 1111 0010b
SADEN = 1111 1101b
Given = 1111 1111b,
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send the address FFh.
To communicate with slaves A and B, but not slave C, the master must send the
address FBh.
Reset Address
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and
broadcast addresses are XXXX XXXXb(all don’t care Bits). This ensures that the Serial
Port is backwards compatible with the 80C51 microcontrollers that do not support auto-
matic address recognition.
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AT8xC5132
Interrupt
The Serial I/O Port handles two interrupt sources that are the “end of reception” (RI in
SCON) and “end of transmission” (TI in SCON) flags. As shown in Figure 91 these flags
are combined together to appear as a single interrupt source for the C51 core. Flags
must be cleared by software when executing the serial interrupt service routine.
The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts
are globally enabled by setting EA bit in IEN0 register.
Depending on the selected mode and wether the framing error detection is enabled or
not, RI flag is set during the stop bit or during the ninth bit as detailed in Figure 92.
Figure 91. Serial I/O Interrupt System
SCON.0
RI
Serial I/O
Interrupt Request
TI
ES
SCON.1
IEN0.4
Figure 92. Interrupt Waveforms
a. Mode 1
RXD
D0
D1
D2
D3
D4
D5
D6
D7
Start bit
8-bit data
Stop bit
RI
SMOD0 = X
FE
SMOD0 = 1
b. Mode 2 and 3
RXD
D0
D1
D2
D3
D4
D5
D6
D7
D8
Start bit
9-bit data
Stop bit
RI
SMOD0 = 0
RI
SMOD0 = 1
FE
SMOD0 = 1
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Registers
Table 107. SCON Register
SCON (S:98h) – Serial Control Register
7
6
5
4
3
2
1
0
FE/SM0
OVR/SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Bit
Number
Mnemonic Description
Framing Error Bit
To select this function, set SMOD0 bit in PCON register.
Set by hardware to indicate an invalid stop bit.
Must be cleared by software.
FE
7
Serial Port Mode Bit 0
Refer to Table 105 for mode selection.
SM0
SM1
Serial Port Mode Bit 1
Refer to Table 105 for mode selection.
6
5
Serial Port Mode Bit 2
Set to enable the multiprocessor communication and automatic address
recognition features.
SM2
Clear to disable the multiprocessor communication and automatic address
recognition features.
Receiver Enable Bit
4
3
REN
TB8
Set to enable reception.
Clear to disable reception.
Transmit Bit 8
Modes 0 and 1: Not used.
Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.
Receiver Bit 8
Mode 0: Not used.
Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit
received.
2
RB8
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit
received.
Transmit Interrupt Flag
1
0
TI
Set by the transmitter after the last data bit is transmitted.
Must be cleared by software.
Receive Interrupt Flag
Set by the receiver after the stop bit of a frame has been received.
Must be cleared by software.
RI
Reset Value = 0000 0000b
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AT8xC5132
Table 108. SBUF Register
SBUF (S:99h) – Serial Buffer Register
7
6
5
4
3
2
1
0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Bit
Bit
Number
Mnemonic Description
Serial Data Byte
7 - 0
SD7:0
Read the last data received by the Serial I/O Port.
Write the data to be transmitted by the Serial I/O Port.
Reset value = XXXX XXXXb
Table 109. SADDR Register
SADDR (S:A9h) – Slave Individual Address Register
7
6
5
4
3
2
1
0
SAD7
SAD6
SAD5
SAD4
SAD3
SAD2
SAD1
SAD0
Bit
Bit
Number
Mnemonic Description
7 - 0
SAD7:0 Slave Individual Address.
Reset Value = 0000 0000b
Table 110. SADEN Register
SADEN (S:B9h) – Slave Individual Address Mask Byte Register
7
6
5
4
3
2
1
0
SAE7
SAE6
SAE5
SAE4
SAE3
SAE2
SAE1
SAE0
Bit
Bit
Number
Mnemonic Description
7 - 0
SAE7:0 Slave Address Mask Byte.
Reset Value = 0000 0000b
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Table 111. BDRCON Register
BDRCON (S:92h) – Baud Rate Generator Control Register
7
-
6
-
5
-
4
3
2
1
0
BRR
TBCK
RBCK
SPD
M0SRC
Bit
Bit
Number
Mnemonic Description
Reserved
7-5
4
-
The values read from these Bits are indeterminate. Do not set these Bits.
Baud Rate Run Bit
Set to enable the baud rate generator.
Clear to disable the baud rate generator.
BRR
TBCK
RBCK
SPD
Transmission Baud Rate Selection Bit
Set to select the baud rate generator as transmission baud rate generator.
Clear to select the Timer 1 as transmission baud rate generator.
3
2
1
0
Reception Baud Rate Selection Bit
Set to select the baud rate generator as reception baud rate generator.
Clear to select the Timer 1 as reception baud rate generator.
Baud Rate Speed Bit
Set to select high speed baud rate generation.
Clear to select low speed baud rate generation.
Mode 0 Baud Rate Source Bit
M0SRC Set to select the variable baud rate generator in Mode 0.
Clear to select fixed baud rate in Mode 0.
Reset Value = XXX0 0000b
Table 112. BRL Register
BRL (S:91h) – Baud Rate Generator Reload Register
7
6
5
4
3
2
1
0
BRL7
BRL6
BRL5
BRL4
BRL3
BRL2
BRL1
BRL0
Bit
Bit
Number
Mnemonic Description
7 - 0
BRL7:0 Baud Rate Reload Value.
Reset Value = 0000 0000b
118
AT8xC5132
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AT8xC5132
Synchronous
Peripheral Interface
The AT8xC5132 implement a Synchronous Peripheral Interface with master and slave
modes capability.
Figure 93 shows an SPI bus configuration using the AT8xC5132 as master connected
to slave peripherals. Figure 94 shows an SPI bus configuration using the AT8xC5132 as
slave of an other master.
The bus is made of three wires connecting all the devices together:
•
•
•
Master Output Slave Input (MOSI): it is used to transfer data in series from the
master to a slave. It is driven by the master.
Master Input Slave Output (MISO): it is used to transfer data in series from a slave
to the master. It is driven by the selected slave.
Serial Clock (SCK): it is used to synchronize the data transmission both in and out
of the devices through their MOSI and MISO lines. It is driven by the master for eight
clock cycles which allows to exchange one byte on the serial lines.
Each slave peripheral is selected by one Slave Select pin (SS). If there is only one
slave, it may be continuously selected with SS tied to a low level. Otherwise, the
AT8xC5132 may select each device by software through port pins (Pn.x). Special care
should be taken not to select two slaves at the same time to avoid bus conflicts.
Figure 93. Typical Master SPI Bus Configuration
Pn.z
Pn.y
LCD
Controller
Pn.x
SS#
SO
SS#
SO
SS#
SO
DataFlash 1
DataFlash 2
AT8xC5132
SI
SCK
SI
SCK
SI
SCK
MISO
MOSI
SCK
P4.0
P4.1
P4.2
Figure 94. Typical Slave SPI Bus Configuration
SSn
SS1
SS
AT8xC5132
Slave n
SS0
SS
SS
SO
Slave 1
Slave 2
SO
SI
SCK
SI
SCK
MISO MOSI SCK
MASTER
MISO
MOSI
SCK
119
4173A–8051–08/02
Description
The SPI controller interfaces with the C51 core through three special function registers:
SPCON, the SPI control register (see Table 114); SPSTA, the SPI status register (see
Table 115); and SPDAT, the SPI data register (see Table 116).
Master Mode
The SPI operates in master mode when the MSTR bit in SPCON is set.
Figure 95 shows the SPI block diagram in master mode. Only a master SPI module can
initiate transmissions. Software begins the transmission by writing to SPDAT. Writing to
SPDAT writes to the shift register while reading SPDAT reads an intermediate register
updated at the end of each transfer.
The byte begins shifting out on the MOSI pin under the control of the bit rate generator.
This generator also controls the shift register of the slave peripheral through the SCK
output pin. As the byte shifts out, another byte shifts in from the slave peripheral on the
MISO pin. The byte is transmitted most significant bit (MSB) first. The end of transfer is
signalled by SPIF being set.
In case of the AT8xC5132 is the only master on the bus, it can be useful not to use SS
pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.
Figure 95. SPI Master Mode Block Diagram
MOSI/P4.1
I
Q
MISO/P4.0
SCK/P4.2
SS/P4.3
8-bit Shift Register
SPDAT WR
SPDAT RD
MODF
SSDIS
SPCON.5
SPSTA.4
Control and Clock Logic
WCOL
SPSTA.6
PER
CLOCK
Bit Rate Generator
SPIF
SPSTA.7
SPEN
SPCON.6
SPR2:0
SPCON
CPHA
SPCON.2
CPOL
SPCON.3
Note:
MSTR bit in SPCON is set to select master mode.
Slave Mode
The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has
been loaded in SPDAT.
Figure 96 shows the SPI block diagram in slave mode. In slave mode, before data trans-
mission occurs, the SS pin of the slave SPI must be asserted to low level. SS must
remain low until the transmission of the byte is complete. In the slave SPI module, data
enters the shift register through the MOSI pin under the control of the serial clock pro-
vided by the master SPI module on the SCK input pin. When the master starts a
transmission, the data in the shift register begins shifting out on the MISO pin. The end
of transfer is signaled by SPIF being set.
In case of the AT8xC5132 is the only slave on the bus, it can be useful not to use SS pin
and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This
bit has no effect when CPHA is cleared (see Section "SS Management", page 122).
120
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4173A–8051–08/02
AT8xC5132
Figure 96. SPI Slave Mode Block Diagram
MISO/P4.2
I
Q
MOSI/P4.1
8-bit Shift Register
SPDAT WR
SPDAT RD
SCK/P4.2
SS/P4.3
Control and Clock Logic
SPIF
SPSTA.7
SSDIS
SPCON.5
CPHA
SPCON.2
CPOL
SPCON.3
Note:
MSTR bit in SPCON is cleared to select slave mode.
Bit Rate
The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and
SPR0 control Bits in SPCON according to Table 113. These bit rates are derived from
the peripheral clock (FPER) issued from the Clock Controller block as detailed in
Section “Clock Controller”, page 12.
Table 113. Serial Bit Rates
Bit Rate (kHz) Vs FPER
SPR2 SPR1 SPR0 6 MHz(1) 8 MHz(1)
16 MHz(2)
8000
4000
2000
1000
500
FPER Divider
10 MHz(1) 12 MHz(2)
20 MHz(2)
10000
5000
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3000
1500
750
4000
2000
1000
500
5000
2500
6000
3000
1500
750
2
4
1250
2500
8
375
625
1250
16
32
64
128
1
187.5
93.75
46.875
6000
250
312.5
156.25
78.125
10000
375
625
125
187.5
93.75
12000
250
312.5
156.25
20000
62.5
8000
125
16000
Notes: 1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode, FPER = FOSC
.
Data Transfer
The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle
state(1) while the Clock Phase bit (CPHA in SPCON) defines the edges on which the
input data are sampled and the edges on which the output data are shifted (see
Figure 97 and Figure 98). The SI signal is output from the selected slave and the SO
signal is the output from the master. The AT8xC5132 captures data from the SI line
while the selected slave captures data from the SO line.
For simplicity, the following figures depict the SPI waveforms in idealized form and do
not provide precise timing information. For timing parameters refer to the Section “AC
Characteristics”.
Note:
1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
121
4173A–8051–08/02
Figure 97. Data Transmission Format (CPHA = 0)
1
2
3
4
5
6
7
8
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MSB
bit 6
bit 6
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
LSB
LSB
MOSI (from Master)
MISO (from Slave)
MSB
SS (to Slave)
to Capture Point
Figure 98. Data Transmission Format (CPHA = 1)
1
2
3
4
5
6
7
8
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MSB
MSB
bit 6
bit 6
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
LSB
MOSI (from Master)
MISO (from Slave)
LSB
SS (to Slave)
Capture Point
SS Management
Figure 97 shows an SPI transmission with CPHA = 0, where the first SCK edge is the
MSB capture point. Therefore the slave starts to output its MSB as soon as it is
selected: SS asserted to low level. SS must then be deasserted between each byte
transmission (see Figure 99). SPDAT must be loaded with data before SS is asserted
again.
Figure 98 shows an SPI transmission with CPHA = 1, where the first SCK edge is used
by the slave as a start of transmission signal. Therefore SS may remain asserted
between each byte transmission (see Figure 99).
122
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AT8xC5132
Figure 99. SS# Timing Diagram
Byte 1
Byte 2
Byte 3
SI/SO
SS (CPHA = 0)
SS (CPHA = 1)
Error Conditions
The following flags signal the SPI error conditions:
• MODF in SPSTA signals a mode fault.
MODF flag is relevant only in master mode when SS usage is enabled (SSDIS bit
cleared). It signals when set that another master on the bus has asserted SS pin
and so, may create a conflict on the bus with two masters sending data at the same
time.
A mode fault automatically disables the SPI (SPEN cleared) and configures the SPI
in slave mode (MSTR cleared).
MODF flag can trigger an interrupt as explained in Section "Interrupt", page 123.
MODF flag is cleared by reading SPSTA and re-configuring SPI by writing to
SPCON.
•
WCOL in SPSTA signals a write collision.
WCOL flag is set when SPDAT is loaded while a transfer is on-going. In this case,
data is not written to SPDAT and transfer continues uninterrupted. WCOL flag does
not trigger any interrupt and is relevant jointly with SPIF flag.
WCOL flag is cleared after reading SPSTA and writing new data to SPDAT while no
transfer is ongoing.
Interrupt
The SPI handles two interrupt sources; the “end of transfer” and the “mode fault” flags.
As shown in Figure 100 these flags are combined together to appear as a single inter-
rupt source for the C51 core. The SPIF flag is set at the end of an 8-bit shift in and out
and is cleared by reading SPSTA and then reading from or writing to SPDAT.
The MODF flag is set in case of mode fault error and is cleared by reading SPSTA and
then writing to SPCON.
The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes inter-
rupts are globally enabled by setting EA bit in IEN0 register.
Figure 100. SPI Interrupt System
SPIF
SPI Controller
Interrupt Request
SPSTA.7
MODF
SPSTA.4
ESPI
IEN1.2
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Configuration
The SPI configuration is made through SPCON.
Master Configuration
Slave Configuration
The SPI operates in master mode when the MSTR bit in SPCON is set.
The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has
been loaded in SPDAT.
Data Exchange
There are two possible Policies to exchange data in master and slave modes:
•
•
polling
interrupts
Master Mode with Polling
Policy
Figure 101 shows the initialization phase and the transfer phase flows using the polling
policy. Using this flow prevents any overrun error occurrence.
•
•
•
•
The bit rate is selected according to Table 113.
The transfer format depends on the slave peripheral.
SS may be deasserted between transfers depending also on the slave peripheral.
SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the
“end of transfer” check).
This policy provides the fastest effective transmission and is well adapted when commu-
nicating at high speed with other Microcontrollers. However, the procedure may then be
interrupted at any time by higher priority tasks.
Figure 101. Master SPI Polling Policy Flows
SPI Initialization
Polling Policy
SPI Transfer
Polling Policy
Disable Interrupt
Select Slave
SPIE = 0
Pn.x = L
Select Master Mode
Start Transfer
MSTR = 1
Write Data in SPDAT
Select Bit Rate
program SPR2:0
End Of Transfer?
SPIF = 1?
Select Format
program CPOL & CPHA
Get Data Received
Read SPDAT
Enable SPI
SPEN = 1
Last Transfer?
Deselect Slave
Pn.x = H
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AT8xC5132
Master Mode with Interrupt
Policy
Figure 102 shows the initialization phase and the transfer phase flows using the inter-
rupt policy. Using this flow prevents any overrun error occurrence.
•
•
•
The bit rate is selected according to Table 113.
The transfer format depends on the slave peripheral.
SS may be deasserted between transfers depending also on the slave peripheral.
Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.
Clear is effective when reading SPDAT.
Figure 102. Master SPI Interrupt Policy Flows
SPI Initialization
Interrupt Policy
SPI Interrupt
Service Routine
Select Master Mode
Read Status
MSTR = 1
Read SPSTA
Select Bit Rate
Get Data Received
Program SPR2:0
Read SPDAT
Select Format
Start New Transfer
Program CPOL & CPHA
Write Data in SPDAT
Enable Interrupt
ESPI =1
Last Transfer?
Enable SPI
SPEN = 1
Deselect Slave
Pn.x = H
Select Slave
Pn.x = L
Disable Interrupt
SPIE = 0
Start Transfer
Write Data in SPDAT
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Slave Mode with Polling
Policy
Figure 103 shows the initialization phase and the transfer phase flows using the polling
policy.
The transfer format depends on the master controller.
SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of
reception” check).
This policy provides the fastest effective transmission and is well adapted when commu-
nicating at high speed with other Microcontrollers. However, the procedure may be
interrupted at any time by higher priority tasks.
Figure 103. Slave SPI Polling Policy Flows
SPI Initialization
Polling Policy
SPI Transfer
Polling Policy
Disable interrupt
Data Received?
SPIE = 0
SPIF = 1?
Select Slave Mode
MSTR = 0
Get Data Received
Read SPDAT
Select Format
Program CPOL & CPHA
Prepare Next Transfer
Write Data in SPDAT
Enable SPI
SPEN = 1
Prepare Transfer
write data in SPDAT
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AT8xC5132
Slave Mode with Interrupt
Policy
Figure 102 shows the initialization phase and the transfer phase flows using the inter-
rupt policy.
The transfer format depends on the master controller.
Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.
Clear is effective when reading SPDAT.
Figure 104. Slave SPI Interrupt Policy Flows
SPI Initialization
Interrupt Policy
SPI Interrupt
Service Routine
Select Slave Mode
Get Status
MSTR = 0
Read SPSTA
Select Format
Get Data Received
Program CPOL & CPHA
Read SPDAT
Enable Interrupt
Prepare New Transfer
ESPI =1
Write Data in SPDAT
Enable SPI
SPEN = 1
Prepare Transfer
Write Data in SPDAT
Registers
Table 114. SPCON Register
SPCON (S:C3h) – SPI Control Register
7
6
5
4
3
2
1
0
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit
Bit
Number
Mnemonic Description
SPI Rate Bit 2
Refer to Table 113 for bit rate description.
7
6
SPR2
SPI Enable Bit
Set to enable the SPI interface.
Clear to disable the SPI interface.
SPEN
SSDIS
MSTR
Slave Select Input Disable Bit
Set to disable SS in both master and slave modes. In slave mode this bit has no
effect if CPHA = 0.
5
4
Clear to enable SS in both master and slave modes.
Master Mode Select
Set to select the master mode.
Clear to select the slave mode.
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Bit
Bit
Number
Mnemonic Description
SPI Clock Polarity Bit(1)
3
CPOL
Set to have the clock output set to high level in idle state.
Clear to have the clock output set to low level in idle state.
SPI Clock Phase Bit
2
CPHA
Set to have the data sampled when the clock returns to idle state (see CPOL).
Clear to have the data sampled when the clock leaves the idle state (see CPOL).
SPI Rate Bits 0 and 1
Refer to Table 113 for bit rate description.
1 - 0
SPR1:0
Reset Value = 0001 0100b
Note:
1. When the SPI is disabled, SCK outputs high level.
Table 115. SPSTA Register
SPSTA (S:C4h) – SPI Status Register
7
6
5
-
4
3
-
2
-
1
-
0
-
SPIF
WCOL
MODF
Bit
Bit
Number
Mnemonic Description
SPI Interrupt Flag
Set by hardware when an 8-bit shift is completed.
7
SPIF
Cleared by hardware when reading or writing SPDAT after reading SPSTA.
Write Collision Flag
6
5
WCOL
Set by hardware to indicate that a collision has been detected.
Cleared by hardware to indicate that no collision has been detected.
Reserved
-
The values read from this bit is indeterminate. Do not set this bit.
Mode Fault
4
MODF
-
Set by hardware to indicate that the SS pin is at an appropriate level.
Cleared by hardware to indicate that the SS pin is at an inappropriate level.
Reserved
3:0
The values read from these Bits are indeterminate. Do not set these Bits.
Reset Value = 00000 0000b
Table 116. SPDAT Register
SPDAT (S:C5h) – Synchronous Serial Data Register
7
6
5
4
3
2
1
0
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Bit
Bit
Number
Mnemonic Description
7 - 0
SPD7:0 Synchronous Serial Data
Reset Value = XXXX XXXXb
128
AT8xC5132
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AT8xC5132
Analog-to-Digital
Converter
The AT8xC5132 implement a 2-channel 10-bit (8 true Bits) analog-to-digital converter
(ADC). The first channel of this ADC can be used for battery monitoring while the sec-
ond channel can be used for voice sampling at 8 kHz.
Description
The A/D converter interfaces with the C51 core through four special function registers:
ADCON, the ADC control register (see Table 118); ADDH and ADDL, the ADC data reg-
isters (see Table 120 and Table 121); and ADCLK, the ADC clock register (see
Table 119).
As shown in Figure 105, the ADC is composed of a 10-bit cascaded potentiometric digi-
tal to analog converter, connected to the negative input of a comparator. The output
voltage of this DAC is compared to the analog voltage stored in the Sample and Hold
and coming from AIN0 or AIN1 input depending on the channel selected (see
Table 117).
Figure 105. ADC Structure
ADCON.5
ADCON.3
ADEN
ADSST
ADCON.4
ADC
Interrupt
Request
ADEOC
ADC
CLOCK
CONTROL
EADC
IEN1.3
8
2
0
1
AIN1
AIN0
ADDH
ADDL
+
-
SAR
AVSS
ADCS
ADCON.0
Sample and Hold
10
R/2R DAC
AREFP AREFN
Figure 106 shows the timing diagram of a complete conversion. For simplicity, the figure
depicts the waveforms in idealized form and does not provide precise timing informa-
tion. For ADC characteristics and timing parameters refer to the Section “AC
Characteristics”.
Figure 106. Timing Diagram
CLK
TADCLK
ADEN
TSETUP
ADSST
ADEOC
TCONV
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4173A–8051–08/02
Clock Generation
The ADC clock is generated by division of the peripheral clock (see details in
Section “X2 Feature”, page 12). The division factor is then given by ADCP4:0 Bits in
ADCLK register. Figure 107 shows the ADC clock generator and its calculation
formula(1).
Figure 107. ADC Clock Generator and Symbol Caution:
ADCLK
PER
CLOCK
ADC
CLOCK
÷ 2
ADCD4:0
ADC Clock
ADC Clock Symbol
PERclk
ADCclk = -------------------------
2 ⋅ ADCD
Note:
In all cases, the ADC clock frequency may be higher than the maximum FADCLK parame-
ter reported in the Section “AC Characteristics”.
Channel Selection
The channel on which conversion is performed is selected by the ADCS bit in ADCON
register according to Table 117.
Table 117. ADC Channel Selection
ADCS
Channel
AIN1
0
1
AIN0
Conversion Precision
The 10-bit precision conversion is achieved by stopping the CPU core activity during
conversion for limiting the digital noise induced by the core. This mode called the
Pseudo-Idle mode(1), (2) is enabled by setting the ADIDL bit in ADCON register. Thus,
when conversion is launched (see Section "Conversion Launching", page 131), the
CPU core is stopped until the end of the conversion (see Section "End of Conversion",
page 131). This bit is cleared by hardware at the end of the conversion.
Notes: 1. Only the CPU activity is frozen, peripherals are not affected by the Pseudo-Idle
mode.
2. If some interrupts occur during the Pseudo-Idle mode, they will be delayed and pro-
cessed according to their priority after the end of the conversion.
Configuration
The ADC configuration consists in programming the ADC clock as detailed in the Sec-
tion "Clock Generation", page 130. The ADC is enabled using the ADEN bit in ADCON
register. As shown in Figure 93, user must wait for the setup time (TSETUP) before
launching any conversion.
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AT8xC5132
Figure 108. ADC Configuration Flow
ADC
Configuration
Program ADC Clock
ADCD4:0 = xxxxxb
Enable ADC
ADIDL = x
ADEN = 1
Wait Setup Time
Conversion Launching
The conversion is launched by setting the ADSST bit in ADCON register, this bit
remains set during the conversion. As soon as the conversion is started, it takes 11
clock periods (TCONV) before the data is available in ADDH and ADDL registers.
Figure 109. ADC Conversion Launching Flow
ADC
Conversion Start
Select Channel
ADCS = 0-1
Start Conversion
ADSST = 1
End of Conversion
The end of conversion is signalled by the ADEOC flag in ADCON register becoming set
or by the ADSST bit in ADCON register becoming cleared.
The ADEOC flag can generate an interrupt if enabled by setting EADC bit in IEN1 regis-
ter. This flag is set by hardware and must be reset by software.
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Registers
Table 118. ADCON Register
ADCON (S:F3h) – ADC Control Register
7
-
6
5
4
3
2
-
1
-
0
ADIDL
ADEN
ADEOC
ADSST
ADCS
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The values read from this bit is always 0. Do not set this bit.
ADC Pseudo-Idle Mode
Set to suspend the CPU core activity (pseudo-idle mode) during conversion.
Clear by hardware at the end of conversion.
ADIDL
ADEN
ADC Enable Bit
Set to enable the A-to-D converter.
Clear to disable the A-to-D converter and put it in low power standby mode.
5
4
End Of Conversion Flag
Set by hardware when ADC result is ready to be read. This flag can generate an
interrupt.
ADEOC
Must be cleared by software.
Start and Status Bit
3
2 - 1
0
ADSST
-
Set to start an A-to-D conversion on the selected channel.
Cleared by hardware at the end of conversion.
Reserved
The values read from these Bits are always 0. Do not set these Bits.
Channel Selection Bit
Set to select channel 0 for conversion.
Clear to select channel 1 for conversion.
ADCS
Reset Value = 0000 0000b
Table 119. ADCLK Register
ADCLK (S:F2h) – ADC Clock Divider Register
7
-
6
-
5
-
4
3
2
1
0
ADCD4
ADCD3
ADCD2
ADCD1
ADCD0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4 - 0
-
The values read from these Bits are always 0. Do not set these Bits.
ADC Clock Divider
5-bit divider for ADC clock generation.
ADCD4:0
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Table 120. ADDH Register
ADDH (S:F5h Read Only) – ADC Data High Byte Register
7
6
5
4
3
2
1
0
ADAT9
ADAT8
ADAT7
ADAT6
ADAT5
ADAT4
ADAT3
ADAT2
Bit
Bit
Number
Mnemonic Description
ADC Data
7 - 0
ADAT9:2
Eight Most Significant Bits of the 10-bit ADC data.
Reset Value = 0000 0000b
Table 121. ADDL Register
ADDL (S:F4h Read Only) – ADC Data Low Byte Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
ADAT1
ADAT0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 2
1 - 0
-
The values read from these Bits are always 0. Do not set these Bits.
ADC Data
ADAT1:0
Two Least Significant Bits of the 10-bit ADC data.
Reset Value = 0000 0000b
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Keyboard Interface
The AT8xC5132 implement a keyboard interface allowing the connection of a 4 x n
matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both
high or low level. These inputs are available as alternate function of P1.3:0 and allow
exit from idle and power down modes.
Description
The keyboard interfaces with the C51 core through two special function registers:
KBCON, the keyboard control register (see Table 122); and KBSTA, the keyboard con-
trol and status register (see Table 123).
The keyboard inputs are considered as 4 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (EKB in IEN1 register) allows global
enable or disable of the keyboard interrupt (see Figure 110). As detailed in Figure 111
each keyboard input has the capability to detect a programmable level according to
KINL3:0 bit value in KBCON register. Level detection is then reported in interrupt flags
KINF3:0 in KBSTA register.
A keyboard interrupt is requested each time one of the four flags is set, i.e. the input
level matches the programmed one. Each of these four flags can be masked by soft-
ware using KINM3:0 Bits in KBCON register and is cleared by reading KBSTA register.
This structure allows keyboard arrangement from 1 by n to 4 by n matrix and allow
usage of KIN inputs for any other purposes.
Figure 110. Keyboard Interface Block Diagram
KIN0
KIN1
KIN2
KIN3
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Keyboard Interface
Interrupt Request
EKB
IEN1.4
Figure 111. Keyboard Input Circuitry
0
1
KIN3:0
KINF3:0
KBSTA.3:0
KINM3:0
KBCON.3:0
KINL3:0
KBCON.7:4
Power Reduction Mode
KIN3:0 inputs allow exit from idle and power down modes as detailed in Section “Power
Management”, page 46. To enable this feature, KPDE bit in KBSTA register must be set
to logic 1.
Due to the asynchronous keypad detection in power down mode (all clocks are
stopped), exit may happen on parasitic key press. In this case, no key is detected and
software must enter power-down again.
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Registers
Table 122. KBCON Register
KBCON (S:A3h) – Keyboard Control Register
7
6
5
4
3
2
1
0
KINL3
KINL2
KINL1
KINL0
KINM3
KINM2
KINM1
KINM0
Bit
Bit
Number
Mnemonic Description
Keyboard Input Level Bit
7 - 4
3 - 0
KINL3:0 Set to enable a high level detection on the respective KIN3:0 input.
Clear to enable a low level detection on the respective KIN3:0 input.
Keyboard Input Mask Bit
KINM3:0 Set to prevent the respective KINF3:0 flag from generating a keyboard interrupt.
Clear to allow the respective KINF3:0 flag to generate a keyboard interrupt.
Reset Value = 0000 1111b
Table 123. KBSTA Register
KBSTA (S:A4h) – Keyboard Control and Status Register
7
6
-
5
-
4
-
3
2
1
0
KPDE
KINF3
KINF2
KINF1
KINF0
Bit
Bit
Number
Mnemonic Description
Keyboard Power Down Enable Bit
7
KPDE
-
Set to enable exit of power down mode by the keyboard interrupt.
Clear to disable exit of power down mode by the keyboard interrupt.
Reserved
6 - 4
3 - 0
The values read from these Bits are always 0. Do not set these Bits.
Keyboard Input Interrupt Flag
KINF3:0 Set by hardware when the respective KIN3:0 input detects a programmed level.
Cleared when reading KBSTA.
Reset Value = 0000 0000b
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Electrical Characteristics
Absolute Maximum Ratings
NOTE:
Stressing the device beyond the “Absolute Maxi-
mum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond
the “operating conditions” is not recommended
and extended exposure beyond the “Operating
Conditions” may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on any other Pin to VSS .....................................-0.3to+4.0V
IOL per I/O Pin ................................................................. 5 mA
Power Dissipation............................................................. 1 W
Ambient Temperature Under Bias.................... -40°C to +85°C
VDD ....................................................................................... 2.7V to 3.3V
DC Characteristics
Digital Logic
Table 124. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C
Symbol Parameter
Min
Typ(1)
Max
Units Test Conditions
0.2·VDD
-
VIL
Input Low Voltage
-0.5
V
0.1
Input High Voltage (except
RST)
0.2·VDD + 0.
VIH1
VIH2
VDD
V
V
9
Input High Voltage (RST)
0.7·VDD
VDD + 0.5
Output Low Voltage
(except P0, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK,
DSEL, DOUT)
VOL1
0.45
V
IOL = 1.6 mA
Output Low Voltage
(P0, ALE, MCMD, MDAT,
MCLK, SCLK, DCLK, DSEL,
DOUT)
VOL2
0.45
V
V
IOL = 3.2 mA
Output High Voltage
(P1, P2, P3, P4 and P5)
VOH1
VDD - 0.7
VDD - 0.7
IOH = -30 µA
Output High Voltage
(P0, P2 address mode, ALE,
VOH2 MCMD, MDAT, MCLK,
SCLK, DCLK, DSEL, DOUT,
D+, D-)
V
IOH = -3.2 mA
Logical 0 Input Current (P1,
P2, P3, P4 and P5)
IIL
-50
µA Vin = 0.45V
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AT8xC5132
Table 124. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C
Symbol Parameter
Min
Typ(1)
Max
Units Test Conditions
Input Leakage Current (P0,
ILI
ALE, MCMD, MDAT, MCLK,
SCLK, DCLK, DSEL, DOUT)
10
µA 0.45 < VIN < VDD
Logical 1 to 0 Transition
Current
(P1, P2, P3, P4 and P5)
ITL
-650
200
µA Vin = 2.0V
RRST Pull-down Resistor
CIO Pin Capacitance
VRET VDD Data Retention Limit
50
90
10
kΩ
pF TA = 25°C
1.8
V
12 MHz, VDD < 3.3V
mA 16 MHz, VDD < 3.3V
20 MHz, VDD < 3.3V
IDD
Operating Current
TBD
TBD
12 MHz, VDD < 3.3V
mA 16 MHz, VDD < 3.3V
20 MHz, VDD < 3.3V
IDL
Idle Mode Current
TBD
TBD
TBD
TBD
IPD
Power-down Current
µA VRET < VDD < 3.3V
Note:
1. Typical values are obtained using VDD = 3V and TA = 25°C. They are not tested and
there is no guarantee on these values.
Figure 112. IDD/IDL Versus XTAL Frequency; VDD = 2.7 to 3.3V
TBD
TBD
TBD
0
2
4
6
8
10
12
14
16
18
20
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
Frequency at XTAL (MHz)
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IDD, IDL and IPD Test Conditions Figure 113. IDD Test Condition, Active Mode
VDD
VDD
IDD
RST
VDD
VDD
P0
(NC)
Clock Signal
X2
X1
TST
VSS
VSS
All other pins are unconnected
Figure 114. IDL Test Condition, Idle Mode
VDD
IDL
RST
VDD
VSS
VDD
P0
(NC)
Clock Signal
X2
X1
TST
VSS
VSS
All other pins are unconnected
Figure 115. IPD Test Condition, Power-Down Mode
VDD
IPD
RST
VDD
VSS
VDD
P0
(NC)
X2
X1
MCMD
MDAT
TST
VSS
VSS
All other pins are unconnected
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4173A–8051–08/02
AT8xC5132
A-to-D Converter
Table 125. A-to-D Converter DC Characteristics VDD = 2.7 to 3.3V , TA = -40°C to
+85°C
Symbol
Parameter
Min
Typ
Max
Units Test Conditions
AVDD
Analog Supply Voltage
2.7
3.3
V
Analog Operating Supply
Current
AVDD = 3.3V
µA
AIDD
600
AIN1:0 = 0 to AVDD
AVDD = 3.3V
µA
AIPD
AVIN
Analog Standby Current
Analog Input Voltage
2
ADEN = 0 or PD = 1
AVSS
AVDD
V
Reference Voltage
AREFN
AREFP
AVREF
AVSS
2.4
V
V
AVDD
30
RREF
CIA
AREF Input Resistance
Analog Input capacitance
10
kΩ
TA = 25°C
TA = 25°C
10
pF
Oscillator and Crystal
Schematic
Figure 116. Crystal Connection
X1
X2
C1
C2
Q
VSS
Note:
For operation with most standard crystals, no external components are needed on X1
and X2. It may be necessary to add external capacitors on X1 and X2 to ground in spe-
cial cases (max 10 pF). X1 and X2 may not be used to drive other circuits.
Parameters
Table 126. Oscillator and Crystal Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C
Symbol
CX1
CX2
CL
Parameter
Min
Typ
10
10
5
Max
Unit
pF
Internal Capacitance (X1 - VSS
Internal Capacitance (X2 - VSS
)
)
pF
Equivalent Load Capacitance (X1 - X2)
Drive Level
pF
DL
50
20
40
6
µW
MHz
Ω
F
Crystal Frequency
RS
Crystal Series Resistance
Crystal Shunt Capacitance
CS
pF
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Phase Lock Loop
Schematic
Figure 117. PLL Filter Connection
PFILT
R
C2
C1
VSS
VSS
Parameters
Table 127. PLL Filter Characteristics
V
DD = 2.7 to 3.3V , TA = -40° to +85°C
Symbol
Parameter
Min
Typ
100
10
Max
Unit
Ω
R
Filter Resistor
C1
C2
Filter Capacitance 1
Filter Capacitance 2
nF
nF
2.2
In-system Programming
Schematic
Figure 118. ISP Pull-down Connection
ISP
RISP
VSS
Table 128. ISP Pull-Down Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C
Parameters
Symbol
Parameter
Min
Typ
Max
Unit
RISP
ISP Pull-Down Resistor
2.2
kΩ
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AT8xC5132
AC Characteristics
External 8-bit Bus Cycles
Definition of Symbols
Table 129. External 8-bit Bus Cycles Timing Symbol Definitions
Signals
Conditions
High
A
D
L
Address
Data In
ALE
H
L
Low
V
X
Z
Valid
Q
R
W
Data Out
RD
No Longer Valid
Floating
WR
Timings
Test conditions: capacitive load on all pins = 50 pF.
Table 130. External 8-bit Bus Cycle – Data Read AC Timings
V
DD = 2.7 to 3.3V, TA = -40° to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol Parameter
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLCL
TLHLL
TAVLL
TLLAX
TLLRL
Clock Period
50
50
ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
TCLCL-15
Address Valid to ALE Low
Address hold after ALE Low
ALE Low to RD Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
TRLRH RD Pulse Width
TRHLH RD high to ALE High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20
TAVDV
TAVRL
TRLDV RD Low to Valid Data
TRLAZ RD Low to Address Float
Address Valid to Valid Data In
9·TCLCL-65
4.5·TCLCL-65
Address Valid to RD Low
4·TCLCL-30
2·TCLCL-30
5·TCLCL-30
2.5·TCLCL-30
0
0
TRHDX Data Hold After RD High
0
0
Instruction Float After RD
TRHDZ
High
2·TCLCL-25
TCLCL-25
ns
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Table 131. External 8-bit Bus Cycle – Data Write AC Timings
DD = 2.7 to 3.3V, TA = -40° to +85°C
V
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol Parameter
Min
50
Max
Min
Max
Unit
ns
TCLCL
TLHLL
TAVLL
Clock Period
50
ALE Pulse Width
Address Valid to ALE Low
2·TCLCL-15
TCLCL-20
TCLCL-15
ns
0.5·TCLCL-20
ns
Address hold after ALE
Low
TLLAX
TLLWL
T
CLCL-20
0.5·TCLCL-20
ns
ALE Low to WR Low
3·TCLCL-30
6·TCLCL-25
TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
ns
ns
ns
ns
ns
TWLWH WR Pulse Width
TWHLH WR High to ALE High
TAVWL Address Valid to WR Low
TQVWH Data Valid to WR High
TWHQX Data Hold after WR High
TCLCL+20
0.5·TCLCL-20
2·TCLCL-30
0.5·TCLCL+20
4·TCLCL-30
7·TCLCL-20
TCLCL-15
3.5·TCLCL-20
0.5·TCLCL-15
Waveforms
Figure 119. External 8-bit Bus Cycle – Data Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRHDX
TRLAZ
TLLAX
TAVLL
P0
P2
A7:0
TAVRL
TAVDV
D7:0
Data In
A15:8
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AT8xC5132
Figure 120. External 8-bit Bus Cycle – Data Write Waveforms
ALE
TLHLL
TWHLH
TLLWL
TWLWH
WR
TAVWL
TLLAX
TAVLL
TQVWH
TWHQX
P0
P2
A7:0
D7:0
Data Out
A15:8
External IDE 16-bit Bus Cycles
Definition of Symbols
Table 132. External IDE 16-bit Bus Cycles Timing Symbol Definitions
Signals
Address
Conditions
A
D
L
H
L
High
Data In
ALE
Low
V
X
Z
Valid
Q
R
W
Data Out
RD
No Longer Valid
Floating
WR
Timings
Test conditions: capacitive load on all pins = 50 pF.
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Table 133. External IDE 16-bit Bus Cycle – Data Read AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol Parameter
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
TCLCL-15
TAVLL Address Valid to ALE Low
TLLAX Address hold after ALE Low
TLLRL ALE Low to RD Low
TRLRH RD Pulse Width
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
TRHLH RD high to ALE High
TAVDV Address Valid to Valid Data In
TAVRL Address Valid to RD Low
TRLDV RD Low to Valid Data
TRLAZ RD Low to Address Float
TRHDX Data Hold After RD High
TCLCL+20
0.5·TCLCL-20
0.5·TCLCL+20
4.5·TCLCL-65
9·TCLCL-65
4·TCLCL-30
2·TCLCL-30
5·TCLCL-30
2.5·TCLCL-30
0
0
0
0
Instruction Float After RD
TRHDZ
High
2·TCLCL-25
TCLCL-25
ns
Table 134. External IDE 16-bit Bus Cycle – Data Write AC Timings
DD = 2.7 to 3.3V, TA = -40° to +85°C
V
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol Parameter
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
4·TCLCL-30
7·TCLCL-20
TCLCL-15
TCLCL-15
TAVLL Address Valid to ALE Low
TLLAX Address hold after ALE Low
TLLWL ALE Low to WR Low
TWLWH WR Pulse Width
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
TWHLH WR High to ALE High
TAVWL Address Valid to WR Low
TQVWH Data Valid to WR High
TWHQX Data Hold after WR High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20
2·TCLCL-30
3.5·TCLCL-20
0.5·TCLCL-15
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Waveforms
Figure 121. External IDE 16-bit Bus Cycle – Data Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRHDX
TRLAZ
TLLAX
TAVLL
P0
P2
A7:0
TAVRL
TAVDV
D7:0
Data In
A15:8
D15:81
Data In
Note:
D15:8 is written in DAT16H SFR.
Figure 122. External IDE 16-bit Bus Cycle – Data Write Waveforms
ALE
TLHLL
TWHLH
TLLWL
TWLWH
WR
TAVWL
TLLAX
TAVLL
TQVWH
TWHQX
P0
P2
A7:0
D7:0
Data Out
A15:8
D15:81
Data Out
Note:
D15:8 is the content of DAT16H SFR.
SPI Interface
Definition of Symbols
Table 135. SPI Interface Timing Symbol Definitions
Signals
Conditions
High
C
I
Clock
H
L
Data In
Data Out
Low
O
V
X
Z
Valid
No Longer Valid
Floating
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4173A–8051–08/02
Timings
Table 136. SPI Interface Master AC Timing
DD = 2.7 to 3.3V, TA = -40° to +85°C
V
Symbol
Parameter
Min
Max
Unit
Slave Mode
TCHCH
Clock Period
8
TOSC
TOSC
TOSC
ns
TCHCX
Clock High Time
Clock Low Time
SS Low to Clock edge
3.2
3.2
200
100
100
TCLCX
TSLCH, TSLCL
T
T
T
T
T
T
T
IVCL, TIVCH
CLIX, TCHIX
CLOV, TCHOV
CLOX, TCHOX
CLSH, TCHSH
IVCL, TIVCH
CLIX, TCHIX
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
SS High after Clock Edge
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
SS Low to Output Data Valid
Output Data Hold after SS High
SS High to SS Low
ns
ns
100
ns
0
ns
0
ns
100
100
ns
ns
TSLOV
TSHOX
TSHSL
TILIH
130
130
ns
ns
(1)
Input Rise Time
2
µs
µs
ns
ns
TIHIL
Input Fall Time
2
TOLOH
TOHOL
Output Rise Time
100
100
Output Fall Time
Master Mode
TCHCH
Clock Period
4
TOSC
TOSC
TOSC
ns
TCHCX
Clock High Time
1.6
1.6
50
50
TCLCX
Clock Low Time
TIVCL, TIVCH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
Input Data Rise Time
T
T
T
CLIX, TCHIX
CLOV, TCHOV
CLOX, TCHOX
ns
65
ns
0
ns
TILIH
2
2
µs
TIHIL
Input Data Fall Time
µs
TOLOH
TOHOL
Output Data Rise Time
50
50
ns
Output Data Fall Time
ns
Notes: 1. Value of this parameter depends on software.
2. Test conditions: capacitive load on all pins = 100 pF
146
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AT8xC5132
Waveforms
Figure 123. SPI Slave Waveforms (SSCPHA = 0)
SS
(input)
TCLSH
TCHSH
TSLCH
TSLCL
TCHCH
TSHSL
TCLCH
SCK
(SSCPOL = 0)
(input)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(input)
TCLOX
TCHOX
TCLOV
TCHOV
TSLOV
TSHOX
MISO
(output)
SLAVE MSB OUT
BIT 6
SLAVE LSB OUT
1
TCHIX
TCLIX
TIVCH
TIVCL
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
Not Defined but generally the MSB of the character that has just been received.
Figure 124. SPI Slave Waveforms (SSCPHA = 1)
SS#1
(output)
TCHCH
TCLCH
SCK
(SSCPOL = 0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(output)
TIVCH
TCHIX
TIVCL TCLIX
SI
(input)
MSB IN
BIT 6
TCLOV
TCHOV
LSB IN
TCLOX
TCHOX
SO
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
Not Defined but generally the LSB of the character that has just been received.
147
4173A–8051–08/02
Figure 125. SPI Master Waveforms (SSCPHA = 0)
SS#1
(input)
TSLCH
TCLSH
TCHSH
TSLCL
TCHCH
TSHSL
TCLCH
SCK
(SSCPOL = 0)
(input)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(input)
TCHOV
TCLOV
TCHOX
TCLOX
TSLOV
SLAVE MSB OUT
TSHOX
MISO
(output)
BIT 6
SLAVE LSB OUT
1
TIVCH
TIVCL
TCHIX
TCLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
SS handled by software using general purpose port pin.
Figure 126. SPI Master Waveforms (SSCPHA = 1)
SS#1
(output)
TCHCH
TCLCH
SCK
(SSCPOL = 0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(output)
TIVCH
TCHIX
TIVCL TCLIX
SI
(input)
MSB IN
TCLOV
BIT 6
TCLOX
TCHOX
BIT 6
LSB IN
TCHOV
SO
(output)
Port Data
MSB OUT
LSB OUT
Port Data
Note:
SS handled by software using general purpose port pin.
148
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AT8xC5132
Specific Controller
MMC Interface
To be defined.
Definition of Symbols
Table 137. MMC Interface Timing Symbol Definitions
Signals
Conditions
High
C
D
O
Clock
H
L
Data In
Data Out
Low
V
X
Valid
No Longer Valid
Timings
Table 138. MMC Interface AC timings
DD = 2.7 to 3.3V, TA = 0 to 70°C, CL ≤ 100pF (10 Cards)
V
Symbol
TCHCH
Parameter
Min
50
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Period
TCHCX
TCLCX
TCLCH
TCHCL
TDVCH
TCHDX
TCHOX
TOVCH
Clock High Time
10
Clock Low Time
10
Clock Rise Time
10
10
Clock Fall Time
Input Data Valid to Clock High
Input Data Hold after Clock High
Output Data Hold after Clock High
Output Data Valid to Clock High
3
3
5
5
Waveforms
Figure 127. MMC Input Output Waveforms
TCHCH
TCHCX
TCLCX
MCLK
TCHCL
TCLCH
TIVCH
TCHIX
MCMD Input
MDAT Input
TCHOX
TOVCH
MCMD Output
MDAT Output
149
4173A–8051–08/02
Audio Interface
Definition of Symbols
Table 139. Audio Interface Timing Symbol Definitions
Signals
Conditions
High
C
O
S
Clock
H
L
Data Out
Data Select
Low
V
X
Valid
No Longer Valid
Timings
Table 140. Audio Interface AC timings
DD = 2.7 to 3.3V, TA = 0 to 70°C, CL ≤ 30pF
V
Symbol
Parameter
Min
Max
Unit
ns
TCHCH
TCHCX
TCLCX
TCLCH
TCHCL
TCLSV
Clock Period
325.5(1)
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
Clock Low to Select Valid
30
30
ns
ns
10
10
10
10
ns
ns
ns
TCLOV
Note:
Clock Low to Data Valid
ns
32-bit format with Fs = 48 kHz.
Waveforms
Figure 128. Audio Interface Waveforms
TCHCH
TCHCX
TCLCX
DCLK
TCHCL
TCLCH
TCLSV
DSEL
DDAT
Right
Left
TCLOV
150
AT8xC5132
4173A–8051–08/02
AT8xC5132
Analog to Digital Converter
Definition of Symbols
Table 141. Analog to Digital Converter Timing Symbol Definitions
Signals
Conditions
High
C
E
Clock
H
L
Enable (ADEN bit)
Low
Start Conversion
(ADSST bit)
S
Characteristics
Table 142. Analog to Digital Converter AC Characteristics
DD = 2.7 to 3.3V, TA = 0 to 70°C
V
Symbol
Parameter
Min
Max
Unit
µs
TCLCL
TEHSH
TSHSL
Clock Period
Start-up Time
Conversion Time
1.43
4
µs
11·TCLCL
µs
Differential non-
DLe
ILe
TBD
TBD
LSB
LSB
linearity error(1), (2)
Integral non-
linearity error(1),( 3)
OSe
Ge
Offset error(1),(4)
Gain error(1),( 5)
TBD
TBD
LSB
%
Notes: 1. AVDD = AVREFP = 3.0V, AVSS = AVREFN = 0V. ADC is monotonic with no missing code.
2. The differential non-linearity is the difference between the actual step width and the
ideal step width (see Figure 130).
3. The integral non-linearity is the peak difference between the center of the actual step
and the ideal transfer curve after appropriate adjustment of gain and offset errors
(see Figure 130).
4. The offset error is the absolute difference between the straight line which fits the
actual transfer curve (after removing of gain error), and the straight line which fits the
ideal transfer curve (see Figure 130).
5. The gain error is the relative difference in percent between the straight line which fits
the actual transfer curve (after removing of offset error), and the straight line which
fits the ideal transfer curve (see Figure 130).
Waveforms
Figure 129. Analog-to-Digital Converter Internal Waveforms
CLK
TCLCL
ADEN Bit
TEHSH
ADSST Bit
TSHSL
151
4173A–8051–08/02
Figure 130. Analog-to-Digital Converter Characteristics
Offset Gain
Error Error
Code Out
OSe
Ge
1023
1022
1021
1020
1019
1018
Ideal Transfer Curve
7
6
5
4
Example of an Actual Transfer Curve
Center of a Step
Integral Non-linearity (ILe)
3
2
1
Differential Non-linearity (DLe)
1 LSB
(Ideal)
0
0
AVIN (LSBideal)
1
2
3
4
5
6
7
1018 1019 1020 1021 1022 1023 1024
Offset
Error
OSe
Flash Memory
Definition of Symbols
Table 143. Flash Memory Timing Symbol Definitions
Signals
Conditions
S
R
B
ISP#
L
V
X
Low
RST
Valid
FBUSY flag
No Longer Valid
Timings
Table 144. Flash Memory AC Timing
DD = 2.7 to 3.3V, TA = -40° to +85°C
V
Symbol
Parameter
Min
50
Typ
Max
Unit
TSVRL
TRLSX
TBHBL
Input ISP Valid to RST Edge
Input ISP Hold after RST Edge
Flash Internal Busy (Programming) Time
ns
ns
50
10
ms
152
AT8xC5132
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AT8xC5132
Waveforms
Figure 131. Flash Memory – ISP Waveforms
RST
TSVRL
TRLSX
ISP1
Note:
ISP must be driven through a pull-down resistor (see Section “In-system Programming”,
page 140).
Figure 132. Flash Memory – Internal Busy Waveforms
FBUSY bit
TBHBL
External Clock Drive and Logic Level References
Definition of Symbols Table 145. External Clock Timing Symbol Definitions
Signals
Clock
Conditions
High
C
H
L
Low
X
No Longer Valid
Timings
Table 146. External Clock AC Timings
DD = 2.7 to 3.3V, TA= 0 to 70°C
V
Symbol
TCLCL
Parameter
Min
50
10
10
3
Max
Unit
ns
ns
ns
ns
ns
%
Clock Period
High Time
TCHCX
TCLCX
TCLCH
TCHCL
TCR
Low Time
Rise Time
Fall Time
3
Cyclic Ratio in X2 Mode
40
60
Waveforms
Figure 133. External Clock Waveform
TCLCH
TCHCX
VDD - 0.5
VIH1
TCLCX
VIL
0.45 V
TCHCL
TCLCL
153
4173A–8051–08/02
Figure 134. AC Testing Input/Output Waveforms
INPUTS
OUTPUTS
VIH min
VIL max
- 0.5
DD
0.7 VDD
0.3 VDD
0.45 V
Notes: 1. During AC testing, all inputs are driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0.
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 135. Float Waveforms
VLOAD + 0.1V
LOAD - 0.1V
VOH - 0.1V
OL + 0.1V
VLOAD
Timing Reference Points
V
V
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a
100 mV change from the loading VOH/VOL level occurs with IOL/IOH = 20 mA.
154
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AT8xC5132
Ordering Information
Possible Order Entries(2)
Temperature
Range
Memory Size
Supply
Voltage
Max Frequency
(MHz)
Part Number
AT89C5132-ROTIL
AT83C5132xxx(1)-ROTIL
(Bytes)
64K Flash
64K ROM
64K ROM
64K ROM
Package
Packing
Tray
3V
3V
3V
3V
Industrial
Industrial
Industrial
Industrial
40
40
40
40
TQFP80
TQFP80
TQFP64
TQFP64
Tray
AT89C5132-RDTIL
AT83C5132xxx(1)-RDTIL
Tray
Tray
Notes: 1. Refers to ROM code. Check for availability.
2. PLCC84 package only available for development board.
155
4173A–8051–08/02
Package Information
TQFP80
156
AT8xC5132
4173A–8051–08/02
AT8xC5132
PLCC84
157
4173A–8051–08/02
TQFP64
158
AT8xC5132
4173A–8051–08/02
AT8xC5132
Table of Contents
Features ................................................................................................. 1
Description ............................................................................................ 1
Typical Applications ............................................................................. 1
Block Diagram ....................................................................................... 2
Pin Configuration .................................................................................. 3
Pin Description ..................................................................................... 6
Internal Pin Structure.......................................................................................... 11
Clock Controller .................................................................................. 12
Oscillator............................................................................................................. 12
X2 Feature.......................................................................................................... 12
PLL ..................................................................................................................... 13
Registers..............................................................................................................15
Program/Code Memory ...................................................................... 18
ROM Memory Architecture ................................................................................. 18
Flash Memory Architecture................................................................................. 19
Hardware Security System ................................................................................. 20
Boot Memory Execution...................................................................................... 20
Registers..............................................................................................................22
Hardware Bytes ...................................................................................................23
Data Memory ....................................................................................... 24
Internal Space..................................................................................................... 24
External Space ....................................................................................................26
Dual Data Pointer ............................................................................................... 28
Registers............................................................................................................. 29
Special Function Registers ................................................................ 31
Interrupt System ................................................................................. 36
Interrupt System Priorities .................................................................................. 36
External Interrupts .............................................................................................. 39
Registers..............................................................................................................40
Power Management ............................................................................ 46
Reset .................................................................................................................. 46
Reset Recommendation to Prevent Flash Corruption ........................................ 46
Idle Mode............................................................................................................ 47
159
4173A–8051–08/02
Power-down Mode.............................................................................................. 47
Registers............................................................................................................. 49
Timers/Counters ................................................................................. 50
Timer/Counter Operations .................................................................................. 50
Timer Clock Controller........................................................................................ 50
Timer 0................................................................................................................ 51
Timer 1................................................................................................................ 53
Interrupt .............................................................................................................. 54
Registers..............................................................................................................55
Watchdog Timer .................................................................................. 58
Description.......................................................................................................... 58
Watchdog Clock Controller................................................................................. 58
Watchdog Operation............................................................................................59
Registers..............................................................................................................60
Audio Output Interface ....................................................................... 61
Description.......................................................................................................... 61
Clock Generator...................................................................................................62
Data Converter ................................................................................................... 62
Audio Buffer........................................................................................................ 63
Interrupt Request................................................................................................ 64
Voice or Sound Playing ...................................................................................... 64
Registers..............................................................................................................66
Universal Serial Bus ........................................................................... 68
Description...........................................................................................................69
USB Interrupt System......................................................................................... 71
Registers..............................................................................................................73
MultiMedia Card Controller ................................................................ 82
Card Concept...................................................................................................... 82
Bus Concept ....................................................................................................... 82
Description.......................................................................................................... 87
Clock Generator.................................................................................................. 88
Command Line Controller................................................................................... 89
Data Line Controller.............................................................................................91
Interrupt ...............................................................................................................97
Registers..............................................................................................................98
IDE/ATAPI Interface .......................................................................... 104
Description........................................................................................................ 104
Registers........................................................................................................... 106
160
AT8xC5132
4173A–8051–08/02
AT8xC5132
Serial I/O Port .................................................................................... 107
Mode Selection................................................................................................. 107
Baud Rate Generator........................................................................................ 107
Synchronous Mode (Mode 0) ........................................................................... 108
Asynchronous Modes (Modes 1, 2 and 3).........................................................110
Multiprocessor Communication (Modes 2 and 3) ..............................................113
Automatic Address Recognition........................................................................ 113
Interrupt .............................................................................................................115
Registers............................................................................................................116
Synchronous Peripheral Interface .................................................. 119
Description.........................................................................................................120
Interrupt ............................................................................................................ 123
Configuration .....................................................................................................124
Registers........................................................................................................... 127
Analog-to-Digital Converter ............................................................. 129
Description........................................................................................................ 129
Registers............................................................................................................132
Keyboard Interface ........................................................................... 134
Description........................................................................................................ 134
Registers............................................................................................................135
Electrical Characteristics ................................................................. 136
Absolute Maximum Ratings.............................................................................. 136
DC Characteristics............................................................................................ 136
AC Characteristics............................................................................................ 141
Ordering Information ........................................................................ 155
Package Information ........................................................................ 156
TQFP80 ............................................................................................................ 156
PLCC84 .............................................................................................................157
TQFP64 ............................................................................................................ 158
161
4173A–8051–08/02
Atmel Headquarters
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Corporate Headquarters
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e-mail
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Web Site
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
Atmel®, is a registered trademark of Atmel. MultiMedia Card® is a registered trademark of MultiMedia
Corporation. SmartMedia® is a registered trademark of Toshiba Corporation. CompactFlash™ is a trademark of
CompactFlash Corporation.
Printed on recycled paper.
4173A–8051–08/02
/0M
Other terms and product names may be the trademarks of others.
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