AT83C5134_14_技术文档

Features

•

80C52X2 Core (6 Clocks per Instruction)

– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode

– Dual Data Pointer

– Full-duplex Enhanced UART (EUART), TxD and Rxd are 5 Volt Tolerant

– Three 16-bit Timer/Counters: T0, T1 and T2

– 256 Bytes of Scratchpad RAM

•

8/16/32-Kbyte On-chip ROM

512 byte or 32-Kbyte EEPROM⁽¹⁾

8-bit

On-chip Expanded RAM (ERAM): 1024 Bytes

Microcontroller

with Full Speed

USB Device

Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply

USB 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion (12Mbps)

– Endpoint 0 for Control Transfers: 32-byte FIFO

– 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or

Isochronous Transfers

• Endpoint 1, 2, 3: 32-byte FIFO

• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)

– Suspend/Resume Interrupts

AT83C5134

AT83C5135

AT83C5136

– Power-on Reset and USB Bus Reset

– 48 MHz DPLL for Full-speed Bus Operation

– USB Bus Disconnection on Microcontroller Request

5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed

Output, Compare/Capture, PWM and Watchdog Timer Capabilities

Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 50 ms to

6s at 4 MHz

•

Keyboard Interrupt Interface on Port P1 (8 Bits)

TWI (Two Wire Interface) 400Kbit/s

SPI Interface (Master/Slave Mode) MISO,MOSI,SCK and SS are 5 Volt Tolerant

34 I/O Pins

4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical

4-level Priority Interrupt System (11 sources)

Idle and Power-down Modes

0 to 32 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis

Industrial Temperature Range

Low Voltage Range Supply: 2.7V to 3.6V

Packages: Die SO28, QFN32, MLF48, TQFP64

Notes: 1. EEPROM only available on MLF48

1. Description

AT83C5134/35/36 are high performance ROM versions

of the 80C51 single-chip 8-bit microcontrollers with full

speed USB functions.

AT83C5134/35 is pin compatible with AT89C5130A 16-

Kbytes In-System Programmable Flash microcontrollers.

This allows to use AT89C5130A for development, pre-production and flexibility, while using

AT83C5134/35 for cost reduction in mass production. Similarly AT83C5136 is pin compatible

with AT89C5131A 32-Kbytes Flash microcontroller.

AT83C5134/35/36 features a full-speed USB module compatible with the USB specifications

Version 2.0. This module integrates the USB transceivers and the Serial Interface Engine (SIE)

with Digital Phase Locked Loop and 48 MHz clock recovery. USB Event detection logic (Reset

and Suspend/Resume) and FIFO buffers supporting the mandatory control Endpoint (EP0) and

5 versatile Endpoints (EP1/EP2/EP3/EP4/EP5) with minimum software overhead are also part of

the USB module.

AT83C5134/35/36 retains the features of the Atmel 80C52 with extended ROM cpacity (8/16/32

Kbytes), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1),

a full duplex enhanced UART (EUART) and an on-chip oscillator.

In addition, AT83C5134/35/36 has an on-chip expanded RAM of 1024 bytes (ERAM), a dual-

data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA), up to 4 pro-

grammable LED current sources, a programmable hardware watchdog and a power-on reset.

AT83C5134/35/36 has two software-selectable modes of reduced activity for further reduction in

power consumption. In the idle mode the CPU is frozen while the timers, the serial ports and the

interrupt system are still operating. In the power-down mode the RAM is saved, the peripheral

clock is frozen, but the device has full wake-up capability through USB events or external

interrupts.

2

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

3. Block Diagram

(1)

(1) (1)

(1) (1) (1)

(1) (1)

(2) (2)

XTAL1

XTAL2

EEPROM*

1Kx8

ERAM

1Kx8

EUART

+

BRG

32Kx8 ROM

RAM

256x8

SPI

PCA

TWI

Timer2

TWI interface

ALE

C51

CORE

PSEN

CPU

EA

(2)

Parallel I/O Ports & Ext. Bus

Port 0Port 1 Port 3

Timer 0

Timer 1

Key Watch

Board Dog

INT

Ctrl

RD

USB

Port 2

Port 4

WR

(2) (2)

* EEPROM only available in MLF48

Notes: 1. Alternate function of Port 1

2. Alternate function of Port 3

3. Alternate function of Port 4

3

7683C–USB–11/07

4. Pinout Description

4.1

Pinout

Figure 4-1. AT83C5134/35/36 64-pin VQFP Pinout

63 62 61 60 59 58

52

49

51 50

57 56 55 54 53

64

48

47

NC

1

2

NC

P2.3/A11

NC

46

45

3

4

P2.4/A12

P2.5/A13

XTAL2

P0.1/AD1

P0.2/AD2

44

43

42

5

6

7

RST

P0.3/AD3

XTAL1

P2.6/A14

VSS

41

40

39

8

P2.7/A15

VDD

NC

VQFP64

9

P0.4/AD4

10

AVDD

P3.7/RD/LED3

P0.5/AD5

38

37

11

12

13

NC

AVSS

NC

P0.6/AD6

P0.7/AD7

P3.6/WR/LED2

NC

36

35

34

14

15

16

P3.0/RxD

NC

33

NC

3132

17 18 19 20 21 22 23 24 25 26 27 28 29

30

4

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Figure 4-2. AT83C5134/35/36 48-pin MLF Pinout

48 47 46 45 44 43 42 41 40 39 38

37

36

P4.1/SDA

P2.3/A11

P2.4/A12

P2.5/A13

XTAL2

1

2

3

4

5

6

7

8

9

P1.0/T2/KIN0

P0.1/AD1

35

34

33

32

P0.2/AD2

RST

P0.3/AD3

XTAL1

31 VSS

P2.6/A14

P2.7/A15

30

P0.4/AD4

MLF48

P3.7/RD/LED3

P0.5/AD5

29

28

VDD

AVDD

10

11

27

26

25

P0.6/AD6

AVSS

P0.7/AD7

P3.0/RxD 12

13

P3.6/WR/LED2

15 16 17 18

20

24

21 22 23

19

14

Figure 4-3. AT83C5134/35/36 28-pin SO Pinout

P1.5/CEX2/KIN5/MISO

P1.6/CEX3/KIN6/SCK

P1.7/CEX4/KIN7/MOSI

P4.0/SCL

28 P1.4/CEX1/KIN4

27 P1.3/CEX0/KIN3

1

2

26

25

P1.2/ECI/KIN2

3

4

P1.1/T2EX/KIN1/SS

P1.0/T2/KIN0

P4.1/SDA

24

5

SO28

XTAL2

23 RST

6

7

8

VSS

22

21

XTAL1

VDD

P3.7/RD/LED3

P3.6/WR/LED2

9

20

19

18

AVSS

P3.5/T1/LED1

P3.4/T0

10

P3.0/RxD

11

12

PLLF

D-

P3.3/INT1/LED0

P3.2/INT0

17

16

15

D+

13

14

VREF

P3.1/TxD

5

7683C–USB–11/07

Figure 4-4. AT83C5134/35/36 32-pin QFN Pinout

32 31 30 29 28 27 26 25

P4.1/SDA

XTAL2

XTAL1

VDD

1

2

3

4

5

6

7

8

24

23

P1.0/T2/KIN0

RST

22 NC

21 VSS

20 VSS

QFN32

AVDD

AVSS

19

18

17

P3.7/RD/LED3

P3.6/WR/LED2

P3.5/T1/LED1

P3.0/RxD

PLLF

9 10 11 12 13 14 15 16

Note : The metal plate can be connected to Vss

4.2

Signals

All the AT83C5134/35/36 signals are detailed by functionality on Table 4-1 through Table 4-12.

Table 4-1.

Keypad Interface Signal Description

Signal

Name

Alternate

Function

Type Description

Keypad Input Lines

KIN[7:0)

I

Holding one of these pins high or low for 24 oscillator periods triggers a keypad

interrupt if enabled. Held line is reported in the KBCON register.

P1[7:0]

Table 4-2.

Programmable Counter Array Signal Description

Signal

Name

Alternate

Function

Type Description

ECI

I

External Clock Input

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

Capture External Input

CEX[4:0]

I/O

Compare External Output

6

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 4-3.

Serial I/O Signal Description

Signal

Name

Alternate

Function

Type Description

Serial Input

I

RxD

TxD

P3.0

The serial input for Extended UART. This I/O is 5 Volt Tolerant.

Serial Output

The serial output for Extended UART. This I/O is 5 Volt Tolerant.

O

P3.1

Table 4-4.

Timer 0, Timer 1 and Timer 2 Signal Description

Signal

Name

Alternate

Function

Type Description

Timer 0 Gate Input

INT0 serves as external run control for timer 0, when selected by GATE0 bit in

TCON register.

INT0

I

P3.2

External Interrupt 0

INT0 input set IE0 in the TCON register. If bit IT0 in this register is set, bits IE0 are

set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by a low level on

INT0.

Timer 1 Gate Input

INT1 serves as external run control for Timer 1, when selected by GATE1 bit in

TCON register.

INT1

I

P3.3

External Interrupt 1

INT1 input set IE1 in the TCON register. If bit IT1 in this register is set, bits IE1 are

set by a falling edge on INT1. If bit IT1 is cleared, bits IE1 is set by a low level on

INT1.

Timer Counter 0 External Clock Input

When Timer 0 operates as a counter, a falling edge on the T0 pin increments the

count.

T0

T1

I

P3.4

P3.5

Timer/Counter 1 External Clock Input

When Timer 1 operates as a counter, a falling edge on the T1 pin increments the

count.

I

Timer/Counter 2 External Clock Input

Timer/Counter 2 Clock Output

T2

P1.0

P1.1

O

T2EX

I

Timer/Counter 2 Reload/Capture/Direction Control Input

Table 4-5.

LED Signal Description

Signal

Name

Alternate

Function

Type Description

Direct Drive LED Output

P3.3

P3.5

P3.6

P3.7

These pins can be directly connected to the Cathode of standard LEDs without

external current limiting resistors. The typical current of each output can be

programmed by software to 2, 6 or 10 mA. Several outputs can be connected

together to get higher drive capabilities.

LED[3:0]

O

7

7683C–USB–11/07

Table 4-6.

TWI Signal Description

Signal

Name

Alternate

Function

Type Description

SCL: TWI Serial Clock

SCL output the serial clock to slave peripherals.

SCL input the serial clock from master.

SCL

SDA

I/O

P4.0

P4.1

SDA: TWI Serial Data

SCL is the bidirectional TWI data line.

Table 4-7.

SPI Signal Description

Signal

Name

Alternate

Function

Type Description

SS

I/O

SS: SPI Slave Select . This I/O is 5 Volt tolerant

P1.1

MISO: SPI Master Input Slave Output line

When SPI is in master mode, MISO receives data from the slave peripheral. When

SPI is in slave mode, MISO outputs data to the master controller. This I/O is 5 Volt

tolerant

MISO

I/O

P1.5

SCK: SPI Serial Clock

SCK

I/O

SCK outputs clock to the slave peripheral or receive clock from the master.

This I/O is 5 Volt tolerant.

P1.6

P1.7

MOSI: SPI Master Output Slave Input line

When SPI is in master mode, MOSI outputs data to the slave peripheral. When

SPI is in slave mode, MOSI receives data from the master controller.

MOSI

This I/O is 5 Volt tolerant.

Table 4-8.

Ports Signal Description

Signal

Name

Type Description

Port 0

Alternate Function

P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that

P0[7:0]

I/O

have 1s written to them float and can be used as high

impedance inputs. To avoid any parasitic current consumption,

AD[7:0]

Floating P0 inputs must be pulled to V_DDor V_SS

.

KIN[7:0]

T2

Port 1

P1 is an 8-bit bidirectional I/O port with internal pull-ups.

P1[7:0]

P2[7:0]

I/O

T2EX

ECI

CEX[4:0]

Port 2

A[15:8]

P2 is an 8-bit bidirectional I/O port with internal pull-ups.

8

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Signal

Name

Type Description

Alternate Function

LED[3:0]

RxD

TxD

INT0

INT1

T0

Port 3

P3[7:0]

I/O

P3 is an 8-bit bidirectional I/O port with internal pull-ups.

T1

WR

RD

SCL

SDA

Port 4

P4 is an 2-bit open port.

P4[1:0]

I/O

Table 4-9.

Clock Signal Description

Signal

Name

Alternate

Function

Type Description

Input to the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If

an external oscillator is used, its output is connected to this pin.

XTAL1

I

-

Output of the on-chip inverting oscillator amplifier

XTAL2

PLLF

O

I

To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If

an external oscillator is used, leave XTAL2 unconnected.

-

PLL Low Pass Filter input

Receives the RC network of the PLL low pass filter (See Figure 5-1 on page 11 ).

Table 4-10. USB Signal Description

Signal

Name

Alternate

Function

Type Description

USB Data + signal

D+

I/O

O

-

Set to high level under reset.

USB Data - signal

D-

Set to low level under reset.

USB Reference Voltage

VREF

Connect this pin to D+ using a 1.5 kΩ resistor to use the Detach function.

Table 4-11. System Signal Description

Signal

Name

Alternate

Function

Type Description

Multiplexed Address/Data LSB for external access

I/O

AD[7:0]

P0[7:0]

P2[7:0]

Data LSB for Slave port access (used for 8-bit and 16-bit modes)

Address Bus MSB for external access

A[15:8]

I/O

Data MSB for Slave port access (used for 16-bit mode only)

9

7683C–USB–11/07

Signal

Name

Alternate

Function

Type Description

Read Signal

Read signal asserted during external data memory read operation.

RD

I/O

P3.7

P3.6

Control input for slave port read access cycles.

Write Signal

Write signal asserted during external data memory write operation.

WR

I/O

Control input for slave write access cycles.

Reset

Holding this pin low for 64 oscillator periods while the oscillator is running resets

the device. The Port pins are driven to their reset conditions when a voltage lower

than V_ILis applied, whether or not the oscillator is running.

This pin has an internal pull-up resistor which allows the device to be reset by

connecting a capacitor between this pin and VSS.

RST

I/O

-

Asserting RST when the chip is in Idle mode or Power-down mode returns the chip

to normal operation.

This pin is set to 0 for at least 12 oscillator periods when an internal reset occurs

(hardware watchdog or Power monitor).

Address Latch Enable Output

ALE

O

The falling edge of ALE strobes the address into external latch. This signal is

active only when reading or writing external memory using MOVX instructions.

-

Program Strobe Enable / Hardware conditions Input for ISP

PSEN

-

Used as input under reset to detect external hardware conditions of ISP mode

External Access Enable

This pin must be held low to force the device to fetch code from external program

memory starting at address 0000h. It is latched during reset and cannot be

dynamically changed during operation.

EA

I

-

Table 4-12. Power Signal Description

Signal

Name

Alternate

Function

Type Description

Alternate Ground

AVSS

GND

PWR

GND

-

AVSS is used to supply the on-chip PLL and the USB PAD.

Alternate Supply Voltage

AVDD is used to supply the on-chip PLL and the USB PAD.

AVDD

VSS

Digital Ground

VSS is used to supply the buffer ring and the digital core.

Digital Supply Voltage

VDD is used to supply the buffer ring on all versions of the device.

VDD

PWR

-

It is also used to power the on-chip voltage regulator of the Standard versions or

the digital core of the Low Power versions.

USB pull-up Controlled Output

VREF is used to control the USB D+ 1.5 kΩ pull up.

VREF

O

The Vref output is in high impedance when the bit DETACH is set in the USBCON

register.

10

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

5. Typical Application

5.1

Recommended External components

All the external components described in the figure below must be implemented as close as pos-

sible from the microcontroller package.

The following figure represents the typical wiring schematic.

Figure 5-1. Typical Application

VDD

100nF

4.7µF

VSS

1.5K

USB

VBUS

D+

VRef

AT83C5134/35/3

27R

D+

D-

XTAL1

22pF

D-

Q

GND

VSS

XTAL2

VSS

PLLF

560

820pF

150pF

VSS

11

7683C–USB–11/07

5.2

PCB Recommandations

Figure 5-2. USB Pads

Components must be

close to the

Wires must be routed in Parallel and

must be as short as possible

microcontroller

VRef

D+

D-

USB Connector

If possible, isolate D+ and D- signals from other signals

with ground wires

Note:

No sharp angle in above drawing.

Figure 5-3. USB PLL

AVss PLLF

Components must be

close to the

microcontroller

Isolate filter components

with a ground wire

12

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

6. Clock Controller

6.1

Introduction

The AT83C5134/35/36 clock controller is based on an on-chip oscillator feeding an on-chip

Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated

by this controller.

The AT83C5134/35/36 X1 and X2 pins are the input and the output of a single-stage on-chip

inverter (see Figure 6-1) that can be configured with off-chip components as a Pierce oscillator

(see Figure 6-2). Value of capacitors and crystal characteristics are detailed in the section “DC

Characteristics”.

The X1 pin can also be used as input for an external 48 MHz clock.

The clock controller outputs three different clocks as shown in Figure 6-1:

• a clock for the CPU core

• a clock for the peripherals which is used to generate the Timers, PCA, WD, and Port

sampling clocks

• a clock for the USB controller

These clocks are enabled or disabled depending on the power reduction mode as detailed in

Section “Power Management”, page 135.

Figure 6-1. Oscillator Block Diagram

0

1

÷

2

Peripheral

Clock

CPU Core

Clock

X2

CKCON.0

IDL

PCON.0

PLL

0

1

X1

X2

USB

Clock

EXT48

PLLCON.2

PD

PCON.1

6.2

Oscillator

Two clock sources are available for CPU:

• Crystal oscillator on X1 and X2 pins: Up to 32 MHz

• External 48 MHz clock on X1 pin

13

7683C–USB–11/07

In order to optimize the power consumption, the oscillator inverter is inactive when the PLL out-

put is not selected for the USB device.

Figure 6-2. Crystal Connection

X1

C1

Q

C2

VSS

X2

6.3

PLL

6.3.1

PLL Description

The AT83C5134/35/36 PLL is used to generate internal high frequency clock (the USB Clock)

synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to

generate the USB interface clock. Figure 6-3 shows the internal structure of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the

comparison between the reference clock coming from the N divider and the reverse clock com-

ing from the R divider and generates some pulses on the Up or Down signal depending on the

edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the

clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Figure 6-3) is

set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by inject-

ing or extracting charges from the external filter connected on PLLF pin (see Figure 6-4). Value

of the filter components are detailed in the Section “DC Characteristics”.

The VCO block is the Voltage Controlled Oscillator controlled by the voltage V_REFproduced by

the charge pump. It generates a square wave signal: the PLL clock.

Figure 6-3. PLL Block Diagram and Symbol

PLLF

CHP

PLLCON.1

PLLEN

N divider

N3:0

Up

SC

OCK

Vref

PFLD

VCO

USB Clock

Down

PLOCK

PLLCON.0

R divider

R3:0

USB

CLOCK

OSCclk × (R + 1)

USBclk = ----------------------------------------------

N + 1

USB Clock Sym

14

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Figure 6-4. PLL Filter Connection

PLLF

R

C2

C1

VSS

The typical values are: R = 560 Ω, C1 = 820 pf, C2 = 150 pF.

PLL Programming

6.3.2

The PLL is programmed using the flow shown in Figure 6-5. As soon as clock generation is

enabled user must wait until the lock indicator is set to ensure the clock output is stable.

Figure 6-5. PLL Programming Flow

PLL

Programming

Configure Dividers

N3:0 = xxxxb

R3:0 = xxxxb

Enable PLL

PLLEN = 1

PLL Locked?

LOCK = 1?

6.3.3

Divider Values

To generate a 48 MHz clock using the PLL, the divider values have to be configured following

the oscillator frequency. The typical divider values are shown in Table 6-1.

Table 6-1.

Typical Divider Values

Oscillator Frequency

R+1

16

8

N+1

1

PLLDIV

F0h

70h

3 MHz

6 MHz

1

8 MHz

6

1

50h

12 MHz

16 MHz

18 MHz

20 MHz

24 MHz

4

1

30h

3

1

20h

8

3

72h

12

2

5

B4h

10h

1

15

7683C–USB–11/07

Oscillator Frequency

32 MHz

R+1

3

N+1

2

PLLDIV

21h

40 MHz

12

10

B9h

6.4

Registers

Table 6-2.

CKCON0 (S:8Fh)

Clock Control Register 0

7

6

5

4

3

2

1

0

TWIX2

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Bit

Bit Number Mnemonic Description

TWI Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit

has no effect.

7

6

5

4

3

2

TWIX2

WDX2

PCAX2

SIX2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Watchdog Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit

has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit

has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART Clock (Mode 0 and 2)

This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit

has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer2 Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit

has no effect.

T2X2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer1 Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit

has no effect.

T1X2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer0 Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit

has no effect.

1

0

T0X2

X2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

System Clock Control bit

Clear to select 12 clock periods per machine cycle (STD mode, F_CPU= F_{PER =}F_OSC

Set to select 6 clock periods per machine cycle (X2 mode, F_{CPU =}F_{PER =}F_OSC).

/2).

Reset Value = 0000 0000b

16

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 6-3.

CKCON1 (S:AFh)

Clock Control Register 1

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

SPIX2

Bit

Bit Number Mnemonic Description

Reserved

7-1

0

-

The value read from this bit is always 0. Do not set this bit.

SPI Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit

has no effect.

SPIX2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Reset Value = 0000 0000b

Table 6-4.

PLLCON (S:A3h)

PLL Control Register

7

-

6

-

5

-

4

-

3

-

2

1

0

EXT48

PLLEN

PLOCK

Bit

Bit Number Mnemonic Description

Reserved

7-3

2

-

The value read from this bit is always 0. Do not set this bit.

External 48 MHz Enable Bit

Set this bit to bypass the PLL and disable the crystal oscillator.

Clear this bit to select the PLL output as USB clock and to enable the crystal oscillator.

EXT48

PLL Enable Bit

1

0

PLLEN

PLOCK

Set to enable the PLL.

Clear to disable the PLL.

PLL Lock Indicator

Set by hardware when PLL is locked.

Clear by hardware when PLL is unlocked.

Reset Value = 0000 0000b

Table 6-5.

PLLDIV (S:A4h)

PLL Divider Register

7

6

5

4

3

2

1

0

R3

R2

R1

R0

N3

N2

N1

N0

Bit

Bit Number Mnemonic Description

7-4

3-0

R3:0

N3:0

PLL R Divider Bits

PLL N Divider Bits

Reset Value = 0000 0000

17

7683C–USB–11/07

7. SFR Mapping

The Special Function Registers (SFRs) of the AT83C5134/35/36 fall into the following

categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP

• I/O port registers: P0, P1, P2, P3, P4

• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L,

RCAP2H

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON

• PCA (Programmable Counter Array) registers: CCON, CMOD, CCAPMx, CL, CH, CCAPxH,

CCAPxL (x: 0 to 4)

• Power and clock control registers: PCON

• Hardware Watchdog Timer registers: WDTRST, WDTPRG

• Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1

• Keyboard Interface registers: KBE, KBF, KBLS

• LED register: LEDCON

• Two Wire Interface (TWI) registers: SSCON, SSCS, SSDAT, SSADR

• Serial Port Interface (SPI) registers: SPCON, SPSTA, SPDAT

• USB registers: Uxxx (17 registers)

• PLL registers: PLLCON, PLLDIV

• BRG (Baud Rate Generator) registers: BRL, BDRCON

• Others: AUXR, AUXR1, CKCON0, CKCON1

18

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

The table below shows all SFRs with their address and their reset value.

SFR Descriptions

Table 7-1.

Bit

Addressable

Non-Bit Addressable

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

CH

CCAP0H

CCAP1H

CCAP2H

CCAP3H

CCAP4H

UEPINT

F8h

F0h

FFh

F7h

0000 0000

XXXX XXXX

LEDCON

B

0000 0000

CL

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

E8h

E0h

D8h

D0h

C8h

C0h

EFh

E7h

DFh

D7h

CFh

C7h

0000 0000

XXXX XXXX

ACC

0000 0000

UBYCTLX

0000 0000

UBYCTHX

0000 0000

CCON

CMOD

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

00X0 0000

00XX X000

X000 0000

PSW

UEPCONX

1000 0000

UEPRST

0000 0000

T2CON

0000 0000

T2MOD

XXXX XX00

RCAP2L

0000 0000

RCAP2H

0000 0000

TL2

0000 0000

TH2

0000 0000

UEPSTAX

0000 0000

UEPDATX

0000 0000

P4

SPCON

SPSTA

SPDAT

UEPIEN

USBADDR

1000 0000

UEPNUM

0000 0000

XXXX 1111

0001 0100

0000 0000

XXXX XXXX

IPL0

SADEN

UFNUML

UFNUMH

0000 0000

USBCON

USBINT

USBIEN

B8h

B0h

A8h

A0h

98h

90h

88h

80h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

0000 0000

X000 000

0000 0000

P3

IPL1

IPH1

IPH0

IEN1

X0XX X000

1111 1111

X0XX X000

X000 0000

IEN0

SADDR

CKCON1

0000 0000

P2

AUXR1

WDTRST

WDTPRG

PLLCON

PLLDIV

XXXX XX00

0000 0000

1111 1111

XXXX X0X0

XXXX XXXX

XXXX X000

SCON

SBUF

BRL

BDRCON

KBLS

KBE

KBF

0000 0000

XXXX XXXX

0000 0000

XXX0 0000

0000 0000

P1

SSCON

SSCS

SSDAT

SSADR

1111 1111

0000 0000

1111 1000

1111 1111

1111 1110

TCON

TMOD

TL0

TL1

TH0

TH1

CKCON0

AUXR

XX0X 0000

0000 0000

P0

PCON

SP

0000 0111

DPL

0000 0000

DPH

0000 0000

1111 1111

00X1 0000

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

Note:

1. FCON access is reserved for the Flash API and ISP software.

Reserved

The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories:

19

7683C–USB–11/07

Table 7-2.

C51 Core SFRs

Mnemonic

Add

E0h

F0h

Name

7

6

5

4

3

2

1

0

ACC

B

Accumulator

B Register

Program Status

Word

PSW

SP

D0h

81h

Stack Pointer

LSB of SPX

Data Pointer Low

byte

DPL

DPH

82h

83h

LSB of DPTR

Data Pointer High

byte

MSB of DPTR

Table 7-3.

I/O Port SFRs

Mnemonic

Add

80h

90h

A0h

B0h

C0h

Name

7

6

5

4

3

2

1

0

P0

P1

P2

P3

P4

Port 0

Port 1

Port 2

Port 3

Port 4 (2bits)

Table 7-4.

Timer SFR’s

Mnemonic

Add

8Ch

8Ah

8Dh

8Bh

CDh

CCh

Name

7

6

5

4

3

2

1

0

TH0

TL0

TH1

TL1

TH2

TL2

Timer/Counter 0 High byte

Timer/Counter 0 Low byte

Timer/Counter 1 High byte

Timer/Counter 1 Low byte

Timer/Counter 2 High byte

Timer/Counter 2 Low byte

Timer/Counter 0 and 1

control

TCON

TMOD

88h

89h

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Timer/Counter 0 and 1

Modes

GATE1

TF2

C/T1#

EXF2

M11

M01

GATE0

EXEN2

C/T0#

TR2

M10

M00

T2CON

T2MOD

C8h

C9h

Timer/Counter 2 control

Timer/Counter 2 Mode

RCLK

TCLK

C/T2#

T2OE

CP/RL2#

DCEN

20

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 7-4.

Timer SFR’s (Continued)

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

Timer/Counter 2

Reload/Capture High byte

RCAP2H

RCAP2L

CBh

Timer/Counter 2

Reload/Capture Low byte

CAh

WDTRST

WDTPRG

A6h

A7h

WatchDog Timer Reset

WatchDog Timer Program

S2

S1

S0

Table 7-5.

Serial I/O Port SFR’s

Mnemonic

Add

98h

99h

B9h

A9h

Name

7

6

5

4

3

2

1

0

SCON

SBUF

Serial Control

Serial Data Buffer

Slave Address Mask

Slave Address

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

SADEN

SADDR

Table 7-6.

Baud Rate Generator SFR’s

Mnemonic

Add

9Ah

9Bh

Name

7

6

5

4

3

2

1

0

BRL

Baud Rate Reload

Baud Rate Control

BDRCON

BRR

TBCK

RBCK

SPD

SRC

Table 7-7.

PCA SFR’s

Mnemo-

nic

Add Name

7

6

CR

5

4

3

2

1

0

CCON

CMOD

CL

D8h PCA Timer/Counter Control

D9h PCA Timer/Counter Mode

E9h PCA Timer/Counter Low byte

F9h PCA Timer/Counter High byte

CF

CCF4

CCF3

CCF2

CPS1

CCF1

CPS0

CCF0

ECF

CIDL

WDTE

CH

CCAPM

0

CCAPM

1

DAh PCA Timer/Counter Mode 0

DBh PCA Timer/Counter Mode 1

DCh PCA Timer/Counter Mode 2

DDh PCA Timer/Counter Mode 3

DEh PCA Timer/Counter Mode 4

ECOM0

ECOM1

ECOM2

ECOM3

ECOM4

CAPP0

CAPP1

CAPP2

CAPP3

CAPP4

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

MAT0

MAT1

MAT2

MAT3

MAT4

TOG0

TOG1

TOG2

TOG3

TOG4

PWM0

PWM1

PWM2

PWM3

PWM4

ECCF0

ECCF1

ECCF2

ECCF3

ECCF4

CCAPM

2

CCAPM

3

CCAPM

4

21

7683C–USB–11/07

Table 7-7.

PCA SFR’s

Mnemo-

nic

Add Name

7

6

5

4

3

2

1

0

CCAP0

H

PCA Compare Capture Module 0

H

CCAP1

PCA Compare Capture Module 1

H

FAh

CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0

CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0

CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0

CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0

CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0

H

FBh

FCh

FDh

FEh

CCAP2

H

PCA Compare Capture Module 2

H

CCAP3

H

PCA Compare Capture Module 3

H

CCAP4

H

PCA Compare Capture Module 4

H

PCA Compare Capture Module 0

L

PCA Compare Capture Module 1

L

CCAP0L EAh

CCAP1L EBh

CCAP2L ECh

CCAP3L EDh

CCAP4L EEh

CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1 CCAP0L0

CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1 CCAP1L0

CCAP2L7 CCAP2L6 CCAP2L5 CCAP2L4 CCAP2L3 CCAP2L2 CCAP2L1 CCAP2L0

CCAP3L7 CCAP3L6 CCAP3L5 CCAP3L4 CCAP3L3 CCAP3L2 CCAP3L1 CCAP3L0

CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1 CCAP4L0

PCA Compare Capture Module 2

L

PCA Compare Capture Module 3

L

PCA Compare Capture Module 4

L

Table 7-8.

Interrupt SFR’s

Mnemo-

nic

Add Name

7

6

5

4

3

2

1

0

IEN0

IEN1

IPL0

IPH0

IPL1

IPH1

A8h Interrupt Enable Control 0

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

B1h Interrupt Enable Control 1

EUSB

PPCL

PPCH

PUSBL

PUSBH

ESPI

PX1L

PX1H

PSPIL

PSPIH

ETWI

PT0L

PT0H

PTWIL

PTWIH

EKB

B8h Interrupt Priority Control Low 0

B7h Interrupt Priority Control High 0

B2h Interrupt Priority Control Low 1

B3h Interrupt Priority Control High 1

PT2L

PT2H

PSL

PSH

PT1L

PT1H

PX0L

PX0H

PKBL

PKBH

Table 7-9.

PLL SFRs

Mnemonic

PLLCON

PLLDIV

Add

A3h

A4h

Name

7

6

5

4

3

2

1

0

PLL Control

PLL Divider

EXT48

N2

PLLEN

N1

PLOCK

N0

R3

R2

R1

R0

N3

Table 7-10. Keyboard SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

Keyboard Flag

Register

KBF

9Eh

KBF7

KBE7

KBF6

KBE6

KBF5

KBF4

KBF3

KBF2

KBE2

KBF1

KBE1

KBF0

Keyboard Input Enable

Register

KBE

9Dh

KBE5

KBE4

KBE3

KBE0

22

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 7-10. Keyboard SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

Keyboard Level

Selector Register

KBLS

9Ch

KBLS7

KBLS6

KBLS5

KBLS4

KBLS3

KBLS2

KBLS1

KBLS0

Table 7-11. TWI SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

Synchronous Serial

Control

SSCON

93h

CR2

SSIE

STA

STO

SI

AA

CR1

CR0

Synchronous Serial

Control-Status

SSCS

SSDAT

SSADR

94h

95h

96h

SC4

SD7

A7

SC3

SD6

A6

SC2

SD5

A5

SC1

SD4

A4

SC0

SD3

A3

-

Synchronous Serial

Data

SD2

A2

SD1

A1

SD0

A0

Synchronous Serial

Address

Table 7-12. SPI SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

Serial Peripheral

Control

SPCON

C3h

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Serial Peripheral

Status-Control

SPSTA

SPDAT

C4h

C5h

SPIF

R7

WCOL

R6

SSERR

R5

MODF

R4

-

Serial Peripheral Data

R3

R2

R1

R0

Table 7-13. USB SFR’s

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

SDRMWU

P

USBCON

BCh

USB Global Control

USBE

SUSPCLK

DETACH

UPRSM

RMWUPE

CONFG

FADDEN

USBADDR

USBINT

C6h

BDh

USB Address

FEN

-

UADD6

-

UADD5

UADD4

UADD3

SOFINT

UADD2

-

UADD1

-

UADD0

SPINT

USB Global Interrupt

WUPCPU

EORINT

USB Global Interrupt

Enable

EWUPCP

U

USBIEN

BEh

-

EEORINT ESOFINT

-

ESPINT

UEPNUM

UEPCONX

UEPSTAX

UEPRST

UEPINT

C7h

D4h

CEh

D5h

F8h

USB Endpoint Number

USB Endpoint X Control

USB Endpoint X Status

USB Endpoint Reset

-

EPNUM3

DTGL

EPNUM2

EPDIR

EPNUM1

EPNUM0

EPEN

-

EPTYPE1 EPTYPE0

DIR

RXOUTB1 STALLRQ

TXRDY

EP4RST

EP4INT

STLCRC RXSETUP RXOUTB0

TXCMP

EP0RST

EP0INT

-

EP5RST

EP5INT

EP3RST

EP3INT

EP2RST

EP2INT

EP1RST

EP1INT

USB Endpoint Interrupt

Enable

UEPIEN

C2h

CFh

-

EP5INTE

FDAT5

EP4INTE

FDAT4

EP3INTE

FDAT3

EP2INTE

FDAT2

EP1INTE

FDAT1

EP0INTE

FDAT0

USB Endpoint X FIFO

Data

UEPDATX

FDAT7

FDAT6

23

7683C–USB–11/07

Table 7-13. USB SFR’s

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

USB Byte Counter Low

(EP X)

UBYCTLX

E2h

BYCT7

BYCT6

BYCT5

BYCT4

BYCT3

BYCT2

BYCT1

BYCT0

USB Byte Counter High

(EP X)

UBYCTHX

UFNUML

UFNUMH

E3h

BAh

BBh

-

BYCT10

FNUM2

BYCT9

FNUM1

FNUM9

BYCT8

FNUM0

FNUM8

USB Frame Number

Low

FNUM7

-

FNUM6

-

FNUM5

CRCOK

FNUM4

CRCERR

FNUM3

-

USB Frame Number

High

FNUM10

Table 7-14. Other SFR’s

Mnemonic

Add

87h

8Eh

A2h

8Fh

AFh

F1h

Name

7

6

5

-

4

3

2

GF0

XRS2

-

1

0

IDL

PCON

Power Control

Auxiliary Register 0

Auxiliary Register 1

Clock Control 0

Clock Control 1

LED Control

SMOD1

SMOD0

POF

GF1

XRS1

GF3

T2X2

-

PD

AUXR

DPU

-

M0

-

EXTRAM

A0

AUXR1

-

WDX2

-

ENBOOT

-

SIX2

-

T0X2

-

DPS

X2

CKCON0

CKCON1

LEDCON

TWIX2

-

PCAX2

-

T1X2

-

SPIX2

LED3

LED2

LED1

LED0

24

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

8. Program/Code Memory

The AT83C5134/35/36 implement 16 or 32 Kbytes of on-chip program/code memory. Figure 8-1

shows the split of internal and external program/code memory spaces depending on the

product.

Figure 8-1. Program/Code Memory Organization

FFFFh

32 Kbytes

External Code

48 Kbytes

External Code

8000h

7FFFh

4000h

32 Kbytes

3FFFh

ROM

16 Kbytes

ROM

0000h

AT83C5135

AT83C5136

Note:

If the program executes exclusively from on-chip code memory (not from external memory),

beware of executing code from the upper byte of on-chip memory and thereby disrupting I/O Ports

0 and 2 due to external prefetch. Fetching code constant from this location does not affect Ports 0

and 2.

8.1

External Code Memory Access

8.1.1

Memory Interface

The external memory interface comprises the external bus (Port 0 and Port 2) as well as the bus

control signals (PSEN, and ALE).

Figure 8-2 shows the structure of the external address bus. P0 carries address A7:0 while P2

carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 8-1 describes the exter-

nal memory interface signals.

Figure 8-2. External Code Memory Interface Structure

Flash

EPROM

AT89C5131

A15:8

P2

ALE

P0

A15:8

A7:0

AD7:0

Latch A7:0

D7:0

OE

PSEN

25

7683C–USB–11/07

Table 8-1.

External Data Memory Interface Signals

Signal

Name

Alternate

Function

Type Description

Address Lines

Upper address lines for the external bus.

A15:8

AD7:0

ALE

O

P2.7:0

P0.7:0

-

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

I/O

Address Latch Enable

O

ALE signals indicates that valid address information are available on lines AD7:0.

Program Store Enable Output

This signal is active low during external code fetch or external code read (MOVC

instruction).

PSEN

O

-

8.1.2

External Bus Cycles

This section describes the bus cycles the AT83C5134/35/36 executes to fetch code (see

Figure 8-3) in the external program/code memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock peri-

ods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2

mode (see the clock Section).

For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and

do not provide precise timing information.

Figure 8-3. External Code Fetch Waveforms

CPU Clock

ALE

PSEN

D7:0

PCH

PCL

D7:0

PCL

D7:0

P0

P2

PCH

26

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

9. AT89C5131 ROM

9.1

ROM Structure

The AT89C5131 ROM memory is divided in two different arrays:

• the code array: 16-32 Kbytes.

• the configuration byte:1 byte.

9.1.1

Hardware Configuration Byte

The configuration byte sets the starting microcontroller options and the security levels.

The starting default options are X1 mode, Oscillator A.

Table 9-1.

Hardware Security Byte (HSB)

HSB (S:EFh)

Power configuration Register

7

-

6

-

5

4

3

-

2

-

1

0

OSCON1

OSCON0

LB1

LB0

Bit

Number

Mnemonic

Description

Reserved

7

6

-

Oscillator Control Bits

These two bits are used to control the oscillator in order to reduce consumption.

OSCON1OSCON0 Description

5-4

OSCON1-0

1

0

1 The oscillator is configured to run from 0 to 32 MHz

0 The oscillator is configured to run from 0 to 16 MHz

1 The oscillator is configured to run from 0 to 8 MHz

0 This configuration shouldn’t be set

3

2

-

Reserved

User Program Lock Bits

See Table 9-2 on page 28

1-0

LB1-0

HSB = xxxx xx11b

9.2

ROM Lock System

The program Lock system, when programmed, protects the on-chip program against software

piracy.

27

7683C–USB–11/07

9.2.1

Program ROM lock Bits

The lock bits when programmed according to Table 9-2 will provide different level of protection

for the on-chip code and data.

Table 9-2. Program Lock bits

Program Lock Bits

Protection Description

Security

level

LB1

U

LB0

U

1

3

No program lock feature enabled.

P

U

Reading ROM data from programmer is disabled.

U: unprogrammed

P: programmed

28

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

10. Stacked EEPROM

10.1 Overview

The AT83C5134/35/36 features a stacked 2-wire serial data EEPROM. The data EEPROM

allows to save from 512 Byte for AT24C04 version up to 32 Kbytes for AT24C256 version. The

EEPROM is internally connected to the microcontroller on SDA and SCL pins.

10.2 Protocol

In order to access this memory, it is necessary to use software subroutines according to the

AT24Cxx datasheet. Nevertheless, because the internal pull-up resistors of the

AT83C5134/35/36 is quite high (around 100KΩ), the protocol should be slowed in order to be

sure that the SDA pin can rise to the high level before reading it.

Another solution to keep the access to the EEPROM in specification is to work with a software

pull-up.

Using a software pull-up, consists of forcing a low level at the output pin of the microcontroller

before configuring it as an input (high level).

The C51 the ports are “quasi-bidirectional” ports. It means that the ports can be configured as

output low or as input high. In case a port is configured as an output low, it can sink a current

and all internal pull-ups are disconnected. In case a port is configured as an input high, it is

pulled up with a strong pull-up (a few hundreds Ohms resistor) for 2 clock periods. Then, if the

port is externally connected to a low level, it is only kept high with a weak pull up (around

100KΩ), and if not, the high level is latched high thanks to a medium pull (around 10kΩ).

Thus, when the port is configured as an input, and when this input has been read at a low level,

there is a pull-up of around 100KΩ, which is quite high, to quickly load the SDA capacitance. So

in order to help the reading of a high level just after the reading of a low level, it is possible to

force a transition of the SDA port from an input state (1), to an output low state (0), followed by a

new transition from this output low state to input state; In this case, the high pull-up has been

replaced with a low pull-up which warranties a good reading of the data.

29

7683C–USB–11/07

11. On-chip Expanded RAM (ERAM)

The AT83C5134/35/36 provides additional Bytes of random access memory (RAM) space for

increased data parameters handling and high level language usage.

AT83C5134/35/36 devices have an expanded RAM in the external data space; maximum size

and location are described in Table 11-1.

Table 11-1. Description of Expanded RAM

Address

Part Number

ERAM Size

Start

End

AT83C5134/35/36

1024

00h

3FFh

The AT83C5134/35/36 has on-chip data memory which is mapped into the following four sepa-

rate segments.

1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly

addressable.

2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly address-

able only.

4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the

EXTRAM bit cleared in the AUXR register (see Table 11-1)

The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128

bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same

address space as the SFR. That means they have the same address, but are physically sepa-

rate from SFR space.

Figure 11-1. Internal and External Data Memory Address

0FFh or 3FFh(*)

0FFh

0FFFFh

Upper

128 bytes

Internal

Special

Function

Register

External

Data

Memory

RAM

indirect accesses

direct accesses

80h

7Fh

80h

ERAM

Lower

128 bytes

Internal

RAM

direct or indirect

accesses

00FFh up to 03FFh (*)

0000

00

(*) Depends on XRS1..0

When an instruction accesses an internal location above address 7Fh, the CPU knows whether

the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used

in the instruction.

30

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data,

accesses the SFR at location 0A0h (which is P2).

• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For

example: MOV atR0, # data where R0 contains 0A0h, accesses the data byte at address

0A0h, rather than P2 (whose address is 0A0h).

• The ERAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and

MOVX instructions. This part of memory which is physically located on-chip, logically

occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a

part of the available ERAM as explained in Table 11-1. This can be useful if external

peripherals are mapped at addresses already used by the internal ERAM.

• With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in

combination with any of the registers R0, R1 of the selected bank or DPTR. An access to

ERAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM =

0, MOVX atR0, # data where R0 contains 0A0H, accesses the ERAM at address 0A0H rather

than external memory. An access to external data memory locations higher than the

accessible size of the ERAM will be performed with the MOVX DPTR instructions in the same

way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7

as write and read timing signals. Accesses to ERAM above 0FFH can only be done by the

use of DPTR.

• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.

MOVX at Ri will provide an eight-bit address multiplexed with data on Port0 and any output

port pins can be used to output higher order address bits. This is to provide the external

paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-

order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight

address bits (DPL) with data. MOVX at Ri and MOVX @DPTR will generate either read or

write signals on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)

internal data memory. The stack may not be located in the ERAM.

The M0 bit allows to stretch the ERAM timings; if M0 is set, the read and write pulses are

extended from 6 to 30 clock periods. This is useful to access external slow peripherals.

Table 11-2. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

6

5

4

3

2

1

0

DPU

-

M0

-

XRS1

XRS0

EXTRAM

AO

Bit

Number

Mnemonic

Description

Disable Weak Pull Up

7

6

DPU

-

Cleared to enabled weak pull up on standard Ports.

Set to disable weak pull up on standard Ports.

Reserved

The value read from this bit is indeterminate. Do not set this bit

Pulse length

Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods

(default).

5

M0

Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.

31

7683C–USB–11/07

Bit

Number

Mnemonic

Description

Reserved

4

3

-

The value read from this bit is indeterminate. Do not set this bit

XRS1

ERAM Size

XRS1XRS0

ERAM size

0

1

0

1

0

1

256 bytes

512 bytes

2

XRS0

768 bytes

1024 bytes (default)

EXTRAM bit

Cleared to access internal ERAM using MOVX at Ri at DPTR.

Set to access external memory.

1

0

EXTRAM

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2

mode is used) (default).

AO

Set, ALE is active only when a MOVX or MOVC instruction is used.

Reset Value = 0X0X 1100b

Not bit addressable

32

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

12. Timer 2

The Timer 2 in the AT83C5134/35/36 is the standard C52 Timer 2. It is a 16-bit timer/counter:

the count is maintained by two cascaded eight-bit timer registers, TH2 and TL2. It is controlled

by T2CON (Table 12-1) and T2MOD (Table 12-2) registers. Timer 2 operation is similar to Timer

0 and Timer 1. C/T2 selects F_OSC/12 (timer operation) or external pin T2 (counter operation) as

the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 has 3 operating modes: capture, auto reload and Baud Rate Generator. These modes

are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).

Refer to the Atmel 8-bit microcontroller hardware documentation for the description of Capture

and Baud Rate Generator Modes.

Timer 2 includes the following enhancements:

• Auto-reload mode with up or down counter

• Programmable Clock-output

12.1 Auto-reload Mode

The Auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic

reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel 8-bit

microcontroller hardware description). If DCEN bit is set, Timer 2 acts as an Up/down

timer/counter as shown in Figure 12-1. In this mode the T2EX pin controls the direction of count.

When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag

and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and

RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer

registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The under-

flow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the

count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.

33

7683C–USB–11/07

Figure 12-1. Auto-reload Mode Up/Down Counter (DCEN = 1)

F_{CLK PERIPH}

: 6

0

1

T2

TR2

C/T2

T2CON

(DOWN COUNTING RELOAD VALUE) T2EX:

if DCEN = 1, 1 = UP

FFh

(8-bit)

FFh

(8-bit)

if DCEN = 1, 0 = DOWN

if DCEN = 0, up counting

T2CON

EXF2

TOGGLE

TL2

(8-bit)

TH2

(8-bit)

Timer 2

INTERRUPT

TF2

T2CON

RCAP2L

(8-bit)

RCAP2H

(8-bit)

(UP COUNTING RELOAD VALUE)

12.2 Programmable Clock Output

In the Clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator

(See Figure 12-2). The input clock increments TL2 at frequency F_{CLK PERIPH}/2. The timer repeat-

edly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L

registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate inter-

rupts. The following formula gives the Clock-out frequency as a function of the system oscillator

frequency and the value in the RCAP2H and RCAP2L registers

F_CLKPERIPH

Clock – OutFrequency = ----------------------------------------------------------------------------------------

4 × (65536 – RCAP2H ⁄ RCAP2L)

For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz

(F_{CLK PERIPH}/2¹⁶⁾to 4 MHz (F_{CLK PERIPH}/4). The generated clock signal is brought out to T2 pin

(P1.0).

Timer 2 is programmed for the Clock-out mode as follows:

• Set T2OE bit in T2MOD register.

• Clear C/T2 bit in T2CON register.

• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value

or a different one depending on the application.

• To start the timer, set TR2 run control bit in T2CON register.

34

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For

this configuration, the baud rates and clock frequencies are not independent since both func-

tions use the values in the RCAP2H and RCAP2L registers.

Figure 12-2. Clock-out Mode C/T2 = 0

: 6

F_{CLK PERIPH}

TR2

T2CON

TH2

(8-bit)

TL2

(8-bit)

OVERFLOW

RCAP2H

(8-bit)

RCAP2L

(8-bit)

Toggle

T2

Q

D

T2OE

T2MOD

Timer 2

INTERRUPT

T2EX

EXF2

T2CON

EXEN2

T2CON

35

7683C–USB–11/07

Table 12-1. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Mnemonic

Description

Timer 2 overflow Flag

7

6

TF2

Must be cleared by software.

Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2 = 1.

When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt

is enabled.

EXF2

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter

mode (DCEN = 1).

Receive Clock bit

Cleared to use Timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

5

4

RCLK

TCLK

Transmit Clock bit

Cleared to use Timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for Timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is detected, if

Timer 2 is not used to clock the serial port.

3

2

1

EXEN2

TR2

Timer 2 Run control bit

Cleared to turn off Timer 2.

Set to turn on Timer 2.

Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: F_{CLK PERIPH}).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for

clock out mode.

C/T2#

Timer 2 Capture/Reload bit

If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to Auto-reload on

Timer 2 overflow.

0

CP/RL2#

Cleared to Auto-reload on Timer 2 overflows or negative transitions on T2EX pin if

EXEN2 = 1.

Set to capture on negative transitions on T2EX pin if EXEN2 = 1.

Reset Value = 0000 0000b

Bit addressable

36

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 12-2. T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

7

6

5

4

3

2

-

1

0

-

T2OE

DCEN

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable bit

1

0

T2OE

DCEN

Cleared to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

Down Counter Enable bit

Cleared to disable Timer 2 as up/down counter.

Set to enable Timer 2 as up/down counter.

Reset Value = xxxx xx00b

Not bit addressable

37

7683C–USB–11/07

13. Programmable Counter Array (PCA)

The PCA provides more timing capabilities with less CPU intervention than the standard

timer/counters. Its advantages include reduced software overhead and improved accuracy. The

PCA consists of a dedicated timer/counter which serves as the time base for an array of five

compare/capture modules. Its clock input can be programmed to count any one of the following

signals:

• Peripheral clock frequency (F_{CLK PERIPH}

• Timer 0 overflow

)

÷

6

2

• External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

• rising and/or falling edge capture,

• software timer

• high-speed output, or

• pulse width modulator

Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog Timer",

page 48).

When the compare/capture modules are programmed in the capture mode, software timer, or

high speed output mode, an interrupt can be generated when the module executes its function.

All five modules plus the PCA timer overflow share one interrupt vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins

are listed below. If the port pin is not used for the PCA, it can still be used for standard I/O.

PCA Component

16-bit Counter

16-bit Module 0

16-bit Module 1

16-bit Module 2

16-bit Module 3

16-bit Module 4

External I/O Pin

P1.2/ECI

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

The PCA timer is a common time base for all five modules (see Figure 13-1). The timer count

source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 13-1) and can

be programmed to run at:

• 1/6 the peripheral clock frequency (F_{CLK PERIPH}

• 1/2 the peripheral clock frequency (F_{CLK PERIPH}

• The Timer 0 overflow

)

.

)

• The input on the ECI pin (P1.2)

38

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Figure 13-1. PCA Timer/Counter

To PCA

modules

F

_{CLK PERIPH}/6

overflow

It

F_{CLK PERIPH}/2

T0 OVF

P1.2

CH

CL

16 Bit Up Counter

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Idle

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

Table 13-1. CMOD Register

CMOD - PCA Counter Mode Register (D9h)

7

6

5

4

3

2

1

0

CIDL

WDTE

-

CPS1

CPS0

ECF

Bit

Number

Mnemonic

Description

Counter Idle Control

7

6

CIDL

Cleared to program the PCA Counter to continue functioning during idle Mode.

Set to program PCA to be gated off during idle.

Watchdog Timer Enable

WDTE

Cleared to disable Watchdog Timer function on PCA Module 4.

Set to enable Watchdog Timer function on PCA Module 4.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5

4

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

CPS1

PCA Count Pulse Select

CPS1CPS0

0

Selected PCA input

Internal clock f_{CLK PERIPH}/6

0

1

0

1

Internal clock f_{CLK PERIPH}/2

Timer 0 Overflow

1

0

CPS0

ECF

External clock at ECI/P1.2 pin (max rate = f_{CLK PERIPH}/ 4)

PCA Enable Counter Overflow Interrupt

Cleared to disable CF bit in CCON to inhibit an interrupt.

Set to enable CF bit in CCON to generate an interrupt.

39

7683C–USB–11/07

Reset Value = 00XX X000b

Not bit addressable

The CMOD register includes three additional bits associated with the PCA (See Figure 13-1 and

Table 13-1).

• The CIDL bit allows the PCA to stop during idle mode.

• The WDTE bit enables or disables the watchdog function on module 4.

• The ECF bit when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR)

to be set when the PCA timer overflows.

The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF)

and each module (see Table 13-2).

• Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this

bit.

• Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be

generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by

software.

• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and

are set by hardware when either a match or a capture occurs. These flags can only be

cleared by software.

Table 13-2. CCON Register

CCON - PCA Counter Control Register (D8h)

7

6

5

4

3

2

1

0

CF

CR

–

CCF4

CCF3

CCF2

CCF1

CCF0

Bit

Number Mnemonic Description

PCA Counter Overflow flag

7

CF

Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set.

CF may be set by either hardware or software but can only be cleared by software.

PCA Counter Run control bit

6

5

4

CR

–

Must be cleared by software to turn the PCA counter off.

Set by software to turn the PCA counter on.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

PCA Module 4 interrupt flag

CCF4

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 3 interrupt flag

3

2

CCF3

CCF2

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 2 interrupt flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

40

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Bit

Number Mnemonic Description

PCA Module 1 Interrupt Flag

1

0

CCF1

CCF0

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 0 Interrupt Flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

Reset Value = 000X 0000b

Not bit addressable

The watchdog timer function is implemented in module 4 (See Figure 13-4).

The PCA interrupt system is shown in Figure 13-2.

Figure 13-2. PCA Interrupt System

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

PCA Timer/Counter

Module 0

Module 1

Module 2

Module 3

To Interrupt

priority decoder

Module 4

CMOD.0

IE.6

EC

IE.7

EA

CCAPMn.0

ECCFn

ECF

PCA Modules: each one of the five compare/capture modules has six possible functions. It can

perform:

• 16-bit capture, positive-edge triggered

• 16-bit capture, negative-edge triggered

• 16-bit capture, both positive and negative-edge triggered

• 16-bit Software Timer

• 16-bit High-speed Output

• 8-bit Pulse Width Modulator

In addition, module 4 can be used as a Watchdog Timer.

Each module in the PCA has a special function register associated with it. These registers are:

CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Table 13-3). The registers contain the

bits that control the mode that each module will operate in.

41

7683C–USB–11/07

• The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the

CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the

associated module.

• PWM (CCAPMn.1) enables the pulse width modulation mode.

• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to

toggle when there is a match between the PCA counter and the module's capture/compare

register.

• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be

set when there is a match between the PCA counter and the module's capture/compare

register.

• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a

capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit

enables the positive edge. If both bits are set both edges will be enabled and a capture will

occur for either transition.

• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.

Table 13-4 shows the CCAPMn settings for the various PCA functions.

Table 13-3. CCAPMn Registers (n = 0-4)

CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)

CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)

CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)

CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)

CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)

7

-

6

5

4

3

2

1

0

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

Bit

Number

Mnemonic

Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

Enable Comparator

ECOMn

Cleared to disable the comparator function.

Set to enable the comparator function.

Capture Positive

5

4

CAPPn

CAPNn

Cleared to disable positive edge capture.

Set to enable positive edge capture.

Capture Negative

Cleared to disable negative edge capture.

Set to enable negative edge capture.

Match

When MATn = 1, a match of the PCA counter with this module's compare/capture

register causes the

3

2

MATn

TOGn

CCFn bit in CCON to be set, flagging an interrupt.

Toggle

When TOGn = 1, a match of the PCA counter with this module's compare/capture

register causes the CEXn pin to toggle.

42

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Bit

Number

Mnemonic

Description

Pulse Width Modulation Mode

1

0

PWMn

ECCFn

Cleared to disable the CEXn pin to be used as a pulse width modulated output.

Set to enable the CEXn pin to be used as a pulse width modulated output.

Enable CCF Interrupt

Cleared to disable compare/capture flag CCFn in the CCON register to generate an

interrupt.

Set to enable compare/capture flag CCFn in the CCON register to generate an

interrupt.

Reset Value = X000 0000b

Not bit addressable

Table 13-4. PCA Module Modes (CCAPMn Registers)

ECOMn

CAPPn

CAPNn

MATn TOGn PWMm ECCFn Module Function

0

No Operation

16-bit capture by a positive-edge

trigger on CEXn

X

1

0

1

0

1

0

X

16-bit capture by a negative trigger

on CEXn

0

1

0

X

16-bit capture by a transition on

CEXn

16-bit Software Timer/Compare

mode.

1

0

1

0

1

0

1

0

X

0

16-bit High Speed Output

8-bit PWM

X

Watchdog Timer (module 4 only)

There are two additional registers associated with each of the PCA modules. They are CCAPnH

and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a

compare should occur. When a module is used in the PWM mode these registers are used to

control the duty cycle of the output (see Table 13-5 and Table 13-6)

43

7683C–USB–11/07

Table 13-5. CCAPnH Registers (n = 0-4)

CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)

CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)

CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)

CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)

CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic

Description

PCA Module n Compare/Capture Control

7 - 0

-

CCAPnH Value

Reset Value = XXXX XXXXb

Not bit addressable

Table 13-6. CCAPnL Registers (n = 0-4)

CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)

CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)

CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)

CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)

CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic

Description

PCA Module n Compare/Capture Control

CCAPnL Value

7 - 0

-

Reset Value = XXXX XXXXb

Not bit addressable

Table 13-7. CH Register

CH - PCA Counter Register High (0F9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic

Description

PCA counter

CH Value

7 - 0

-

Reset Value = 0000 0000b

Not bit addressable

44

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 13-8. CL Register

CL - PCA Counter Register Low (0E9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic

Description

PCA Counter

CL Value

7 - 0

-

Reset Value = 0000 0000b

Not bit addressable

13.1 PCA Capture Mode

To use one of the PCA modules in the capture mode either one or both of the CCAPM bits

CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1)

is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of

the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and

CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn

SFR are set then an interrupt will be generated (see Figure 13-3).

Figure 13-3. PCA Capture Mode

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

PCA IT

PCA Counter/Timer

Cex.n

CH

CL

Capture

CCAPnH

CCAPnL

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

13.2 16-bit Software Timer/Compare Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT bits in

the modules CCAPMn register. The PCA timer will be compared to the module's capture regis-

ters and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn

(CCAPMn SFR) bits for the module are both set (see Figure 13-4).

45

7683C–USB–11/07

Figure 13-4. PCA Compare Mode and PCA Watchdog Timer

CCON

0xD8

CCF4

CCF3 CCF2 CCF1 CCF0

CF

CR

Write to

CCAPnL Reset

PCA IT

Write to

CCAPnH

CCAPnL

Enable

1

0

Match

16-bit Comparator

RESET⁽¹⁾

CH

CL

PCA Counter/Timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Note:

1. Only for Module 4

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other-

wise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur

while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user

software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be

controlled by accessing to CCAPMn register.

13.3 High Speed Output Mode

In this mode, the CEX output (on port 1) associated with the PCA module will toggle each time a

match occurs between the PCA counter and the module's capture registers. To activate this

mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (see

Figure 13-5).

A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

46

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Figure 13-5. PCA High-speed Output Mode

CCON

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

0xD8

Write to

CCAPnL

Reset

PCA IT

Write to

CCAPnH

CCAPnL

0

Enable

1

Match

16-bit Comparator

CEXn

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other-

wise an unwanted match could happen.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur

while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user

software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be

controlled by accessing to CCAPMn register.

13.4 Pulse Width Modulator Mode

All of the PCA modules can be used as PWM outputs. Figure 13-6 shows the PWM function.

The frequency of the output depends on the source for the PCA timer. All of the modules will

have the same frequency of output because they all share the PCA timer. The duty cycle of each

module is independently variable using the module's capture register CCAPLn. When the value

of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low,

when it is equal to or greater than the output will be high. When CL overflows from FF to 00,

CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches.

The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM

mode.

47

7683C–USB–11/07

Figure 13-6. PCA PWM Mode

CCAPnH

Overflow

CCAPnL

“0”

“1”

CEXn

Enable

<

≥

8-bit Comparator

CL

PCA Counter/Timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

13.5 PCA Watchdog Timer

An on-board watchdog timer is available with the PCA to improve the reliability of the system

without increasing chip count. Watchdog timers are useful for systems that are susceptible to

noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be

programmed as a watchdog. However, this module can still be used for other modes if the

watchdog is not needed. Figure 13-4 shows a diagram of how the watchdog works. The user

pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit

value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be

generated. This will not cause the RST pin to be driven low.

In order to hold off the reset, the user has three options:

1. Periodically change the compare value so it will never match the PCA timer

2. Periodically change the PCA timer value so it will never match the compare values, or

3. Disable the watchdog by clearing the WDTE bit before a match occurs and then re-

enable it

The first two options are more reliable because the watchdog timer is never disabled as in option

#3. If the program counter ever goes astray, a match will eventually occur and cause an internal

reset. The second option is also not recommended if other PCA modules are being used.

Remember, the PCA timer is the time base for all modules; changing the time base for other

modules would not be a good idea. Thus, in most applications the first solution is the best option.

This watchdog timer won’t generate a reset out on the reset pin.

48

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

14. Serial I/O Port

The serial I/O port in the AT83C5134/35/36 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as an Uni-

versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2

and 3). Asynchronous transmission and reception can occur simultaneously and at different

baud rates.

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

14.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To

enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 14-

1).

Figure 14-1. Framing Error Block Diagram

SM0/FE SM1

SM2 REN

TB8

RB8

TI

RI

SCON (98h)

Set FE Bit if Stop Bit is 0 (framing error) (SMOD0 = 1

SM0 to UART Mode Control (SMOD0 = 0)

PCON (87h)

SMOD1 SMOD0

-

POF GF1

GF0

PD

IDL

To UART Framing Error Control

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.

An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by

two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table

14-1) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set, only soft-

ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear

FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure

14-2 and Figure 14-3).

Figure 14-2. UART Timings in Mode 1

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Start

Bit

Data Byte

Stop

Bit

RI

SMOD0 = X

FE

SMOD0 = 1

49

7683C–USB–11/07

Figure 14-3. UART Timings in Modes 2 and 3

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start

Bit

Data Byte

Ninth Stop

Bit

RI

SMOD0 = 0

RI

SMOD0 = 1

FE

SMOD0 = 1

14.2 Automatic Address Recognition

The automatic address recognition feature is enabled when the multiprocessor communication

feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor commu-

nication feature by allowing the serial port to examine the address of each incoming command

frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON

register to generate an interrupt. This ensures that the CPU is not interrupted by command

frames addressed to other devices.

If desired, you may enable the automatic address recognition feature in mode 1. In this configu-

ration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received

command frame address matches the device’s address and is terminated by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and a broad-

cast address.

Note:

The multiprocessor communication and automatic address recognition features cannot be

enabled in mode 0 (i.e., setting SM2 bit in SCON register in mode 0 has no effect).

14.2.1

Given Address

Each device has an individual address that is specified in SADDR register; the SADEN register

is a mask byte that contains don’t care bits (defined by zeros) to form the device’s given

address. The don’t care bits provide the flexibility to address one or more slaves at a time. The

following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111 1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

50

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Slave C:SADDR1111 0011b

SADEN1111 1101b

Given1111 00X1b

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate

with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).

For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves

B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111

0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1

clear, and bit 2 clear (e.g. 1111 0001b).

14.2.2

Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers with

zeros defined as don’t care bits, e.g.:

SADDR0101 0110b

SADEN1111 1100b

Broadcast = SADDR OR SADEN1111 111Xb

The use of don’t care bits provides flexibility in defining the broadcast address, in most applica-

tions, a broadcast address is FFh. The following is an example of using broadcast addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Broadcast1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Broadcast1111 1X11B,

Slave C:SADDR = 1111 0011b

SADEN1111 1101b

Broadcast1111 1111b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of

the slaves, the master must send an address FFh. To communicate with slaves A and B, but not

slave C, the master can send and address FBh.

14.2.3

Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast

addresses are XXXX XXXXb(all don’t care bits). This ensures that the serial port will reply to any

address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not

support automatic address recognition.

51

7683C–USB–11/07

SADEN - Slave Address Mask Register (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

SADDR - Slave Address Register (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

14.3 Baud Rate Selection for UART for Mode 1 and 3

The Baud Rate Generator for transmit and receive clocks can be selected separately via the

T2CON and BDRCON registers.

Figure 14-4. Baud Rate Selection

TIMER1

TIMER_BRG_RX

0

1

0

1

TIMER2

/ 16

Rx Clock

RCLK

RBCK

INT_BRG

TIMER1

TIMER2

TIMER_BRG_TX

0

1

0

1

/ 16

Tx Clock

TCLK

TBCK

INT_BRG

52

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

14.3.1

Baud Rate Selection Table for UART

TCLK

RCLK

TBCK

RBCK

Clock Source

UART Rx

(T2CON)

(BDRCON)

UART Tx

0

1

0

1

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

Timer 1

Timer 2

Timer 1

Timer 2

INT_BRG

Timer 1

Timer 2

INT_BRG

Timer 2

INT_BRG

14.3.2

Internal Baud Rate Generator (BRG)

When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG

overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON

register and the value of the SMOD1 bit in PCON register.

Figure 14-5. Internal Baud Rate

auto reload counter

overflow

BRG

/2

Peripheral Clock

0

1

/6

0

1

INT_BRG

BRL

SPD

SMOD1

BRR

• The baud rate for UART is token by formula:

SMOD1

2

x

F

CLK PERIPH

Baud_Rate =

(1-SPD)

2 x 6

x 16 x [256 - (BRL)]

2^SMOD1x FCLK PERIPH

(BRL) = 256

-

(1-SPD)

2 x 6

x 16 x Baud_Rate

Table 14-1. SCON Register – SCON Serial Control Register (98h)

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

53

7683C–USB–11/07

Bit

Number

Mnemonic

Description

Framing Error bit (SMOD0 = 1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

FE

SMOD0 must be set to enable access to the FE bit

7

Serial port Mode bit 0

Refer to SM1 for serial port mode selection.

SM0

SMOD0 must be cleared to enable access to the SM0 bit

Serial port Mode bit 1

SM0 SM1

Mode

Description Baud Rate

Shift Register F_{CPU PERIPH}/6

0

1

0

1

0

1

2

6

5

SM1

SM2

8-bit UART

9-bit UART

Variable

F_{CPU PERIPH/}32 or/16

1

3

9-bit UART

Variable

Serial port Mode 2 bit/Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3, and eventually

mode 1. This bit should be cleared in mode 0.

Reception Enable bit

Clear to disable serial reception.

Set to enable serial reception.

4

3

REN

TB8

Transmitter Bit 8/Ninth bit to Transmit in Modes 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8/Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

2

1

0

RB8

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit

in the other modes.

TI

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 14-2. and Figure 14-

3. in the other modes.

RI

Reset Value = 0000 0000b

Bit addressable

54

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Example of computed value when X2 = 1, SMOD1 = 1, SPD = 1

F_OSC= 16.384 MHz

Baud Rates

F_OSC= 24 MHz

BRL

247

238

229

220

203

149

43

Error (%)

BRL

243

230

217

204

178

100

-

Error (%)

0.16

-

115200

57600

38400

28800

19200

9600

1.23

0.63

0.31

4800

1.23

Example of computed value when X2 = 0, SMOD1 = 0, SPD = 0

F_OSC= 16.384 MHz

F_OSC= 24 MHz

Baud Rates

4800

BRL

Error (%)

BRL

243

230

202

152

Error (%)

0.16

247

238

220

185

1.23

0.16

2400

0.16

1200

3.55

600

0.16

The baud rate generator can be used for mode 1 or 3 (refer to Figure 14-4.), but also for mode 0

for UART, thanks to the bit SRC located in BDRCON register (Table 14-4.)

14.4 UART Registers

SADEN - Slave Address Mask Register for UART (B9h)

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

–

Reset Value = 0000 0000b

SADDR - Slave Address Register for UART (A9h)

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

–

Reset Value = 0000 0000b

SBUF - Serial Buffer Register for UART (99h)

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

–

Reset Value = XXXX XXXXb

55

7683C–USB–11/07

BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

–

Reset Value = 0000 0000b

Table 14-2. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Mnemonic Description

Timer 2 overflow Flag

7

6

TF2

Must be cleared by software.

Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2

= 1.

When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is

enabled.

EXF2

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode

(DCEN = 1)

Receive Clock bit for UART

Cleared to use Timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

5

4

RCLK

TCLK

Transmit Clock bit for UART

Cleared to use Timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for Timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is detected, if

Timer 2 is not used to clock the serial port.

3

2

1

EXEN2

TR2

Timer 2 Run control bit

Cleared to turn off Timer 2.

Set to turn on Timer 2.

Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: F_{CLK PERIPH}).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock

out mode.

C/T2#

Timer 2 Capture/Reload bit

If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to Auto-reload on Timer

2 overflow.

Cleared to Auto-reload on Timer 2 overflows or negative transitions on T2EX pin if

EXEN2 = 1.

0

CP/RL2#

Set to capture on negative transitions on T2EX pin if EXEN2 = 1.

Reset Value = 0000 0000b

Bit addressable

56

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 14-3. PCON Register

PCON - Power Control Register (87h)

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Serial port Mode bit 1 for UART

Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0 for UART

7

6

5

SMOD1

SMOD0

-

Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Cleared to recognize next reset type.

4

POF

Set by hardware when V_CCrises from 0 to its nominal voltage. Can also be set by

software.

General-purpose Flag

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

3

2

1

0

GF1

GF0

PD

General-purpose Flag

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

Power-down Mode Bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle Mode Bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00x1 0000b

Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect

the value of this bit.

57

7683C–USB–11/07

Table 14-4. BDRCON Register

BDRCON - Baud Rate Control Register (9Bh)

7

-

6

-

5

-

4

3

2

1

0

BRR

TBCK

RBCK

SPD

SRC

Bit

Number

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit

7

6

5

-

Reserved

The value read from this bit is indeterminate. Do not set this bit

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Baud Rate Run Control bit

Cleared to stop the internal Baud Rate Generator.

Set to start the internal Baud Rate Generator.

4

3

2

1

0

BRR

TBCK

RBCK

SPD

Transmission Baud rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Reception Baud Rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Baud Rate Speed Control bit for UART

Cleared to select the SLOW Baud Rate Generator.

Set to select the FAST Baud Rate Generator.

Baud Rate Source select bit in Mode 0 for UART

SRC

Cleared to select F_OSC/12 as the Baud Rate Generator (F_{CLK PERIPH}/6 in X2 mode).

Set to select the internal Baud Rate Generator for UARTs in mode 0.

Reset Value = xxx0 0000b

Not bit addressable

58

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

15. Dual Data Pointer Register

The additional data pointer can be used to speed up code execution and reduce code size.

The dual DPTR structure is a way by which the chip will specify the address of an external data

memory location. There are two 16-bit DPTR registers that address the external memory, and a

single bit called DPS = AUXR1.0 (see Table 15-1) that allows the program code to switch

between them (see Figure 15-1).

Figure 15-1. Use of Dual Pointer

External Data Memory

7

0

DPS

DPTR1

DPTR0

AUXR1(A2H)

DPH(83H) DPL(82H)

Table 15-1. AUXR1 Register

AUXR1- Auxiliary Register 1(0A2h)

7

-

6

-

5

-

4

-

3

2

0

1

-

0

GF3

DPS

Bit

Number

Mnemonic

Description

Reserved

7

6

5

4

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3

2

GF3

0

This bit is a general-purpose user flag.

Always cleared.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1

0

-

Data Pointer Selection

Cleared to select DPTR0.

Set to select DPTR1.

DPS

Reset Value = xxxx x0x0b

Not bit addressable

a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

ASSEMBLY LANGUAGE

59

7683C–USB–11/07

; Block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; note: DPS exits opposite of entry state

; unless an extra INC AUXR1 is added

;

00A2 AUXR1 EQU 0A2H

;

0000 909000MOV DPTR,#SOURCE ; address of SOURCE

0003 05A2 INC AUXR1 ; switch data pointers

0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1 ; switch data pointers

000A E0 MOVX A,@DPTR ; get a byte from SOURCE

000B A3 INC DPTR ; increment SOURCE address

000C 05A2 INC AUXR1 ; switch data pointers

000E F0 MOVX @DPTR,A ; write the byte to DEST

000F A3 INC DPTR ; increment DEST address

0010 70F6JNZ LOOP ; check for 0 terminator

0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR.

However, note that the INC instruction does not directly force the DPS bit to a particular state,

but simply toggles it. In simple routines, such as the block move example, only the fact that DPS

is toggled in the proper sequence matters, not its actual value. In other words, the block move

routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc-

tion (INC AUXR1), the routine will exit with DPS in the opposite state.

60

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

16. Interrupt System

16.1 Overview

The AT83C5134/35/36 has a total of 11 interrupt vectors: two external interrupts (INT0 and

INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard

interrupt, USB interrupt and the PCA global interrupt. These interrupts are shown in Figure 16-1.

Figure 16-1. Interrupt Control System

High priority

interrupt

IPH, IPL

TCON.0

IT0

0

1

3

0

INT0

IE0

3

0

3

0

3

TF0

INT1

TF1

TCON.2

IT1

0

1

Interrupt

Polling

IE1

Sequence, Decreasing From

High-to-Low Priority

0

3

PCA IT

0

3

0

RI

TI

3

TF2

EXF2

0

3

KBD IT

0

3

TWI IT

SPI IT

0

3

0

3

0

USBINT

UEPINT

Low Priority

Interrupt

Individual Enable

Global Disable

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit

in the Interrupt Enable register (Table 16-2). This register also contains a global disable bit,

which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority levels by

setting or clearing a bit in the Interrupt Priority register (Table 16-3.) and in the Interrupt Priority

61

7683C–USB–11/07

High register (Table 16-4). Table 16-1. shows the bit values and priority levels associated with

each combination.

16.2 Registers

The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at

address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors

addresses are the same as standard C52 devices.

Table 16-1. Priority Level Bit Values

IPH.x

IPL.x

Interrupt Level Priority

0

1

0

1

0

1

0 (Lowest)

1

2

3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-

ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.

If two interrupt requests of different priority levels are received simultaneously, the request of

higher priority level is serviced. If interrupt requests of the same priority level are received simul-

taneously, an internal polling sequence determines which request is serviced. Thus within each

priority level there is a second priority structure determined by the polling sequence.

62

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 16-2. IEN0 Register

IEN0 - Interrupt Enable Register (A8h)

7

6

5

4

3

2

1

0

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

Bit

Number

Mnemonic

Description

Enable All interrupt bit

7

EA

EC

Cleared to disable all interrupts.

Set to enable all interrupts.

PCA interrupt enable bit

Cleared to disable.

6

5

4

3

2

1

0

Set to enable.

Timer 2 overflow interrupt Enable bit

Cleared to disable Timer 2 overflow interrupt.

Set to enable Timer 2 overflow interrupt.

ET2

ES

Serial port Enable bit

Cleared to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

Cleared to disable Timer 1 overflow interrupt.

Set to enable Timer 1 overflow interrupt.

ET1

EX1

ET0

EX0

External interrupt 1 Enable bit

Cleared to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Cleared to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

External interrupt 0 Enable bit

Cleared to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0000 0000b

Bit addressable

63

7683C–USB–11/07

Table 16-3. IPL0 Register

IPL0 - Interrupt Priority Register (B8h)

7

-

6

5

4

3

2

1

0

PPCL

PT2L

PSL

PT1L

PX1L

PT0L

PX0L

Bit

Number

Mnemonic

Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

PCA interrupt Priority bit

Refer to PPCH for priority level.

PPCL

PT2L

PSL

Timer 2 overflow interrupt Priority bit

Refer to PT2H for priority level.

Serial port Priority bit

Refer to PSH for priority level.

Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

PT1L

PX1L

PT0L

PX0L

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

Reset Value = x000 0000b

Bit addressable

64

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 16-4. IPH0 Register

IPH0 - Interrupt Priority High Register (B7h)

7

-

6

5

4

3

2

1

0

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Number

Mnemonic

Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

PCA interrupt Priority high bit.

PPCH PPCL Priority Level

0

1

0

1

0

1

Lowest

PPCH

Highest

Timer 2 overflow interrupt Priority High bit

PT2H PT2L Priority Level

0

1

0

1

0

1

Lowest

5

4

3

2

1

0

PT2H

Highest

Serial port Priority High bit

Priority Level

Lowest

PSH PSL

0

1

0

1

0

1

PSH

Highest

Timer 1 overflow interrupt Priority High bit

PT1H PT1L Priority Level

0

1

0

1

0

1

Lowest

PT1H

PX1H

PT0H

PX0H

Highest

External interrupt 1 Priority High bit

PX1H PX1L Priority Level

0

1

0

1

0

1

Lowest

Highest

Timer 0 overflow interrupt Priority High bit

PT0H PT0L Priority Level

0

1

0

1

0

1

Lowest

Highest

External interrupt 0 Priority High bit

PX0H PX0L Priority Level

0

1

0

1

0

1

Lowest

Highest

Reset Value = x000 0000b

Not bit addressable

65

7683C–USB–11/07

Table 16-5. IEN1 Register

IEN1 - Interrupt Enable Register (B1h)

7

-

6

5

-

4

-

3

-

2

1

0

EUSB

ESPI

ETWI

EKB

Bit

Number

Mnemonic

Description

7

-

Reserved

USB Interrupt Enable bit

6

EUSB

Cleared to disable USB interrupt.

Set to enable USB interrupt.

5

4

3

-

Reserved

SPI interrupt Enable bit

Cleared to disable SPI interrupt.

Set to enable SPI interrupt.

2

1

0

ESPI

ETWI

EKB

TWI interrupt Enable bit

Cleared to disable TWI interrupt.

Set to enable TWI interrupt.

Keyboard interrupt Enable bit

Cleared to disable keyboard interrupt.

Set to enable keyboard interrupt.

Reset Value = x0xx x000b

Not bit addressable

66

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 16-6. IPL1 Register

IPL1 - Interrupt Priority Register (B2h)

7

-

6

5

-

4

-

3

-

2

1

0

PUSBL

PSPIL

PTWIL

PKBDL

Bit

Number

Mnemonic

Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

USB Interrupt Priority bit

Refer to PUSBH for priority level.

PUSBL

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

SPI Interrupt Priority bit

Refer to PSPIH for priority level.

PSPIL

PTWIL

PKBL

TWI Interrupt Priority bit

Refer to PTWIH for priority level.

Keyboard Interrupt Priority bit

Refer to PKBH for priority level.

Reset Value = X0XX X000b

Not bit addressable

67

7683C–USB–11/07

Table 16-7. IPH1 Register

IPH1 - Interrupt Priority High Register (B3h)

7

-

6

5

-

4

-

3

-

2

1

0

PUSBH

PSPIH

PTWIH

PKBH

Bit

Number

Mnemonic

Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

USB Interrupt Priority High bit

PUSBHPUSBLPriority Level

0

1

0

1

0

1

Lowest

PUSBH

Highest

Reserved

5

4

3

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Priority High bit

PSPIHPSPIL Priority Level

0

1

0

1

0

1

Lowest

2

1

0

PSPIH

PTWIH

PKBH

Highest

TWI Interrupt Priority High bit

PTWIHPTWIL Priority Level

0

1

0

1

0

1

Lowest

Highest

Keyboard Interrupt Priority High bit

PKBH PKBL Priority Level

0

1

0

1

0

1

Lowest

Highest

Reset Value = X0XX X000b

Not bit addressable

68

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

16.3 Interrupt Sources and Vector Addresses

Table 16-8. Vector Table

Vector

Polling

Priority

Interrupt

Source

Interrupt

Request

Number

Address

0000h

0003h

000Bh

0013h

001Bh

0023h

002Bh

0033h

003Bh

0043h

004Bh

0053h

005Bh

0063h

006Bh

0073h

0

1

0

1

Reset

INT0

IE0

2

Timer 0

INT1

TF0

IE1

3

4

Timer 1

UART

Timer 2

PCA

IF1

5

6

RI+TI

6

7

TF2+EXF2

CF + CCFn (n = 0-4)

KBDIT

7

5

8

Keyboard

TWI

9

TWIIT

10

11

12

13

14

15

10

11

12

13

14

15

SPI

SPIIT

USB

UEPINT + USBINT

69

7683C–USB–11/07

17. Keyboard Interface

17.1 Introduction

The AT83C5134/35/36 implements a keyboard interface allowing the connection of a 8 x n

matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or

low level. These inputs are available as an alternate function of P1 and allow to exit from idle

and power down modes.

17.2 Description

The keyboard interface communicates with the C51 core through 3 special function registers:

KBLS, the Keyboard Level Selection register (Table 17-3), KBE, The Keyboard interrupt Enable

register (Table 17-2), and KBF, the Keyboard Flag register (Table 17-1).

17.2.1

Interrupt

The keyboard inputs are considered as 8 independent interrupt sources sharing the same inter-

rupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard

interrupt (see Figure 17-1). As detailed in Figure 17-2 each keyboard input has the capability to

detect a programmable level according to KBLS.x bit value. Level detection is then reported in

interrupt flags KBF.x that can be masked by software using KBE.x bits.

This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage of P1

inputs for other purpose.

Figure 17-1. Keyboard Interface Block Diagram

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

Input Circuitry

KBDIT

Keyboard Interface

Interrupt Request

KBD

IE1.0

Figure 17-2. Keyboard Input Circuitry

Vcc

0

1

P1:x

KBF.x

KBE.x

Internal Pull-up

KBLS.x

70

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

17.2.2

Power Reduction Mode

P1 inputs allow exit from idle and power down modes as detailed in section “Power-down Mode”.

17.3 Registers

Table 17-1. KBF Register

KBF - Keyboard Flag Register (9Eh)

7

6

5

4

3

2

1

0

KBF7

KBF6

KBF5

KBF4

KBF3

KBF2

KBF1

KBF0

Bit

Bit Number Mnemonic Description

Keyboard line 7 flag

Set by hardware when the Port line 7 detects a programmed level. It generates a

Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set.

Cleared by hardware when reading KBF SFR by software.

7

6

5

4

3

2

1

0

KBF7

KBF6

KBF5

KBF4

KBF3

KBF2

KBF1

KBF0

Keyboard line 6 flag

Set by hardware when the Port line 6 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.6 bit in KBIE register is set.

Cleared by hardware when reading KBF SFR by software.

Keyboard line 5 flag

Set by hardware when the Port line 5 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.5 bit in KBIE register is set.

Cleared by hardware when reading KBF SFR by software.

Keyboard line 4 flag

Set by hardware when the Port line 4 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.4 bit in KBIE register is set.

Cleared by hardware when reading KBF SFR by software.

Keyboard line 3 flag

Set by hardware when the Port line 3 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.3 bit in KBIE register is set.

Cleared by hardware when reading KBF SFR by software.

Keyboard line 2 flag

Set by hardware when the Port line 2 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.2 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 1 flag

Set by hardware when the Port line 1 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.1 bit in KBIE register is set.

Cleared by hardware when reading KBF SFR by software.

Keyboard line 0 flag

Set by hardware when the Port line 0 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.0 bit in KBIE register is set.

Cleared by hardware when reading KBF SFR by software.

Reset Value = 0000 0000b

71

7683C–USB–11/07

Table 17-2. KBE Register

KBE - Keyboard Input Enable Register (9Dh)

7

6

5

4

3

2

1

0

KBE7

KBE6

KBE5

KBE4

KBE3

KBE2

KBE1

KBE0

Bit

Number

Bit

Mnemonic Description

Keyboard line 7 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.7 bit in KBF register to generate an interrupt request.

7

6

5

4

3

2

1

0

KBE7

KBE6

KBE5

KBE4

KBE3

KBE2

KBE1

KBE0

Keyboard line 6 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.6 bit in KBF register to generate an interrupt request.

Keyboard line 5 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.5 bit in KBF register to generate an interrupt request.

Keyboard line 4 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.4 bit in KBF register to generate an interrupt request.

Keyboard line 3 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.3 bit in KBF register to generate an interrupt request.

Keyboard line 2 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.2 bit in KBF register to generate an interrupt request.

Keyboard line 1 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.1 bit in KBF register to generate an interrupt request.

Keyboard line 0 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.0 bit in KBF register to generate an interrupt request.

Reset Value = 0000 0000b

72

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 17-3. KBLS Register

KBLS-Keyboard Level Selector Register (9Ch)

7

6

5

4

3

2

1

0

KBLS7

KBLS6

KBLS5

KBLS4

KBLS3

KBLS2

KBLS1

KBLS0

Bit

Bit Number Mnemonic Description

Keyboard line 7 Level Selection bit

7

6

5

4

3

2

1

0

KBLS7

KBLS6

KBLS5

KBLS4

KBLS3

KBLS2

KBLS1

KBLS0

Cleared to enable a low level detection on Port line 7.

Set to enable a high level detection on Port line 7.

Keyboard line 6 Level Selection bit

Cleared to enable a low level detection on Port line 6.

Set to enable a high level detection on Port line 6.

Keyboard line 5 Level Selection bit

Cleared to enable a low level detection on Port line 5.

Set to enable a high level detection on Port line 5.

Keyboard line 4 Level Selection bit

Cleared to enable a low level detection on Port line 4.

Set to enable a high level detection on Port line 4.

Keyboard line 3 Level Selection bit

Cleared to enable a low level detection on Port line 3.

Set to enable a high level detection on Port line 3.

Keyboard line 2 Level Selection bit

Cleared to enable a low level detection on Port line 2.

Set to enable a high level detection on Port line 2.

Keyboard line 1 Level Selection bit

Cleared to enable a low level detection on Port line 1.

Set to enable a high level detection on Port line 1.

Keyboard line 0 Level Selection bit

Cleared to enable a low level detection on Port line 0.

Set to enable a high level detection on Port line 0.

Reset Value = 0000 0000b

73

7683C–USB–11/07

18. Programmable LED

AT83C5134/35/36 have up to 4 programmable LED current sources, configured by the register

LEDCON.

Table 18-1. LEDCON Register

LEDCON (S:F1h) LED Control Register

7

6

5

4

3

2

1

0

LED3

LED2

LED1

LED0

Bit

Bit Number Mnemonic

Description

Port LED3

Configuration

0

1

0

1

0

1

Standard C51 Port

7:6

5:4

3:2

1:0

LED3

LED2

LED1

LED0

2 mA current source when P3.7 is low

4 mA current source when P3.7 is low

10 mA current source when P3.7 is low

Port /LED2 Configuration

0

1

0

1

0

1

Standard C51 Port

2 mA current source when P3.6 is low

4 mA current source when P3.6 is low

10 mA current source when P3.6 is low

Port/ LED1

Configuration

Standard C51 Port

0

1

0

1

0

1

2 mA current source when P3.5 is low

4 mA current source when P3.5 is low

10 mA current source when P3.5 is low

Port/ LED0

Configuration

0

1

0

1

0

1

Standard C51 Port

2 mA current source when P3.3 is low

4 mA current source when P3.3 is low

10 mA current source when P3.3 is low

Reset Value = 00h

74

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

19. Serial Peripheral Interface (SPI)

The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial communica-

tion between the MCU and peripheral devices, including other MCUs.

19.1 Features

Features of the SPI module include the following:

• Full-duplex, three-wire synchronous transfers

• Master or Slave operation

• Eight programmable Master clock rates

• Serial clock with programmable polarity and phase

• Master mode fault error flag with MCU interrupt capability

• Write collision flag protection

19.2 Signal Description

Figure 19-1 shows a typical SPI bus configuration using one Master controller and many Slave

peripherals. The bus is made of three wires connecting all the devices:

Figure 19-1. SPI Master/Slaves Interconnection

Slave 1

MISO

MOSI

SCK

SS

VDD

Master

0

1

2

3

Slave 4

Slave 3

Slave 2

The Master device selects the individual Slave devices by using four pins of a parallel port to

control the four SS pins of the Slave devices.

19.2.1

19.2.2

Master Output Slave Input (MOSI)

This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI

line is used to transfer data in series from the Master to the Slave. Therefore, it is an output sig-

nal from the Master, and an input signal to a Slave. A byte (8-bit word) is transmitted most

significant bit (MSB) first, least significant bit (LSB) last.

Master Input Slave Output (MISO)

This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO

line is used to transfer data in series from the Slave to the Master. Therefore, it is an output sig-

nal from the Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most

significant bit (MSB) first, least significant bit (LSB) last.

75

7683C–USB–11/07

19.2.3

19.2.4

SPI Serial Clock (SCK)

This signal is used to synchronize the data movement both in and out the devices through their

MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange

one byte on the serial lines.

Slave Select (SS)

Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any

message for a Slave. It is obvious that only one Master (SS high level) can drive the network.

The Master may select each Slave device by software through port pins (Figure 19-1). To pre-

vent bus conflicts on the MISO line, only one slave should be selected at a time by the Master

for a transmission.

In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI

Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see

Section “Error Conditions”, page 79).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general-purpose if the following conditions are met:

• The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of

configuration can be found when only one Master is driving the network and there is no way

that the SS pin could be pulled low. Therefore, the MODF flag in the SPSTA will never be

set⁽¹⁾.

• The Device is configured as a Slave with CPHA and SSDIS control bits set⁽²⁾This kind of

configuration can happen when the system comprises one Master and one Slave only.

Therefore, the device should always be selected and there is no reason that the Master uses

the SS pin to select the communicating Slave device.

Notes: 1. Clearing SSDIS control bit does not clear MODF.

2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in this

mode, the SS is used to start the transmission.

19.2.5

Baud Rate

In Master mode, the baud rate can be selected from a baud rate generator which is controlled by

three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one

of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128.

Table 19-1 gives the different clock rates selected by SPR2:SPR1:SPR0:

Table 19-1. SPI Master Baud Rate Selection

SPR2

SPR1

SPR0

Clock Rate

Baud Rate Divisor (BD)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Don’t Use

No BRG

F_{CLK PERIPH}/4

F_{CLK PERIPH}/8

F_{CLK PERIPH}/16

F_{CLK PERIPH}/32

F_{CLK PERIPH}/64

F_{CLK PERIPH}/128

Don’t Use

4

8

16

32

64

128

No BRG

76

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

19.3 Functional Description

Figure 19-2 shows a detailed structure of the SPI module.

Figure 19-2. SPI Module Block Diagram

Internal Bus

SPDAT

Shift Register

4

FCLK PERIPH

7

6

5

3

2

1

0

/4

Clock

Divider

/8

/16

/32

/64

Receive Data Register

Control

Logic

MOSI

MISO

/128

Clock

Logic

M

S

SCK

SS

Clock

Select

SPR2

SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPCON

8-bit bus

SPI

Control

1-bit signal

SPI Interrupt Request

SPSTA

-

SPIF WCOL SSERR MODF

19.3.1

Operating Modes

The Serial Peripheral Interface can be configured as one of the two modes: Master mode or

Slave mode. The configuration and initialization of the SPI module is made through one register:

• The Serial Peripheral CONtrol register (SPCON)

Once the SPI is configured, the data exchange is made using:

• SPCON

• The Serial Peripheral STAtus register (SPSTA)

• The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and

received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the

two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a

Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.

When the Master device transmits data to the Slave device via the MOSI line, the Slave device

responds by sending data to the Master device via the MISO line. This implies full-duplex trans-

mission with both data out and data in synchronized with the same clock (Figure 19-3).

77

7683C–USB–11/07

Figure 19-3. Full-duplex Master/Slave Interconnection

MISO

MOSI

MISO

8-bit Shift Register

MOSI

SCK

SPI

Clock Generator

SCK

SS

VDD

Master MCU

Slave MCU

VSS

19.3.1.1

Master Mode

The SPI operates in Master mode when the Master bit, MSTR ⁽¹⁾, in the SPCON register is set.

Only one Master SPI device can initiate transmissions. Software begins the transmission from a

Master SPI module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register

is empty, the byte is immediately transferred to the shift register. The byte begins shifting out on

MOSI pin under the control of the serial clock, SCK. Simultaneously, another byte shifts in from

the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer

data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received

byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF

by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading

the SPDAT.

19.3.1.2

Slave Mode

The SPI operates in Slave mode when the Master bit, MSTR ⁽²⁾, in the SPCON register is

cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must

be set to’0’. SS must remain low until the transmission is complete.

In a Slave SPI module, data enters the shift register under the control of the SCK from the Mas-

ter SPI module. After a byte enters the shift register, it is immediately transferred to the receive

data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software

must then read the SPDAT before another byte enters the shift register ⁽³⁾. A Slave SPI must

complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI

starts a transmission. If the write to the data register is late, the SPI transmits the data already in

the shift register from the previous transmission.

19.3.2

Transmission Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity using two

bits in the SPCON: the Clock POLarity (CPOL ⁽⁴⁾) and the Clock PHAse (CPHA⁴). CPOL defines

the default SCK line level in idle state. It has no significant effect on the transmission format.

CPHA defines the edges on which the input data are sampled and the edges on which the out-

put data are shifted (Figure 19-4 and Figure 19-5). The clock phase and polarity should be

identical for the Master SPI device and the communicating Slave device.

1.

The SPI module should be configured as a Master before it is enabled (SPEN set). Also the Mas-

ter SPI should be configured before the Slave SPI.

2.

3.

4.

The SPI module should be configured as a Slave before it is enabled (SPEN set).

The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.

Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’).

78

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Figure 19-4. Data Transmission Format (CPHA = 0)

1

2

3

4

5

6

7

8

SCK cycle number

SPEN (internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI (from Master)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MISO (from Slave)

MSB

SS (to Slave)

Capture point

Figure 19-5. Data Transmission Format (CPHA = 1)

1

2

3

4

5

6

7

8

SCK cycle number

SPEN (internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MOSI (from Master)

MISO (from Slave)

SS (to Slave)

Capture point

Figure 19-6. CPHA/SS Timing

Byte 3

MISO/MOSI

Byte 1

Byte 2

Master SS

Slave SS

(CPHA = 0)

Slave SS

(CPHA = 1)

As shown in Figure 19-5, the first SCK edge is the MSB capture strobe. Therefore the Slave

must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to

start the transmission. The SS pin must be toggled high and then low between each byte trans-

mitted (Figure 19-2).

Figure 19-6 shows an SPI transmission in which CPHA is’1’. In this case, the Master begins driv-

ing its MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start

transmission signal. The SS pin can remain low between transmissions (Figure 19-1). This for-

mat may be preferable in systems having only one Master and only one Slave driving the MISO

data line.

19.3.3

Error Conditions

The following flags in the SPSTA signal SPI error conditions:

79

7683C–USB–11/07

19.3.3.1

Mode Fault (MODF)

Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is

inconsistent with the actual mode of the device. MODF is set to warn that there may have a

multi-master conflict for system control. In this case, the SPI system is affected in the following

ways:

• An SPI receiver/error CPU interrupt request is generated,

• The SPEN bit in SPCON is cleared. This disable the SPI,

• The MSTR bit in SPCON is cleared

When SS DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the

SS signal becomes “0”.

However, as stated before, for a system with one Master, if the SS pin of the Master device is

pulled low, there is no way that another Master attempt to drive the network. In this case, to pre-

vent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and

therefore making the SS pin as a general-purpose I/O pin.

Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed

by a write to the SPCON register. SPEN Control bit may be restored to its original set state after

the MODF bit has been cleared.

19.3.3.2

Write Collision (WCOL)

A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done

during a transmit sequence.

WCOL does not cause an interruption, and the transfer continues uninterrupted.

Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an

access to SPDAT.

19.3.3.3

Overrun Condition

An overrun condition occurs when the Master device tries to send several data bytes and the

Slave devise has not cleared the SPIF bit issuing from the previous data byte transmitted. In this

case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the

SPDAT returns this byte. All others bytes are lost.

This condition is not detected by the SPI peripheral.

Two SPI status flags can generate a CPU interrupt requests:

Table 19-2. SPI Interrupts

19.3.4

Interrupts

Flag

Request

SPIF (SP Data Transfer)

MODF (Mode Fault)

SPI Transmitter Interrupt request

SPI Receiver/Error Interrupt Request (if SSDIS = “0”)

Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been

completed. SPIF bit generates transmitter CPU interrupt requests.

80

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent

with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt

requests.

Figure 19-7 gives a logical view of the above statements.

Figure 19-7. SPI Interrupt Requests Generation

SPIF

SPI Transmitter

CPU Interrupt Request

SPI

CPU Interrupt Request

MODF

SSDIS

SPI Receiver/Error

CPU Interrupt Request

19.3.5

Registers

There are three registers in the module that provide control, status and data storage functions. These registers are

describes in the following paragraphs.

19.3.5.1

Serial Peripheral Control Register (SPCON)

• The Serial Peripheral Control Register does the following:

– Selects one of the Master clock rates

– Configure the SPI module as Master or Slave

– Selects serial clock polarity and phase

– Enables the SPI module

– Frees the SS pin for a general-purpose

Table 19-3 describes this register and explains the use of each bit.

Table 19-3. SPCON Register

7

6

5

4

3

2

1

0

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Bit

Number

Bit Mnemonic Description

Serial Peripheral Rate 2

SPR2

7

6

Bit with SPR1 and SPR0 define the clock rate.

Serial Peripheral Enable

SPEN

Cleared to disable the SPI interface.

Set to enable the SPI interface.

SS Disable

Cleared to enable SS in both Master and Slave modes.

5

SSDIS

Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no

effect if CPHA = “0”.

Serial Peripheral Master

5

4

MSTR

CPOL

Cleared to configure the SPI as a Slave.

Set to configure the SPI as a Master.

Clock Polarity

Cleared to have the SCK set to “0” in idle state.

Set to have the SCK set to “1” in idle state.

81

7683C–USB–11/07

Bit

Number

Bit Mnemonic Description

Clock Phase

3

2

CPHA

Cleared to have the data sampled when the SCK leaves the idle state (see CPOL).

Set to have the data sampled when the SCK returns to idle state (see CPOL).

SPR2 SPR1

SPR0

Serial Peripheral Rate

Reserved

SPR1

0

1

0

1

0

1

0

1

0

1

0

F_{CLK PERIPH/}

4

8

F_{CLK PERIPH/}16

F_{CLK PERIPH/}32

F_{CLK PERIPH/}64

F_{CLK PERIPH/}128

Reserved

1

SPR0

0

1

Reset Value = 0001 0100b

Not bit addressable

19.3.5.2

Serial Peripheral Status Register (SPSTA)

The Serial Peripheral Status Register contains flags to signal the following conditions:

• Data transfer complete

• Write collision

• Inconsistent logic level on SS pin (mode fault error)

Table 19-4 describes the SPSTA register and explains the use of every bit in the register.

Table 19-4. SPSTA Register

SPSTA - Serial Peripheral Status and Control register (0C4H)

Table 3.

7

6

5

4

3

-

2

-

1

-

0

-

SPIF

WCOL

SSERR

MODF

Bit

Bit Number Mnemonic Description

Serial Peripheral data transfer flag

Cleared by hardware to indicate data transfer is in progress or has been approved by a

clearing sequence.

7

6

5

SPIF

WCOL

SSERR

Set by hardware to indicate that the data transfer has been completed.

Write Collision flag

Cleared by hardware to indicate that no collision has occurred or has been approved by a

clearing sequence.

Set by hardware to indicate that a collision has been detected.

Synchronous Serial Slave Error flag

Set by hardware when SS is de-

asserted before the end of a received data.

Cleared by disabling the SPI (clearing SPEN bit in SPCON).

82

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Bit

Bit Number Mnemonic Description

Mode Fault

Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been

approved by a clearing sequence.

4

MODF

Set by hardware to indicate that the SS pin is at inappropriate logic level.

Reserved

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = 00X0 XXXXb

Not Bit addressable

19.3.5.3

Serial Peripheral Data Register (SPDAT)

The Serial Peripheral Data Register (Table 19-5) is a read/write buffer for the receive data regis-

ter. A write to SPDAT places data directly into the shift register. No transmit buffer is available in

this model.

A Read of the SPDAT returns the value located in the receive buffer and not the content of the

shift register.

Table 19-5. SPDAT Register

SPDAT - Serial Peripheral Data Register (0C5H)

7

6

5

4

3

2

1

0

R7

R6

R5

R4

R3

R2

R1

R0

Reset Value = Indeterminate

R7:R0: Receive data bits

SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-

going exchange. However, special care should be taken when writing to them while a transmis-

sion is on-going:

• Do not change SPR2, SPR1 and SPR0

• Do not change CPHA and CPOL

• Do not change MSTR

• Clearing SPEN would immediately disable the peripheral

• Writing to the SPDAT will cause an overflow

83

7683C–USB–11/07

20. Two Wire Interface (TWI

)

This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial com-

munication standard. It is designed primarily for simple but efficient integrated circuit (IC) control.

The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry infor-

mation between the ICs connected to them. The serial data transfer is limited to 100 Kbit/s in

standard mode. Various communication configuration can be designed using this bus. Figure

20-1 shows a typical 2-wire bus configuration. All the devices connected to the bus can be mas-

ter and slave.

Figure 20-1. 2-wire Bus Configuration

...

device1

device2

device3

deviceN

SCL

SDA

84

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Figure 20-2. Block Diagram

8

SSADR

Address Register

Comparator

Input

Filter

SDA

Output

Stage

ACK

SSDAT

Shift Register

8

Arbitration &

Sink Logic

Input

Filter

Timing &

Control

logic

F_{CLK PERIPH}/4

SCL

Interrupt

Output

Stage

Serial clock

generator

Timer 1

overflow

SSCON

Control Register

7

Status

Decoder

Status

Bits

SSCS

Status Register

8

85

7683C–USB–11/07

20.1 Description

The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the

Synchronous Serial Control register (SSCON; Table 20-10), the Synchronous Serial Data regis-

ter (SSDAT; Table 20-11), the Synchronous Serial Control and Status register (SSCS; Table 20-

12) and the Synchronous Serial Address register (SSADR Table 20-13).

SSCON is used to enable the TWI interface, to program the bit rate (see Table 20-3), to enable

slave modes, to acknowledge or not a received data, to send a START or a STOP condition on

the 2-wire bus, and to acknowledge a serial interrupt. A hardware reset disables the TWI

module.

SSCS contains a status code which reflects the status of the 2-wire logic and the 2-wire bus.

The three least significant bits are always zero. The five most significant bits contains the status

code. There are 26 possible status codes. When SSCS contains F8h, no relevant state informa-

tion is available and no serial interrupt is requested. A valid status code is available in SSCS one

machine cycle after SI is set by hardware and is still present one machine cycle after SI has

been reset by software. to Table 20-9. give the status for the master modes and miscellaneous

states.

SSDAT contains a byte of serial data to be transmitted or a byte which has just been received. It

is addressable while it is not in process of shifting a byte. This occurs when 2-wire logic is in a

defined state and the serial interrupt flag is set. Data in SSDAT remains stable as long as SI is

set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always

contains the last byte present on the bus.

SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which the TWI

module will respond when programmed as a slave transmitter or receiver. The LSB is used to

enable general call address (00h) recognition.

Figure 20-3 shows how a data transfer is accomplished on the 2-wire bus.

Figure 20-3. Complete Data Transfer on 2-wire Bus

MSB

SDA

SCL

acknowledgement

signal from receiver

acknowledgement

signal from receiver

1

2

3-8

9

7

1

2

8

9

S

ACK

clock line held low

while interrupts are serviced

P

stop

condition

start

condition

The four operating modes are:

• Master Transmitter

• Master Receiver

• Slave transmitter

• Slave receiver

Data transfer in each mode of operation is shown in Table to Table 20-9 and Figure 20-4. to

Figure 20-7.. These figures contain the following abbreviations:

S

: START condition

86

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

R

: Read bit (high level at SDA)

: Write bit (low level at SDA)

Acknowledge bit (low level at SDA)

W

A:

A: Not acknowledge bit (high level at SDA)

Data: 8-bit data byte

P

: STOP condition

In Figure 20-4 to Figure 20-7, circles are used to indicate when the serial interrupt flag is set.

The numbers in the circles show the status code held in SSCS. At these points, a service routine

must be executed to continue or complete the serial transfer. These service routines are not crit-

ical since the serial transfer is suspended until the serial interrupt flag is cleared by software.

When the serial interrupt routine is entered, the status code in SSCS is used to branch to the

appropriate service routine. For each status code, the required software action and details of the

following serial transfer are given in Table to Table 20-9.

20.1.1

Master Transmitter Mode

In the master transmitter mode, a number of data bytes are transmitted to a slave receiver

(Figure 20-4). Before the master transmitter mode can be entered, SSCON must be initialised as

follows:

Table 20-1. SSCON Initialization

CR2

SSIE

STA

STO

SI

AA

CR1

CR0

bit rate

1

0

X

bit rate

CR0, CR1 and CR2 define the internal serial bit rate if external bit rate generator is not used.

SSIE must be set to enable TWI. STA, STO and SI must be cleared.

The master transmitter mode may now be entered by setting the STA bit. The 2-wire logic will

now test the 2-wire bus and generate a START condition as soon as the bus becomes free.

When a START condition is transmitted, the serial interrupt flag (SI bit in SSCON) is set, and the

status code in SSCS will be 08h. This status must be used to vector to an interrupt routine that

loads SSDAT with the slave address and the data direction bit (SLA+W).

When the slave address and the direction bit have been transmitted and an acknowledgement

bit has been received, SI is set again and a number of status code in SSCS are possible. There

are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was

enabled (AA=logic 1). The appropriate action to be taken for each of these status code is

detailed in Table . This scheme is repeated until a STOP condition is transmitted.

SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to

Table 11. After a repeated START condition (state 10h) the TWI module may switch to the mas-

ter receiver mode by loading SSDAT with SLA+R.

20.1.2

Master Receiver Mode

In the master receiver mode, a number of data bytes are received from a slave transmitter

(Figure 20-5). The transfer is initialized as in the master transmitter mode. When the START

condition has been transmitted, the interrupt routine must load SSDAT with the 7-bit slave

87

7683C–USB–11/07

address and the data direction bit (SLA+R). The serial interrupt flag SI must then be cleared

before the serial transfer can continue.

When the slave address and the direction bit have been transmitted and an acknowledgement

bit has been received, the serial interrupt flag is set again and a number of status code in SSCS

are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the

slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these sta-

tus code is detailed in Table . This scheme is repeated until a STOP condition is transmitted.

SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to

Table 11. After a repeated START condition (state 10h) the TWI module may switch to the mas-

ter transmitter mode by loading SSDAT with SLA+W.

20.1.3

Slave Receiver Mode

In the slave receiver mode, a number of data bytes are received from a master transmitter

(Figure 20-6). To initiate the slave receiver mode, SSADR and SSCON must be loaded as

follows:

Table 20-2. SSADR: Slave Receiver Mode Initialization

A6

A5

A4

A3

A2

A1

A0

GC

own slave address

The upper 7 bits are the address to which the TWI module will respond when addressed by a

master. If the LSB (GC) is set the TWI module will respond to the general call address (00h);

otherwise it ignores the general call address.

Table 20-3. SSCON: Slave Receiver Mode Initialization

CR2

SSIE

STA

STO

SI

AA

CR1

CR0

bit rate

1

0

1

bit rate

CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable the TWI. The

AA bit must be set to enable the own slave address or the general call address acknowledge-

ment. STA, STO and SI must be cleared.

When SSADR and SSCON have been initialised, the TWI module waits until it is addressed by

its own slave address followed by the data direction bit which must be at logic 0 (W) for the TWI

to operate in the slave receiver mode. After its own slave address and the W bit have been

received, the serial interrupt flag is set and a valid status code can be read from SSCS. This sta-

tus code is used to vector to an interrupt service routine.The appropriate action to be taken for

each of these status code is detailed in Table . The slave receiver mode may also be entered if

arbitration is lost while TWI is in the master mode (states 68h and 78h).

If the AA bit is reset during a transfer, TWI module will return a not acknowledge (logic 1) to SDA

after the next received data byte. While AA is reset, the TWI module does not respond to its own

slave address. However, the 2-wire bus is still monitored and address recognition may be

resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate

the module from the 2-wire bus.

88

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

20.1.4

Slave Transmitter Mode

In the slave transmitter mode, a number of data bytes are transmitted to a master receiver

(Figure 20-7). Data transfer is initialized as in the slave receiver mode. When SSADR and

SSCON have been initialized, the TWI module waits until it is addressed by its own slave

address followed by the data direction bit which must be at logic 1 (R) for TWI to operate in the

slave transmitter mode. After its own slave address and the R bit have been received, the serial

interrupt flag is set and a valid status code can be read from SSCS. This status code is used to

vector to an interrupt service routine. The appropriate action to be taken for each of these status

code is detailed in Table . The slave transmitter mode may also be entered if arbitration is lost

while the TWI module is in the master mode.

If the AA bit is reset during a transfer, the TWI module will transmit the last byte of the transfer

and enter state C0h or C8h. the TWI module is switched to the not addressed slave mode and

will ignore the master receiver if it continues the transfer. Thus the master receiver receives all

1’s as serial data. While AA is reset, the TWI module does not respond to its own slave address.

However, the 2-wire bus is still monitored and address recognition may be resume at any time

by setting AA. This means that the AA bit may be used to temporarily isolate the TWI module

from the 2-wire bus.

20.1.5

Miscellaneous States

There are two SSCS codes that do not correspond to a define TWI hardware state (Table 20-9 ).

These codes are discuss hereafter.

Status F8h indicates that no relevant information is available because the serial interrupt flag is

not set yet. This occurs between other states and when the TWI module is not involved in a

serial transfer.

Status 00h indicates that a bus error has occurred during a TWI serial transfer. A bus error is

caused when a START or a STOP condition occurs at an illegal position in the format frame.

Examples of such illegal positions happen during the serial transfer of an address byte, a data

byte, or an acknowledge bit. When a bus error occurs, SI is set. To recover from a bus error, the

STO flag must be set and SI must be cleared. This causes the TWI module to enter the not

addressed slave mode and to clear the STO flag (no other bits in SSCON are affected). The

SDA and SCL lines are released and no STOP condition is transmitted.

20.2 Notes

the TWI module interfaces to the external 2-wire bus via two port pins: SCL (serial clock line)

and SDA (serial data line). To avoid low level asserting on these lines when the TWI module is

enabled, the output latches of SDA and SLC must be set to logic 1.

Table 20-4. Bit Frequency Configuration

Bit Frequency ( kHz)

CR2

CR1

CR0

F_OSCA= 12 MHz

F_OSCA= 16 MHz

F_OSCAdivided by

0

1

0

1

0

1

47

53.5

62.5

75

62.5

71.5

83

256

224

192

160

100

89

7683C–USB–11/07

Bit Frequency ( kHz)

CR2

CR1

CR0

F_OSCA= 12 MHz

F_OSCA= 16 MHz

F_OSCAdivided by

1

0

1

0

1

0

-

Unused

120

100

200

133.3

266.6

60

Timer 1 in mode 2 can be used as TWI baudrate

generator with the following formula:

1

0.5 <. < 62.5

0.67 <. < 83

96.(256-”Timer1 reload value”)

Figure 20-4. Format and State in the Master Transmitter Mode

MT

Successfull

S

SLA

W

A

Data

A

P

transmission

to a slave

receiver

28h

08h

18h

Next transfer

started with a

repeated start

condition

S

SLA

W

R

10h

Not acknowledge

received after the

slave address

A

P

20h

MR

Not acknowledge

received after a data

byte

A

P

30h

Other master

continues

Arbitration lost in slave

address or data byte

Other master

continues

A or A

38h

A or A

38h

A

Arbitration lost and

addressed as slave

Other master

continues

68h 78h B0h

To corresponding

states in slave mode

Any number of data bytes and their associated

acknowledge bits

From master to slave

AT83C5134/35/36

From slave to master

Data

A

90

7683C–USB–11/07

This number (contained in SSCS) corresponds

to a defined state of the 2-wire bus

n

AT83C5134/35/36

Table 20-5. Status in Master Transmitter Mode

Application software response

To SSCON

SSSTO SSI

Status Status of the Two-

Code wire Bus and Two-

SSSTA wire Hardware

To/From SSDAT

SSSTA

SSAA Next Action Taken by Two-wire Hardware

A START condition has

08h

Write SLA+W

X

0

X

SLA+W will be transmitted.

been transmitted

Write SLA+W

Write SLA+R

X

0

X

A repeated START

condition has been

transmitted

10h

18h

SLA+R will be transmitted.

Logic will switch to master receiver mode

Data byte will be transmitted.

Write data byte

0

1

0

1

0

X

Repeated START will be transmitted.

No SSDAT action

SLA+W has been

transmitted; ACK has

been received

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

No SSDAT action

1

0

X

Data byte will be transmitted.

Write data byte

0

1

0

1

0

X

Repeated START will be transmitted.

No SSDAT action

SLA+W has been

STOP condition will be transmitted and SSSTO flag

will be reset.

20h

transmitted; NOT ACK

has been received

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

No SSDAT action

1

0

X

Data byte will be transmitted.

Write data byte

0

1

0

1

0

X

Repeated START will be transmitted.

No SSDAT action

Data byte has been

transmitted; ACK has

been received

STOP condition will be transmitted and SSSTO flag

will be reset.

28h

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

No SSDAT action

1

0

X

Data byte will be transmitted.

Write data byte

0

1

0

1

0

X

Repeated START will be transmitted.

No SSDAT action

Data byte has been

transmitted; NOT ACK

has been received

STOP condition will be transmitted and SSSTO flag

will be reset.

30h

38h

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

No SSDAT action

1

0

X

Two-wire bus will be released and not addressed

slave mode will be entered.

No SSDAT action

0

1

0

X

Arbitration lost in

SLA+W or data bytes

A START condition will be transmitted when the bus

becomes free.

91

7683C–USB–11/07

Figure 20-5. Format and State in the Master Receiver Mode

MR

Successfull

transmission

to a slave

receiver

Data

A

P

S

SLA

R

A

Data

50h

58h

08h

40h

Next transfer

started with a

repeated start

condition

S

SLA

R

10h

Not acknowledge

received after the

slave address

W

A

P

MT

48h

Arbitration lost in slave

address or acknowledge bit

Other master

continues

Other master

continues

A

A or A

38h

A

38h

Other master

continues

Arbitration lost and

addressed as slave

To corresponding

states in slave mode

68h 78h B0h

From master to slave

From slave to master

Any number of data bytes and their associated

acknowledge bits

Data

n

A

This number (contained in SSCS) corresponds

to a defined state of the 2-wire bus

92

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 20-6. Status in Master Receiver Mode

Application software response

To SSCON

SSSTO SSI

Status Status of the Two-

Code wire Bus and Two-

SSSTA wire Hardware

To/From SSDAT

SSSTA

SSAA Next Action Taken by Two-wire Hardware

A START condition has

08h

Write SLA+R

X

0

X

SLA+R will be transmitted.

been transmitted

Write SLA+R

Write SLA+W

X

0

X

A repeated START

condition has been

transmitted

10h

SLA+W will be transmitted.

Logic will switch to master transmitter mode.

Two-wire bus will be released and not addressed

slave mode will be entered.

No SSDAT action

0

1

0

X

0

1

Arbitration lost in

SLA+R or NOT ACK

bit

38h

40h

A START condition will be transmitted when the bus

becomes free.

Data byte will be received and NOT ACK will be

returned.

SLA+R has been

transmitted; ACK has

been received

Data byte will be received and ACK will be returned.

Repeated START will be transmitted.

No SSDAT action

1

0

1

0

X

SLA+R has been

STOP condition will be transmitted and SSSTO flag

will be reset.

48h

50h

58h

transmitted; NOT ACK

has been received

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

No SSDAT action

Read data byte

1

0

1

0

X

0

1

Data byte will be received and NOT ACK will be

returned.

Data byte has been

received; ACK has

been returned

Data byte will be received and ACK will be returned.

Repeated START will be transmitted.

Read data byte

1

0

1

0

X

Data byte has been

received; NOT ACK

has been returned

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

Read data byte

1

0

X

93

7683C–USB–11/07

Figure 20-6. Format and State in the Slave Receiver Mode

Reception of the own

P or S

Data

A

S

SLA

W

A

slave address and one or

more data bytes. All are

acknowledged.

60h

80h

A0h

80h

A

Last data byte received

is not acknowledged.

P or S

88h

Arbitration lost as master

and addressed as slave

A

68h

Reception of the general call

address and one or more data

bytes.

P or S

Data

A

General Call

A

90h

A

70h

90h

A0h

Last data byte received is

not acknowledged.

P or S

98h

A

Arbitration lost as master and

addressed as slave by general call

78h

From master to slave

From slave to master

Any number of data bytes and their associated

acknowledge bits

Data

n

A

This number (contained in SSCS) corresponds

to a defined state of the 2-wire bus

94

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 20-7. Status in Slave Receiver Mode

Application Software Response

To/from SSDAT To SSCON

Status

Code

(SSCS)

Status of the 2-wire bus and

2-wire hardware

STA

X

STO

SI

0

AA Next Action Taken By 2-wire Software

Data byte will be received and NOT ACK will be

No SSDAT action or

No SSDAT action

0

Own SLA+W has been

received; ACK has been

returned

60h

68h

70h

78h

80h

Data byte will be received and ACK will be

returned

X

0

1

Data byte will be received and NOT ACK will be

returned

Arbitration lost in SLA+R/W as

master; own SLA+W has been

received; ACK has been

returned

No SSDAT action or

No SSDAT action

X

0

Data byte will be received and ACK will be

1

returned

Data byte will be received and NOT ACK will be

returned

No SSDAT action or

No SSDAT action

X

0

General call address has been

received; ACK has been

returned

Data byte will be received and ACK will be

returned

1

Data byte will be received and NOT ACK will be

Arbitration lost in SLA+R/W as

master; general call address

has been received; ACK has

been returned

No SSDAT action or

No SSDAT action

X

0

returned

Data byte will be received and ACK will be

returned

1

Data byte will be received and NOT ACK will be

returned

Previously addressed with own

SLA+W; data has been

received; ACK has been

returned

No SSDAT action or

No SSDAT action

X

0

Data byte will be received and ACK will be

1

returned

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

Read data byte or

0

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

1

GC=logic 1

Previously addressed with own

SLA+W; data has been

received; NOT ACK has been

returned

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START

condition will be transmitted when the bus

88h

Read data byte or

Read data byte

1

0

becomes free

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be

1

transmitted when the bus becomes free

Data byte will be received and NOT ACK will be

returned

Previously addressed with

general call; data has been

received; ACK has been

returned

X

0

Read data byte or

Read data byte

90h

Data byte will be received and ACK will be

returned

1

95

7683C–USB–11/07

Table 20-7. Status in Slave Receiver Mode (Continued)

Application Software Response

To/from SSDAT

To SSCON

Status

Code

(SSCS)

Status of the 2-wire bus and

2-wire hardware

STA

STO

SI

AA Next Action Taken By 2-wire Software

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

Read data byte or

0

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1

1

Previously addressed with

general call; data has been

received; NOT ACK has been

returned

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START

98h

Read data byte or

Read data byte

1

0

condition will be transmitted when the bus

becomes free

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

1

GC=logic 1. A START condition will be

transmitted when the bus becomes free

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

No SSDAT action or

0

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1

1

A STOP condition or repeated

START condition has been

received while still addressed

as slave

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START

A0h

No SSDAT action or

No SSDAT action

1

0

condition will be transmitted when the bus

becomes free

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

1

GC=logic 1. A START condition will be

transmitted when the bus becomes free

96

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Figure 20-7. Format and State in the Slave Transmitter Mode

Reception of the

own slave address

and one or more

data bytes

A

P or S

A

Data

A

S

SLA

R

A8h

A

B8h

C0h

Arbitration lost as master

and addressed as slave

B0h

Last data byte transmitted.

Switched to not addressed

slave (AA=0)

All 1’s

P or S

A

C8h

From master to slave

From slave to master

Any number of data bytes and their associated

acknowledge bits

Data

A

This number (contained in SSCS) corresponds

to a defined state of the 2-wire bus

n

Table 20-8. Status in Slave Transmitter Mode

Application Software Response

To/from SSDAT To SSCON

Status

Code

(SSCS)

Status of the 2-wire bus and

2-wire hardware

STA

X

STO

SI

0

AA Next Action Taken By 2-wire Software

Last data byte will be transmitted and NOT ACK

Load data byte or

Load data byte

0

Own SLA+R has been

received; ACK has been

returned

will be received

A8h

B0h

B8h

Data byte will be transmitted and ACK will be

received

X

0

1

Last data byte will be transmitted and NOT ACK

will be received

Arbitration lost in SLA+R/W as

master; own SLA+R has been

received; ACK has been

returned

Load data byte or

Load data byte

X

0

Data byte will be transmitted and ACK will be

1

received

Last data byte will be transmitted and NOT ACK

will be received

Load data byte or

Load data byte

X

0

Data byte in SSDAT has been

transmitted; NOT ACK has

been received

Data byte will be transmitted and ACK will be

received

1

97

7683C–USB–11/07

Table 20-8. Status in Slave Transmitter Mode (Continued)

Application Software Response

To/from SSDAT

To SSCON

Status

Code

(SSCS)

Status of the 2-wire bus and

2-wire hardware

STA

STO

SI

AA Next Action Taken By 2-wire Software

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

No SSDAT action or

0

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1

1

Data byte in SSDAT has been

transmitted; NOT ACK has

been received

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START

C0h

No SSDAT action or

No SSDAT action

1

0

condition will be transmitted when the bus

becomes free

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

1

GC=logic 1. A START condition will be transmitted

when the bus becomes free

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

No SSDAT action or

0

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1

1

Last data byte in SSDAT has

been transmitted (AA=0); ACK

has been received

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START

C8h

No SSDAT action or

No SSDAT action

1

0

condition will be transmitted when the bus

becomes free

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

1

GC=logic 1. A START condition will be transmitted

when the bus becomes free

Table 20-9. Miscellaneous Status

Application Software Response

To/from SSDAT To SSCON

STO SI

No SSCON action

Status

Code

(SSCS)

Status of the 2-wire bus and

2-wire hardware

STA

AA Next Action Taken By 2-wire Software

No relevant state information

available; SI= 0

F8h

00h

No SSDAT action

Wait or proceed current transfer

Only the internal hardware is affected, no

STOP condition is sent on the bus. In all

cases, the bus is released and STO is reset.

Bus error due to an illegal

START or STOP condition

No SSDAT action

0

1

0

X

98

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

20.3 Registers

Table 20-10. SSCON Register

SSCON - Synchronous Serial Control Register (93h)

7

6

5

4

3

2

1

0

CR2

SSIE

STA

STO

SI

AA

CR1

CR0

Bit

Bit Number Mnemonic Description

Control Rate bit 2

See .

7

6

CR2

Synchronous Serial Interface Enable bit

Clear to disable SSLC.

Set to enable SSLC.

SSIE

Start flag

Set to send a START condition on the bus.

5

4

STA

ST0

Stop flag

Set to send a STOP condition on the bus.

Synchronous Serial Interrupt flag

Set by hardware when a serial interrupt is requested.

Must be cleared by software to acknowledge interrupt.

3

SI

Assert Acknowledge flag

Clear in master and slave receiver modes, to force a not acknowledge (high level on

SDA).

Clear to disable SLA or GCA recognition.

2

AA

Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter

modes.

Set in master and slave receiver modes, to force an acknowledge (low level on SDA).

This bit has no effect when in master transmitter mode.

Control Rate bit 1

See Table 20-4

1

0

CR1

CR0

Control Rate bit 0

See Table 20-4

Table 20-11. SSDAT (095h) - Synchronous Serial Data Register (read/write)

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

0

7

6

5

4

3

2

1

Bit

Bit Number Mnemonic Description

7

6

5

4

3

2

SD7

SD6

SD5

SD4

SD3

SD2

Address bit 7 or Data bit 7.

Address bit 6 or Data bit 6.

Address bit 5 or Data bit 5.

Address bit 4 or Data bit 4.

Address bit 3 or Data bit 3.

Address bit 2 or Data bit 2.

99

7683C–USB–11/07

Bit

Bit Number Mnemonic Description

1

0

SD1

SD0

Address bit 1 or Data bit 1.

Address bit 0 (R/W) or Data bit 0.

Table 20-12. SSCS (094h) Read - Synchronous Serial Control and Status Register

7

6

5

4

3

2

1

0

SC4

SC3

SC2

SC1

SC0

0

Bit

Bit Number Mnemonic Description

0

1

2

0

Always zero

Status Code bit 0

See Table 20-5 to Table 20-9

3

4

5

6

7

SC0

SC1

SC2

SC3

SC4

Status Code bit 1

See Table 20-5 to Table 20-9

Status Code bit 2

See Table 20-5 to Table 20-9

Status Code bit 3

See Table 20-5 to Table 20-9

Status Code bit 4

See Table 20-5 to Table 20-9

Table 20-13. SSADR (096h) - Synchronous Serial Address Register (read/write)

7

6

5

4

3

2

1

0

A7

A6

A5

A4

A3

A2

A1

A0

Bit

Bit Number Mnemonic Description

7

6

5

4

3

2

1

A7

A6

A5

A4

A3

A2

A1

Slave address bit 7.

Slave address bit 6.

Slave address bit 5.

Slave address bit 4.

Slave address bit 3.

Slave address bit 2.

Slave address bit 1.

General call bit

0

GC

Clear to disable the general call address recognition.

Set to enable the general call address recognition.

100

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

21. USB Controller

.

21.1 Description

The USB device controller provides the hardware that the AT89C5131 needs to interface a USB

link to a data flow stored in a double port memory (DPRAM).

The USB controller requires a 48 MHz 0.25% reference clock, which is the output of the

AT89C5131 PLL (see Section “PLL”, page 14) divided by a clock prescaler. This clock is used to

generate a 12 MHz Full-speed bit clock from the received USB differential data and to transmit

data according to full speed USB device tolerance. Clock recovery is done by a Digital Phase

Locked Loop (DPLL) block, which is compliant with the jitter specification of the USB bus.

The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing, CRC

generation and checking, and the serial-parallel data conversion.

The Universal Function Interface (UFI) realizes the interface between the data flow and the Dual

Port RAM.

Figure 21-1. USB Device Controller Block Diagram

48 MHz +/- 0.25%

DPLL 12 MHz

C51

Microcontroller

Interface

D+

D-

USB

D+/D-

Buffer

UFI

Up to 48 MHz

UC_sysclk

SIE

21.1.1

Serial Interface Engine (SIE)

The SIE performs the following functions:

• NRZI data encoding and decoding.

• Bit stuffing and un-stuffing.

• CRC generation and checking.

• Handshakes.

• TOKEN type identifying.

101

7683C–USB–11/07

• Address checking.

• Clock generation (via DPLL).

Figure 21-2. SIE Block Diagram

End of Packet

Detection

SYNC Detection

PID Decoder

Start of Packet

Detection

NRZI ‘NRZ

D+

D-

Bit Un-stuffing

Packet Bit Counter

DataOut

8

Address Decoder

Serial to

Parallel

Clock

SysClk

Recovery

(12 MHz)

CRC5 and CRC16

Generation/Check

Clk48

USB Pattern Generator

Parallel to Serial Converter

Bit Stuffing

(48 MHz)

8

DataIn [7:0]

NRZI Converter

CRC16 Generator

21.1.2

Function Interface Unit (FIU)

The Function Interface Unit provides the interface between the AT89C5131 and the SIE. It man-

ages transactions at the packet level with minimal intervention from the device firmware, which

reads and writes the endpoint FIFOs.

102

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Figure 21-3. UFI Block Diagram

FIU

Asynchronous Information

Transfer

C51

CSREG 0 to 7

DPLL

Microcontroller

Interface

Transfer

Control

FSM

Registers

Bank

Endpoint 5

Endpoint 4

Endpoint 3

Endpoint 2

Endpoint 1

DPR Control

USB Side

DPR Control

mP side

Up to 48 MHz

UC_sysclk

SIE

Endpoint 0

User DPRAM

Figure 21-4. Minimum Intervention from the USB Device Firmware

OUT Transactions:

OUT DATA0 (n bytes)

OUT DATA1

HOST

UFI

ACK interrupt C51

NACK

ACK

Endpoint FIFO read (n bytes)

C51

IN Transactions:

IN

ACK

HOST

DATA1

NACK

Endpoint FIFO write

UFI

interrupt C51

Endpoint FIFO write

C51

21.2 Configuration

21.2.1

General Configuration

• USB controller enable

Before any USB transaction, the 48 MHz required by the USB controller must be correctly

generated (See “Clock Controller” on page 13.).

The USB controller will be then enabled by setting the EUSB bit in the USBCON register.

• Set address

After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the

USBADDR register. This action will allow the USB controller to answer to the requests sent

at the address 0.

When a SET_ADDRESS request has been received, the USB controller must only answer

to the address defined by the request. The new address will be stored in the USBADDR reg-

ister. The FEN bit and the FADDEN bit in the USBCON register will be set to allow the USB

controller to answer only to requests sent at the new address.

103

7683C–USB–11/07

• Set configuration

The CONFG bit in the USBCON register has to be set after a SET_CONFIGURATION

request with a non-zero value. Otherwise, this bit has to be cleared.

21.2.2

Endpoint Configuration

• Selection of an Endpoint

The endpoint register access is performed using the UEPNUM register. The registers

– UEPSTAX

– UEPCONX

– UEPDATX

– UBYCTLX

– UBYCTHX

These registers correspond to the endpoint whose number is stored in the UEPNUM regis-

ter. To select an Endpoint, the firmware has to write the endpoint number in the UEPNUM

register.

Figure 21-5. Endpoint Selection

UEPSTA0

UEPCON0

UEPDAT0

0

Endpoint 0

SFR registers

UBYCTH0

UBYCTL0

1

2

3

4

UEPSTAX

UEPCONX

UEPDATX

X

UBYCTHX

UBYCTLX

5

UEPSTA5

UEPCON5

UEPDAT5

Endpoint 5

UBYCTH5

UBYCTL5

UEPNUM

• Endpoint enable

Before using an endpoint, this one will be enabled by setting the EPEN bit in the UEPCONX

register.

An endpoint which is not enabled won’t answer to any USB request. The Default Control

Endpoint (Endpoint 0) will always be enabled in order to answer to USB standard requests.

• Endpoint type configuration

All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode.

The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous mode. The

configuration of an endpoint is performed by setting the field EPTYPE with the following

values:

– Control:EPTYPE = 00b

– Isochronous:EPTYPE = 01b

– Bulk:EPTYPE = 10b

– Interrupt:EPTYPE = 11b

104

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

The Endpoint 0 is the Default Control Endpoint and will always be configured in Control type.

• Endpoint direction configuration

For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of

the UEPCONX register with the following values:

– IN:EPDIR = 1b

– OUT:EPDIR = 0b

For Control endpoints, the EPDIR bit has no effect.

• Summary of Endpoint Configuration:

Do not forget to select the correct endpoint number in the UEPNUM register before access-

ing to endpoint specific registers.

Table 21-1. Summary of Endpoint Configuration

Endpoint Configuration

EPEN

EPDIR

Xb

EPTYPE

XXb

00b

UEPCONX

0XXX XXXb

80h

Disabled

0b

Control

1b

Xb

Bulk-in

1b

10b

86h

Bulk-out

1b

0b

10b

82h

Interrupt-In

1b

11b

87h

Interrupt-Out

Isochronous-In

Isochronous-Out

• Endpoint FIFO reset

1b

0b

11b

83h

1b

01b

85h

1b

0b

01b

81h

Before using an endpoint, its FIFO will be reset. This action resets the FIFO pointer to its

original value, resets the byte counter of the endpoint (UBYCTLX and UBYCTHX registers),

and resets the data toggle bit (DTGL bit in UEPCONX).

The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corre-

sponding bit in the UEPRST register.

For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000

0000b in the UEPRST register.

Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints.

21.3 Read/Write Data FIFO

21.3.1

FIFO Mapping

Depending on the selected endpoint through the UEPNUM register, the UEPDATX register

allows to access the corresponding endpoint data fifo.

105

7683C–USB–11/07

Figure 21-6. Endpoint FIFO Configuration

UEPSTA0

UEPCON0

UEPDAT0

0

Endpoint 0

SFR registers

UBYCTH0

UBYCTL0

1

2

3

4

UEPSTAX

UEPCONX

UEPDATX

X

UBYCTHX

UBYCTLX

5

UEPSTA5

UEPCON5

UEPDAT5

Endpoint 5

UBYCTH5

UBYCTL5

UEPNUM

21.3.2

Read Data FIFO

The read access for each OUT endpoint is performed using the UEPDATX register.

After a new valid packet has been received on an Endpoint, the data are stored into the FIFO

and the byte counter of the endpoint is updated (UBYCTLX and UBYCTHX registers). The firm-

ware has to store the endpoint byte counter before any access to the endpoint FIFO. The byte

counter is not updated when reading the FIFO.

To read data from an endpoint, select the correct endpoint number in UEPNUM and read the

UEPDATX register. This action automatically decreases the corresponding address vector, and

the next data is then available in the UEPDATX register.

21.3.3

Write Data FIFO

The write access for each IN endpoint is performed using the UEPDATX register.

To write a byte into an IN endpoint FIFO, select the correct endpoint number in UEPNUM and

write into the UEPDATX register. The corresponding address vector is automatically increased,

and another write can be carried out.

Warning 1: The byte counter is not updated.

Warning 2: Do not write more bytes than supported by the corresponding endpoint.

21.4 Bulk/Interrupt Transactions

Bulk and Interrupt transactions are managed in the same way.

106

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

21.4.1

Bulk/Interrupt OUT Transactions in Standard Mode

Figure 21-7. Bulk/Interrupt OUT transactions in Standard Mode

HOST

UFI

C51

OUT DATA0 (n bytes)

ACK

RXOUTB0

Endpoint FIFO read byte 1

Endpoint FIFO read byte 2

OUT DATA1

NAK

Endpoint FIFO read byte n

Clear RXOUTB0

DATA1

OUT

ACK

RXOUTB0

Endpoint FIFO read byte 1

An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt

packets.

When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB con-

troller. This triggers an interrupt if enabled. The firmware has to select the corresponding

endpoint, store the number of data bytes by reading the UBYCTLX and UBYCTHX registers. If

the received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register val-

ues are equal to 0 and no data has to be read.

When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUTB0 bit to

allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0 bit

has been cleared by the firmware, the USB controller will answer a NAK handshake for each

OUT requests.

If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be

stored, but the USB controller will consider that the packet is valid if the CRC is correct and the

endpoint byte counter contains the number of bytes sent by the Host.

107

7683C–USB–11/07

21.4.2

Bulk/Interrupt OUT Transactions in Ping-pong Mode

Figure 21-8. Bulk/Interrupt OUT Transactions in Ping-pong Mode

HOST

UFI

C51

OUT DATA0 (n Bytes)

ACK

RXOUTB0

Endpoint FIFO Bank 0 - Read Byte 1

Endpoint FIFO Bank 0 - Read Byte 2

DATA1 (m Bytes)

OUT

ACK

Endpoint FIFO Bank 0 - Read Byte n

Clear RXOUTB0

RXOUTB1

OUT DATA0 (p Bytes)

Endpoint FIFO Bank 1 - Read Byte 1

Endpoint FIFO Bank 1 - Read Byte 2

Endpoint FIFO Bank 1 - Read Byte m

Clear RXOUTB1

RXOUTB0

Endpoint FIFO Bank 0 - Read Byte 1

Endpoint FIFO Bank 0 - Read Byte 2

Endpoint FIFO Bank 0 - Read Byte p

Clear RXOUTB0

An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt

packets.

When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the

USB controller. This triggers an interrupt if enabled. The firmware has to select the correspond-

ing endpoint, store the number of data bytes by reading the UBYCTLX and UBYCTHX registers.

If the received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register val-

ues are equal to 0 and no data has to be read.

When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUB0 bit to

allow the USB controller to accept the next OUT packet on the endpoint bank 0. This action

switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware,

the USB controller will answer a NAK handshake for each OUT requests on the bank 0 endpoint

FIFO.

When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by

the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 end-

point FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the

firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 1

endpoint FIFO.

The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new valid

packet receipt.

The firmware has to clear one of these two bits after having read all the data FIFO to allow a new

valid packet to be stored in the corresponding bank.

108

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released

by the firmware.

If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be

stored, but the USB controller will consider that the packet is valid if the CRC is correct.

21.4.3

Bulk/Interrupt IN Transactions in Standard Mode

Figure 21-9. Bulk/Interrupt IN Transactions in Standard Mode

HOST

UFI

C51

Endpoint FIFO Write Byte 1

Endpoint FIFO Write Byte 2

IN

NAK

Endpoint FIFO Write Byte n

Set TXRDY

IN

DATA0 (n Bytes)

ACK

TXCMPL

Clear TXCMPL

Endpoint FIFO Write Byte 1

An endpoint will be first enabled and configured before being able to send Bulk or Interrupt

packets.

The firmware will fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX

register to allow the USB controller to send the data stored in FIFO at the next IN request con-

cerning this endpoint. To send a Zero Length Packet, the firmware will set the TXRDY bit without

writing any data into the endpoint FIFO.

Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK hand-

shake for each IN requests.

To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The packet stored

in the endpoint FIFO is then cleared and a new packet can be written and sent.

When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in the UEP-

STAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware

will clear the TXCMPL bit before filling the endpoint FIFO with new data.

The firmware will never write more bytes than supported by the endpoint FIFO.

All USB retry mechanisms are automatically managed by the USB controller.

109

7683C–USB–11/07

21.4.4

Bulk/Interrupt IN Transactions in Ping-pong Mode

Figure 21-10. Bulk/Interrupt IN Transactions in Ping-pong Mode

HOST

UFI

C51

Endpoint FIFO Bank 0 - Write Byte 1

Endpoint FIFO Bank 0 - Write Byte 2

IN

NACK

Endpoint FIFO Bank 0 - Write Byte n

Set TXRDY

IN

Endpoint FIFO Bank 1 - Write Byte 1

Endpoint FIFO Bank 1 - Write Byte 2

DATA0 (n Bytes)

ACK

Endpoint FIFO Bank 1 - Write Byte m

Clear TXCMPL

TXCMPL

Set TXRDY

IN

Endpoint FIFO Bank 0 - Write Byte 1

Endpoint FIFO Bank 0 - Write Byte 2

DATA1 (m Bytes)

ACK

Endpoint FIFO Bank 0 - Write Byte p

Clear TXCMPL

TXCMPL

Set TXRDY

IN

Endpoint FIFO Bank 1 - Write Byte 1

DATA0 (p Bytes)

ACK

An endpoint will be first enabled and configured before being able to send Bulk or Interrupt

packets.

The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEP-

STAX register to allow the USB controller to send the data stored in FIFO at the next IN request

concerning the endpoint. The FIFO banks are automatically switched, and the firmware can

immediately write into the endpoint FIFO bank 1.

When the IN packet concerning the bank 0 has been sent and acknowledged by the Host, the

TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware

will clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks

are then automatically switched.

When the IN packet concerning the bank 1 has been sent and acknowledged by the Host, the

TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware

will clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data.

The bank switch is performed by the USB controller each time the TXRDY bit is set by the firm-

ware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller

will answer a NAK handshake for each IN requests concerning this bank.

Note that in the example above, the firmware clears the Transmit Complete bit (TXCMPL) before

setting the Transmit Ready bit (TXRDY). This is done in order to avoid the firmware to clear at

the same time the TXCMPL bit for bank 0 and the bank 1.

110

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

The firmware will never write more bytes than supported by the endpoint FIFO.

21.5 Control Transactions

21.5.1

Setup Stage

The DIR bit in the UEPSTAX register will be at 0.

Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP

bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate

that an Out packet with a Setup PID has been received on the Control endpoint. When the

RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an inter-

rupt is triggered if enabled.

The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing

the RXSETUP bit to free the endpoint FIFO for the next transaction.

21.5.2

Data Stage: Control Endpoint Direction

The data stage management is similar to Bulk management.

A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All

other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to

specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX regis-

ter.

The firmware has to use the DIR bit before data IN in order to meet the data-toggle

requirements:

• If the data stage consists of INs,

the firmware has to set the DIR bit in the UEPSTAX register before writing into the FIFO and

sending the data by setting to 1 the TXRDY bit in the UEPSTAX register. The IN transaction

is complete when the TXCMPL has been set by the hardware. The firmware will clear the

TXCMPL bit before any other transaction.

• If the data stage consists of OUTs,

the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware when a new

valid packet has been received on the endpoint. The firmware must read the data stored into

the FIFO and then clear the RXOUTB0 bit to reset the FIFO and to allow the next transaction.

To send a STALL handshake, see “STALL Handshake” on page 114.

21.5.3

Status Stage

The DIR bit in the UEPSTAX register will be reset at 0 for IN and OUT status stage.

The status stage management is similar to Bulk management.

• For a Control Write transaction or a No-Data Control transaction, the status stage consists of

a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions in Standard Mode” on page

109). To send a STALL handshake, see “STALL Handshake” on page 114.

• For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see

“Bulk/Interrupt OUT Transactions in Standard Mode” on page 107).

111

7683C–USB–11/07

21.6 Isochronous Transactions

21.6.1

Isochronous OUT Transactions in Standard Mode

An endpoint will be first enabled and configured before being able to receive Isochronous

packets.

When a OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller.

This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint,

store the number of data bytes by reading the UBYCTLX and UBYCTHX registers. If the

received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register values

are equal to 0 and no data has to be read.

The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in

FIFO has a corrupted CRC. This bit is updated after each new packet receipt.

When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUTB0 bit to

allow the USB controller to store the next OUT packet data into the endpoint FIFO. Until the

RXOUTB0 bit has been cleared by the firmware, the data sent by the Host at each OUT transac-

tion will be lost.

If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will store only

the remaining bytes into the FIFO.

If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be

stored, but the USB controller will consider that the packet is valid if the CRC is correct.

21.6.2

Isochronous OUT Transactions in Ping-pong Mode

An endpoint will be first enabled and configured before being able to receive Isochronous

packets.

When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB

controller. This triggers an interrupt if enabled. The firmware has to select the corresponding

endpoint, store the number of data bytes by reading the UBYCTLX and UBYCTHX registers. If

the received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register val-

ues are equal to 0 and no data has to be read.

The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in

FIFO has a corrupted CRC. This bit is updated after each new packet receipt.

When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUB0 bit to

allow the USB controller to store the next OUT packet data into the endpoint FIFO bank 0. This

action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firm-

ware, the data sent by the Host on the bank 0 endpoint FIFO will be lost.

If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the USB

controller will store only the remaining bytes into the FIFO.

When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the

USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint

FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firm-

ware, the data sent by the Host on the bank 1 endpoint FIFO will be lost.

The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new

packet receipt.

112

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

The firmware has to clear one of these two bits after having read all the data FIFO to allow a new

packet to be stored in the corresponding bank.

If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be

stored, but the USB controller will consider that the packet is valid if the CRC is correct.

21.6.3

Isochronous IN Transactions in Standard Mode

An endpoint will be first enabled and configured before being able to send Isochronous packets.

The firmware will fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX

register to allow the USB controller to send the data stored in FIFO at the next IN request con-

cerning this endpoint.

If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB

controller.

When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB

controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit

before filling the endpoint FIFO with new data.

The firmware will never write more bytes than supported by the endpoint FIFO

21.6.4

Isochronous IN Transactions in Ping-pong Mode

An endpoint will be first enabled and configured before being able to send Isochronous packets.

The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEP-

STAX register to allow the USB controller to send the data stored in FIFO at the next IN request

concerning the endpoint. The FIFO banks are automatically switched, and the firmware can

immediately write into the endpoint FIFO bank 1.

If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB

controller.

When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the USB

controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit

before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically

switched.

When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the USB

controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit

before filling the endpoint FIFO bank 1 with new data.

The bank switch is performed by the USB controller each time the TXRDY bit is set by the firm-

ware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller

won’t send anything at each IN requests concerning this bank.

The firmware will never write more bytes than supported by the endpoint FIFO.

21.7 Miscellaneous

21.7.1

USB Reset

The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been

detected on the USB bus. This triggers a USB interrupt if enabled. The USB controller is still

enabled, but all the USB registers are reset by hardware. The firmware will clear the EORINT bit

to allow the next USB reset detection.

113

7683C–USB–11/07

21.7.2

STALL Handshake

This function is only available for Control, Bulk, and Interrupt endpoints.

The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake

at the next request of the Host on the endpoint selected with the UEPNUM register. The

RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first reset to 0. The bit

STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an inter-

rupt if enabled.

The firmware will clear the STALLRQ and STLCRC bits after each STALL sent.

The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on

a CONTROL type endpoint.

Important note: when a Clear Halt Feature occurs for an endpoint, the firmware will reset this

endpoint using the UEPRST register in order to reset the data toggle management.

21.7.3

21.7.4

Start of Frame Detection

The SOFINT bit in the USBINT register is set when the USB controller detects a Start of Frame

PID. This triggers an interrupt if enabled. The firmware will clear the SOFINT bit to allow the next

Start of Frame detection.

Frame Number

When receiving a Start of Frame, the frame number is automatically stored in the UFNUML and

UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start of

Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The UFNUML and UFNUMH

registers are automatically updated when receiving a new Start of Frame.

21.7.5

Data Toggle Bit

The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted by the

USB controller and cleared by hardware when a DATA1 packet is received and accepted by the

USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST

register.

For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling is then

used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Sta-

tus stage completes the data transfer with a DATA1 (for a control read transfer).

For Isochronous endpoints, the device firmware will ignore the data-toggle.

21.8 Suspend/Resume Management

21.8.1

Suspend

The Suspend state can be detected by the USB controller if all the clocks are enabled and if the

USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for

more than 3 ms. This triggers a USB interrupt if enabled.

In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop

the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active.

The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new

suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSP-

CLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-

up event is detected.

114

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

The stop of the 48 MHz clock from the PLL should be done in the following order:

1. Clear suspend interrupt bit in USBINT (required to allow the USB pads to enter power

down mode).

2. Enable USB resume interrupt.

3. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit

in the USBCON register.

4. Disable the PLL by clearing the PLLEN bit in the PLLCON register.

5. Make the CPU core enter power down mode by setting PDOWN bit in PCON.

21.8.2

Resume

When the USB controller is in Suspend state, the Resume detection is active even if all the

clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by

hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled.

This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is

then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the

SUSPCLK bit in the USBCON register if needed.

The firmware has to clear the SPINT bit in the USBINT register before any other USB operation

in order to wake up the USB controller from its Suspend mode.

The USB controller is then re-activated.

Figure 21-11. Example of a Suspend/Resume Management

USB Controller Init

SPINT

Detection of a SUSPEND State

Clear SPINT

Set SUSPCLK

Disable PLL

microcontroller in Power-down

WUPCPU

Detection of a RESUME State

Enable PLL

Clear SUSPCLK

Clear WUPCPU Bit

115

7683C–USB–11/07

21.8.3

Upstream Resume

A USB device can be allowed by the Host to send an upstream resume for Remote Wake Up

purpose.

When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP,

the firmware will set to 1 the RMWUPE bit in the USBCON register to enable this functionality.

RMWUPE value will be 0 in the other cases.

If the device is in SUSPEND mode, the USB controller can send an upstream resume by clear-

ing first the SPINT bit in the USBINT register and by setting then to 1 the SDRMWUP bit in the

USBCON register. The USB controller sets to 1 the UPRSM bit in the USBCON register. All

clocks must be enabled first. The Remote Wake is sent only if the USB bus was in Suspend

state for at least 5 ms. When the upstream resume is completed, the UPRSM bit is reset to 0 by

hardware. The firmware will then clear the SDRMWUP bit.

Figure 21-12. Example of REMOTE WAKEUP Management

USB Controller Init

SET_FEATURE: DEVICE_REMOTE_WAKEUP

Set RMWUPE

SPINT

Detection of a SUSPEND State

Suspend Management

Need USB Resume

Enable Clocks

Clear SPINT

Set SDMWUP

UPRSM = 1

UPRSM

Upstream RESUME Sent

Clear SDRMWUP

116

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

21.9 Detach Simulation

In order to be re-enumerated by the Host, the AT83C5134/35/36 has the possibility to simulate a

DETACH - ATTACH of the USB bus.

The V_REFoutput voltage is between 3.0V and 3.6V. This output can be connected to the D+ pull-

up as shown in Figure 21-13. This output can be put in high-impedance when the DETACH bit is

set to 1 in the USBCON register. Maintaining this output in high impedance for more than 3 µs

will simulate the disconnection of the device. When resetting the DETACH bit, an attach is then

simulated.

Figure 21-13. Example of V_REFConnection

V_REF

1.5 kW

1

V_CC

2

D-

3

4

D+

GND

USB-B Connector

AT89C5131

Figure 21-14. Disconnect Timing

D+

V

_IHZ(min)

V_IL

D-

V_SS

> = 2,5 ms

Disconnect

Detected

Device

Disconnected

21.10 USB Interrupt System

21.10.1 Interrupt System Priorities

Figure 21-15. USB Interrupt Control System

00

01

10

11

D+

D-

USB

Controller

EUSB

IE1.6

EA

IE0.7

IPH/L

Interrupt Enable

Priority Enable

Lowest Priority Interrupts

117

7683C–USB–11/07

Table 21-2. Priority Levels

IPHUSB

IPLUSB

USB Priority Level

0

1

0

1

0

1

0

1

2

3

Lowest

Highest

21.10.2 USB Interrupt Control System

As shown in Figure 21-16, many events can produce a USB interrupt:

• TXCMPL: Transmitted In Data (see Table 21-9 on page 125). This bit is set by hardware

when the Host accept a In packet.

• RXOUTB0: Received Out Data Bank 0 (see Table 21-9 on page 125). This bit is set by

hardware when an Out packet is accepted by the endpoint and stored in bank 0.

• RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (see Table 21-9 on

page 125). This bit is set by hardware when an Out packet is accepted by the endpoint and

stored in bank 1.

• RXSETUP: Received Setup (see Table 21-9 on page 125). This bit is set by hardware when

an SETUP packet is accepted by the endpoint.

• STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (see Table 21-9 on page

125). This bit is set by hardware when a STALL handshake has been sent as requested by

STALLRQ, and is reset by hardware when a SETUP packet is received.

• SOFINT: Start of Frame Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global

Interrupt Enable Register” on page 122.). This bit is set by hardware when a USB Start of

Frame packet has been received.

• WUPCPU: Wake-Up CPU Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global

Interrupt Enable Register” on page 122.). This bit is set by hardware when a USB resume is

detected on the USB bus, after a SUSPEND state.

• SPINT: Suspend Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global Interrupt

Enable Register” on page 122.). This bit is set by hardware when a USB suspend is detected

on the USB bus.

118

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Figure 21-16. USB Interrupt Control Block Diagram

Endpoint X (X = 0..5)

TXCMP

UEPSTAX.0

RXOUTB0

UEPSTAX.1

EPXINT

UEPINT.X

RXOUTB1

UEPSTAX.6

EPXIE

UEPIEN.X

RXSETUP

UEPSTAX.2

STLCRC

UEPSTAX.3

WUPCPU

USBINT.5

EUSB

IE1.6

EWUPCPU

USBIEN.5

EORINT

USBINT.4

EEORINT

USBIEN.4

SOFINT

USBINT.3

ESOFINT

USBIEN.3

SPINT

USBINT.0

ESPINT

USBIEN.0

119

7683C–USB–11/07

21.11 USB Registers

Table 21-3. USBCON Register

USBCON (S:BCh)

USB Global Control Register

7

6

5

4

3

2

1

0

USBE

SUSPCLK

SDRMWUP

DETACH

UPRSM

RMWUPE

CONFG

FADDEN

Bit Number

Bit Mnemonic

Description

USB Enable

Set this bit to enable the USB controller.

7

USBE

Clear this bit to disable and reset the USB controller, to disable the USB

transceiver an to disable the USB controller clock inputs.

Suspend USB Clock

Set this bit to disable the 48 MHz clock input (Resume Detection is still active).

Clear this bit to enable the 48 MHz clock input.

6

5

SUSPCLK

Send Remote Wake Up

Set this bit to force an external interrupt on the USB controller for Remote Wake

UP purpose.

SDRMWUP

An upstream resume is send only if the bit RMWUPE is set, all USB clocks are

enabled AND the USB bus was in SUSPEND state for at least 5 ms. See UPRSM

below.

This bit is cleared by software.

Detach Command

Set this bit to simulate a Detach on the USB line. The V_REFpin is then in a floating

state.

Clear this bit to maintain V_REFat high level.

4

3

DETACH

UPRSM

Upstream Resume (read only)

This bit is set by hardware when SDRMWUP has been set and if RMWUPE is

enabled.

This bit is cleared by hardware after the upstream resume has been sent.

Remote Wake-Up Enable

Set this bit to enabled request an upstream resume signaling to the host.

Clear this bit otherwise.

2

RMWUPE

Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP

feature for the device.

Configured

This bit will be set by the device firmware after a SET_CONFIGURATION request

with a non-zero value has been correctly processed.

1

CONFG

It will be cleared by the device firmware when a SET_CONFIGURATION request

with a zero value is received. It is cleared by hardware on hardware reset or when

an USB reset is detected on the bus (SE0 state for at least 32 Full Speed bit times:

typically 2.7 µs).

Function Address Enable

This bit will be set by the device firmware after a successful status phase of a

SET_ADDRESS transaction.

0

FADDEN

It will not be cleared afterwards by the device firmware. It is cleared by hardware

on hardware reset or when an USB reset is received (see above). When this bit is

cleared, the default function address is used (0).

Reset Value = 00h

120

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 21-4. USBINT Register

USBINT (S:BDh)

USB Global Interrupt Register

7

-

6

-

5

4

3

2

-

1

-

0

WUPCPU

EORINT

SOFINT

SPINT

Bit

Bit Number Mnemonic Description

Reserved

7-6

-

The value read from these bits is always 0. Do not set these bits.

Wake Up CPU Interrupt

This bit is set by hardware when the USB controller is in SUSPEND state and is re-

activated by a non-idle signal FROM USB line (not by an upstream resume). This

triggers a USB interrupt when EWUPCPU is set in Table 21-5 on page 122.

When receiving this interrupt, user has to enable all USB clock inputs.

This bit will be cleared by software (USB clocks must be enabled before).

5

WUPCPU

End Of Reset Interrupt

This bit is set by hardware when a End Of Reset has been detected by the USB

controller. This triggers a USB interrupt when EEORINT is set (see Figure 21-5 on page

122).

4

3

EORINT

SOFINT

This bit will be cleared by software.

Start of Frame Interrupt

This bit is set by hardware when an USB Start of Frame PID (SOF) has been detected.

This triggers a USB interrupt when ESOFINT is set (see Table 21-5 on page 122).

This bit will be cleared by software.

Reserved

The value read from this bit is always 0. Do not set this bit.

2

1

-

Reserved

The value read from this bit is always 0. Do not set this bit.

Suspend Interrupt

This bit is set by hardware when a USB Suspend (Idle bus for three frame periods: a J

state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in see

Table 21-5 on page 122.

0

SPINT

This bit will be cleared by software BEFORE any other USB operation to re-activate the

macro.

Reset Value = 00h

121

7683C–USB–11/07

Table 21-5. USBIEN Register

USBIEN (S:BEh)

USB Global Interrupt Enable Register

7

-

6

-

5

4

3

2

-

1

-

0

EWUPCPU

EEORINT

ESOFINT

ESPINT

Bit Number

Bit Mnemonic Description

Reserved

The value read from these bits is always 0. Do not set these bits.

7-6

-

Enable Wake Up CPU Interrupt

Set this bit to enable Wake Up CPU Interrupt. (See “USBIEN Register USBIEN

(S:BEh) USB Global Interrupt Enable Register” on page 122.)

Clear this bit to disable Wake Up CPU Interrupt.

5

4

3

EWUPCPU

EEOFINT

ESOFINT

Enable End Of Reset Interrupt

Set this bit to enable End Of Reset Interrupt. (See “USBIEN Register USBIEN

(S:BEh) USB Global Interrupt Enable Register” on page 122.). This bit is set after

reset.

Clear this bit to disable End Of Reset Interrupt.

Enable SOF Interrupt

Set this bit to enable SOF Interrupt. (See “USBIEN Register USBIEN (S:BEh) USB

Global Interrupt Enable Register” on page 122.).

Clear this bit to disable SOF Interrupt.

2

1

-

Reserved

The value read from these bits is always 0. Do not set these bits.

Enable Suspend Interrupt

Set this bit to enable Suspend Interrupts (see the “USBIEN Register USBIEN

(S:BEh) USB Global Interrupt Enable Register” on page 122).

Clear this bit to disable Suspend Interrupts.

0

ESPINT

Reset Value = 10h

122

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 21-6. USBADDR Register

USBADDR (S:C6h)

USB Address Register

7

6

5

4

3

2

1

0

FEN

UADD6

UADD5

UADD4

UADD3

UADD2

UADD1

UADD0

Bit

Bit Number Mnemonic Description

Function Enable

7

FEN

Set this bit to enable the address filtering function.

Cleared this bit to disable the function.

USB Address

This field contains the default address (0) after power-up or USB bus reset.

6-0

UADD[6:0]

It will be written with the value set by a SET_ADDRESS request received by the device

firmware.

Reset Value = 80h

Table 21-7. UEPNUM Register

UEPNUM (S:C7h)

USB Endpoint Number

7

-

6

-

5

-

4

-

3

2

1

0

EPNUM3

EPNUM2

EPNUM1

EPNUM0

Bit Number

Bit Mnemonic Description

Reserved

The value read from these bits is always 0. Do not set these bits.

7-4

-

Endpoint Number

Set this field with the number of the endpoint which will be accessed when reading

or writing to, UEPDATX Register UEPDATX (S:CFh) USB FIFO Data Endpoint X (X

= EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number),

UBYCTLX Register UBYCTLX (S:E2h) USB Byte Count Low Register X (X =

EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number),

UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High Register X (X =

EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number) or

UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register. This

value can be 0, 1, 2, 3, 4, or 5.

3-0

EPNUM[3:0]

Reset Value = 00h

123

7683C–USB–11/07

Table 21-8. UEPCONX Register

UEPCONX (S:D4h)

USB Endpoint X Control Register

7

6

-

5

-

4

-

3

2

1

0

EPEN

DTGL

EPDIR

EPTYPE1

EPTYPE0

Bit Number Bit Mnemonic Description

Endpoint Enable

Set this bit to enable the endpoint according to the device configuration. Endpoint 0 will

always be enabled after a hardware or USB bus reset and participate in the device

configuration.

7

EPEN

Clear this bit to disable the endpoint according to the device configuration.

Reserved

6

5

4

-

The value read from this bit is always 0. Do not set this bit.

Reserved

The value read from this bit is always 0. Do not set this bit.

Reserved

The value read from this bit is always 0. Do not set this bit.

Data Toggle (Read-only)

3

2

DTGL

This bit is set by hardware when a valid DATA0 packet is received and accepted.

This bit is cleared by hardware when a valid DATA1 packet is received and accepted.

Endpoint Direction

Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.

Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.

This bit has no effect for Control endpoints.

EPDIR

Endpoint Type

Set this field according to the endpoint configuration (Endpoint 0 will always be

configured as control):

1-0

EPTYPE[1:0] 00Control endpoint

01Isochronous endpoint

10Bulk endpoint

11Interrupt endpoint

Note:

1. (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number)

Reset Value = 80h when UEPNUM = 0 (default Control Endpoint)

Reset Value = 00h otherwise for all other endpoints

124

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 21-9. UEPSTAX (S:CEh) USB Endpoint X Status Register

7

6

5

4

3

2

1

0

DIR

RXOUTB1

STALLRQ

TXRDY

STL/CRC

RXSETUP

RXOUTB0

TXCMP

Bit

Mnemonic Description

Bit Number

Control Endpoint Direction

This bit is used only if the endpoint is configured in the control type (seeSection “UEPCONX Register UEPCONX (S:D4h)

USB Endpoint X Control Register”).

This bit determines the Control data and status direction.

7

DIR

The device firmware will set this bit ONLY for the IN data stage, before any other USB operation. Otherwise, the device

firmware will clear this bit.

Received OUT Data Bank 1 for Endpoints 4, 5 and 6 (Ping-pong mode)

This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 1 (only in Ping-pong

mode). Then, the endpoint interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB

Endpoint Interrupt Register” on page 128) and all the following OUT packets to the endpoint bank 1 are rejected (NAK’ed)

until this bit has been cleared, excepted for Isochronous Endpoints.

6

5

RXOUTB1

This bit will be cleared by the device firmware after reading the OUT data from the endpoint FIFO.

Stall Handshake Request

STALLRQ Set this bit to request a STALL answer to the host for the next handshake.Clear this bit otherwise.

For CONTROL endpoints: cleared by hardware when a valid SETUP PID is received.

TX Packet Ready

Set this bit after a packet has been written into the endpoint FIFO for IN data transfers. Data will be written into the

endpoint FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Zero

Length Packet.

4

TXRDY

This bit is cleared by hardware, as soon as the packet has been sent for Isochronous endpoints, or after the host has

acknowledged the packet for Control, Bulk and Interrupt endpoints. When this bit is cleared, the endpoint interrupt is

triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on page 128).

Stall Sent/CRC error flag

- For Control, Bulk and Interrupt Endpoints:

This bit is set by hardware after a STALL handshake has been sent as requested by STALLRQ. Then, the endpoint

interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on

page 128)

3

STLCRC

It will be cleared by the device firmware.

- For Isochronous Endpoints (Read-Only)

:

This bit is set by hardware if the last received data is corrupted (CRC error on data).

This bit is updated by hardware when a new data is received.

Received SETUP

This bit is set by hardware when a valid SETUP packet has been received from the host. Then, all the other bits of the

2

1

0

RXSETUP register are cleared by hardware and the endpoint interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h

read-only) USB Endpoint Interrupt Register” on page 128).

It will be cleared by the device firmware after reading the SETUP data from the endpoint FIFO.

Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints)

This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the endpoint

interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on

RXOUTB0 page 128) and all the following OUT packets to the endpoint bank 0 are rejected (NAK’ed) until this bit has been cleared,

excepted for Isochronous Endpoints. However, for control endpoints, an early SETUP transaction may overwrite the

content of the endpoint FIFO, even if its Data packet is received while this bit is set.

This bit will be cleared by the device firmware after reading the OUT data from the endpoint FIFO.

Transmitted IN Data Complete

This bit is set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been

TXCMPL

accepted (ACK’ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if

enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on page 128).

This bit will be cleared by the device firmware before setting TXRDY.

Reset Value = 00h

125

7683C–USB–11/07

Table 21-10. UEPDATX Register

UEPDATX (S:CFh)

USB FIFO Data Endpoint X (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number)

7

6

5

4

3

2

1

0

FDAT7

FDAT6

FDAT5

FDAT4

FDAT3

FDAT2

FDAT1

FDAT0

Bit Number

Bit Mnemonic Description

Endpoint X FIFO data

Data byte to be written to FIFO or data byte to be read from the FIFO, for the Endpoint X (see EPNUM).

7 - 0

FDAT[7:0]

Reset Value = XXh

Table 21-11. UBYCTLX Register

UBYCTLX (S:E2h)

USB Byte Count Low Register X (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number)

7

6

5

4

3

2

1

0

BYCT7

BYCT6

BYCT5

BYCT4

BYCT3

BYCT2

BYCT1

BYCT0

Bit Number

Bit Mnemonic Description

Byte Count LSB

Least Significant Byte of the byte count of a received data packet. The most significant part is provided by the

UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High Register X (X = EPNUM set in UEPNUM Register

UEPNUM (S:C7h) USB Endpoint Number) (see Figure 21-11 on page 126). This byte count is equal to the

number of data bytes received after the Data PID.

7 - 0

BYCT[7:0]

Reset Value = 00h

Table 21-12. UBYCTHX Register

UBYCTHX (S:E3h)

USB Byte Count High Register X (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number)

7

-

6

-

5

-

4

-

3

-

2

-

1

0

BYCT9

BYCT8

Bit Number

Bit Mnemonic

Description

Reserved

7-2

-

The value read from these bits is always 0. Do not set these bits.

Byte Count MSB

Most Significant Byte of the byte count of a received data packet. The Least significant part is provided by

UBYCTLX Register UBYCTLX (S:E2h) USB Byte Count Low Register X (X = EPNUM set in UEPNUM

Register UEPNUM (S:C7h) USB Endpoint Number) (see Figure 21-11 on page 126).

2-0

BYCT[10:8]

Reset Value = 00h

126

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 21-13. UEPRST Register

UEPRST (S:D5h)

USB Endpoint FIFO Reset Register

7

-

6

-

5

4

3

2

1

0

EP5RST

EP4RST

EP3RST

EP2RST

EP1RST

EP0RST

Bit

Bit Number Mnemonic Description

Reserved

7

6

-

The value read from this bit is always 0. Do not set this bit.

Reserved

The value read from this bit is always 0. Do not set this bit.

Endpoint 5 FIFO Reset

Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset

or when an USB bus reset has been received.

Then, clear this bit to complete the reset operation and start using the FIFO.

5

4

3

2

1

0

EP5RST

EP4RST

EP3RST

EP2RST

EP1RST

EP0RST

Endpoint 4 FIFO Reset

Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset

or when an USB bus reset has been received.

Then, clear this bit to complete the reset operation and start using the FIFO.

Endpoint 3 FIFO Reset

Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset

or when an USB bus reset has been received.

Then, clear this bit to complete the reset operation and start using the FIFO.

Endpoint 2 FIFO Reset

Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset

or when an USB bus reset has been received.

Then, clear this bit to complete the reset operation and start using the FIFO.

Endpoint 1 FIFO Reset

Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset

or when an USB bus reset has been received.

Then, clear this bit to complete the reset operation and start using the FIFO.

Endpoint 0 FIFO Reset

Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset

or when an USB bus reset has been received.

Then, clear this bit to complete the reset operation and start using the FIFO.

Reset Value = 00h

127

7683C–USB–11/07

Table 21-14. UEPINT Register

UEPINT (S:F8h read-only)

USB Endpoint Interrupt Register

7

-

6

-

5

4

3

2

1

0

EP5INT

EP4INT

EP3INT

EP2INT

EP1INT

EP0INT

Bit

Bit Number Mnemonic Description

Reserved

7

6

-

The value read from this bit is always 0. Do not set this bit.

Reserved

The value read from this bit is always 0. Do not set this bit.

Endpoint 5 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 5. The endpoint interrupt sources are in the UEPSTAX register and can be:

TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

5

4

3

2

1

0

EP5INT

EP4INT

EP3INT

EP2INT

EP1INT

EP0INT

A USB interrupt is triggered when the EP5IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

Endpoint 4 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 4. The endpoint interrupt sources are in the UEPSTAX register and can be:

TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP4IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

Endpoint 3 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 3. The endpoint interrupt sources are in the UEPSTAX register and can be:

TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP3IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

Endpoint 2 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 2. The endpoint interrupt sources are in the UEPSTAX register and can be:

TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

Endpoint 1 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 1. The endpoint interrupt sources are in the UEPSTAX register and can be:

TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

Endpoint 0 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 0. The endpoint interrupt sources are in the UEPSTAX register and can be:

TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

Reset Value = 00h

128

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 21-15. UEPIEN Register

UEPIEN (S:C2h)

USB Endpoint Interrupt Enable Register

7

-

6

-

5

4

3

2

1

0

EP5INTE

EP4INTE

EP3INTE

EP2INTE

EP1INTE

EP0INTE

Bit

Bit Number Mnemonic Description

Reserved

7

6

-

The value read from this bit is always 0. Do not set this bit.

Reserved

The value read from this bit is always 0. Do not set this bit.

Endpoint 5 Interrupt Enable

Set this bit to enable the interrupts for this endpoint.

Clear this bit to disable the interrupts for this endpoint.

5

4

3

2

1

0

EP5INTE

EP4INTE

EP3INTE

EP2INTE

EP1INTE

EP0INTE

Endpoint 4 Interrupt Enable

Set this bit to enable the interrupts for this endpoint.

Clear this bit to disable the interrupts for this endpoint.

Endpoint 3 Interrupt Enable

Set this bit to enable the interrupts for this endpoint.

Clear this bit to disable the interrupts for this endpoint.

Endpoint 2 Interrupt Enable

Set this bit to enable the interrupts for this endpoint.

Clear this bit to disable the interrupts for this endpoint.

Endpoint 1 Interrupt Enable

Set this bit to enable the interrupts for this endpoint.

Clear this bit to disable the interrupts for this endpoint.

Endpoint 0 Interrupt Enable

Set this bit to enable the interrupts for this endpoint.

Clear this bit to disable the interrupts for this endpoint.

Reset Value = 00h

129

7683C–USB–11/07

Table 21-16. UFNUMH Register

UFNUMH (S:BBh, read-only)

USB Frame Number High Register

7

-

6

-

5

4

3

-

2

1

0

CRCOK

CRCERR

FNUM10

FNUM9

FNUM8

Bit

Number Bit Mnemonic Description

Frame Number CRC OK

This bit is set by hardware when a new Frame Number in Start of Frame Packet is

received without CRC error.

5

CRCOK

This bit is updated after every Start of Frame packet receipt.

Important note: the Start of Frame interrupt is generated just after the PID receipt.

Frame Number CRC Error

This bit is set by hardware when a corrupted Frame Number in Start of Frame packet is

received.

4

3

CRCERR

This bit is updated after every Start of Frame packet receipt.

Important note: the Start of Frame interrupt is generated just after the PID receipt.

Reserved

The value read from this bit is always 0. Do not set this bit.

-

Frame Number

FNUM[10:8] are the upper 3 bits of the 11-bit Frame Number (see the “UFNUML Register

UFNUML (S:BAh, read-only) USB Frame Number Low Register” on page 130). It is

provided in the last received SOF packet (see SOFINT in the “USBIEN Register USBIEN

(S:BEh) USB Global Interrupt Enable Register” on page 122). FNUM is updated if a

corrupted SOF is received.

2-0

FNUM[10:8]

Reset Value = 00h

Table 21-17. UFNUML Register

UFNUML (S:BAh, read-only)

USB Frame Number Low Register

7

6

5

4

3

2

1

0

FNUM7

FNUM6

FNUM5

FNUM4

FNUM3

FNUM2

FNUM1

FNUM0

Bit

Bit Number Mnemonic Description

Frame Number

7 - 0

FNUM[7:0] FNUM[7:0] are the lower 8 bits of the 11-bit Frame Number (See “UFNUMH Register

UFNUMH (S:BBh, read-only) USB Frame Number High Register” on page 130.).

Reset Value = 00h

130

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

22. Reset

22.1 Introduction

The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset

input.

Figure 22-1. Reset schematic

Power

Monitor

Hardware

Watchdog

Internal Reset

PCA

Watchdog

RST

22.2 Reset Input

The Reset input can be used to force a reset pulse longer than the internal reset controlled by

the Power Monitor. RST input has a pull-up resistor allowing power-on reset by simply connect-

ing an external capacitor to V_SSas shown in Figure 22-2. Resistor value and input

characteristics are discussed in the Section “DC Characteristics” of the AT83C5134/35/36

datasheet.

Figure 22-2. Reset Circuitry and Power-On Reset

VCC

RST

+

RST

To internal reset

VSS

a. RST input circuitry

b. Power-on Reset

22.3 Reset Output

As detailed in Section “Hardware Watchdog Timer”, page 138, the WDT generates a 96-clock

period pulse on the RST pin. In order to properly propagate this pulse to the rest of the applica-

tion in case of external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be

added as shown Figure 22-3.

131

7683C–USB–11/07

Figure 22-3. Recommended Reset Output Schematic

VDD

RST

1K

AT89C5131A-M

VSS

+

To other

on-board

circuitry

VSS

132

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

23. Power Monitor

The POR/PFD function monitors the internal power-supply of the CPU core memories and the

peripherals, and if needed, suspends their activity when the internal power supply falls below a

safety threshold. This is achieved by applying an internal reset to them.

By generating the Reset the Power Monitor insures a correct start up when AT89C5131 is pow-

ered up.

23.1 Description

In order to startup and maintain the microcontroller in correct operating mode, V_CChas to be sta-

bilized in the V_CCoperating range and the oscillator has to be stabilized with a nominal amplitude

compatible with logic level VIH/VIL.

These parameters are controlled during the three phases: power-up, normal operation and

power going down. See Figure 23-1.

Figure 23-1. Power Monitor Block Diagram

VCC

CPU core

Regulated

Supply

Power On Reset

Power Fail Detect

Voltage Regulator

Memories

Peripherals

XTAL1

(1)

Internal Reset

RST pin

PCA

Watchdog

Hardware

Watchdog

Note:

1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock period delay

will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail

Detect threshold level, the Reset will be applied immediately.

The Voltage regulator generates a regulated internal supply for the CPU core the memories and

the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator.

The Power fail detect monitor the supply generated by the voltage regulator and generate a

reset if this supply falls below a safety threshold as illustrated in the Figure 23-2 below.

133

7683C–USB–11/07

Figure 23-2. Power Fail Detect

Vcc

t

Reset

Vcc

When the power is applied, the Power Monitor immediately asserts a reset. Once the internal

supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL

clock input. The internal reset will remain asserted until the Xtal1 levels are above and below

VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is

de-asserted.

If the internal power supply falls below a safety level, a reset is immediately asserted.

.

134

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

24. Power Management

24.1 Idle Mode

An instruction that sets PCON.0 indicates that it is the last instruction to be executed before

going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but

not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety:

the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers

maintain their data during Idle. The port pins hold the logical states they had at the time Idle was

activated. ALE and PSEN hold at logic high level.

There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause

PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced,

and following RETI the next instruction to be executed will be the one following the instruction

that put the device into idle.

The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during nor-

mal operation or during an Idle. For example, an instruction that activates Idle can also set one

or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can exam-

ine the flag bits.

The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is

still running, the hardware reset needs to be held active for only two machine cycles (24 oscilla-

tor periods) to complete the reset.

24.2 Power-down Mode

To save maximum power, a power-down mode can be invoked by software (refer to Table 13,

PCON register).

In power-down mode, the oscillator is stopped and the instruction that invoked power-down

mode is the last instruction executed. The internal RAM and SFRs retain their value until the

power-down mode is terminated. V_CCcan be lowered to save further power. Either a hardware

reset or an external interrupt can cause an exit from power-down. To properly terminate power-

down, the reset or external interrupt should not be executed before V_CCis restored to its normal

operating level and must be held active long enough for the oscillator to restart and stabilize.

Only:

• external interrupt INT0,

• external interrupt INT1,

• Keyboard interrupt and

• USB Interrupt

are useful to exit from power-down. For that, interrupt must be enabled and configured as level

or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power down mode,

1024 clocks are necessary to exit to power-down mode and enter in operating mode.

Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed

in Figure 24-1. When both interrupts are enabled, the oscillator restarts as soon as one of the

two inputs is held low and power-down exit will be completed when the first input is released. In

this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced,

the next instruction to be executed after RETI will be the one following the instruction that put

AT83C5134/35/36 into power-down mode.

135

7683C–USB–11/07

Figure 24-1. Power-down Exit Waveform

INT0

INT1

XTAL

Active Phase

Power-down Phase Oscillator restart Phase

Active Phase

Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter-

rupt does no affect the SFRs.

Exit from power-down by either reset or external interrupt does not affect the internal RAM

content.

Note:

If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is

unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is

not entered.

This table shows the state of ports during idle and power-down modes.

Table 24-1. State of Ports

Program

Mode

Idle

Memory

Internal

External

Internal

External

ALE

PSEN

PORT0

PORT1

Port Data

PORT2

Port Data

Address

Port Data

PORT3

Port Data

PORTI2

Port Data

Port

Data⁽¹⁾

1

0

1

0

Idle

Floating

Port

Data⁽¹⁾

Power-down

Floating

Note:

1. Port 0 can force a 0 level. A “one” will leave port floating.

136

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

24.3 Registers

Table 24-2. PCON Register

PCON (S:87h)

Power Control Register

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Bit Number Mnemonic Description

Serial Port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

6

5

SMOD1

SMOD0

-

Serial Port Mode bit 0

Set to select FE bit in SCON register.

Clear to select SM0 bit in SCON register

Reserved

The value read from this bit is always 0. Do not set this bit.

Power-Off Flag

Set by hardware when V_CCrises from 0 to its nominal voltage. Can also be set by

software.

Clear to recognize next reset type.

4

POF

General-purpose Flag 1

3

2

1

0

GF1

GF0

PD

Set by software for general-purpose usage.

Cleared by software for general-purpose usage.

General-purpose Flag 0

Set by software for general-purpose usage.

Cleared by software for general-purpose usage.

Power-down mode bit

Set this bit to enter in power-down mode.

Cleared by hardware when reset occurs.

Idle mode bit

IDL

Set this bit to enter in Idle mode.

Cleared by hardware when interrupt or reset occurs.

Reset Value = 10h

137

7683C–USB–11/07

25. Hardware Watchdog Timer

The WDT is intended as a recovery method in situations where the CPU may be subjected to

software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT

(WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user

must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is

enabled, it will increment every machine cycle while the oscillator is running and there is no way

to disable the WDT except through reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will drive an output RESET LOW pulse at the RST-pin.

25.1 Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca-

tion 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to

WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH)

and this will reset the device. When WDT is enabled, it will increment every machine cycle while

the oscillator is running. This means the user must reset the WDT at least every 16383 machine

cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write

only register. The WDT counter cannot be read or written. When WDT overflows, it will generate

an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T_{CLK PERIPH}, where

T_{CLK PERIPH}= 1/F_{CLK PERIPH}. To make the best use of the WDT, it should be serviced in those sec-

tions of code that will periodically be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 2⁷counter has been added to extend the Time-out capability,

ranking from 16 ms to 2s at F_OSCA= 12 MHz. To manage this feature, refer to WDTPRG register

description, Table 25-2.

Table 25-1. WDTRST Register

WDTRST - Watchdog Reset Register (0A6h)

7

6

5

4

3

2

1

0

-

Reset Value = XXXX XXXXb

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.

138

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 25-2. WDTPRG Register

WDTPRG - Watchdog Timer Out Register (0A7h)

7

6

5

4

3

2

1

0

-

S2

S1

S0

Bit

Number

Mnemonic

Description

7

6

5

4

3

2

1

0

-

Reserved

The value read from this bit is undetermined. Do not try to set this bit.

-

S2

S1

S0

WDT Time-out select bit 2

WDT Time-out select bit 1

WDT Time-out select bit 0

S2 S1 S0 Selected Time-out

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16384x2^(214 - 1) machine cycles, 16.3 ms at FOSC = 12 MHz

16384x2^(215 - 1) machine cycles, 32.7 ms at FOSC = 12 MHz

16384x2^(216 - 1) machine cycles, 65.5 ms at FOSC = 12 MHz

16384x2^(217 - 1) machine cycles, 131 ms at FOSC = 12 MHz

16384x2^(218 - 1) machine cycles, 262 ms at FOSC = 12 MHz

16384x2^(219 - 1) machine cycles, 542 ms at FOSC = 12 MHz

16384x2^(220 - 1) machine cycles, 1.05 s at FOSC = 12 MHz

16384x2^(221 - 1) machine cycles, 2.09 s at FOSC = 12 MHz

16384x2^S machine cycles

Reset value = XXXX X000

25.2 WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-

down mode the user does not need to service the WDT. There are 2 methods of exiting Power-

down mode: by a hardware reset or via a level activated external interrupt which is enabled prior

to entering Power-down mode. When Power-down is exited with hardware reset, servicing the

WDT should occur as it normally should whenever the AT83C5134/35/36 is reset. Exiting

Power-down with an interrupt is significantly different. The interrupt is held low long enough for

the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent

the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until

the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service

routine.

To ensure that the WDT does not overflow within a few states of exiting of power-down, it is bet-

ter to reset the WDT just before entering power-down.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the

AT83C5134/35/36 while in Idle mode, the user should always set up a timer that will periodically

exit Idle, service the WDT, and re-enter Idle mode.

139

7683C–USB–11/07

AT83C5134/35/36

26. Reduced EMI Mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with exter-

nal program or data memory. Nevertheless, during internal code execution, ALE signal is still

generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit.

The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer

output but remains active during MOVX and MOVC instructions and external fetches. During

ALE disabling, ALE pin is weakly pulled high.

Table 26-1. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

6

5

4

3

2

1

0

DPU

-

M0

-

XRS1

XRS0

EXTRAM

AO

Bit

Mnemonic Description

Number

Disable Weak Pull Up

7

6

DPU

-

Cleared to enabled weak pull up on standard Ports

Set to disable weak pull up on standard Ports

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Pulse length

Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods

(default).

5

M0

Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.

Reserved

4

3

-

The value read from this bit is indeterminate. Do not set this bit.

XRS1

ERAM Size

XRS1 XRS0 ERAM size

0

1

0

1

0

1

256 bytes

512 bytes

2

1

0

XRS0

EXTRAM

AO

768 bytes

1024 bytes (default)

EXTRAM bit

Cleared to access internal ERAM using MOVX at Ri at DPTR.

Set to access external memory.

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2

mode is used) (default).

Set, ALE is active only during a MOVX or MOVC instruction is used.

Reset Value = 0X0X 1100b

Not bit addressable

141

7683B–USB–03/07

27. Electrical Characteristics

27.1 Absolute Maximum Ratings

Note:

Stresses at or above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions above those indicated in the operational

sections of this specification is not implied. Exposure

to absolute maximum rating conditions may affect

device reliability.

Ambient Temperature Under Bias:

I = industrial ........................................................-40°C to 85°C

Storage Temperature.................................... -65°C to + 150°C

Voltage on V_CCfrom V_SS......................................-0.5V to + 6V

Voltage on Any Pin from V_SS.....................-0.5V to V_CC+ 0.2V

27.2 DC Parameters

TA = -40°C to +85°C; V_SS= 0V; V_CC= 2.7 - 3.6V; F = 0 to 40 MHz

Symbol

Parameter

Min

-0.5

Typ⁽⁵⁾

Max

Unit Test Conditions

V_IL

V_IH

Input Low Voltage

0.2Vcc - 0.1

V_CC+ 0.5

V

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

0.2 V_CC+ 0.9

0.7 V_CC

V_IH1

0.3

0.45

1.0

V

I_OL= 100 µ

A⁽⁴⁾

I_OL= 0.8 mA⁽⁴⁾

I_OL= 1.6mA⁽⁴⁾

V_OL

Output Low Voltage, ports 1, 2, 3 and 4⁽⁶⁾

Output Low Voltage, port 0, ALE, PSEN ⁽⁶⁾

0.3

0.45

1.0

V

I_OL= 200 µ

A⁽⁴⁾

I_OL= 1.6 mA⁽⁴⁾

I_OL= 3.5 mA⁽⁴⁾

V_OL1

I_OH= -10

I_OH= -30

I_OH= -60

µ

A

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

V_OH

Output High Voltage, ports 1, 2, 3, 4 and 5

Output High Voltage, port 0, ALE, PSEN

V_CC= 2.7 - 3.6V

I_OH= -200

µ

A

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

I_OH= -1.6 mA

I_OH= -3.5 mA

V_CC= 2.7 - 3.6V

V_OH1

R_RST

I_IL

RST Pullup Resistor

50

100

200

-50

10

kΩ

Logical 0 Input Current ports 1, 2, 3 and 4

Input Leakage Current

µ

A

Vin = 0.45V

I_LI

0.45V < Vin < V_CC

Logical 1 to 0 Transition Current, ports 1, 2, 3

and 4

I_TL

-650

µ

A

Vin = 2.0V

Fc = 1 MHz

C_IO

I_PD

Capacitance of I/O Buffer

Power-down Current

Power Supply Current

10

pF

TA

= 25

°C

100

µA

2.7V < V_CC< 3.6V⁽³⁾

I_CCOP= 0.33xF(MHz)+1.46

I_CCIDLE= 0.3xF(MHz)+1.46

I_CCwrite= 0.8xF(MHz)+15

I_CC

V_CC= 3.3V ⁽¹⁾⁽²⁾

V_PFDP

Power Fail High Level Threshold

2.7

V

142

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Symbol

Parameter

Min

2.2

Typ⁽⁵⁾

Max

Unit Test Conditions

V_PFDM

Power Fail Low Level Threshold

Power fail hysteresis V_PFDP- V_PFDM

V

0.15

Notes: 1. Operating I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 27-4.), V_IL=

V_SS+ 0.5V,

V_IH= V_CC- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V_CC. I_CCwould be slightly higher if a crystal oscillator used (see Figure

27-1.).

2. Idle I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5V, V_IH= V_CC

0.5V; XTAL2 N.C; Port 0 = V_CC; EA = RST = V_SS(see Figure 27-2).

-

3. Power-down I_CCis measured with all output pins disconnected; EA = V_CC, PORT 0 = V_CC; XTAL2 NC.; RST = V_SS(see Fig-

ure 27-3.). In addition, the WDT must be inactive and the POF flag must be set.

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLSof ALE and Ports 1

and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed

0.45V with maxi V_OLpeak 0.6V. A Schmitt Trigger use is not necessary.

5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature.

6. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8-bit port:

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I_OLfor all output pins: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

Figure 27-1. I_CCTest Condition, Active Mode

V_CC

I_CC

V_CC

P0

RST

EA

(NC)

CLOCK

SIGNAL

XTAL2

XTAL1

V_SS

All other pins are disconnected.

143

7683C–USB–11/07

Figure 27-2. I_CCTest Condition, Idle Mode

V_CC

I_CC

V_CC

P0

EA

V_CC

RST

(NC)

CLOCK

SIGNAL

XTAL2

XTAL1

V_SS

All other pins are disconnected.

Figure 27-3. I_CCTest Condition, Power-down Mode

V_CC

I_CC

V_CC

P0

V_CC

RST

EA

(NC)

XTAL2

XTAL1

V_SS

All other pins are disconnected.

Figure 27-4. Clock Signal Waveform for I_CCTests in Active and Idle Modes

V_CC-0.5V

0.7V_CC

0.2V_CC-0.1

0.45V

T_CLCH

T_CHCL

T_CLCH= T_CHCL= 5ns.

27.2.1

LED’s

Table 27-1. LED Outputs DC Parameters

Symbol

Parameter

Min

Typ

Max

Unit Test Conditions

1

2

5

2

4

8

mA

2 mA configuration

4 mA configuration

10 mA configuration

I_OL

Output Low Current, P3.6 and P3.7 LED modes

10

20

Note:

1. (TA = -20°C to +50°C, V_CC- V_OL= 2 V 20%)

144

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

27.3 USB DC Parameters

1 - V

BUS

2 - D -

3 - D +

4 - GND

R

V

REF

D +

D -

3

2

1

Rpad

USB “B”

Receptacle

4

R = 1.5 kΩ

pad = 27Ω

R

Symbol Parameter

V_REFUSB Reference Voltage

V_IHInput High Voltage for D+ and D- (Driven)

Min

Typ

Max

Unit

V

3.0

2.0

2.7

3.6

V

V_IHZ

V_IL

Input High Voltage for D+ and D- (Floating)

Input Low Voltage for D+ and D-

3.6

0.8

3.6

0.3

V

V_OH

V_OL

Output High Voltage for D+ and D-

Output Low Voltage for D+ and D-

2.8

0.0

V

27.4 AC Parameters

27.4.1

Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The

other characters, depending on their positions, stand for the name of a signal or the logical sta-

tus of that signal. The following is a list of all the characters and what they stand for.

Example:T_AVLL= Time for Address Valid to ALE Low.

T_LLPL= Time for ALE Low to PSEN Low.

T_A= -40°C to +85°C; V_SS= 0V; V_CC

=

2.7 - 3.6V; F = 0 to 40 MHz.

2.7 - 3.6V

.

(Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capacitance for all other outputs =

60 pF.)

Table 27-3, Table 27-6 and Table 27-9 give the description of each AC symbols.

Table 27-4, Table 27-8 and Table 27-10 give for each range the AC parameter.

Table 27-5, Table 27-8 and Table 27-11 give the frequency derating formula of the AC parame-

ter for each speed range description. To calculate each AC symbols. take the x value and use

this value in the formula.

145

7683C–USB–11/07

Example: T_LLIVand 20 MHz, Standard clock.

x = 30 ns

T = 50 ns

T_CCIV= 4T - x = 170 ns

27.4.2

External Program Memory Characteristics

Table 27-2. Symbol Description

Symbol

T

Parameter

Oscillator Clock Period

ALE Pulse Width

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

Address Valid to ALE

Address Hold after ALE

ALE to Valid Instruction In

ALE to PSEN

PSEN Pulse Width

PSEN to Valid Instruction In

Input Instruction Hold after PSEN

Input Instruction Float after PSEN

Address to Valid Instruction In

PSEN Low to Address Float

Table 27-3. AC Parameters for a Fix Clock (F = 40 MHz)

Symbol

T

Min

25

Max

Units

ns

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

40

ns

10

ns

10

ns

70

35

ns

15

55

ns

0

ns

18

85

10

ns

146

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 27-4. AC Parameters for a Variable Clock

Standard

Symbol

T_LHLL

T_AVLL

T_LLAX

T_LLIV

Type

Min

Clock

2 T - x

T - x

4 T - x

T - x

3 T - x

x

X2 Clock

T - x

X Parameter

Units

ns

10

15

30

10

20

40

0

Min

0.5 T - x

2 T - x

0.5 T - x

1.5 T - x

x

ns

Min

ns

Max

Min

ns

T_LLPL

T_PLPH

T_PLIV

ns

Min

ns

Max

Min

ns

T_PXIX

T_PXIZ

T_AVIV

ns

Max

T - x

5 T - x

x

0.5 T - x

2.5 T - x

x

7

ns

40

10

ns

T_PLAZ

ns

27.4.3

External Program Memory Read Cycle

12 T_CLCL

T_LHLL

T_LLIV

T_LLPL

ALE

PSEN

T_PLPH

T_PXAV

T_PXIZ

T_LLAX

T_AVLL

T_PLIV

TPLAZ

T_PXIX

INSTR IN

PORT 0

PORT 2

INSTR IN

A0-A7

INSTR IN

T_AVIV

ADDRESS A8-A15

ADDRESS

OR SFR-P2

ADDRESS A8-A15

147

7683C–USB–11/07

27.4.4

External Data Memory Characteristics

Table 27-5. Symbol Description

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Parameter

RD Pulse Width

WR Pulse Width

RD to Valid Data In

Data Hold After RD

Data Float After RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

Address to WR or RD

Data Valid to WR Transition

Data set-up to WR High

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE high

T_WHLH

Table 27-6. AC Parameters for a Variable Clock (F = 40 MHz)

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Min

130

Max

Units

ns

100

0

30

160

165

100

T_AVDV

T_LLWL

50

75

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

10

160

15

0

10

40

148

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 27-7. AC Parameters for a Variable Clock

Standard

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Type

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Clock

6 T - x

5 T - x

x

X2 Clock

3 T - x

2.5 T - x

x

X Parameter

Units

ns

20

25

0

2 T - x

8 T - x

9 T - x

3 T - x

3 T + x

4 T - x

T - x

20

40

60

25

15

25

10

0

4T -x

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

4.5 T - x

1.5 T - x

1.5 T + x

2 T - x

0.5 T - x

3.5 T - x

0.5 T - x

x

7 T - x

T - x

x

T - x

0.5 T - x

0.5 T + x

15

T + x

27.4.5

External Data Memory Write Cycle

T_WHLH

ALE

PSEN

WR

T_LLWL

T_WLWH

T_QVWX

T_WHQX

T_LLAX

A0-A7

T_QVWH

DATA OUT

PORT 0

T_AVWL

ADDRESS

OR SFR-P2

PORT 2

ADDRESS A8-A15 OR SFR P2

149

7683C–USB–11/07

27.4.6

External Data Memory Read Cycle

T_WHLH

T_LLDV

ALE

PSEN

RD

T_LLWL

T_RLRH

T_RHDZ

T_AVDV

T_LLAX

T_RHDX

DATA IN

PORT 0

PORT 2

A0-A7

T_RLAZ

T_AVWL

ADDRESS

OR SFR-P2

ADDRESS A8-A15 OR SFR P2

27.4.7

Serial Port Timing - Shift Register Mode

Table 27-8. Symbol Description (F = 40 MHz)

Symbol

T_XLXL

Parameter

Serial port clock cycle time

T_QVHX

T_XHQX

T_XHDX

T_XHDV

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

Table 27-9. AC Parameters for a Fix Clock (F = 40 MHz)

Symbol

T_XLXL

Min

300

200

30

Max

Units

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

ns

0

ns

117

ns

Table 27-10. AC Parameters for a Variable Clock

Standard

Clock

X Parameter

for -M Range

Symbol

T_XLXL

Type

Min

Max

X2 Clock

6 T

Units

12 T

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

10 T - x

2 T - x

x

5 T - x

T - x

50

20

0

x

10 T - x

5 T- x

133

150

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

27.4.8

Shift Register Timing Waveform

0

1

2

3

4

5

6

7

8

INSTRUCTION

ALE

T_XLXL

CLOCK

T_XHQX

1

T_QVXH

0

2

3

4

5

6

7

OUTPUT DATA

T_XHDX

SET TI

T_XHDV

WRITE to SBUF

INPUT DATA

VALID

SET RI

CLEAR RI

27.4.9

External Clock Drive Characteristics (XTAL1)

Table 27-11. AC Parameters

Symbol

T_CLCL

Parameter

Min

Max

Units

ns

Oscillator Period

High Time

Low Time

21

5

T_CHCX

T_CLCX

T_CLCH

T_CHCL

ns

5

ns

Rise Time

5

ns

Fall Time

ns

T_CHCX/T_CLCXCyclic ratio in X2 mode

40

60

%

27.4.10 External Clock Drive Waveforms

V_CC-0.5V

0.7V_CC

0.2V_CC-0.1

0.45V

T_CHCX

T_CLCX

T_CHCL

T_CLCH

T_CLCL

27.4.11 AC Testing Input/Output Waveforms

V_CC-0.5V

0.45V

0.2 V_CC+ 0.9

0.2 V_CC- 0.1

INPUT/OUTPUT

AC inputs during testing are driven at V_CC- 0.5 for a logic “1” and 0.45V for a logic “0”. Timing

measurement are made at V_IHmin for a logic “1” and V_ILmax for a logic “0”.

27.4.12 Float Waveforms

FLOAT

V_LOAD

V_OH- 0.1 V

V_OL+ 0.1 V

V_LOAD+ 0.1 V

V_LOAD- 0.1 V

For timing purposes as port pin is no longer floating when a 100 mV change from load voltage

occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel occurs. I_OL/I_OH

≥ 20 mA.

151

7683C–USB–11/07

27.4.13 Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.

STATE4

P1 P2

STATE5

P1 P2

STATE6

P1 P2

STATE1

STATE2

P1 P2

STATE3

P1 P2

STATE4

P1 P2

STATE5

P1 P2

INTERNAL

CLOCK

P1

P2

XTAL2

ALE

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

EXTERNAL PROGRAM MEMORY FETCH

PSEN

P0

DATA

SAMPLED

PCL OUT

DATA

SAMPLED

PCL OUT

DATA

SAMPLED

PCL OUT

FLOAT

P2 (EXT)

INDICATES ADDRESS TRANSITIONS

READ CYCLE

RD

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DPL OR Rt OUT

DATA

SAMPLED

P0

FLOAT

P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

WRITE CYCLE

WR

PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

DPL OR Rt OUT

P0

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL

DATA OUT

P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

PORT OPERATION

MOV PORT SRC

OLD DATA

NEW DATA

P0 PINS SAMPLED

MOV DEST P0

MOV DEST PORT (P1. P2. P3)

(INCLUDES INTO. INT1. TO T1)

P1, P2, P3 PINS SAMPLED

RXD SAMPLED

P1, P2, P3 PINS SAMPLED

SERIAL PORT SHIFT CLOCK

RXD SAMPLED

TXD (MODE 0)

This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,

ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propa-

gation also varies from output to output and component. Typically though (T_A= 25°C fully loaded) RD and WR propagation

delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC

specifications.

152

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

Table 27-12. Memory AC Timing

VDD = 3.3V 10%, T_A= -40 to +85°C

Symbol

T_SVRL

T_RLSX

Parameter

Min

50

Typ

Max

Unit

ns

Input PSEN Valid to RST Edge

Input PSEN Hold after RST Edge

50

ns

27.5 USB AC Parameters

Rise Time

Fall Time

V

Hmin

Lmax

90%

V

CRS

10%

Differential

Data Lines

tF

tR

Table 27-13. USB AC Parameters

Symbol Parameter

Min

Typ

Max

20

Unit

ns

Test Conditions

t_R

t_F

Rise Time

4

Fall Time

20

ns

t_FDRATE

V_CRS

Full-speed Data Rate

Crossover Voltage

11.9700

1.3

12.0300

2.0

Mb/s

V

Source Jitter Total to Next

Transaction

t_DJ1

t_DJ2

t_JR1

t_JR2

-3.5

-4

3.5

4

ns

Source Jitter Total for Paired

Transactions

Receiver Jitter to Next

Transaction

-18.5

-9

18.5

9

Receiver Jitter for Paired

Transactions

27.6 SPI Interface AC Parameters

27.6.0.1

Definition of Symbols

Table 27-14. SPI Interface Timing Symbol Definitions

Signals

Conditions

High

C

I

Clock

H

L

Data In

Data Out

Low

O

V

X

Z

Valid

No Longer Valid

Floating

153

7683C–USB–11/07

27.6.0.2

Timings

Test conditions: capacitive load on all pins= 50 pF.

Table 27-15. SPI Interface Master AC Timing

V

_DD= 2.7 to 5.5 V, T_A= -40 to +85°C

Symbol

Parameter

Slave Mode

Min

Max

Unit

T_CHCH

Clock Period

2

T_PER

ns

T_CHCX

Clock High Time

Clock Low Time

0.8

100

50

T_CLCX

T_SLCH, T_SLCL

T_IVCL, T_IVCH

T_CLIX, T_CHIX

T_CLOV,T_CHOV

T_CLOX, T_CHOX

T_CLSH, T_CHSH

T_SLOV

SS Low to Clock edge

Input Data Valid to Clock Edge

Input Data Hold after Clock Edge

Output Data Valid after Clock Edge

Output Data Hold Time after Clock Edge

SS High after Clock Edge

SS Low to Output Data Valid

Output Data Hold after SS High

SS High to SS Low

ns

50

ns

50

ns

0

ns

4T_PER+20

ns

T_SHOX

2T_PER+100

ns

T_SHSL

2T_PER+120

T_ILIH

Input Rise Time

2

µ

s

T_IHIL

Input Fall Time

2

T_OLOH

Output Rise time

100

ns

T_OHOL

Output Fall Time

Master Mode

T_CHCH

Clock Period

4

2T_PER-20

50

T_PER

ns

T_CHCX

Clock High Time

T_CLCX

Clock Low Time

ns

T_IVCL, T_IVCH

T_CLIX, T_CHIX

T_CLOV,T_CHOV

T_CLOX, T_CHOX

Input Data Valid to Clock Edge

Input Data Hold after Clock Edge

Output Data Valid after Clock Edge

Output Data Hold Time after Clock Edge

ns

50

ns

20

ns

0

ns

Note:

T_PERis XTAL period when SPI interface operates in X2 mode or twice XTAL period when SPI

interface operates in X1 mode.

154

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

27.6.0.3

Waveforms

Figure 27-5. SPI Slave Waveforms (CPHA= 0)

SS

(input)

T_SLCH

T_CLSH

T_CHCH

T_SHSL

T_SLCL

T_CHSH

T_CLCH

SCK

(CPOL= 0)

(input)

T_CHCX

T_CLCX

T_CHCL

SCK

(CPOL= 1)

(input)

T_CLOX

T_CHOX

T_CLOV

T_CHOV

T_SLOV

SLAVE MSB OUT

T_SHOX

MISO

(output)

(1)

BIT 6

SLAVE LSB OUT

T_CHIX

T_CLIX

T_IVCH

T_IVCL

MOSI

(input)

MSB IN

BIT 6

LSB IN

Note:

1. Not Defined but generally the MSB of the character which has just been received.

Figure 27-6. SPI Slave Waveforms (CPHA= 1)

SS

(input)

T_SLCH

T_CLSH

T_CHSH

T_SLCL

T_CHCH

T_SHSL

T_CLCH

SCK

(CPOL= 0)

(input)

T_CHCX

T_CLCX

T_CHCL

SCK

(CPOL= 1)

(input)

T_CHOV

T_CLOV

T_CHOX

T_CLOX

T_SLOV

T_SHOX

MISO

(output)

(1)

SLAVE MSB OUT

BIT 6

SLAVE LSB OUT

T_IVCH

T_IVCL

T_CHIX

T_CLIX

MOSI

(input)

MSB IN

BIT 6

LSB IN

Note:

1. Not Defined but generally the LSB of the character which has just been received.

155

7683C–USB–11/07

Figure 27-7. SPI Master Waveforms (SSCPHA= 0)

SS

(output)

T_CHCH

T_CLCH

SCK

(CPOL= 0)

(output)

T_CHCX

T_CLCX

T_CHCL

SCK

(CPOL= 1)

(output)

T_IVCH

T_CHIX

T_IVCLT_CLIX

MOSI

(input)

MSB IN

BIT 6

T_CLOV

T_CHOV

LSB IN

T_CLOX

T_CHOX

MISO

(output)

Port Data

MSB OUT

BIT 6

LSB OUT

Port Data

Note:

1. SS handled by software using general purpose port pin.

Figure 27-8. SPI Master Waveforms (SSCPHA= 1)

SS⁽¹⁾

(output)

T_CHCH

T_CLCH

SCK

(CPOL= 0)

(output)

T_CHCX

T_CLCX

T_CHCL

SCK

(CPOL= 1)

(output)

T_IVCH

T_CHIX

T_IVCLT_CLIX

MOSI

(input)

MSB IN

T_CLOV

BIT 6

LSB IN

T_CLOX

T_CHOX

T_CHOV

MISO

Port Data

MSB OUT

BIT 6

LSB OUT

Port Data

(output)

SS handled by software using general purpose port pin.

156

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

28. Ordering Information

Table Possible Order Entries

Part Number

Memory Size

Supply Voltage

Temperature Range

Package

Packing

AT83C5134xxx-PNTUL

8KB

2.7 to 3.6V

Industrial & Green

QFN32

Tray

AT83C5135xxx-PNTUL

16KB

2.7 to 3.6V

Industrial & Green

QFN32

Tray

AT83C5136xxx-PNTUL

AT83C5136xxx-PLTUL

AT83C5136xxx-TISUL

AT83C5136-RDTUL

AT83C5136xxx-DDW

32KB

32

2.7 to 3.6V

Industrial & Green

QFN32

QFN/MLF48

SO28

Tray

Stick

VQFP64

Die

Tray

32KB

Inked Wafer

32KB with 512-byte of

EEPROM

AT83EC5136xxx-PNTUL

AT83EI5136xxx-PNTUL

2.7 to 3.6V

Industrial & Green

QFN/MLF48

Tray

32KB with 32-kbyte of

EEPROM

157

7683C–USB–11/07

29. Packaging Information

29.1 64-lead VQFP

158

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

29.2 48-lead MLF

159

7683C–USB–11/07

160

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

29.3 28-lead SO

161

7683C–USB–11/07

29.4 QFN32

162

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

30. Document Revision History

30.1 Changes from Rev A. to Rev. B

1. Added QFN32 package.

30.2 Changes from Rev B. to Rev. C

1. Updated package drawings.

163

7683C–USB–11/07

1

2

3

4

Features.................................................................................................... 1

Description ............................................................................................... 1

Block Diagram.......................................................................................... 3

Pinout Description................................................................................... 4

4.1

4.2

Pinout ................................................................................................................ 4

Signals............................................................................................................... 6

5

6

Typical Application................................................................................ 11

5.1

5.2

Recommended External components ............................................................. 11

PCB Recommandations .................................................................................. 12

Clock Controller..................................................................................... 13

6.1

6.2

6.3

6.4

Introduction...................................................................................................... 13

Oscillator.......................................................................................................... 13

PLL .................................................................................................................. 14

Registers ......................................................................................................... 16

7

8

SFR Mapping.......................................................................................... 18

Program/Code Memory ......................................................................... 25

8.1

External Code Memory Access ....................................................................... 25

9

AT89C5131 ROM .................................................................................... 27

9.1

9.2

ROM Structure................................................................................................. 27

ROM Lock System........................................................................................... 27

10 Stacked EEPROM................................................................................... 29

10.1

10.2

Overview.......................................................................................................... 29

Protocol ........................................................................................................... 29

11 On-chip Expanded RAM (ERAM) .......................................................... 30

12 Timer 2 .................................................................................................... 33

12.1

12.2

Auto-reload Mode............................................................................................ 33

Programmable Clock Output ........................................................................... 34

13 Programmable Counter Array (PCA).................................................... 38

13.1

13.2

13.3

13.4

PCA Capture Mode ......................................................................................... 45

16-bit Software Timer/Compare Mode ............................................................ 45

High Speed Output Mode................................................................................ 46

Pulse Width Modulator Mode .......................................................................... 47

164

AT83C5134/35/36

7683C–USB–11/07

AT83C5134/35/36

13.5

PCA Watchdog Timer...................................................................................... 48

14 Serial I/O Port ......................................................................................... 49

14.1

14.2

14.3

14.4

Framing Error Detection .................................................................................. 49

Automatic Address Recognition ...................................................................... 50

Baud Rate Selection for UART for Mode 1 and 3............................................ 52

UART Registers............................................................................................... 55

15 Dual Data Pointer Register.................................................................... 59

16 Interrupt System .................................................................................... 61

16.1

16.2

16.3

Overview.......................................................................................................... 61

Registers ......................................................................................................... 62

Interrupt Sources and Vector Addresses......................................................... 69

17 Keyboard Interface ................................................................................ 70

17.1

17.2

17.3

Introduction...................................................................................................... 70

Description....................................................................................................... 70

Registers ......................................................................................................... 71

18 Programmable LED................................................................................ 74

19 Serial Peripheral Interface (SPI) ........................................................... 75

19.1

19.2

19.3

Features .......................................................................................................... 75

Signal Description............................................................................................ 75

Functional Description..................................................................................... 77

20 Two Wire Interface (TWI)....................................................................... 84

20.1

20.2

20.3

Description....................................................................................................... 86

Notes ............................................................................................................... 89

Registers ......................................................................................................... 99

21 USB Controller ..................................................................................... 101

21.1

21.2

21.3

21.4

21.5

21.6

21.7

21.8

Description..................................................................................................... 101

Configuration ................................................................................................. 103

Read/Write Data FIFO................................................................................... 105

Bulk/Interrupt Transactions............................................................................ 106

Control Transactions ..................................................................................... 111

Isochronous Transactions ............................................................................. 112

Miscellaneous................................................................................................ 113

Suspend/Resume Management.................................................................... 114

165

7683C–USB–11/07

21.9

Detach Simulation ......................................................................................... 117

21.10 USB Interrupt System.................................................................................... 117

21.11 USB Registers............................................................................................... 120

22 Reset ..................................................................................................... 131

22.1

22.2

22.3

Introduction.................................................................................................... 131

Reset Input .................................................................................................... 131

Reset Output ................................................................................................. 131

23 Power Monitor...................................................................................... 133

23.1

Description..................................................................................................... 133

24 Power Management ............................................................................. 135

24.1

24.2

24.3

Idle Mode....................................................................................................... 135

Power-down Mode......................................................................................... 135

Registers ....................................................................................................... 137

25 Hardware Watchdog Timer ................................................................. 138

25.1

25.2

Using the WDT .............................................................................................. 138

WDT During Power-down and Idle................................................................ 139

26 Reduced EMI Mode.............................................................................. 141

27 Electrical Characteristics.................................................................... 142

27.1

27.2

27.3

27.4

27.5

27.6

Absolute Maximum Ratings .......................................................................... 142

DC Parameters.............................................................................................. 142

USB DC Parameters ..................................................................................... 145

AC Parameters.............................................................................................. 145

USB AC Parameters...................................................................................... 153

SPI Interface AC Parameters ........................................................................ 153

28 Ordering Information ........................................................................... 157

29 Packaging Information ........................................................................ 158

29.1

29.2

29.3

29.4

64-lead VQFP................................................................................................ 158

48-lead MLF .................................................................................................. 159

28-lead SO .................................................................................................... 161

QFN32........................................................................................................... 162

30 Document Revision History................................................................ 163

30.1

30.2

Changes from Rev A. to Rev. B .................................................................... 163

Changes from Rev B. to Rev. C .................................................................... 163

166

AT83C5134/35/36

7683C–USB–11/07

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Atmel Asia

Room 1219

Atmel Europe

Le Krebs

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

8, Rue Jean-Pierre Timbaud

BP 309

Chuo-ku, Tokyo 104-0033

Japan

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

78054 Saint-Quentin-en-

Yvelines Cedex

France

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

www.atmel.com

Technical Support

Enter Product Line E-mail

Sales Contact

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT

OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

7683C–USB–11/07


型号：	AT83C5134_14
厂家：	ATMEL
描述：	Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
文件：	总166页 (文件大小：2044K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT83C5134_14 [ATMEL]

相关型号：

AT83C5135

AT83C5135XXX-PNTUL

AT83C5135_14

AT83C5136

AT83C5136-RDTUL

AT83C5136XXX-DDW

AT83C5136XXX-PLTUL

AT83C5136XXX-PNTUL

AT83C5136XXX-TISUL

AT83C5136_14

AT83C51IC2

AT83C51IC2_14