23LC1024T-I/ST [MICROCHIP]
STANDARD SRAM;
| 型号： | 23LC1024T-I/ST |
| 厂家： | 
MICROCHIP |
| 描述： | STANDARD SRAM 时钟 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总32页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
23A1024/23LC1024
1Mbit SPI Serial SRAM with SDI and SQI Interface
Device Selection Table
Part
Number
Temp.
Ranges
Dual I/O
(SDI)
Quad I/O
(SQI)
Max. Clock
Frequency
VCC Range
Packages
23A1024
23LC1024
1.7-2.2V
2.5-5.5V
I, E
I, E
Yes
Yes
Yes
Yes
20 MHz(1)
20 MHz(1)
SN, ST, P
SN, ST, P
Note 1: 16 MHz for E-temp.
Features
Description
• SPI Bus Interface:
- SPI compatible
The Microchip Technology Inc. 23A1024/23LC1024
are 1 Mbit Serial SRAM devices. The memory is
accessed via a simple Serial Peripheral Interface (SPI)
compatible serial bus. The bus signals required are a
clock input (SCK), a data in line (SI) and a data out line
(SO). Access to the device is controlled through a Chip
Select (CS) input. Additionally, SDI (Serial Dual
Interface) and SQI (Serial Quad Interface) is supported
if your application needs faster data rates.
- SDI (dual) and SQI (quad) compatible
- 20 MHz Clock rate for all modes
• Low-Power CMOS Technology:
- Read Current: 3 mA at 5.5V, 20 MHz
- Standby Current: 4 A at +85°C
• Unlimited Read and Write Cycles
• Zero Write Time
This device also supports unlimited reads and writes to
the memory array.
• 128K x 8-bit Organization:
- 32-byte page
The 23A1024/23LC1024 is available in standard
packages including 8-lead SOIC, PDIP and advanced
8-lead TSSOP.
• Byte, Page and Sequential Mode for Reads and
Writes
• High Reliability
Package Types (not to scale)
• Temperature Ranges Supported:
- Industrial (I):
- Automotive (E):
-40C to +85C
-40C to +125C
• RoHS Compliant
SOIC/TSSOP/PDIP
• 8 Lead SOIC, TSSOP and PDIP Packages
CS
1
8
VCC
SO/SIO1
SIO2
2
3
7
6
HOLD/SIO3
SCK
Pin Function Table
Name
Function
VSS
4
5
SI/SIO0
CS
Chip Select Input Pin
Serial Output/SDI/SQI Pin
SQI Pin
SO/SIO1
SIO2
VSS
Ground Pin
SI/SIO0
SCK
Serial Input/SDI/SQI Pin
Serial Clock Pin
HOLD/SIO3 Hold/SQI Pin
VCC
Power Supply Pin
2012-2015 Microchip Technology Inc.
DS20005142C-page 1
23A1024/23LC1024
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
All Inputs and Outputs w.r.t. VSS ........................................................................................................ -0.3V to VCC +0.3V
Storage Temperature...............................................................................................................................-65°C to +150°C
Ambient Temperature under Bias............................................................................................................-40°C to +125°C
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
Automotive (E): TA = -40°C to +125°C
TA = -40°C to +85°C
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Typ.(3)
Max.
Units
Test Conditions
23A1024
D001
VCC
Supply Voltage
1.7
2.5
—
2.2
5.5
V
V
V
23LC1024
D002
D003
VIH
VIL
High-level Input
Voltage
0.7VCC
—
—
VCC + 0.3
Low-level Input
Voltage
-0.3
0.2 VCC
0.1 VCC
0.2
V
V
V
23A1024
23LC1024
IOL = 1 mA
D004
D005
VOL
VOH
ILI
Low-level Output
Voltage
—
VCC - 0.5
—
—
—
—
—
High-level Output
Voltage
—
±1
±1
V
IOH = -400 A
Input Leakage
Current
A
A
D006
D007
D008
CS = VCC, VIN = VSS OR VCC
CS = VCC, VOUT = VSS OR VCC
ILO
Output Leakage
Current
—
ICC Read Operating Current
—
1
3
1
10
10
4
mA FCLK = 20 MHz; SO = O, 2.2V
mA FCLK = 20 MHz; SO = O, 5.5V
ICCS
Standby Current
—
A
A
A
A
pF
V
D009
CS = VCC = 2.2V, Inputs tied to
VCC or VSS, I-Temp
—
4
12
10
20
7
CS = VCC = 2.2V, Inputs tied to
VCC or VSS, E-Temp
CS = VCC = 5.5V, Inputs tied to
VCC or VSS, I-Temp
—
—
1.0
CS = VCC = 5.5V, Inputs tied to
VCC or VSS, E-Temp
CINT
VDR
Input Capacitance
—
—
D010
D011
VCC = 5.0V, f = 1 MHz, TA = 25°C
(Note 1)
RAM Data Retention
Voltage
—
(Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This is the limit to which VCC can be lowered without losing RAM data. This parameter is periodically
sampled and not 100% tested.
3: Typical measurements taken at room temperature.
DS20005142C-page 2
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
Automotive (E): TA = -40°C to +125°C
TA = -40°C to +85°C
AC CHARACTERISTICS
Param.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
No.
1
2
FCLK Clock Frequency
—
20
16
—
—
—
—
—
—
—
20
20
—
—
—
—
—
—
25
32
—
20
—
—
—
MHz I-Temp
MHz E-Temp
TCSS CS Setup Time
25
32
50
25
32
10
10
—
—
25
32
25
32
25
32
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I-Temp
E-Temp
TCSH CS Hold Time
3
4
TCSD CS Disable Time
I-Temp
E-Temp
5
6
7
8
9
TSU Data Setup Time
THD Data Hold Time
TR
TF
CLK Rise Time
CLK Fall Time
(Note 1)
(Note 1)
I-Temp
THI Clock High Time
TLO Clock Low Time
TCLD Clock Delay Time
E-Temp
I-Temp
10
11
12
E-Temp
I-Temp
E-Temp
I-Temp
TV
Output Valid from Clock Low
E-Temp
(Note 1)
13
14
15
16
THO Output Hold Time
0
TDIS Output Disable Time
THS HOLD Setup Time
THH HOLD Hold Time
—
10
10
10
THZ HOLD Low to Output High-Z
17
18
THV HOLD High to Output Valid
—
50
ns
Note 1: This parameter is periodically sampled and not 100% tested.
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform
Input Pulse Level
0.1 VCC to 0.9 VCC
Input Rise/Fall Time
CL = 30 pF
5 ns
—
Timing Measurement Reference Level
Input
Output
0.5 VCC
0.5 VCC
2012-2015 Microchip Technology Inc.
DS20005142C-page 3
23A1024/23LC1024
FIGURE 1-1: HOLD TIMING
CS
16
15
16
15
SCK
17
18
High-Impedance
Don’t Care
n
SO
n + 2
n + 2
n + 1
n
n - 1
5
n
n + 1
n
n - 1
SI
HOLD
FIGURE 1-2: SERIAL INPUT TIMING (SPI MODE)
4
CS
2
11
7
3
8
SCK
5
6
SI
MSB in
LSB in
High-Impedance
SO
FIGURE 1-3: SERIAL OUTPUT TIMING (SPI MODE)
CS
3
9
10
SCK
12
14
LSB out
13
MSB out
SO
SI
Don’t Care
DS20005142C-page 4
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
2.3
Read Sequence
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the
23A1024/23LC1024 followed by the 24-bit address,
with the first seven MSB’s of the address being “don’t
care” bits. After the correct READ instruction and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO pin.
The 23A1024/23LC1024 is an 1 Mbit Serial SRAM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
firmware to match the SPI protocol. In addition, the
23A1024/23LC1024 is capable of operation in SDI and
SQI modes. In SDI mode, the SI and SO data lines are
bidirectional, allowing the transfer of two bits per clock
pulse. In SQI mode, two additional data lines enable
the transfer of four bits per clock pulse.
If operating in Sequential mode, the data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
Address Pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached (1FFFFh),
the address counter rolls over to address 00000h,
allowing the read cycle to be continued indefinitely.
The read operation is terminated by raising the CS
pin.
The 23A1024/23LC1024 contains an 8-bit instruction
register. The device is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The
CS pin must be low for the entire operation.
2.4
Write Sequence
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Prior to any attempt to write data to the
23A1024/23LC1024, the device must be selected by
bringing CS low.
Once the device is selected, the Write command can
be started by issuing a WRITE instruction, followed by
the 24-bit address, with the first seven MSB’s of the
address being “don’t care” bits, and then the data to be
written. A write is terminated by the CS being brought
high.
2.2
Modes of Operation
The 23X1024 has three modes of operation that are
selected by setting bits 7 and 6 in the MODE register.
The modes of operation are Byte, Page and Burst.
Byte Operation – is selected when bits 7 and 6 in the
MODE register are set to 00. In this mode, the
read/write operations are limited to only one byte. The
Command followed by the 24-bit address is clocked into
the device and the data to/from the device is transferred
on the next eight clocks (Figure 2-1, Figure 2-2).
If operating in Page mode, after the initial data byte is
shifted in, additional bytes can be shifted into the
device. The Address Pointer is automatically
incremented. This operation can continue for the entire
page (32 bytes) before data will start to be overwritten.
If operating in Sequential mode, after the initial data
byte is shifted in, additional bytes can be clocked into
the device. The internal Address Pointer is
automatically incremented. When the Address Pointer
reaches the highest address (1FFFFh), the address
counter rolls over to (00000h). This allows the
operation to continue indefinitely, however, previous
data will be overwritten.
Page Operation – is selected when bits 7 and 6 in the
MODE register are set to 10. The 23X1024 has
4096 pages of 32 bytes. In this mode, the read and write
operations are limited to within the addressed page (the
address is automatically incremented internally). If the
data being read or written reaches the page boundary,
then the internal address counter will increment to the
start of the page (Figure 2-3, Figure 2-4).
Sequential Operation – is selected when bits 7 and 6
in the MODE register are set to 01. Sequential
operation allows the entire array to be written to and
read from. The internal address counter is automatically
incremented and page boundaries are ignored. When
the internal address counter reaches the end of the
array, the address counter will roll over to 0x00000
(Figure 2-5, Figure 2-6).
2012-2015 Microchip Technology Inc.
DS20005142C-page 5
23A1024/23LC1024
TABLE 2-1:
INSTRUCTION SET
Hex
Code
Instruction Name Instruction Format
Description
READ
WRITE
EDIO
EQIO
RSTIO
RDMR
WRMR
0000 0011
0000 0010
0011 1011
0011 1000
1111 1111
0000 0101
0000 0001
0x03
0x02
0x3B
0x38
0xFF
0x05
0x01
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Enter Dual I/O access (enter SDI bus mode)
Enter Quad I/O access (enter SQI bus mode)
Reset Dual and Quad I/O access (revert to SPI bus mode)
Read Mode Register
Write Mode Register
FIGURE 2-1: BYTE READ SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
SCK
SI
Instruction
24-bit Address
1 23 22 21 20
0
0
0
0
0
0
1
2
1
0
Data Out
High-Impedance
7
6
5
4
3
2
1
0
SO
FIGURE 2-2: BYTE WRITE SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
Data Byte
SCK
SI
Instruction
24-bit Address
23 22 21 20
0
0
0
0
0
0
1
0
2
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
DS20005142C-page 6
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
FIGURE 2-3: PAGE READ SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
SCK
SI
Instruction
24-bit Address
1 23 22 21 20
Page X, Word Y
0
0
0
0
0
0
1
2
1
0
Page X, Word Y
High-Impedance
SO
7
6
5
4
3
2
1
0
CS
40 41 42 43 44 45 46 47
SCK
SI
Page X, Word Y+1
Page X, Word 31
Page X, Word 0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
FIGURE 2-4:
PAGE WRITE SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
Page X, Word Y
SCK
Instruction
24-bit Address
0 23 22 21 20
Page X, Word Y
0
0
0
0
0
0
1
2
1
0
7
6
5
4
3
2
1
0
SI
High-Impedance
SO
CS
40 41 42 43 44 45 46 47
Page X, Word Y+1
SCK
Page X, Word 31
Page X, Word 0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SI
High-Impedance
SO
2012-2015 Microchip Technology Inc.
DS20005142C-page 7
23A1024/23LC1024
FIGURE 2-5:
SEQUENTIAL READ SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
SCK
Instruction
24-bit Address
23 22 21 20
0
0
0
0
0
0
1
1
2
1
0
SI
Page X, Word Y
7
6
5
4
3
2
1
0
SO
CS
SCK
SI
Page X, Word 31
Page X+1, Word 0
Page X+1, Word 1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
CS
SCK
SI
Page X+1, Word 31
Page X+n, Word 1
Page X+n, Word 31
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
DS20005142C-page 8
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
FIGURE 2-6:
SEQUENTIAL WRITE SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
Data Byte 1
SCK
Instruction
24-bit Address
0 23 22 21 20
0
0
0
0
0
0
1
2
1
0
7
6
5
4
3
2
1
0
SI
High-Impedance
SO
CS
40 41 42 43 44 45 46 47
Data Byte 2
49 50 51 52 53 54 55
Data Byte 3
48
7
SCK
Data Byte n
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SI
High-Impedance
SO
2012-2015 Microchip Technology Inc.
DS20005142C-page 9
23A1024/23LC1024
The mode bits indicate the operating mode of the
SRAM. The possible modes of operation are:
2.5
Read Mode Register Instruction
(RDMR)
0 0= Byte mode
The Read Mode Register instruction (RDMR) provides
access to the MODE register. The MODE register may
be read at any time. The MODE register is formatted as
follows:
1 0= Page mode
0 1= Sequential mode (default operation)
1 1= Reserved
Bits 0 through 5 are reserved and should always be set
to ‘0’.
TABLE 2-2:
MODE REGISTER
7
6
5
–
0
4
–
0
3
–
0
2
–
0
1
–
0
0
–
0
See Figure 2-7 for the RDMRtiming sequence.
W/R
W/R
MODE MODE
W/R = writable/readable
FIGURE 2-7: READ MODE REGISTER TIMING SEQUENCE (RDMR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
Instruction
0
0
0
0
0
1
0
1
Data from MODE Register
High-Impedance
7
6
5
4
3
2
1
0
SO
DS20005142C-page 10
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
2.6
Write Mode Register Instruction
(WRMR)
The Write Mode Register instruction (WRMR) allows the
user to write to the bits in the MODE register as shown
in Table 2-2. This allows for setting of the Device
operating mode. Several of the bits in the MODE
register must be cleared to ‘0’. See Figure 2-8 for the
WRMRtiming sequence.
FIGURE 2-8: WRITE MODE REGISTER TIMING SEQUENCE (WRMR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
15
0
SCK
SI
Instruction
Data to MODE Register
7
6
5
4
3
2
0
0
0
0
0
0
0
1
High-Impedance
SO
2.7
Power-On State
The 23A1024/23LC1024 powers on in the following
state:
• The device is in low-power Standby mode
(CS= 1)
• A high-to-low-level transition on CS is required to
enter active state
2012-2015 Microchip Technology Inc.
DS20005142C-page 11
23A1024/23LC1024
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
SOIC/PDIP/TSSOP
Symbol
Description
1
2
3
4
5
6
7
8
CS
SO/SIO1
SIO2
Chip Select Input
Serial Output (SPI)/Serial I/O 1 (SDI)/Serial I/O 1 (SQI)
Serial I/O 2 (SQI)
VSS
Ground
SI/SIO0
SCK
Serial Input (SPI)/Serial I/O 0 (SDI)/Serial I/O 0 (SQI)
Serial Clock Input
HOLD/SIO3
VCC
Hold/Serial I/O 3
Power Supply
FIGURE 3-1:
SPI, SDI and SQI Pin Configurations
SPI Mode:
SDI Mode:
SQI Mode:
CS
1
8
VCC
CS
1
8
VCC
CS
1
8
VCC
SIO1
NU
2
3
4
7
6
5
HOLD
SCK
SO
NU
2
3
7
6
HOLD
SCK
SIO1
SIO2
2
3
7
6
SIO3
SCK
Vss
4
5
SI
Vss
SIO0
Vss
4
5
SIO0
Note:
Pin 3 is not used in SPI and SDI modes, and should not be left floating (see Section 3.3 “Serial I/O
(SIO2)”).
3.1
Chip Select (CS)
3.4
Serial Input, Serial I/O 0 (SI/SIO0)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
When the device is deselected, SO goes to the
high-impedance state, allowing multiple parts to share
the same SPI bus. After power-up, a low level on CS is
required, prior to any sequence being initiated.
The SI pin is used to transfer data into the device when
the SPI bus is being used. When in SDI or SQI bus
modes, the SI/SIO0 pin is a bidirectional I/O pin.
3.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between master and the 23A1024/23LC1024.
3.2
Serial Output, Serial I/O (SO/SIO1)
a
Instructions, addresses or data present on the SI pin
are latched on the rising edge of the clock input, while
data on the SO pin is updated after the falling edge of
the clock input.
The SO/SIO1 pin is used to transfer data out of the
23A1024/23LC1024 when the SPI bus is being used.
When in SDI or SQI bus modes, the SO/SIO1 pin is a
bidirectional I/O pin. Data is shifted out on this pin after
the falling edge of the serial clock, and it is latched in
on the rising edge of the serial clock.
3.6
Hold, Serial I/O 3 (HOLD/SIO3)
When the device is in SQI bus mode, pin HOLD/SIO3
is a bidirectional I/O pin. When in SPI or SDI bus
modes, the pin has the HOLD function.
3.3
Serial I/O 2 (SIO2)
The SIO2 pin is a bidirectional I/O pin used only in SQI
mode. If not using SQI bus mode, this pin should not be
left floating. Deciding to pull the SIO2 pin high would
allow successful recovery of the bus from SQI bus
mode in case an accidental EQIO command has been
registered.
The HOLD pin is used to suspend transmission to the
23A1024/23LC1024 while in the middle of a serial
sequence without having to avoid retransmitting the
entire sequence over again. It must be held high any
time this function is not being used. Once the device is
DS20005142C-page 12
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
selected and a serial sequence is underway, the HOLD
pin may be pulled low to pause further serial
communication without resetting the serial sequence.
The HOLD pin should be brought low while SCK is low,
otherwise the HOLD function will not be invoked until
the
next
SCK
high-to-low
transition.
The
23A1024/23LC1024 must remain selected during this
sequence. The SI and SCK levels are “don’t cares”
during the time the device is paused and any
transitions on these pins will be ignored. To resume
serial communication, HOLD should be brought high
while the SCK pin is low, otherwise serial
communication will not be resumed until the next SCK
high-to-low transition.
The SO line will tri-state immediately upon a high-to low
transition of the HOLD pin, and will begin outputting
again immediately upon a subsequent low-to-high
transition of the HOLD pin, independent of the state of
SCK.
Hold functionality is not available when operating in
SQI bus mode.
2012-2015 Microchip Technology Inc.
DS20005142C-page 13
23A1024/23LC1024
4.0
DUAL AND QUAD SERIAL
MODE
The 23A1024/23LC1024 also supports SDI (Serial
Dual) and SQI (Serial Quad) mode of operation when
used with compatible master devices. As a convention
for SDI mode of operation, two bits are entered per
clock using the SIO0 and SIO1 pins. Bits are clocked
MSB first.
For SQI mode of operation, four bits of data are entered
per clock, or one nibble per clock. The nibbles are
clocked MSB first.
4.1
Dual Interface Mode
The 23A1024/23LC1024 supports Serial Dual Input
(SDI) mode of operation. To enter SDI mode the EDIO
command must be clocked in (Figure 4-1). It should be
noted that if the MCU resets before the SRAM, the user
will need to determine the serial mode of operation of
the SRAM and reset it accordingly. Byte read and write
sequence in SDI mode is shown in Figure 4-2 and
Figure 4-3.
FIGURE 4-1: ENTER SDI MODE (EDIO) FROM SPI MODE
CS
0
1
2
3
4
5
6
7
SCK
0
0
1
1
1
0
1
1
SI
High-Impedance
SO
DS20005142C-page 14
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
FIGURE 4-2:
BYTE READ MODE SDI
CS
21 22 23
9 10 11 12 13 14 15 16 17 18 19 20
0
1
2
3
4
5
6
7
8
SCK
0
0
1
0
0
0
14 12 10
8
6
7
4
5
2
3
6
7
4
2
22 20 18 16
1
1
SIO0
24-Bit Address
Instruction
Dummy Byte
Data Out
1
0
0
15 13 11
23 21 19 17
9
5
3
0
SIO1
Note 1: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is
brought high.
2: The first byte read after the address will be a dummy byte.
FIGURE 4-3:
BYTE WRITE MODE SDI
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
SCK
SIO0
SIO1
8
6
7
4
5
2
3
0
1
6
7
0
1
2
0
0
18 16
14 12
10
4
0
22 20
23 21
0
0
24-Bit Address
Instruction
Data In
0
0
9
3
19 17 15 13 11
5
1
Note:
Page and Sequential mode are similar in that additional bytes can be clocked in before CS is brought high.
2012-2015 Microchip Technology Inc.
DS20005142C-page 15
23A1024/23LC1024
4.2
Quad Interface Mode
In addition to the Serial Dual interface (SDI) mode of
operation Serial Quad Interface (SQI) is also
supported. In this mode the HOLD functionality is not
available. To enter SQI mode the EQIO command must
be clocked in (Figure 4-4).
FIGURE 4-4:
ENTER SQI MODE (EQIO) FROM SPI MODE
CS
0
1
2
3
4
5
6
7
SCK
0
0
1
1
1
0
0
0
SI
High-Impedance
SO
FIGURE 4-5:
BYTE READ MODE SQI
CS
0
1
2
3
4
5
6
7
8
9
10
4
11
0
SCK
SIO0
0
1
4
0
20 16 12
8
SIO1
0
5
6
7
1
2
3
1
5
6
1
2
21 17
22 18
13
14
15
9
SIO2
SIO3
0
0
10
0
0
7
3
23
19
11
Data Out
24-Bit Address
Dummy Byte
Instruction
Note 1: Page and Sequential mode is similar in that additional bytes can be clocked out before CS is
brought high.
2: The first byte read after the address will be a dummy byte.
DS20005142C-page 16
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
FIGURE 4-6:
BYTE WRITE MODE SQI
CS
0
1
2
3
4
5
6
7
8
9
SCK
0
0
4
5
0
1
4
5
0
1
20 16 12
8
SIO0
0
0
1
0
21 17 13
9
SIO1
6
7
2
3
6
2
22 18 14 10
SIO2
SIO3
0
0
7
3
23 19 15 11
24-Bit Address
Instruction
Data In
Note:
Page and Sequential mode are similar in that additional bytes can be clocked out before CS is
brought high.
4.3
Exit SDI or SQI Mode
To exit from SDI mode, the RSTIO command must be
issued. The command must be entered in the current
device configuration, either SDI or SQI, see Figure 4-7
and Figure 4-8.
FIGURE 4-7:
RESET SDI MODE (RSTIO) – FROM SDI MODE
CS
0
1
2
3
SCK
1
1
1
1
SIO0
SIO1
1
1
1
1
2012-2015 Microchip Technology Inc.
DS20005142C-page 17
23A1024/23LC1024
FIGURE 4-8:
RESET SDI/SQI MODE (RSTIO) – FROM SQI MODE
CS
0
1
SCK
1
1
1
SIO0
SIO1
1
1
1
1
SIO2
SIO3
1
DS20005142C-page 18
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
Example:
23A1024
8-Lead PDIP
XXXXXXXX
T/XXXNNN
I/P
e
3
1L7
1343
YYWW
8-Lead SOIC (3.90 mm)
Example:
23A1024I
XXXXXXXT
XXXXYYWW
SN
1328
e
3
NNN
1L7
Example:
3ABI
8-Lead TSSOP
XXXT
YYWW
1328
1L7
NNN
1st Line Marking Codes
Part Number
PDIP
SOIC
TSSOP
23A1024
23LC1024
Note:
23A1024
23LC1024
23A1024T
23LCBT
3ABT
3LBT
T = Temperature grade (I, E)
Legend: XX...X Part number or part number code
T
Temperature (I, E)
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
YY
WW
NNN
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
Note: For very small packages with no room for the Pb-free JEDEC® designator
, the marking will only appear on the outer carton or reel label.
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2012-2015 Microchip Technology Inc.
DS20005142C-page 19
23A1024/23LC1024
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢐꢁꢂꢋꢐꢃꢆꢑꢇꢒꢆꢓꢆꢔꢕꢕꢆꢖꢋꢈꢆꢗꢘꢅꢙꢆꢚꢇꢍꢏꢇꢛ
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
A1
c
e
eB
b1
b
ꢯꢄꢃꢏꢇ
ꢰꢱꢝꢲꢠꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ
ꢢꢰꢱ
ꢱꢴꢢ
ꢶ
ꢁꢀꢣꢣꢅꢩꢛꢝ
ꢷ
ꢁꢀꢞꢣ
ꢷ
ꢁꢞꢀꢣ
ꢁꢙꢨꢣ
ꢁꢞꢺꢨ
ꢁꢀꢞꢣ
ꢁꢣꢀꢣ
ꢁꢣꢺꢣ
ꢁꢣꢀꢶ
ꢷ
ꢢꢦꢵ
ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ
ꢂꢃꢏꢖꢘ
ꢫꢕꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢩꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢹꢃꢋꢏꢘ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢹꢃꢋꢏꢘ
ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ
ꢱ
ꢌ
ꢦ
ꢦꢙ
ꢦꢀ
ꢠ
ꢠꢀ
ꢟ
ꢳ
ꢖ
ꢔꢀ
ꢔ
ꢌꢩ
ꢷ
ꢁꢙꢀꢣ
ꢁꢀꢸꢨ
ꢷ
ꢁꢀꢀꢨ
ꢁꢣꢀꢨ
ꢁꢙꢸꢣ
ꢁꢙꢥꢣ
ꢁꢞꢥꢶ
ꢁꢀꢀꢨ
ꢁꢣꢣꢶ
ꢁꢣꢥꢣ
ꢁꢣꢀꢥ
ꢷ
ꢁꢞꢙꢨ
ꢁꢙꢶꢣ
ꢁꢥꢣꢣ
ꢁꢀꢨꢣ
ꢁꢣꢀꢨ
ꢁꢣꢻꢣ
ꢁꢣꢙꢙ
ꢁꢥꢞꢣ
ꢫꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢯꢡꢡꢌꢐꢅꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ
ꢳꢕꢗꢌꢐꢅꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ
ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꢤꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ
ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ
ꢩꢛꢝꢪꢅꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢀꢶꢩ
DS20005142C-page 20
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2015 Microchip Technology Inc.
DS20005142C-page 21
23A1024/23LC1024
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005142C-page 22
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢜꢒꢆꢓꢆꢜꢄꢠꢠꢘꢡꢢꢆꢔꢣꢤꢕꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢞꢟꢏꢥꢛ
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
2012-2015 Microchip Technology Inc.
DS20005142C-page 23
23A1024/23LC1024
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢦꢧꢋꢐꢆꢞꢧꢠꢋꢐꢨꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢦꢒꢆꢓꢆꢩꢣꢩꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢦꢞꢞꢟꢇꢛ
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
D
N
E
E1
NOTE 1
1
2
b
e
c
φ
A
A2
A1
L
L1
ꢯꢄꢃꢏꢇ
ꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ
ꢢꢰꢱ
ꢱꢴꢢ
ꢢꢦꢵ
ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ
ꢂꢃꢏꢖꢘ
ꢱ
ꢌ
ꢶ
ꢣꢁꢺꢨꢅꢩꢛꢝ
ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢛꢏꢉꢄꢋꢕꢎꢎꢅ
ꢦ
ꢷ
ꢣꢁꢶꢣ
ꢣꢁꢣꢨ
ꢷ
ꢀꢁꢣꢣ
ꢷ
ꢀꢁꢙꢣ
ꢀꢁꢣꢨ
ꢣꢁꢀꢨ
ꢦꢙ
ꢦꢀ
ꢠ
ꢴꢆꢌꢐꢉꢊꢊꢅꢹꢃꢋꢏꢘ
ꢺꢁꢥꢣꢅꢩꢛꢝ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢹꢃꢋꢏꢘ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢳꢌꢄꢜꢏꢘ
ꢬꢕꢕꢏꢅꢳꢌꢄꢜꢏꢘ
ꢠꢀ
ꢟ
ꢳ
ꢥꢁꢞꢣ
ꢙꢁꢸꢣ
ꢣꢁꢥꢨ
ꢥꢁꢥꢣ
ꢞꢁꢣꢣ
ꢣꢁꢺꢣ
ꢥꢁꢨꢣ
ꢞꢁꢀꢣ
ꢣꢁꢻꢨ
ꢬꢕꢕꢏꢡꢐꢃꢄꢏ
ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ
ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ
ꢳꢀ
ꢀ
ꢀꢁꢣꢣꢅꢼꢠꢬ
ꢣꢾ
ꢣꢁꢣꢸ
ꢣꢁꢀꢸ
ꢷ
ꢷ
ꢷ
ꢶꢾ
ꢖ
ꢔ
ꢣꢁꢙꢣ
ꢣꢁꢞꢣ
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ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢶꢺꢩ
DS20005142C-page 24
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2015 Microchip Technology Inc.
DS20005142C-page 25
23A1024/23LC1024
APPENDIX A: REVISION HISTORY
Revision A (July 2012)
Initial release.
Revision B (November 2013)
Added E-temp specs.
Revision C (January 2015)
• Updated Features section.
• Updated Description section.
• Updated Section 2.0, Functional Description.
• Updated Table 2-1.
• Updated Section 3.0, Pin Descriptions.
• Updated Table 3-1.
• Updated Section 4.0, Dual and Quad Serial
Mode.
• Minor typographical corrections.
DS20005142C-page 26
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2012-2015 Microchip Technology Inc.
DS20005142C-page 27
23A1024/23LC1024
NOTES:
DS20005142C-page 28
2012-2015 Microchip Technology Inc.
23A1024/23LC1024
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not all possible ordering options
are shown below..
PART NO.
Device
X
/XX
X
–
Examples:
Tape & Reel
Package
Temp Range
a)
23A1024-I/ST = 1 Mbit, 1.7-2.2V Serial SRAM,
Industrial temp., TSSOP package
b)
23LC1024T-I/SN = 1 Mbit, 2.5-5.5V Serial
SRAM, Industrial temp., Tape & Reel, SOIC
package
Device:
23A1024 =
23LC1024 =
1 Mbit, 1.7 - 2.2V, SPI Serial SRAM
1 Mbit, 2.5 - 5.5V, SPI Serial SRAM
c)
d)
e)
23LC1024-I/P = 1 Mbit, 2.5-5.5V Serial SRAM,
Industrial temp., PDIP package
23A1024-E/ST
= 1 Mbit, 1.7-2.2V Serial
SRAM, Extended temp., TSSOP package
23LC1024T-E/SN = 1 Mbit, 2.5-5.5V Serial
SRAM, Extended temp., Tape & Reel, SOIC
package
Tape & Reel: Blank
=
=
Standard packaging (tube)
Tape & Reel
T
Temperature
Range:
I
E
=
=
-40C to +85C
-40C to +125C
f)
23LC1024-E/P
= 1 Mbit, 2.5-5.5V Serial
SRAM, Extended temp., PDIP package
Package:
SN
ST
P
=
=
=
Plastic SOIC (3.90 mm body), 8-lead
Plastic TSSOP (4.4 mm body), 8-lead
Plastic PDIP (300 mil body), 8-lead
2012-2015 Microchip Technology Inc.
DS20005142C-page 29
23A1024/23LC1024
NOTES:
DS20005142C-page 30
2012-2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-967-1
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2012-2015 Microchip Technology Inc.
DS20005142C-page 31
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-3019-1500
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Austin, TX
Tel: 512-257-3370
Germany - Pforzheim
Tel: 49-7231-424750
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Italy - Venice
Tel: 39-049-7625286
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Poland - Warsaw
Tel: 48-22-3325737
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Sweden - Stockholm
Tel: 46-8-5090-4654
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Novi, MI
Tel: 248-848-4000
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Houston, TX
Tel: 281-894-5983
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Taiwan - Kaohsiung
Tel: 886-7-213-7830
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Los Angeles
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
DS20005142C-page 32
2012-2015 Microchip Technology Inc.
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