23LC512-E/SN [MICROCHIP]
512Kbit SPI Serial SRAM with SDI and SQI Interface;
| 型号： | 23LC512-E/SN |
| 厂家： | 
MICROCHIP |
| 描述： | 512Kbit SPI Serial SRAM with SDI and SQI Interface 静态存储器 |
| 文件： | 总32页 (文件大小：643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
23A512/23LC512
512Kbit SPI Serial SRAM with SDI and SQI Interface
Device Selection Table
Part
Number
Temp.
Ranges
Dual I/O
(SDI)
Quad I/O
(SQI)
Max. Clock
Frequency
VCC Range
Packages
23A512
23LC512
1.7-2.2V
2.5-5.5V
I, E
I, E
Yes
Yes
Yes
Yes
20 MHz(1)
20 MHz(1)
SN, ST, P
SN, ST, P
Note 1: 16 MHz for E-temp.
Features:
Description:
• SPI-Compatible Bus Interface:
- 20 MHz Clock rate
The Microchip Technology Inc. 23A512/23LC512 are
512Kbit Serial SRAM devices. The memory is
accessed via a simple Serial Peripheral Interface (SPI)
compatible serial bus. The bus signals required are a
clock input (SCK) plus separate data in (SI) and data
out (SO) lines. Access to the device is controlled
through a Chip Select (CS) input. Additionally, SDI
(Serial Dual Interface) and SQI (Serial Quad Interface)
is supported if your application needs faster data rates.
- SPI/SDI/SQI mode
• Low-Power CMOS Technology:
- Read Current: 3 mA at 5.5V, 20 MHz
- Standby Current: 4 A at +85°C
• Unlimited Read and Write Cycles
• Zero Write Time
This device also supports unlimited reads and writes to
the memory array.
• 64K x 8-bit Organization:
- 32-byte page
The 23A512/23LC512 is available in standard
packages including 8-lead SOIC, PDIP and advanced
8-lead TSSOP.
• Byte, Page and Sequential mode for Reads and
Writes
• High Reliability
• Temperature Ranges Supported:
Package Types (not to scale)
- Industrial (I):
-40C to +85C
-40C to +125C
- Automotive (E):
• RoHS Compliant
• 8-Lead SOIC, TSSOP and PDIP Packages
SOIC/TSSOP/PDIP
CS
1
8
VCC
Pin Function Table
SO/SIO1
SIO2
2
3
4
7
6
5
HOLD/SIO3
SCK
Name
Function
CS
Chip Select Input
VSS
SI/SIO0
SO/SIO1
SIO2
Serial Output/SDI/SQI Pin
SQI Pin
VSS
Ground
SI/SIO0
SCK
Serial Input/SDI/SQI Pin
Serial Clock
HOLD/SIO3 Hold/SQI Pin
Power Supply
VCC
2012-2013 Microchip Technology Inc.
DS20005155B-page 1
23A512/23LC512
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +0.3V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias.............................................................................................................-40°C to +125°C
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
Automotive (E): TA = -40°C to +125°C
TA = -40°C to +85°C
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Typ.
Max.
Units
Test Conditions
D001
VCC
Supply voltage
1.7
2.5
—
2.2
5.5
V
23A512
23LC512
D002
D003
D004
D005
D006
D007
D008
D009
VIH
VIL
VOL
VOH
ILI
High-level input
voltage
0.7 VCC
—
—
—
—
—
—
VCC + 0.3
V
V
—
Low-level input
voltage
-0.3
0.2 VCC
0.1 VCC
23A512
23LC512
Low-level output
voltage
—
0.2
V
IOL = 1 mA
High-level output
voltage
VCC - 0.5
—
—
V
IOH = -400 A
Input leakage
current
±1
±1
A
A
CS = VCC, VIN = VSS OR VCC
CS = VCC, VOUT = VSS OR VCC
ILO
Output leakage
current
—
ICC Read Operating current
—
—
1
3
10
10
mA FCLK = 20 MHz; SO = O, 2.2V
mA FCLK = 20 MHz; SO = O, 5.5V
ICCS
Standby current
—
—
—
—
1
—
4
4
A CS = VCC = 2.2V, Inputs tied to
VCC or VSS, I-Temp
A CS = VCC = 2.2V, Inputs tied to
VCC or VSS, E-Temp
A CS = VCC = 5.5V, Inputs tied to
VCC or VSS, I-Temp
A CS = VCC = 5.5V, Inputs tied to
VCC or VSS, E-Temp
12
10
20
—
D010
D011
CINT
VDR
Input capacitance
—
—
—
7
pF VCC = 5.0V, f = 1 MHz, TA = 25°C
(Note 1)
RAM data retention
voltage
1.0
—
V
(Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This is the limit to which VCC can be lowered without losing RAM data. This parameter is periodically
sampled and not 100% tested.
3: Typical measurements taken at room temperature.
DS20005155B-page 2
2012-2013 Microchip Technology Inc.
23A512/23LC512
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
Automotive (E): TA = -40°C to +125°C
TA = -40°C to +85°C
AC CHARACTERISTICS
Param.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
No.
1
2
FCLK Clock frequency
—
20
16
MHz I-Temp
E-Temp
I-Temp
TCSS CS setup time
25
32
—
ns
E-Temp
—
3
4
TCSH CS hold time
50
—
—
ns
ns
I-Temp
E-Temp
TCSD CS disable time
25
32
5
6
7
8
9
Tsu
THD
TR
Data setup time
Data hold time
CLK rise time
CLK fall time
10
10
—
—
—
—
20
20
—
ns
ns
ns
ns
ns
—
—
(Note 1)
(Note 1)
TF
THI
Clock high time
I-Temp
E-Temp
25
32
10
11
12
TLO
Clock low time
I-Temp
E-Temp
25
32
—
—
ns
ns
ns
TCLD Clock delay time
I-Temp
E-Temp
25
32
TV
Output valid from clock low
I-Temp
E-Temp
—
25
32
13
14
THO
TDIS
Output hold time
0
—
20
—
—
—
50
ns
ns
ns
ns
ns
ns
(Note 1)
Output disable time
—
—
10
10
10
—
15
16
17
18
THS
THH
THZ
THV
HOLD setup time
—
—
—
—
HOLD hold time
HOLD low to output High-Z
HOLD high to output valid
Note 1: This parameter is periodically sampled and not 100% tested.
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform:
Input pulse level
Input rise/fall time
CL = 30 pF
0.1 VCC to 0.9 VCC
5 ns
—
Timing Measurement Reference Level:
Input
0.5 VCC
0.5 VCC
Output
2012-2013 Microchip Technology Inc.
DS20005155B-page 3
23A512/23LC512
FIGURE 1-1: HOLD TIMING
CS
16
16
15
15
SCK
17
18
High-Impedance
Don’t Care
n
SO
n + 2
n + 2
n + 1
n
n - 1
5
n
n + 1
n
n - 1
SI
HOLD
FIGURE 1-2: SERIAL INPUT TIMING (SPI MODE)
4
CS
2
11
7
3
8
SCK
5
6
SI
MSB in
LSB in
High-Impedance
SO
FIGURE 1-3: SERIAL OUTPUT TIMING (SPI MODE)
CS
3
9
10
SCK
12
14
LSB out
13
MSB out
SO
SI
Don’t Care
DS20005155B-page 4
2012-2013 Microchip Technology Inc.
23A512/23LC512
If operating in Sequential mode, the data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
Address Pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached (FFFFh),
the address counter rolls over to address 0000h,
allowing the read cycle to be continued indefinitely.
The read operation is terminated by raising the CS
pin.
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
The 23A512/23LC512 is an 512Kbit Serial SRAM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol. In addition, the 23A512/
23LC512 is also capable of operating in SDI/SQI high
speed SPI mode.
2.4
Write Sequence
Prior to any attempt to write data to the 23A512/
23LC512, the device must be selected by bringing CS
low.
The 23A512/23LC512 contains an 8-bit instruction reg-
ister. The device is accessed via the SI pin, with data
being clocked in on the rising edge of SCK. The CS pin
must be low for the entire operation.
Once the device is selected, the Write command can
be started by issuing a WRITE instruction, followed by
the 16-bit address, and then the data to be written. A
write is terminated by the CS being brought high.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
If operating in Page mode, after the initial data byte is
shifted in, additional bytes can be shifted into the
device. The Address Pointer is automatically
incremented. This operation can continue for the entire
page (32 bytes) before data will start to be overwritten.
2.2
Modes of Operation
The 23x512 has three modes of operation that are
selected by setting bits 7 and 6 in the MODE register.
The modes of operation are Byte, Page and Burst.
If operating in Sequential mode, after the initial data
byte is shifted in, additional bytes can be clocked into
the device. The internal Address Pointer is automati-
cally incremented. When the Address Pointer reaches
the highest address (FFFFh), the address counter rolls
over to (0000h). This allows the operation to continue
indefinitely, however, previous data will be overwritten.
Byte Operation – is selected when bits 7 and 6 in the
MODE register are set to 00. In this mode, the read/
write operations are limited to only one byte. The
Command followed by the 16-bit address is clocked into
the device and the data to/from the device is transferred
on the next eight clocks (Figure 2-1, Figure 2-2).
Page Operation – is selected when bits 7 and 6 in the
MODE register are set to 10. The 23x512 has 2048
pages of 32 bytes. In this mode, the read and write oper-
ations are limited to within the addressed page (the
address is automatically incremented internally). If the
data being read or written reaches the page boundary,
then the internal address counter will increment to the
start of the page (Figure 2-3, Figure 2-4).
Sequential Operation – is selected when bits 7 and 6
in the MODE register are set to 01. Sequential opera-
tion allows the entire array to be written to and read
from. The internal address counter is automatically
incremented and page boundaries are ignored. When
the internal address counter reaches the end of the
array, the address counter will roll over to 0x0000
(Figure 2-5, Figure 2-6).
2.3
Read Sequence
The device is selected by pulling CS low. The 8-bit
READinstruction is transmitted to the 23A512/23LC512
followed by the 16-bit address. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin.
2012-2013 Microchip Technology Inc.
DS20005155B-page 5
23A512/23LC512
TABLE 2-1:
INSTRUCTION SET
Hex
Code
Instruction Name Instruction Format
Description
READ
WRITE
EDIO
EQIO
RSTIO
RDMR
WRMR
0000 0011
0000 0010
0011 1011
0011 1000
1111 1111
0000 0101
0000 0001
0x03
0x02
0x3B
0x38
0xFF
0x05
0x01
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Enter Dual I/O access
Enter Quad I/O access
Reset Dual and Quad I/O access
Read Mode Register
Write Mode Register
FIGURE 2-1: BYTE READ SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Instruction
16-bit Address
0 0 0 0 0 0 1 1 15 14 13 12
2
1
0
Data Out
High-Impedance
7
6
5
4
3
2
1
0
SO
FIGURE 2-2: BYTE WRITE SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Instruction
16-bit Address Data Byte
0 0 0 0 0 0 1 0 15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
DS20005155B-page 6
2012-2013 Microchip Technology Inc.
23A512/23LC512
FIGURE 2-3: PAGE READ SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Instruction
0 0 0 0 0 0 1 1 15 14 13 12
Page X, Word Y
16-bit Address
2
1
0
Page X, Word Y
High-Impedance
SO
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39
SCK
SI
Page X, Word Y+1
Page X, Word 31
Page X, Word 0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
FIGURE 2-4:
PAGE WRITE SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
Page X, Word Y
SCK
16-bit Address
Instruction
0 0 0 0 0 0 1 0
2
1
0
7
6
5
4
3
2
1
0
15 14 13 12
Page X, Word Y
SI
CS
SCK
SI
32 33 34 35 36 37 38 39
Page X, Word Y+1
Page X, Word 31
Page X, Word 0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2012-2013 Microchip Technology Inc.
DS20005155B-page 7
23A512/23LC512
FIGURE 2-5:
SEQUENTIAL READ SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16-bit Address
0 0 0 0 0 0 1 1 15 14 13 12
2
1
0
SI
Page X, Word Y
7
6
5
4
3
2
1
0
SO
CS
SCK
SI
Page X, Word 31
Page X+1, Word 0
Page X+1, Word 1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
CS
SCK
SI
Page X+1, Word 31
Page X+n, Word 1
Page X+n, Word 31
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
DS20005155B-page 8
2012-2013 Microchip Technology Inc.
23A512/23LC512
FIGURE 2-6:
SEQUENTIAL WRITE SEQUENCE (SPI MODE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
0 0 0 0 0 0 1 0 15 14 13 12
16-bit Address Data Byte 1
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39
Data Byte 2
41 42 43 44 45 46 47
Data Byte 3
40
7
SCK
SI
Data Byte n
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2012-2013 Microchip Technology Inc.
DS20005155B-page 9
23A512/23LC512
The mode bits indicate the operating mode of the
SRAM. The possible modes of operation are:
2.5
Read Mode Register Instruction
(RDMR)
0 0= Byte mode
The Read Mode Register instruction (RDMR) provides
access to the MODE register. The MODE register may
be read at any time. The MODE register is formatted as
follows:
1 0= Page mode
0 1= Sequential mode (default operation)
1 1= Reserved
Bits 0 through 5 are reserved and should always be set
to ‘0’.
TABLE 2-2:
MODE REGISTER
7
6
5
–
4
–
3
–
2
–
1
–
0
–
0
See Figure 2-7 for the RDMRtiming sequence.
W/R
W/R
MODE MODE 0 0 0 0 0
W/R = writable/readable
FIGURE 2-7: READ MODE REGISTER TIMING SEQUENCE (RDMR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
Instruction
0
0
0
0
0
1
0
1
Data from MODE Register
High-Impedance
7
6
5
4
3
2
1
0
SO
DS20005155B-page 10
2012-2013 Microchip Technology Inc.
23A512/23LC512
2.6
Write Mode Register Instruction
(WRMR)
The Write Mode Register instruction (WRMR) allows the
user to write to the bits in the MODE register as shown
in Table 2-2. This allows for setting of the Device
Operating mode. Several of the bits in the MODE
register must be cleared to ‘0’. See Figure 2-8 for the
WRMRtiming sequence.
FIGURE 2-8: WRITE MODE REGISTER TIMING SEQUENCE (WRMR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
15
0
SCK
SI
Instruction
Data to MODE Register
7
6
5
4
3
2
0
0
0
0
0
0
0
1
High-Impedance
SO
2.7
Power-On State
The 23A512/23LC512 powers on in the following state:
• The device is in low-power Standby mode
(CS= 1)
• A high-to-low-level transition on CS is required to
enter active state
2012-2013 Microchip Technology Inc.
DS20005155B-page 11
23A512/23LC512
3.6
Serial Clock (SCK)
3.0
PIN DESCRIPTIONS
The SCK is used to synchronize the communication
between a master and the 23A512/23LC512. Instruc-
tions, addresses or data present on the SI pin are
latched on the rising edge of the clock input, while data
on the SO pin is updated after the falling edge of the
clock input.
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
Name
PIN FUNCTION TABLE
SOIC/
PDIP
Function
TSSOP
3.7
Hold Function (HOLD)
CS
1
2
Chip Select Input
The HOLD pin is used to suspend transmission to the
23A512/23LC512 while in the middle of a serial
sequence without having to re-transmit the entire
sequence over again. It must be held high any time
this function is not being used. Once the device is
selected and a serial sequence is underway, the
HOLD pin may be pulled low to pause further serial
communication without resetting the serial sequence.
SO/SIO1
Serial Data Output/SDI/SQI
Pin
SIO2
3
4
5
6
7
8
SQI Pin
VSS
Ground
SI/SIO0
SCK
Serial Data Input/SDI/SQI Pin
Serial Clock Input
Hold/SQI Pin
HOLD/SIO3
VCC
Power Supply
The HOLD pin should be brought low while SCK is
low, otherwise the HOLD function will not be invoked
until the next SCK high-to-low transition. The 23A512/
23LC512 must remain selected during this sequence.
The SI and SCK levels are “don’t cares” during the
time the device is paused and any transitions on these
pins will be ignored. To resume serial communication,
HOLD should be brought high while the SCK pin is
low, otherwise serial communication will not be
3.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
When the device is deselected, SO goes to the high-
impedance state, allowing multiple parts to share the
same SPI bus. After power-up, a low level on CS is
required, prior to any sequence being initiated.
3.2
Serial Output (SO)
resumed until the next SCK high-to-low transition.
The SO pin is used to transfer data out of the 23A512/
23LC512. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
The SO line will tri-state immediately upon a high-to
low transition of the HOLD pin, and will begin
outputting again immediately upon a subsequent low-
to-high transition of the HOLD pin, independent of the
state of SCK.
3.3
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
Hold functionality is not available when operating in
SQI mode.
3.4
Serial Dual Interface Pins(SIO0,
SIO1)
The SIO0 and SIO1 pins are used for SDI mode of
operation. Functionality of these I/O pins is shared with
SO and SI.
3.5
Serial Quad Interface Pins (SIO0 –
SIO3)
The SIO0 through SIO3 pins are used for SQI mode of
operation. Because of the shared functionality of these
pins the HOLD feature is not available when using SQI
mode.
DS20005155B-page 12
2012-2013 Microchip Technology Inc.
23A512/23LC512
3.8
SPI/SDI and SQI Pin Designations
SPI Mode:
CS
1
8
Vcc
SO
NC
2
3
7
6
HOLD
SCK
Vss
4
5
SI
SDI Mode:
CS
1
8
Vcc
SIO1
NC
2
3
7
6
HOLD
SCK
Vss
4
5
SIO0
SQI Mode:
CS
1
8
Vcc
SIO1
SIO2
2
3
7
6
SIO3
SCK
Vss
4
5
SIO0
Note:
Pin 3 should not be left floating when
using SPI/SDI mode.
2012-2013 Microchip Technology Inc.
DS20005155B-page 13
23A512/23LC512
4.1
Dual Interface Mode
4.0
DUAL AND QUAD SERIAL
MODE
The 23A512/23LC512 supports Serial Dual Input (SDI)
mode of operation. To enter SDI mode the EDIO com-
mand must be clocked in (Figure 4-1). It should be
noted that if the MCU resets before the SRAM, the user
will need to determine the serial mode of operation of
the SRAM and reset it accordingly. Byte read and write
sequence in SDI mode is shown in Figure 4-2 and
Figure 4-3.
The 23A512/23LC512 also supports SDI (Serial Dual)
and SQI (Serial Quad) mode of operation when used
with compatible master devices. As a convention for
SDI mode of operation, two bits are entered per clock
using the SIO0 and SIO1 pins. Bits are clocked MSB
first.
For SQI mode of operation, four bits of data are entered
per clock, or one nibble per clock. The nibbles are
clocked MSB first.
FIGURE 4-1: ENTER SDI MODE (EDIO) FROM SPI MODE
CS
0
1
2
3
4
5
6
7
SCK
0
0
1
1
1
0
1
1
SI
High-Impedance
SO
4.2
Quad Interface Mode
In addition to the Serial Dual Interface (SDI) mode of
operation Serial Quad Interface (SQI) is also
supported. In this mode the HOLD functionality is not
available. To enter SQI mode the EQIO command must
be clocked in (Figure 4-4).
DS20005155B-page 14
2012-2013 Microchip Technology Inc.
23A512/23LC512
FIGURE 4-2:
BYTE READ MODE SDI
CS
0
1
2
3
4
5
18 19
9 10 11 12 13 14 15 16 17
6
7
8
SCK
0
1
0
0
0
0
1
6
7
4
2
14 12 10
8
6
4
2
3
0
SIO0
Dummy Byte
Data Out
Instruction
16-Bit Address
0
0
1
5
3
15 13 11 9
7
5
1
SIO1
Note:
Note:
Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high.
The first byte read after the address will be a dummy byte.
FIGURE 4-3:
BYTE WRITE MODE SDI
CS
5
0
1
2
3
4
6
7
9 10 11 12
15
13 14
8
SCK
SIO0
0
0
0
0
0
0
1
14 12 10
8
6
4
2
3
0
6
7
4
2
Data In
Instruction
16-Bit Address
0
0
1
15 13 11 9
7
5
1
5
3
SIO1
Note:
Page and Sequential mode are similar in that additional bytes can be clocked in before CS is brought high.
2012-2013 Microchip Technology Inc.
DS20005155B-page 15
23A512/23LC512
FIGURE 4-4:
ENTER SQI MODE (EQIO) FROM SPI MODE
CS
SCK
SI
0
1
2
3
4
5
6
7
0
0
1
1
1
0
0
0
High-Impedance
SO
4.3
Exit SDI or SQI Mode
To exit from SDI mode, the RSTIO command must be
issued. The command must be entered in the current
device configuration, either SDI or SQI, see Figure 4-7
and Figure 4-8.
FIGURE 4-5:
BYTE READ MODE SQI
CS
4
0
1
2
3
5
6
7
9
8
SCK
SIO0
0
1
0
1
12
8
9
4
5
6
7
0
1
2
3
4
5
6
SIO1
0
0
1
0
13
SIO2
SIO3
2
14 10
7
3
0
15 11
0
16-Bit Address
Instruction
Dummy Byte
Data Out
Note:
Note:
Page and Sequential mode is similar in that additional bytes can be clocked out before CS is brought high.
The first byte read after the address will be a dummy byte.
DS20005155B-page 16
2012-2013 Microchip Technology Inc.
23A512/23LC512
FIGURE 4-6:
CS
BYTE WRITE MODE SQI
4
0
1
2
3
5
6
7
9
8
SCK
SIO0
0
1
0
1
2
4
5
6
0
1
12
8
9
4
5
6
7
0
1
2
3
4
5
6
SIO1
0
1
13
SIO2
SIO3
0 0
2
14 10
7
3
7
3
0
15 11
0
16-Bit Address
Instruction
Data N
Data N+1
Note:
Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high.
FIGURE 4-7:
RESET SDI MODE (RSTIO) – FROM SDI MODE
CS
3
2
0
1
SCK
1 1 1 1
SIO0
SIO1
1 1 1 1
2012-2013 Microchip Technology Inc.
DS20005155B-page 17
23A512/23LC512
FIGURE 4-8:
RESET SDI/SQI MODE (RSTIO) – FROM SQI MODE
CS
0
1
SCK
SIO0
SIO1
SIO2
SIO3
1
1
1
1
1
1
1
1
DS20005155B-page 18
2012-2013 Microchip Technology Inc.
23A512/23LC512
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
Example:
23A512
8-Lead PDIP
XXXXXXXX
T/XXXNNN
I/P
e
3
1L7
1343
YYWW
8-Lead SOIC (3.90 mm)
Example:
23A512I
XXXXXXXT
XXXXYYWW
SN
1343
e
3
NNN
1L7
Example:
3LAI
8-Lead TSSOP
XXXT
YYWW
1343
1L7
NNN
1st Line Marking Codes
Part Number
PDIP
SOIC
TSSOP
23A512
23LC512
Note:
23A512
23LC512
23A512
3AAT
3LAT
23LC512T
T = Temperature grade (I, E)
Legend: XX...X Part number or part number code
T
Temperature (I, E)
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
YY
WW
NNN
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
Note: For very small packages with no room for the Pb-free JEDEC® designator
, the marking will only appear on the outer carton or reel label.
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2012-2013 Microchip Technology Inc.
DS20005155B-page 19
23A512/23LC512
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢐꢁꢂꢋꢐꢃꢆꢑꢇꢒꢆꢓꢆꢔꢕꢕꢆꢖꢋꢈꢆꢗꢘꢅꢙꢆꢚꢇꢍꢏꢇꢛ
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
A1
c
e
eB
b1
b
ꢯꢄꢃꢏꢇ
ꢰꢱꢝꢲꢠꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ
ꢢꢰꢱ
ꢱꢴꢢ
ꢶ
ꢁꢀꢣꢣꢅꢩꢛꢝ
ꢷ
ꢁꢀꢞꢣ
ꢷ
ꢁꢞꢀꢣ
ꢁꢙꢨꢣ
ꢁꢞꢺꢨ
ꢁꢀꢞꢣ
ꢁꢣꢀꢣ
ꢁꢣꢺꢣ
ꢁꢣꢀꢶ
ꢷ
ꢢꢦꢵ
ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ
ꢂꢃꢏꢖꢘ
ꢫꢕꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢩꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢹꢃꢋꢏꢘ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢹꢃꢋꢏꢘ
ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ
ꢱ
ꢌ
ꢦ
ꢦꢙ
ꢦꢀ
ꢠ
ꢠꢀ
ꢟ
ꢳ
ꢖ
ꢔꢀ
ꢔ
ꢌꢩ
ꢷ
ꢁꢙꢀꢣ
ꢁꢀꢸꢨ
ꢷ
ꢁꢀꢀꢨ
ꢁꢣꢀꢨ
ꢁꢙꢸꢣ
ꢁꢙꢥꢣ
ꢁꢞꢥꢶ
ꢁꢀꢀꢨ
ꢁꢣꢣꢶ
ꢁꢣꢥꢣ
ꢁꢣꢀꢥ
ꢷ
ꢁꢞꢙꢨ
ꢁꢙꢶꢣ
ꢁꢥꢣꢣ
ꢁꢀꢨꢣ
ꢁꢣꢀꢨ
ꢁꢣꢻꢣ
ꢁꢣꢙꢙ
ꢁꢥꢞꢣ
ꢫꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢯꢡꢡꢌꢐꢅꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ
ꢳꢕꢗꢌꢐꢅꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ
ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꢤꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ
ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ
ꢩꢛꢝꢪꢅꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢀꢶꢩ
DS20005155B-page 20
2012-2013 Microchip Technology Inc.
23A512/23LC512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2013 Microchip Technology Inc.
DS20005155B-page 21
23A512/23LC512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005155B-page 22
2012-2013 Microchip Technology Inc.
23A512/23LC512
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢜꢒꢆꢓꢆꢜꢄꢠꢠꢘꢡꢢꢆꢔꢣꢤꢕꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢞꢟꢏꢥꢛ
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
2012-2013 Microchip Technology Inc.
DS20005155B-page 23
23A512/23LC512
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢦꢧꢋꢐꢆꢞꢧꢠꢋꢐꢨꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢦꢒꢆꢓꢆꢩꢣꢩꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢦꢞꢞꢟꢇꢛ
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
D
N
E
E1
NOTE 1
1
2
b
e
c
φ
A
A2
A1
L
L1
ꢯꢄꢃꢏꢇ
ꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ
ꢢꢰꢱ
ꢱꢴꢢ
ꢢꢦꢵ
ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ
ꢂꢃꢏꢖꢘ
ꢱ
ꢌ
ꢶ
ꢣꢁꢺꢨꢅꢩꢛꢝ
ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢛꢏꢉꢄꢋꢕꢎꢎꢅ
ꢦ
ꢷ
ꢣꢁꢶꢣ
ꢣꢁꢣꢨ
ꢷ
ꢀꢁꢣꢣ
ꢷ
ꢀꢁꢙꢣ
ꢀꢁꢣꢨ
ꢣꢁꢀꢨ
ꢦꢙ
ꢦꢀ
ꢠ
ꢴꢆꢌꢐꢉꢊꢊꢅꢹꢃꢋꢏꢘ
ꢺꢁꢥꢣꢅꢩꢛꢝ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢹꢃꢋꢏꢘ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢳꢌꢄꢜꢏꢘ
ꢬꢕꢕꢏꢅꢳꢌꢄꢜꢏꢘ
ꢠꢀ
ꢟ
ꢳ
ꢥꢁꢞꢣ
ꢙꢁꢸꢣ
ꢣꢁꢥꢨ
ꢥꢁꢥꢣ
ꢞꢁꢣꢣ
ꢣꢁꢺꢣ
ꢥꢁꢨꢣ
ꢞꢁꢀꢣ
ꢣꢁꢻꢨ
ꢬꢕꢕꢏꢡꢐꢃꢄꢏ
ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ
ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ
ꢳꢀ
ꢀ
ꢀꢁꢣꢣꢅꢼꢠꢬ
ꢣꢾ
ꢣꢁꢣꢸ
ꢣꢁꢀꢸ
ꢷ
ꢷ
ꢷ
ꢶꢾ
ꢖ
ꢔ
ꢣꢁꢙꢣ
ꢣꢁꢞꢣ
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
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ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢶꢺꢩ
DS20005155B-page 24
2012-2013 Microchip Technology Inc.
23A512/23LC512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2013 Microchip Technology Inc.
DS20005155B-page 25
23A512/23LC512
APPENDIX A: REVISION HISTORY
Revision A (September 2012)
Initial release.
Revision B (November 2013)
Added E-Temp specs.
DS20005155B-page 26
2012-2013 Microchip Technology Inc.
23A512/23LC512
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2013 Microchip Technology Inc.
DS20005155B-page 27
23A512/23LC512
NOTES:
DS20005155B-page 28
2013 Microchip Technology Inc.
23A512/23LC512
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not all possible ordering options
are shown below..
PART NO.
Device
X
/XX
X
–
Examples:
Tape & Reel
Package
Temp Range
a)
23A512-I/ST = 512 Kbit, 1.7-2.2V Serial
SRAM, Industrial temp., TSSOP package
b)
23LC512T-I/SN = 512 Kbit, 2.5-5.5V Serial
SRAM, Industrial temp., Tape & Reel, SOIC
package
Device:
23A512 =
23LC512 =
512 Kbit, 1.7 - 2.2V, SPI Serial SRAM
512 Kbit, 2.5 - 5.5V, SPI Serial SRAM
c)
d)
e)
23LC512-I/P = 512 Kbit, 2.5-5.5V Serial
SRAM, Industrial temp., PDIP package
23A512-E/ST
= 512 Kbit, 1.7-2.2V Serial
Tape & Reel: Blank
=
=
Standard packaging (tube)
Tape & Reel
SRAM, Extended temp., TSSOP package
23LC512T-E/SN = 512 Kbit, 2.5-5.5V Serial
SRAM, Extended temp., Tape & Reel, SOIC
package
T
Temperature
Range:
I
E
=
=
-40C to +85C
-40C to +125C
f)
23LC512-E/P
= 512 Kbit, 2.5-5.5V Serial
SRAM, Extended temp., PDIP package
Package:
SN
ST
P
=
=
=
Plastic SOIC (3.90 mm body), 8-lead
Plastic TSSOP (4.4 mm body), 8-lead
Plastic PDIP (300 mil body), 8-lead
2012-2013 Microchip Technology Inc.
DS20005155B-page 29
23A512/23LC512
NOTES:
DS20005155B-page 30
2012-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620776179
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2012-2013 Microchip Technology Inc.
DS20005155B-page 31
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-3019-1500
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Austin, TX
Tel: 512-257-3370
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Tel: 49-7231-424750
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
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China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
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Tel: 774-760-0087
Fax: 774-760-0088
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Italy - Venice
Tel: 39-049-7625286
Chicago
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Netherlands - Drunen
Tel: 31-416-690399
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Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
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Tel: 852-2943-5100
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Tel: 216-447-0464
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Tel: 48-22-3325737
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Tel: 60-4-227-8870
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Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
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Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
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Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
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Tel: 63-2-634-9065
Fax: 63-2-634-9069
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Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Sweden - Stockholm
Tel: 46-8-5090-4654
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Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Novi, MI
Tel: 248-848-4000
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Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
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Tel: 886-3-5778-366
Fax: 886-3-5770-955
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Fax: 86-24-2334-2393
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Tel: 317-773-8323
Fax: 317-773-5453
Taiwan - Kaohsiung
Tel: 886-7-213-7830
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Los Angeles
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
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Fax: 86-29-8833-7256
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Tel: 631-435-6000
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Tel: 408-735-9110
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
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Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
10/28/13
DS20005155B-page 32
2012-2013 Microchip Technology Inc.
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