SY100E175 [MICREL]
9-BIT LATCH WITH PARITY; 带奇偶校验的9位锁存器型号: | SY100E175 |
厂家: | MICREL SEMICONDUCTOR |
描述: | 9-BIT LATCH WITH PARITY |
文件: | 总4页 (文件大小:63K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
9-BIT LATCH
WITH PARITY
SY10E175
SY100E175
FEATURES
DESCRIPTION
■ 9-bit latch
The SY10/100E175 are 9-bit latches. They also feature
a tenth latched output (ODDPAR) which is formed as the
odd parity of the nine data inputs (ODDPAR is HIGH if
an odd number of the inputs are HIGH).
The E175 can also be used to generate byte parity by
using D8 as the parity-type select (L = even parity, H =
odd parity) and using ODDPAR as the byte parity output.
The LEN pin latches the data when asserted with a
logical high and makes the latch transparent when placed
at a logic low level.
■ Extended 100E VEE range of –4.2V to –5.5V
■ Parity detection/generation
■ 800ps max. D to Output
■ Reset
■ Internal 75KΩ input pull-down resistors
■ Fully compatible with Motorola MC10E/100E175
■ Available in 28-pin PLCC package
PIN CONFIGURATION
BLOCK DIAGRAM
D0
D
Q
Q0
EN
R
25
24 23 22 21 20 19
D
5
Q
Q
6
5
26
27
28
1
18
17
16
15
14
13
12
D
D
4
3
bits
1 – 7
V
CC
TOP VIEW
PLCC
V
EE
Q
Q
4
3
J28-1
LEN
MR
2
D8
D
Q
Q8
V
CCO
3
EN
D
2
Q2
4
R
5
6
7
8
9
10 11
D
Q
ODDPAR
EN
R
PIN NAMES
LEN
MR
Pin
D0 – D8
LEN
Function
Data Inputs
Latch Enable
Master Reset
Data Outputs
Parity Output
VCC to Output
MR
Q0 – Q8
ODDPAR
VCCO
Rev.: C
Amendment:/1
Issue Date: February, 1998
1
SY10E175
Micrel
SY100E175
TRUTH TABLE
D
H
L
LEN
L
MR
L
Q
H
ODDPAR
H if odd no. of Dn HIGH
L
L
L
H if odd no. of Dn HIGH
X
X
H
L
Q0
L
Q0
L
X
H
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
IIH
Parameter
Input HIGH Current
Power Supply Current
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Condition
—
—
150
—
—
150
—
—
150
µA
—
—
IEE
mA
10E
100E
—
—
110
110
132
132
—
—
110
110
132
132
—
—
110
127
132
152
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Condition
tPLH
tPHL
Propagation Delay to Output
D to Q
ps
—
450
600
800
450
600
800
450
600
800
D to ODDPAR
850 1150 1450 850 1150 1450 850 1150 1450
LEN to Q
LEN to ODDPAR
MR to Q (tPHL)
525
525
525
525
700
700
700
700
900
900
900
900
525
525
525
525
700
700
700
700
900
900
900
900
525
525
525
525
700
700
700
700
900
900
900
900
MR to ODDPAR (tPHL)
tS
tH
Set-up Time
D (Q)
D (ODDPAR)
ps
ps
—
—
275
900
100
700
—
—
275
900
—
—
—
—
275
900
—
—
—
—
Hold Time
D (Q)
D (ODDPAR)
175 –100
–300 –700
—
—
175
–300
—
—
—
—
175
–300
—
—
—
—
tRR
Reset Recovery Time
850
600
—
850
600
—
850
600
—
ps
ps
—
tskew
Within-Device Skew
LEN, MR
D to Q
1
—
—
—
75
75
200
—
—
—
—
—
—
75
75
200
—
—
—
—
—
—
75
75
200
—
—
—
D to ODDPAR
tr
tf
Rise/Fall Times
20–80%
300
500
800
300
500
800
300
500
800
ps
—
NOTE:
1. Within-device skew is defined as identical transitions on similar paths
through a device.
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY10E175JC
J28-1
J28-1
J28-1
J28-1
Commercial
Commercial
Commercial
Commercial
SY10E175JCTR
SY100E175JC
SY100E175JCTR
2
SY10E175
Micrel
SY100E175
28 LEAD PLCC (J28-1)
Rev. 03
3
SY10E175
Micrel
SY100E175
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
4
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