SY100E175JC [MICREL]

9-BIT LATCH WITH PARITY; 带奇偶校验的9位锁存器


型号：	SY100E175JC
厂家：	MICREL SEMICONDUCTOR
描述：	9-BIT LATCH WITH PARITY 带奇偶校验的9位锁存器触发器锁存器逻辑集成电路
文件：	总4页 (文件大小：63K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

9-BIT LATCH

WITH PARITY

SY10E175

SY100E175

FEATURES

DESCRIPTION

■ 9-bit latch

The SY10/100E175 are 9-bit latches. They also feature

a tenth latched output (ODDPAR) which is formed as the

odd parity of the nine data inputs (ODDPAR is HIGH if

an odd number of the inputs are HIGH).

The E175 can also be used to generate byte parity by

using D8 as the parity-type select (L = even parity, H =

odd parity) and using ODDPAR as the byte parity output.

The LEN pin latches the data when asserted with a

logical high and makes the latch transparent when placed

at a logic low level.

■ Extended 100E VEE range of –4.2V to –5.5V

■ Parity detection/generation

■ 800ps max. D to Output

■ Reset

■ Internal 75KΩ input pull-down resistors

■ Fully compatible with Motorola MC10E/100E175

■ Available in 28-pin PLCC package

PIN CONFIGURATION

BLOCK DIAGRAM

24 23 22 21 20 19

bits

1 – 7

TOP VIEW

PLCC

J28-1

LEN

CCO

10 11

ODDPAR

PIN NAMES

LEN

D0 – D8

LEN

Function

Data Inputs

Latch Enable

Master Reset

Data Outputs

Parity Output

VCC to Output

Q0 – Q8

ODDPAR

VCCO

Rev.: C

Amendment:/1

Issue Date: February, 1998

SY10E175

Micrel

SY100E175

TRUTH TABLE

LEN

ODDPAR

H if odd no. of Dn HIGH

DC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

IIH

Parameter

Input HIGH Current

Power Supply Current

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Condition

—

150

—

150

—

150

µA

—

IEE

10E

100E

—

110

132

—

110

132

—

110

127

132

152

AC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Condition

tPLH

tPHL

Propagation Delay to Output

D to Q

—

450

600

800

450

600

800

450

600

800

D to ODDPAR

850 1150 1450 850 1150 1450 850 1150 1450

LEN to Q

LEN to ODDPAR

MR to Q (tPHL)

525

700

900

525

700

900

525

700

900

MR to ODDPAR (tPHL)

Set-up Time

D (Q)

D (ODDPAR)

—

275

900

100

700

—

275

900

—

275

900

—

Hold Time

D (Q)

D (ODDPAR)

175 –100

–300 –700

—

175

–300

—

175

–300

—

tRR

Reset Recovery Time

850

600

—

850

600

—

850

600

—

tskew

Within-Device Skew

LEN, MR

D to Q

—

200

—

200

—

200

—

D to ODDPAR

Rise/Fall Times

20–80%

300

500

800

300

500

800

300

500

800

—

NOTE:

1. Within-device skew is defined as identical transitions on similar paths

through a device.

PRODUCT ORDERING CODE

Ordering

Code

Package

Type

Operating

Range

SY10E175JC

J28-1

Commercial

SY10E175JCTR

SY100E175JC

SY100E175JCTR

SY10E175

Micrel

SY100E175

28 LEAD PLCC (J28-1)

Rev. 03

SY10E175

Micrel

SY100E175

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA

TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.