MIC50396 [MICREL]
Six Decade Counter / Display Decoder Not Recommended for New Designs; 六十进制计数器/显示译码器不推荐用于新设计
| 型号： | MIC50396 |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Six Decade Counter / Display Decoder Not Recommended for New Designs |
| 文件： | 总6页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MIC50395/50396/50397
Six Decade Counter / Display Decoder
Not Recommended for New Designs
General Description
Features
The MIC50395 is an ion-implanted, P-channel MOS six-
decade synchronous up/down-counter/display driver with
compare-register and storage-latches. The counter as well
as the register can be loaded digit-by-digit with BCD data.
The counter has an asynchronous-clear function.
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Single power supply
Schmitt-Trigger on the count-input
Drivescommonanodeorcathodedisplays(CAwithbuffer)
Six decades of synchronous up/down counting
Look-ahead carry or borrow
Loadable counter
Scanning is controlled by the scan oscillator input which is
self-oscillating or can be driven by an external signal. The
six-decade register is constantly compared to the state of
the six-decade counter and when both the register and the
counter have the same content, an EQUAL signal is gener-
ated. The contents of the counter can be transferred into the
6-digit latch which is then multiplexed from MSD to LSD in
BCD and 7-segment format to the output. The seven-
segment decoder incorporates a leading-zero blanking
circuit which can be disabled by an external signal. This
device is intended to interface directly with the standard
CMOS logic families.
Loadable compare-register with comparator output
Multiplexed BCD and seven-segment outputs
Internal scan oscillator
Direct LED segment drive
Interfaces directly with CMOS logic
Leading zero blanking
MIC50396 programmed to count time:
– 99 hrs. 59 min. 59 sec.
MIC50397 programmed to count time:
– 59 hrs. 59 min. 99/100 min.
•
Ordering Information
The MIC50396 and MIC50397 operate identically to the
MIC50395 except that two digits in each were reprogrammed
to provide divide by six circuitry instead of divide by ten. The
MIC50396 is well suited for industrial timer applications while
the MIC50397 is best suited for stop watch or real time
computer clock applications.
Part Number
MIC50395CN
MIC50396CN
MIC50397CN
Temp. Range
Package
0°C to 70°C
0°C to 70°C
0°C to 70°C
40-pin Plastic DIP
40-pin Plastic DIP
40-pin Plastic DIP
Pin Connection
V
1
2
40 UP/DOWN
39 ZERO
SS
SET
LZB
a
3
38 CARRY
4
37 COUNT INHIBIT
36 COUNT
b
5
R
R
R
R
c
6
35
34
33
32
A
B
C
D
SEGMENTS
d
7
REGISTER
BCD
e
8
IN
f
9
MIC50395CN
MIC50396CN
MIC50397CN
Segment Identification
g
10
11
12
13
14
31 LOAD COUNTER
30 LOAD REGISTER
a
A
D
D
D
D
D
D
B
29
28
27
26
25
24
MSD
6
5
4
3
2
1
BCD
OUT
f
b
c
g
d
C
D
DIGIT
e
STORE 15
STROBES
C
C
C
C
16
17
18
19
D
C
B
A
LSD
COUNTER
BCD
23 EQUAL
IN
V
22
DD
CLEAR 20
21 SCAN
8-4
August 1998
MIC50395/50396/50397
Operations:
Micrel
following a negative transition of Load Counter or Load
Register.
Six Decade Counter, Latch
The carry output goes high with the leading edge of the
count input at the count of 000000 when counting up or at
999999* when counting down and goes low with the negative
going edge of the same count input.
The six decade counter is synchronously incremented or
decremented on the positive edge of the count input signal.
A Schmitt trigger on this input provides hysteresis for protec-
tion against both a noisy environment and double triggering
due to a slow rising edge at the count input.
A count frequency of 1 MHz can be achieved if the equal
output, zero output and carry output are not used. These
outputs do not respond at this frequency due to their output
delay illustrated on the timing diagram.
The count inhibit can be changed in coincidence with
the positive transition of the count input; the count input is
inhibited when the count inhibit is high.
Six Decade Compare Register
The counter will increment when up/down input is high (VSS)
and will decrement when up/down input is low. The up/down
input can be changed 0.75 µs prior to the positive transition
of the count input.
The register is loaded identically to the load counter paragraph
described previously. The register may be loaded
independently of the counter, however, the clear input will
not remove the register contents. Contents of the register
are not displayed by the BCD or seven segment outputs.
The clear input is asynchronous and will reset all decades to
zero when brought high but does not affect the six digit latch
or the scan counter.
BCD Seven Segment Outputs
BCD or seven segment outputs are available. Digit strobes
are decoded internally by a divide by six Johnson counter.
This counter scans from MSD to LSD. By bringing the SET
input low, this counter will be forced to the MSD decade
count. During this time the segment outputs are blanked to
protect against display burn out.
As long as store input is low, data is continuously transferred
from the counter to the display. Data in the counter will be
latched and displayed when store input is high. Store can be
changed in coincidence with the positive transition of the
count input.
The counter is loaded digit by digit corresponding to the digit
strobe outputs. BCD thumb wheel switches with four diodes
per decade connected between the digit strobe outputs and
the BCD inputs is one method to supply BCD data for
loading the counter decades.
BCD outputs are valid for MSD when SET is low. Applying
VSS to SET allows normal scan to resume. Digit 6 output is
active (VSS) until the next scan clock pulse brings up digit 5
output.
The segment outputs and digit strobes are blanked during
the interdigit blanking time. Leading zero blanking affects
only the segment outputs. This option is disabled by bringing
the LZB input high. Typically the interdigit blanking time is 5
to 25 µs when using the internal scan oscillator.
The load counter pulse must be at VSS 2 µs prior to the
positive transition of the digit strobe of the digit to be loaded.
The load counter pulse may be removed after the positive
transition of the digit strobe since the chip internally latches
this signal. The BCD data to be loaded must be valid through
the negative transition of the digit strobe.
8
BCD output data changes at the beginning of the interdigit
blanking time. Therefore the BCD output data is valid when
the positive transition of a digit output occurs.
Inputs, Outputs
The seven segment outputs are open drain capable of
sourcing 10mA average current per segment over one digit
cycle. Segments are on when at VSS. The Carry, Equal,
Zero, BCD and digit strobe outputs are push pull and are on
when at VSS. All inputs except Counter BCD, Register BCD,
and SCAN inputs are high impedance CMOS compatible.
Scan Oscillator
The MIC50395 has an internal scan oscillator. The frequency
of the scan oscillator is determined by an external capacitor
between VSS or VDD and scan input. The wave form present
on the scan oscillator input is triangular in the self oscillate
mode.
Three basic outputs originate from the counter: zero output,
equal output, and carry output. Each output goes high on the
positive (VSS) going edge of the count input under the
following conditions:
An external oscillator may also be used to drive the scan
input. In either case, external capacitors of 150pF each will
be required from VSS to Counter BCD inputs and register
BCD inputs. This will allow asynchronous loading of the
BCD inputs.
Zero output goes high for one count period when all decades
contain zero. During a load counter operation the zero
output is inhibited.
In the internal drive mode the interdigit blanking time will be
the sum of the negative dwell period of the external oscillator
and the normal self oscillate blanking time. (5→25 µs). Dis-
play brightness can be controlled by the duty cycle of the
external scan oscillator.
Equal output goes high for one count period when the con-
tents of the counter and compare register are equal. The
equal output is inhibited by a load counter or load register
operation, which lasts until the next interdigit blanking period
*Carry occurs at 99:59:59 for the 50396 and 59:59:99 for the 50397
August 1998
8-5
MIC50395/50396/50397
Micrel
If external capacitors on the BCD inputs are undesirable, it
will be necessary to synchronize the negative going edge of
the load register and/or load counter command to coincide
with the positive going edge of the scan input signal. Also
the VSS range should be limited from 10.8 to 13.2 Volts.
CIN
Min
Max
820 pF
470 pF
120 pF
1.4 kHz
2.0 kHz
7.0 kHz
4.8 kHz
6.8 kHz
20 kHz
Typically, the scan oscillator will oscillate at the following
frequencies with these nominal capacitor values from VSS to
scan input.
Functional Diagram
SN75492A
*
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August 1998
MIC50395/50396/50397
Micrel
Absolute Maximum Ratings
Voltage on Any Terminal Relative to VSS
Operating Temperature Range (Ambient)
+0.3V to –20V
0°C to +70°C
Storage Temperature Range (Ambient) –40°C to +100°C
Maximum Operating Conditions
Symbol
Parameter
Min
Max
Units
Notes
TA
Operating Temperature
0
70
°C
VSS
ISS
BV
Supply voltage (VDD = 0V)
Supply Current
10
15
35
V
1
2
mA
Break Down Voltage
(Segment only @ 10 µA)
VSS – 26
V
PD
Power Dissipation
670
mW
3
Electrical Characteristics
(VDD = 0V, VSS = +10.0V to +15.0, 0°C ≤ TA ≤ 70°C)
Static Operating Conditions
Symbol
VIL
Parameter
Input Low Voltage, “0”
Min
VDD
Max
0.2 VSS
VSS
Units
Notes
V
V
V
V
VIH
Input High Voltage, “1”
VSS – 1
4
5
5
VOL
Output Voltage “0” @ 30 µA
Output Voltage “1” @ 1.5 mA
0.2 VSS
VOH
IOH
0.8 VSS
Output Current “1”
Digit strobes
3.0
10.0
mA
mA
6
7
8
Segment outputs
ISCAN
ISCAN
ISET
Scan Input Pullup Current @ 0 V
Scan Input Pulldown Current @ 15 V
SET Input Pullup Current @ 0V
5.5
40
60
mA
µA
µA
2
5
Note 1: With 150 pF capacitor to VSS from counter BCD and register BCD inputs.
Note 2: ISS with inputs and outputs open at 0°C. 33 mA at 25°C and 28 mA at 70°C. This does not include segment current.
Total power per segment must be limited not to exceed power dissipation of package. (θJA = 100°C/Watt)
Note 3: All outputs loaded.
Note 4: MIN VIH from RA RB RC RD CA CB CC CD inputs is VSS – 2.5 V. Those inputs have internal pulldown resistors to VDD
Note 5: This applied to the push pull CMOS compatible outputs. Does not include digit strobes or segment outputs.
Note 6: For VOUT = VSS – 2.0 Volts. Average value over one digit cycle.
.
Note 7: For VOUT = VSS – 3.0 Volts. Average value over one digit cycle.
August 1998
8-7
MIC50395/50396/50397
Micrel
Timing
1
2
3
4
5
6
7
8
9
10
11
COUNT
UP/DOWN
COUNT INHIBIT
STORE
tUDS
tUDS
tCIS
t CIS
tSS
tPCW
tSPW
CLEAR
tCS
COUNT
ZERO
t OA
t CA
tOH
t CH
CARRY
EQUAL
t EA
tEH
SCAN
LOAD COUNTER
LOAD REGISTER
t L
t L
Loading Counter, Register (1 Digit)
tLS
LOAD COUNTER
OR REGISTER
tDV
tLS 2.0 µs min NOTE: REF. TO POSITIVE
BCD DATA INPUT
TRANSITION OF DIGIT OUTPUT
tDV 2.0 µs min NOTE: REF. TO NEGATIVE
DIGIT OUTPUT 6
EDGE OF DIGIT OUTPUT
DIGIT OUTPUT 5 ETC
COUNT INPUT, CARRY
EQUAL, ZERO OUTPUT
INHIBITED DURING THIS
TIME
COUNT INPUT
tOA
tOH
ZERO OUTPUT
tCA
NOTE:
tCH
The inhibit function of the zero or equal outputs
does not end when the Load Counter input goes to
a “0” unless that transition occurs during interdigit
blanking period at least 2.0 µs prior to a positive
transition of a digit output. This same timing
restriction holds for Equal and Load Register.
CARRY OUTPUT
tEA
tEH
EQUAL OUTPUT
8-8
August 1998
MIC50395/50396/50397
Micrel
Dynamic Operating Conditions
Symbol
fCI
Parameter
Count Input Frequency
Scan Input Frequency
Count Pulse Width
Store Pulse Width
Store Setup Time
Count Inhibit Setup Time
Up/Down Setup Time
Clear Pulse Width
Clear Setup Time
Zero Access Time
Zero Hold Time
Min
0
Max
1.00
20
Units
MHz
kHz
ns
Notes
8,9
fSI
0
tCPW
tSPW
tSS
400
2.0
0
10
µs
µs
11
11
11
11
11
11
11
11
12
11
11
tCIS
tUDS
tCPW
tCS
0
µs
–0.75
2.0
–0.5
µs
µs
µs
tOA
3.0
1.5
1.5
µs
tOH
µs
tCA
Carry Access Time
Carry Hold Time
µs
tCH
0.9
2.0
µs
tEA
Equal Access Time
Equal Hold Time
µs
tEH
1.5
µs
tL
Load Time
1/6 fSI
Note 8: Measured at 50% duty cycle.
Note 9: If carry, equal, or zero outputs are used, the count frequency will be limited by their respective output times.
Note 10: The count pulse width must be greater than the carry access time when using the carry output.
Note 11: The positive edge of the count input is the t = 0 reference.
Note 12: Measured from negative edge of count input.
8
August 1998
8-9
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