DSC2043FI5-T [MICREL]
Low-Jitter Configurable HCSL-LVDS Oscillator;
| 型号： | DSC2043FI5-T |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Low-Jitter Configurable HCSL-LVDS Oscillator |
| 文件： | 总6页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSC2043
Low-Jitter Configurable HCSL-LVDS Oscillator
General Description
Features
The DSC2043 series of high performance
dual output oscillators utilize a proven silicon
MEMS technology to provide excellent jitter
and stability while incorporating additional
device functionality. The two outputs are
controlled by separate supply voltages to
allow for high output isolation. The
frequencies of the outputs can be identical or
independently derived from a common PLL
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o Industrial: -40° to 85° C
o Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Two Independent Outputs
o LVDS & HCSL
Pin-Selectable Configurations
frequency source.
The DSC2043 has
provision for up to eight user-defined pre-
programmed, pin selectable output frequency
combinations.
o 3-bit Output Frequency Combinations
Short Lead Times: 2 Weeks
DSC2043 is packaged in a 14-pin 3.2x2.5
Wide Freq. Range:
o HCSL output: 2.3 – 460 MHz
o LVDS output: 2.3 – 460 MHz
mm
QFN
package
and
available
in
temperature grades from Ext. Commercial to
Industrial.
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
High Reliability
o 20x better MTF than quartz oscillators
Block Diagram
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Applications
Storage Area Networks
o SATA, SAS, Fibre Channel
Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
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DSC2043 Page 1 MK-Q-B-P-D-12042613-2
Low-Jitter Configurable HCSL-LVDS Oscillator
DSC2043
Pin Description
Pin No.
Pin Name Pin Type
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
Leave unconnected or grounded
Ground
1
2
3
Enable
NC
I
NA
NC
NA
4
GND
Power
5
6
7
8
FS0
FS1
FS2
I
I
I
O
O
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
Positive HCSL Output 1
Negative HCSL Output 1
Negative LVDS Output 2
Positive LVDS Output 2
Power Supply 2 for LVDS Output 2
Power Supply
Output1+
Output1-
Output 2-
Output 2+
VDD2
VDD
9
10
11
12
13
14
O
O
Power
Power
NA
NC
Leave unconnected or grounded
Operational Description
The DSC2043 is a dual oscillator with an LVDS
output and an HCSL output. The device
consists of a MEMS resonator and a support
PLL IC. The two outputs are generated
through independent 8-bit programmable
dividers from the output of the internal PLL.
Two constraints are imposed on the output
frequencies: 1) f2=M x f1/N, where M and N
are even integers between 4 and 254, 2)
1.2GHz < N x f2 < 1.7GHz.
memory (OTP).
coefficients required by the PLL for up to eight
different frequency combinations. Three
control pins (FS0 – FS2) select the output
frequency combination. Discera supports
customer defined versions of the DSC2043.
Standard frequency options are described in in
the following sections.
This memory stores all
When Enable (pin 1) is floated or connected to
VDD, the DSC2043 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The actual frequencies output by the DSC2043
are controlled by an internal pre-programmed
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DSC2043 Page 2 MK-Q-B-P-D-12042613-2
Low-Jitter Configurable HCSL-LVDS Oscillator
DSC2043
Output Clock Frequencies
Table 1 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code. Customer defined combinations are available.
Table 1. Pre-programmed pin-selectable output frequency combinations
Freq Select Bits [FS2, FS1, FS0] – Default is [111]
Ordering
Info
Freq
(MHz)
000
001 010 011 100 101 110
111
fOUT1
fOUT2
fOUT1
fOUT2
N0001
NXXXXX
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and
the device will output the associated frequency highlighted in Bold.
Absolute Maximum Ratings
Ordering Code
Item
Min
Max
Unit Condition
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
Supply Voltage
-0.3
+4.0
V
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
-0.3 VDD+0.3
V
°C
°C
-
-55
-
+150
+150
+260
DSC2043
F
2
xxxxx
I
T
°C
V
40sec max.
Package
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Freq (MHz)
See Freq. table
ESD
HBM
MM
-
F: 3.2x2.5mm
4000
400
CDM
1500
Note: 1000+ years of data retention on internal memory
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DSC2043 Page 3 MK-Q-B-P-D-12042613-2
Low-Jitter Configurable HCSL-LVDS Oscillator
DSC2043
Specifications (Unless specified otherwise: T=25° C)
Parameter
Supply Voltage1
Condition
Min.
Typ.
Max.
3.6
Unit
V
VDD
IDD
2.25
Supply Current
Supply Current2
EN pin low – outputs are disabled
21
76
23
mA
EN pin high – outputs are enabled
RL=50Ω, FO1= FO2=156.25 MHz
IDD
mA
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
±10
±25
±50
±5
5
Frequency Stability
Aging
Startup Time3
Δf
ppm
Δf
tSU
1 year @25°C
T=25°C
ppm
ms
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
0.75xVDD
-
-
V
0.25xVDD
Output Disable Time4
Output Enable Time
Pull-Up Resistor2
tDA
5
ns
ns
tEN
20
Pull-up exists on all digital IO
40
kΩ
HCSL Outputs
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
0.725
-
-
0.1
V
Pk to Pk Output Swing
Output Transition time4
Rise Time
Single-Ended
750
mV
ps
20% to 80%
RL=50Ω, CL= 2pF
tR
tF
200
400
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
SYM
Period Jitter5
JPER
FO1=FO2=156.25 MHz
2.8
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.25
0.37
1.7
Integrated Phase Noise
JPH
psRMS
2
LVDS Outputs
Output Offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
R=100Ω Differential
1.125
1.4
50
V
mV
mV
Single-Ended
350
200
Output Transition time4
Rise Time
20% to 80%
RL=100Ω, CL= 2pF
tR
tF
350
ps
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
Period Jitter5
SYM
JPER
FO1=125 MHz
2.5
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.25
0.38
1.7
Integrated Phase Noise
JCC
psRMS
2
Notes:
1.
Pin 4 VDD should be filtered with 0.01uf capacitor.
2.
3.
4.
5.
Output is enabled if Enable pad is floated or not connected.
tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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DSC2043 Page 4 MK-Q-B-P-D-12042613-2
Low-Jitter Configurable HCSL-LVDS Oscillator
DSC2043
Nominal Performance Parameters (Unless specified otherwise: T=25° C, VDD=3.3 V)
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0.0
156MHz-LVDS
212MHz-LVDS
320MHz-LVDS
410MHz-LVDS
50MHz-HCSL
106MHz-HCSL
156MHz-HCSL
212MHz-HCSL
0
200
400
600
800
1000
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
Low-end of integration BW: x kHz to 20 MHz
HCSL Phase jitter (integrated phase noise)
LVDS Phase jitter (integrated phase noise)
Output Waveform: HCSL
tR
tF
Output
Output
80%
50%
20%
675 mV
tEN
1/fo
tDA
VIH
Enable
VIL
Output Waveform: LVDS
tR
tF
Output
80%
350 mV
50%
20%
Output
tEN
1/fo
tDA
VIH
Enable
VIL
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DSC2043 Page 5 MK-Q-B-P-D-12042613-2
Low-Jitter Configurable HCSL-LVDS Oscillator
DSC2043
Solder Reflow Profile
20-40
Sec
260°C
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max.
217°C
200°C
60-150
Sec
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
Time within 5°C of actual Peak
Ramp-Down Rate
60-180 Sec
60-150 Sec
255-260°C
20-40 Sec
6°C/Sec Max.
8 min Max.
Reflow
60-180
Sec
150°C
Cool
Pre heat
25°C
Time 25°C to Peak Temperature
Time
8 min max
Package Dimensions
3.2 x 2.5 mm 14 Lead Plastic Package
Disclaimer:
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information
is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and
descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted
by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims
any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the
body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or
sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any
damages resulting from such use or sale.
MICREL, Inc.
Phone: +1 (408) 944-0800
●
●
2180 Fortune Drive,
Fax: +1 (408) 474-1000
San Jose, California
95131
●
●
USA
●
Email: hbwhelp@micrel.com
www.micrel.com
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DSC2043 Page 6 MK-Q-B-P-D-12042613-2
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