DSC2042FI1-F0014T [MICREL]
Crystal-less⢠Configurable Clock Generator;
| 型号： | DSC2042FI1-F0014T |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Crystal-less⢠Configurable Clock Generator |
| 文件： | 总7页 (文件大小：787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSC2042FI1-F0014
Crystal-less™ Configurable Clock Generator
General Description
Features
The DSC2042FI1-F0014 is a programmable, high
performance dual output oscillator utilizing Micrel's
proven silicon MEMS technology to provide excellent
jitter and stability while incorporating additional
device functionality. The Two outputs are controlled
by separate supply voltages to allow for high output
isolation. The frequencies of the outrputs can be
identical or independently derived from a common
PLL frequency source.
• Frequency and output formats:
- HCSL
100MHz
- LVPECL
100MHz
• Low RMS phase jitter: <1ps (typ)
• ±50ppm frequency stability
• -40°C to +85°C industrial temperature range
• High supply noise rejection: -50dBc
• Pin-selectable configurations
- Up to 8 output frequency combinations
• Excellent shock & vibration immunity
- Qualified to MIL-STD-883
• High reliability
- 20x better MTF than quartz oscillators
• Supply range of 2.25 to 3.6V
• AEC-Q100 automotive qualified
• 14-pin 3.2mm x 2.5mm QFN package
The DSC2042FI1-F0014 has provision for up to eight
user-defined pre-programmed, pin-selectable output
frequency combinations.
Applications
• Consumer Electronics
• Storage Area Networks
- SATA, SAS, Fibre Channel
• Passive Optical Networks
- EPON, 10G-EPON, GPON, 10G-GPON
• Ethernet
- 1G, 10GBASE-T/KR/LR/SR, and FCoE
• HD/SD/SDI Video & Surveillance
• PCI Express
• Automotive
VDD/VDD2
Block Diagram
CLK1+
100MHz HCSL
CLK1-
Control Circuitry
÷ 2
÷ M1
MEMS
PLL
CLK2+
÷ 2
÷ M2
100MHz LVPECL
CLK2-
FS0/FS1/FS2
OE
VSS
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 07, 2016
3771
Revision 1.0
tcghelp@micrel.comor (408) 955-1690
Micrel, Inc.
DSC2042FI1-F0014
Ordering Information
Ordering Part Number
DSC2042FI1-F0014
DSC2042FI1-F0014T
Industrial Temperature Range
-40°C to +85°C
Shipping
Tube
Package
14-pin 3.2mm x 2.5mm QFN
14-pin 3.2mm x 2.5mm QFN
-40°C to +85°C
Tape and Reel
Devices are Green and RoHS compliant. Sample material may have only a partial top mark.
Pin Configuration
OE
CLK2+
CLK2-
CLK1-
CLK1+
NC
NC
GND
14-pin 3.2mm x 2.5mm QFN
Pin Description
Pin Number
Pin Name
OE
Pin Type
Pin Function
Enables outputs when high and disables outputs when low
Leave unconnected or connect to ground
Leave unconnected or connect to ground
Ground
1
2
I
NC
3
NC
4
GND
FS0
PWR
5
I
Least significant bit for frequency selection, see Table 1 for details
Middle bit for frequency selection, see Table 1 for details
Most significant bit for frequency selection, see Table 1 for details
Positive HCSL output
6
FS1
I
I
7
FS2
8
CLK1+
CLK1-
CLK2-
CLK2+
VDD2
VDD
NC
O
9
O
Negative HCSL output
10
11
12
13
14
O
Negative LVPECL output
O
Positive LVPECL output
PWR
PWR
Power supply for LVPECL output CLK2, 1.65V to 3.6V (VDD2 ≤ VDD)
Power supply
Leave unconnected or connect to ground
April 07, 2016
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Micrel, Inc.
DSC2042FI1-F0014
Operational Description
The DSC2042FI1-F0014 is a dual oscillator with an
HCSL output and an LVPECL output. The device
consists of a MEMS resonator and a supporting PLL
IC. Two outputs are generated through independent
8-bit programmable dividers from the output of the
internal PLL.
When OE (pin 1) is floated or connected to VDD, the
DSC2042FI1-F0014 is in operational mode. Driving
OE to ground will tri-state both output drivers (hi-
impedance mode).
Two constraints are imposed on the output frequencies:
1) f2 = M x f1/N, where M and N are even integers
between 4 and 254, 2) 1.2GHz < N x f2 < 1.7GHz.
The actual frequencies output by DSC2042FI1-F0014
are controlled by an internal pre-programmed memory
(OTP). This memory stores all coefficients required by
the PLL for up to eight different frequency
combinations. Three control pins (FS0 - FS2) select
the output frequency combination.
Output Clock Frequencies
Frequency select bits are weakly tied high so if left unconnected the default setting will be [111] and the device will output the
associated frequency highlighted in bold.
Freq Select Bits [FS2, FS1, FS0] - Default is [111]
Freq (MHz)
000
NA
NA
001
NA
NA
010
NA
NA
011
NA
NA
100
NA
NA
101
NA
NA
110
NA
NA
111
100
100
CLK1
CLK2
Table 1. Pin-Selectable Output Frequencies
Absolute Maximum Ratings
Item
Min.
-0.3
-0.3
-
Max.
+4.0
Units
V
Condition
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
VDD + 0.3
+150
V
°C
°C
°C
-55
-
+150
+260
40sec max.
ESD
HBM
MM
4000
400
-
V
CDM
1500
1000+ years of data retention on internal memory
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Micrel, Inc.
DSC2042FI1-F0014
Specifications (Unless specified otherwise: T = 25°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Units
Supply Voltage¹
Supply Current
VDD
IDD
2.25
3.6
23
V
OE pin low - output is disabled
21
76
mA
OE pin high - outputs are enabled
RL = 50Ohms, F01 = F02 = 156.25MHz
Supply Current²
IDD
F
mA
Includes frequency variation due to initial
tolerance, temp. and power supply voltage
Frequency Stability
±50
ppm
Aging
F
First year (@ 25°C)
T = 25°C
±5
5
ppm
ms
Startup Time³
tSU
Input Logic Levels
Input Logic High
Input Logic Low
VIH
VIL
0.75 x VDD
-
-
V
0.25 x VDD
4
Output Disable Time
Output Enable Time
Pull-Up Resistor²
tDA
tEN
5
ns
ns
20
Pull-up exists on all digital IO
40
kOhms
HCSL Output
Output Logic Levels
Output Logic High
Output Logic Low
VOH
VOL
RL = 50Ohms
Single-Ended
0.725
-
-
0.1
V
mV
ps
Pk to Pk Output Swing
750
4
Output Transition Time
Rise Time
tR
tF
20% to 80%
RL = 50Ohms, CL = 2pF
200
48
400
52
Fall Time
Frequency
CLK1
[FS2, FS1, FS0] = [1, 1, 1]
100
2.8
MHz
Output Duty Cycle
Period Jitter5
SYM
JPER
Differential
%
F01 = F02 = 156.25MHz
psRMS
200kHz to 20MHz @ 156.25MHz
100kHz to 20MHz @ 156.25MHz
12kHz to 20MHz @ 156.25MHz
0.25
0.37
1.7
Integrated Phase Noise
JPH
2
psRMS
LVPECL Output
Output Logic Levels
Output Logic High
Output Logic Low
VOH
VOL
VDD - 1.08
-
-
RL = 50Ohms
Single-Ended
VDD - 1.55
V
Pk to Pk Output Swing
800
mV
4
Output Transition Time
Rise Time
tR
tF
20% to 80%
RL = 50Ohms
Fall Time
250
100
ps
MHz
%
Frequency
CLK2
SYM
JPER
[FS2, FS1, FS0] = [1, 1, 1]
Differential
Output Duty Cycle
Period Jitter5
48
52
2
F01 = F02 = 156.25MHz
2.5
psRMS
200kHz to 20MHz @ 156.25MHz
100kHz to 20MHz @ 156.25MHz
12kHz to 20MHz @ 156.25MHz
0.25
0.38
1.7
Integrated Phase Noise
JPH
psRMS
1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.
2. Output is enabled if OE pin is floated or not connected.
3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures below define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
April 07, 2016
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Micrel, Inc.
DSC2042FI1-F0014
Nominal Performance Parameters (Unless specified otherwise: T = 25°C, VDD = 3.3V)
Figure 1. HCSL Phase Jitter (integrated phase noise)
Low-end of integration BW: x kHz to 20 MHz
Figure 2. LVPECL Phase Jitter (integrated phase noise)
April 07, 2016
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Micrel, Inc.
DSC2042FI1-F0014
HCSL Output Waveform
675
OE
Figure 3. HCSL Output Waveform
LVPECL Output Waveform
830
OE
Figure 4. LVPECL Output Waveform
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
3°C/sec Max.
60 - 180 sec
60 - 150 sec
255 - 260°C
20 - 40 sec
Time within 5°C of actual Peak
Ramp-Down Rate
6°C/sec Max.
8 min Max.
Time 25°C to Peak Temperature
April 07, 2016
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tcghelp@micrel.comor (408) 955-1690
Micrel, Inc.
DSC2042FI1-F0014
Solder Reflow Profile
Figure 5. Solder Reflow Profile
Package Information7
3.2mm x 2.5mm 14 Lead Plastic Package
Notes:
6. Connect the exposed die paddle to ground.
7. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data
sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right
to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel's terms and
conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty
relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction
of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a)
are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected
to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices
or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2016 Micrel, Incorporated.
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